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OSADL Articles:
2023-11-12 12:00
Open Source License Obligations Checklists even better now
Import the checklists to other tools, create context diffs and merged lists
2022-07-11 12:00
Call for participation in phase #4 of Open Source OPC UA open62541 support project
Letter of Intent fulfills wish list from recent survey
2022-01-13 12:00
Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed
Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached
2021-02-09 12:00
Open Source OPC UA PubSub over TSN project phase #3 launched
Letter of Intent with call for participation is now available |
COOL - Compact OSADL Online Lectures - November 2024 edition
OSADL talks at ESE Embedded Software Engineering Kongress
COOL - Compact OSADL Online Lectures - December 2024 edition
OSADL QA Farm on Real-time of Mainline Linux
About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards
Effect of sleep state setting on latency and power consumption
Wakeup latency of all systems - Real-time optimization - Peer-to-peer UDP duplex link - OPC UA PubSub over TSN - Powerlink - Ethercat - Network load - kvm - Sleep states
For testing purposes, particular sleep states were disabled on one of the 12-way systems (6 cores with hyperthreading). Core #2 was not allowed to enter any sleep state, and core #3 was not allowed to enter a sleep state deeper than 1. Core #1 was left unmodified, i.e. any sleep state can be entered according to the system load. In addition, the scaling governor of CPU #2 was set to performance from 5.05 a.m. to 5.05 p.m. and left at ondemand (same as the other cores) in the remaining time period. For details, please refer to the related profile section.
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- Please note that the recorded latency values represent maxima of 5-min intervals. Thus, the data in the columns labeled "Min:" and "Avg:" should not be considered; the only relevant result is the maximum of consecutive 5-min maxima at the rightmost column labeled "Max:".
The data clearly demonstrate that the sleep state setting has no effect on the latency and on the power consumption while the 200-µs cyclic activity of the cyclictest program is creating continuous system load. Under idle conditions, however, only the core that is not allowed to enter a sleep state deeper than 1 continues to deliver the same real-time capabilities. The other cores suffer from up to 10 times higher latencies. On the other hand, allowing cores to enter a deep sleep state has a clear beneficial effect on the power consumption. Note that the power consumption reflects the entire system and not only the processor.
