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2024-09-27 - 09:26

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00027.09. 01:10
r0s0sx86_​644 x 23,40054,39227.09. 01:10
r0s1x86_​644 x 22,30056,00027.09. 01:11
r0s1sx86_​644 x 23,30052,67227.09. 01:11
r0s2x86_​644 x 23,50055,86427.09. 01:11
r0s2sx86_​6410 x 13,70073,99027.09. 01:12
r0s3x86_​648 x 23,600115,20027.09. 01:12
r0s3sx86_​644 x 23,60067,20026.08. 01:14
r0s4x86_​648 x 23,600115,20027.09. 01:14
r0s4sx86_​648 x 23,600115,20027.09. 01:15
r0s5x86_​648 x 23,500115,20027.09. 01:16
r0s5sx86_​648 x 23,600115,20027.09. 01:16
r0s6x86_​648 x 23,600115,20027.09. 01:19
r0s6sx86_​6410 x 23,700147,98027.09. 01:20
r0s7x86_​648 x 23,600115,20027.09. 01:21
r0s7sx86_​642 x 23,70029,53226.08. 13:20
r0s8x86_​648 x 23,600115,20027.09. 01:22
r0s8sx86_​646 x 23,47083,37627.09. 01:22
r1s0x86_​644 x 13,10024,80027.09. 01:23
r1s1x86_​642 x 22,60021,69627.09. 01:24
r1s2x86_​644 x 12,30028,00027.09. 01:24
r1s2sx86_​644 x 12,30028,00027.09. 01:25
r1s3x86_​644 x 12,80022,42427.09. 01:26
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004827.09. 01:26
r1s4sarm​v7l2 x 14004827.09. 01:27
r1s5aarch​644 x 11,20079627.09. 01:27
r1s6x86_​642 x 22,13017,06427.09. 01:28
r1s6sx86_​642 x 21,66713,33227.09. 01:28
r1s7arm​v6l1 x 11,66753027.09. 01:29
r1s8i6861 x 21,6006,39827.09. 01:29
r1s8sx86_​644 x 11,90015,19627.09. 01:30
r2s0x86_​644 x 13,10024,80027.09. 01:30
r2s1arm​v5tejl1 x 120019927.09. 01:31
r2s2arm​v7l1 x 172049927.09. 01:32
r2s3arm​v7l0 x 1 x 162462427.09. 01:32
r2s3sarm​v7l0 x 1 x 16001,20027.09. 01:33
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966627.09. 01:33
r2s6i6861 x 11,5002,99927.09. 01:34
r2s6saarch​644 x 11,3506427.09. 01:34
r2s7aarch​644 x 12,40043227.09. 01:35
r2s7saarch​644 x 11,50043227.09. 01:36
r2s8ppc1 x 14006627.09. 01:36
r3s0i6864 x 23,50055,99227.09. 01:37
r3s1i6864 x 12,40019,12727.09. 01:38
r3s2riscv641 x 11,00028427.09. 01:39
r3s2sriscv644 x 1028427.09. 01:40
r3s3x86_​646 x 23,33379,99227.09. 01:41
r3s4aarch​646 x 11,3009627.09. 01:42
r3s5i5861 x 113326527.09. 01:42
r3s5sppc2 x 11,20040027.09. 01:44
r3s6x86_​641 x 21,6606,66627.09. 01:45
r3s6sx86_​642 x 22,66721,33227.09. 01:45
r3s7i6861 x 15331,06627.09. 01:46
r3s8i6866 x 13,20038,52627.09. 01:47
r4s0x86_​642 x 22,30018,39627.09. 01:47
r4s1arm​v7l4 x 11,50086427.09. 01:48
r4s1sarm​v7l4 x 11,50086427.09. 01:48
r4s2arm​v7l1 x 180079627.09. 01:49
r4s2sarm​v7l1 x 180053027.09. 01:51
r4s3i5861 x 150099627.09. 01:52
r4s3si6861 x 11,4662,93228.07. 02:17
r4s4ppc4 x 11,20049827.09. 01:53
r4s5arm​v7l1 x 1500027.09. 01:57
r4s5saarch​644 x 11,60020027.09. 01:57
r4s6x86_​644 x 23,40054,25627.09. 01:57
r4s6sarm​v7l0 x 1 x 11,0006627.09. 01:58
r4s7i6864 x 11,83314,66427.09. 01:59
r4s7sx86_​642 x 11,8337,33227.09. 02:00
r4s8arm​v7l1 x 140039827.09. 02:01
r4s8sarm​v7l1 x 140039827.09. 02:01
r5s0x86_​642 x 22,20017,58227.09. 02:02
r5s1x86_​646 x 13,33340,09227.09. 02:02
r5s2x86_​644 x 12,70021,69927.09. 02:03
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87227.09. 02:04
r5s3sx86_​644 x 11,60012,74827.09. 02:04
r5s4x86_​642 x 22,53020,26427.09. 02:05
r5s4sx86_​642 x 22,53020,26427.09. 02:06
r5s5arm​v7l1 x 160059727.09. 02:07
r5s5sarm​v7l1 x 160060027.09. 02:09
r5s6ppc1 x 153313327.09. 02:12
r5s7arm​v7l1 x 15286427.09. 02:13
r5s7sarm​v7l1 x 15284827.09. 02:14
r5s8x86_​644 x 12,00015,97227.09. 02:16
r6s0x86_​642 x 10 x 21,700136,18027.09. 02:16
r6s1x86_​642 x 12,0007,97827.09. 02:17
r6s2x86_​642 x 11,6679,57827.09. 02:17
r6s3x86_​644 x 22,20035,12027.09. 02:17
r6s4x86_​642 x 11,1004,37627.09. 02:18
r6s5i6861 x 11,5002,99227.09. 02:19
r6s6i6861 x 11,6003,19227.09. 02:20
r6s7i6862 x 12,3009,17627.09. 02:21
r6s8x86_​642 x 22,30018,35627.09. 02:21
r7s0x86_​642 x 22,30018,40027.09. 02:22
r7s1x86_​644 x 11,60012,84027.09. 02:22
r7s2aarch​642 x 11,7009627.09. 02:22
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700527.09. 02:23
r7s3sarm​v7l4 x 11,40035627.09. 02:26
r7s4arm​v7l1 x 153634827.09. 02:27
r7s4sarm​v7l4 x 11,5001,08027.09. 02:27
r7s5i6861 x 11,3002,59327.09. 02:28
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76727.09. 02:29
r7s7sx86_​642 x 22,30018,39627.09. 02:29
r7s8arm​v7l1 x 11,00099527.09. 02:30
r7s8sarm​v7l1 x 11,00099627.09. 02:31
r8s0x86_​642 x 22,30018,40027.09. 02:32
r8s1i5861 x 135070127.09. 02:32
r8s2x86_​642 x 22,10016,76027.09. 02:33
r8s2sx86_​642 x 22,10016,76027.09. 02:34
r8s3x86_​644 x 12,66721,28027.09. 02:34
r8s4x86_​644 x 21,60028,80027.09. 02:35
r8s4sx86_​644 x 21,60028,80027.09. 02:36
r8s5i6864 x 23,40054,40027.09. 02:36
r8s6arm​v7l1 x 150049827.09. 02:37
r8s6sx86_​644 x 13,30026,41627.09. 02:37
r8s7x86_​644 x 13,20025,49627.09. 02:37
r8s7sx86_​642 x 13,00011,98027.09. 02:38
r8s8x86_​642 x 11,3005,14427.09. 02:38
r9s0x86_​642 x 22,30018,39627.09. 02:39
r9s1x86_​642 x 12,0003,99227.09. 02:40
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74827.09. 02:40
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74827.09. 02:41
r9s3sx86_​644 x 13,00024,00027.09. 02:41
r9s4i6861 x 21,0003,99027.09. 02:42
r9s4sx86_​642 x 11,3335,34727.09. 02:47
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,30013,19827.09. 02:48
r9s6x86_​642 x 23,00023,94427.09. 02:48
r9s7arm​v7l2 x 11,000027.09. 02:49
r9s8sarm​v7l1 x 180079627.09. 02:50
ras0x86_​642 x 22,30018,41727.09. 02:51
ras1i6861 x 11,4002,79927.09. 02:51
ras2x86_​642 x 11,0674,26627.09. 02:51
ras2sx86_​644 x 11,90015,05227.09. 02:52
ras3aarch​648 x 12,0004,00027.09. 02:52
ras3sarm​v7l1 x 11,30084027.09. 02:52
ras4arm​v7l1 x 150039827.09. 02:53
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002427.09. 02:53
ras5sarm​v7l2 x 11,0002427.09. 02:54
ras6aarch​648 x 12,0003,20027.09. 02:54
ras6sarm​v7l1 x 11,0001,98727.09. 02:55
ras7ppc1 x 13966527.09. 02:56
ras8x86_​644 x 11,60014,40027.09. 02:57
ras8sx86_​644 x 11,60012,74827.09. 02:57
rbs0i6862 x 22,50017,60027.09. 02:57
rbs1x86_​644 x 12,00015,97227.09. 02:58
rbs2x86_​644 x 12,00015,97227.09. 02:58
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962427.09. 02:59
rbs3sarm​v7l4 x 11,40035627.09. 03:00
rbs4x86_​644 x 11,2009,60027.09. 03:01
rbs4sx86_​644 x 11,60012,74827.09. 03:01
rbs5i6864 x 2049,53927.09. 03:02
rbs5saarch​644 x 11,6006427.09. 03:02
rbs6x86_​644 x 11,91515,32427.09. 03:02
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rbs7arm​v7l4 x 19961227.09. 03:03
rbs7sarm​v7l4 x 19962427.09. 03:04
rbs8arm​v7l2 x 16662,65027.09. 03:05
rbs8sx86_​644 x 22,40038,70427.09. 03:06
rcs0x86_​648 x 22,40076,60027.09. 03:07
rcs1x86_​646 x 23,46783,37627.09. 03:08
rcs2x86_​642 x 12,80011,23227.09. 03:08
rcs3i6862 x 11,4005,58627.09. 03:09
rcs3sx86_​644 x 13,30026,39627.09. 03:10
rcs4x86_​642 x 11,1004,37627.09. 03:11
rcs4sx86_​644 x 11,1008,75216.09. 03:07
rcs5x86_​642 x 12,80011,19827.09. 03:12
rcs5sx86_​642 x 12,80011,19827.09. 03:14
rcs6x86_​644 x 23,50063,99227.09. 03:14
rcs7x86_​642 x 21,80014,40027.09. 03:15
rcs7sx86_​644 x 11,50011,98027.09. 03:16
rcs8x86_​6416 x 23,700217,15227.09. 03:20
rcs8sx86_​644 x 23,30052,80027.09. 03:21
rds0x86_​644 x 21,80031,99227.09. 03:21
rds1x86_​644 x 11,91015,32427.09. 03:22
rds2x86_​644 x 11,91015,32423.09. 03:21
rds3x86_​644 x 11,91015,32423.09. 03:22
rds4x86_​644 x 11,91015,32427.09. 03:22
rds5x86_​644 x 11,60012,74827.09. 03:23
rds6x86_​644 x 11,60012,74827.09. 03:24
rds7x86_​644 x 11,60012,74827.09. 03:24
rds8x86_​644 x 11,60012,74827.09. 03:25
res0x86_​644 x 23,40054,39227.09. 03:25
res1x86_​644 x 11,60014,40027.09. 03:26
res1sx86_​644 x 11,60014,40027.09. 03:26
res2x86_​644 x 11,60014,40027.09. 03:27
res3x86_​644 x 12,00015,97227.09. 03:27
res3saarch​640 x 1 x 11,0001,60027.09. 03:27
res4x86_​644 x 11,90015,05227.09. 03:28
res4sx86_​644 x 11,90015,05227.09. 03:29
res5x86_​642 x 22,20019,20027.09. 03:29
res5sx86_​642 x 22,20019,20027.09. 03:30
res6x86_​644 x 11,1008,75227.09. 03:30
res6saarch​644 x 101,60027.09. 03:31
res7arm​v7l0 x 1 x 11,0001227.09. 03:32
res7sarm​v7l0 x 1 x 11,0001227.09. 03:33
res8x86_​644 x 11,90015,05227.09. 03:33
res8sx86_​644 x 11,90015,05227.09. 03:34
rfs0x86_​6416 x 22,000127,96827.09. 03:35
rfs1aarch​644 x 11,50043227.09. 03:35
rfs2aarch​644 x 11,50043227.09. 03:35
rfs3x86_​644 x 11,60012,74827.09. 03:36
rfs3sx86_​644 x 11,60012,74827.09. 03:36
rfs4arm​v7l1 x 180080027.09. 03:37
rfs4sarm​v7l1 x 180080027.09. 03:38
rfs6arm​v7l1 x 16671,33227.09. 03:39
rfs6sarm​v7l1 x 16671,33227.09. 03:39
rfs7x86_​644 x 22,60041,60027.09. 03:40
rfs7sx86_​644 x 17006,44827.09. 03:41
rfs8arm​v7l1 x 11,00012023.09. 03:41
 

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