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2024-07-16 - 06:48

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00016.07. 01:10
r0s1x86_​644 x 22,30055,99216.07. 01:12
r0s1sx86_​644 x 23,30052,67216.07. 01:14
r0s2x86_​644 x 23,50055,86416.07. 01:16
r0s2sx86_​6410 x 13,70073,99016.07. 01:19
r0s3x86_​648 x 23,600115,20016.07. 01:22
r0s3sx86_​644 x 23,60067,20016.07. 01:28
r0s4x86_​648 x 23,600115,20016.07. 01:31
r0s4sx86_​648 x 23,600115,20016.07. 01:34
r0s5x86_​648 x 23,500115,20016.07. 01:36
r0s5sx86_​648 x 23,600115,20016.07. 01:39
r0s6x86_​648 x 23,600115,20016.07. 01:41
r0s6sx86_​6410 x 23,700147,98016.07. 01:45
r0s7x86_​648 x 23,600115,20016.07. 01:50
r0s7sx86_​642 x 23,70029,52816.07. 01:57
r0s8x86_​648 x 23,600115,20016.07. 01:59
r0s8sx86_​646 x 23,47083,38816.07. 02:03
r1s0x86_​644 x 13,10024,80016.07. 02:06
r1s1x86_​642 x 22,60021,69616.07. 02:08
r1s2x86_​644 x 12,30028,00016.07. 02:10
r1s2sx86_​644 x 12,30028,00016.07. 02:13
r1s3x86_​644 x 12,80022,42416.07. 02:15
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004816.07. 02:17
r1s4sarm​v7l2 x 14004816.07. 02:19
r1s5aarch​644 x 11,20079616.07. 02:20
r1s6x86_​642 x 22,13017,06416.07. 02:22
r1s6sx86_​642 x 21,66713,33216.07. 02:24
r1s7arm​v6l1 x 11,66753016.07. 02:26
r1s8i6861 x 21,6006,39816.07. 02:27
r1s8sx86_​644 x 11,90015,19616.07. 02:30
r2s0x86_​644 x 13,10024,80016.07. 02:31
r2s1arm​v5tejl1 x 120019916.07. 02:33
r2s2arm​v7l1 x 172049916.07. 02:35
r2s3arm​v7l0 x 1 x 162462416.07. 02:35
r2s3sarm​v7l0 x 1 x 16001,20016.07. 02:37
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966612.07. 14:26
r2s6i6861 x 11,5002,99916.07. 02:40
r2s6saarch​644 x 11,3506416.07. 02:42
r2s7aarch​644 x 12,40043216.07. 02:44
r2s7saarch​644 x 11,50043216.07. 02:47
r2s8ppc1 x 14006616.07. 02:50
r3s0i6864 x 23,50055,99216.07. 02:52
r3s1i6864 x 12,40019,12716.07. 02:55
r3s2riscv641 x 11,00028416.07. 02:57
r3s2sriscv644 x 1028416.07. 02:59
r3s3x86_​646 x 23,33379,99216.07. 03:00
r3s4aarch​646 x 11,3009616.07. 03:03
r3s5i5861 x 113326514.07. 15:11
r3s5sppc2 x 11,20040030.06. 02:58
r3s6x86_​641 x 11,6603,33316.07. 03:13
r3s6sx86_​642 x 22,66721,33216.07. 03:16
r3s7i6861 x 15331,06616.07. 03:18
r3s8i6866 x 13,20038,52616.07. 03:20
r4s0x86_​642 x 22,30018,39616.07. 03:21
r4s1arm​v7l4 x 11,50086416.07. 03:24
r4s1sarm​v7l4 x 11,5001,08016.07. 03:27
r4s2arm​v7l1 x 180079616.07. 03:32
r4s2sarm​v7l1 x 180053016.07. 03:35
r4s3i5861 x 150099616.07. 03:41
r4s3si6861 x 11,4662,93216.07. 03:44
r4s4ppc4 x 11,20049816.07. 03:46
r4s5arm​v7l1 x 1500016.07. 03:51
r4s5saarch​644 x 11,60020016.07. 03:52
r4s6x86_​644 x 23,40054,25616.07. 03:54
r4s6sarm​v7l0 x 1 x 11,0006616.07. 04:02
r4s7i6864 x 11,83314,66416.07. 04:05
r4s7sx86_​642 x 11,8337,33216.07. 04:06
r4s8arm​v7l1 x 140039816.07. 04:10
r4s8sarm​v7l1 x 140039816.07. 04:11
r5s0x86_​642 x 22,20017,58215.07. 15:47
r5s1x86_​646 x 13,33340,09215.07. 15:50
r5s2x86_​644 x 12,70021,69915.07. 15:51
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87215.07. 15:55
r5s3sx86_​644 x 11,60012,74815.07. 15:57
r5s4x86_​642 x 22,53020,26415.07. 16:01
r5s4sx86_​642 x 22,53020,26415.07. 16:03
r5s5arm​v7l1 x 160059715.07. 16:09
r5s5sarm​v7l1 x 160060015.07. 16:13
r5s6ppc1 x 153313315.07. 16:21
r5s7arm​v7l1 x 15286415.07. 16:22
r5s7sarm​v7l1 x 15286415.07. 16:25
r6s0x86_​642 x 10 x 21,700136,18015.07. 16:27
r6s1x86_​642 x 12,0007,97815.07. 16:30
r6s2x86_​642 x 11,6679,57815.07. 05:01
r6s3x86_​644 x 22,20035,12015.07. 16:32
r6s4x86_​642 x 11,1004,37615.07. 16:35
r6s5i6861 x 11,5002,99215.07. 16:37
r6s6i6861 x 11,6003,19115.07. 16:40
r6s7i6862 x 12,3009,17615.07. 16:42
r6s8x86_​642 x 22,30018,35615.07. 16:45
r7s0x86_​642 x 22,30018,40015.07. 16:46
r7s1x86_​644 x 11,60012,84015.07. 16:49
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700515.07. 16:51
r7s3sarm​v7l4 x 11,40035615.07. 16:55
r7s4arm​v7l1 x 153634815.07. 17:00
r7s4sarm​v7l4 x 11,5001,08015.07. 17:03
r7s5i6861 x 11,3002,59315.07. 17:05
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76715.07. 17:06
r7s7sx86_​642 x 22,30018,39615.07. 05:44
r7s8arm​v7l1 x 11,00099515.07. 17:08
r7s8sarm​v7l1 x 11,00059715.07. 17:11
r8s0x86_​642 x 22,30018,40015.07. 17:12
r8s1i5861 x 135070115.07. 17:15
r8s2x86_​642 x 22,10016,76015.07. 17:19
r8s2sx86_​642 x 22,10016,76015.07. 17:22
r8s3x86_​644 x 12,66721,28015.07. 17:25
r8s4x86_​644 x 21,60028,80015.07. 17:26
r8s4sx86_​644 x 21,60028,80015.07. 17:28
r8s5i6864 x 23,40054,40015.07. 17:30
r8s6arm​v7l1 x 150049815.07. 17:32
r8s6sx86_​644 x 13,30026,41615.07. 17:33
r8s7x86_​644 x 13,20025,49615.07. 17:35
r8s7sx86_​642 x 13,00011,98015.07. 17:37
r8s8x86_​642 x 11,3005,14415.07. 17:38
r9s0x86_​642 x 22,30018,39615.07. 17:40
r9s1x86_​642 x 12,0003,99215.07. 17:43
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74815.07. 17:45
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74815.07. 17:46
r9s3sx86_​644 x 13,00024,00015.07. 17:47
r9s4i6861 x 21,0003,99015.07. 17:50
r9s4sx86_​642 x 11,3335,34715.07. 17:56
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,30013,19815.07. 17:58
r9s6x86_​642 x 23,00023,94415.07. 18:00
r9s7arm​v7l2 x 11,000015.07. 18:03
r9s8sarm​v7l1 x 180079615.07. 18:04
ras0x86_​642 x 22,30018,41615.07. 18:06
ras1i6861 x 11,4002,79915.07. 18:07
ras2x86_​642 x 11,0674,26615.07. 18:09
ras3aarch​648 x 12,0004,00015.07. 18:11
ras3sarm​v7l1 x 11,30084015.07. 18:12
ras4arm​v7l1 x 150039815.07. 18:13
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002415.07. 18:14
ras5sarm​v7l2 x 11,0002415.07. 18:15
ras6aarch​648 x 12,0003,20020.05. 17:01
ras6sarm​v7l1 x 11,0001,98715.07. 18:17
ras7ppc1 x 13966515.07. 18:18
ras8x86_​644 x 11,60014,40015.07. 18:19
ras8sx86_​644 x 11,60012,74815.07. 18:21
rbs0i6862 x 22,50017,60015.07. 18:23
rbs1x86_​644 x 12,00015,97230.06. 06:25
rbs2x86_​644 x 12,00015,97230.06. 06:26
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962815.07. 18:26
rbs3sarm​v7l4 x 11,40035615.07. 18:27
rbs4x86_​644 x 11,2009,60015.07. 18:32
rbs4sx86_​644 x 11,60012,74815.07. 18:33
rbs5i6864 x 2049,53915.07. 18:35
rbs5saarch​644 x 11,6006415.07. 18:37
rbs6x86_​644 x 11,91515,32415.07. 18:38
rbs6sx86_​642 x 11,3335,33215.07. 18:41
rbs7arm​v7l4 x 19962815.07. 18:44
rbs7sarm​v7l4 x 19962415.07. 18:47
rbs8arm​v7l2 x 16662,65015.07. 18:51
rbs8sx86_​644 x 22,40038,70414.07. 19:36
rcs0x86_​648 x 22,40076,60015.07. 18:55
rcs1x86_​646 x 23,46783,37615.07. 18:58
rcs2x86_​642 x 12,80011,23215.07. 19:01
rcs3i6862 x 11,4005,58815.07. 19:04
rcs3sx86_​644 x 23,30052,69615.07. 19:06
rcs4x86_​642 x 11,1004,37615.07. 19:11
rcs4sx86_​644 x 11,1008,75215.07. 19:14
rcs5x86_​642 x 12,80011,19815.07. 19:17
rcs5sx86_​642 x 12,80011,19815.07. 19:21
rcs6x86_​644 x 23,50063,99215.07. 19:24
rcs7x86_​642 x 21,80014,39615.07. 19:27
rcs7sx86_​644 x 11,50011,98015.07. 19:30
rcs8x86_​6416 x 23,700217,15215.07. 19:38
rcs8sx86_​644 x 23,30052,79215.07. 19:41
rds0x86_​644 x 21,80031,99215.07. 19:44
rds1x86_​644 x 11,91015,32415.07. 19:46
rds2x86_​644 x 11,91015,32415.07. 19:48
rds3x86_​644 x 11,91015,32415.07. 19:51
rds4x86_​644 x 11,91015,32415.07. 19:54
rds5x86_​644 x 11,60012,74815.07. 19:56
rds6x86_​644 x 11,60012,74815.07. 19:58
rds7x86_​644 x 11,60012,74815.07. 20:01
rds8x86_​644 x 11,60012,74815.07. 20:03
res0x86_​644 x 21,80031,99215.07. 20:05
res1x86_​644 x 11,60014,40015.07. 20:08
res1sx86_​644 x 11,60014,40015.07. 20:10
res2x86_​644 x 11,60014,40015.07. 20:12
res3x86_​644 x 12,00015,97215.07. 20:13
res3saarch​640 x 1 x 11,0001,60015.07. 20:16
res4x86_​644 x 11,90015,05215.07. 20:18
res4sx86_​644 x 11,90015,05215.07. 20:21
res5x86_​642 x 22,20019,20015.07. 20:23
res5sx86_​642 x 22,20019,20015.07. 20:25
res6x86_​644 x 11,1008,75215.07. 20:28
res6saarch​644 x 101,60015.07. 20:31
res7arm​v7l0 x 1 x 11,0001215.07. 20:34
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
res8x86_​644 x 11,90015,05215.07. 20:37
res8sx86_​644 x 11,90015,05215.07. 20:40
rfs0x86_​6416 x 22,000127,96815.07. 20:42
rfs1aarch​644 x 11,50043215.07. 20:44
rfs2aarch​644 x 11,50043215.07. 20:45
rfs3x86_​644 x 11,60012,74815.07. 20:46
rfs3sx86_​644 x 11,60012,74815.07. 20:47
rfs4arm​v7l1 x 180080015.07. 20:49
rfs4sarm​v7l1 x 180080015.07. 21:02
rfs6arm​v7l1 x 16671,33215.07. 21:16
rfs6sarm​v7l1 x 16671,33215.07. 10:01
 

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