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2025-04-05 - 05:36

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00005.04. 01:10
r0s0sx86_​644 x 23,40054,39205.04. 01:10
r0s1x86_​644 x 22,30056,00005.04. 01:11
r0s1sx86_​644 x 23,30052,79205.04. 01:11
r0s2x86_​644 x 23,50055,86405.04. 01:11
r0s2sx86_​6410 x 13,70073,99005.04. 01:12
r0s3x86_​648 x 23,600115,20005.04. 01:13
r0s3sx86_​644 x 23,60067,20005.04. 01:15
r0s4x86_​648 x 23,600115,20005.04. 01:15
r0s4sx86_​648 x 23,600115,20005.04. 01:16
r0s5x86_​648 x 23,500115,20001.04. 13:16
r0s5sx86_​648 x 23,600115,20005.04. 01:17
r0s6x86_​648 x 23,600115,20028.02. 13:18
r0s6sx86_​6410 x 23,700147,98005.04. 01:17
r0s7x86_​648 x 23,600115,20005.04. 01:18
r0s7sx86_​642 x 23,70029,53205.04. 01:19
r0s8x86_​648 x 23,600115,20005.04. 01:20
r0s8sx86_​646 x 23,47083,37605.04. 01:21
r1s0x86_​644 x 13,10024,80005.04. 01:21
r1s1x86_​642 x 22,60021,69605.04. 01:22
r1s2x86_​644 x 12,30028,00005.04. 01:22
r1s2sx86_​644 x 12,30028,00005.04. 01:23
r1s3x86_​644 x 12,80022,42405.04. 01:23
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004805.04. 01:24
r1s4sarm​v7l2 x 14004805.04. 01:25
r1s5aarch​644 x 11,20079605.04. 01:25
r1s6x86_​642 x 22,13017,06405.04. 01:26
r1s6sx86_​642 x 21,66713,33205.04. 01:26
r1s7arm​v6l1 x 11,66753005.04. 01:27
r1s8i6861 x 21,6006,39805.04. 01:27
r1s8sx86_​644 x 11,90015,19605.04. 01:28
r2s0x86_​644 x 13,10024,80005.04. 01:28
r2s1arm​v5tejl1 x 120019905.04. 01:30
r2s2arm​v7l1 x 172049905.04. 01:33
r2s3arm​v7l0 x 1 x 162462405.04. 01:33
r2s3sarm​v7l0 x 2 x 16001,20005.04. 01:34
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966605.04. 01:35
r2s5sarm​v7l4 x 11,20015205.04. 01:35
r2s6i6861 x 11,5002,99905.04. 01:36
r2s6saarch​644 x 11,3506405.04. 01:37
r2s7aarch​644 x 12,40043205.04. 01:37
r2s7saarch​644 x 11,50043205.04. 01:38
r2s8ppc1 x 14006605.04. 01:39
r3s0i6864 x 23,50055,99205.04. 01:40
r3s1i6864 x 12,40019,12705.04. 01:40
r3s2riscv641 x 11,00028405.04. 01:41
r3s2sriscv644 x 1028405.04. 01:42
r3s3x86_​646 x 23,33379,99205.04. 01:42
r3s3sx86_​644 x 13,40011,98005.04. 01:43
r3s4aarch​646 x 11,3009605.04. 01:44
r3s5i5861 x 113326505.04. 01:45
r3s5sppc2 x 11,20040002.04. 13:44
r3s6x86_​641 x 21,6606,66605.04. 01:47
r3s6sx86_​642 x 22,66721,33205.04. 01:47
r3s7i6861 x 15331,06617.03. 13:50
r3s8i6864 x 13,20027,36405.04. 01:48
r4s0x86_​642 x 22,30018,40005.04. 01:49
r4s1arm​v7l4 x 11,50072005.04. 01:49
r4s1sarm​v7l4 x 11,50093605.04. 01:50
r4s2arm​v7l1 x 180079605.04. 01:51
r4s2sarm​v7l1 x 180053005.04. 01:52
r4s3i5861 x 150099605.04. 01:54
r4s3si6861 x 11,4662,93228.07. 02:17
r4s4ppc4 x 11,20049805.04. 01:55
r4s5arm​v7l1 x 1500005.04. 01:58
r4s5saarch​644 x 11,60020005.04. 01:58
r4s6x86_​644 x 23,40054,25605.04. 01:59
r4s6sarm​v7l0 x 1 x 11,0006605.04. 02:00
r4s7i6864 x 11,83314,66405.04. 02:01
r4s7sx86_​642 x 11,8337,33205.04. 02:02
r4s8arm​v7l1 x 140039805.04. 02:02
r4s8sarm​v7l1 x 140039805.04. 02:03
r5s0x86_​642 x 22,20017,58205.04. 02:03
r5s1x86_​648 x 13,33353,45605.04. 02:04
r5s2x86_​644 x 12,70021,69905.04. 02:04
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87205.04. 02:05
r5s3sx86_​644 x 11,60012,74805.04. 02:06
r5s4x86_​642 x 22,53020,26405.04. 02:07
r5s4sx86_​642 x 22,53020,26405.04. 02:07
r5s5arm​v7l1 x 160059705.04. 02:09
r5s5sarm​v7l1 x 160060005.04. 02:11
r5s6ppc1 x 153313305.04. 02:14
r5s7arm​v7l1 x 15286405.04. 02:14
r5s7sarm​v7l1 x 15284805.04. 02:16
r5s8x86_​644 x 12,00015,97205.04. 02:17
r6s0x86_​642 x 10 x 21,700136,18005.04. 02:18
r6s1x86_​642 x 12,0007,97805.04. 02:19
r6s2x86_​642 x 11,6679,57805.04. 02:20
r6s3x86_​644 x 22,20035,12005.04. 02:20
r6s4x86_​642 x 11,1004,37605.04. 02:21
r6s5i6861 x 11,5002,99205.04. 02:21
r6s6i6861 x 11,6003,19205.04. 02:22
r6s7i6862 x 12,3009,17605.04. 02:23
r6s8x86_​642 x 22,30018,35605.04. 02:24
r7s0x86_​642 x 22,30018,40005.04. 02:24
r7s1x86_​644 x 11,60012,84005.04. 02:25
r7s2aarch​642 x 11,7009605.04. 02:25
r7s2sriscv644 x 1028430.03. 14:27
r7s3arm​v6l1 x 1700505.04. 02:26
r7s3sarm​v7l4 x 11,40035605.04. 02:28
r7s4arm​v7l1 x 153634805.04. 02:29
r7s4sarm​v7l4 x 11,5001,08005.04. 02:30
r7s5i6861 x 11,3002,59305.04. 02:31
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76705.04. 02:31
r7s7sx86_​642 x 22,30018,39605.04. 02:32
r7s8arm​v7l1 x 11,00099505.04. 02:33
r7s8sarm​v7l1 x 11,00079605.04. 02:34
r8s0x86_​642 x 22,30018,40005.04. 02:34
r8s1i5861 x 135070105.04. 02:35
r8s2x86_​642 x 22,10016,76005.04. 02:37
r8s2sx86_​642 x 22,10016,76005.04. 02:37
r8s3x86_​644 x 12,66721,28005.04. 02:38
r8s4x86_​644 x 21,60028,80005.04. 02:39
r8s4sx86_​644 x 21,60028,80005.04. 02:39
r8s5i6864 x 23,40054,40005.04. 02:40
r8s6arm​v7l1 x 150049805.04. 02:41
r8s6sx86_​644 x 13,30026,41605.04. 02:41
r8s7x86_​644 x 13,20025,49605.04. 02:42
r8s7sx86_​642 x 13,00011,98005.04. 02:42
r8s8x86_​642 x 11,3005,14405.04. 02:43
r9s0x86_​642 x 22,30018,39605.04. 02:43
r9s1x86_​642 x 12,0003,99205.04. 02:44
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74805.04. 02:45
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74805.04. 02:46
r9s3sx86_​644 x 13,00024,00005.04. 02:46
r9s4i6861 x 21,0003,99005.04. 02:47
r9s4sx86_​642 x 11,3335,34705.04. 02:52
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,30013,19805.04. 02:53
r9s6x86_​642 x 23,00023,94405.04. 02:54
r9s7arm​v7l2 x 11,000005.04. 02:55
r9s8sarm​v7l1 x 180079605.04. 02:55
ras0x86_​642 x 22,30018,41805.04. 02:56
ras1i6861 x 11,4002,79905.04. 02:57
ras2x86_​642 x 11,0674,26605.04. 02:57
ras2sx86_​644 x 11,90015,05205.04. 02:57
ras3aarch​648 x 12,0004,00005.04. 02:58
ras3sarm​v7l1 x 11,30084005.04. 02:58
ras4arm​v7l1 x 150039805.04. 02:59
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002405.04. 02:59
ras5sarm​v7l2 x 11,0002405.04. 03:00
ras6aarch​648 x 12,0003,20005.04. 03:00
ras6sarm​v7l1 x 11,0001,98705.04. 03:01
ras7ppc1 x 13966505.04. 03:02
ras8x86_​644 x 11,60014,40005.04. 03:03
ras8sx86_​644 x 11,60012,74805.04. 03:03
rbs0i6862 x 22,50017,60005.04. 03:04
rbs1x86_​644 x 12,00015,97205.04. 03:05
rbs2x86_​644 x 12,00015,97205.04. 03:05
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962405.04. 03:06
rbs3sarm​v7l4 x 11,40035605.04. 03:06
rbs4x86_​644 x 11,2009,60005.04. 03:07
rbs4sx86_​644 x 11,60012,74805.04. 03:08
rbs5i6864 x 2049,55105.04. 03:09
rbs5saarch​644 x 11,6006405.04. 03:10
rbs6x86_​644 x 11,91515,32405.04. 03:11
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rbs7arm​v7l4 x 19961205.04. 03:12
rbs7sarm​v7l4 x 19962405.04. 03:13
rbs8arm​v7l2 x 16662,65005.04. 03:14
rbs8sx86_​644 x 22,40038,70405.04. 03:14
rcs0x86_​648 x 22,40076,60005.04. 03:16
rcs1x86_​646 x 23,46783,37605.04. 03:16
rcs2x86_​642 x 12,80011,23205.04. 03:17
rcs3i6862 x 11,4005,58605.04. 03:18
rcs3sx86_​644 x 13,30026,39605.04. 03:18
rcs4x86_​642 x 11,1004,37605.04. 03:19
rcs5x86_​642 x 12,80011,19805.04. 03:21
rcs5sx86_​642 x 12,80011,19805.04. 03:22
rcs6x86_​644 x 23,50063,99205.04. 03:23
rcs7x86_​642 x 21,80014,40005.04. 03:24
rcs7sx86_​644 x 11,50011,98005.04. 03:25
rcs8x86_​6416 x 23,700217,15205.04. 03:28
rcs8sx86_​644 x 23,30052,80005.04. 03:29
rds0x86_​644 x 21,80031,99205.04. 03:30
rds1x86_​644 x 11,60012,74805.04. 03:31
rds2x86_​644 x 11,60012,74805.04. 03:31
rds3x86_​644 x 11,60012,74805.04. 03:32
rds4x86_​644 x 11,60012,74805.04. 03:32
rds5x86_​644 x 11,60012,74805.04. 03:33
rds6x86_​644 x 11,60012,74805.04. 03:34
rds7x86_​644 x 11,60012,74805.04. 03:34
rds8x86_​644 x 11,60012,74805.04. 03:35
res0x86_​644 x 23,40054,39205.04. 03:35
res1x86_​644 x 11,60014,40005.04. 03:37
res1sx86_​644 x 11,60014,40005.04. 03:37
res2x86_​644 x 11,60014,40005.04. 03:37
res3x86_​644 x 12,00015,97205.04. 03:38
res3saarch​640 x 1 x 11,0001,60005.04. 03:39
res4x86_​644 x 11,90015,05205.04. 03:39
res4sx86_​644 x 11,90015,05205.04. 03:40
res5x86_​642 x 22,20019,20005.04. 03:41
res5sx86_​642 x 22,20019,20005.04. 03:41
res6x86_​644 x 11,1008,75205.04. 03:42
res6saarch​644 x 101,60005.04. 03:43
res7arm​v7l0 x 1 x 11,0001205.04. 03:44
res7sarm​v7l0 x 1 x 11,0001205.04. 03:44
res8x86_​644 x 11,90015,05205.04. 03:45
res8sx86_​644 x 11,90015,05205.04. 03:46
rfs0x86_​6416 x 22,000127,96805.04. 03:47
rfs1aarch​644 x 11,50043205.04. 03:47
rfs1saarch​644 x 11,50043205.04. 03:48
rfs2x86_​644 x 14,10023,99605.04. 03:48
rfs3x86_​644 x 11,60012,74805.04. 03:48
rfs3sx86_​644 x 11,60012,74805.04. 03:49
rfs4arm​v7l1 x 180080005.04. 03:50
rfs4sarm​v7l1 x 180080005.04. 03:51
rfs6arm​v7l1 x 16671,33205.04. 03:52
rfs6sarm​v7l1 x 16671,33205.04. 03:53
rfs7x86_​644 x 22,60041,60005.04. 03:53
rfs7sx86_​644 x 17006,44805.04. 03:54
rfs8arm​v7l1 x 11,00012004.03. 03:47
 

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