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2025-04-04 - 03:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Apr 04, 2025 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2851899220,18cyclictest0-21swapper/023:22:140
2852799215,2cyclictest4528-21H212:26:332
28527992118,2cyclictest4536-21H212:26:332
2852299211,17cyclictest0-21swapper/120:50:071
28527992016,3cyclictest0-21swapper/223:52:122
28527992010,0cyclictest0-21swapper/223:40:172
2852799200,5cyclictest0-21swapper/222:35:022
2852299202,9cyclictest1887-21python323:35:011
28522992017,2cyclictest4593-21H212:26:331
28522992013,3cyclictest0-21swapper/120:15:391
2852799193,1cyclictest0-21swapper/220:04:582
2852799193,15cyclictest0-21swapper/223:22:412
28527991917,1cyclictest28-21ksoftirqd/219:54:302
28527991910,5cyclictest0-21swapper/200:30:192
2852799190,16cyclictest4538-21H212:26:332
2852799190,16cyclictest4530-21H212:26:332
28522991916,2cyclictest4536-21H212:26:331
28522991915,3cyclictest0-21swapper/123:02:371
2852299190,2cyclictest4536-21H212:26:331
2852299190,18cyclictest823-21systemd-network19:20:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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