Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/bootp/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/boot/bootp/Makefile 2014-07-20 22:05:50.289065747 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/bootp/Makefile 2014-07-20 22:06:33.833347334 +0200 @@ -5,6 +5,8 @@ # architecture-specific flags and dependencies. # +GCOV_PROFILE := n + LDFLAGS_bootp :=-p --no-undefined -X \ --defsym initrd_phys=$(INITRD_PHYS) \ --defsym params_phys=$(PARAMS_PHYS) -T Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/compressed/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/boot/compressed/Makefile 2014-07-20 22:05:50.288065763 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/compressed/Makefile 2014-07-20 22:06:33.848347087 +0200 @@ -37,6 +37,8 @@ OBJS += hyp-stub.o endif +GCOV_PROFILE := n + # # Architecture dependencies # Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/boot/dts/Makefile 2014-07-20 22:05:50.284065829 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/Makefile 2014-07-20 22:06:33.863346840 +0200 @@ -264,6 +264,15 @@ wm8750-apc8750.dtb \ wm8850-w70v2.dtb dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ + zynq-zc702-base-trd.dtb \ + zynq-zc702-drm-v4l2.dtb \ + zynq-afx-nand.dtb \ + zynq-afx-nor.dtb \ + zynq-cc108.dtb \ + zynq-zc770-xm010.dtb \ + zynq-zc770-xm011.dtb \ + zynq-zc770-xm012.dtb \ + zynq-zc770-xm013.dtb \ zynq-zc706.dtb \ zynq-zed.dtb Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-afx-nand.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-afx-nand.dts 2014-07-20 22:06:33.874346658 +0200 @@ -0,0 +1,291 @@ +/* + * Device Tree Generator version: 1.1 + * + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.5 EDK_P.58f + * + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + aliases { + serial0 = &ps7_uart_1; + } ; + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0001000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + reg-names = "cpu0", "cpu1"; + } ; + ps7_ddr_0: memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clock-names = "apb_pclk"; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_gpio_0: ps7-gpio@e000a000 { + #gpio-cells = <2>; + clocks = <&clkc 42>; + compatible = "xlnx,ps7-gpio-1.00.a"; + emio-gpio-width = <64>; + gpio-controller ; + gpio-mask-high = <0x3cffff>; + gpio-mask-low = <0xff008002>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_ocmc_0: ps7-ocmc@f800c000 { + compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr"; + reg = <0xf8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clkc: clkc { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + } ; + } ; + } ; + ps7_smcc_0: ps7-smcc@e000e000 { + #address-cells = <1>; + #size-cells = <1>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 11>, <&clkc 44>; + compatible = "xlnx,ps7-smcc-1.00.a", "xlnx,ps7-smc"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 18 4>; + ranges ; + reg = <0xe000e000 0x1000>; + xlnx,addr25 = <0x0>; + xlnx,nor-chip-sel0 = <0x0>; + xlnx,nor-chip-sel1 = <0x0>; + xlnx,sram-chip-sel0 = <0x0>; + xlnx,sram-chip-sel1 = <0x0>; + ps7_nand_0: ps7-nand@e1000000 { + compatible = "xlnx,ps7-nand-1.00.a"; + reg = <0xe1000000 0x1000000>; + xlnx,nand-cycle-t0 = <0x4>; + xlnx,nand-cycle-t1 = <0x4>; + xlnx,nand-cycle-t2 = <0x1>; + xlnx,nand-cycle-t3 = <0x2>; + xlnx,nand-cycle-t4 = <0x2>; + xlnx,nand-cycle-t5 = <0x2>; + xlnx,nand-cycle-t6 = <0x4>; + xlnx,nand-width = <0x10>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + partition@nand-fsbl-uboot { + label = "nand-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@nand-linux { + label = "nand-linux"; + reg = <0x100000 0x500000>; + }; + partition@nand-device-tree { + label = "nand-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@nand-rootfs { + label = "nand-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@nand-bitstream { + label = "nand-bitstream"; + reg = <0xC00000 0x400000>; + + }; + } ; + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_ttc_1: ps7-ttc@f8002000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 37 4>, <0 38 4>, <0 39 4>; + reg = <0xf8002000 0x1000>; + } ; + ps7_uart_1: serial@e0001000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 24>, <&clkc 41>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 50 4>; + port-number = <0>; + reg = <0xe0001000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_wdt_0: ps7-wdt@f8005000 { + clocks = <&clkc 45>; + compatible = "xlnx,ps7-wdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + reset = <0>; + timeout = <10>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-afx-nor.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-afx-nor.dts 2014-07-20 22:06:33.882346526 +0200 @@ -0,0 +1,269 @@ +/* + * Device Tree Generator version: 1.1 + * + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.5 EDK_P.58f + * + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + aliases { + serial0 = &ps7_uart_1; + } ; + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0001000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + reg-names = "cpu0", "cpu1"; + } ; + ps7_ddr_0: memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clock-names = "apb_pclk"; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_ocmc_0: ps7-ocmc@f800c000 { + compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr"; + reg = <0xf8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clkc: clkc { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + } ; + } ; + } ; + ps7_smcc_0: ps7-smcc@e000e000 { + #address-cells = <1>; + #size-cells = <1>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 11>, <&clkc 44>; + compatible = "xlnx,ps7-smcc-1.00.a", "xlnx,ps7-smc"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 18 4>; + ranges ; + reg = <0xe000e000 0x1000>; + xlnx,addr25 = <0x1>; + xlnx,nor-chip-sel0 = <0x1>; + xlnx,nor-chip-sel1 = <0x0>; + xlnx,sram-chip-sel0 = <0x0>; + xlnx,sram-chip-sel1 = <0x0>; + ps7_nor_0: ps7-nor@e2000000 { + bank-width = <1>; + compatible = "xlnx,ps7-nor-1.00.a", "cfi-flash"; + reg = <0xe2000000 0x1000>; + xlnx,sram-cycle-t0 = <0xb>; + xlnx,sram-cycle-t1 = <0xb>; + xlnx,sram-cycle-t2 = <0x5>; + xlnx,sram-cycle-t3 = <0x4>; + xlnx,sram-cycle-t4 = <0x3>; + xlnx,sram-cycle-t5 = <0x3>; + xlnx,sram-cycle-t6 = <0x2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@nor-fsbl-uboot { + label = "nor-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@nor-linux { + label = "nor-linux"; + reg = <0x100000 0x500000>; + }; + partition@nor-device-tree { + label = "nor-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@nor-rootfs { + label = "nor-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@nor-bitstream { + label = "nor-bitstream"; + reg = <0xC00000 0x400000>; + }; + + } ; + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_ttc_1: ps7-ttc@f8002000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 37 4>, <0 38 4>, <0 39 4>; + reg = <0xf8002000 0x1000>; + } ; + ps7_uart_1: serial@e0001000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 24>, <&clkc 41>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 50 4>; + port-number = <0>; + reg = <0xe0001000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-cc108.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-cc108.dts 2014-07-20 22:06:33.891346378 +0200 @@ -0,0 +1,363 @@ +/* + * Device Tree Generator version: 1.1 + * + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.7 EDK_P.20131013 + * + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + aliases { + ethernet0 = &ps7_ethernet_0; + serial0 = &ps7_uart_1; + spi0 = &ps7_qspi_0; + } ; + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0001000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + reg-names = "cpu0", "cpu1"; + } ; + ps7_ddr_0: memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clock-names = "apb_pclk"; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_ethernet_0: ps7-ethernet@e000b000 { + #address-cells = <1>; + #size-cells = <0>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 13>, <&clkc 30>; + compatible = "xlnx,ps7-ethernet-1.00.a"; + enet-reset = <&ps7_gpio_0 0 0>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 22 4>; + local-mac-address = [00 0a 35 00 00 00]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + reg = <0xe000b000 0x1000>; + xlnx,eth-mode = <0x1>; + xlnx,has-mdio = <0x1>; + xlnx,ptp-enet-clock = <111111115>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@1 { + compatible = "marvell,88e1510"; + device_type = "ethernet-phy"; + reg = <1>; + } ; + } ; + } ; + ps7_gpio_0: ps7-gpio@e000a000 { + #gpio-cells = <2>; + clocks = <&clkc 42>; + compatible = "xlnx,ps7-gpio-1.00.a"; + emio-gpio-width = <64>; + gpio-controller ; + gpio-mask-high = <0x0>; + gpio-mask-low = <0x0>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_ocmc_0: ps7-ocmc@f800c000 { + compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_qspi_0: ps7-qspi@e000d000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 19 4>; + is-dual = <0>; + num-chip-select = <1>; + reg = <0xe000d000 0x1000>; + xlnx,fb-clk = <0x0>; + xlnx,qspi-mode = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { /* 16 MB */ + compatible = "n25q128"; + reg = <0x0>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot-bs"; + reg = <0x0 0x400000>; /* 4MB */ + }; + partition@0x400000 { + label = "qspi-linux"; + reg = <0x400000 0x400000>; /* 4MB */ + }; + partition@0x800000 { + label = "qspi-rootfs"; + reg = <0x800000 0x400000>; /* 4MB */ + }; + partition@0xc00000 { + label = "qspi-devicetree"; + reg = <0xc00000 0x100000>; /* 1MB */ + }; + partition@0xd00000 { + label = "qspi-scratch"; + reg = <0xd00000 0x200000>; /* 2MB */ + }; + partition@0xf00000 { + label = "qspi-uboot-env"; + reg = <0xf00000 0x100000>; /* 1MB */ + }; + }; + } ; + ps7_qspi_linear_0: ps7-qspi-linear@fc000000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-linear-1.00.a"; + reg = <0xfc000000 0x1000000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_sd_1: ps7-sdio@e0101000 { + broken-cd ; + wp-inverted ; + clock-frequency = <50000000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 22>, <&clkc 33>; + compatible = "xlnx,ps7-sdio-1.00.a", "generic-sdhci", "arasan,sdhci-8.9a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 47 4>; + reg = <0xe0101000 0x1000>; + xlnx,has-cd = <0x0>; + xlnx,has-power = <0x0>; + xlnx,has-wp = <0x0>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr"; + reg = <0xf8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clkc: clkc { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + } ; + } ; + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_ttc_1: ps7-ttc@f8002000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 37 4>, <0 38 4>, <0 39 4>; + reg = <0xf8002000 0x1000>; + } ; + ps7_uart_0: serial@e0000000 { + status = "disabled"; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 23>, <&clkc 40>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 27 4>; + port-number = <0>; + reg = <0xe0000000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_uart_1: serial@e0001000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 24>, <&clkc 41>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 50 4>; + port-number = <0>; + reg = <0xe0001000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_usb_0: ps7-usb@e0002000 { + clocks = <&clkc 28>; + compatible = "xlnx,ps7-usb-1.00.a"; + dr_mode = "peripheral"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 21 4>; + phy_type = "ulpi"; + reg = <0xe0002000 0x1000>; + usb-reset = <&ps7_gpio_0 9 0>; + } ; + ps7_usb_1: ps7-usb@e0003000 { + clocks = <&clkc 29>; + compatible = "xlnx,ps7-usb-1.00.a"; + dr_mode = "host"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 44 4>; + phy_type = "ulpi"; + reg = <0xe0003000 0x1000>; + } ; + ps7_wdt_0: ps7-wdt@f8005000 { + clocks = <&clkc 45>; + compatible = "xlnx,ps7-wdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + reset = <0>; + timeout = <10>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc702-base-trd.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc702-base-trd.dts 2014-07-20 22:06:33.901346213 +0200 @@ -0,0 +1,652 @@ +/dts-v1/; + +/ { + model = "Xilinx Zynq ZC702"; + compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + #address-cells = <0x1>; + #size-cells = <0x1>; + interrupt-parent = <0x1>; + aliases { + spi1 = &qspi0; + }; + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + chosen { + bootargs = "console=tty0 console=ttyPS0,115200 root=/dev/ram rw ip=192.168.1.10:::255.255.255.0:ZC702:eth0 earlyprintk mem=768M"; + linux,stdout-path = "/amba@0/uart@E0001000"; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 5 4>, <0 6 4>; + interrupt-parent = <&gic>; + }; + + amba@0 { + compatible = "simple-bus"; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + + gic: intc@f8f01000 { + interrupt-controller; + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + reg = <0xf8f01000 0x1000>, + <0xf8f00100 0x0100>; + }; + + pl310@f8f02000 { + compatible = "arm,pl310-cache"; + cache-unified; + cache-level = <2>; + reg = <0xf8f02000 0x1000>; + interrupts = <0 2 4>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + }; + + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + + ps7_ocm_0: ps7-ocm@0xfffc0000 { + compatible = "xlnx,ps7-ocm"; + reg = <0xfffc0000 0x40000>; /* 256k */ + }; + + uart@e0001000 { + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + clocks = <&clkc 24>, <&clkc 41>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xe0001000 0x1000>; + interrupts = <0 50 4>; + interrupt-parent = <&gic>; + }; + + slcr: slcr@f8000000 { + compatible = "xlnx,zynq-slcr"; + reg = <0xF8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + + clkc: clkc { + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + ps-clk-frequency = <33333333>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", + "dma", "usb0_aper", "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", "sdio1_aper", + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", + "gpio_aper", "lqspi_aper", "smc_aper", "swdt", + "dbg_trc", "dbg_apb"; + }; + } ; + }; + + timer@0xf8001000 { + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xf8001000 0x1000>; + interrupts = <0 10 4>,<0 11 4>,<0 12 4>; + interrupt-parent = <&gic>; + }; + + timer@f8f00600 { + compatible = "arm,cortex-a9-twd-timer"; + clocks = <&clkc 4>; + reg = <0xf8f00600 0x20>; + interrupts = <1 13 0x301>; + interrupt-parent = <&gic>; + }; + + swdt@f8005000 { + device_type = "watchdog"; + compatible = "xlnx,ps7-wdt-1.00.a"; + clocks = <&clkc 45>; + reg = <0xf8005000 0x100>; + interrupts = <0 9 4>; + interrupt-parent = <&gic>; + reset = <0>; + timeout = <10>; + }; + + scuwdt@f8f00620 { + device_type = "watchdog"; + compatible = "arm,mpcore_wdt"; + clocks = <&clkc 4>; + reg = <0xf8f00620 0x20>; + clock-frequency = <333333333>; + reset = <1>; + }; + + eth@e000b000 { + compatible = "xlnx,ps7-ethernet-1.00.a"; + clocks = <&clkc 13>, <&clkc 30>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xe000b000 0x1000>; + interrupts = <0 22 4>; + interrupt-parent = <&gic>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + xlnx,ptp-enet-clock = <111111111>; + xlnx,slcr-div0-1000Mbps = <8>; + xlnx,slcr-div0-100Mbps = <8>; + xlnx,slcr-div0-10Mbps = <8>; + xlnx,slcr-div1-1000Mbps = <1>; + xlnx,slcr-div1-100Mbps = <5>; + xlnx,slcr-div1-10Mbps = <50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@7 { + compatible = "marvell,88e1116r"; + device_type = "ethernet-phy"; + reg = <7>; + }; + }; + }; + + i2c0: i2c@e0004000 { + compatible = "xlnx,ps7-i2c-1.00.a"; + clocks = <&clkc 38>; + reg = <0xE0004000 0x1000>; + interrupts = <0 25 4>; + interrupt-parent = <&gic>; + bus-id = <0>; + input-clk = <111111111>; + i2c-clk = <100000>; + + #address-cells = <1>; + #size-cells = <0>; + i2cswitch@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + osc@5d { + compatible = "si570"; + reg = <0x5d>; + factory-fout = <156250000>; + initial-fout = <148500000>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + hdmio@39 { + compatible = "adv7511"; + reg = <0x39>; + interrupts = <0 54 4>; + interrupt-parent = <&gic>; + dma-request = <&logicvc0>; + edid-addr = <0x50>; + video-input { + input-id = <1>; + input-style = <3>; + input-color-depth = <8>; + bit-justification = <1>; + hsync-polarity = <0>; + vsync-polarity = <0>; + clock-delay = <3>; + }; + video-output { + hdmi-mode = <0>; + output-format = <0>; + output-color-space = <0>; + up-conversion = <0>; + csc-enable = <1>; + csc-scaling-factor = <2>; + csc-coefficients { + a1 = <0x0B37>; + a2 = <0x0800>; + a3 = <0x0000>; + a4 = <0x1A86>; + b1 = <0x1A49>; + b2 = <0x0800>; + b3 = <0x1D3F>; + b4 = <0x0422>; + c1 = <0x0000>; + c2 = <0x0800>; + c3 = <0x0E2D>; + c4 = <0x1914>; + }; + }; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@54 { + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + rtc@54 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c@5{ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + eeprom@50 { + compatible = "at,24c02"; + reg = <0x50>; + }; + }; + + i2c@6{ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + eeprom@50 { + compatible = "at,24c02"; + reg = <0x50>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + hwmon@52 { + compatible = "pmbus,ucd9248"; + reg = <52>; + }; + hwmon@53 { + compatible = "pmbus,ucd9248"; + reg = <53>; + }; + hwmon@54 { + compatible = "pmbus,ucd9248"; + reg = <54>; + }; + }; + }; + }; + + i2c1: i2c@e0005000 { + compatible = "xlnx,ps7-i2c-1.00.a"; + clocks = <&clkc 39>; + reg = <0xE0005000 0x1000>; + interrupts = <0 48 4>; + interrupt-parent = <&gic>; + bus-id = <1>; + input-clk = <111111111>; + i2c-clk = <100000>; + + #address-cells = <1>; + #size-cells = <0>; + i2cswitch@70 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c_adv7611: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + ioexp: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + }; + + sdhci@e0100000 { + compatible = "xlnx,ps7-sdhci-1.00.a"; + clocks = <&clkc 21>, <&clkc 32>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xe0100000 0x1000>; + xlnx,has-cd = <0x1>; + interrupts = <0 24 4>; + interrupt-parent = <&gic>; + clock-frequency = <33333000>; + }; + + usb@e0002000 { + compatible = "xlnx,ps7-usb-1.00.a"; + clocks = <&clkc 28>; + reg = <0xe0002000 0x1000>; + interrupts = <0 21 4>; + interrupt-parent = <&gic>; + dr_mode = "host"; + phy_type = "ulpi"; + }; + + gpio@e000a000 { + compatible = "xlnx,ps7-gpio-1.00.a"; + clocks = <&clkc 42>; + reg = <0xe000a000 0x1000>; + interrupts = <0 20 4>; + interrupt-parent = <&gic>; + }; + + qspi0: spi@e000d000 { + compatible = "xlnx,ps7-qspi-1.00.a"; + clocks = <&clkc 10>, <&clkc 43>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xE000D000 0x1000>; + interrupts = <0 19 4>; + interrupt-parent = <&gic>; + speed-hz = <200000000>; + num-chip-select = <1>; + #address-cells = <1>; + #size-cells = <0>; + is-dual = <0>; + flash@0 { + compatible = "n25q128"; + reg = <0x0>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; + }; + + devcfg@f8007000 { + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + reg = <0xf8007000 0x100>; + interrupts = <0 8 4>; + interrupt-parent = <&gic>; + }; + + xadc@f8007100 { + compatible = "xlnx,ps7-xadc-1.00.a"; + clocks = <&clkc 12>; + reg = <0xf8007100 0x20>; + interrupts = <0 7 4>; + interrupt-parent = <&gic>; + }; + + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + arm,primecell-periphid = <0x41330>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + clocks = <&clkc 27>; + interrupt-parent = <&gic>; + interrupts = <0 13 4 0 14 4 0 15 4 0 16 4 0 17 4 0 40 4 0 41 4 0 42 4 0 43 4>; + reg = <0xf8003000 0x1000>; + }; + + axi_sobel_0: axi-sobel@0x400D0000 { + compatible = "generic-uio"; + reg = <0x400D0000 0x10000>; + interrupts = <0 55 4>; + interrupt-parent = <&gic>; + }; + + yuv2rgb_0: v-ycrcb2rgb@0x40050000 { + compatible = "generic-uio"; + reg = <0x40050000 0x10000>; + }; + + tpg_0: v-tpg@40080000 { + compatible = "generic-uio"; + reg = <0x40080000 0x10000>; + }; + + cresample_0: v-cresample@40040000 { + compatible = "generic-uio"; + reg = <0x40040000 0x10000>; + }; + + vtc_0: v-tc@40070000 { + compatible = "generic-uio"; + reg = <0x40070000 0x10000>; + }; + + perf_mon_hp0_hp2: axi-perf-mon@400f0000 { + compatible = "generic-uio"; + reg = <0x400f0000 0x10000>; + }; + + axi_vdma_0: axivdma@0x40090000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,axi-vdma"; + ranges = <0x40090000 0x40090000 0x10000>; + reg = <0x40090000 0x10000>; + xlnx,flush-fsync = <0x1>; + xlnx,include-sg = <0x0>; + xlnx,num-fstores = <0x3>; + xlnx,family = "zynq-770"; + dma-channel@0x40090000 { + compatible = "xlnx,axi-vdma-s2mm-channel"; + interrupt-parent = <&gic>; + interrupts = <0 58 4>; + xlnx,datawidth = <0x08>; + xlnx,genlock-mode = <0x1>; + xlnx,include-dre = <0x1>; + xlnx,device-id = <0x0>; + }; + }; + + axi_vdma_1: axivdma@0x400B0000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,axi-vdma"; + ranges = <0x400B0000 0x400B0000 0x10000>; + reg = <0x400B0000 0x10000>; + xlnx,flush-fsync = <0x1>; + xlnx,include-sg = <0x0>; + xlnx,num-fstores = <0x3>; + xlnx,family = "zynq-770"; + dma-s2mmchannel@0x400B0000 { + compatible = "xlnx,axi-vdma-s2mm-channel"; + interrupt-parent = <&gic>; + interrupts = <0 57 4>; + xlnx,datawidth = <0x08>; + xlnx,genlock-mode = <0x1>; + xlnx,include-dre = <0x1>; + xlnx,device-id = <0x1>; + }; + dma-mm2schannel@0x400B0000 { + compatible = "xlnx,axi-vdma-mm2s-channel"; + interrupt-parent = <&gic>; + interrupts = <0 56 4>; + xlnx,datawidth = <0x08>; + xlnx,genlock-mode = <0x1>; + xlnx,include-dre = <0x1>; + xlnx,device-id = <0x1>; + }; + }; + + logicvc0: logicvc@40030000 { + compatible = "xylon,logicvc-3.00.a"; + reg = <0x40030000 0x6000>; + interrupt-parent = <&gic>; + interrupts = <0 59 4>; + + xlnx,display-interface = <0>; + xlnx,display-color-space = <1>; + xlnx,ip-license-type = <0>; + xlnx,ip-major-revision = <3>; + xlnx,ip-minor-revision = <0>; + xlnx,ip-patch-level = <0>; + xlnx,num-of-layers = <3>; + xlnx,layer-0-type = <0>; + xlnx,layer-0-alpha-mode = <0>; + xlnx,layer-0-data-width = <16>; + xlnx,layer-0-offset = <0>; + xlnx,layer-1-type = <0>; + xlnx,layer-1-alpha-mode = <0>; + xlnx,layer-1-data-width = <24>; + xlnx,layer-1-offset = <1620>; + xlnx,layer-2-type = <0>; + xlnx,layer-2-alpha-mode = <0>; + xlnx,layer-2-data-width = <24>; + xlnx,layer-2-offset = <6480>; + xlnx,layer-3-type = <0>; + xlnx,layer-3-alpha-mode = <0>; + xlnx,layer-3-data-width = <24>; + xlnx,layer-3-offset = <9720>; + xlnx,layer-4-type = <0>; + xlnx,layer-4-alpha-mode = <0>; + xlnx,layer-4-data-width = <24>; + xlnx,layer-4-offset = <12960>; + xlnx,buffer-0-offset = <1080>; + xlnx,buffer-1-offset = <1080>; + xlnx,buffer-2-offset = <1080>; + xlnx,buffer-3-offset = <1080>; + xlnx,buffer-4-offset = <1080>; + xlnx,little-endian = <1>; + xlnx,readable-regs = <1>; + xlnx,row-stride = <2048>; + xlnx,use-background = <1>; + xlnx,use-size-position = <1>; + xlnx,vmem-baseaddr = <0x30000000>; + xlnx,vmem-highaddr = <0x3FFFFFFF>; + + //0-EXT; 1-ZynqPS; 2-logiCLK; 3-SI570 + pixel-clock-source = <3>; + pixel-data-invert = <0>; + pixel-clock-active-high = <1>; + pixel-component-format = "ARGB"; + pixel-component-layer = <0>,<1>,<2>; + active-layer = <0>; + videomode = "1920x1080"; + edid { + preffered-videomode = <1>; + display-data = <0>; + }; + }; + + xylon-video-params { + 800x480_TM050RBH01 { + name = "800x480_TM050RBH01"; + refresh = <60>; + xres = <800>; + yres = <480>; + pixclock-khz = <30000>; + left-margin = <40>; + right-margin = <40>; + upper-margin = <29>; + lower-margin = <13>; + hsync-len = <48>; + vsync-len = <3>; + sync = <0>; + vmode = <0>; + }; + 1280x720 { + name = "1280x720"; + refresh = <60>; + xres = <1280>; + yres = <720>; + pixclock-khz = <74250>; + left-margin = <220>; + right-margin = <110>; + upper-margin = <20>; + lower-margin = <5>; + hsync-len = <40>; + vsync-len = <5>; + sync = <0>; + vmode = <0>; + }; + 1680x1050 { + name = "1680x1050"; + refresh = <60>; + xres = <1680>; + yres = <1050>; + pixclock-khz = <119000>; + left-margin = <80>; + right-margin = <48>; + upper-margin = <21>; + lower-margin = <3>; + hsync-len = <32>; + vsync-len = <6>; + sync = <0>; + vmode = <0>; + }; + 1920x1080 { + name = "1920x1080"; + refresh = <60>; + xres = <1920>; + yres = <1080>; + pixclock-khz = <148500>; + left-margin = <148>; + right-margin = <88>; + upper-margin = <36>; + lower-margin = <4>; + hsync-len = <44>; + vsync-len = <5>; + sync = <0>; + vmode = <0>; + }; + }; + }; +}; Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc702-drm-v4l2.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc702-drm-v4l2.dts 2014-07-20 22:06:33.915345982 +0200 @@ -0,0 +1,595 @@ +/* + * Device Tree Generator version: 1.1 + * + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.5 EDK_P.58f + * + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + aliases { + ethernet0 = &ps7_ethernet_0; + i2c0 = &ps7_i2c_0; + serial0 = &ps7_uart_1; + spi0 = &ps7_qspi_0; + } ; + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0001000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + } ; + ps7_ddr_0: memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_can_0: ps7-can@e0008000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 19>, <&clkc 36>; + compatible = "xlnx,ps7-can-1.00.a", "xlnx,ps7-can"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 28 4>; + reg = <0xe0008000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + arm,primecell-periphid = <0x41330>; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_ethernet_0: ps7-ethernet@e000b000 { + #address-cells = <1>; + #size-cells = <0>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 13>, <&clkc 30>; + compatible = "xlnx,ps7-ethernet-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 22 4>; + local-mac-address = [00 0a 35 00 00 00]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + reg = <0xe000b000 0x1000>; + xlnx,enet-reset = "MIO 11"; + xlnx,eth-mode = <0x1>; + xlnx,has-mdio = <0x1>; + xlnx,ptp-enet-clock = <111111115>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@7 { + compatible = "marvell,88e1116r"; + device_type = "ethernet-phy"; + reg = <7>; + } ; + } ; + } ; + ps7_gpio_0: ps7-gpio@e000a000 { + #gpio-cells = <2>; + clocks = <&clkc 42>; + compatible = "xlnx,ps7-gpio-1.00.a"; + emio-gpio-width = <64>; + gpio-controller ; + gpio-mask-high = <0x0>; + gpio-mask-low = <0x5600>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + } ; + ps7_i2c_0: ps7-i2c@e0004000 { + bus-id = <0>; + clocks = <&clkc 38>; + compatible = "xlnx,ps7-i2c-1.00.a"; + i2c-clk = <400000>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 25 4>; + reg = <0xe0004000 0x1000>; + xlnx,has-interrupt = <0x0>; + xlnx,i2c-reset = "MIO 13"; + #address-cells = <1>; + #size-cells = <0>; + i2cswitch@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + si570: si570@5d { + compatible = "si570"; + reg = <0x5d>; + factory-fout = <156250000>; + initial-fout = <148500000>; + }; + }; + + i2c_adv7511: i2c@1 { + #size-cells = <0>; + #address-cells = <1>; + reg = <1>; + + adv7511: adv7511@39 { + compatible = "adi,adv7511"; + reg = <0x39>; + adi,input-style = <0x02>; + adi,input-id = <0x01>; + adi,input-color-depth = <0x3>; + adi,sync-pulse = <0x03>; + adi,bit-justification = <0x01>; + adi,up-conversion = <0x00>; + adi,timing-generation-sequence = <0x00>; + adi,vsync-polarity = <0x02>; + adi,hsync-polarity = <0x02>; + adi,tdms-clock-inversion; + adi,clock-delay = <0x00>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@54 { + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + rtc@54 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + hwmon@52 { + compatible = "pmbus,ucd9248"; + reg = <52>; + }; + hwmon@53 { + compatible = "pmbus,ucd9248"; + reg = <53>; + }; + hwmon@54 { + compatible = "pmbus,ucd9248"; + reg = <54>; + }; + }; + }; + + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_qspi_0: ps7-qspi@e000d000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 19 4>; + is-dual = <0>; + num-chip-select = <1>; + reg = <0xe000d000 0x1000>; + xlnx,fb-clk = <0x1>; + xlnx,qspi-mode = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "n25q128"; + reg = <0x0>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; + + } ; + ps7_qspi_linear_0: ps7-qspi-linear@fc000000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-linear-1.00.a"; + reg = <0xfc000000 0x1000000>; + } ; + ps7_ram_0: ps7-ram@0 { + compatible = "xlnx,ps7-ram-1.00.a", "xlnx,ps7-ocm"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xfffc0000 0x40000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_sd_0: ps7-sdio@e0100000 { + clock-frequency = <50000000>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 21>, <&clkc 32>; + compatible = "xlnx,ps7-sdio-1.00.a", "generic-sdhci"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + xlnx,has-cd = <0x1>; + xlnx,has-power = <0x0>; + xlnx,has-wp = <0x1>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr"; + reg = <0xf8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clkc: clkc { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + } ; + } ; + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_uart_1: serial@e0001000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 24>, <&clkc 41>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 50 4>; + port-number = <0>; + reg = <0xe0001000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_usb_0: ps7-usb@e0002000 { + clocks = <&clkc 28>; + compatible = "xlnx,ps7-usb-1.00.a"; + dr_mode = "host"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 21 4>; + phy_type = "ulpi"; + reg = <0xe0002000 0x1000>; + xlnx,usb-reset = "MIO 7"; + } ; + ps7_wdt_0: ps7-wdt@f8005000 { + clocks = <&clkc 45>; + compatible = "xlnx,ps7-wdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + reset = <0>; + timeout = <10>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + + axi_vdma_0: axivdma@40000000 { + compatible = "xlnx,axi-vdma"; + reg = <0x40000000 0x10000>; + + xlnx,flush-fsync = <1>; + xlnx,num-fstores = <1>; + xlnx,family = "zynq-770"; + + #dma-cells = <1>; + dma-mm2schannel@40000000 { + compatible = "xlnx,axi-vdma-mm2s-channel"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 58 0x4>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0>; + }; + }; + + axi_vdma_1: axivdma@40060000 { + compatible = "xlnx,axi-vdma"; + reg = <0x40060000 0x10000>; + + xlnx,flush-fsync = <1>; + xlnx,num-fstores = <1>; + xlnx,family = "zynq-770"; + + #dma-cells = <1>; + dma-mm2schannel@40060000 { + compatible = "xlnx,axi-vdma-mm2s-channel"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 57 0x4>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0>; + }; + dma-s2mmchannel@40060000 { + compatible = "xlnx,axi-vdma-s2mm-channel"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 56 4>; + xlnx,datawidth = <0x40>; + xlnx,include-dre; + xlnx,device-id = <1>; + }; + }; + + axi_vdma_2: axivdma@400a0000 { + compatible = "xlnx,axi-vdma"; + reg = <0x400a0000 0x10000>; + + xlnx,flush-fsync = <1>; + xlnx,num-fstores = <1>; + xlnx,family = "zynq-770"; + + #dma-cells = <1>; + dma-mm2schannel@400a0000 { + compatible = "xlnx,axi-vdma-mm2s-channel"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 35 0x4>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0>; + }; + }; + + vtc_0: v-tc@40010000 { + compatible = "xlnx,v-tc-6.0"; + reg = <0x40010000 0x10000>; + interrupts = <0 54 4>; + interrupt-parent = <&ps7_scugic_0>; + }; + + cresample_0: v-cresample@40020000 { + compatible = "xlnx,v-cresample-4.0"; + reg = <0x40020000 0x10000>; + xlnx,input-format = "yuv444"; + xlnx,output-format = "yuv422"; + }; + + rgb2ycrcb_0: v-rgb2ycrcb@40030000 { + compatible = "xlnx,v-rgb2ycrcb-7.0"; + reg = <0x40030000 0x10000>; + }; + + osd_0: v-osd@40040000 { + compatible = "xlnx,v-osd-6.0"; + reg = <0x40040000 0x10000>; + xlnx,num-layers = <3>; + xlnx,screen-width = <1920>; + }; + + xilinx_drm { + compatible = "xlnx,drm"; + osd = <&osd_0>; + vtc = <&vtc_0>; + encoder-slave = <&adv7511>; + clocks = <&si570>; + planes { + plane0 { + dmas = <&axi_vdma_0 0>; + dma-names = "vdma"; + rgb2yuv = <&rgb2ycrcb_0>; + cresample = <&cresample_0>; + }; + plane1 { + dmas = <&axi_vdma_1 0>; + dma-names = "vdma"; + }; + plane2 { + dmas = <&axi_vdma_2 0>; + dma-names = "vdma"; + }; + }; + }; + + axi_tpg_0: axi_tpg@40050000 { + compatible = "xlnx,axi-tpg"; + reg = <0x40050000 0x10000>; + + xlnx,axi-video-format = "yuv422"; + xlnx,axi-video-width = <8>; + + port { + tpg0_out: endpoint { + remote-endpoint = <&vcap0_in>; + }; + }; + }; + + axi_video_cap { + compatible = "xlnx,axi-video"; + dmas = <&axi_vdma_1 1>; + dma-names = "vdma-s2mm"; + + vdma-s2mm { + port { + vcap0_in: endpoint { + remote-endpoint = <&tpg0_out>; + }; + }; + }; + }; + + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc702.dts =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/boot/dts/zynq-zc702.dts 2014-07-20 22:05:50.283065845 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc702.dts 2014-07-20 22:06:33.926345800 +0200 @@ -1,34 +1,422 @@ /* - * Copyright (C) 2011 Xilinx - * Copyright (C) 2012 National Instruments Corp. + * Device Tree Generator version: 1.1 * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.5 EDK_P.58f * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ -/dts-v1/; -/include/ "zynq-7000.dtsi" +/dts-v1/; / { - model = "Zynq ZC702 Development Board"; - compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; - - memory { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + aliases { + ethernet0 = &ps7_ethernet_0; + i2c0 = &ps7_i2c_0; + serial0 = &ps7_uart_1; + spi0 = &ps7_qspi_0; + } ; + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0001000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + reg-names = "cpu0", "cpu1"; + } ; + ps7_ddr_0: memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; - }; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_can_0: ps7-can@e0008000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 19>, <&clkc 36>; + compatible = "xlnx,ps7-can-1.00.a", "xlnx,ps7-can"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 28 4>; + reg = <0xe0008000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clock-names = "apb_pclk"; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_ethernet_0: ps7-ethernet@e000b000 { + #address-cells = <1>; + #size-cells = <0>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 13>, <&clkc 30>; + compatible = "xlnx,ps7-ethernet-1.00.a"; + enet-reset = <&ps7_gpio_0 11 0>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 22 4>; + local-mac-address = [00 0a 35 00 00 00]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + reg = <0xe000b000 0x1000>; + xlnx,eth-mode = <0x1>; + xlnx,has-mdio = <0x1>; + xlnx,ptp-enet-clock = <111111115>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@7 { + compatible = "marvell,88e1116r"; + device_type = "ethernet-phy"; + reg = <7>; + } ; + } ; + } ; + ps7_gpio_0: ps7-gpio@e000a000 { + #gpio-cells = <2>; + clocks = <&clkc 42>; + compatible = "xlnx,ps7-gpio-1.00.a"; + emio-gpio-width = <64>; + gpio-controller ; + gpio-mask-high = <0x0>; + gpio-mask-low = <0x5600>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + } ; + ps7_i2c_0: ps7-i2c@e0004000 { + bus-id = <0>; + clocks = <&clkc 38>; + compatible = "xlnx,ps7-i2c-1.00.a"; + i2c-clk = <400000>; + i2c-reset = <&ps7_gpio_0 13 0>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 25 4>; + reg = <0xe0004000 0x1000>; + xlnx,has-interrupt = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + i2cswitch@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; - chosen { - bootargs = "console=ttyPS0,115200 earlyprintk"; - }; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + si570: clock-generator@5d { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x5d>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@54 { + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + rtc@54 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + hwmon@52 { + compatible = "pmbus,ucd9248"; + reg = <52>; + }; + hwmon@53 { + compatible = "pmbus,ucd9248"; + reg = <53>; + }; + hwmon@54 { + compatible = "pmbus,ucd9248"; + reg = <54>; + }; + }; + }; -}; + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_ocmc_0: ps7-ocmc@f800c000 { + compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_qspi_0: ps7-qspi@e000d000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 19 4>; + is-dual = <0>; + num-chip-select = <1>; + reg = <0xe000d000 0x1000>; + xlnx,fb-clk = <0x1>; + xlnx,qspi-mode = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "n25q128"; + reg = <0x0>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; -&uart1 { - status = "okay"; -}; + } ; + ps7_qspi_linear_0: ps7-qspi-linear@fc000000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-linear-1.00.a"; + reg = <0xfc000000 0x1000000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_sd_0: ps7-sdio@e0100000 { + clock-frequency = <50000000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + compatible = "xlnx,ps7-sdio-1.00.a", "generic-sdhci", "arasan,sdhci-8.9a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + xlnx,has-cd = <0x1>; + xlnx,has-power = <0x0>; + xlnx,has-wp = <0x1>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr"; + reg = <0xf8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clkc: clkc { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + } ; + } ; + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_uart_1: serial@e0001000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 24>, <&clkc 41>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 50 4>; + port-number = <0>; + reg = <0xe0001000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_usb_0: ps7-usb@e0002000 { + clocks = <&clkc 28>; + compatible = "xlnx,ps7-usb-1.00.a"; + dr_mode = "host"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 21 4>; + phy_type = "ulpi"; + reg = <0xe0002000 0x1000>; + usb-reset = <&ps7_gpio_0 7 0>; + } ; + ps7_wdt_0: ps7-wdt@f8005000 { + clocks = <&clkc 45>; + compatible = "xlnx,ps7-wdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + reset = <0>; + timeout = <10>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc706.dts =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/boot/dts/zynq-zc706.dts 2014-07-20 22:05:50.285065813 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc706.dts 2014-07-20 22:06:33.939345586 +0200 @@ -1,35 +1,415 @@ /* - * Copyright (C) 2011 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * Copyright (C) 2013 Xilinx + * Device Tree Generator version: 1.1 * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.5 EDK_P.58f * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ -/dts-v1/; -/include/ "zynq-7000.dtsi" +/dts-v1/; / { - model = "Zynq ZC706 Development Board"; - compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; - - memory { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + aliases { + ethernet0 = &ps7_ethernet_0; + i2c0 = &ps7_i2c_0; + serial0 = &ps7_uart_1; + spi0 = &ps7_qspi_0; + } ; + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0001000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + reg-names = "cpu0", "cpu1"; + } ; + ps7_ddr_0: memory@0 { device_type = "memory"; - reg = <0 0x40000000>; - }; + reg = <0x0 0x40000000>; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clock-names = "apb_pclk"; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_ethernet_0: ps7-ethernet@e000b000 { + #address-cells = <1>; + #size-cells = <0>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 13>, <&clkc 30>; + compatible = "xlnx,ps7-ethernet-1.00.a"; + enet-reset = <&ps7_gpio_0 47 0>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 22 4>; + local-mac-address = [00 0a 35 00 00 00]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + reg = <0xe000b000 0x1000>; + xlnx,eth-mode = <0x1>; + xlnx,has-mdio = <0x1>; + xlnx,ptp-enet-clock = <111111115>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@7 { + compatible = "marvell,88e1116r"; + device_type = "ethernet-phy"; + reg = <7>; + } ; + } ; + } ; + ps7_gpio_0: ps7-gpio@e000a000 { + #gpio-cells = <2>; + clocks = <&clkc 42>; + compatible = "xlnx,ps7-gpio-1.00.a"; + emio-gpio-width = <64>; + gpio-controller ; + gpio-mask-high = <0x0>; + gpio-mask-low = <0x0>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + } ; + ps7_i2c_0: ps7-i2c@e0004000 { + bus-id = <0>; + clocks = <&clkc 38>; + compatible = "xlnx,ps7-i2c-1.00.a"; + i2c-clk = <400000>; + i2c-reset = <&ps7_gpio_0 46 0>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 25 4>; + reg = <0xe0004000 0x1000>; + xlnx,has-interrupt = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + i2cswitch@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; - chosen { - bootargs = "console=ttyPS0,115200 earlyprintk"; - }; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + si570: clock-generator@5d { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x5d>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@54 { + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + ucd90120@65 { + compatible = "pmbus,ucd90120"; + reg = <0x65>; + }; + }; + }; -}; + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_ocmc_0: ps7-ocmc@f800c000 { + compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_qspi_0: ps7-qspi@e000d000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 19 4>; + is-dual = <1>; + num-chip-select = <1>; + reg = <0xe000d000 0x1000>; + xlnx,fb-clk = <0x1>; + xlnx,qspi-mode = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "n25q128"; + reg = <0x0>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; -&uart1 { - status = "okay"; -}; + } ; + ps7_qspi_linear_0: ps7-qspi-linear@fc000000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-linear-1.00.a"; + reg = <0xfc000000 0x2000000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_sd_0: ps7-sdio@e0100000 { + clock-frequency = <50000000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + compatible = "xlnx,ps7-sdio-1.00.a", "generic-sdhci", "arasan,sdhci-8.9a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + xlnx,has-cd = <0x1>; + xlnx,has-power = <0x0>; + xlnx,has-wp = <0x1>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr"; + reg = <0xf8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clkc: clkc { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + } ; + } ; + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_ttc_1: ps7-ttc@f8002000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 37 4>, <0 38 4>, <0 39 4>; + reg = <0xf8002000 0x1000>; + } ; + ps7_uart_1: serial@e0001000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 24>, <&clkc 41>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 50 4>; + port-number = <0>; + reg = <0xe0001000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_usb_0: ps7-usb@e0002000 { + clocks = <&clkc 28>; + compatible = "xlnx,ps7-usb-1.00.a"; + dr_mode = "host"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 21 4>; + phy_type = "ulpi"; + reg = <0xe0002000 0x1000>; + usb-reset = <&ps7_gpio_0 7 0>; + } ; + ps7_wdt_0: ps7-wdt@f8005000 { + clocks = <&clkc 45>; + compatible = "xlnx,ps7-wdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + reset = <0>; + timeout = <10>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc770-xm010.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc770-xm010.dts 2014-07-20 22:06:33.950345405 +0200 @@ -0,0 +1,378 @@ +/* + * Device Tree Generator version: 1.1 + * + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.5 EDK_P.58f + * + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + aliases { + ethernet0 = &ps7_ethernet_0; + i2c0 = &ps7_i2c_0; + serial0 = &ps7_uart_1; + spi0 = &ps7_spi_1; + spi1 = &ps7_qspi_0; + } ; + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0001000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + reg-names = "cpu0", "cpu1"; + } ; + ps7_ddr_0: memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_can_0: ps7-can@e0008000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 19>, <&clkc 36>; + compatible = "xlnx,ps7-can-1.00.a", "xlnx,ps7-can"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 28 4>; + reg = <0xe0008000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clock-names = "apb_pclk"; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_ethernet_0: ps7-ethernet@e000b000 { + #address-cells = <1>; + #size-cells = <0>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 13>, <&clkc 30>; + compatible = "xlnx,ps7-ethernet-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 22 4>; + local-mac-address = [00 0a 35 00 00 00]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + reg = <0xe000b000 0x1000>; + xlnx,eth-mode = <0x1>; + xlnx,has-mdio = <0x1>; + xlnx,ptp-enet-clock = <111111115>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@7 { + compatible = "marvell,88e1116r"; + device_type = "ethernet-phy"; + reg = <7>; + } ; + } ; + } ; + ps7_gpio_0: ps7-gpio@e000a000 { + #gpio-cells = <2>; + clocks = <&clkc 42>; + compatible = "xlnx,ps7-gpio-1.00.a"; + emio-gpio-width = <64>; + gpio-controller ; + gpio-mask-high = <0x0>; + gpio-mask-low = <0x200>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + } ; + ps7_i2c_0: ps7-i2c@e0004000 { + bus-id = <0>; + clocks = <&clkc 38>; + compatible = "xlnx,ps7-i2c-1.00.a"; + i2c-clk = <400000>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 25 4>; + reg = <0xe0004000 0x1000>; + xlnx,has-interrupt = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; + }; + + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_ocmc_0: ps7-ocmc@f800c000 { + compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_qspi_0: ps7-qspi@e000d000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 19 4>; + is-dual = <0>; + num-chip-select = <1>; + reg = <0xe000d000 0x1000>; + xlnx,fb-clk = <0x1>; + xlnx,qspi-mode = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "n25q128"; + reg = <0x0>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; + + } ; + ps7_qspi_linear_0: ps7-qspi-linear@fc000000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-linear-1.00.a"; + reg = <0xfc000000 0x1000000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_sd_0: ps7-sdio@e0100000 { + clock-frequency = <50000000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + compatible = "xlnx,ps7-sdio-1.00.a", "generic-sdhci", "arasan,sdhci-8.9a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + xlnx,has-cd = <0x1>; + xlnx,has-power = <0x0>; + xlnx,has-wp = <0x1>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr"; + reg = <0xf8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clkc: clkc { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + } ; + } ; + } ; + ps7_spi_1: ps7-spi@e0007000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 26>, <&clkc 35>; + compatible = "xlnx,ps7-spi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 49 4>; + num-chip-select = <4>; + reg = <0xe0007000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "sst25wf080"; + reg = <1>; + spi-max-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@test { + label = "spi-flash"; + reg = <0x0 0x100000>; + }; + }; + + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_uart_1: serial@e0001000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 24>, <&clkc 41>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 50 4>; + port-number = <0>; + reg = <0xe0001000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_usb_0: ps7-usb@e0002000 { + clocks = <&clkc 28>; + compatible = "xlnx,ps7-usb-1.00.a"; + dr_mode = "host"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 21 4>; + phy_type = "ulpi"; + reg = <0xe0002000 0x1000>; + usb-reset = <&ps7_gpio_0 7 0>; + } ; + ps7_wdt_0: ps7-wdt@f8005000 { + clocks = <&clkc 45>; + compatible = "xlnx,ps7-wdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + reset = <0>; + timeout = <10>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc770-xm011.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc770-xm011.dts 2014-07-20 22:06:33.961345223 +0200 @@ -0,0 +1,329 @@ +/* + * Device Tree Generator version: 1.1 + * + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.5 EDK_P.58f + * + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + aliases { + i2c0 = &ps7_i2c_1; + serial0 = &ps7_uart_1; + spi0 = &ps7_spi_0; + } ; + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0001000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + reg-names = "cpu0", "cpu1"; + } ; + ps7_ddr_0: memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_can_0: ps7-can@e0008000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 19>, <&clkc 36>; + compatible = "xlnx,ps7-can-1.00.a", "xlnx,ps7-can"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 28 4>; + reg = <0xe0008000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clock-names = "apb_pclk"; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_gpio_0: ps7-gpio@e000a000 { + #gpio-cells = <2>; + clocks = <&clkc 42>; + compatible = "xlnx,ps7-gpio-1.00.a"; + emio-gpio-width = <64>; + gpio-controller ; + gpio-mask-high = <0xfc>; + gpio-mask-low = <0xff8002>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + } ; + ps7_i2c_1: ps7-i2c@e0005000 { + bus-id = <0>; + clocks = <&clkc 39>; + compatible = "xlnx,ps7-i2c-1.00.a"; + i2c-clk = <400000>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 48 4>; + reg = <0xe0005000 0x1000>; + xlnx,has-interrupt = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; + }; + + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_ocmc_0: ps7-ocmc@f800c000 { + compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr"; + reg = <0xf8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clkc: clkc { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + } ; + } ; + } ; + ps7_smcc_0: ps7-smcc@e000e000 { + #address-cells = <1>; + #size-cells = <1>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 11>, <&clkc 44>; + compatible = "xlnx,ps7-smcc-1.00.a", "xlnx,ps7-smc"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 18 4>; + ranges ; + reg = <0xe000e000 0x1000>; + xlnx,addr25 = <0x0>; + xlnx,nor-chip-sel0 = <0x0>; + xlnx,nor-chip-sel1 = <0x0>; + xlnx,sram-chip-sel0 = <0x0>; + xlnx,sram-chip-sel1 = <0x0>; + ps7_nand_0: ps7-nand@e1000000 { + compatible = "xlnx,ps7-nand-1.00.a"; + reg = <0xe1000000 0x1000000>; + xlnx,nand-cycle-t0 = <0x4>; + xlnx,nand-cycle-t1 = <0x4>; + xlnx,nand-cycle-t2 = <0x1>; + xlnx,nand-cycle-t3 = <0x2>; + xlnx,nand-cycle-t4 = <0x2>; + xlnx,nand-cycle-t5 = <0x2>; + xlnx,nand-cycle-t6 = <0x4>; + xlnx,nand-width = <0x8>; + #address-cells = <1>; + #size-cells = <1>; + + partition@nand-fsbl-uboot { + label = "nand-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@nand-linux { + label = "nand-linux"; + reg = <0x100000 0x500000>; + }; + partition@nand-device-tree { + label = "nand-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@nand-rootfs { + label = "nand-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@nand-bitstream { + label = "nand-bitstream"; + reg = <0xC00000 0x400000>; + + }; + + } ; + } ; + ps7_spi_0: ps7-spi@e0006000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 25>, <&clkc 34>; + compatible = "xlnx,ps7-spi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 26 4>; + num-chip-select = <4>; + reg = <0xe0006000 0x1000>; + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_uart_1: serial@e0001000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 24>, <&clkc 41>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 50 4>; + port-number = <0>; + reg = <0xe0001000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_usb_1: ps7-usb@e0003000 { + clocks = <&clkc 29>; + compatible = "xlnx,ps7-usb-1.00.a"; + dr_mode = "host"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 44 4>; + phy_type = "ulpi"; + reg = <0xe0003000 0x1000>; + } ; + ps7_wdt_0: ps7-wdt@f8005000 { + clocks = <&clkc 45>; + compatible = "xlnx,ps7-wdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + reset = <0>; + timeout = <10>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc770-xm012.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc770-xm012.dts 2014-07-20 22:06:33.969345091 +0200 @@ -0,0 +1,344 @@ +/* + * Device Tree Generator version: 1.1 + * + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.5 EDK_P.58f + * + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + aliases { + i2c0 = &ps7_i2c_0; + i2c1 = &ps7_i2c_1; + serial0 = &ps7_uart_1; + spi0 = &ps7_spi_1; + } ; + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0001000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + reg-names = "cpu0", "cpu1"; + } ; + ps7_ddr_0: memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_can_1: ps7-can@e0009000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 20>, <&clkc 37>; + compatible = "xlnx,ps7-can-1.00.a", "xlnx,ps7-can"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 51 4>; + reg = <0xe0009000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clock-names = "apb_pclk"; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_gpio_0: ps7-gpio@e000a000 { + #gpio-cells = <2>; + clocks = <&clkc 42>; + compatible = "xlnx,ps7-gpio-1.00.a"; + emio-gpio-width = <64>; + gpio-controller ; + gpio-mask-high = <0x0>; + gpio-mask-low = <0x4004>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + } ; + ps7_i2c_0: ps7-i2c@e0004000 { + bus-id = <0>; + clocks = <&clkc 38>; + compatible = "xlnx,ps7-i2c-1.00.a"; + i2c-clk = <400000>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 25 4>; + reg = <0xe0004000 0x1000>; + xlnx,has-interrupt = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; + }; + + } ; + ps7_i2c_1: ps7-i2c@e0005000 { + bus-id = <1>; + clocks = <&clkc 39>; + compatible = "xlnx,ps7-i2c-1.00.a"; + i2c-clk = <400000>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 48 4>; + reg = <0xe0005000 0x1000>; + xlnx,has-interrupt = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; + }; + + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_ocmc_0: ps7-ocmc@f800c000 { + compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr"; + reg = <0xf8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clkc: clkc { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + } ; + } ; + } ; + ps7_smcc_0: ps7-smcc@e000e000 { + #address-cells = <1>; + #size-cells = <1>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 11>, <&clkc 44>; + compatible = "xlnx,ps7-smcc-1.00.a", "xlnx,ps7-smc"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 18 4>; + ranges ; + reg = <0xe000e000 0x1000>; + xlnx,addr25 = <0x1>; + xlnx,nor-chip-sel0 = <0x1>; + xlnx,nor-chip-sel1 = <0x0>; + xlnx,sram-chip-sel0 = <0x0>; + xlnx,sram-chip-sel1 = <0x0>; + ps7_nor_0: ps7-nor@e2000000 { + bank-width = <1>; + compatible = "xlnx,ps7-nor-1.00.a", "cfi-flash"; + reg = <0xe2000000 0x1000>; + xlnx,sram-cycle-t0 = <0xb>; + xlnx,sram-cycle-t1 = <0xb>; + xlnx,sram-cycle-t2 = <0x4>; + xlnx,sram-cycle-t3 = <0x4>; + xlnx,sram-cycle-t4 = <0x3>; + xlnx,sram-cycle-t5 = <0x3>; + xlnx,sram-cycle-t6 = <0x2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@nor-fsbl-uboot { + label = "nor-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@nor-linux { + label = "nor-linux"; + reg = <0x100000 0x500000>; + }; + partition@nor-device-tree { + label = "nor-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@nor-rootfs { + label = "nor-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@nor-bitstream { + label = "nor-bitstream"; + reg = <0xC00000 0x400000>; + }; + } ; + } ; + ps7_spi_1: ps7-spi@e0007000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 26>, <&clkc 35>; + compatible = "xlnx,ps7-spi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 49 4>; + num-chip-select = <4>; + reg = <0xe0007000 0x1000>; + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_ttc_1: ps7-ttc@f8002000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 37 4>, <0 38 4>, <0 39 4>; + reg = <0xf8002000 0x1000>; + } ; + ps7_uart_1: serial@e0001000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 24>, <&clkc 41>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 50 4>; + port-number = <0>; + reg = <0xe0001000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_wdt_0: ps7-wdt@f8005000 { + clocks = <&clkc 45>; + compatible = "xlnx,ps7-wdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + reset = <0>; + timeout = <10>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc770-xm013.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zc770-xm013.dts 2014-07-20 22:06:33.978344943 +0200 @@ -0,0 +1,357 @@ +/* + * Device Tree Generator version: 1.1 + * + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.5 EDK_P.58f + * + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + aliases { + ethernet0 = &ps7_ethernet_1; + i2c0 = &ps7_i2c_1; + serial0 = &ps7_uart_0; + spi0 = &ps7_spi_0; + spi1 = &ps7_qspi_0; + } ; + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0000000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + reg-names = "cpu0", "cpu1"; + } ; + ps7_ddr_0: memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_can_1: ps7-can@e0009000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 20>, <&clkc 37>; + compatible = "xlnx,ps7-can-1.00.a", "xlnx,ps7-can"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 51 4>; + reg = <0xe0009000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clock-names = "apb_pclk"; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_ethernet_1: ps7-ethernet@e000c000 { + #address-cells = <1>; + #size-cells = <0>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 14>, <&clkc 31>; + compatible = "xlnx,ps7-ethernet-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 45 4>; + local-mac-address = [00 0a 35 00 00 00]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + reg = <0xe000c000 0x1000>; + xlnx,eth-mode = <0x1>; + xlnx,has-mdio = <0x1>; + xlnx,ptp-enet-clock = <111111115>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@7 { + compatible = "vitesse,vsc8211"; + device_type = "ethernet-phy"; + reg = <7>; + } ; + } ; + } ; + ps7_gpio_0: ps7-gpio@e000a000 { + #gpio-cells = <2>; + clocks = <&clkc 42>; + compatible = "xlnx,ps7-gpio-1.00.a"; + emio-gpio-width = <64>; + gpio-controller ; + gpio-mask-high = <0xdc000>; + gpio-mask-low = <0xfc00080>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + } ; + ps7_i2c_1: ps7-i2c@e0005000 { + bus-id = <0>; + clocks = <&clkc 39>; + compatible = "xlnx,ps7-i2c-1.00.a"; + i2c-clk = <400000>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 48 4>; + reg = <0xe0005000 0x1000>; + xlnx,has-interrupt = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + si570: clock-generator@55 { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x55>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_ocmc_0: ps7-ocmc@f800c000 { + compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_qspi_0: ps7-qspi@e000d000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 19 4>; + is-dual = <1>; + num-chip-select = <1>; + reg = <0xe000d000 0x1000>; + xlnx,fb-clk = <0x1>; + xlnx,qspi-mode = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "n25q128"; + reg = <0x0>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; + + } ; + ps7_qspi_linear_0: ps7-qspi-linear@fc000000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-linear-1.00.a"; + reg = <0xfc000000 0x2000000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr"; + reg = <0xf8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clkc: clkc { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + } ; + } ; + } ; + ps7_spi_0: ps7-spi@e0006000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 25>, <&clkc 34>; + compatible = "xlnx,ps7-spi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 26 4>; + num-chip-select = <4>; + reg = <0xe0006000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + eeprom: at25@0 { + at25,byte-len = <8192>; + at25,addr-mode = <2>; + at25,page-size = <32>; + + compatible = "atmel,at25"; + reg = <2>; + spi-max-frequency = <1000000>; + }; + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_uart_0: serial@e0000000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 23>, <&clkc 40>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 27 4>; + port-number = <0>; + reg = <0xe0000000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_wdt_0: ps7-wdt@f8005000 { + clocks = <&clkc 45>; + compatible = "xlnx,ps7-wdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + reset = <0>; + timeout = <10>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zed.dts =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/boot/dts/zynq-zed.dts 2014-07-20 22:05:50.287065779 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/boot/dts/zynq-zed.dts 2014-07-20 22:06:33.988344778 +0200 @@ -1,35 +1,317 @@ /* - * Copyright (C) 2011 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * Copyright (C) 2013 Xilinx + * Device Tree Generator version: 1.1 * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. + * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 14.5 EDK_P.58f * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ -/dts-v1/; -/include/ "zynq-7000.dtsi" +/dts-v1/; / { - model = "Zynq Zed Development Board"; + #address-cells = <1>; + #size-cells = <1>; compatible = "xlnx,zynq-7000"; - - memory { - device_type = "memory"; - reg = <0 0x20000000>; - }; - + model = "Xilinx Zynq"; + aliases { + ethernet0 = &ps7_ethernet_0; + serial0 = &ps7_uart_1; + spi0 = &ps7_qspi_0; + } ; chosen { - bootargs = "console=ttyPS0,115200 earlyprintk"; - }; - -}; + bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rootwait rw earlyprintk"; + linux,stdout-path = "/amba@0/serial@e0001000"; + } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + ps7_cortexa9_0: cpu@0 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x0>; + } ; + ps7_cortexa9_1: cpu@1 { + bus-handle = <&ps7_axi_interconnect_0>; + compatible = "arm,cortex-a9"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <&ps7_scugic_0>; + reg = <0x1>; + } ; + } ; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 5 4>, <0 6 4>; + reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; + reg-names = "cpu0", "cpu1"; + } ; + ps7_ddr_0: memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + } ; + ps7_axi_interconnect_0: amba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; + ranges ; + ps7_afi_0: ps7-afi@f8008000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8008000 0x1000>; + } ; + ps7_afi_1: ps7-afi@f8009000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf8009000 0x1000>; + } ; + ps7_afi_2: ps7-afi@f800a000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800a000 0x1000>; + } ; + ps7_afi_3: ps7-afi@f800b000 { + compatible = "xlnx,ps7-afi-1.00.a"; + reg = <0xf800b000 0x1000>; + } ; + ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; + xlnx,has-ecc = <0x0>; + } ; + ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + compatible = "xlnx,ps7-dev-cfg-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 8 4>; + reg = <0xf8007000 0x100>; + } ; + ps7_dma_s: ps7-dma@f8003000 { + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clock-names = "apb_pclk"; + clocks = <&clkc 27>; + compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330"; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; + reg = <0xf8003000 0x1000>; + } ; + ps7_ethernet_0: ps7-ethernet@e000b000 { + #address-cells = <1>; + #size-cells = <0>; + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 13>, <&clkc 30>; + compatible = "xlnx,ps7-ethernet-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 22 4>; + local-mac-address = [00 0a 35 00 00 00]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + reg = <0xe000b000 0x1000>; + xlnx,eth-mode = <0x1>; + xlnx,has-mdio = <0x1>; + xlnx,ptp-enet-clock = <111111115>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@0 { + compatible = "marvell,88e1510"; + device_type = "ethernet-phy"; + reg = <0>; + } ; + } ; + } ; + ps7_gpio_0: ps7-gpio@e000a000 { + #gpio-cells = <2>; + clocks = <&clkc 42>; + compatible = "xlnx,ps7-gpio-1.00.a"; + emio-gpio-width = <64>; + gpio-controller ; + gpio-mask-high = <0xc0000>; + gpio-mask-low = <0xfe81>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + } ; + ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { + compatible = "xlnx,ps7-iop-bus-config-1.00.a"; + reg = <0xe0200000 0x1000>; + } ; + ps7_ocmc_0: ps7-ocmc@f800c000 { + compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; + } ; + ps7_pl310_0: ps7-pl310@f8f02000 { + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-level = <2>; + cache-unified ; + compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + } ; + ps7_qspi_0: ps7-qspi@e000d000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 19 4>; + is-dual = <0>; + num-chip-select = <1>; + reg = <0xe000d000 0x1000>; + xlnx,fb-clk = <0x1>; + xlnx,qspi-mode = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "n25q128"; + reg = <0x0>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; -&uart1 { - status = "okay"; -}; + } ; + ps7_qspi_linear_0: ps7-qspi-linear@fc000000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 10>, <&clkc 43>; + compatible = "xlnx,ps7-qspi-linear-1.00.a"; + reg = <0xfc000000 0x1000000>; + } ; + ps7_scugic_0: ps7-scugic@f8f01000 { + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <1>; + compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic"; + interrupt-controller ; + num_cpus = <2>; + num_interrupts = <96>; + reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; + } ; + ps7_scutimer_0: ps7-scutimer@f8f00600 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 13 0x301>; + reg = <0xf8f00600 0x20>; + } ; + ps7_scuwdt_0: ps7-scuwdt@f8f00620 { + clocks = <&clkc 4>; + compatible = "xlnx,ps7-scuwdt-1.00.a"; + device_type = "watchdog"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <1 14 0x301>; + reg = <0xf8f00620 0xe0>; + } ; + ps7_sd_0: ps7-sdio@e0100000 { + clock-frequency = <50000000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + compatible = "xlnx,ps7-sdio-1.00.a", "generic-sdhci", "arasan,sdhci-8.9a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + xlnx,has-cd = <0x1>; + xlnx,has-power = <0x0>; + xlnx,has-wp = <0x1>; + } ; + ps7_slcr_0: ps7-slcr@f8000000 { + compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr"; + reg = <0xf8000000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clkc: clkc { + #clock-cells = <1>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", + "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", + "can1", "sdio0", "sdio1", "uart0", "uart1", + "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", + "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", + "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", + "swdt", "dbg_trc", "dbg_apb"; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; + } ; + } ; + } ; + ps7_ttc_0: ps7-ttc@f8001000 { + clocks = <&clkc 6>; + compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc"; + interrupt-names = "ttc0", "ttc1", "ttc2"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + reg = <0xf8001000 0x1000>; + } ; + ps7_uart_1: serial@e0001000 { + clock-names = "ref_clk", "aper_clk"; + clocks = <&clkc 24>, <&clkc 41>; + compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps"; + current-speed = <115200>; + device_type = "serial"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 50 4>; + port-number = <0>; + reg = <0xe0001000 0x1000>; + xlnx,has-modem = <0x0>; + } ; + ps7_usb_0: ps7-usb@e0002000 { + clocks = <&clkc 28>; + compatible = "xlnx,ps7-usb-1.00.a"; + dr_mode = "host"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 21 4>; + phy_type = "ulpi"; + reg = <0xe0002000 0x1000>; + } ; + ps7_xadc: ps7-xadc@f8007100 { + clocks = <&clkc 12>; + compatible = "xlnx,ps7-xadc-1.00.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 7 4>; + reg = <0xf8007100 0x20>; + } ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/arm/configs/xilinx_zynq_apf_defconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/configs/xilinx_zynq_apf_defconfig 2014-07-20 22:06:34.025344167 +0200 @@ -0,0 +1,3043 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.12.0 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_NO_IOPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="arm-xilinx-linux-gnueabi-" +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="-xilinx-trd" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_FHANDLE is not set +# CONFIG_AUDIT is not set + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_KTIME_SCALAR=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_USER_QS is not set +CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +# CONFIG_RCU_NOCB_CPU is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_PCI_QUIRKS=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_BCM is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_SHMOBILE_MULTI is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_ARCH_VEXPRESS=y + +# +# Versatile Express platform type +# +CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y +# CONFIG_ARCH_VEXPRESS_CA9X4 is not set +CONFIG_PLAT_VERSATILE_CLCD=y +CONFIG_PLAT_VERSATILE_SCHED_CLOCK=y +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_WM8850 is not set +CONFIG_ARCH_ZYNQ=y + +# +# Xilinx Specific Options +# +CONFIG_XILINX_L1_PREFETCH=y +CONFIG_XILINX_L2_PREFETCH=y +CONFIG_XILINX_AXIPCIE=y +CONFIG_PLAT_VERSATILE=y +CONFIG_ARM_TIMER_SP804=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +CONFIG_PL310_ERRATA_588369=y +# CONFIG_ARM_ERRATA_643719 is not set +CONFIG_ARM_ERRATA_720789=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_ERRATA_775420=y +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_ERRATA_773022 is not set +CONFIG_ICST=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set + +# +# PCI host controller drivers +# +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_HAVE_ARM_SCU=y +# CONFIG_HAVE_ARM_ARCH_TIMER is not set +CONFIG_HAVE_ARM_TWD=y +# CONFIG_MCPM is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=4 +CONFIG_HOTPLUG_CPU=y +# CONFIG_ARM_PSCI is not set +CONFIG_ARCH_NR_GPIO=1024 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_ZBUD is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_XEN is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +# CONFIG_ARM_APPENDED_DTB is not set +CONFIG_CMDLINE="console=ttyPS0,115200n8 root=/dev/ram rw initrd=0x00800000,16M earlyprintk mtdparts=physmap-flash.0:512K(nor-fsbl),512K(nor-u-boot),5M(nor-linux),9M(nor-user),1M(nor-scratch),-(nor-rootfs)" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + +# +# ARM CPU frequency scaling drivers +# +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_ZYNQ_CPUFREQ=y + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +# CONFIG_KERNEL_MODE_NEON is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_HAS_OPP=y +CONFIG_PM_OPP=y +CONFIG_PM_CLK=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=m +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_GRE is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_MMAP is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_NET_MPLS_GSO is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +CONFIG_HAVE_BPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 + +# +# Bus devices +# +# CONFIG_ARM_CCI is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_M25PXX_USE_FAST_READ is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_DENALI is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_DOCG4 is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_NAND_ZYNQ=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# +CONFIG_PROC_DEVICETREE=y +# CONFIG_OF_SELFTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_MTD=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_VIRTIO_BLK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_ARM_CHARLCD is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +CONFIG_SI570=y +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_SCSI_BNX2X_FCOE is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_VIRTIO is not set +# CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_HAVE_PATA_PLATFORM=y +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_VIRTIO_NET is not set +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +CONFIG_NET_VENDOR_ARC=y +# CONFIG_ARC_EMAC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +CONFIG_NET_CADENCE=y +# CONFIG_ARM_AT91_ETHER is not set +# CONFIG_MACB is not set +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +CONFIG_TIGON3=y +# CONFIG_BNX2X is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_NET_VENDOR_INTEL=y +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +CONFIG_E1000E=y +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_I40E is not set +CONFIG_NET_VENDOR_I825XX=y +# CONFIG_IP1000 is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +CONFIG_R8169=y +# CONFIG_SH_ETH is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_SFC is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_XILINX=y +CONFIG_XILINX_EMACLITE=y +CONFIG_XILINX_AXI_EMAC=y +CONFIG_XILINX_PS_EMAC=y +# CONFIG_XILINX_PS_EMAC_HWTSTAMP is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AT803X_PHY is not set +# CONFIG_AMD_PHY is not set +CONFIG_MARVELL_PHY=y +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +CONFIG_VITESSE_PHY=y +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +CONFIG_MDIO_BITBANG=y +# CONFIG_MDIO_GPIO is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set +# CONFIG_WL_TI is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_OLPC_APSP is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_MFD_HSU is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_PCH_UART is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +CONFIG_XILINX_DEVCFG=y +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_PCA9541 is not set +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_VERSATILE is not set +CONFIG_I2C_ZYNQ=y +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_FSL_DSPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI_ZYNQ_QSPI=y +# CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED is not set +CONFIG_SPI_ZYNQ=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_HSI is not set + +# +# PPS support +# +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_TS5500 is not set +CONFIG_GPIO_XILINX=y +CONFIG_GPIO_ZYNQ=y +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_GRGPIO is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# LPC GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# + +# +# USB GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_SMB347 is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_RESTART is not set +CONFIG_POWER_RESET_VEXPRESS=y +# CONFIG_POWER_AVS is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VEXPRESS is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_XADCPS=y +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +CONFIG_ZYNQ_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_MEN_A21_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_VEXPRESS_CONFIG=y +# CONFIG_REGULATOR is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_RC_SUPPORT is not set +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_V4L2=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_V4L2_INT_DEVICE is not set +# CONFIG_TTPCI_EEPROM is not set + +# +# Media drivers +# +# CONFIG_MEDIA_USB_SUPPORT is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_TIMBERDALE is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_VIDEO_XILINX is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set + +# +# Supported MMC/SDIO adapters +# +# CONFIG_CYPRESS_FIRMWARE is not set + +# +# Media ancillary drivers (tuners, sensors, i2c, frontends) +# +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set + +# +# Encoders, decoders, sensors and other helper chips +# + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +CONFIG_VIDEO_ADV7604=y +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +CONFIG_VIDEO_ADV7511=y +# CONFIG_VIDEO_AD9389B is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_THS8200 is not set + +# +# Camera sensor devices +# +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_S5C73M3 is not set + +# +# Flash devices +# +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_AS3645A is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set + +# +# Miscelaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set + +# +# Sensors used on soc_camera driver +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_DRM is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_XILINX is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_SIMPLE is not set +CONFIG_FB_XYLON=y +# CONFIG_FB_XYLON_PLATFORM is not set +CONFIG_FB_XYLON_OF=y +CONFIG_FB_XYLON_PIXCLK=y +# CONFIG_FB_XYLON_PIXCLK_ZYNQ_PS is not set +# CONFIG_FB_XYLON_PIXCLK_LOGICLK is not set +CONFIG_FB_XYLON_PIXCLK_SI570=y +CONFIG_FB_XYLON_MISC=y +CONFIG_FB_XYLON_MISC_ADV7511=y +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_LOGO is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_SOUND is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_HUION is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO_TPKBD is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +CONFIG_HID_MICROSOFT=y +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_XUSBPS_DR_OF=y +CONFIG_USB_EHCI_XUSBPS=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FUSBH200_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_CHIPIDEA is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_RCAR_PHY is not set +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y +# CONFIG_USB_ZYNQ_PHY is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 + +# +# USB Peripheral Controller +# +CONFIG_USB_GADGET_XUSBPS=y +CONFIG_XUSBPS_ERRATA_DT654401=y +CONFIG_USB_XUSBPS=y +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_SS_LB=m +# CONFIG_USB_CONFIGFS is not set +CONFIG_USB_ZERO=m +# CONFIG_USB_ZERO_HNPTEST is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_MM_EDAC=y +CONFIG_EDAC_ZYNQ=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +CONFIG_RTC_DRV_PCF8563=y +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_RX4581 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_DS2404 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_MOXART is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_XILINX_DMA_ENGINES=y +CONFIG_XILINX_AXIDMA=y +# CONFIG_XILINX_DMATEST is not set +CONFIG_XILINX_AXIVDMA=y +# CONFIG_XILINX_VDMATEST is not set +CONFIG_XILINX_AXICDMA=y +# CONFIG_XILINX_CDMATEST is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_TIMB_DMA is not set +CONFIG_PL330_DMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +# CONFIG_UIO_CIF is not set +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_AEC is not set +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_UIO_PCI_GENERIC is not set +# CONFIG_UIO_NETX is not set +# CONFIG_UIO_MF624 is not set +# CONFIG_UIO_XILINX_APM is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO=m + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_ET131X is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_ECHO is not set +# CONFIG_COMEDI is not set +# CONFIG_R8187SE is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTLLIB is not set +# CONFIG_R8712U is not set +# CONFIG_R8188EU is not set +# CONFIG_RTS5139 is not set +# CONFIG_TRANZPORT is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set +# CONFIG_DX_SEP is not set +# CONFIG_ZSMALLOC is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_CRYSTALHD is not set +# CONFIG_FB_XGI is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_STAGING_MEDIA is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_USB_WPAN_HCD is not set +# CONFIG_WIMAX_GDM72XX is not set +# CONFIG_LTE_GDM724X is not set +CONFIG_NET_VENDOR_SILICOM=y +# CONFIG_SBYPASS is not set +# CONFIG_BPCTL is not set +# CONFIG_CED1401 is not set +# CONFIG_DGRP is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_LUSTRE_FS is not set +# CONFIG_XILLYBUS is not set +# CONFIG_DGNC is not set +# CONFIG_DGAP is not set +CONFIG_XILINX_VIDEO_IP=y +CONFIG_XILINX_VDMA_WRAPPER=y +CONFIG_XILINX_APF=y +CONFIG_XILINX_DMA_APF=y +# CONFIG_PMODS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +CONFIG_COMMON_CLK_DEBUG=y +CONFIG_COMMON_CLK_VERSATILE=y +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CADENCE_TTC_TIMER=y +# CONFIG_MAILBOX is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_OF_IOMMU=y + +# +# Remoteproc drivers +# +CONFIG_REMOTEPROC=m +# CONFIG_STE_MODEM_RPROC is not set +CONFIG_ZYNQ_REMOTEPROC=m +CONFIG_MB_REMOTEPROC=m + +# +# Rpmsg drivers +# +CONFIG_RPMSG=m +# CONFIG_RPMSG_SERVER_SAMPLE is not set +# CONFIG_RPMSG_OMX is not set +# CONFIG_RPMSG_FREERTOS_STAT is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +CONFIG_MEMORY=y +CONFIG_ZYNQ_SMC=y +# CONFIG_IIO is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_F2FS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU_DELAY is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_CPU_STALL_VERBOSE is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ZYNQ_UART0 is not set +CONFIG_DEBUG_ZYNQ_UART1=y +# CONFIG_DEBUG_VEXPRESS_UART0_DETECT is not set +# CONFIG_DEBUG_VEXPRESS_UART0_CA9 is not set +# CONFIG_DEBUG_VEXPRESS_UART0_RS1 is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +CONFIG_DEBUG_LL_INCLUDE="debug/zynq.S" +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_EARLY_PRINTK=y +# CONFIG_OC_ETM is not set +# CONFIG_PID_IN_CONTEXTIDR is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=m +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +CONFIG_FONT_SUPPORT=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_VIRTUALIZATION=y Index: linux-3.12.24-rt38-xilinx/arch/arm/configs/xilinx_zynq_base_trd_defconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/configs/xilinx_zynq_base_trd_defconfig 2014-07-20 22:06:34.056343656 +0200 @@ -0,0 +1,3031 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.12.0 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_NO_IOPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="-xilinx-trd" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_FHANDLE is not set +# CONFIG_AUDIT is not set + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_KTIME_SCALAR=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_USER_QS is not set +CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +# CONFIG_RCU_NOCB_CPU is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_PCI_QUIRKS=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_BCM is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_SHMOBILE_MULTI is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_ARCH_VEXPRESS=y + +# +# Versatile Express platform type +# +CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y +# CONFIG_ARCH_VEXPRESS_CA9X4 is not set +CONFIG_PLAT_VERSATILE_CLCD=y +CONFIG_PLAT_VERSATILE_SCHED_CLOCK=y +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_WM8850 is not set +CONFIG_ARCH_ZYNQ=y + +# +# Xilinx Specific Options +# +CONFIG_XILINX_L1_PREFETCH=y +CONFIG_XILINX_L2_PREFETCH=y +CONFIG_XILINX_AXIPCIE=y +CONFIG_PLAT_VERSATILE=y +CONFIG_ARM_TIMER_SP804=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +CONFIG_PL310_ERRATA_588369=y +# CONFIG_ARM_ERRATA_643719 is not set +CONFIG_ARM_ERRATA_720789=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_ERRATA_775420=y +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_ERRATA_773022 is not set +CONFIG_ICST=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set + +# +# PCI host controller drivers +# +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_HAVE_ARM_SCU=y +# CONFIG_HAVE_ARM_ARCH_TIMER is not set +CONFIG_HAVE_ARM_TWD=y +# CONFIG_MCPM is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=4 +CONFIG_HOTPLUG_CPU=y +# CONFIG_ARM_PSCI is not set +CONFIG_ARCH_NR_GPIO=1024 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_ZBUD is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_XEN is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +# CONFIG_ARM_APPENDED_DTB is not set +CONFIG_CMDLINE="console=ttyPS0,115200n8 root=/dev/ram rw initrd=0x00800000,16M earlyprintk mtdparts=physmap-flash.0:512K(nor-fsbl),512K(nor-u-boot),5M(nor-linux),9M(nor-user),1M(nor-scratch),-(nor-rootfs)" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + +# +# ARM CPU frequency scaling drivers +# +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_ZYNQ_CPUFREQ=y + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +# CONFIG_KERNEL_MODE_NEON is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_HAS_OPP=y +CONFIG_PM_OPP=y +CONFIG_PM_CLK=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=m +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_GRE is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_MMAP is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_NET_MPLS_GSO is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +CONFIG_HAVE_BPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_DMA_CMA is not set + +# +# Bus devices +# +# CONFIG_ARM_CCI is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_M25PXX_USE_FAST_READ is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_DENALI is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_DOCG4 is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_NAND_ZYNQ=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# +CONFIG_PROC_DEVICETREE=y +# CONFIG_OF_SELFTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_MTD=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_VIRTIO_BLK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_ARM_CHARLCD is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +CONFIG_SI570=y +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_SCSI_BNX2X_FCOE is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_VIRTIO is not set +# CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_HAVE_PATA_PLATFORM=y +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_VIRTIO_NET is not set +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +CONFIG_NET_VENDOR_ARC=y +# CONFIG_ARC_EMAC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +CONFIG_NET_CADENCE=y +# CONFIG_ARM_AT91_ETHER is not set +# CONFIG_MACB is not set +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +CONFIG_TIGON3=y +# CONFIG_BNX2X is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_NET_VENDOR_INTEL=y +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +CONFIG_E1000E=y +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_I40E is not set +CONFIG_NET_VENDOR_I825XX=y +# CONFIG_IP1000 is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +CONFIG_R8169=y +# CONFIG_SH_ETH is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_SFC is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_XILINX=y +CONFIG_XILINX_EMACLITE=y +CONFIG_XILINX_AXI_EMAC=y +CONFIG_XILINX_PS_EMAC=y +# CONFIG_XILINX_PS_EMAC_HWTSTAMP is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AT803X_PHY is not set +# CONFIG_AMD_PHY is not set +CONFIG_MARVELL_PHY=y +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +CONFIG_VITESSE_PHY=y +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +CONFIG_MDIO_BITBANG=y +# CONFIG_MDIO_GPIO is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set +# CONFIG_WL_TI is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_OLPC_APSP is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_MFD_HSU is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_PCH_UART is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +CONFIG_XILINX_DEVCFG=y +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_PCA9541 is not set +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_VERSATILE is not set +CONFIG_I2C_ZYNQ=y +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_FSL_DSPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI_ZYNQ_QSPI=y +# CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED is not set +CONFIG_SPI_ZYNQ=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_HSI is not set + +# +# PPS support +# +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_TS5500 is not set +CONFIG_GPIO_XILINX=y +CONFIG_GPIO_ZYNQ=y +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_GRGPIO is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# LPC GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# + +# +# USB GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_SMB347 is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_RESTART is not set +CONFIG_POWER_RESET_VEXPRESS=y +# CONFIG_POWER_AVS is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VEXPRESS is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_XADCPS=y +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +CONFIG_ZYNQ_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_MEN_A21_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_VEXPRESS_CONFIG=y +# CONFIG_REGULATOR is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_RC_SUPPORT is not set +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_V4L2=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_V4L2_INT_DEVICE is not set +# CONFIG_TTPCI_EEPROM is not set + +# +# Media drivers +# +# CONFIG_MEDIA_USB_SUPPORT is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_TIMBERDALE is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_VIDEO_XILINX is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set + +# +# Supported MMC/SDIO adapters +# +# CONFIG_CYPRESS_FIRMWARE is not set + +# +# Media ancillary drivers (tuners, sensors, i2c, frontends) +# +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set + +# +# Encoders, decoders, sensors and other helper chips +# + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +CONFIG_VIDEO_ADV7604=y +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +CONFIG_VIDEO_ADV7511=y +# CONFIG_VIDEO_AD9389B is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_THS8200 is not set + +# +# Camera sensor devices +# +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_S5C73M3 is not set + +# +# Flash devices +# +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_AS3645A is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set + +# +# Miscelaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set + +# +# Sensors used on soc_camera driver +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_DRM is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_XILINX is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_SIMPLE is not set +CONFIG_FB_XYLON=y +# CONFIG_FB_XYLON_PLATFORM is not set +CONFIG_FB_XYLON_OF=y +CONFIG_FB_XYLON_PIXCLK=y +# CONFIG_FB_XYLON_PIXCLK_ZYNQ_PS is not set +# CONFIG_FB_XYLON_PIXCLK_LOGICLK is not set +CONFIG_FB_XYLON_PIXCLK_SI570=y +CONFIG_FB_XYLON_MISC=y +CONFIG_FB_XYLON_MISC_ADV7511=y +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_LOGO is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_SOUND is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_HUION is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO_TPKBD is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +CONFIG_HID_MICROSOFT=y +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_XUSBPS_DR_OF=y +CONFIG_USB_EHCI_XUSBPS=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FUSBH200_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_CHIPIDEA is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_RCAR_PHY is not set +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y +# CONFIG_USB_ZYNQ_PHY is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 + +# +# USB Peripheral Controller +# +CONFIG_USB_GADGET_XUSBPS=y +CONFIG_XUSBPS_ERRATA_DT654401=y +CONFIG_USB_XUSBPS=y +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_SS_LB=m +# CONFIG_USB_CONFIGFS is not set +CONFIG_USB_ZERO=m +# CONFIG_USB_ZERO_HNPTEST is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_MM_EDAC=y +CONFIG_EDAC_ZYNQ=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +CONFIG_RTC_DRV_PCF8563=y +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_RX4581 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_DS2404 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_MOXART is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_XILINX_DMA_ENGINES=y +CONFIG_XILINX_AXIDMA=y +# CONFIG_XILINX_DMATEST is not set +CONFIG_XILINX_AXIVDMA=y +# CONFIG_XILINX_VDMATEST is not set +CONFIG_XILINX_AXICDMA=y +# CONFIG_XILINX_CDMATEST is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_TIMB_DMA is not set +CONFIG_PL330_DMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +# CONFIG_UIO_CIF is not set +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_AEC is not set +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_UIO_PCI_GENERIC is not set +# CONFIG_UIO_NETX is not set +# CONFIG_UIO_MF624 is not set +# CONFIG_UIO_XILINX_APM is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO=m + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_ET131X is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_ECHO is not set +# CONFIG_COMEDI is not set +# CONFIG_R8187SE is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTLLIB is not set +# CONFIG_R8712U is not set +# CONFIG_R8188EU is not set +# CONFIG_RTS5139 is not set +# CONFIG_TRANZPORT is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set +# CONFIG_DX_SEP is not set +# CONFIG_ZSMALLOC is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_CRYSTALHD is not set +# CONFIG_FB_XGI is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_STAGING_MEDIA is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_USB_WPAN_HCD is not set +# CONFIG_WIMAX_GDM72XX is not set +# CONFIG_LTE_GDM724X is not set +CONFIG_NET_VENDOR_SILICOM=y +# CONFIG_SBYPASS is not set +# CONFIG_BPCTL is not set +# CONFIG_CED1401 is not set +# CONFIG_DGRP is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_LUSTRE_FS is not set +# CONFIG_XILLYBUS is not set +# CONFIG_DGNC is not set +# CONFIG_DGAP is not set +CONFIG_XILINX_VIDEO_IP=y +CONFIG_XILINX_VDMA_WRAPPER=y +# CONFIG_XILINX_APF is not set +# CONFIG_PMODS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +CONFIG_COMMON_CLK_DEBUG=y +CONFIG_COMMON_CLK_VERSATILE=y +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CADENCE_TTC_TIMER=y +# CONFIG_MAILBOX is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_OF_IOMMU=y + +# +# Remoteproc drivers +# +CONFIG_REMOTEPROC=m +# CONFIG_STE_MODEM_RPROC is not set +CONFIG_ZYNQ_REMOTEPROC=m +CONFIG_MB_REMOTEPROC=m + +# +# Rpmsg drivers +# +CONFIG_RPMSG=m +# CONFIG_RPMSG_SERVER_SAMPLE is not set +# CONFIG_RPMSG_OMX is not set +# CONFIG_RPMSG_FREERTOS_STAT is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +CONFIG_MEMORY=y +CONFIG_ZYNQ_SMC=y +# CONFIG_IIO is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_F2FS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU_DELAY is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_CPU_STALL_VERBOSE is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ZYNQ_UART0 is not set +CONFIG_DEBUG_ZYNQ_UART1=y +# CONFIG_DEBUG_VEXPRESS_UART0_DETECT is not set +# CONFIG_DEBUG_VEXPRESS_UART0_CA9 is not set +# CONFIG_DEBUG_VEXPRESS_UART0_RS1 is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +CONFIG_DEBUG_LL_INCLUDE="debug/zynq.S" +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_EARLY_PRINTK=y +# CONFIG_OC_ETM is not set +# CONFIG_PID_IN_CONTEXTIDR is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=m +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +CONFIG_FONT_SUPPORT=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_VIRTUALIZATION=y Index: linux-3.12.24-rt38-xilinx/arch/arm/configs/xilinx_zynq_defconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/configs/xilinx_zynq_defconfig 2014-07-20 22:06:34.086343161 +0200 @@ -0,0 +1,2860 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.12.0 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_NO_IOPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="-xilinx" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_FHANDLE is not set +# CONFIG_AUDIT is not set + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_KTIME_SCALAR=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_USER_QS is not set +CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +# CONFIG_RCU_NOCB_CPU is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_PCI_QUIRKS=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_SHMOBILE_MULTI is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_ARCH_VEXPRESS=y + +# +# Versatile Express platform type +# +CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y +# CONFIG_ARCH_VEXPRESS_CA9X4 is not set +CONFIG_PLAT_VERSATILE_CLCD=y +CONFIG_PLAT_VERSATILE_SCHED_CLOCK=y +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_WM8850 is not set +CONFIG_ARCH_ZYNQ=y + +# +# Xilinx Specific Options +# +CONFIG_XILINX_L1_PREFETCH=y +CONFIG_XILINX_L2_PREFETCH=y +CONFIG_XILINX_AXIPCIE=y +CONFIG_PLAT_VERSATILE=y +CONFIG_ARM_TIMER_SP804=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +CONFIG_PL310_ERRATA_588369=y +# CONFIG_ARM_ERRATA_643719 is not set +CONFIG_ARM_ERRATA_720789=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_ERRATA_775420=y +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_ERRATA_773022 is not set +CONFIG_ICST=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set + +# +# PCI host controller drivers +# +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_HAVE_ARM_SCU=y +# CONFIG_HAVE_ARM_ARCH_TIMER is not set +CONFIG_HAVE_ARM_TWD=y +# CONFIG_MCPM is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=4 +CONFIG_HOTPLUG_CPU=y +# CONFIG_ARM_PSCI is not set +CONFIG_ARCH_NR_GPIO=1024 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_ZBUD is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_XEN is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +# CONFIG_ARM_APPENDED_DTB is not set +CONFIG_CMDLINE="console=ttyPS0,115200n8 root=/dev/ram rw initrd=0x00800000,16M earlyprintk mtdparts=physmap-flash.0:512K(nor-fsbl),512K(nor-u-boot),5M(nor-linux),9M(nor-user),1M(nor-scratch),-(nor-rootfs)" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + +# +# ARM CPU frequency scaling drivers +# +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_ZYNQ_CPUFREQ=y + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +# CONFIG_KERNEL_MODE_NEON is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_HAS_OPP=y +CONFIG_PM_OPP=y +CONFIG_PM_CLK=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_CPU_PM=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=m +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_GRE is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_MMAP is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_NET_MPLS_GSO is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +CONFIG_HAVE_BPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_DMA_CMA is not set + +# +# Bus devices +# +# CONFIG_ARM_CCI is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_M25PXX_USE_FAST_READ is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_DENALI is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_DOCG4 is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_NAND_ZYNQ=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# +CONFIG_PROC_DEVICETREE=y +# CONFIG_OF_SELFTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_MTD=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_VIRTIO_BLK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_ARM_CHARLCD is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_SI570 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_SCSI_BNX2X_FCOE is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_VIRTIO is not set +# CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_HAVE_PATA_PLATFORM=y +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_VIRTIO_NET is not set +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +CONFIG_NET_VENDOR_ARC=y +# CONFIG_ARC_EMAC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +CONFIG_NET_CADENCE=y +# CONFIG_ARM_AT91_ETHER is not set +CONFIG_MACB=y +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +CONFIG_TIGON3=y +# CONFIG_BNX2X is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_NET_VENDOR_INTEL=y +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +CONFIG_E1000E=y +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_I40E is not set +CONFIG_NET_VENDOR_I825XX=y +# CONFIG_IP1000 is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +CONFIG_R8169=y +# CONFIG_SH_ETH is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_SFC is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_XILINX=y +CONFIG_XILINX_EMACLITE=y +CONFIG_XILINX_AXI_EMAC=y +CONFIG_XILINX_PS_EMAC=y +# CONFIG_XILINX_PS_EMAC_HWTSTAMP is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AT803X_PHY is not set +# CONFIG_AMD_PHY is not set +CONFIG_MARVELL_PHY=y +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +CONFIG_VITESSE_PHY=y +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +CONFIG_MDIO_BITBANG=y +# CONFIG_MDIO_GPIO is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set +# CONFIG_WL_TI is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_OLPC_APSP is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_MFD_HSU is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_PCH_UART is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +CONFIG_XILINX_DEVCFG=y +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_PCA9541 is not set +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_VERSATILE is not set +CONFIG_I2C_ZYNQ=y +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_FSL_DSPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +CONFIG_SPI_XILINX=y +CONFIG_SPI_ZYNQ_QSPI=y +# CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED is not set +CONFIG_SPI_ZYNQ=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_HSI is not set + +# +# PPS support +# +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_TS5500 is not set +CONFIG_GPIO_XILINX=y +CONFIG_GPIO_ZYNQ=y +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_GRGPIO is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# LPC GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# + +# +# USB GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_SMB347 is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_RESTART is not set +CONFIG_POWER_RESET_VEXPRESS=y +# CONFIG_POWER_AVS is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VEXPRESS is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_XADCPS=y +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +CONFIG_ZYNQ_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set +CONFIG_XILINX_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_VEXPRESS_CONFIG=y +# CONFIG_REGULATOR is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +# CONFIG_MEDIA_CAMERA_SUPPORT is not set +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_RC_SUPPORT is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_TTPCI_EEPROM is not set + +# +# Media drivers +# +# CONFIG_MEDIA_USB_SUPPORT is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set + +# +# Supported MMC/SDIO adapters +# +# CONFIG_CYPRESS_FIRMWARE is not set + +# +# Media ancillary drivers (tuners, sensors, i2c, frontends) +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_DRM is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_XILINX is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_SIMPLE is not set +CONFIG_FB_XYLON=y +# CONFIG_FB_XYLON_PLATFORM is not set +CONFIG_FB_XYLON_OF=y +# CONFIG_FB_XYLON_PIXCLK is not set +# CONFIG_FB_XYLON_MISC is not set +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_LOGO is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_SOUND is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_HUION is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO_TPKBD is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +CONFIG_HID_MICROSOFT=y +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_XUSBPS_DR_OF=y +CONFIG_USB_EHCI_XUSBPS=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FUSBH200_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_CHIPIDEA is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_RCAR_PHY is not set +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y +# CONFIG_USB_ZYNQ_PHY is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 + +# +# USB Peripheral Controller +# +CONFIG_USB_GADGET_XUSBPS=y +CONFIG_XUSBPS_ERRATA_DT654401=y +CONFIG_USB_XUSBPS=y +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_R8A66597 is not set +CONFIG_USB_GADGET_XILINX=y +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_SS_LB=m +# CONFIG_USB_CONFIGFS is not set +CONFIG_USB_ZERO=m +# CONFIG_USB_ZERO_HNPTEST is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_MM_EDAC=y +CONFIG_EDAC_ZYNQ=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +CONFIG_RTC_DRV_PCF8563=y +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_RX4581 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_DS2404 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_MOXART is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_XILINX_DMA_ENGINES=y +CONFIG_XILINX_AXIDMA=y +# CONFIG_XILINX_DMATEST is not set +CONFIG_XILINX_AXIVDMA=y +# CONFIG_XILINX_VDMATEST is not set +CONFIG_XILINX_AXICDMA=y +# CONFIG_XILINX_CDMATEST is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_TIMB_DMA is not set +CONFIG_PL330_DMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +# CONFIG_UIO_CIF is not set +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_AEC is not set +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_UIO_PCI_GENERIC is not set +# CONFIG_UIO_NETX is not set +# CONFIG_UIO_MF624 is not set +CONFIG_UIO_XILINX_APM=y +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO=m + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +CONFIG_COMMON_CLK_DEBUG=y +CONFIG_COMMON_CLK_VERSATILE=y +# CONFIG_COMMON_CLK_SI5351 is not set +CONFIG_COMMON_CLK_SI570=y +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CADENCE_TTC_TIMER=y +# CONFIG_MAILBOX is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_OF_IOMMU=y + +# +# Remoteproc drivers +# +CONFIG_REMOTEPROC=m +# CONFIG_STE_MODEM_RPROC is not set +CONFIG_ZYNQ_REMOTEPROC=m +CONFIG_MB_REMOTEPROC=m + +# +# Rpmsg drivers +# +CONFIG_RPMSG=m +# CONFIG_RPMSG_SERVER_SAMPLE is not set +# CONFIG_RPMSG_OMX is not set +# CONFIG_RPMSG_FREERTOS_STAT is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +CONFIG_MEMORY=y +CONFIG_ZYNQ_SMC=y +# CONFIG_IIO is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_F2FS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU_DELAY is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_CPU_STALL_VERBOSE is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ZYNQ_UART0 is not set +CONFIG_DEBUG_ZYNQ_UART1=y +# CONFIG_DEBUG_VEXPRESS_UART0_DETECT is not set +# CONFIG_DEBUG_VEXPRESS_UART0_CA9 is not set +# CONFIG_DEBUG_VEXPRESS_UART0_RS1 is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +CONFIG_DEBUG_LL_INCLUDE="debug/zynq.S" +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_EARLY_PRINTK=y +# CONFIG_OC_ETM is not set +# CONFIG_PID_IN_CONTEXTIDR is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=m +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +CONFIG_FONT_SUPPORT=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_VIRTUALIZATION=y Index: linux-3.12.24-rt38-xilinx/arch/arm/configs/xilinx_zynq_drm_defconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/configs/xilinx_zynq_drm_defconfig 2014-07-20 22:06:34.116342666 +0200 @@ -0,0 +1,3065 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.12.0 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_NO_IOPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="-xilinx-drm" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_FHANDLE is not set +# CONFIG_AUDIT is not set + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_KTIME_SCALAR=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_USER_QS is not set +CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +# CONFIG_RCU_NOCB_CPU is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_PCI_QUIRKS=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_SHMOBILE_MULTI is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_ARCH_VEXPRESS=y + +# +# Versatile Express platform type +# +CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y +# CONFIG_ARCH_VEXPRESS_CA9X4 is not set +CONFIG_PLAT_VERSATILE_CLCD=y +CONFIG_PLAT_VERSATILE_SCHED_CLOCK=y +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_WM8850 is not set +CONFIG_ARCH_ZYNQ=y + +# +# Xilinx Specific Options +# +CONFIG_XILINX_L1_PREFETCH=y +CONFIG_XILINX_L2_PREFETCH=y +CONFIG_XILINX_AXIPCIE=y +CONFIG_PLAT_VERSATILE=y +CONFIG_ARM_TIMER_SP804=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +CONFIG_PL310_ERRATA_588369=y +# CONFIG_ARM_ERRATA_643719 is not set +CONFIG_ARM_ERRATA_720789=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_ERRATA_775420=y +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_ERRATA_773022 is not set +CONFIG_ICST=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set + +# +# PCI host controller drivers +# +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_HAVE_ARM_SCU=y +# CONFIG_HAVE_ARM_ARCH_TIMER is not set +CONFIG_HAVE_ARM_TWD=y +# CONFIG_MCPM is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=4 +CONFIG_HOTPLUG_CPU=y +# CONFIG_ARM_PSCI is not set +CONFIG_ARCH_NR_GPIO=1024 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_ZBUD is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_XEN is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +# CONFIG_ARM_APPENDED_DTB is not set +CONFIG_CMDLINE="console=ttyPS0,115200n8 root=/dev/ram rw initrd=0x00800000,16M earlyprintk mtdparts=physmap-flash.0:512K(nor-fsbl),512K(nor-u-boot),5M(nor-linux),9M(nor-user),1M(nor-scratch),-(nor-rootfs)" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + +# +# ARM CPU frequency scaling drivers +# +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_ZYNQ_CPUFREQ=y + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +# CONFIG_KERNEL_MODE_NEON is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_HAS_OPP=y +CONFIG_PM_OPP=y +CONFIG_PM_CLK=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_CPU_PM=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=m +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_GRE is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_MMAP is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_NET_MPLS_GSO is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +CONFIG_HAVE_BPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=128 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 + +# +# Bus devices +# +# CONFIG_ARM_CCI is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_M25PXX_USE_FAST_READ is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_DENALI is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_DOCG4 is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_NAND_ZYNQ=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# +CONFIG_PROC_DEVICETREE=y +# CONFIG_OF_SELFTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_MTD=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_VIRTIO_BLK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_ARM_CHARLCD is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_SI570 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_SCSI_BNX2X_FCOE is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_VIRTIO is not set +# CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_HAVE_PATA_PLATFORM=y +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_VIRTIO_NET is not set +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +CONFIG_NET_VENDOR_ARC=y +# CONFIG_ARC_EMAC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +CONFIG_NET_CADENCE=y +# CONFIG_ARM_AT91_ETHER is not set +CONFIG_MACB=y +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +CONFIG_TIGON3=y +# CONFIG_BNX2X is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_NET_VENDOR_INTEL=y +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +CONFIG_E1000E=y +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_I40E is not set +CONFIG_NET_VENDOR_I825XX=y +# CONFIG_IP1000 is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +CONFIG_R8169=y +# CONFIG_SH_ETH is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_SFC is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_XILINX=y +CONFIG_XILINX_EMACLITE=y +CONFIG_XILINX_AXI_EMAC=y +CONFIG_XILINX_PS_EMAC=y +# CONFIG_XILINX_PS_EMAC_HWTSTAMP is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AT803X_PHY is not set +# CONFIG_AMD_PHY is not set +CONFIG_MARVELL_PHY=y +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +CONFIG_VITESSE_PHY=y +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +CONFIG_MDIO_BITBANG=y +# CONFIG_MDIO_GPIO is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set +# CONFIG_WL_TI is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_OLPC_APSP is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_MFD_HSU is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_PCH_UART is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +CONFIG_XILINX_DEVCFG=y +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_PCA9541 is not set +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_VERSATILE is not set +CONFIG_I2C_ZYNQ=y +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_FSL_DSPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +CONFIG_SPI_XILINX=y +CONFIG_SPI_ZYNQ_QSPI=y +# CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED is not set +CONFIG_SPI_ZYNQ=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_HSI is not set + +# +# PPS support +# +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_TS5500 is not set +CONFIG_GPIO_XILINX=y +CONFIG_GPIO_ZYNQ=y +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_GRGPIO is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# LPC GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# + +# +# USB GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_SMB347 is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_RESTART is not set +CONFIG_POWER_RESET_VEXPRESS=y +# CONFIG_POWER_AVS is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VEXPRESS is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_XADCPS=y +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +CONFIG_ZYNQ_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set +CONFIG_XILINX_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_VEXPRESS_CONFIG=y +# CONFIG_REGULATOR is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_RC_SUPPORT is not set +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_V4L2=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_DMA_CONTIG=y +# CONFIG_VIDEO_V4L2_INT_DEVICE is not set +# CONFIG_TTPCI_EEPROM is not set + +# +# Media drivers +# +# CONFIG_MEDIA_USB_SUPPORT is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_TIMBERDALE is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_VIDEO_XILINX=y +CONFIG_VIDEO_XILINX_REMAPPER=y +CONFIG_VIDEO_XILINX_TPG=y +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set + +# +# Supported MMC/SDIO adapters +# +# CONFIG_CYPRESS_FIRMWARE is not set + +# +# Media ancillary drivers (tuners, sensors, i2c, frontends) +# +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y + +# +# Audio decoders, processors and mixers +# + +# +# RDS decoders +# + +# +# Video decoders +# + +# +# Video and audio decoders +# + +# +# Video encoders +# + +# +# Camera sensor devices +# + +# +# Flash devices +# + +# +# Video improvement chips +# + +# +# Miscelaneous helper chips +# + +# +# Sensors used on soc_camera driver +# + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_DRM=y +CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_KMS_CMA_HELPER=y + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +CONFIG_DRM_ENCODER_ADV7511=y +# CONFIG_DRM_TDFX is not set +# CONFIG_DRM_R128 is not set +# CONFIG_DRM_RADEON is not set +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_MGA is not set +# CONFIG_DRM_VIA is not set +# CONFIG_DRM_SAVAGE is not set +# CONFIG_DRM_EXYNOS is not set +# CONFIG_DRM_VMWGFX is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_AST is not set +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_RCAR_DU is not set +# CONFIG_DRM_SHMOBILE is not set +# CONFIG_DRM_TILCDC is not set +# CONFIG_DRM_QXL is not set +CONFIG_DRM_XILINX=y +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_HDMI=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_XILINX is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_SIMPLE is not set +CONFIG_FB_XYLON=y +# CONFIG_FB_XYLON_PLATFORM is not set +CONFIG_FB_XYLON_OF=y +# CONFIG_FB_XYLON_PIXCLK is not set +# CONFIG_FB_XYLON_MISC is not set +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_LOGO is not set +# CONFIG_FB_SSD1307 is not set +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_COMPRESS_OFFLOAD=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CS5535AUDIO is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +CONFIG_SND_ARM=y +# CONFIG_SND_ARMAACI is not set +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_HIFACE is not set +CONFIG_SND_SOC=y +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_DESIGNWARE_I2S is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SIMPLE_CARD is not set +# CONFIG_SOUND_PRIME is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_HUION is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO_TPKBD is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +CONFIG_HID_MICROSOFT=y +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_XUSBPS_DR_OF=y +CONFIG_USB_EHCI_XUSBPS=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FUSBH200_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_CHIPIDEA is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_RCAR_PHY is not set +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y +# CONFIG_USB_ZYNQ_PHY is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 + +# +# USB Peripheral Controller +# +CONFIG_USB_GADGET_XUSBPS=y +CONFIG_XUSBPS_ERRATA_DT654401=y +CONFIG_USB_XUSBPS=y +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_R8A66597 is not set +CONFIG_USB_GADGET_XILINX=y +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_SS_LB=m +# CONFIG_USB_CONFIGFS is not set +CONFIG_USB_ZERO=m +# CONFIG_USB_ZERO_HNPTEST is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_MM_EDAC=y +CONFIG_EDAC_ZYNQ=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +CONFIG_RTC_DRV_PCF8563=y +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_RX4581 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_DS2404 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_MOXART is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_XILINX_DMA_ENGINES=y +CONFIG_XILINX_AXIDMA=y +# CONFIG_XILINX_DMATEST is not set +CONFIG_XILINX_AXIVDMA=y +# CONFIG_XILINX_VDMATEST is not set +CONFIG_XILINX_AXICDMA=y +# CONFIG_XILINX_CDMATEST is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_TIMB_DMA is not set +CONFIG_PL330_DMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +# CONFIG_UIO_CIF is not set +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_AEC is not set +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_UIO_PCI_GENERIC is not set +# CONFIG_UIO_NETX is not set +# CONFIG_UIO_MF624 is not set +CONFIG_UIO_XILINX_APM=y +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO=m + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +CONFIG_COMMON_CLK_DEBUG=y +CONFIG_COMMON_CLK_VERSATILE=y +# CONFIG_COMMON_CLK_SI5351 is not set +CONFIG_COMMON_CLK_SI570=y +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CADENCE_TTC_TIMER=y +# CONFIG_MAILBOX is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_OF_IOMMU=y + +# +# Remoteproc drivers +# +CONFIG_REMOTEPROC=m +# CONFIG_STE_MODEM_RPROC is not set +CONFIG_ZYNQ_REMOTEPROC=m +CONFIG_MB_REMOTEPROC=m + +# +# Rpmsg drivers +# +CONFIG_RPMSG=m +# CONFIG_RPMSG_SERVER_SAMPLE is not set +# CONFIG_RPMSG_OMX is not set +# CONFIG_RPMSG_FREERTOS_STAT is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +CONFIG_MEMORY=y +CONFIG_ZYNQ_SMC=y +# CONFIG_IIO is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_F2FS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU_DELAY is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_CPU_STALL_VERBOSE is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ZYNQ_UART0 is not set +CONFIG_DEBUG_ZYNQ_UART1=y +# CONFIG_DEBUG_VEXPRESS_UART0_DETECT is not set +# CONFIG_DEBUG_VEXPRESS_UART0_CA9 is not set +# CONFIG_DEBUG_VEXPRESS_UART0_RS1 is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +CONFIG_DEBUG_LL_INCLUDE="debug/zynq.S" +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_EARLY_PRINTK=y +# CONFIG_OC_ETM is not set +# CONFIG_PID_IN_CONTEXTIDR is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=m +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +CONFIG_FONT_SUPPORT=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_VIRTUALIZATION=y Index: linux-3.12.24-rt38-xilinx/arch/arm/include/asm/elf.h =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/include/asm/elf.h 2014-07-20 22:05:50.291065713 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/include/asm/elf.h 2014-07-20 22:06:34.131342419 +0200 @@ -50,6 +50,7 @@ #define R_ARM_ABS32 2 #define R_ARM_CALL 28 #define R_ARM_JUMP24 29 +#define R_ARM_TARGET1 38 #define R_ARM_V4BX 40 #define R_ARM_PREL31 42 #define R_ARM_MOVW_ABS_NC 43 Index: linux-3.12.24-rt38-xilinx/arch/arm/include/asm/hardirq.h =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/include/asm/hardirq.h 2014-07-20 22:05:50.292065697 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/include/asm/hardirq.h 2014-07-20 22:06:34.141342254 +0200 @@ -5,7 +5,7 @@ #include #include -#define NR_IPI 6 +#define NR_IPI 16 typedef struct { unsigned int __softirq_pending; Index: linux-3.12.24-rt38-xilinx/arch/arm/include/asm/setup.h =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/include/asm/setup.h 2014-07-20 22:05:50.290065730 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/include/asm/setup.h 2014-07-20 22:06:34.155342023 +0200 @@ -49,7 +49,7 @@ #define bank_phys_end(bank) ((bank)->start + (bank)->size) #define bank_phys_size(bank) (bank)->size -extern int arm_add_memory(phys_addr_t start, phys_addr_t size); +extern int arm_add_memory(u64 start, u64 size); extern void early_print(const char *str, ...); extern void dump_machine_table(void); Index: linux-3.12.24-rt38-xilinx/arch/arm/include/asm/smp.h =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/include/asm/smp.h 2014-07-20 22:05:50.293065680 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/include/asm/smp.h 2014-07-20 22:06:34.167341825 +0200 @@ -117,4 +117,7 @@ */ extern void smp_set_ops(struct smp_operations *); +extern int set_ipi_handler(int ipinr, void *handler, char *desc); +extern void clear_ipi_handler(int ipinr); + #endif /* ifndef __ASM_ARM_SMP_H */ Index: linux-3.12.24-rt38-xilinx/arch/arm/Kconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/Kconfig 2014-07-20 22:05:50.276065961 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/Kconfig 2014-07-20 22:06:34.186341512 +0200 @@ -4,7 +4,7 @@ select ARCH_BINFMT_ELF_RANDOMIZE_PIE select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST - select ARCH_HAVE_CUSTOM_GPIO_H + select ARCH_HAVE_CUSTOM_GPIO_H if (!ARCH_ZYNQ) select ARCH_WANT_IPC_PARSE_VERSION select BUILDTIME_EXTABLE_SORT if MMU select CLONE_BACKWARDS @@ -1601,7 +1601,7 @@ # selected platforms. config ARCH_NR_GPIO int - default 1024 if ARCH_SHMOBILE || ARCH_TEGRA + default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX default 392 if ARCH_U8500 default 352 if ARCH_VT8500 @@ -2097,7 +2097,7 @@ config KEXEC bool "Kexec system call (EXPERIMENTAL)" - depends on (!SMP || PM_SLEEP_SMP) + depends on PM_SLEEP_SMP help kexec is a system call that implements the ability to shutdown your current kernel, and to start another kernel. It is like a reboot Index: linux-3.12.24-rt38-xilinx/arch/arm/kernel/machine_kexec.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/kernel/machine_kexec.c 2014-07-20 22:05:50.281065878 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/kernel/machine_kexec.c 2014-07-20 22:06:34.201341264 +0200 @@ -2,6 +2,7 @@ * machine_kexec.c - handle transition of Linux booting another kernel */ +#include #include #include #include @@ -116,6 +117,7 @@ unsigned long msecs; local_irq_disable(); + disable_nonboot_cpus(); atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1); smp_call_function(machine_crash_nonpanic_core, NULL, false); Index: linux-3.12.24-rt38-xilinx/arch/arm/kernel/module.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/kernel/module.c 2014-07-20 22:05:50.280065895 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/kernel/module.c 2014-07-20 22:06:34.212341083 +0200 @@ -89,6 +89,7 @@ break; case R_ARM_ABS32: + case R_ARM_TARGET1: *(u32 *)loc += sym->st_value; break; Index: linux-3.12.24-rt38-xilinx/arch/arm/kernel/process.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/kernel/process.c 2014-07-20 22:05:50.278065928 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/kernel/process.c 2014-07-20 22:06:34.223340901 +0200 @@ -188,6 +188,9 @@ void machine_shutdown(void) { disable_nonboot_cpus(); +#ifdef CONFIG_SMP + smp_send_stop(); +#endif } /* Index: linux-3.12.24-rt38-xilinx/arch/arm/kernel/setup.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/kernel/setup.c 2014-07-20 22:05:50.279065912 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/kernel/setup.c 2014-07-20 22:06:34.237340670 +0200 @@ -619,7 +619,7 @@ /* can't use cpu_relax() here as it may require MMU setup */; } -int __init arm_add_memory(phys_addr_t start, phys_addr_t size) +int __init arm_add_memory(u64 start, u64 size) { struct membank *bank = &meminfo.bank[meminfo.nr_banks]; u64 aligned_start; @@ -691,8 +691,8 @@ static int __init early_mem(char *p) { static int usermem __initdata = 0; - phys_addr_t size; - phys_addr_t start; + u64 size; + u64 start; char *endp; /* Index: linux-3.12.24-rt38-xilinx/arch/arm/kernel/smp.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/kernel/smp.c 2014-07-20 22:05:50.282065862 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/kernel/smp.c 2014-07-20 22:06:34.250340456 +0200 @@ -448,14 +448,25 @@ smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); } -static const char *ipi_types[NR_IPI] = { -#define S(x,s) [x] = s - S(IPI_WAKEUP, "CPU wakeup interrupts"), - S(IPI_TIMER, "Timer broadcast interrupts"), - S(IPI_RESCHEDULE, "Rescheduling interrupts"), - S(IPI_CALL_FUNC, "Function call interrupts"), - S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"), - S(IPI_CPU_STOP, "CPU stop interrupts"), +struct ipi { + const char *desc; + void (*handler)(void); +}; + +static void ipi_cpu_stop(void); + +static struct ipi ipi_types[NR_IPI] = { +#define S(x, s, f) [x].desc = s, [x].handler = f + S(IPI_WAKEUP, "CPU wakeup interrupts", NULL), +#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST + S(IPI_TIMER, "Timer broadcast interrupts", tick_receive_broadcast), +#endif + S(IPI_RESCHEDULE, "Rescheduling interrupts", scheduler_ipi), + S(IPI_CALL_FUNC, "Function call interrupts", + generic_smp_call_function_interrupt), + S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts", + generic_smp_call_function_single_interrupt), + S(IPI_CPU_STOP, "CPU stop interrupts", ipi_cpu_stop), }; void show_ipi_list(struct seq_file *p, int prec) @@ -463,13 +474,13 @@ unsigned int cpu, i; for (i = 0; i < NR_IPI; i++) { - seq_printf(p, "%*s%u: ", prec - 1, "IPI", i); - - for_each_online_cpu(cpu) - seq_printf(p, "%10u ", - __get_irq_stat(cpu, ipi_irqs[i])); - - seq_printf(p, " %s\n", ipi_types[i]); + if (ipi_types[i].handler) { + seq_printf(p, "%*s%u: ", prec - 1, "IPI", i); + for_each_present_cpu(cpu) + seq_printf(p, "%10u ", + __get_irq_stat(cpu, ipi_irqs[i])); + seq_printf(p, " %s\n", ipi_types[i].desc); + } } } @@ -496,8 +507,10 @@ /* * ipi_cpu_stop - handle IPI from smp_send_stop() */ -static void ipi_cpu_stop(unsigned int cpu) +static void ipi_cpu_stop(void) { + unsigned int cpu = smp_processor_id(); + if (system_state == SYSTEM_BOOTING || system_state == SYSTEM_RUNNING) { raw_spin_lock(&stop_lock); @@ -528,50 +541,48 @@ unsigned int cpu = smp_processor_id(); struct pt_regs *old_regs = set_irq_regs(regs); - if (ipinr < NR_IPI) + if (ipi_types[ipinr].handler) { __inc_irq_stat(cpu, ipi_irqs[ipinr]); - - switch (ipinr) { - case IPI_WAKEUP: - break; - -#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST - case IPI_TIMER: irq_enter(); - tick_receive_broadcast(); + (*ipi_types[ipinr].handler)(); irq_exit(); - break; -#endif + } else + pr_debug("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); - case IPI_RESCHEDULE: - scheduler_ipi(); - break; + set_irq_regs(old_regs); +} - case IPI_CALL_FUNC: - irq_enter(); - generic_smp_call_function_interrupt(); - irq_exit(); - break; +/* + * set_ipi_handler: + * Interface provided for a kernel module to specify an IPI handler function. + */ +int set_ipi_handler(int ipinr, void *handler, char *desc) +{ + unsigned int cpu = smp_processor_id(); - case IPI_CALL_FUNC_SINGLE: - irq_enter(); - generic_smp_call_function_single_interrupt(); - irq_exit(); - break; + if (ipi_types[ipinr].handler) { + pr_crit("CPU%u: IPI handler 0x%x already registered to %pf\n", + cpu, ipinr, ipi_types[ipinr].handler); + return -1; + } - case IPI_CPU_STOP: - irq_enter(); - ipi_cpu_stop(cpu); - irq_exit(); - break; + ipi_types[ipinr].handler = handler; + ipi_types[ipinr].desc = desc; - default: - printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n", - cpu, ipinr); - break; - } - set_irq_regs(old_regs); + return 0; +} +EXPORT_SYMBOL(set_ipi_handler); + +/* + * clear_ipi_handler: + * Interface provided for a kernel module to clear an IPI handler function. + */ +void clear_ipi_handler(int ipinr) +{ + ipi_types[ipinr].handler = NULL; + ipi_types[ipinr].desc = NULL; } +EXPORT_SYMBOL(clear_ipi_handler); void smp_send_reschedule(int cpu) { Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/common.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/mach-zynq/common.c 2014-07-20 22:05:50.272066027 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/common.c 2014-07-20 22:06:34.265340209 +0200 @@ -16,15 +16,20 @@ #include #include +#include #include #include #include #include +#include #include #include #include #include #include +#include +#include +#include #include #include @@ -39,23 +44,130 @@ void __iomem *zynq_scu_base; -static struct of_device_id zynq_of_bus_ids[] __initdata = { - { .compatible = "simple-bus", }, - {} +/** + * zynq_memory_init() - Initialize special memory + * + * We need to stop things allocating the low memory as DMA can't work in + * the 1st 512K of memory. Using reserve vs remove is not totally clear yet. + */ +static void __init zynq_memory_init(void) +{ + /* + * Reserve the 0-0x4000 addresses (before page tables and kernel) + * which can't be used for DMA + */ + if (!__pa(PAGE_OFFSET)) + memblock_reserve(0, 0x4000); +} + +#ifdef CONFIG_CPU_FREQ +#define CPUFREQ_MIN_FREQ_HZ 200000000 +static unsigned int freq_divs[] __initdata = { + 2, 3 }; +static long __init xilinx_calc_opp_freq(struct clk *clk, long rate) +{ + long rate_nearest = clk_round_rate_nearest(clk, rate); + long rate_round = clk_round_rate(clk, rate_nearest / 1000 * 1000); + + if (rate_round != rate_nearest) + rate_nearest += 1000; + + return rate_nearest; +} + /** - * zynq_init_machine - System specific initialization, intended to be - * called from board specific initialization. + * zynq_opp_init() - Register OPPs + * + * Registering frequency/voltage operating points for voltage and frequency + * scaling. Currently we only support frequency scaling. */ -static void __init zynq_init_machine(void) +static int __init zynq_opp_init(void) +{ + long freq; + unsigned int i; + struct device *dev = get_cpu_device(0); + int ret = 0; + struct clk *cpuclk = clk_get(NULL, "cpufreq_clk"); + + if (!dev) { + pr_warn("%s: no cpu device. DVFS not available.", __func__); + return -ENODEV; + } + + if (IS_ERR(cpuclk)) { + pr_warn("%s: CPU clock not found. DVFS not available.", + __func__); + return PTR_ERR(cpuclk); + } + + /* frequency/voltage operating points. For now use f only */ + freq = clk_get_rate(cpuclk); + ret |= opp_add(dev, xilinx_calc_opp_freq(cpuclk, freq), 0); + for (i = 0; i < ARRAY_SIZE(freq_divs); i++) { + long tmp = xilinx_calc_opp_freq(cpuclk, freq / freq_divs[i]); + if (tmp >= CPUFREQ_MIN_FREQ_HZ) + ret |= opp_add(dev, tmp, 0); + } + freq = xilinx_calc_opp_freq(cpuclk, CPUFREQ_MIN_FREQ_HZ); + if (freq >= CPUFREQ_MIN_FREQ_HZ && IS_ERR(opp_find_freq_exact(dev, freq, + 1))) + ret |= opp_add(dev, freq, 0); + + if (ret) + pr_warn("%s: Error adding OPPs.", __func__); + + return ret; +} +device_initcall(zynq_opp_init); +#endif + +#ifdef CONFIG_CACHE_L2X0 +static int __init zynq_l2c_init(void) +{ + /* 64KB way size, 8-way associativity, parity disabled, + * prefetching option */ +#ifndef CONFIG_XILINX_L2_PREFETCH + return l2x0_of_init(0x02060000, 0xF0F0FFFF); +#else + return l2x0_of_init(0x72060000, 0xF0F0FFFF); +#endif +} +early_initcall(zynq_l2c_init); +#endif + + +#ifdef CONFIG_XILINX_L1_PREFETCH +static void __init zynq_data_prefetch_enable(void *info) { /* - * 64KB way size, 8-way associativity, parity disabled + * Enable prefetching in aux control register. L2 prefetch must + * only be enabled if the slave supports it (PL310 does) */ - l2x0_of_init(0x02060000, 0xF0F0FFFF); + asm volatile ("mrc p15, 0, r1, c1, c0, 1\n" + "orr r1, r1, #6\n" + "mcr p15, 0, r1, c1, c0, 1\n" + : : : "r1"); +} +#endif + +static void __init zynq_init_late(void) +{ + zynq_pm_late_init(); - of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); +#ifdef CONFIG_XILINX_L1_PREFETCH + on_each_cpu(zynq_data_prefetch_enable, NULL, 0); +#endif +} + +/** + * zynq_init_machine - System specific initialization, intended to be + * called from board specific initialization. + */ +static void __init zynq_init_machine(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static void __init zynq_timer_init(void) @@ -91,6 +203,12 @@ zynq_scu_map_io(); } +static void __init zynq_irq_init(void) +{ + gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; + irqchip_init(); +} + static void zynq_system_reset(enum reboot_mode mode, const char *cmd) { zynq_slcr_system_reset(); @@ -104,8 +222,11 @@ DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") .smp = smp_ops(zynq_smp_ops), .map_io = zynq_map_io, + .init_irq = zynq_irq_init, .init_machine = zynq_init_machine, + .init_late = zynq_init_late, .init_time = zynq_timer_init, .dt_compat = zynq_dt_match, + .reserve = zynq_memory_init, .restart = zynq_system_reset, MACHINE_END Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/common.h =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/mach-zynq/common.h 2014-07-20 22:05:50.267066110 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/common.h 2014-07-20 22:06:34.274340060 +0200 @@ -21,8 +21,10 @@ extern void zynq_slcr_system_reset(void); extern void zynq_slcr_cpu_stop(int cpu); extern void zynq_slcr_cpu_start(int cpu); +extern u32 zynq_slcr_get_ocm_config(void); #ifdef CONFIG_SMP +extern void zynq_secondary_startup(void); extern void secondary_startup(void); extern char zynq_secondary_trampoline; extern char zynq_secondary_trampoline_jump; @@ -31,10 +33,28 @@ extern struct smp_operations zynq_smp_ops __initdata; #endif +extern void zynq_slcr_write(u32 val, u32 offset); +extern u32 zynq_slcr_read(u32 offset); + +extern void zynq_slcr_init_preload_fpga(void); +extern void zynq_slcr_init_postload_fpga(void); + extern void __iomem *zynq_slcr_base; extern void __iomem *zynq_scu_base; /* Hotplug */ extern void zynq_platform_cpu_die(unsigned int cpu); +#ifdef CONFIG_SUSPEND +int zynq_pm_late_init(void); +#else +static inline int zynq_pm_late_init(void) +{ + return 0; +} +#endif + +extern unsigned int zynq_sys_suspend_sz; +int zynq_sys_suspend(void __iomem *ddrc_base, void __iomem *slcr_base); + #endif Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/headsmp.S =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/mach-zynq/headsmp.S 2014-07-20 22:05:50.275065977 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/headsmp.S 2014-07-20 22:06:34.284339895 +0200 @@ -18,5 +18,9 @@ .word /* cpu 1 */ .globl zynq_secondary_trampoline_end zynq_secondary_trampoline_end: - ENDPROC(zynq_secondary_trampoline) + +ENTRY(zynq_secondary_startup) + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(zynq_secondary_startup) Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/Kconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/mach-zynq/Kconfig 2014-07-20 22:05:50.273066011 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/Kconfig 2014-07-20 22:06:34.295339714 +0200 @@ -2,16 +2,51 @@ bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7 select ARM_AMBA select ARM_GIC - select COMMON_CLK - select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ICST select MIGHT_HAVE_CACHE_L2X0 - select USE_OF select HAVE_SMP - select SPARSE_IRQ + select CACHE_L2X0 + select ARCH_REQUIRE_GPIOLIB + select ARCH_HAS_CPUFREQ + select ARCH_HAS_OPP + select MIGHT_HAVE_PCI select CADENCE_TTC_TIMER + select GENERIC_ALLOCATOR help Support for Xilinx Zynq ARM Cortex A9 Platform + +if ARCH_ZYNQ + +menu "Xilinx Specific Options" + +config XILINX_L1_PREFETCH + bool "L1 Cache Prefetch" + default y + help + This option turns on L1 cache prefetching to get the best performance + in many cases. This may not always be the best performance depending on + the usage. There are some cases where this may cause issues when booting. + +config XILINX_L2_PREFETCH + bool "L2 Cache Prefetch" + default y + help + This option turns on L2 cache prefetching to get the best performance + in many cases. This may not always be the best performance depending on + the usage. + +config XILINX_AXIPCIE + bool "Xilinx AXI PCIe host bridge support" + select PCI + select ARCH_SUPPORTS_MSI + help + Say 'Y' here if you want kernel to support the Xilinx AXI PCIe + Host Bridge. This supports Message Signal Interrupts (MSI), if you + want to use this feature select CONFIG_PCI_MSI from 'Bus Support ->'. + +endmenu + +endif Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/mach-zynq/Makefile 2014-07-20 22:05:50.270066060 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/Makefile 2014-07-20 22:06:34.304339565 +0200 @@ -3,8 +3,12 @@ # # Common support -obj-y := common.o slcr.o +obj-y := common.o slcr.o zynq_ocm.o + +obj-$(CONFIG_PCI_MSI) += xaxipcie-msi.o CFLAGS_REMOVE_hotplug.o =-march=armv6k CFLAGS_hotplug.o =-Wa,-march=armv7-a -mcpu=cortex-a9 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_SMP) += headsmp.o platsmp.o +obj-$(CONFIG_SUSPEND) += pm.o suspend.o +obj-$(CONFIG_XILINX_AXIPCIE) += xaxipcie.o Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/Makefile.boot =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/mach-zynq/Makefile.boot 2014-07-20 22:05:50.269066076 +0200 +++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,3 +0,0 @@ - zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/platsmp.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/mach-zynq/platsmp.c 2014-07-20 22:05:50.268066093 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/platsmp.c 2014-07-20 22:06:34.333339087 +0200 @@ -39,7 +39,7 @@ u32 trampoline_code_size = &zynq_secondary_trampoline_end - &zynq_secondary_trampoline; - if (cpu > ncores) { + if (cpu >= ncores) { pr_warn("CPU No. is not available in the system\n"); return -1; } @@ -95,7 +95,7 @@ static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle) { - return zynq_cpun_start(virt_to_phys(secondary_startup), cpu); + return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu); } /* @@ -114,23 +114,23 @@ static void __init zynq_smp_prepare_cpus(unsigned int max_cpus) { - int i; - - /* - * Initialise the present map, which describes the set of CPUs - * actually populated at the present time. - */ - for (i = 0; i < max_cpus; i++) - set_cpu_present(i, true); - scu_enable(zynq_scu_base); } +#ifdef CONFIG_HOTPLUG_CPU +static int zynq_cpu_kill(unsigned cpu) +{ + zynq_slcr_cpu_stop(cpu); + return 1; +} +#endif + struct smp_operations zynq_smp_ops __initdata = { .smp_init_cpus = zynq_smp_init_cpus, .smp_prepare_cpus = zynq_smp_prepare_cpus, .smp_boot_secondary = zynq_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = zynq_platform_cpu_die, + .cpu_kill = zynq_cpu_kill, #endif }; Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/pm.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/pm.c 2014-07-20 22:06:34.343338922 +0200 @@ -0,0 +1,280 @@ +/* + * Suspend support for Zynq + * + * Copyright (C) 2012 Xilinx + * + * Soren Brinkmann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +#define DDRC_CTRL_REG1_OFFS 0x60 +#define DDRC_DRAM_PARAM_REG3_OFFS 0x20 +#define SCU_CTRL 0 + +#define DDRC_CLOCKSTOP_MASK BIT(23) +#define DDRC_SELFREFRESH_MASK BIT(12) +#define SCU_STBY_EN_MASK BIT(5) + +static void __iomem *ddrc_base; +static void __iomem *ocm_base; + +static int zynq_pm_prepare_late(void) +{ + return zynq_clk_suspend_early(); +} + +static void zynq_pm_wake(void) +{ + zynq_clk_resume_late(); +} + +static int zynq_pm_suspend(unsigned long arg) +{ + u32 reg; + int (*zynq_suspend_ptr)(void __iomem *, void __iomem *); + int do_ddrpll_bypass = 1; + + /* Enable DDR self-refresh and clock stop */ + if (ddrc_base) { + reg = readl(ddrc_base + DDRC_CTRL_REG1_OFFS); + reg |= DDRC_SELFREFRESH_MASK; + writel(reg, ddrc_base + DDRC_CTRL_REG1_OFFS); + + reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); + reg |= DDRC_CLOCKSTOP_MASK; + writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); + } else { + do_ddrpll_bypass = 0; + } + + /* SCU standby mode */ + if (zynq_scu_base) { + reg = readl(zynq_scu_base + SCU_CTRL); + reg |= SCU_STBY_EN_MASK; + writel(reg, zynq_scu_base + SCU_CTRL); + } + + /* Topswitch clock stop disable */ + zynq_clk_topswitch_disable(); + + /* A9 clock gating */ + asm volatile ("mrc p15, 0, r12, c15, c0, 0\n" + "orr r12, r12, #1\n" + "mcr p15, 0, r12, c15, c0, 0\n" + : /* no outputs */ + : /* no inputs */ + : "r12"); + + if (ocm_base) { + /* + * Copy code to suspend system into OCM. The suspend code + * needs to run from OCM as DRAM may no longer be available + * when the PLL is stopped. + */ + memcpy((__force void *)ocm_base, &zynq_sys_suspend, + zynq_sys_suspend_sz); + flush_icache_range((unsigned long)ocm_base, + (unsigned long)(ocm_base) + zynq_sys_suspend_sz); + zynq_suspend_ptr = (__force void *)ocm_base; + } else { + do_ddrpll_bypass = 0; + } + + /* Transfer to suspend code in OCM */ + if (do_ddrpll_bypass) { + /* + * Going this way will turn off DDR related clocks and the DDR + * PLL. I.e. We might brake sub systems relying on any of this + * clocks. And even worse: If there are any other masters in the + * system (e.g. in the PL) accessing DDR they are screwed. + */ + flush_cache_all(); + if (zynq_suspend_ptr(ddrc_base, zynq_slcr_base)) + pr_warn("DDR self refresh failed.\n"); + } else { + WARN_ONCE(1, "DRAM self-refresh not available\n"); + cpu_do_idle(); + } + + /* Topswitch clock stop enable */ + zynq_clk_topswitch_enable(); + + /* SCU standby mode */ + if (zynq_scu_base) { + reg = readl(zynq_scu_base + SCU_CTRL); + reg &= ~SCU_STBY_EN_MASK; + writel(reg, zynq_scu_base + SCU_CTRL); + } + + /* A9 clock gating */ + asm volatile ("mrc p15, 0, r12, c15, c0, 0\n" + "bic r12, r12, #1\n" + "mcr p15, 0, r12, c15, c0, 0\n" + : /* no outputs */ + : /* no inputs */ + : "r12"); + + /* Disable DDR self-refresh and clock stop */ + if (ddrc_base) { + reg = readl(ddrc_base + DDRC_CTRL_REG1_OFFS); + reg &= ~DDRC_SELFREFRESH_MASK; + writel(reg, ddrc_base + DDRC_CTRL_REG1_OFFS); + + reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); + reg &= ~DDRC_CLOCKSTOP_MASK; + writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); + } + + return 0; +} + +static int zynq_pm_enter(suspend_state_t suspend_state) +{ + switch (suspend_state) { + case PM_SUSPEND_STANDBY: + case PM_SUSPEND_MEM: + outer_disable(); + cpu_suspend(0, zynq_pm_suspend); + outer_resume(); + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct platform_suspend_ops zynq_pm_ops = { + .prepare_late = zynq_pm_prepare_late, + .enter = zynq_pm_enter, + .wake = zynq_pm_wake, + .valid = suspend_valid_only_mem, +}; + +/** + * zynq_pm_ioremap() - Create IO mappings + * @comp DT compatible string + * Returns a pointer to the mapped memory or NULL. + * + * Remap the memory region for a compatible DT node. + */ +static void __iomem *zynq_pm_ioremap(const char *comp) +{ + struct device_node *np; + void __iomem *base = NULL; + + np = of_find_compatible_node(NULL, NULL, comp); + if (np) { + base = of_iomap(np, 0); + of_node_put(np); + } else { + pr_warn("%s: no compatible node found for '%s'\n", __func__, + comp); + } + + return base; +} + +/** + * zynq_pm_remap_ocm() - Remap OCM + * Returns a pointer to the mapped memory or NULL. + * + * Remap the OCM. + */ +static void __iomem *zynq_pm_remap_ocm(void) +{ + struct device_node *np; + const char *comp = "xlnx,zynq-ocm-1.0"; + void __iomem *base = NULL; + + np = of_find_compatible_node(NULL, NULL, comp); + if (np) { + struct device *dev; + unsigned long pool_addr; + unsigned long pool_addr_virt; + struct gen_pool *pool; + + of_node_put(np); + + dev = &(of_find_device_by_node(np)->dev); + + /* Get OCM pool from device tree or platform data */ + pool = dev_get_gen_pool(dev); + if (!pool) { + pr_warn("%s: OCM pool is not available\n", __func__); + return NULL; + } + + pool_addr_virt = gen_pool_alloc(pool, zynq_sys_suspend_sz); + if (!pool_addr_virt) { + pr_warn("%s: Can't get OCM poll\n", __func__); + return NULL; + } + pool_addr = gen_pool_virt_to_phys(pool, pool_addr_virt); + if (!pool_addr) { + pr_warn("%s: Can't get physical address of OCM pool\n", + __func__); + return NULL; + } + base = __arm_ioremap(pool_addr, zynq_sys_suspend_sz, MT_MEMORY); + if (!base) { + pr_warn("%s: IOremap OCM pool failed\n", __func__); + return NULL; + } + pr_debug("%s: Remap OCM %s from %lx to %lx\n", __func__, comp, + pool_addr_virt, (unsigned long)base); + } else { + pr_warn("%s: no compatible node found for '%s'\n", __func__, + comp); + } + + return base; +} + +int __init zynq_pm_late_init(void) +{ + ddrc_base = zynq_pm_ioremap("xlnx,ps7-ddrc"); + if (!ddrc_base) + pr_warn("%s: Unable to map DDRC IO memory.\n", __func__); + + /* + * FIXME: should be done by an ocm driver which then provides allocators + */ + ocm_base = zynq_pm_remap_ocm(); + if (!ocm_base) + pr_warn("%s: Unable to map OCM.\n", __func__); + + suspend_set_ops(&zynq_pm_ops); + + return 0; +} Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/slcr.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/mach-zynq/slcr.c 2014-07-20 22:05:50.274065994 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/slcr.c 2014-07-20 22:06:34.351338790 +0200 @@ -15,15 +15,20 @@ */ #include +#include #include #include #include "common.h" /* register offsets */ #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */ + #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ +#define SLCR_FPGA_RST_CTRL_OFFSET 0x240 /* FPGA Software Reset Control */ #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ +#define SLCR_LVL_SHFTR_EN_OFFSET 0x900 /* Level Shifters Enable */ +#define SLCR_OCM_CFG_OFFSET 0x910 /* OCM Address Mapping */ #define SLCR_UNLOCK_MAGIC 0xDF0D #define SLCR_A9_CPU_CLKSTOP 0x10 @@ -56,12 +61,79 @@ } /** + * zynq_slcr_write - Write to a register in SLCR block + * + * @val: Value to write to the register + * @offset: Register offset in SLCR block + */ +void zynq_slcr_write(u32 val, u32 offset) +{ + writel(val, zynq_slcr_base + offset); +} +EXPORT_SYMBOL(zynq_slcr_write); + +/** + * zynq_slcr_read - Read a register in SLCR block + * + * @offset: Register offset in SLCR block + * + * return: Value read from the SLCR register + */ +u32 zynq_slcr_read(u32 offset) +{ + return readl(zynq_slcr_base + offset); +} +EXPORT_SYMBOL(zynq_slcr_read); + +/** + * zynq_slcr_get_ocm_config - Get SLCR OCM config + * + * return: OCM config bits + */ +u32 zynq_slcr_get_ocm_config(void) +{ + return zynq_slcr_read(SLCR_OCM_CFG_OFFSET); +} + +/** + * zynq_slcr_init_preload_fpga - Disable communication from the PL to PS. + */ +void zynq_slcr_init_preload_fpga(void) +{ + + /* Assert FPGA top level output resets */ + zynq_slcr_write(0xF, SLCR_FPGA_RST_CTRL_OFFSET); + + /* Disable level shifters */ + zynq_slcr_write(0, SLCR_LVL_SHFTR_EN_OFFSET); + + /* Enable output level shifters */ + zynq_slcr_write(0xA, SLCR_LVL_SHFTR_EN_OFFSET); +} +EXPORT_SYMBOL(zynq_slcr_init_preload_fpga); + +/** + * zynq_slcr_init_postload_fpga - Re-enable communication from the PL to PS. + */ +void zynq_slcr_init_postload_fpga(void) +{ + + /* Enable level shifters */ + zynq_slcr_write(0xf, SLCR_LVL_SHFTR_EN_OFFSET); + + /* Deassert AXI interface resets */ + zynq_slcr_write(0, SLCR_FPGA_RST_CTRL_OFFSET); +} +EXPORT_SYMBOL(zynq_slcr_init_postload_fpga); + +/** * zynq_slcr_cpu_start - Start cpu * @cpu: cpu number */ void zynq_slcr_cpu_start(int cpu) { u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + reg &= ~(SLCR_A9_CPU_RST << cpu); writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/suspend.S =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/suspend.S 2014-07-20 22:06:34.360338641 +0200 @@ -0,0 +1,135 @@ +/* + * Suspend support for Zynq + * + * Copyright (C) 2012 Xilinx + * + * Soren Brinkmann + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define DDRPLL_CTRL_OFFS 0x104 +#define PLLSTATUS_OFFS 0x10c +#define DDR_CLK_CTRL_OFFS 0x124 +#define DCI_CLK_CTRL_OFFS 0x128 +#define DDR_CMD_STA_OFFS 0x618 +#define MODE_STS_OFFS 0x54 + +#define PLL_RESET_MASK 1 +#define PLL_PWRDWN_MASK (1 << 1) +#define PLL_BYPASS_MASK (1 << 4) +#define DCICLK_ENABLE_MASK 1 +#define DDRCLK_ENABLE_MASK 3 +#define DDR_LOCK_MASK (1 << 1) +#define DDR_STATUS_MASK 7 + +#define DDR_OPMODE_SR 3 +#define MAXTRIES 100 + + .text + +/** + * zynq_sys_suspend - Enter suspend + * @ddrc_base: Base address of the DDRC + * @slcr_base: Base address of the SLCR + * Returns -1 if DRAM subsystem is not gated off, 0 otherwise. + * + * This function is moved into OCM and finishes the suspend operation. I.e. DDR + * related clocks are gated off and the DDR PLL is bypassed. + */ +ENTRY(zynq_sys_suspend) + dsb + /* Check DDRC is in self-refresh mode */ + ldr r2, [r0, #MODE_STS_OFFS] + and r2, #DDR_STATUS_MASK + cmp r2, #DDR_OPMODE_SR + movweq r3, #0xff00 + bne suspend + + mov r3, #0 + /* Wait for command queue empty */ +1: cmp r3, #MAXTRIES + movweq r3, #0xff00 + beq suspend + ldr r2, [r1, #DDR_CMD_STA_OFFS] + cmp r2, #0 + addne r3, #1 + bne 1b + + dsb + + /* Stop DDR clocks */ + ldr r2, [r1, #DDR_CLK_CTRL_OFFS] + bic r2, #DDRCLK_ENABLE_MASK + str r2, [r1, #DDR_CLK_CTRL_OFFS] + + dmb + + ldr r2, [r1, #DCI_CLK_CTRL_OFFS] + bic r2, #DCICLK_ENABLE_MASK + str r2, [r1, #DCI_CLK_CTRL_OFFS] + + dmb + + /* Bypass and powerdown DDR PLL */ + ldr r2, [r1, #DDRPLL_CTRL_OFFS] + orr r2, #PLL_BYPASS_MASK + str r2, [r1, #DDRPLL_CTRL_OFFS] + orr r2, #(PLL_PWRDWN_MASK | PLL_RESET_MASK) + str r2, [r1, #DDRPLL_CTRL_OFFS] + +suspend: + wfi + dsb + cmp r3, #0xff00 + moveq r0, #-1 + beq exit + + /* Power up DDR PLL */ + ldr r2, [r1, #DDRPLL_CTRL_OFFS] + bic r2, #(PLL_PWRDWN_MASK | PLL_RESET_MASK) + str r2, [r1, #DDRPLL_CTRL_OFFS] + /* wait for lock */ +1: ldr r2, [r1, #PLLSTATUS_OFFS] + and r2, #DDR_LOCK_MASK + cmp r2, #0 + beq 1b + + dsb + + /* Disable PLL bypass */ + ldr r2, [r1, #DDRPLL_CTRL_OFFS] + bic r2, #PLL_BYPASS_MASK + str r2, [r1, #DDRPLL_CTRL_OFFS] + + dmb + + /* Start DDR clocks */ + ldr r2, [r1, #DCI_CLK_CTRL_OFFS] + orr r2, #DCICLK_ENABLE_MASK + str r2, [r1, #DCI_CLK_CTRL_OFFS] + + dmb + + ldr r2, [r1, #DDR_CLK_CTRL_OFFS] + orr r2, #DDRCLK_ENABLE_MASK + str r2, [r1, #DDR_CLK_CTRL_OFFS] + + dsb + + mov r0, #0 +exit: bx lr + +ENTRY(zynq_sys_suspend_sz) + .word . - zynq_sys_suspend + + ENDPROC(zynq_sys_suspend) Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/xaxipcie.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/xaxipcie.c 2014-07-20 22:06:34.374338411 +0200 @@ -0,0 +1,1054 @@ +/* + * Xilinx AXI PCIe IP hardware initialation, setup and + * configuration spaces access file. + * + * Copyright (c) 2012 Xilinx, Inc. + * + * This program has adopted some work from PCI/PCIE support for AMCC + * PowerPC boards written by Benjamin Herrenschmidt. + * Copyright 2007 Ben. Herrenschmidt , IBM Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register definitions */ +#define PCIE_CFG_CMD 0x00000004 +#define PCIE_CFG_CLS 0x00000008 +#define PCIE_CFG_HDR 0x0000000C +#define PCIE_CFG_AD1 0x00000010 +#define PCIE_CFG_AD2 0x00000014 +#define PCIE_CFG_BUS 0x00000018 +#define PCIE_CFG_IO 0x0000001C +#define PCIE_CFG_MEM 0x00000020 +#define PCIE_CFG_PREF_MEM 0x00000024 +#define PCIE_CFG_PREF_BASE_UPPER 0x00000028 +#define PCIE_CFG_PREF_LIMIT_UPPER 0x0000002c +#define PCIE_CFG_IO_UPPER 0x00000030 + +#define XAXIPCIE_REG_VSECC 0x00000128 +#define XAXIPCIE_REG_VSECH 0x0000012c +#define XAXIPCIE_REG_BIR 0x00000130 +#define XAXIPCIE_REG_BSCR 0x00000134 +#define XAXIPCIE_REG_IDR 0x00000138 +#define XAXIPCIE_REG_IMR 0x0000013c +#define XAXIPCIE_REG_BLR 0x00000140 +#define XAXIPCIE_REG_PSCR 0x00000144 +#define XAXIPCIE_REG_RPSC 0x00000148 +#define XAXIPCIE_REG_MSIBASE1 0x0000014c +#define XAXIPCIE_REG_MSIBASE2 0x00000150 +#define XAXIPCIE_REG_RPEFR 0x00000154 +#define XAXIPCIE_REG_RPIFR1 0x00000158 +#define XAXIPCIE_REG_RPIFR2 0x0000015c +#define XAXIPCIE_REG_VSECC2 0x00000200 +#define XAXIPCIE_REG_VSECH2 0x00000204 + +/* Interrupt register defines */ +#define XAXIPCIE_INTR_LINK_DOWN (1 << 0) +#define XAXIPCIE_INTR_ECRC_ERR (1 << 1) +#define XAXIPCIE_INTR_STR_ERR (1 << 2) +#define XAXIPCIE_INTR_HOT_RESET (1 << 3) +#define XAXIPCIE_INTR_CFG_COMPL (7 << 5) +#define XAXIPCIE_INTR_CFG_TIMEOUT (1 << 8) +#define XAXIPCIE_INTR_CORRECTABLE (1 << 9) +#define XAXIPCIE_INTR_NONFATAL (1 << 10) +#define XAXIPCIE_INTR_FATAL (1 << 11) +#define XAXIPCIE_INTR_INTX (1 << 16) +#define XAXIPCIE_INTR_MSI (1 << 17) +#define XAXIPCIE_INTR_SLV_UNSUPP (1 << 20) +#define XAXIPCIE_INTR_SLV_UNEXP (1 << 21) +#define XAXIPCIE_INTR_SLV_COMPL (1 << 22) +#define XAXIPCIE_INTR_SLV_ERRP (1 << 23) +#define XAXIPCIE_INTR_SLV_CMPABT (1 << 24) +#define XAXIPCIE_INTR_SLV_ILLBUR (1 << 25) +#define XAXIPCIE_INTR_MST_DECERR (1 << 26) +#define XAXIPCIE_INTR_MST_SLVERR (1 << 27) +#define XAXIPCIE_INTR_MST_ERRP (1 << 28) + +#define BUS_LOC_SHIFT 20 +#define DEV_LOC_SHIFT 12 +#define PRIMARY_BUS 1 +#define PORT_REG_SIZE 0x1000 +#define PORT_HEADER_SIZE 0x128 + +#define XAXIPCIE_LOCAL_CNFG_BASE 0x00000000 +#define XAXIPCIE_REG_BASE 0x00000128 +#define XAXIPCIE_REG_PSCR_LNKUP 0x00000800 +#define XAXIPCIE_REG_IMR_MASKALL 0x1FF30FED +#define XAXIPCIE_REG_IDR_MASKALL 0xFFFFFFFF +#define XAXIPCIE_REG_RPSC_BEN 0x00000001 +#define BUS_MASTER_ENABLE 0x00000004 + +#define XAXIPCIE_ACCESS8 1 +#define XAXIPCIE_ACCESS16 2 + +#define XAXIPCIE_MEM_SPACE 2 +#define XAXIPCIE_MEM_SPACE64 3 + +/* Config structure for PCIe */ +struct xaxi_pcie_of_config { + u32 num_instances; + u32 device_id; + u32 device_type; + u32 ecam_base; + u32 ecam_high; + u32 baseaddr; + u32 highaddr; + u32 bars_num; + u32 irq_num; + u32 reg_base; + u32 reg_len; + u32 pcie2axibar_0; + u32 pcie2axibar_1; + const __be32 *ranges; + int range_len; + u32 address_cells; +}; + +/* PCIe Root Port Structure */ +struct xaxi_pcie_port { + struct device_node *node; + u32 reg_base; + u32 reg_len; + u32 ecam_base; + u32 ecam_high; + u32 baseaddr; + u32 highaddr; + u32 header_addr; + u8 index; + u8 type; + u8 link_up; + u8 bars_num; + u32 irq_num; + const __be32 *ranges; + int range_len; + u32 pna; + u8 __iomem *base_addr_remap; + u8 __iomem *header_remap; + u8 __iomem *ecam_remap; + u32 pcie2axibar_0; + u32 pcie2axibar_1; + u32 root_bus_nr; + u32 first_busno; + u32 last_busno; + resource_size_t isa_mem_phys; + resource_size_t isa_mem_size; + resource_size_t pci_mem_offset; + struct resource io_resource; + struct resource mem_resources[3]; + char mem_space_name[16]; +}; + +static struct xaxi_pcie_port *xaxi_pcie_ports; +static int xaxi_pcie_port_cnt; +static int last_bus_on_record; + +/* ISA Memory physical address */ +static resource_size_t isa_mem_base; + +#ifdef CONFIG_PCI_MSI +static int xaxipcie_msi_irq_base; + +int xaxipcie_alloc_msi_irqdescs(struct device_node *node, + unsigned long msg_addr); +#endif + +/* Macros */ +#define is_link_up(base_address) \ + ((readl(base_address + XAXIPCIE_REG_PSCR) & \ + XAXIPCIE_REG_PSCR_LNKUP) ? 1 : 0) + +#define bridge_enable(base_address) \ + writel((readl(base_address + XAXIPCIE_REG_RPSC) | \ + XAXIPCIE_REG_RPSC_BEN), \ + (base_address + XAXIPCIE_REG_RPSC)) + +/** + * xaxi_pcie_verify_config + * @port: A pointer to a pcie port that needs to be handled + * @bus: Bus structure of current bus + * @devfun: device/function + * + * @return: Error / no error + * + * @note: Make sure we can handle this configuration call on our + * device. + */ +static int xaxi_pcie_verify_config(struct xaxi_pcie_port *port, + struct pci_bus *bus, + unsigned int devfn) +{ + static int message; + + /* Endpoint can not generate upstream(remote) config cycles */ + if ((!port->type) && bus->number != port->first_busno) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* Check we are within the mapped range */ + if (bus->number > port->last_busno) { + if (!message) { + pr_warn("Warning! Probing bus %u out of range !\n", + bus->number); + message++; + } + return PCIBIOS_DEVICE_NOT_FOUND; + } + + /* The other side of the RC has only one device as well */ + if (bus->number == (port->first_busno + 1) && + PCI_SLOT(devfn) != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* Check if we have a link */ + if (!port->link_up) + port->link_up = is_link_up(port->base_addr_remap); + + if ((bus->number != port->first_busno) && !port->link_up) + return PCIBIOS_DEVICE_NOT_FOUND; + + return 0; +} + +/** + * xaxi_pcie_get_config_base + * @port: A pointer to a pcie port that needs to be handled + * @bus: Bus structure of current bus + * @devfun: Device/function + * @where: Offset from base + * + * @return: Base address of the configuration space needed to be + * accessed. + * + * @note: Get the base address of the configuration space for this + * pcie device. + */ +static void __iomem *xaxi_pcie_get_config_base( + struct xaxi_pcie_port *port, + struct pci_bus *bus, + unsigned int devfn, int where) +{ + int relbus; + + relbus = ((bus->number << BUS_LOC_SHIFT) | (devfn << DEV_LOC_SHIFT)); + + return port->header_remap + relbus + where; +} + +/** + * xaxi_pcie_read_config - Read config reg. + * @port: A pointer to a pcie port that needs to be handled + * @bus: Bus structure of current bus + * @devfun: Device/function + * @where: Offset from base + * @size: Byte/word/dword + * @val: A pointer to value read + * + * @return: Error / no error + * + * + * @note: Read byte/word/dword from pcie device config reg. + */ +static int xaxi_pcie_read_config(struct pci_bus *bus, + unsigned int devfn, + int where, + int size, + u32 *val) +{ + struct pci_sys_data *sys = bus->sysdata; + struct xaxi_pcie_port *port = sys->private_data; + void __iomem *addr; + + if (xaxi_pcie_verify_config(port, bus, devfn) != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + addr = xaxi_pcie_get_config_base(port, bus, devfn, where); + + if ((bus->number == 0) && devfn > 0) { + *val = 0xFFFFFFFF; + return PCIBIOS_SUCCESSFUL; + } + + switch (size) { + case XAXIPCIE_ACCESS8: + *val = readb(addr); + break; + case XAXIPCIE_ACCESS16: + *val = readw(addr); + break; + default: + *val = readl(addr); + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +/** + * xaxi_pcie_write_config - Write config reg. + * @port: A pointer to a pcie port that needs to be handled + * @bus: Bus structure of current bus + * @devfun: Device/function + * @where: Offset from base + * @size: Byte/word/dword + * @val: Value to be written to device + * + * @return: Error / no error + * + * + * @note: Write byte/word/dword to pcie device config reg. + */ +static int xaxi_pcie_write_config(struct pci_bus *bus, + unsigned int devfn, + int where, + int size, + u32 val) +{ + struct pci_sys_data *sys = bus->sysdata; + struct xaxi_pcie_port *port = sys->private_data; + void __iomem *addr; + + if (xaxi_pcie_verify_config(port, bus, devfn) != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + addr = xaxi_pcie_get_config_base(port, bus, devfn, where); + + if ((bus->number == 0) && devfn > 0) + return PCIBIOS_SUCCESSFUL; + + switch (size) { + case XAXIPCIE_ACCESS8: + writeb(val, addr); + break; + case XAXIPCIE_ACCESS16: + writew(val, addr); + break; + default: + writel(val, addr); + break; + } + + wmb(); + + return PCIBIOS_SUCCESSFUL; +} + +/** + * xaxi_pcie_set_bridge_resource - Setup base & limit registers of config space. + * @port: Pointer to a root port + * + * @return: None + * + * @note: None + */ +static void xaxi_pcie_set_bridge_resource(struct xaxi_pcie_port *port) +{ + const __be32 *ranges = port->ranges; + int rlen = port->range_len; + int np = port->pna + 5; + u32 pci_space; + unsigned long long pci_addr, size; + u32 val = 0; + + while ((rlen -= np * 4) >= 0) { + pci_space = be32_to_cpup(ranges); + pci_addr = of_read_number(ranges + 1, 2); + size = of_read_number(ranges + port->pna + 3, 2); + + pr_info("%s:pci_space: 0x%08x pci_addr:0x%016llx size: 0x%016llx\n", + __func__, pci_space, pci_addr, size); + + ranges += np; + + switch ((pci_space >> 24) & 0x3) { + case XAXIPCIE_MEM_SPACE: /* PCI Memory space */ + pr_info("%s:Setting resource in Memory Space\n", + __func__); + writel(port->pcie2axibar_0, + port->header_remap + + PCIE_CFG_AD1); + writel(port->pcie2axibar_1, + port->header_remap + + PCIE_CFG_AD2); + break; + case XAXIPCIE_MEM_SPACE64: /* PCI 64 bits Memory space */ + pr_info("%s:Setting resource in Prefetchable Memory Space\n", + __func__); + + val = ((pci_addr >> 16) & 0xfff0) | + ((pci_addr + size - 1) & 0xfff00000); + + writel(val, port->header_remap + + PCIE_CFG_PREF_MEM); + + val = ((pci_addr >> 32) & 0xffffffff); + writel(val, port->header_remap + + PCIE_CFG_PREF_BASE_UPPER); + + val = (((pci_addr + size - 1) >> 32) & 0xffffffff); + writel(val, port->header_remap + + PCIE_CFG_PREF_LIMIT_UPPER); + break; + } + } +} + +static int xaxi_pcie_hookup_resources(struct xaxi_pcie_port *port, + struct pci_sys_data *sys) +{ + struct resource *res; + int i; + + /* Hookup Memory resources */ + for (i = 0; i < 3; ++i) { + res = &port->mem_resources[i]; + snprintf(port->mem_space_name, sizeof(port->mem_space_name), + "PCIe %d MEM", port->index); + port->mem_space_name[sizeof(port->mem_space_name) - 1] = 0; + res->name = port->mem_space_name; + + if (!res->flags) { + if (i > 0) + continue; + /* Workaround for lack of MEM resource only on 32-bit */ + res->start = port->pci_mem_offset; + res->end = (resource_size_t)-1LL; + res->flags = IORESOURCE_MEM; + } + if (request_resource(&iomem_resource, res)) + panic("Request PCIe%d Memory resource failed\n", + port->index); + pci_add_resource_offset(&sys->resources, + res, port->pci_mem_offset); + + pr_info("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", + i, (unsigned long long)res->start, + (unsigned long long)res->end, + (unsigned long)res->flags); + } + + return 0; +} + +static void xaxi_pcie_process_bridge_OF_ranges(struct xaxi_pcie_port *port, + int primary) +{ + /* The address cells of PCIe node */ + int pna = port->pna; + int np = pna + 5; + int memno = 0, isa_hole = -1; + u32 pci_space; + unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; + unsigned long long isa_mb = 0; + struct resource *res; + const __be32 *ranges = port->ranges; + int rlen = port->range_len; + struct device_node *node = port->node; + + pr_info("PCI host bridge %s %s ranges:\n", + node->full_name, primary ? "(primary)" : ""); + + /* Parse it */ + pr_debug("Parsing ranges property...\n"); + while ((rlen -= np * 4) >= 0) { + /* Read next ranges element */ + pci_space = be32_to_cpup(ranges); + pci_addr = of_read_number(ranges + 1, 2); + cpu_addr = of_translate_address(node, ranges + 3); + size = of_read_number(ranges + pna + 3, 2); + + pr_debug("pci_space: 0x%08x pci_addr:0x%016llx\n", + pci_space, pci_addr); + pr_debug("cpu_addr:0x%016llx size:0x%016llx\n", cpu_addr, size); + + ranges += np; + + /* If we failed translation or got a zero-sized region + * (some FW try to feed us with non sensical zero sized regions + * such as power3 which look like some kind of attempt + * at exposing the VGA memory hole) + */ + if (cpu_addr == OF_BAD_ADDR || size == 0) + continue; + + /* Now consume following elements while they are contiguous */ + for (; rlen >= np * sizeof(u32); + ranges += np, rlen -= np * 4) { + if (be32_to_cpup(ranges) != pci_space) + break; + pci_next = of_read_number(ranges + 1, 2); + cpu_next = of_translate_address(node, ranges + 3); + if (pci_next != pci_addr + size || + cpu_next != cpu_addr + size) + break; + size += of_read_number(ranges + pna + 3, 2); + } + + /* Act based on address space type */ + res = NULL; + switch ((pci_space >> 24) & 0x3) { + case XAXIPCIE_MEM_SPACE: /* PCI Memory space */ + case XAXIPCIE_MEM_SPACE64: /* PCI 64 bits Memory space */ + pr_info("MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", + cpu_addr, cpu_addr + size - 1, pci_addr, + (pci_space & 0x40000000) ? "Prefetch" : ""); + + /* We support only 3 memory ranges */ + if (memno >= 3) { + pr_info("\\--> Skipped (too many) !\n"); + continue; + } + /* Handles ISA memory hole space here */ + if (pci_addr == 0) { + isa_mb = cpu_addr; + isa_hole = memno; + if (primary || isa_mem_base == 0) + isa_mem_base = cpu_addr; + port->isa_mem_phys = cpu_addr; + port->isa_mem_size = size; + } + + /* We get the PCI/Mem offset from the first range or + * the, current one if the offset came from an ISA + * hole. If they don't match, bugger. + */ + if (memno == 0 || + (isa_hole >= 0 && pci_addr != 0 && + port->pci_mem_offset == isa_mb)) + port->pci_mem_offset = cpu_addr - pci_addr; + else if (pci_addr != 0 && + port->pci_mem_offset != cpu_addr - pci_addr) { + pr_info("\\--> Skipped (offset mismatch) !\n"); + continue; + } + + /* Build resource */ + res = &port->mem_resources[memno++]; + res->flags = IORESOURCE_MEM; + if (pci_space & 0x40000000) + res->flags |= IORESOURCE_PREFETCH; + res->start = cpu_addr; + break; + } + if (res != NULL) { + res->name = node->full_name; + res->end = res->start + size - 1; + res->parent = NULL; + res->sibling = NULL; + res->child = NULL; + } + } + + /* If there's an ISA hole and the pci_mem_offset is -not- matching + * the ISA hole offset, then we need to remove the ISA hole from + * the resource list for that brige + */ + if (isa_hole >= 0 && port->pci_mem_offset != isa_mb) { + unsigned int next = isa_hole + 1; + pr_info("Removing ISA hole at 0x%016llx\n", isa_mb); + if (next < memno) + memmove(&port->mem_resources[isa_hole], + &port->mem_resources[next], + sizeof(struct resource) * (memno - next)); + port->mem_resources[--memno].flags = 0; + } +} + +static struct pci_ops xaxi_pcie_ops = { + .read = xaxi_pcie_read_config, + .write = xaxi_pcie_write_config, +}; + +static int xaxi_pcie_setup(int nr, struct pci_sys_data *sys) +{ + u32 val; + struct xaxi_pcie_port *port = &xaxi_pcie_ports[nr]; + + sys->private_data = port; + + /* Get bus range */ + port->first_busno = last_bus_on_record; + + val = readl(port->base_addr_remap + XAXIPCIE_REG_PSCR); + val = readl(port->header_remap + XAXIPCIE_REG_BIR); + val = (val >> 16) & 0x7; + port->last_busno = (((port->reg_base - port->reg_len - 1) >> 20) + & 0xFF) & val; + + /* Write primary, secondary and subordinate bus numbers */ + val = port->first_busno; + val |= ((port->first_busno + 1) << 8); + val |= (port->last_busno << 16); + + writel(val, (port->header_remap + PCIE_CFG_BUS)); + last_bus_on_record = port->last_busno + 1; + + xaxi_pcie_set_bridge_resource(port); + + /* Parse outbound mapping resources */ + xaxi_pcie_process_bridge_OF_ranges(port, PRIMARY_BUS); + xaxi_pcie_hookup_resources(port, sys); + + return 1; +} + +static struct pci_bus __init *xaxi_pcie_scan_bus(int nr, + struct pci_sys_data *sys) +{ + struct xaxi_pcie_port *port; + + if (nr >= xaxi_pcie_port_cnt) + return NULL; + + port = &xaxi_pcie_ports[nr]; + port->root_bus_nr = sys->busnr; + + return pci_scan_root_bus(NULL, sys->busnr, &xaxi_pcie_ops, sys, + &sys->resources); +} + +static int xaxi_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + struct pci_sys_data *sys = dev->sysdata; + struct xaxi_pcie_port *port = sys->private_data; + + return port->irq_num; +} + +/* Interrupt handler */ +static irqreturn_t xaxi_pcie_intr_handler(int irq, void *data) +{ + struct xaxi_pcie_port *port = (struct xaxi_pcie_port *)data; + u32 val = 0, mask = 0; + u32 status; + u32 msi_addr = 0; + u32 msi_data = 0; + + /* Read interrupt decode and mask registers */ + val = readl(port->header_remap + XAXIPCIE_REG_IDR); + mask = readl(port->header_remap + XAXIPCIE_REG_IMR); + + status = val & mask; + if (!status) + return IRQ_NONE; + + if (status & XAXIPCIE_INTR_LINK_DOWN) + pr_err("Link Down\n"); + + if (status & XAXIPCIE_INTR_ECRC_ERR) + pr_warn("ECRC failed\n"); + + if (status & XAXIPCIE_INTR_STR_ERR) + pr_warn("Streaming error\n"); + + if (status & XAXIPCIE_INTR_HOT_RESET) + pr_info("Hot reset\n"); + + if (status & XAXIPCIE_INTR_CFG_TIMEOUT) + pr_warn("ECAM access timeout\n"); + + if (status & XAXIPCIE_INTR_CORRECTABLE) { + pr_warn("Correctable error message\n"); + val = readl(port->header_remap + + XAXIPCIE_REG_RPEFR); + if (val & (1 << 18)) { + writel(0xFFFFFFFF, + port->base_addr_remap + + XAXIPCIE_REG_RPEFR); + pr_debug("Requester ID %d\n", (val & 0xffff)); + } + } + + if (status & XAXIPCIE_INTR_NONFATAL) { + pr_warn("Non fatal error message\n"); + val = readl((port->header_remap) + + XAXIPCIE_REG_RPEFR); + if (val & (1 << 18)) { + writel(0xFFFFFFFF, + port->base_addr_remap + + XAXIPCIE_REG_RPEFR); + pr_debug("Requester ID %d\n", (val & 0xffff)); + } + } + + if (status & XAXIPCIE_INTR_FATAL) { + pr_warn("Fatal error message\n"); + val = readl(port->header_remap + + XAXIPCIE_REG_RPEFR); + if (val & (1 << 18)) { + writel(0xFFFFFFFF, + port->base_addr_remap + + XAXIPCIE_REG_RPEFR); + pr_debug("Requester ID %d\n", (val & 0xffff)); + } + } + + if (status & XAXIPCIE_INTR_INTX) { + /* INTx interrupt received */ + val = readl(port->header_remap + XAXIPCIE_REG_RPIFR1); + + /* Check whether interrupt valid */ + if (!(val & (1 << 31))) { + pr_warn("RP Intr FIFO1 read error\n"); + return IRQ_HANDLED; + } + + /* Check MSI or INTX */ + if (!(val & (1 << 30))) { + if (val & (1 << 29)) + pr_debug("INTx assert\n"); + else + pr_debug("INTx deassert\n"); + } + + /* Clear interrupt FIFO register 1 */ + writel(0xFFFFFFFF, + port->base_addr_remap + XAXIPCIE_REG_RPIFR1); + } + + if (status & XAXIPCIE_INTR_MSI) { + /* MSI Interrupt */ + val = readl(port->header_remap + XAXIPCIE_REG_RPIFR1); + + if (!(val & (1 << 31))) { + pr_warn("RP Intr FIFO1 read error\n"); + return IRQ_HANDLED; + } + + if (val & (1 << 30)) { + msi_addr = (val >> 16) & 0x7FF; + msi_data = readl(port->header_remap + + XAXIPCIE_REG_RPIFR2) & 0xFFFF; + pr_debug("%s: msi_addr %08x msi_data %08x\n", + __func__, msi_addr, msi_data); + } + + /* Clear interrupt FIFO register 1 */ + writel(0xFFFFFFFF, + port->base_addr_remap + XAXIPCIE_REG_RPIFR1); +#ifdef CONFIG_PCI_MSI + /* Handle MSI Interrupt */ + if (msi_data >= xaxipcie_msi_irq_base) + generic_handle_irq(msi_data); +#endif + } + + if (status & XAXIPCIE_INTR_SLV_UNSUPP) + pr_warn("Slave unsupported request\n"); + + if (status & XAXIPCIE_INTR_SLV_UNEXP) + pr_warn("Slave unexpected completion\n"); + + if (status & XAXIPCIE_INTR_SLV_COMPL) + pr_warn("Slave completion timeout\n"); + + if (status & XAXIPCIE_INTR_SLV_ERRP) + pr_warn("Slave Error Poison\n"); + + if (status & XAXIPCIE_INTR_SLV_CMPABT) + pr_warn("Slave Completer Abort\n"); + + if (status & XAXIPCIE_INTR_SLV_ILLBUR) + pr_warn("Slave Illegal Burst\n"); + + if (status & XAXIPCIE_INTR_MST_DECERR) + pr_warn("Master decode error\n"); + + if (status & XAXIPCIE_INTR_MST_SLVERR) + pr_warn("Master slave error\n"); + + if (status & XAXIPCIE_INTR_MST_ERRP) + pr_warn("Master error poison\n"); + + /* Clear the Interrupt Decode register */ + writel(status, port->base_addr_remap + XAXIPCIE_REG_IDR); + + return IRQ_HANDLED; +} + +/** + * xaxi_pcie_init_port - Initialize hardware + * @port: A pointer to a pcie port that needs to be initialized + * + * @return: Error / no error + * + * @note: None + */ +static int xaxi_pcie_init_port(struct xaxi_pcie_port *port) +{ + void __iomem *base_addr_remap = NULL; + int err = 0; +#ifdef CONFIG_PCI_MSI + unsigned long xaxipcie_msg_addr; +#endif + + base_addr_remap = ioremap(port->reg_base, port->reg_len); + if (!base_addr_remap) + return -ENOMEM; + + port->base_addr_remap = base_addr_remap; + + /* make sure it is root port before touching header */ + if (port->type) { + port->header_remap = base_addr_remap; + writel(BUS_MASTER_ENABLE, + port->base_addr_remap + PCIE_CFG_CMD); + } + +#ifdef CONFIG_PCI_MSI + xaxipcie_msg_addr = port->reg_base & ~0xFFF; /* 4KB aligned */ + writel(0x0, port->base_addr_remap + + XAXIPCIE_REG_MSIBASE1); + + writel(xaxipcie_msg_addr, port->base_addr_remap + + XAXIPCIE_REG_MSIBASE2); + + xaxipcie_msi_irq_base = xaxipcie_alloc_msi_irqdescs(port->node, + xaxipcie_msg_addr); + if (xaxipcie_msi_irq_base < 0) { + pr_err("%s: Couldn't allocate MSI IRQ numbers\n", + __func__); + return -ENODEV; + } +#endif + + port->link_up = is_link_up(port->base_addr_remap); + if (!port->link_up) + pr_info("%s: LINK IS DOWN\n", __func__); + else + pr_info("%s: LINK IS UP\n", __func__); + + /* Disable all interrupts*/ + writel(~XAXIPCIE_REG_IDR_MASKALL, + port->base_addr_remap + XAXIPCIE_REG_IMR); + + /* Clear pending interrupts*/ + writel(readl(port->base_addr_remap + XAXIPCIE_REG_IDR) & + XAXIPCIE_REG_IMR_MASKALL, + port->base_addr_remap + XAXIPCIE_REG_IDR); + + /* Enable all interrupts*/ + writel(XAXIPCIE_REG_IMR_MASKALL, + port->base_addr_remap + XAXIPCIE_REG_IMR); + + /* + * Bridge enable must be done after enumeration, + * but there is no callback defined + */ + bridge_enable(port->base_addr_remap); + + /* Register Interrupt Handler */ + err = request_irq(port->irq_num, xaxi_pcie_intr_handler, + IRQF_SHARED, "zynqpcie", port); + if (err) { + pr_err("%s: Could not allocate interrupt\n", __func__); + return err; + } + + return 0; +} + +static struct xaxi_pcie_port * +xaxi_pcie_instantiate_port_info(struct xaxi_pcie_of_config *config, + struct device_node *node) +{ + struct xaxi_pcie_port *port; + int port_num; + + port_num = config->device_id; + port = &xaxi_pcie_ports[port_num]; + port->node = of_node_get(node); + port->index = port_num; + port->type = config->device_type; + port->reg_base = config->reg_base; + port->reg_len = config->reg_len; + port->bars_num = config->bars_num; + port->irq_num = config->irq_num; + port->header_addr = port->reg_base + XAXIPCIE_LOCAL_CNFG_BASE; + port->pcie2axibar_0 = config->pcie2axibar_0; + port->pcie2axibar_1 = config->pcie2axibar_1; + port->ranges = config->ranges; + port->range_len = config->range_len; + port->pna = config->address_cells; + + return port; +} + +/** + * xaxi_get_pcie_of_config - Read info from device tree + * @node: A pointer to device node to read from + * @info: A pointer to xilinx_pcie_node struct to write device tree + * info into to. + * + * @return: Error / no error + * + * @note: Read related info from device tree + */ +static int xaxi_pcie_get_of_config(struct device_node *node, + struct xaxi_pcie_of_config *info) +{ + const __be32 *value; + int rlen; + + info->num_instances = 1; + + value = of_get_property(node, "xlnx,device-num", &rlen); + + info->device_id = 0; + + value = of_get_property(node, "xlnx,include-rc", &rlen); + if (value) + info->device_type = be32_to_cpup(value); + else + return -ENODEV; + + value = of_get_property(node, "reg", &rlen); + if (value) { + info->reg_base = + be32_to_cpup(value); + info->reg_len = + be32_to_cpup(value + 1); + } else + return -ENODEV; + + value = of_get_property(node, "xlnx,pciebar-num", &rlen); + if (value) + info->bars_num = be32_to_cpup(value); + else + return -ENODEV; + + info->irq_num = irq_of_parse_and_map(node, 0); + + /* Get address translation parameters */ + value = of_get_property(node, "xlnx,pciebar2axibar-0", &rlen); + if (value) { + info->pcie2axibar_0 = + be32_to_cpup(value); + } else + return -ENODEV; + + value = of_get_property(node, "xlnx,pciebar2axibar-1", &rlen); + if (value) { + info->pcie2axibar_1 = + be32_to_cpup(value); + } else + return -ENODEV; + + /* The address cells of PCIe node */ + info->address_cells = of_n_addr_cells(node); + + /* Get ranges property */ + value = of_get_property(node, "ranges", &rlen); + if (value) { + info->ranges = value; + info->range_len = rlen; + } else + return -ENODEV; + + return 0; +} + +static int __init xaxi_pcie_of_probe(struct device_node *node) +{ + int err = 0; + struct xaxi_pcie_of_config config; + struct xaxi_pcie_port *port; + + err = xaxi_pcie_get_of_config(node, &config); + if (err) { + pr_err("%s: Invalid Configuration\n", __func__); + return err; + } + + if (!xaxi_pcie_port_cnt) { + xaxi_pcie_port_cnt = config.num_instances; + + if (xaxi_pcie_port_cnt) { + xaxi_pcie_ports = (struct xaxi_pcie_port *) + kzalloc(xaxi_pcie_port_cnt * + sizeof(struct xaxi_pcie_port), GFP_KERNEL); + + if (!xaxi_pcie_ports) { + pr_err("%s: Memory allocation failed\n", + __func__); + return -ENOMEM; + } + } else /* not suppose to be here + * when we don't have pcie ports */ + return -ENODEV; + } + + port = xaxi_pcie_instantiate_port_info(&config, node); + err = xaxi_pcie_init_port(port); + if (err) { + pr_err("%s: Port Initalization failed\n", __func__); + return err; + } + + return err; +} + +static struct of_device_id xaxi_pcie_match[] = { + { .compatible = "xlnx,axi-pcie-1.05.a" ,}, + {} +}; + +static struct hw_pci xaxi_pcie_hw __initdata = { + .nr_controllers = 1, + .setup = xaxi_pcie_setup, + .scan = xaxi_pcie_scan_bus, + .map_irq = xaxi_pcie_map_irq, +}; + +static int __init xaxi_pcie_init(void) +{ + int err; + int init = 0; + struct device_node *node; + + for_each_matching_node(node, xaxi_pcie_match) { + err = xaxi_pcie_of_probe(node); + if (err) { + pr_err("%s: Root Port Probe failed\n", __func__); + + return err; + } + pr_info("AXI PCIe Root Port Probe Successful\n"); + init++; + } + + if (init) + pci_common_init(&xaxi_pcie_hw); + + return 0; +} + +subsys_initcall(xaxi_pcie_init); Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/xaxipcie-msi.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/xaxipcie-msi.c 2014-07-20 22:06:34.382338279 +0200 @@ -0,0 +1,186 @@ +/* + * Xilinx PCIe IP hardware MSI initialisation + * + * Copyright (c) 2012 Xilinx, Inc. + * + * This program has adopted some work from PCI/PCIE support for AMCC + * PowerPC boards written by Benjamin Herrenschmidt. + * Copyright 2007 Ben. Herrenschmidt , IBM Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include + +#define XILINX_NUM_MSI_IRQS 128 + +static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS); + +static unsigned long xaxipcie_msg_addr; +static struct irq_domain *xaxipcie_irq_domain; +static int xaxipcie_msi_irq_base; + +/* Dynamic irq allocate and deallocation */ + +/** + * create_irq- Dynamic irq allocate + * void + * + * @return: Interrupt number allocated/ error + * + * @note: None + */ +int create_irq(void) +{ + int irq, pos; +again: + pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); + + irq = irq_find_mapping(xaxipcie_irq_domain, pos); + + /* test_and_set_bit operates on 32-bits at a time */ + if (test_and_set_bit(pos, msi_irq_in_use)) + goto again; + + dynamic_irq_init(irq); + set_irq_flags(irq, IRQF_VALID); + + return irq; +} + +/** + * destroy_irq- Dynamic irq de-allocate + * @irq: Interrupt number to de-allocate + * + * @return: None + * + * @note: None + */ +void destroy_irq(unsigned int irq) +{ + int pos = irq - xaxipcie_msi_irq_base; + + dynamic_irq_cleanup(irq); + + clear_bit(pos, msi_irq_in_use); +} + +/** + * arch_teardown_msi_irq-Teardown the Interrupt + * @irq: Interrupt number to teardown + * + * @return: None + * + * @note: This function is called when pci_disable_msi is called + */ +void arch_teardown_msi_irq(unsigned int irq) +{ + destroy_irq(irq); +} + +/** + * xilinx_msi_nop-No operation handler + * @irq: Interrupt number + * + * @return: None + * + * @note: None + */ +static void xilinx_msi_nop(struct irq_data *d) +{ + return; +} + +static struct irq_chip xilinx_msi_chip = { + .name = "PCIe-MSI", + .irq_ack = xilinx_msi_nop, + .irq_enable = unmask_msi_irq, + .irq_disable = mask_msi_irq, + .irq_mask = mask_msi_irq, + .irq_unmask = unmask_msi_irq, +}; + +/** + * arch_setup_msi_irq-Setup MSI interrupt + * @pdev: Pointer to current pci device structure + * @desc: Pointer to MSI description structure + * + * @return: Error/ no-error + * + * @note: This function is called when pci_enable_msi is called + */ +int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) +{ + int irq = create_irq(); + struct msi_msg msg; + + if (irq < 0) + return irq; + + irq_set_msi_desc(irq, desc); + + msg.address_hi = 0x00000000; + msg.address_lo = xaxipcie_msg_addr; + msg.data = irq; + + pr_debug("irq %d addr_hi %08x low %08x data %08x\n", + irq, msg.address_hi, msg.address_lo, msg.data); + + write_msi_msg(irq, &msg); + + irq_set_chip_and_handler(irq, &xilinx_msi_chip, handle_simple_irq); + + return 0; +} + + +/** + * xaxipcie_alloc_msi_irqdescs - allocate msi irq descs + * @node: Pointer to device node structure + * @msg_addr: PCIe MSI message address + * + * @return: Allocated MSI IRQ Base/ error + * + * @note: This function is called when xaxipcie_init_port() is called + */ +int xaxipcie_alloc_msi_irqdescs(struct device_node *node, + unsigned long msg_addr) +{ + /* Store the PCIe MSI message address */ + xaxipcie_msg_addr = msg_addr; + + /* Allocate MSI IRQ descriptors */ + xaxipcie_msi_irq_base = irq_alloc_descs(-1, 0, + XILINX_NUM_MSI_IRQS, 0); + + if (xaxipcie_msi_irq_base < 0) + return -ENODEV; + + /* Register IRQ domain */ + xaxipcie_irq_domain = irq_domain_add_legacy(node, + XILINX_NUM_MSI_IRQS, + xaxipcie_msi_irq_base, + 0, &irq_domain_simple_ops, NULL); + + if (!xaxipcie_irq_domain) + return -ENOMEM; + + return xaxipcie_msi_irq_base; +} +EXPORT_SYMBOL(xaxipcie_alloc_msi_irqdescs); Index: linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/zynq_ocm.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/arm/mach-zynq/zynq_ocm.c 2014-07-20 22:06:34.390338147 +0200 @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2013 Xilinx + * + * Based on "Generic on-chip SRAM allocation driver" + * + * Copyright (C) 2012 Philipp Zabel, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" + +#define ZYNQ_OCM_HIGHADDR 0xfffc0000 +#define ZYNQ_OCM_LOWADDR 0x0 +#define ZYNQ_OCM_BLOCK_SIZE 0x10000 +#define ZYNQ_OCM_BLOCKS 4 +#define ZYNQ_OCM_GRANULARITY 32 + +#define ZYNQ_OCM_PARITY_CTRL 0x0 +#define ZYNQ_OCM_PARITY_ENABLE 0x1e + +#define ZYNQ_OCM_PARITY_ERRADDRESS 0x4 + +#define ZYNQ_OCM_IRQ_STS 0x8 +#define ZYNQ_OCM_IRQ_STS_ERR_MASK 0x7 + +struct zynq_ocm_dev { + void __iomem *base; + int irq; + struct gen_pool *pool; + struct resource res[ZYNQ_OCM_BLOCKS]; +}; + +/** + * zynq_ocm_irq_handler - Interrupt service routine of the OCM controller + * @irq: IRQ number + * @data: Pointer to the zynq_ocm_dev structure + * + * returns: IRQ_HANDLED always + */ +static irqreturn_t zynq_ocm_irq_handler(int irq, void *data) +{ + u32 sts; + u32 err_addr; + struct zynq_ocm_dev *zynq_ocm = data; + + /* check status */ + sts = readl(zynq_ocm->base + ZYNQ_OCM_IRQ_STS); + if (sts & ZYNQ_OCM_IRQ_STS_ERR_MASK) { + /* check error address */ + err_addr = readl(zynq_ocm->base + ZYNQ_OCM_PARITY_ERRADDRESS); + pr_err("%s: OCM err intr generated at 0x%04x (stat: 0x%08x).", + __func__, err_addr, sts & ZYNQ_OCM_IRQ_STS_ERR_MASK); + } + pr_warn("%s: Interrupt generated by OCM, but no error is found.", + __func__); + + return IRQ_HANDLED; +} + +/** + * zynq_ocm_probe - Probe method for the OCM driver + * @pdev: Pointer to the platform_device structure + * + * This function initializes the driver data structures and the hardware. + * + * returns: 0 on success and error value on failure + */ +static int zynq_ocm_probe(struct platform_device *pdev) +{ + int ret; + struct zynq_ocm_dev *zynq_ocm; + u32 i, ocm_config, curr; + struct resource *res; + + ocm_config = zynq_slcr_get_ocm_config(); + + zynq_ocm = devm_kzalloc(&pdev->dev, sizeof(*zynq_ocm), GFP_KERNEL); + if (!zynq_ocm) + return -ENOMEM; + + zynq_ocm->pool = devm_gen_pool_create(&pdev->dev, + ilog2(ZYNQ_OCM_GRANULARITY), -1); + if (!zynq_ocm->pool) + return -ENOMEM; + + curr = 0; /* For storing current struct resource for OCM */ + for (i = 0; i < ZYNQ_OCM_BLOCKS; i++) { + u32 base, start, end; + + /* Setup base address for 64kB OCM block */ + if (ocm_config & BIT(i)) + base = ZYNQ_OCM_HIGHADDR; + else + base = ZYNQ_OCM_LOWADDR; + + /* Calculate start and end block addresses */ + start = i * ZYNQ_OCM_BLOCK_SIZE + base; + end = start + (ZYNQ_OCM_BLOCK_SIZE - 1); + + /* Concatenate OCM blocks together to get bigger pool */ + if (i > 0 && start == (zynq_ocm->res[curr - 1].end + 1)) { + zynq_ocm->res[curr - 1].end = end; + } else { +#ifdef CONFIG_SMP + /* + * OCM block if placed at 0x0 has special meaning + * for SMP because jump trampoline is added there. + * Ensure that this address won't be allocated. + */ + if (!base) { + u32 trampoline_code_size = + &zynq_secondary_trampoline_end - + &zynq_secondary_trampoline; + dev_dbg(&pdev->dev, + "Allocate reset vector table %dB\n", + trampoline_code_size); + /* postpone start offset */ + start += trampoline_code_size; + } +#endif + /* First resource is always initialized */ + zynq_ocm->res[curr].start = start; + zynq_ocm->res[curr].end = end; + zynq_ocm->res[curr].flags = IORESOURCE_MEM; + curr++; /* Increment curr value */ + } + dev_dbg(&pdev->dev, "OCM block %d, start %x, end %x\n", + i, start, end); + } + + /* + * Separate pool allocation from OCM block detection to ensure + * the biggest possible pool. + */ + for (i = 0; i < ZYNQ_OCM_BLOCKS; i++) { + unsigned long size; + void __iomem *virt_base; + + /* Skip all zero size resources */ + if (zynq_ocm->res[i].end == 0) + break; + dev_dbg(&pdev->dev, "OCM resources %d, start %x, end %x\n", + i, zynq_ocm->res[i].start, zynq_ocm->res[i].end); + size = resource_size(&zynq_ocm->res[i]); + virt_base = devm_ioremap_resource(&pdev->dev, + &zynq_ocm->res[i]); + if (IS_ERR(virt_base)) + return PTR_ERR(virt_base); + + ret = gen_pool_add_virt(zynq_ocm->pool, + (unsigned long)virt_base, + zynq_ocm->res[i].start, size, -1); + if (ret < 0) { + dev_err(&pdev->dev, "Gen pool failed\n"); + return ret; + } + dev_info(&pdev->dev, "ZYNQ OCM pool: %ld KiB @ 0x%p\n", + size / 1024, virt_base); + } + + /* Get OCM config space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + zynq_ocm->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(zynq_ocm->base)) + return PTR_ERR(zynq_ocm->base); + + /* Allocate OCM parity IRQ */ + zynq_ocm->irq = platform_get_irq(pdev, 0); + if (zynq_ocm->irq < 0) { + dev_err(&pdev->dev, "irq resource not found\n"); + return zynq_ocm->irq; + } + ret = devm_request_irq(&pdev->dev, zynq_ocm->irq, zynq_ocm_irq_handler, + 0, pdev->name, zynq_ocm); + if (ret != 0) { + dev_err(&pdev->dev, "request_irq failed\n"); + return ret; + } + + /* Enable parity errors */ + writel(ZYNQ_OCM_PARITY_ENABLE, zynq_ocm->base + ZYNQ_OCM_PARITY_CTRL); + + platform_set_drvdata(pdev, zynq_ocm); + + return 0; +} + +/** + * zynq_ocm_remove - Remove method for the OCM driver + * @pdev: Pointer to the platform_device structure + * + * This function is called if a device is physically removed from the system or + * if the driver module is being unloaded. It frees all resources allocated to + * the device. + * + * returns: 0 on success and error value on failure + */ +static int zynq_ocm_remove(struct platform_device *pdev) +{ + struct zynq_ocm_dev *zynq_ocm = platform_get_drvdata(pdev); + + if (gen_pool_avail(zynq_ocm->pool) < gen_pool_size(zynq_ocm->pool)) + dev_dbg(&pdev->dev, "removed while SRAM allocated\n"); + + return 0; +} + +static struct of_device_id zynq_ocm_dt_ids[] = { + { .compatible = "xlnx,zynq-ocm-1.0" }, + { /* end of table */ } +}; + +static struct platform_driver zynq_ocm_driver = { + .driver = { + .name = "zynq_ocm", + .of_match_table = zynq_ocm_dt_ids, + }, + .probe = zynq_ocm_probe, + .remove = zynq_ocm_remove, +}; + +static int __init zynq_ocm_init(void) +{ + return platform_driver_register(&zynq_ocm_driver); +} + +arch_initcall(zynq_ocm_init); Index: linux-3.12.24-rt38-xilinx/arch/arm/mm/mmu.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/arm/mm/mmu.c 2014-07-20 22:05:50.277065944 +0200 +++ linux-3.12.24-rt38-xilinx/arch/arm/mm/mmu.c 2014-07-20 22:06:34.408337850 +0200 @@ -571,8 +571,8 @@ mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; break; } - printk("Memory policy: ECC %sabled, Data cache %s\n", - ecc_mask ? "en" : "dis", cp->policy); + pr_info("Memory policy: %sData cache %s\n", + ecc_mask ? "ECC enabled, " : "", cp->policy); for (i = 0; i < ARRAY_SIZE(mem_types); i++) { struct mem_type *t = &mem_types[i]; Index: linux-3.12.24-rt38-xilinx/arch/microblaze/boot/dts/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/boot/dts/Makefile 2014-07-20 22:05:50.320065235 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/boot/dts/Makefile 2014-07-20 22:06:34.427337536 +0200 @@ -1,6 +1,4 @@ # -# arch/microblaze/boot/Makefile -# obj-y += linked_dtb.o Index: linux-3.12.24-rt38-xilinx/arch/microblaze/include/asm/io.h =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/include/asm/io.h 2014-07-20 22:05:50.323065185 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/include/asm/io.h 2014-07-20 22:06:34.445337239 +0200 @@ -342,4 +342,12 @@ #define iowrite32_rep(p, src, count) \ outsl((unsigned long) (p), (src), (count)) +#define readb_relaxed readb +#define readw_relaxed readw +#define readl_relaxed readl + +#define writeb_relaxed writeb +#define writew_relaxed writew +#define writel_relaxed writel + #endif /* _ASM_MICROBLAZE_IO_H */ Index: linux-3.12.24-rt38-xilinx/arch/microblaze/include/asm/irq.h =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/include/asm/irq.h 2014-07-20 22:05:50.322065202 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/include/asm/irq.h 2014-07-20 22:06:34.455337075 +0200 @@ -9,7 +9,21 @@ #ifndef _ASM_MICROBLAZE_IRQ_H #define _ASM_MICROBLAZE_IRQ_H -#define NR_IRQS (32 + 1) +/* + * Linux IRQ# is currently offset by one to map to the hardware + * irq number. So hardware IRQ0 maps to Linux irq 1. + */ +#define NO_IRQ_OFFSET 1 +#define IRQ_OFFSET NO_IRQ_OFFSET +/* AXI PCIe MSI support */ +#if defined(CONFIG_XILINX_AXIPCIE) && defined(CONFIG_PCI_MSI) +#define IRQ_XILINX_MSI_0 128 +#define XILINX_NUM_MSI_IRQS 32 +#define NR_IRQS (32 + IRQ_XILINX_MSI_0 + IRQ_OFFSET) +#else +#define NR_IRQS (32 + IRQ_OFFSET) +#endif + #include struct pt_regs; Index: linux-3.12.24-rt38-xilinx/arch/microblaze/Kconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/Kconfig 2014-07-20 22:05:50.312065367 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/Kconfig 2014-07-20 22:06:34.466336893 +0200 @@ -29,6 +29,7 @@ select MODULES_USE_ELF_RELA select CLONE_BACKWARDS3 select CLKSRC_OF + select BUILDTIME_EXTABLE_SORT config SWAP def_bool n @@ -82,11 +83,6 @@ bool "MMU support" default n -config NO_MMU - bool - depends on !MMU - default y - comment "Boot options" config CMDLINE_BOOL @@ -250,10 +246,6 @@ endchoice -config KERNEL_PAD - hex "Kernel PAD for unpacking" if ADVANCED_OPTIONS - default "0x80000" if MMU - endmenu source "mm/Kconfig" @@ -279,6 +271,11 @@ bool "Xilinx PCI host bridge support" depends on PCI +config XILINX_AXIPCIE + bool "Xilinx AXI PCIe host bridge support" + depends on PCI + select ARCH_SUPPORTS_MSI + source "drivers/pci/Kconfig" endmenu Index: linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/cpu/cpuinfo.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/kernel/cpu/cpuinfo.c 2014-07-20 22:05:50.316065301 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/cpu/cpuinfo.c 2014-07-20 22:06:34.483336613 +0200 @@ -39,6 +39,7 @@ {"8.30.a", 0x17}, {"8.40.a", 0x18}, {"8.40.b", 0x19}, + {"8.50.a", 0x1a}, {"9.0", 0x1b}, {"9.1", 0x1d}, {NULL, 0}, Index: linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/head.S =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/kernel/head.S 2014-07-20 22:05:50.319065251 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/head.S 2014-07-20 22:06:34.494336431 +0200 @@ -64,6 +64,10 @@ #endif mts rmsr, r0 +/* Disable stack protection from bootloader */ + mts rslr, r0 + addi r8, r0, 0xFFFFFFF + mts rshr, r8 /* * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc' * if the msrclr instruction is not enabled. We use this to detect @@ -176,7 +180,7 @@ /* start to do TLB calculation */ addik r12, r0, _end rsub r12, r3, r12 - addik r12, r12, CONFIG_KERNEL_PAD /* that's the pad */ + addik r12, r12, CONFIG_LOWMEM_SIZE >> PTE_SHIFT /* that's the pad */ or r9, r0, r0 /* TLB0 = 0 */ or r10, r0, r0 /* TLB1 = 0 */ Index: linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/hw_exception_handler.S =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/kernel/hw_exception_handler.S 2014-07-20 22:05:50.318065268 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/hw_exception_handler.S 2014-07-20 22:06:34.634334122 +0200 @@ -147,15 +147,14 @@ or r3, r0, NUM_TO_REG (regnum); /* Shift right instruction depending on available configuration */ - #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0 - #define BSRLI(rD, rA, imm) \ - bsrli rD, rA, imm - #else - #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA) + #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL == 0 /* Only the used shift constants defined here - add more if needed */ #define BSRLI2(rD, rA) \ srl rD, rA; /* << 1 */ \ srl rD, rD; /* << 2 */ + #define BSRLI4(rD, rA) \ + BSRLI2(rD, rA); \ + BSRLI2(rD, rD) #define BSRLI10(rD, rA) \ srl rD, rA; /* << 1 */ \ srl rD, rD; /* << 2 */ \ @@ -170,7 +169,33 @@ #define BSRLI20(rD, rA) \ BSRLI10(rD, rA); \ BSRLI10(rD, rD) + + .macro bsrli, rD, rA, IMM + .if (\IMM) == 2 + BSRLI2(\rD, \rA) + .elseif (\IMM) == 10 + BSRLI10(\rD, \rA) + .elseif (\IMM) == 12 + BSRLI2(\rD, \rA) + BSRLI10(\rD, \rD) + .elseif (\IMM) == 14 + BSRLI4(\rD, \rA) + BSRLI10(\rD, \rD) + .elseif (\IMM) == 20 + BSRLI20(\rD, \rA) + .elseif (\IMM) == 24 + BSRLI4(\rD, \rA) + BSRLI20(\rD, \rD) + .elseif (\IMM) == 28 + BSRLI4(\rD, \rA) + BSRLI4(\rD, \rD) + BSRLI20(\rD, \rD) + .else + .error "BSRLI shift macros \IMM" + .endif + .endm #endif + #endif /* CONFIG_MMU */ .extern other_exception_handler /* Defined in exception.c */ @@ -193,8 +218,8 @@ * - W S REG EXC * * - * STACK FRAME STRUCTURE (for NO_MMU) - * --------------------------------- + * STACK FRAME STRUCTURE (for CONFIG_MMU=n) + * ---------------------------------------- * * +-------------+ + 0 * | MSR | @@ -604,7 +629,7 @@ ex4: tophys(r4,r4) /* Create L1 (pgdir/pmd) address */ - BSRLI(r5,r3, PGDIR_SHIFT - 2) + bsrli r5, r3, PGDIR_SHIFT - 2 andi r5, r5, PAGE_SIZE - 4 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ or r4, r4, r5 @@ -613,7 +638,7 @@ beqi r5, ex2 /* Bail if no table */ tophys(r5,r5) - BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */ + bsrli r6, r3, PTE_SHIFT /* Compute PTE address */ andi r6, r6, PAGE_SIZE - 4 or r5, r5, r6 lwi r4, r5, 0 /* Get Linux PTE */ @@ -705,7 +730,7 @@ ex6: tophys(r4,r4) /* Create L1 (pgdir/pmd) address */ - BSRLI(r5,r3, PGDIR_SHIFT - 2) + bsrli r5, r3, PGDIR_SHIFT - 2 andi r5, r5, PAGE_SIZE - 4 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ or r4, r4, r5 @@ -714,7 +739,7 @@ beqi r5, ex7 /* Bail if no table */ tophys(r5,r5) - BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */ + bsrli r6, r3, PTE_SHIFT /* Compute PTE address */ andi r6, r6, PAGE_SIZE - 4 or r5, r5, r6 lwi r4, r5, 0 /* Get Linux PTE */ @@ -776,7 +801,7 @@ ex9: tophys(r4,r4) /* Create L1 (pgdir/pmd) address */ - BSRLI(r5,r3, PGDIR_SHIFT - 2) + bsrli r5, r3, PGDIR_SHIFT - 2 andi r5, r5, PAGE_SIZE - 4 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ or r4, r4, r5 @@ -785,7 +810,7 @@ beqi r5, ex10 /* Bail if no table */ tophys(r5,r5) - BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */ + bsrli r6, r3, PTE_SHIFT /* Compute PTE address */ andi r6, r6, PAGE_SIZE - 4 or r5, r5, r6 lwi r4, r5, 0 /* Get Linux PTE */ @@ -922,7 +947,7 @@ .ent _unaligned_data_exception _unaligned_data_exception: andi r8, r3, 0x3E0; /* Mask and extract the register operand */ - BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */ + bsrli r8, r8, 2; /* r8 >> 2 = register operand * 8 */ andi r6, r3, 0x400; /* Extract ESR[S] */ bneid r6, ex_sw_vm; andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */ Index: linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/setup.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/kernel/setup.c 2014-07-20 22:05:50.314065334 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/setup.c 2014-07-20 22:06:34.645333941 +0200 @@ -174,7 +174,7 @@ #else if (!msr) { pr_info("!!!Your kernel not setup MSR instruction but "); - pr_cont"CPU have it %x\n", msr); + pr_cont("CPU have it %x\n", msr); } #endif Index: linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/syscall_table.S =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/kernel/syscall_table.S 2014-07-20 22:05:50.317065284 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/syscall_table.S 2014-07-20 22:06:34.656333759 +0200 @@ -192,7 +192,7 @@ .long sys_ni_syscall /* reserved for streams2 */ .long sys_vfork /* 190 */ .long sys_getrlimit - .long sys_mmap_pgoff /* mmap2 */ + .long sys_mmap2 .long sys_truncate64 .long sys_ftruncate64 .long sys_stat64 /* 195 */ Index: linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/sys_microblaze.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/kernel/sys_microblaze.c 2014-07-20 22:05:50.313065351 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/sys_microblaze.c 2014-07-20 22:06:34.665333611 +0200 @@ -33,12 +33,23 @@ #include #include -asmlinkage long sys_mmap(unsigned long addr, unsigned long len, - unsigned long prot, unsigned long flags, - unsigned long fd, off_t pgoff) +SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len, + unsigned long, prot, unsigned long, flags, unsigned long, fd, + off_t, pgoff) { if (pgoff & ~PAGE_MASK) return -EINVAL; return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff >> PAGE_SHIFT); } + +SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, + unsigned long, prot, unsigned long, flags, unsigned long, fd, + unsigned long, pgoff) +{ + if (pgoff & (~PAGE_MASK >> 12)) + return -EINVAL; + + return sys_mmap_pgoff(addr, len, prot, flags, fd, + pgoff >> (PAGE_SHIFT - 12)); +} Index: linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/timer.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/kernel/timer.c 2014-07-20 22:05:50.315065317 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/kernel/timer.c 2014-07-20 22:06:34.676333429 +0200 @@ -148,7 +148,7 @@ static struct irqaction timer_irqaction = { .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER, + .flags = IRQF_TIMER, .name = "timer", .dev_id = &clockevent_xilinx_timer, }; Index: linux-3.12.24-rt38-xilinx/arch/microblaze/pci/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/pci/Makefile 2014-07-20 22:05:50.310065400 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/pci/Makefile 2014-07-20 22:06:34.689333215 +0200 @@ -4,3 +4,5 @@ obj-$(CONFIG_PCI) += pci-common.o indirect_pci.o iomap.o obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o +obj-$(CONFIG_XILINX_AXIPCIE) += xilinx_axipcie.o +obj-$(CONFIG_PCI_MSI) += msi.o Index: linux-3.12.24-rt38-xilinx/arch/microblaze/pci/msi.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/pci/msi.c 2014-07-20 22:06:34.697333083 +0200 @@ -0,0 +1,148 @@ +/* + * Xilinx PCIe IP hardware MSI initialisation + * + * Copyright (c) 2010-2011 Xilinx, Inc. + * + * This program has adopted some work from PCI/PCIE support for AMCC + * PowerPC boards written by Benjamin Herrenschmidt. + * Copyright 2007 Ben. Herrenschmidt , IBM Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include "xilinx_axipcie.h" + +static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS); + +/* + * Dynamic irq allocate and deallocation + */ + +/** +* create_irq- Dynamic irq allocate +* void +* +* @return: Interrupt number allocated/ error +* +* @note: None +*/ +int create_irq(void) +{ + int irq, pos; +again: + pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); + + irq = IRQ_XILINX_MSI_0 + pos; + if (irq > NR_IRQS) + return -ENOSPC; + + /* test_and_set_bit operates on 32-bits at a time */ + if (test_and_set_bit(pos, msi_irq_in_use)) + goto again; + + dynamic_irq_init(irq); + + return irq; +} + +/** +* destroy_irq- Dynamic irq de-allocate +* @irq: Interrupt number to de-allocate +* +* @return: None +* +* @note: None +*/ +void destroy_irq(unsigned int irq) +{ + int pos = irq - IRQ_XILINX_MSI_0; + + dynamic_irq_cleanup(irq); + + clear_bit(pos, msi_irq_in_use); +} + +/** +* arch_teardown_msi_irq-Teardown the Interrupt +* @irq: Interrupt number to teardown +* +* @return: None +* +* @note: This function is called when pci_disable_msi is called +*/ +void arch_teardown_msi_irq(unsigned int irq) +{ + destroy_irq(irq); +} + +/** +* xilinx_msi_nop-No operation handler +* @irq: Interrupt number +* +* @return: None +* +* @note: None +*/ +static void xilinx_msi_nop(struct irq_data *d) +{ + return; +} + +static struct irq_chip xilinx_msi_chip = { + .name = "PCI-MSI", + .irq_ack = xilinx_msi_nop, + .irq_enable = unmask_msi_irq, + .irq_disable = mask_msi_irq, + .irq_mask = mask_msi_irq, + .irq_unmask = unmask_msi_irq, +}; + +/** +* arch_setup_msi_irq-Setup MSI interrupt +* @pdev: Pointer to current pci device structure +* @desc: Pointer to MSI description structure +* +* @return: Error/ no-error +* +* @note: This function is called when pci_enable_msi is called +*/ + +int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) +{ + int irq = create_irq(); + struct msi_msg msg; + + if (irq < 0) + return irq; + + irq_set_msi_desc(irq, desc); + + msg.address_hi = 0x00000000; + msg.address_lo = msg_addr; + msg.data = irq; + + DBG("irq %d addr_hi %08x low %08x data %08x\n", + irq, msg.address_hi, msg.address_lo, msg.data); + + write_msi_msg(irq, &msg); + + irq_set_chip_and_handler(irq, &xilinx_msi_chip, handle_simple_irq); + + return 0; +} Index: linux-3.12.24-rt38-xilinx/arch/microblaze/pci/pci-common.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/microblaze/pci/pci-common.c 2014-07-20 22:05:50.311065383 +0200 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/pci/pci-common.c 2014-07-20 22:06:34.712332835 +0200 @@ -187,7 +187,7 @@ return device_create_file(&pdev->dev, &dev_attr_devspec); } -void pcibios_set_master(struct pci_dev *dev) +void __weak pcibios_set_master(struct pci_dev *dev) { /* No special bus mastering setup handling */ } Index: linux-3.12.24-rt38-xilinx/arch/microblaze/pci/xilinx_axipcie.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/pci/xilinx_axipcie.c 2014-07-20 22:06:34.726332604 +0200 @@ -0,0 +1,840 @@ +/* + * Xilinx AXI PCIe IP hardware initialation, setup and + * configuration spaces access file. + * + * Copyright (c) 2010-2011 Xilinx, Inc. + * + * This program has adopted some work from PCI/PCIE support for AMCC + * PowerPC boards written by Benjamin Herrenschmidt. + * Copyright 2007 Ben. Herrenschmidt , IBM Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "xilinx_axipcie.h" + +static struct xilinx_axipcie_port *xilinx_axipcie_ports; +static unsigned int xilinx_axipcie_port_count; + +static const struct of_device_id xilinx_axipcie_match[] = { + { .compatible = "xlnx,axi-pcie-1.05.a" ,}, + {} +}; + +static int last_bus_on_record; + +#ifdef CONFIG_PCI_MSI +unsigned long msg_addr; +#endif + +/* Macros */ +#define is_link_up(base_address) \ + ((in_le32(((u8 *)base_address) + AXIPCIE_REG_PSCR) & \ + AXIPCIE_REG_PSCR_LNKUP) ? 1 : 0) + +#define bridge_enable(base_address) \ + out_le32((((u8 *)base_address) + AXIPCIE_REG_RPSC), \ + (in_le32(((u8 *)base_address) + AXIPCIE_REG_RPSC) | \ + AXIPCIE_REG_RPSC_BEN)) + +/** + * xilinx_get_axipcie_ip_config_info - Read info from device tree + * @dev: A pointer to device node to read from + * @ip_config_info: A pointer to xilinx_pcie_node struct to write device tree + * info into to. + * + * @return: Error / no error + * + * @note: Read related info from device tree + */ +int xilinx_get_axipcie_ip_config_info(struct device_node *dev, + struct xilinx_axipcie_node *ip_config_info) +{ + u32 *ip_setup_parameter; + u32 rlen; + + ip_config_info->number_of_instances = 1; + + ip_setup_parameter = (u32 *) of_get_property(dev, + "xlnx,device-num", &rlen); + ip_config_info->device_id = 0; + + ip_setup_parameter = (u32 *) of_get_property(dev, + "xlnx,include-rc", &rlen); + + if (ip_setup_parameter) + ip_config_info->device_type = be32_to_cpup(ip_setup_parameter); + else + return -ENODEV; + + ip_setup_parameter = (u32 *) of_get_property(dev, + "reg", &rlen); + + if (ip_setup_parameter) { + ip_config_info->reg_base = + be32_to_cpup(ip_setup_parameter); + ip_config_info->reg_len = + be32_to_cpup(ip_setup_parameter + 1); + } else + return -ENODEV; + + ip_setup_parameter = (u32 *) of_get_property(dev, + "xlnx,pciebar-num", &rlen); + + if (ip_setup_parameter) + ip_config_info->bars_num = be32_to_cpup(ip_setup_parameter); + else + return -ENODEV; + + ip_config_info->irq_num = irq_of_parse_and_map(dev, 0); + + /* Get address translation parameters */ + ip_setup_parameter = (u32 *) of_get_property(dev, + "xlnx,pciebar2axibar-0", &rlen); + + if (ip_setup_parameter) + ip_config_info->pcie2axibar_0 = + be32_to_cpup(ip_setup_parameter); + else + return -ENODEV; + + ip_setup_parameter = (u32 *) of_get_property(dev, + "xlnx,pciebar2axibar-1", &rlen); + + if (ip_setup_parameter) + ip_config_info->pcie2axibar_1 = + be32_to_cpup(ip_setup_parameter); + else + ip_config_info->pcie2axibar_1 = 0x0; + + return 0; +} + +/** + * fixup_xilinx_axipcie_bridge + * @dev: A pointer to device pcie device struct + * + * @return: None + * + * @note: A fix up routine to be called by kernel during enumeration + */ +static void fixup_xilinx_axipcie_bridge(struct pci_dev *dev) +{ + struct pci_controller *hose; + int i; + + if (dev->devfn != 0 || dev->bus->self != NULL) + return; + + hose = pci_bus_to_host(dev->bus); + if (hose == NULL) + return; + + if (!of_match_node(xilinx_axipcie_match, hose->dn)) + return; + + /* Hide the PCI host BARs from the kernel as their content doesn't + * fit well in the resource management + */ + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + dev->resource[i].start = dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } +} + +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_xilinx_axipcie_bridge); + +/** + * xilinx_init_axipcie_port - Initialize hardware + * @port: A pointer to a pcie port that needs to be initialized + * + * @return: Error / no error + * + * @note: None + */ +static int xilinx_init_axipcie_port(struct xilinx_axipcie_port *port) +{ + void __iomem *base_addr_remap = NULL; + + /* base_addr_remap = ioremap(port->reg_base, PORT_REG_SIZE); */ + base_addr_remap = ioremap(port->reg_base, port->reg_len); + if (!base_addr_remap) + return -ENOMEM; + + port->base_addr_remap = base_addr_remap; + + /* make sure it is root port before touching header */ + if (port->type) { + + port->header_remap = base_addr_remap; + out_le32((((u8 *)port->base_addr_remap) + PCIE_CFG_CMD), + BUS_MASTER_ENABLE); + } + +#ifdef CONFIG_PCI_MSI + msg_addr = port->reg_base & ~0xFFF; /* 4KB aligned */ + out_le32((((u8 *)port->base_addr_remap) + AXIPCIE_REG_MSIBASE1), + 0x00000000); + out_le32((((u8 *)port->base_addr_remap) + AXIPCIE_REG_MSIBASE2), + msg_addr); +#endif + + port->link = is_link_up(port->base_addr_remap); + if (!port->link) + pr_info("LINK IS DOWN\n"); + else + pr_info("LINK IS UP\n"); + + /* Disable all interrupts*/ + out_le32((((u8 *)port->base_addr_remap) + AXIPCIE_REG_IMR), + ~AXIPCIE_REG_IDR_MASKALL); + /* Clear pending interrupts*/ + out_le32((((u8 *)port->base_addr_remap) + AXIPCIE_REG_IDR), + in_le32(((u8 *)port->base_addr_remap) + AXIPCIE_REG_IDR) & + AXIPCIE_REG_IMR_MASKALL); + /* Enable all interrupts*/ + out_le32((((u8 *)port->base_addr_remap) + AXIPCIE_REG_IMR), + AXIPCIE_REG_IMR_MASKALL); + + /* Bridge enable must be done after enumeration, + but there is no callback defined */ + bridge_enable(port->base_addr_remap); + + return 0; +} + +/** + * xilinx_axipcie_verify_config + * @port: A pointer to a pcie port that needs to be handled + * @bus: Bus structure of current bus + * @devfun: device/function + * + * @return: Error / no error + * + * @note: Make sure we can handle this configuration call on our + * device. + */ +static int xilinx_axipcie_verify_config(struct xilinx_axipcie_port *port, + struct pci_bus *bus, + unsigned int devfn) +{ + static int message; + + /* Endpoint can not generate upstream(remote) config cycles */ + if ((!port->type) && bus->number != port->hose->first_busno) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* Check we are within the mapped range */ + if (bus->number > port->hose->last_busno) { + if (!message) { + printk(KERN_WARNING "Warning! Probing bus %u" + " out of range !\n", bus->number); + message++; + } + return PCIBIOS_DEVICE_NOT_FOUND; + } + + /* The other side of the RC has only one device as well */ + if (bus->number == (port->hose->first_busno + 1) && + PCI_SLOT(devfn) != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* Check if we have a link */ + if (!port->link) + port->link = is_link_up(port->base_addr_remap); + + if ((bus->number != port->hose->first_busno) && !port->link) + return PCIBIOS_DEVICE_NOT_FOUND; + + return 0; +} + +/** + * xilinx_axipcie_get_config_base + * @port: A pointer to a pcie port that needs to be handled + * @bus: Bus structure of current bus + * @devfun: Device/function + * + * @return: Base address of the configuration space needed to be + * accessed. + * + * @note: Get the base address of the configuration space for this + * pcie device. + */ +static void __iomem *xilinx_axipcie_get_config_base( + struct xilinx_axipcie_port *port, + struct pci_bus *bus, + unsigned int devfn) +{ + int relbus; + + relbus = ((bus->number << BUS_LOC_SHIFT) | (devfn << DEV_LOC_SHIFT)); + + if (relbus == 0) + return (void __iomem *)port->header_remap; + + return (void __iomem *)port->hose->cfg_data + relbus; +} + +/** + * xilinx_axipcie_read_config - Read config reg. + * @port: A pointer to a pcie port that needs to be handled + * @bus: Bus structure of current bus + * @devfun: Device/function + * @offset: Offset from base + * @len: Byte/word/dword + * @val: A pointer to value read + * + * @return: Error / no error + * + * + * @note: Read byte/word/dword from pcie device config reg. + */ +static int xilinx_axipcie_read_config(struct pci_bus *bus, + unsigned int devfn, + int offset, + int len, + u32 *val) +{ + struct pci_controller *hose = (struct pci_controller *) bus->sysdata; + struct xilinx_axipcie_port *port = + &xilinx_axipcie_ports[hose->indirect_type]; + void __iomem *addr; + + if (xilinx_axipcie_verify_config(port, bus, devfn) != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + addr = xilinx_axipcie_get_config_base(port, bus, devfn); + + if ((bus->number == 0) && devfn > 0) { + *val = 0xFFFFFFFF; + return PCIBIOS_SUCCESSFUL; + } + + switch (len) { + case 1: + *val = in_8((u8 *)(addr + offset)); + break; + case 2: + *val = in_le16((u16 *)(addr + offset)); + break; + default: + *val = in_le32((u32 *)(addr + offset)); + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +/** + * xilinx_axipcie_write_config - Write config reg. + * @port: A pointer to a pcie port that needs to be handled + * @bus: Bus structure of current bus + * @devfun: Device/function + * @offset: Offset from base + * @len: Byte/word/dword + * @val: Value to be written to device + * + * @return: Error / no error + * + * + * @note: Write byte/word/dword to pcie device config reg. + */ +static int xilinx_axipcie_write_config(struct pci_bus *bus, + unsigned int devfn, + int offset, + int len, + u32 val) +{ + struct pci_controller *hose = (struct pci_controller *) bus->sysdata; + struct xilinx_axipcie_port *port = + &xilinx_axipcie_ports[hose->indirect_type]; + void __iomem *addr; + + if (xilinx_axipcie_verify_config(port, bus, devfn) != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + addr = xilinx_axipcie_get_config_base(port, bus, devfn); + + if ((bus->number == 0) && devfn > 0) + return PCIBIOS_SUCCESSFUL; + + switch (len) { + case 1: + out_8((u8 *)(addr + offset), val); + break; + case 2: + out_le16((u16 *)(addr + offset), val); + break; + default: + out_le32((u32 *)(addr + offset), val); + break; + } + + wmb(); + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops xlnx_pcie_pci_ops = { + .read = xilinx_axipcie_read_config, + .write = xilinx_axipcie_write_config, +}; + +/** + * xilinx_set_bridge_resource - Setup base & limit registers of config space. + * @port: Pointer to a root port + * + * @return: None + * + * @note: None + */ +void xilinx_set_bridge_resource(struct xilinx_axipcie_port *port) +{ + const u32 *ranges; + int rlen; + /* The address cells of PCIe parent node */ + int pna = of_n_addr_cells(port->node); + int np = pna + 5; + u32 pci_space; + unsigned long long pci_addr, size; + struct device_node *dev; + u32 val = 0; + + dev = port->node; + + /* Get ranges property */ + ranges = of_get_property(dev, "ranges", &rlen); + if (ranges == NULL) { + printk(KERN_DEBUG "%s:Didnot get any ranges property\n", + __func__); + return; + } + + while ((rlen -= np * 4) >= 0) { + pci_space = be32_to_cpup(ranges); + pci_addr = of_read_number(ranges + 1, 2); + size = of_read_number(ranges + pna + 3, 2); + + printk(KERN_INFO "%s:pci_space: 0x%08x pci_addr:0x%016llx size:" + "0x%016llx\n", __func__, pci_space, pci_addr, size); + + ranges += np; + + switch ((pci_space >> 24) & 0x3) { + case 1: /* PCI IO space */ + printk(KERN_INFO "%s:Setting resource in IO Space\n", + __func__); + + val = ((pci_addr >> 8) & 0x000000F0) | + ((pci_addr + size - 1) & 0x0000F000); + + out_le32((((u8 *)port->header_remap) + PCIE_CFG_IO), + val); + + val = ((pci_addr >> 16) & 0x0000FFFF) | + ((pci_addr + size - 1) & 0xFFFF0000); + + out_le32((((u8 *)port->header_remap) + + PCIE_CFG_IO_UPPER), val); + + break; + case 2: /* PCI Memory space */ + printk(KERN_INFO "%s:Setting resource in Memory Space\n", + __func__); + val = ((pci_addr >> 16) & 0xfff0) | + ((pci_addr + size - 1) & 0xfff00000); + + /* out_le32((((u8 *)port->header_remap) + PCIE_CFG_MEM), + val); */ + + break; + case 3: /* PCI 64 bits Memory space */ + printk(KERN_INFO "%s:Setting resource in Prefetchable" + " Memory Space\n", __func__); + + val = ((pci_addr >> 16) & 0xfff0) | + ((pci_addr + size - 1) & 0xfff00000); + + out_le32((((u8 *)port->header_remap) + + PCIE_CFG_PREF_MEM), val); + + val = ((pci_addr >> 32) & 0xffffffff); + out_le32((((u8 *)port->header_remap) + + PCIE_CFG_PREF_BASE_UPPER), val); + + val = (((pci_addr + size - 1) >> 32) & 0xffffffff); + out_le32((((u8 *)port->header_remap) + + PCIE_CFG_PREF_LIMIT_UPPER), val); + + break; + } + } + + /* EP initiated memory access */ + out_le32((((u8 *)port->header_remap) + PCIE_CFG_AD1), + port->pcie2axibar_0); + out_le32((((u8 *)port->header_remap) + PCIE_CFG_AD2), + port->pcie2axibar_1); +} + +/** + * xilinx_setup_axipcie_root_port - Setup root port + * @port: Pointer to a root port + * + * @return: Error / no error + * + * @note: This is a root port so set it up accordingly + */ +static int __init xilinx_setup_axipcie_root_port( + struct xilinx_axipcie_port *port) +{ + struct pci_controller *hose = NULL; + u32 val = 0; + + /* Allocate the host controller data structure */ + hose = pcibios_alloc_controller(port->node); + if (!hose) { + iounmap(port->base_addr_remap); + iounmap(port->header_remap); + return -ENOMEM; + } + + hose->indirect_type = port->index; + + /* Get bus range */ + hose->first_busno = last_bus_on_record; + + val = in_le32(((u8 *)port->header_remap) + AXIPCIE_REG_BIR); + val = (val >> 16) & 0x7; + hose->last_busno = (((port->reg_base - port->reg_len - 1) >> 20) + & 0xFF) & val; + + /* Write primary, secondary and subordinate bus numbers */ + val = hose->first_busno; + val |= ((hose->first_busno + 1) << 8); + val |= (hose->last_busno << 16); + + out_le32((((u8 *)port->header_remap) + PCIE_CFG_BUS), val); + last_bus_on_record = hose->last_busno + 1; + + port->ecam_remap = port->header_remap; + + /* Setup config space */ + hose->cfg_addr = port->header_remap; + hose->cfg_data = port->ecam_remap; + hose->ops = &xlnx_pcie_pci_ops; + port->hose = hose; + + xilinx_set_bridge_resource(port); + /* Parse outbound mapping resources */ + pci_process_bridge_OF_ranges(hose, port->node, PRIMARY_BUS); + + return 0; +} + +/** + * Interrupt handler + */ +static irqreturn_t xilinx_axipcie_intr_handler(int irq, void *data) +{ + struct xilinx_axipcie_port *port = (struct xilinx_axipcie_port *)data; + u32 val = 0, mask = 0; + u32 status; + u32 msi_addr = 0; + u32 msi_data = 0; + + /* Read interrupt decode and mask registers */ + val = in_le32(((u8 *)port->header_remap) + AXIPCIE_REG_IDR); + mask = in_le32(((u8 *)port->header_remap) + AXIPCIE_REG_IMR); + + status = val & mask; + if (!status) + return IRQ_NONE; + + if (status & AXIPCIE_INTR_LINK_DOWN) + printk(KERN_ERR "Link Down\n"); + + if (status & AXIPCIE_INTR_ECRC_ERR) + printk(KERN_WARNING "ECRC failed\n"); + + if (status & AXIPCIE_INTR_STR_ERR) + printk(KERN_WARNING "Streaming error\n"); + + if (status & AXIPCIE_INTR_HOT_RESET) + printk(KERN_INFO "Hot reset\n"); + + if (status & AXIPCIE_INTR_CFG_TIMEOUT) + printk(KERN_WARNING "ECAM access timeout\n"); + + if (status & AXIPCIE_INTR_CORRECTABLE) { + printk(KERN_WARNING "Correctable error message\n"); + val = in_le32(((u8 *)port->header_remap) + + AXIPCIE_REG_RPEFR); + if (val & (1 << 18)) { + out_le32((((u8 *)port->base_addr_remap) + + AXIPCIE_REG_RPEFR), 0xFFFFFFFF); + DBG("Requester ID %d\n", (val & 0xffff)); + } + } + + if (status & AXIPCIE_INTR_NONFATAL) { + printk(KERN_WARNING "Non fatal error message\n"); + val = in_le32(((u8 *)port->header_remap) + + AXIPCIE_REG_RPEFR); + if (val & (1 << 18)) { + out_le32((((u8 *)port->base_addr_remap) + + AXIPCIE_REG_RPEFR), 0xFFFFFFFF); + DBG("Requester ID %d\n", (val & 0xffff)); + } + } + + if (status & AXIPCIE_INTR_FATAL) { + printk(KERN_WARNING "Fatal error message\n"); + val = in_le32(((u8 *)port->header_remap) + + AXIPCIE_REG_RPEFR); + if (val & (1 << 18)) { + out_le32((((u8 *)port->base_addr_remap) + + AXIPCIE_REG_RPEFR), 0xFFFFFFFF); + DBG("Requester ID %d\n", (val & 0xffff)); + } + } + + if (status & AXIPCIE_INTR_INTX) { + /* INTx interrupt received */ + val = in_le32(((u8 *)port->header_remap) + AXIPCIE_REG_RPIFR1); + + /* Check whether interrupt valid */ + if (!(val & (1 << 31))) { + printk(KERN_WARNING "RP Intr FIFO1 read error\n"); + return IRQ_HANDLED; + } + + /* Check MSI or INTX */ + if (!(val & (1 << 30))) { + if (val & (1 << 29)) + DBG("INTx assert\n"); + else + DBG("INTx deassert\n"); + } + + /* Clear interrupt FIFO register 1 */ + out_le32((((u8 *)port->base_addr_remap) + AXIPCIE_REG_RPIFR1), + 0xFFFFFFFF); + } + + if (status & AXIPCIE_INTR_MSI) { + /* MSI Interrupt */ + val = in_le32(((u8 *)port->header_remap) + AXIPCIE_REG_RPIFR1); + + if (!(val & (1 << 31))) { + printk(KERN_WARNING "RP Intr FIFO1 read error\n"); + return IRQ_HANDLED; + } + + if (val & (1 << 30)) { + msi_addr = (val >> 16) & 0x7FF; + msi_data = in_le32(((u8 *)port->header_remap) + + AXIPCIE_REG_RPIFR2) & 0xFFFF; + DBG("%s: msi_addr %08x msi_data %08x\n", + __func__, msi_addr, msi_data); + } + + /* Clear interrupt FIFO register 1 */ + out_le32((((u8 *)port->base_addr_remap) + AXIPCIE_REG_RPIFR1), + 0xFFFFFFFF); +#ifdef CONFIG_PCI_MSI + /* Handle MSI Interrupt */ + if (msi_data >= IRQ_XILINX_MSI_0) + generic_handle_irq(msi_data); +#endif + } + + if (status & AXIPCIE_INTR_SLV_UNSUPP) + printk(KERN_WARNING "Slave unsupported request\n"); + + if (status & AXIPCIE_INTR_SLV_UNEXP) + printk(KERN_WARNING "Slave unexpected completion\n"); + + if (status & AXIPCIE_INTR_SLV_COMPL) + printk(KERN_WARNING "Slave completion timeout\n"); + + if (status & AXIPCIE_INTR_SLV_ERRP) + printk(KERN_WARNING "Slave Error Poison\n"); + + if (status & AXIPCIE_INTR_SLV_CMPABT) + printk(KERN_WARNING "Slave Completer Abort\n"); + + if (status & AXIPCIE_INTR_SLV_ILLBUR) + printk(KERN_WARNING "Slave Illegal Burst\n"); + + if (status & AXIPCIE_INTR_MST_DECERR) + printk(KERN_WARNING "Master decode error\n"); + + if (status & AXIPCIE_INTR_MST_SLVERR) + printk(KERN_WARNING "Master slave error\n"); + + if (status & AXIPCIE_INTR_MST_ERRP) + printk(KERN_WARNING "Master error poison\n"); + + /* Clear the Interrupt Decode register */ + out_le32((((u8 *)port->base_addr_remap) + AXIPCIE_REG_IDR), status); + + return IRQ_HANDLED; +} + +/** + * xilinx_probe_axipcie_node + * @np: Pointer to device node to be probed + * + * @return: Error / no error + * + * @note: Find out how this pcie node is configured + */ +static int __init xilinx_probe_axipcie_node(struct device_node *np) +{ + struct xilinx_axipcie_port *port; + struct xilinx_axipcie_node ip_setup_info; + int portno; + int error; + int ret; + + printk(KERN_INFO "Probing Xilinx PCI Express root complex device\n"); + + error = xilinx_get_axipcie_ip_config_info(np , &ip_setup_info); + + if (error) { + printk(KERN_INFO "Error while getting pcie config info\n"); + return error; + } + + if (!xilinx_axipcie_port_count) { + xilinx_axipcie_port_count = ip_setup_info.number_of_instances; + + if (xilinx_axipcie_port_count) { + + xilinx_axipcie_ports = + kzalloc(xilinx_axipcie_port_count * + sizeof(struct xilinx_axipcie_port), GFP_KERNEL); + + if (!xilinx_axipcie_ports) { + printk(KERN_INFO "Memory allocation failed\n"); + return -ENOMEM; + } + } else /* not suppose to be here + * when we don't have pcie ports */ + return -ENODEV; + } + + /* Initialize this port vital info. struct */ + portno = ip_setup_info.device_id; + + port = &xilinx_axipcie_ports[portno]; + port->node = of_node_get(np); + port->index = portno; + port->type = ip_setup_info.device_type; + port->reg_base = ip_setup_info.reg_base; + port->reg_len = ip_setup_info.reg_len; + port->bars_num = ip_setup_info.bars_num; + port->irq_num = ip_setup_info.irq_num; + port->header_addr = port->reg_base + AXIPCIE_LOCAL_CNFG_BASE; + port->pcie2axibar_0 = ip_setup_info.pcie2axibar_0; + port->pcie2axibar_1 = ip_setup_info.pcie2axibar_1; + + irq_set_chip_data(port->irq_num, port); + + /* initialize hardware */ + error = xilinx_init_axipcie_port(port); + if (error) { + printk(KERN_INFO "Error while initialize pcie port\n"); + return error; + } + + /* Register interrupt handler */ + ret = request_irq(port->irq_num, xilinx_axipcie_intr_handler, + IRQF_SHARED, "xaxipcie", port); + if (ret) { + printk(KERN_ERR "%s: Could not allocate interrupt\n", __func__); + return ret; + } + + /* Setup hose data structure */ + if (port->type) { + error = xilinx_setup_axipcie_root_port(port); + if (error) { + printk(KERN_INFO "Error while initialize " + "pcie root port\n"); + return error; + } + } + + return 0; +} + +/** + * pcibios_set_master - Architecture specific function + * @dev: A pointer to device pcie device struct + * + * @return: Error / no error + * @note: Enables Bridge Enable bit during the rescan process + */ +void pcibios_set_master(struct pci_dev *dev) +{ + struct pci_controller *hose = + (struct pci_controller *) dev->bus->sysdata; + struct xilinx_axipcie_port *port = + &xilinx_axipcie_ports[hose->indirect_type]; + + if (port->link) + bridge_enable(port->base_addr_remap); +} + +/** + * xilinx_find_axipcie_nodes - Entry function + * void + * + * @return: Error / no error + * @note: Find pcie nodes in device tree + */ +static int __init xilinx_find_axipcie_nodes(void) +{ + struct device_node *np; + const struct of_device_id *matches = xilinx_axipcie_match; + int error = 0; + + printk(KERN_INFO "Initialising Xilinx PCI Express root" + " complex device\n"); + for_each_matching_node(np, matches) { + error = xilinx_probe_axipcie_node(np); + if (error) + return error; + } + return 0; +} + +arch_initcall(xilinx_find_axipcie_nodes); Index: linux-3.12.24-rt38-xilinx/arch/microblaze/pci/xilinx_axipcie.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/microblaze/pci/xilinx_axipcie.h 2014-07-20 22:06:34.734332472 +0200 @@ -0,0 +1,156 @@ +/* + * Header file for Xilinx AXI PCIe IP driver. + * + * Copyright (c) 2010-2011 Xilinx, Inc. + * + * This program has adopted some work from PCI/PCIE support for AMCC + * PowerPC boards written by Benjamin Herrenschmidt. + * Copyright 2007 Ben. Herrenschmidt , IBM Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef XILINX_AXIPCIE_H_ +#define XILINX_AXIPCIE_H_ + +/* Register definitions */ +#define PCIE_CFG_CMD 0x00000004 +#define PCIE_CFG_CLS 0x00000008 +#define PCIE_CFG_HDR 0x0000000C +#define PCIE_CFG_AD1 0x00000010 +#define PCIE_CFG_AD2 0x00000014 +#define PCIE_CFG_BUS 0x00000018 +#define PCIE_CFG_IO 0x0000001C +#define PCIE_CFG_MEM 0x00000020 +#define PCIE_CFG_PREF_MEM 0x00000024 +#define PCIE_CFG_PREF_BASE_UPPER 0x00000028 +#define PCIE_CFG_PREF_LIMIT_UPPER 0x0000002c +#define PCIE_CFG_IO_UPPER 0x00000030 + +#define AXIPCIE_REG_VSECC 0x00000128 +#define AXIPCIE_REG_VSECH 0x0000012c +#define AXIPCIE_REG_BIR 0x00000130 +#define AXIPCIE_REG_BSCR 0x00000134 +#define AXIPCIE_REG_IDR 0x00000138 +#define AXIPCIE_REG_IMR 0x0000013c +#define AXIPCIE_REG_BLR 0x00000140 +#define AXIPCIE_REG_PSCR 0x00000144 +#define AXIPCIE_REG_RPSC 0x00000148 +#define AXIPCIE_REG_MSIBASE1 0x0000014c +#define AXIPCIE_REG_MSIBASE2 0x00000150 +#define AXIPCIE_REG_RPEFR 0x00000154 +#define AXIPCIE_REG_RPIFR1 0x00000158 +#define AXIPCIE_REG_RPIFR2 0x0000015c +#define AXIPCIE_REG_VSECC2 0x00000200 +#define AXIPCIE_REG_VSECH2 0x00000204 + +/* Interrupt register defines */ +#define AXIPCIE_INTR_LINK_DOWN (1 << 0) +#define AXIPCIE_INTR_ECRC_ERR (1 << 1) +#define AXIPCIE_INTR_STR_ERR (1 << 2) +#define AXIPCIE_INTR_HOT_RESET (1 << 3) +#define AXIPCIE_INTR_CFG_COMPL (7 << 5) +#define AXIPCIE_INTR_CFG_TIMEOUT (1 << 8) +#define AXIPCIE_INTR_CORRECTABLE (1 << 9) +#define AXIPCIE_INTR_NONFATAL (1 << 10) +#define AXIPCIE_INTR_FATAL (1 << 11) +#define AXIPCIE_INTR_INTX (1 << 16) +#define AXIPCIE_INTR_MSI (1 << 17) +#define AXIPCIE_INTR_SLV_UNSUPP (1 << 20) +#define AXIPCIE_INTR_SLV_UNEXP (1 << 21) +#define AXIPCIE_INTR_SLV_COMPL (1 << 22) +#define AXIPCIE_INTR_SLV_ERRP (1 << 23) +#define AXIPCIE_INTR_SLV_CMPABT (1 << 24) +#define AXIPCIE_INTR_SLV_ILLBUR (1 << 25) +#define AXIPCIE_INTR_MST_DECERR (1 << 26) +#define AXIPCIE_INTR_MST_SLVERR (1 << 27) +#define AXIPCIE_INTR_MST_ERRP (1 << 28) + +#define BUS_LOC_SHIFT 20 +#define DEV_LOC_SHIFT 12 +#define PRIMARY_BUS 1 +#define PORT_REG_SIZE 0x1000 +#define PORT_HEADER_SIZE 0x128 + +#define AXIPCIE_LOCAL_CNFG_BASE 0x00000000 +#define AXIPCIE_REG_BASE 0x00000128 +#define AXIPCIE_REG_PSCR_LNKUP 0x00000800 +#define AXIPCIE_REG_IMR_MASKALL 0x1FF30FED +#define AXIPCIE_REG_IDR_MASKALL 0xFFFFFFFF +#define AXIPCIE_REG_RPSC_BEN 0x00000001 +#define BUS_MASTER_ENABLE 0x00000004 + +/* debug */ +//#define XILINX_AXIPCIE_DEBUG +#ifdef XILINX_AXIPCIE_DEBUG +#define DBG(x...) ((void)printk(x)) +#else +#define DBG(x...) \ + do { \ + } while(0) +#endif + +/* Xilinx CR# 657412 */ +/* Byte swapping */ +#define xpcie_out_be32(a, v) __raw_writel(__cpu_to_be32(v), (a)) +#define xpcie_out_be16(a, v) __raw_writew(__cpu_to_be16(v), (a)) + +#define xpcie_in_be32(a) __be32_to_cpu(__raw_readl(a)) +#define xpcie_in_be16(a) __be16_to_cpu(__raw_readw(a)) + +#ifdef CONFIG_PCI_MSI +extern unsigned long msg_addr; +#endif + +struct xilinx_axipcie_node { + u32 number_of_instances; + u32 device_id; + u32 device_type; + u32 ecam_base; + u32 ecam_high; + u32 baseaddr; + u32 highaddr; + u32 bars_num; + u32 irq_num; + u32 reg_base; + u32 reg_len; + u32 pcie2axibar_0; + u32 pcie2axibar_1; +}; + +struct xilinx_axipcie_port { + struct pci_controller *hose; + struct device_node *node; + u32 reg_base; + u32 reg_len; + u32 ecam_base; + u32 ecam_high; + u32 baseaddr; + u32 highaddr; + u32 header_addr; + u8 index; + u8 type; + u8 link; + u8 bars_num; + u32 irq_num; + unsigned int __iomem *base_addr_remap; + unsigned int __iomem *header_remap; + unsigned int __iomem *ecam_remap; + u32 pcie2axibar_0; + u32 pcie2axibar_1; +}; + +#endif /* XILINX_AXIPCIE_H_ */ Index: linux-3.12.24-rt38-xilinx/arch/powerpc/boot/dts/virtex405-ml405.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/boot/dts/virtex405-ml405.dts 2014-07-20 22:06:34.749332225 +0200 @@ -0,0 +1,171 @@ +/* + * This file supports the Xilinx ML405 board with the 405 processor. + * A reference design for the FPGA is provided at http://git.xilinx.com. + * + * (C) Copyright 2008 Xilinx, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,virtex"; + model = "testing"; + DDR_SDRAM: memory@0 { + device_type = "memory"; + reg = < 0 0x8000000 >; + } ; + chosen { + bootargs = "console=ttyS0 ip=on root=/dev/ram"; + linux,stdout-path = "/plb@0/serial@83e00000"; + } ; + cpus { + #address-cells = <1>; + #cpus = <1>; + + #size-cells = <0>; + ppc405_0: cpu@0 { + clock-frequency = <0x11e1a300>; + compatible = "PowerPC,405", "ibm,ppc405"; + d-cache-line-size = <0x20>; + d-cache-size = <0x4000>; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x4000>; + model = "PowerPC,405"; + reg = <0>; + timebase-frequency = <0x11e1a300>; + xlnx,apu-control = <0xde00>; + xlnx,apu-udi-1 = <0xa18983>; + xlnx,apu-udi-2 = <0xa38983>; + xlnx,apu-udi-3 = <0xa589c3>; + xlnx,apu-udi-4 = <0xa789c3>; + xlnx,apu-udi-5 = <0xa98c03>; + xlnx,apu-udi-6 = <0xab8c03>; + xlnx,apu-udi-7 = <0xad8c43>; + xlnx,apu-udi-8 = <0xaf8c43>; + xlnx,deterministic-mult = <0>; + xlnx,disable-operand-forwarding = <1>; + xlnx,fastest-plb-clock = "DPLB0"; + xlnx,generate-plb-timespecs = <1>; + xlnx,mmu-enable = <1>; + xlnx,pvr-high = <0>; + xlnx,pvr-low = <0>; + } ; + } ; + plb: plb@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,plb-v46-1.02.a", "simple-bus"; + ranges ; + IIC_EEPROM: i2c@81600000 { + compatible = "xlnx,xps-iic-2.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 4 2 >; + reg = < 0x81600000 0x10000 >; + xlnx,clk-freq = <0x5f5e100>; + xlnx,family = "virtex4"; + xlnx,gpo-width = <1>; + xlnx,iic-freq = <0x186a0>; + xlnx,scl-inertial-delay = <0>; + xlnx,sda-inertial-delay = <0>; + xlnx,ten-bit-adr = <0>; + } ; + LEDs_4Bit: gpio@81400000 { + compatible = "xlnx,xps-gpio-1.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 5 2 >; + reg = < 0x81400000 0x10000 >; + xlnx,all-inputs = <0>; + xlnx,all-inputs-2 = <0>; + xlnx,dout-default = <0>; + xlnx,dout-default-2 = <0>; + xlnx,family = "virtex4"; + xlnx,gpio-width = <4>; + xlnx,interrupt-present = <1>; + xlnx,is-bidir = <1>; + xlnx,is-bidir-2 = <1>; + xlnx,is-dual = <0>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + } ; + RS232_Uart: serial@83e00000 { + compatible = "ns16550"; + device_type = "serial"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 6 2 >; + reg = < 0x83e00000 0x10000 >; + reg-offset = <0x1003>; + reg-shift = <2>; + clock-frequency = <0x05f5e100>; + xlnx,family = "virtex4"; + xlnx,has-external-rclk = <0>; + xlnx,has-external-xin = <0>; + xlnx,is-a-16550 = <1>; + } ; + SysACE_CompactFlash: sysace@83600000 { + compatible = "xlnx,xps-sysace-1.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 3 2 >; + reg = < 0x83600000 0x10000 >; + xlnx,family = "virtex4"; + xlnx,mem-width = <0x10>; + } ; + TriMode_MAC_GMII: xps-ll-temac@81c00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,compound"; + ethernet@81c00000 { + compatible = "xlnx,xps-ll-temac-1.01.a"; + device_type = "network"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 2 2 >; + llink-connected = <&PIM2>; + local-mac-address = [ 02 00 00 00 00 01 ]; + reg = < 0x81c00000 0x40 >; + xlnx,bus2core-clk-ratio = <1>; + xlnx,phy-type = <1>; + xlnx,phyaddr = <1>; + xlnx,rxcsum = <0>; + xlnx,rxfifo = <0x1000>; + xlnx,temac-type = <1>; + xlnx,txcsum = <0>; + xlnx,txfifo = <0x1000>; + } ; + } ; + mpmc@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,mpmc-4.00.a"; + PIM2: sdma@84600100 { + compatible = "xlnx,ll-dma-1.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 1 2 0 2 >; + reg = < 0x84600100 0x80 >; + } ; + } ; + xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 { + compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; + reg = < 0xffffe000 0x2000 >; + xlnx,family = "virtex4"; + } ; + xps_intc_0: interrupt-controller@81800000 { + #interrupt-cells = <2>; + compatible = "xlnx,xps-intc-1.00.a"; + interrupt-controller ; + reg = < 0x81800000 0x10000 >; + xlnx,num-intr-inputs = <7>; + } ; + } ; + ppc405_0_dplb1: plb@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,plb-v46-1.02.a", "simple-bus"; + ranges ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/powerpc/boot/dts/virtex440-avnet-v5fx30t.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/boot/dts/virtex440-avnet-v5fx30t.dts 2014-07-20 22:06:34.758332077 +0200 @@ -0,0 +1,355 @@ +/* + * Device Tree Generator version: 1.1 + * + * This file supports the Avnet V5FX30T board with the 440 processor. + * A reference design for the FPGA is provided at the avnet web site. + * + * (C) Copyright 2009 Xilinx, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,virtex440", "xlnx,virtex"; + dcr-parent = <&ppc440_0>; + model = "testing"; + DDR2_SDRAM_16Mx32: memory@0 { + device_type = "memory"; + reg = < 0x0 0x4000000 >; + } ; + chosen { + bootargs = "console=ttyS0 root=/dev/ram"; + linux,stdout-path = "/plb@0/serial@83e00000"; + } ; + cpus { + #address-cells = <1>; + #cpus = <0x1>; + #size-cells = <0>; + ppc440_0: cpu@0 { + #address-cells = <1>; + #size-cells = <1>; + clock-frequency = <400000000>; + compatible = "PowerPC,440", "ibm,ppc440"; + d-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + dcr-access-method = "native"; + dcr-controller ; + device_type = "cpu"; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + model = "PowerPC,440"; + reg = <0>; + timebase-frequency = <400000000>; + xlnx,apu-control = <0x2000>; + xlnx,apu-udi-0 = <0x0>; + xlnx,apu-udi-1 = <0x0>; + xlnx,apu-udi-10 = <0x0>; + xlnx,apu-udi-11 = <0x0>; + xlnx,apu-udi-12 = <0x0>; + xlnx,apu-udi-13 = <0x0>; + xlnx,apu-udi-14 = <0x0>; + xlnx,apu-udi-15 = <0x0>; + xlnx,apu-udi-2 = <0x0>; + xlnx,apu-udi-3 = <0x0>; + xlnx,apu-udi-4 = <0x0>; + xlnx,apu-udi-5 = <0x0>; + xlnx,apu-udi-6 = <0x0>; + xlnx,apu-udi-7 = <0x0>; + xlnx,apu-udi-8 = <0x0>; + xlnx,apu-udi-9 = <0x0>; + xlnx,dcr-autolock-enable = <0x1>; + xlnx,dcu-rd-ld-cache-plb-prio = <0x0>; + xlnx,dcu-rd-noncache-plb-prio = <0x0>; + xlnx,dcu-rd-touch-plb-prio = <0x0>; + xlnx,dcu-rd-urgent-plb-prio = <0x0>; + xlnx,dcu-wr-flush-plb-prio = <0x0>; + xlnx,dcu-wr-store-plb-prio = <0x0>; + xlnx,dcu-wr-urgent-plb-prio = <0x0>; + xlnx,dma0-control = <0x0>; + xlnx,dma0-plb-prio = <0x0>; + xlnx,dma0-rxchannelctrl = <0x1010000>; + xlnx,dma0-rxirqtimer = <0x3ff>; + xlnx,dma0-txchannelctrl = <0x1010000>; + xlnx,dma0-txirqtimer = <0x3ff>; + xlnx,dma1-control = <0x0>; + xlnx,dma1-plb-prio = <0x0>; + xlnx,dma1-rxchannelctrl = <0x1010000>; + xlnx,dma1-rxirqtimer = <0x3ff>; + xlnx,dma1-txchannelctrl = <0x1010000>; + xlnx,dma1-txirqtimer = <0x3ff>; + xlnx,dma2-control = <0x0>; + xlnx,dma2-plb-prio = <0x0>; + xlnx,dma2-rxchannelctrl = <0x1010000>; + xlnx,dma2-rxirqtimer = <0x3ff>; + xlnx,dma2-txchannelctrl = <0x1010000>; + xlnx,dma2-txirqtimer = <0x3ff>; + xlnx,dma3-control = <0x0>; + xlnx,dma3-plb-prio = <0x0>; + xlnx,dma3-rxchannelctrl = <0x1010000>; + xlnx,dma3-rxirqtimer = <0x3ff>; + xlnx,dma3-txchannelctrl = <0x1010000>; + xlnx,dma3-txirqtimer = <0x3ff>; + xlnx,endian-reset = <0x0>; + xlnx,generate-plb-timespecs = <0x1>; + xlnx,icu-rd-fetch-plb-prio = <0x0>; + xlnx,icu-rd-spec-plb-prio = <0x0>; + xlnx,icu-rd-touch-plb-prio = <0x0>; + xlnx,interconnect-imask = <0xffffffff>; + xlnx,mplb-allow-lock-xfer = <0x1>; + xlnx,mplb-arb-mode = <0x0>; + xlnx,mplb-awidth = <0x20>; + xlnx,mplb-counter = <0x500>; + xlnx,mplb-dwidth = <0x80>; + xlnx,mplb-max-burst = <0x8>; + xlnx,mplb-native-dwidth = <0x80>; + xlnx,mplb-p2p = <0x0>; + xlnx,mplb-prio-dcur = <0x2>; + xlnx,mplb-prio-dcuw = <0x3>; + xlnx,mplb-prio-icu = <0x4>; + xlnx,mplb-prio-splb0 = <0x1>; + xlnx,mplb-prio-splb1 = <0x0>; + xlnx,mplb-read-pipe-enable = <0x1>; + xlnx,mplb-sync-tattribute = <0x0>; + xlnx,mplb-wdog-enable = <0x1>; + xlnx,mplb-write-pipe-enable = <0x1>; + xlnx,mplb-write-post-enable = <0x1>; + xlnx,num-dma = <0x1>; + xlnx,pir = <0xf>; + xlnx,ppc440mc-addr-base = <0x0>; + xlnx,ppc440mc-addr-high = <0x3ffffff>; + xlnx,ppc440mc-arb-mode = <0x0>; + xlnx,ppc440mc-bank-conflict-mask = <0x300000>; + xlnx,ppc440mc-control = <0xf850008f>; + xlnx,ppc440mc-max-burst = <0x8>; + xlnx,ppc440mc-prio-dcur = <0x2>; + xlnx,ppc440mc-prio-dcuw = <0x3>; + xlnx,ppc440mc-prio-icu = <0x4>; + xlnx,ppc440mc-prio-splb0 = <0x1>; + xlnx,ppc440mc-prio-splb1 = <0x0>; + xlnx,ppc440mc-row-conflict-mask = <0xfff80>; + xlnx,ppcdm-asyncmode = <0x0>; + xlnx,ppcds-asyncmode = <0x0>; + xlnx,user-reset = <0x0>; + DMA0: sdma@80 { + compatible = "xlnx,ll-dma-1.00.a"; + dcr-reg = < 0x80 0x11 >; + interrupt-parent = <&xps_intc_0>; + interrupts = < 7 2 8 2 >; + } ; + } ; + } ; + plb_v46_0: plb@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,plb-v46-1.03.a", "simple-bus"; + ranges ; + DIP_Switches_8Bit: gpio@81420000 { + compatible = "xlnx,xps-gpio-1.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 5 2 >; + reg = < 0x81420000 0x10000 >; + xlnx,all-inputs = <0x1>; + xlnx,all-inputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,family = "virtex5"; + xlnx,gpio-width = <0x8>; + xlnx,interrupt-present = <0x1>; + xlnx,is-bidir = <0x0>; + xlnx,is-bidir-2 = <0x1>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + } ; + FLASH_8Mx16: flash@86000000 { + bank-width = <2>; + compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; + reg = < 0x86000000 0x2000000 >; + xlnx,family = "virtex5"; + xlnx,include-datawidth-matching-0 = <0x1>; + xlnx,include-datawidth-matching-1 = <0x0>; + xlnx,include-datawidth-matching-2 = <0x0>; + xlnx,include-datawidth-matching-3 = <0x0>; + xlnx,include-negedge-ioregs = <0x0>; + xlnx,include-plb-ipif = <0x1>; + xlnx,include-wrbuf = <0x1>; + xlnx,max-mem-width = <0x10>; + xlnx,mch-native-dwidth = <0x20>; + xlnx,mch-plb-clk-period-ps = <0x2710>; + xlnx,mch-splb-awidth = <0x20>; + xlnx,mch0-accessbuf-depth = <0x10>; + xlnx,mch0-protocol = <0x0>; + xlnx,mch0-rddatabuf-depth = <0x10>; + xlnx,mch1-accessbuf-depth = <0x10>; + xlnx,mch1-protocol = <0x0>; + xlnx,mch1-rddatabuf-depth = <0x10>; + xlnx,mch2-accessbuf-depth = <0x10>; + xlnx,mch2-protocol = <0x0>; + xlnx,mch2-rddatabuf-depth = <0x10>; + xlnx,mch3-accessbuf-depth = <0x10>; + xlnx,mch3-protocol = <0x0>; + xlnx,mch3-rddatabuf-depth = <0x10>; + xlnx,mem0-width = <0x10>; + xlnx,mem1-width = <0x20>; + xlnx,mem2-width = <0x20>; + xlnx,mem3-width = <0x20>; + xlnx,num-banks-mem = <0x1>; + xlnx,num-channels = <0x2>; + xlnx,priority-mode = <0x0>; + xlnx,synch-mem-0 = <0x0>; + xlnx,synch-mem-1 = <0x0>; + xlnx,synch-mem-2 = <0x0>; + xlnx,synch-mem-3 = <0x0>; + xlnx,synch-pipedelay-0 = <0x2>; + xlnx,synch-pipedelay-1 = <0x2>; + xlnx,synch-pipedelay-2 = <0x2>; + xlnx,synch-pipedelay-3 = <0x2>; + xlnx,tavdv-ps-mem-0 = <0x1d4c0>; + xlnx,tavdv-ps-mem-1 = <0x3a98>; + xlnx,tavdv-ps-mem-2 = <0x3a98>; + xlnx,tavdv-ps-mem-3 = <0x3a98>; + xlnx,tcedv-ps-mem-0 = <0x1d4c0>; + xlnx,tcedv-ps-mem-1 = <0x3a98>; + xlnx,tcedv-ps-mem-2 = <0x3a98>; + xlnx,tcedv-ps-mem-3 = <0x3a98>; + xlnx,thzce-ps-mem-0 = <0x88b8>; + xlnx,thzce-ps-mem-1 = <0x1b58>; + xlnx,thzce-ps-mem-2 = <0x1b58>; + xlnx,thzce-ps-mem-3 = <0x1b58>; + xlnx,thzoe-ps-mem-0 = <0x1b58>; + xlnx,thzoe-ps-mem-1 = <0x1b58>; + xlnx,thzoe-ps-mem-2 = <0x1b58>; + xlnx,thzoe-ps-mem-3 = <0x1b58>; + xlnx,tlzwe-ps-mem-0 = <0x88b8>; + xlnx,tlzwe-ps-mem-1 = <0x0>; + xlnx,tlzwe-ps-mem-2 = <0x0>; + xlnx,tlzwe-ps-mem-3 = <0x0>; + xlnx,twc-ps-mem-0 = <0x1d4c0>; + xlnx,twc-ps-mem-1 = <0x3a98>; + xlnx,twc-ps-mem-2 = <0x3a98>; + xlnx,twc-ps-mem-3 = <0x3a98>; + xlnx,twp-ps-mem-0 = <0x1d4c0>; + xlnx,twp-ps-mem-1 = <0x2ee0>; + xlnx,twp-ps-mem-2 = <0x2ee0>; + xlnx,twp-ps-mem-3 = <0x2ee0>; + xlnx,xcl0-linesize = <0x4>; + xlnx,xcl0-writexfer = <0x1>; + xlnx,xcl1-linesize = <0x4>; + xlnx,xcl1-writexfer = <0x1>; + xlnx,xcl2-linesize = <0x4>; + xlnx,xcl2-writexfer = <0x1>; + xlnx,xcl3-linesize = <0x4>; + xlnx,xcl3-writexfer = <0x1>; + } ; + Hard_Ethernet_MAC: xps-ll-temac@81c00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,compound"; + ethernet@81c00000 { + compatible = "xlnx,xps-ll-temac-1.01.b"; + device_type = "network"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 3 2 >; + llink-connected = <&DMA0>; + local-mac-address = [ 02 00 00 00 00 00 ]; + reg = < 0x81c00000 0x40 >; + xlnx,bus2core-clk-ratio = <0x1>; + xlnx,phy-type = <0x1>; + xlnx,phyaddr = <0x1>; + xlnx,rxcsum = <0x1>; + xlnx,rxfifo = <0x1000>; + xlnx,temac-type = <0x0>; + xlnx,txcsum = <0x1>; + xlnx,txfifo = <0x1000>; + } ; + } ; + LEDs_8Bit: gpio@81400000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = < 0x81400000 0x10000 >; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,family = "virtex5"; + xlnx,gpio-width = <0x8>; + xlnx,interrupt-present = <0x0>; + xlnx,is-bidir = <0x0>; + xlnx,is-bidir-2 = <0x1>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + } ; + Push_Buttons_3Bit: gpio@81440000 { + compatible = "xlnx,xps-gpio-1.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 4 2 >; + reg = < 0x81440000 0x10000 >; + xlnx,all-inputs = <0x1>; + xlnx,all-inputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,family = "virtex5"; + xlnx,gpio-width = <0x3>; + xlnx,interrupt-present = <0x1>; + xlnx,is-bidir = <0x0>; + xlnx,is-bidir-2 = <0x1>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + } ; + RS232: serial@83e00000 { + clock-frequency = <100000000>; + compatible = "xlnx,xps-uart16550-2.00.b", "ns16550"; + current-speed = <9600>; + device_type = "serial"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 6 2 >; + reg = < 0x83e00000 0x10000 >; + reg-offset = <0x1003>; + reg-shift = <2>; + xlnx,family = "virtex5"; + xlnx,has-external-rclk = <0x0>; + xlnx,has-external-xin = <0x0>; + xlnx,is-a-16550 = <0x1>; + } ; + xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 { + compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; + reg = < 0xffff0000 0x10000 >; + xlnx,family = "virtex5"; + } ; + xps_intc_0: interrupt-controller@81800000 { + #interrupt-cells = <0x2>; + compatible = "xlnx,xps-intc-1.00.a"; + interrupt-controller ; + reg = < 0x81800000 0x10000 >; + xlnx,num-intr-inputs = <0x9>; + } ; + xps_timebase_wdt_1: xps-timebase-wdt@83a00000 { + compatible = "xlnx,xps-timebase-wdt-1.00.b"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 1 0 0 2 >; + reg = < 0x83a00000 0x10000 >; + xlnx,family = "virtex5"; + xlnx,wdt-enable-once = <0x0>; + xlnx,wdt-interval = <0x1e>; + } ; + xps_timer_1: timer@83c00000 { + compatible = "xlnx,xps-timer-1.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 2 2 >; + reg = < 0x83c00000 0x10000 >; + xlnx,count-width = <0x20>; + xlnx,family = "virtex5"; + xlnx,gen0-assert = <0x1>; + xlnx,gen1-assert = <0x1>; + xlnx,one-timer-only = <0x1>; + xlnx,trig0-assert = <0x1>; + xlnx,trig1-assert = <0x1>; + } ; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/arch/powerpc/boot/.gitignore =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/boot/.gitignore 2014-07-20 22:05:50.307065450 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/boot/.gitignore 2014-07-20 22:06:34.766331945 +0200 @@ -28,6 +28,7 @@ zImage.miboot zImage.pmac zImage.pseries +zImage.virtex zconf.h zlib.h zutil.h Index: linux-3.12.24-rt38-xilinx/arch/powerpc/boot/kernel_fdt.its =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/boot/kernel_fdt.its 2014-07-20 22:06:34.773331829 +0200 @@ -0,0 +1,50 @@ +/* + * Simple U-boot uImage source file containing a single kernel and FDT blob + */ +/ { + description = "PetaLinux PPC uImage with single Linux kernel and FDT blob"; + #address-cells = <1>; + + images { + kernel@1 { + description = "PetaLinux kernel"; + data = /incbin/("./vmlinux.bin.gz"); + type = "kernel"; + arch = "ppc"; + os = "linux"; + compression = "gzip"; + load = <00000000>; + entry = <00000000>; + hash@1 { + algo = "crc32"; + }; + hash@2 { + algo = "sha1"; + }; + }; + fdt@1 { + description = "Flattened Device Tree blob"; + data = /incbin/("./target.dtb"); + type = "flat_dt"; + arch = "ppc"; + compression = "none"; +/* + hash@1 { + algo = "crc32"; + }; + hash@2 { + algo = "sha1"; + }; +*/ + }; + }; + + configurations { + default = "conf@1"; + conf@1 { + description = "Boot Linux kernel with FDT blob"; + kernel = "kernel@1"; + fdt = "fdt@1"; + }; + }; +}; Index: linux-3.12.24-rt38-xilinx/arch/powerpc/boot/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/boot/Makefile 2014-07-20 22:05:50.306065466 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/boot/Makefile 2014-07-20 22:06:34.783331664 +0200 @@ -337,6 +337,7 @@ $(obj)/uImage.%: vmlinux $(obj)/%.dtb $(wrapperbits) $(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb) + $(call if_changed,wrap,uboot-fit,,$(obj)/$*.dtb) $(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits) $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz) Index: linux-3.12.24-rt38-xilinx/arch/powerpc/boot/simpleboot.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/boot/simpleboot.c 2014-07-20 22:05:50.305065482 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/boot/simpleboot.c 2014-07-20 22:06:34.794331483 +0200 @@ -31,28 +31,33 @@ const u32 *na, *ns, *reg, *timebase; u64 memsize64; int node, size, i; + void *the_dtb = _dtb_start; + + /* See if we were passed a DTB in the regs. If so, use that instead */ + if (fdt_check_header((void *)r3) == 0) + the_dtb = (void *)r3; /* Make sure FDT blob is sane */ - if (fdt_check_header(_dtb_start) != 0) + if (fdt_check_header(the_dtb) != 0) fatal("Invalid device tree blob\n"); /* Find the #address-cells and #size-cells properties */ - node = fdt_path_offset(_dtb_start, "/"); + node = fdt_path_offset(the_dtb, "/"); if (node < 0) fatal("Cannot find root node\n"); - na = fdt_getprop(_dtb_start, node, "#address-cells", &size); + na = fdt_getprop(the_dtb, node, "#address-cells", &size); if (!na || (size != 4)) fatal("Cannot find #address-cells property"); - ns = fdt_getprop(_dtb_start, node, "#size-cells", &size); + ns = fdt_getprop(the_dtb, node, "#size-cells", &size); if (!ns || (size != 4)) fatal("Cannot find #size-cells property"); /* Find the memory range */ - node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type", + node = fdt_node_offset_by_prop_value(the_dtb, -1, "device_type", "memory", sizeof("memory")); if (node < 0) fatal("Cannot find memory node\n"); - reg = fdt_getprop(_dtb_start, node, "reg", &size); + reg = fdt_getprop(the_dtb, node, "reg", &size); if (size < (*na+*ns) * sizeof(u32)) fatal("cannot get memory range\n"); @@ -69,11 +74,11 @@ memsize64 = 0xffffffff; /* finally, setup the timebase */ - node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type", + node = fdt_node_offset_by_prop_value(the_dtb, -1, "device_type", "cpu", sizeof("cpu")); if (!node) fatal("Cannot find cpu node\n"); - timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size); + timebase = fdt_getprop(the_dtb, node, "timebase-frequency", &size); if (timebase && (size == 4)) timebase_period_ns = 1000000000 / *timebase; @@ -81,7 +86,7 @@ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64); /* prepare the device tree and find the console */ - fdt_init(_dtb_start); + fdt_init(the_dtb); if (platform_specific_init) platform_specific_init(); Index: linux-3.12.24-rt38-xilinx/arch/powerpc/boot/wrapper =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/boot/wrapper 2014-07-20 22:05:50.308065433 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/boot/wrapper 2014-07-20 22:06:34.805331301 +0200 @@ -143,9 +143,12 @@ tmp=$tmpdir/zImage.$$.o ksection=.kernel:vmlinux.strip isection=.kernel:initrd -link_address='0x400000' make_space=y +# default auto-calculate link_address to make room for the kernel +# round up kernel image size to nearest megabyte +link_address=`${CROSS}size -x ${kernel} | grep ${kernel} | awk '{printf("0x%08x", and($4 + 0x0fffff, 0xfffe0000))}'` + case "$platform" in pseries) platformo="$object/of.o $object/epapr.o" @@ -164,7 +167,7 @@ link_address='0x500000' pie= ;; -miboot|uboot*) +miboot|uboot|uboot-fit) # miboot and U-boot want just the bare bits, not an ELF binary ext=bin objflags="-O binary" @@ -339,6 +342,16 @@ fi exit 0 ;; +uboot-fit) + pwd + rm -f "$ofile" + #[ "$vmz" != vmlinux.bin.gz ] && mv "$vmz" "vmlinux.bin.gz" + mv "$dtb" "target.dtb" + cp arch/powerpc/boot/kernel_fdt.its . + mkimage -f kernel_fdt.its "$ofile" + #rm kernet_fdt.its + exit 0 + ;; esac addsec() { Index: linux-3.12.24-rt38-xilinx/arch/powerpc/configs/40x/virtex4_defconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/configs/40x/virtex4_defconfig 2014-07-20 22:06:34.831330872 +0200 @@ -0,0 +1,1521 @@ +# +# Automatically generated make config: don't edit +# Linux/powerpc 2.6.37-rc4 Kernel Configuration +# Tue Dec 14 10:53:11 2010 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +CONFIG_40x=y +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_4xx=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_PPC32=y +CONFIG_32BIT=y +CONFIG_WORD_SIZE=32 +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_PPC_UDBG_16550=y +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFAULT_UIMAGE=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +CONFIG_PPC_DCR_MMIO=y +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_PPC_ADV_DEBUG_REGS=y +CONFIG_PPC_ADV_DEBUG_IACS=2 +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DVCS=0 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_HAVE_GENERIC_HARDIRQS is not set +# CONFIG_SPARSE_IRQ is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +# CONFIG_TINY_RCU is not set +# CONFIG_TINY_PREEMPT_RCU is not set +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_NET_NS=y +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set +# CONFIG_PPC4xx_PCI_EXPRESS is not set + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +# CONFIG_ISS4xx is not set +# CONFIG_PPC4xx_GPIO is not set +CONFIG_XILINX_VIRTEX=y +# CONFIG_ACADIA is not set +# CONFIG_EP405 is not set +# CONFIG_HCU4 is not set +# CONFIG_HOTFOOT is not set +# CONFIG_KILAUEA is not set +# CONFIG_MAKALU is not set +# CONFIG_WALNUT is not set +CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y +# CONFIG_PPC40x_SIMPLE is not set +CONFIG_XILINX_VIRTEX_II_PRO=y +CONFIG_XILINX_VIRTEX_4_FX=y +CONFIG_IBM405_ERR77=y +CONFIG_IBM405_ERR51=y +CONFIG_KVM_GUEST=y +# CONFIG_IPIC is not set +# CONFIG_MPIC is not set +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_MPIC_U3_HT_IRQS is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_FSL_ULI1575 is not set +# CONFIG_SIMPLE_GPIO is not set +# CONFIG_XILINX_PCI is not set + +# +# Kernel options +# +# CONFIG_HIGHMEM is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_SCHED_HRTICK is not set +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_MATH_EMULATION=y +# CONFIG_IOMMU_HELPER is not set +# CONFIG_SWIOTLB is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_MAX_ACTIVE_REGIONS=32 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +CONFIG_PPC_4K_PAGES=y +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="" +CONFIG_EXTRA_TARGETS="simpleImage.virtex405-ml405 simpleImage.initrd.virtex405-ml405" +# CONFIG_PM is not set +CONFIG_SECCOMP=y +# CONFIG_COMPRESSED_DEVICE_TREE is not set +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HAS_RAPIDIO is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_CONSISTENT_SIZE=0x00200000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +# CONFIG_NETFILTER_XT_MARK is not set + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=m +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=m +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_IP_NF_MANGLE=m +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV6 is not set +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# +CONFIG_PROC_DEVICETREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_DEVICE=y +CONFIG_OF_GPIO=y +CONFIG_OF_I2C=y +CONFIG_OF_SPI=y +CONFIG_OF_MDIO=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_XILINX_SYSACE=y +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085 is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +CONFIG_XILINX_DRIVERS=y +CONFIG_NEED_XILINX_LLDMA=y +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +CONFIG_MII=y +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM63XX_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_XILINX_EMAC is not set +# CONFIG_ATL2 is not set +CONFIG_XILINX_EMACLITE=y +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_XILINX_TEMAC is not set +# CONFIG_ATL1E is not set +CONFIG_XILINX_LLTEMAC=y +# CONFIG_XILINX_LLTEMAC_MARVELL_88E1111_RGMII is not set +CONFIG_XILINX_LLTEMAC_MARVELL_88E1111_GMII=y +# CONFIG_XILINX_LLTEMAC_MARVELL_88E1111_MII is not set +# CONFIG_XILINX_LLTEMAC_NATIONAL_DP83865_GMII is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_STMMAC_ETH is not set +# CONFIG_PCH_GBE is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_AIRO is not set +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set + +# +# CAIF transport drivers +# +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_XILINXPS2 is not set +# CONFIG_SERIO_XILINX_XPS_PS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +# CONFIG_SERIAL_MFD_HSU is not set +CONFIG_SERIAL_UARTLITE=y +CONFIG_SERIAL_UARTLITE_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_UDBG is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +CONFIG_XILINX_HWICAP=y +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set +CONFIG_XILINX_IIC=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_IBM_IIC is not set +# CONFIG_I2C_INTEL_MID is not set +# CONFIG_I2C_MPC is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +CONFIG_I2C_DEBUG_CORE=y +CONFIG_I2C_DEBUG_ALGO=y +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_PPC4xx is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +CONFIG_SPI_XILINX=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_BASIC_MMIO is not set +# CONFIG_GPIO_IT8761E is not set +CONFIG_GPIO_XILINX=y +# CONFIG_GPIO_SCH is not set +# CONFIG_GPIO_VX855 is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_LANGWELL is not set +# CONFIG_GPIO_PCH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_DRM is not set +# CONFIG_STUB_POULSBO is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_CT65550 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_IBM_GXT4500 is not set +CONFIG_FB_XILINX=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_XILINX_EDK=y +# CONFIG_XILINX_LLDMA_USE_DCR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +# CONFIG_CUSE is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BLOCK=y +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_DEPRECATED=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_BKL=y +# CONFIG_SPARSE_RCU_POINTER is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_DETECTOR_RUNNABLE=y +CONFIG_RCU_CPU_STALL_VERBOSE=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_PPC_DISABLE_WERROR is not set +CONFIG_PPC_WERROR=y +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_ALGAPI2=m +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=m +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_CRYPTO_DEV_PPC4XX is not set +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set Index: linux-3.12.24-rt38-xilinx/arch/powerpc/configs/44x/avnet_v5fx30t_defconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/configs/44x/avnet_v5fx30t_defconfig 2014-07-20 22:06:34.852330526 +0200 @@ -0,0 +1,1313 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29-rc5 +# Thu Mar 12 19:42:21 2009 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_6xx is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_PPC_DCR_NATIVE=y +CONFIG_PPC_DCR_MMIO=y +CONFIG_PPC_DCR=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set +# CONFIG_PPC4xx_PCI_EXPRESS is not set + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +# CONFIG_BAMBOO is not set +# CONFIG_EBONY is not set +# CONFIG_SAM440EP is not set +# CONFIG_SEQUOIA is not set +# CONFIG_TAISHAN is not set +# CONFIG_KATMAI is not set +# CONFIG_RAINIER is not set +# CONFIG_WARP is not set +# CONFIG_ARCHES is not set +# CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set +# CONFIG_YOSEMITE is not set +CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y +# CONFIG_PPC44x_SIMPLE is not set +# CONFIG_PPC4xx_GPIO is not set +CONFIG_XILINX_VIRTEX_5_FXT=y +# CONFIG_IPIC is not set +# CONFIG_MPIC is not set +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_FSL_ULI1575 is not set +CONFIG_XILINX_VIRTEX=y +# CONFIG_SIMPLE_GPIO is not set + +# +# Kernel options +# +# CONFIG_HIGHMEM is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_SCHED_HRTICK is not set +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_MATH_EMULATION=y +# CONFIG_IOMMU_HELPER is not set +CONFIG_PPC_NEED_DMA_SYNC_OPS=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_64K_PAGES is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_PROC_DEVICETREE=y +# CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="simpleImage.virtex440-avnet-v5fx30t simpleImage.initrd.virtex440-avnet-v5fx30t" +CONFIG_SECCOMP=y +# CONFIG_COMPRESSED_DEVICE_TREE is not set +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_STUB is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HAS_RAPIDIO is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_CONSISTENT_START=0xff100000 +CONFIG_CONSISTENT_SIZE=0x00200000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_COMPAT_NET_DEV_OPS=y +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +CONFIG_NETFILTER_XTABLES=m +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=m +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=m +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_IP_NF_MANGLE=m +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +# CONFIG_WIRELESS_EXT is not set +# CONFIG_LIB80211 is not set +# CONFIG_MAC80211 is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_PARTITIONS is not set +# CONFIG_MTD_TESTS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_PHYSMAP_OF is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_QINFO_PROBE is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +CONFIG_OF_DEVICE=y +CONFIG_OF_I2C=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_XILINX_SYSACE is not set +# CONFIG_XILINX_SYSACE_OLD is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_XILINX_DRIVERS=y +CONFIG_NEED_XILINX_LLDMA=y +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# Enable only one of the two stacks, unless you know what you are doing +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_XILINX_EMAC is not set +# CONFIG_XILINX_EMACLITE is not set +# CONFIG_ATL2 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_XILINX_TEMAC is not set +# CONFIG_ATL1E is not set +CONFIG_XILINX_LLTEMAC=y +# CONFIG_XILINX_LLTEMAC_MARVELL_88E1111_RGMII is not set +# CONFIG_XILINX_LLTEMAC_MARVELL_88E1111_GMII is not set +# CONFIG_XILINX_LLTEMAC_MARVELL_88E1111_MII is not set +CONFIG_XILINX_LLTEMAC_NATIONAL_DP83865_GMII=y +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_XILINXPS2 is not set +# CONFIG_SERIO_XILINX_XPS_PS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_HVC_UDBG is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +CONFIG_XILINX_HWICAP=y +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_IBM_IIC is not set +# CONFIG_I2C_MPC is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Graphics adapter I2C/DDC channel drivers +# +# CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_CT65550 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_IBM_GXT4500 is not set +CONFIG_FB_XILINX=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +CONFIG_XILINX_EDK=y +CONFIG_XILINX_LLDMA_USE_DCR=y +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=y +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_IRQSTACKS is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set Index: linux-3.12.24-rt38-xilinx/arch/powerpc/configs/44x/virtex5_defconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/configs/44x/virtex5_defconfig 2014-07-20 22:05:50.294065664 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/configs/44x/virtex5_defconfig 2014-07-20 22:06:34.873330180 +0200 @@ -1,90 +1,1592 @@ +# +# Automatically generated make config: don't edit +# Linux/powerpc 2.6.37-rc4 Kernel Configuration +# Wed Dec 15 13:45:41 2010 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set CONFIG_44x=y +# CONFIG_E200 is not set +# CONFIG_PPC_FPU is not set +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_PPC32=y +CONFIG_32BIT=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_PPC_UDBG_16550=y +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFAULT_UIMAGE=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +CONFIG_PPC_DCR_MMIO=y +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_PPC_ADV_DEBUG_REGS=y +CONFIG_PPC_ADV_DEBUG_IACS=4 +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DVCS=2 +CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_HAVE_GENERIC_HARDIRQS is not set +# CONFIG_SPARSE_IRQ is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +# CONFIG_TINY_RCU is not set +# CONFIG_TINY_PREEMPT_RCU is not set +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set +# CONFIG_PPC4xx_PCI_EXPRESS is not set + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +# CONFIG_PPC_47x is not set +# CONFIG_BAMBOO is not set +# CONFIG_BLUESTONE is not set # CONFIG_EBONY is not set +# CONFIG_SAM440EP is not set +# CONFIG_SEQUOIA is not set +# CONFIG_TAISHAN is not set +# CONFIG_KATMAI is not set +# CONFIG_RAINIER is not set +# CONFIG_WARP is not set +# CONFIG_ARCHES is not set +# CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set +# CONFIG_REDWOOD is not set +# CONFIG_EIGER is not set +# CONFIG_YOSEMITE is not set +# CONFIG_ISS4xx is not set +# CONFIG_ICON is not set CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y +# CONFIG_XILINX_ML510 is not set +# CONFIG_PPC44x_SIMPLE is not set +# CONFIG_PPC4xx_GPIO is not set +CONFIG_XILINX_VIRTEX=y +CONFIG_XILINX_VIRTEX_5_FXT=y +CONFIG_KVM_GUEST=y +# CONFIG_IPIC is not set +# CONFIG_MPIC is not set +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_MPIC_U3_HT_IRQS is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_FSL_ULI1575 is not set +# CONFIG_SIMPLE_GPIO is not set +# CONFIG_XILINX_PCI is not set + +# +# Kernel options +# +# CONFIG_HIGHMEM is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_SCHED_HRTICK is not set +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set CONFIG_MATH_EMULATION=y +# CONFIG_IOMMU_HELPER is not set +# CONFIG_SWIOTLB is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_MAX_ACTIVE_REGIONS=32 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +CONFIG_STDBINUTILS=y +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_64K_PAGES is not set +CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="" +CONFIG_EXTRA_TARGETS="" +CONFIG_SECCOMP=y +# CONFIG_COMPRESSED_DEVICE_TREE is not set +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HAS_RAPIDIO is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_CONSISTENT_SIZE=0x00200000 CONFIG_NET=y + +# +# Networking options +# CONFIG_PACKET=y CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y # CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +# CONFIG_NETFILTER_XT_MARK is not set + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set CONFIG_IP_NF_IPTABLES=m +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_TTL is not set CONFIG_IP_NF_FILTER=m +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set CONFIG_IP_NF_MANGLE=m +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV6 is not set +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# CONFIG_PROC_DEVICETREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_DEVICE=y +CONFIG_OF_GPIO=y +CONFIG_OF_I2C=y +CONFIG_OF_SPI=y +CONFIG_OF_MDIO=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set CONFIG_XILINX_SYSACE=y +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085 is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +CONFIG_EEPROM_AT25=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +CONFIG_XILINX_DRIVERS=y +CONFIG_NEED_XILINX_LLDMA=y +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set CONFIG_MII=y +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM63XX_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_XILINX_EMAC is not set +# CONFIG_ATL2 is not set +CONFIG_XILINX_EMACLITE=y +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_XILINX_TEMAC is not set +# CONFIG_ATL1E is not set +CONFIG_XILINX_LLTEMAC=y +# CONFIG_XILINX_LLTEMAC_MARVELL_88E1111_RGMII is not set +CONFIG_XILINX_LLTEMAC_MARVELL_88E1111_GMII=y +# CONFIG_XILINX_LLTEMAC_MARVELL_88E1111_MII is not set +# CONFIG_XILINX_LLTEMAC_NATIONAL_DP83865_GMII is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_STMMAC_ETH is not set +# CONFIG_PCH_GBE is not set # CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_AIRO is not set +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set + +# +# CAIF transport drivers +# +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set # CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_XILINXPS2 is not set CONFIG_SERIO_XILINX_XPS_PS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +# CONFIG_SERIAL_MFD_HSU is not set CONFIG_SERIAL_UARTLITE=y CONFIG_SERIAL_UARTLITE_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_UDBG is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set CONFIG_XILINX_HWICAP=y +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set +CONFIG_XILINX_IIC=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_IBM_IIC is not set +# CONFIG_I2C_INTEL_MID is not set +# CONFIG_I2C_MPC is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_PPC4xx is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +CONFIG_SPI_XILINX=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_BASIC_MMIO is not set +# CONFIG_GPIO_IT8761E is not set CONFIG_GPIO_XILINX=y +# CONFIG_GPIO_SCH is not set +# CONFIG_GPIO_VX855 is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_LANGWELL is not set +# CONFIG_GPIO_PCH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_DRM is not set +# CONFIG_STUB_POULSBO is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_CT65550 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_IBM_GXT4500 is not set CONFIG_FB_XILINX=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set # CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_XILINX_EDK=y +CONFIG_XILINX_LLDMA_USE_DCR=y +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# CONFIG_EXT2_FS=y -CONFIG_INOTIFY=y -CONFIG_AUTOFS_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BLOCK=y +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set CONFIG_NLS_ASCII=m CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y + +# +# Kernel hacking +# CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +CONFIG_BKL=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_PPC_DISABLE_WERROR is not set +CONFIG_PPC_WERROR=y +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_CRYPTO_DEV_PPC4XX is not set +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set Index: linux-3.12.24-rt38-xilinx/arch/powerpc/kernel/entry_32.S =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/kernel/entry_32.S 2014-07-20 22:05:50.304065499 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/kernel/entry_32.S 2014-07-20 22:06:34.892329866 +0200 @@ -699,6 +699,13 @@ andc r11,r11,r0 MTMSRD(r11) isync +#if defined(CONFIG_XILINX_VIRTEX_5_FXT) && defined(CONFIG_PPC_FPU) + mfspr r5,SPRN_CCR0 + andis. r5,r5, ~(1<<6)@l + andi. r5,r5, ~(1<<5)@l + mtspr SPRN_CCR0,r5 + isync +#endif 1: stw r11,_MSR(r1) mfcr r10 stw r10,_CCR(r1) Index: linux-3.12.24-rt38-xilinx/arch/powerpc/kernel/fpu.S =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/kernel/fpu.S 2014-07-20 22:05:50.303065516 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/kernel/fpu.S 2014-07-20 22:06:34.903329685 +0200 @@ -124,6 +124,21 @@ * enable the FPU for the current task and return to the task. */ _GLOBAL(load_up_fpu) +#if defined(CONFIG_XILINX_VIRTEX_5_FXT) && defined(CONFIG_PPC_FPU) + li r3,0 + lis r5,excep_state@h + ori r5,r5,excep_state@l + stw r3,0(r5) + + mfspr r5,SPRN_CCR0 + /* set CCR0[9] to disable the load miss queue inside the ppc440 */ + oris r5,r5, (1<<6) + /* set CCR0[26] to ... */ + ori r5,r5, (1<<5) + mtspr SPRN_CCR0,r5 + isync +#endif + mfmsr r5 ori r5,r5,MSR_FP #ifdef CONFIG_VSX @@ -191,6 +206,16 @@ * Enables the FPU for use in the kernel on return. */ _GLOBAL(giveup_fpu) +#if defined(CONFIG_XILINX_VIRTEX_5_FXT) && defined(CONFIG_PPC_FPU) + mfspr r5,SPRN_CCR0 + /* set CCR0[9] to disable the load miss queue inside the ppc440 */ + oris r5,r5, (1<<6) + /* set CCR0[26] to ... */ + ori r5,r5, (1<<5) + mtspr SPRN_CCR0,r5 + isync +#endif + mfmsr r5 ori r5,r5,MSR_FP #ifdef CONFIG_VSX Index: linux-3.12.24-rt38-xilinx/arch/powerpc/kernel/head_44x.S =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/kernel/head_44x.S 2014-07-20 22:05:50.302065532 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/kernel/head_44x.S 2014-07-20 22:06:34.918329437 +0200 @@ -96,6 +96,18 @@ bl init_cpu_state /* + * The following code is needed to make GDB work with soft breakpoints. + * This patch was provided by Brian Hill. + */ + lis r2,DBCR0_IDM@h + mtspr SPRN_DBCR0,r2 + isync + + /* clear any residual debug events */ + li r2,-1 + mtspr SPRN_DBSR,r2 + + /* * This is where the main kernel code starts. */ @@ -932,8 +944,21 @@ tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ + /* Force context change */ +#ifdef CONFIG_XILINX_VIRTEX_5_FXT + /* We can not use the content of the MSR register when we are using XMD + * to connect to a ml5xx board as XMD changes the contents of the MSR + * register. We load the default value instead. + * + * EDK 10.1 fixes this issue so this should be removed once the automated + * testing is updated to 10.1 tools. + */ + lis r0,MSR_KERNEL@h + ori r0,r0,MSR_KERNEL@l +#else mfmsr r0 +#endif mtspr SPRN_SRR1, r0 lis r0,3f@h ori r0,r0,3f@l Index: linux-3.12.24-rt38-xilinx/arch/powerpc/kernel/traps.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/kernel/traps.c 2014-07-20 22:05:50.301065548 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/kernel/traps.c 2014-07-20 22:06:34.936329140 +0200 @@ -80,6 +80,10 @@ EXPORT_SYMBOL(__debugger_fault_handler); #endif +#if defined(CONFIG_XILINX_VIRTEX_5_FXT) && defined(CONFIG_PPC_FPU) +u8 excep_state = 0; +#endif + /* Transactional Memory trap debug */ #ifdef TM_DEBUG_SW #define TM_DEBUG(x...) printk(KERN_INFO x) @@ -1174,6 +1178,17 @@ if (!emulate_math(regs)) goto bail; +#if defined(CONFIG_XILINX_VIRTEX_5_FXT) && defined(CONFIG_PPC_FPU) + if (reason & REASON_ILLEGAL) { + if (excep_state < 1) { + excep_state++; + return; + } + /* should never get here */ + BUG(); + } +#endif + /* Try to emulate it if we should. */ if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { switch (emulate_instruction(regs)) { Index: linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/40x/40x.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/40x/40x.h 2014-07-20 22:06:34.950328910 +0200 @@ -0,0 +1,6 @@ +#ifndef __POWERPC_PLATFORMS_40X_40X_H +#define __POWERPC_PLATFORMS_40X_40X_H + +extern void ppc40x_reset_system(char *cmd); + +#endif /* __POWERPC_PLATFORMS_44X_44X_H */ Index: linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/40x/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/platforms/40x/Makefile 2014-07-20 22:05:50.300065565 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/40x/Makefile 2014-07-20 22:06:34.958328778 +0200 @@ -1,4 +1,4 @@ obj-$(CONFIG_WALNUT) += walnut.o -obj-$(CONFIG_XILINX_VIRTEX_GENERIC_BOARD) += virtex.o +obj-$(CONFIG_XILINX_VIRTEX_GENERIC_BOARD) += virtex.o misc_40x.o obj-$(CONFIG_EP405) += ep405.o obj-$(CONFIG_PPC40x_SIMPLE) += ppc40x_simple.o Index: linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/40x/misc_40x.S =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/40x/misc_40x.S 2014-07-20 22:06:34.966328646 +0200 @@ -0,0 +1,26 @@ +/* + * This file contains miscellaneous low-level functions for PPC 44x. + * Copyright 2007 David Gibson , IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include + + .text + +/* + * void ppc40x_reset_system(char *cmd) + * + * At present, this routine just applies a system reset. + */ +_GLOBAL(ppc40x_reset_system) + mfspr r13,SPRN_DBCR0 + oris r13,r13,DBCR0_RST_SYSTEM@h + mtspr SPRN_DBCR0,r13 + blr Index: linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/40x/virtex.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/platforms/40x/virtex.c 2014-07-20 22:05:50.299065581 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/40x/virtex.c 2014-07-20 22:06:34.974328514 +0200 @@ -18,7 +18,9 @@ #include static struct of_device_id xilinx_of_bus_ids[] __initdata = { + { .compatible = "simple-bus", }, { .compatible = "xlnx,plb-v46-1.00.a", }, + { .compatible = "xlnx,plb-v46-1.02.a", }, { .compatible = "xlnx,plb-v34-1.01.a", }, { .compatible = "xlnx,plb-v34-1.02.a", }, { .compatible = "xlnx,opb-v20-1.10.c", }, Index: linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/44x/Kconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/platforms/44x/Kconfig 2014-07-20 22:05:50.296065631 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/44x/Kconfig 2014-07-20 22:06:34.989328266 +0200 @@ -251,6 +251,15 @@ help Enable gpiolib support for ppc440 based boards +config XILINX_PPC_FPU + depends on XILINX_VIRTEX_5_FXT + bool "Enable Xilinx Soft FPU" + select PPC_FPU + default n + help + This option enables the Xilinx Soft FPU attached to the APU + interface of the PPC440 (requires DP_FULL FPU pcore). + config PPC4xx_OCM bool "PPC4xx On Chip Memory (OCM) support" depends on 4xx Index: linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/Kconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/platforms/Kconfig 2014-07-20 22:05:50.297065614 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/platforms/Kconfig 2014-07-20 22:06:35.000328085 +0200 @@ -332,6 +332,13 @@ config CPM bool +config XILINX_VIRTEX + bool + select PPC_DCR_MMIO + select PPC_DCR_NATIVE + help + Support for Xilinx Virtex platforms. + config OF_RTC bool help Index: linux-3.12.24-rt38-xilinx/arch/powerpc/sysdev/xilinx_pci.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/arch/powerpc/sysdev/xilinx_pci.c 2014-07-20 22:05:50.295065648 +0200 +++ linux-3.12.24-rt38-xilinx/arch/powerpc/sysdev/xilinx_pci.c 2014-07-20 22:06:35.014327854 +0200 @@ -115,9 +115,9 @@ /* Set the max latency timer to 255 */ early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff); - /* Set the max bus number to 255 */ + /* Set the max bus number to 255, and bus/subbus no's to 0 */ pci_reg = of_iomap(pci_node, 0); - out_8(pci_reg + XPLB_PCI_BUS, 0xff); + out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff); iounmap(pci_reg); /* Nothing past the root bridge is working right now. By default Index: linux-3.12.24-rt38-xilinx/config =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/config 2014-07-20 22:06:35.046327326 +0200 @@ -0,0 +1,2900 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.12.14 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_NO_IOPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="-xilinx" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_FHANDLE is not set +# CONFIG_AUDIT is not set + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_KTIME_SCALAR=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_CPU_IDLERUNTIME=y +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_USER_QS is not set +CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_RCU_BOOST=y +CONFIG_RCU_BOOST_PRIO=1 +CONFIG_RCU_BOOST_DELAY=500 +# CONFIG_RCU_NOCB_CPU is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKPATCHSET is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_PCI_QUIRKS=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_PROFILING is not set +CONFIG_TRACEPOINTS=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_JUMP_LABEL is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_SHMOBILE_MULTI is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_ARCH_VEXPRESS=y + +# +# Versatile Express platform type +# +CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y +# CONFIG_ARCH_VEXPRESS_CA9X4 is not set +CONFIG_PLAT_VERSATILE_CLCD=y +CONFIG_PLAT_VERSATILE_SCHED_CLOCK=y +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_WM8850 is not set +CONFIG_ARCH_ZYNQ=y + +# +# Xilinx Specific Options +# +CONFIG_XILINX_L1_PREFETCH=y +CONFIG_XILINX_L2_PREFETCH=y +CONFIG_XILINX_AXIPCIE=y +CONFIG_PLAT_VERSATILE=y +CONFIG_ARM_TIMER_SP804=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +CONFIG_PL310_ERRATA_588369=y +# CONFIG_ARM_ERRATA_643719 is not set +CONFIG_ARM_ERRATA_720789=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_ERRATA_775420=y +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_ERRATA_773022 is not set +CONFIG_ICST=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set + +# +# PCI host controller drivers +# +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_HAVE_ARM_SCU=y +# CONFIG_HAVE_ARM_ARCH_TIMER is not set +CONFIG_HAVE_ARM_TWD=y +# CONFIG_MCPM is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=4 +CONFIG_HOTPLUG_CPU=y +# CONFIG_ARM_PSCI is not set +CONFIG_ARCH_NR_GPIO=1024 +CONFIG_PREEMPT=y +CONFIG_PREEMPT_RT_BASE=y +CONFIG_HAVE_PREEMPT_LAZY=y +CONFIG_PREEMPT_LAZY=y +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT__LL is not set +# CONFIG_PREEMPT_RTB is not set +CONFIG_PREEMPT_RT_FULL=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_ZBUD is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_XEN is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +# CONFIG_ARM_APPENDED_DTB is not set +CONFIG_CMDLINE="console=ttyPS0,115200n8 root=/dev/mmcblk0p2 rw earlyprintk" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + +# +# ARM CPU frequency scaling drivers +# +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_ZYNQ_CPUFREQ=y + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +# CONFIG_KERNEL_MODE_NEON is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_HAS_OPP=y +CONFIG_PM_OPP=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_GRE is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_MMAP is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_NET_MPLS_GSO is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +CONFIG_HAVE_BPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_DMA_CMA is not set + +# +# Bus devices +# +# CONFIG_ARM_CCI is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_M25PXX_USE_FAST_READ is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_DENALI is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_DOCG4 is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_NAND_ZYNQ=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# +CONFIG_PROC_DEVICETREE=y +# CONFIG_OF_SELFTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_MTD=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_VIRTIO_BLK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_DUMMY_IRQ is not set +CONFIG_HWLAT_DETECTOR=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_ARM_CHARLCD is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_SI570 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_SCSI_BNX2X_FCOE is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_VIRTIO is not set +# CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_HAVE_PATA_PLATFORM=y +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_VIRTIO_NET is not set +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +CONFIG_NET_VENDOR_ARC=y +# CONFIG_ARC_EMAC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +CONFIG_NET_CADENCE=y +# CONFIG_ARM_AT91_ETHER is not set +CONFIG_MACB=y +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +CONFIG_TIGON3=y +# CONFIG_BNX2X is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_NET_VENDOR_INTEL=y +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +CONFIG_E1000E=y +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_I40E is not set +CONFIG_NET_VENDOR_I825XX=y +# CONFIG_IP1000 is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +CONFIG_R8169=y +# CONFIG_SH_ETH is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_SFC is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_XILINX=y +CONFIG_XILINX_EMACLITE=y +CONFIG_XILINX_AXI_EMAC=y +CONFIG_XILINX_PS_EMAC=y +# CONFIG_XILINX_PS_EMAC_HWTSTAMP is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AT803X_PHY is not set +# CONFIG_AMD_PHY is not set +CONFIG_MARVELL_PHY=y +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +CONFIG_VITESSE_PHY=y +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +CONFIG_MDIO_BITBANG=y +# CONFIG_MDIO_GPIO is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set +# CONFIG_WL_TI is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_OLPC_APSP is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_MFD_HSU is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_PCH_UART is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +CONFIG_XILINX_DEVCFG=y +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_PCA9541 is not set +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_VERSATILE is not set +CONFIG_I2C_ZYNQ=y +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_FSL_DSPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +CONFIG_SPI_XILINX=y +CONFIG_SPI_ZYNQ_QSPI=y +# CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED is not set +CONFIG_SPI_ZYNQ=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_HSI is not set + +# +# PPS support +# +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_TS5500 is not set +CONFIG_GPIO_XILINX=y +CONFIG_GPIO_ZYNQ=y +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_GRGPIO is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# LPC GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# + +# +# USB GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_SMB347 is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_RESTART is not set +CONFIG_POWER_RESET_VEXPRESS=y +# CONFIG_POWER_AVS is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VEXPRESS is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_XADCPS=y +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +CONFIG_ZYNQ_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set +CONFIG_XILINX_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_VEXPRESS_CONFIG=y +# CONFIG_REGULATOR is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +# CONFIG_MEDIA_CAMERA_SUPPORT is not set +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_RC_SUPPORT is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_TTPCI_EEPROM is not set + +# +# Media drivers +# +# CONFIG_MEDIA_USB_SUPPORT is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set + +# +# Supported MMC/SDIO adapters +# +# CONFIG_CYPRESS_FIRMWARE is not set + +# +# Media ancillary drivers (tuners, sensors, i2c, frontends) +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_DRM is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_XILINX is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_SIMPLE is not set +CONFIG_FB_XYLON=y +# CONFIG_FB_XYLON_PLATFORM is not set +CONFIG_FB_XYLON_OF=y +# CONFIG_FB_XYLON_PIXCLK is not set +# CONFIG_FB_XYLON_MISC is not set +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_LOGO is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_SOUND is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_HUION is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO_TPKBD is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +CONFIG_HID_MICROSOFT=y +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_XUSBPS_DR_OF=y +CONFIG_USB_EHCI_XUSBPS=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FUSBH200_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_CHIPIDEA is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_RCAR_PHY is not set +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 + +# +# USB Peripheral Controller +# +CONFIG_USB_GADGET_XUSBPS=y +CONFIG_XUSBPS_ERRATA_DT654401=y +CONFIG_USB_XUSBPS=y +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_R8A66597 is not set +CONFIG_USB_GADGET_XILINX=y +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_LIBCOMPOSITE=y +CONFIG_USB_U_ETHER=y +CONFIG_USB_U_RNDIS=y +CONFIG_USB_F_ECM=y +CONFIG_USB_F_SUBSET=y +CONFIG_USB_F_RNDIS=y +# CONFIG_USB_CONFIGFS is not set +# CONFIG_USB_ZERO is not set +CONFIG_USB_ETH=y +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_MM_EDAC=y +CONFIG_EDAC_ZYNQ=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +CONFIG_RTC_DRV_PCF8563=y +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_RX4581 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_DS2404 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_MOXART is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_XILINX_DMA_ENGINES=y +CONFIG_XILINX_AXIDMA=y +# CONFIG_XILINX_DMATEST is not set +CONFIG_XILINX_AXIVDMA=y +# CONFIG_XILINX_VDMATEST is not set +CONFIG_XILINX_AXICDMA=y +# CONFIG_XILINX_CDMATEST is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_TIMB_DMA is not set +CONFIG_PL330_DMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +# CONFIG_UIO_CIF is not set +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_AEC is not set +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_UIO_PCI_GENERIC is not set +# CONFIG_UIO_NETX is not set +# CONFIG_UIO_MF624 is not set +CONFIG_UIO_XILINX_APM=y +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO=y + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +CONFIG_COMMON_CLK_DEBUG=y +CONFIG_COMMON_CLK_VERSATILE=y +# CONFIG_COMMON_CLK_SI5351 is not set +CONFIG_COMMON_CLK_SI570=y +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CADENCE_TTC_TIMER=y +# CONFIG_MAILBOX is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_OF_IOMMU=y + +# +# Remoteproc drivers +# +CONFIG_REMOTEPROC=y +# CONFIG_STE_MODEM_RPROC is not set +CONFIG_ZYNQ_REMOTEPROC=y +CONFIG_MB_REMOTEPROC=y + +# +# Rpmsg drivers +# +CONFIG_RPMSG=y +# CONFIG_RPMSG_SERVER_SAMPLE is not set +# CONFIG_RPMSG_OMX is not set +# CONFIG_RPMSG_FREERTOS_STAT is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +CONFIG_MEMORY=y +CONFIG_ZYNQ_SMC=y +# CONFIG_IIO is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_F2FS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_HIGHMEM is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +CONFIG_DEBUG_PREEMPT=y + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_TRACE_IRQFLAGS=y +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU_DELAY is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_VERBOSE=y +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_INTERRUPT_OFF_HIST=y +CONFIG_PREEMPT_TRACER=y +CONFIG_PREEMPT_OFF_HIST=y +CONFIG_SCHED_TRACER=y +CONFIG_WAKEUP_LATENCY_HIST=y +CONFIG_MISSED_TIMER_OFFSETS_HIST=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +CONFIG_DYNAMIC_FTRACE=y +# CONFIG_FUNCTION_PROFILER is not set +CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +CONFIG_OLD_MCOUNT=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ZYNQ_UART0 is not set +CONFIG_DEBUG_ZYNQ_UART1=y +# CONFIG_DEBUG_VEXPRESS_UART0_DETECT is not set +# CONFIG_DEBUG_VEXPRESS_UART0_CA9 is not set +# CONFIG_DEBUG_VEXPRESS_UART0_RS1 is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +CONFIG_DEBUG_LL_INCLUDE="debug/zynq.S" +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_EARLY_PRINTK=y +# CONFIG_OC_ETM is not set +# CONFIG_PID_IN_CONTEXTIDR is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +CONFIG_FONT_SUPPORT=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_VIRTUALIZATION=y Index: linux-3.12.24-rt38-xilinx/debian/changelog =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/debian/changelog 2014-07-20 22:06:35.055327178 +0200 @@ -0,0 +1,5 @@ +linux-image-zedboard-3.12.14-rt23 (3.12.14-rt23-2) unstable; urgency=low + + * Custom built Linux kernel. + + -- Anonymous Wed, 04 Jun 2014 08:42:05 +0200 Index: linux-3.12.24-rt38-xilinx/debian/control =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/debian/control 2014-07-20 22:06:35.060327095 +0200 @@ -0,0 +1,30 @@ +Source: linux-image-zedboard-3.12.14-rt23 +Section: kernel +Priority: optional +Maintainer: Anonymous +Standards-Version: 3.8.4 +Homepage: http://www.kernel.org/ + +Package: linux-image-zedboard-3.12.14-rt23 +Provides: linux-image, linux-image-2.6, linux-modules-3.12.14-rt23 +Suggests: linux-firmware-image-zedboard-3.12.14-rt23 +Architecture: any +Description: Linux kernel, version 3.12.14-rt23 + This package contains the Linux kernel, modules and corresponding other + files, version: 3.12.14-rt23. + +Package: linux-headers-zedboard-3.12.14-rt23 +Provides: linux-headers, linux-headers-2.6 +Architecture: any +Description: Linux kernel headers for 3.12.14-rt23 on amd64 + This package provides kernel header files for 3.12.14-rt23 on amd64 + . + This is useful for people who need to build external modules + +Package: linux-libc-dev +Section: devel +Provides: linux-kernel-headers +Architecture: any +Description: Linux support headers for userspace development + This package provides userspaces headers from the Linux kernel. These headers + are used by the installed headers for GNU glibc and other system libraries. Index: linux-3.12.24-rt38-xilinx/debian/copyright =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/debian/copyright 2014-07-20 22:06:35.066326996 +0200 @@ -0,0 +1,16 @@ +This is a packacked upstream version of the Linux kernel. + +The sources may be found at most Linux ftp sites, including: +ftp://ftp.kernel.org/pub/linux/kernel + +Copyright: 1991 - 2009 Linus Torvalds and others. + +The git repository for mainline kernel development is at: +git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 dated June, 1991. + +On Debian GNU/Linux systems, the complete text of the GNU General Public +License version 2 can be found in `/usr/share/common-licenses/GPL-2'. Index: linux-3.12.24-rt38-xilinx/debian/source/format =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/debian/source/format 2014-07-20 22:06:35.075326848 +0200 @@ -0,0 +1 @@ +3.0 (git) Index: linux-3.12.24-rt38-xilinx/debian/source/options =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/debian/source/options 2014-07-20 22:06:35.080326765 +0200 @@ -0,0 +1,2 @@ +git-ref=HEAD +git-depth=3 Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/arm/zynq/xlnx,zynq-ocm.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/arm/zynq/xlnx,zynq-ocm.txt 2014-07-20 22:06:35.096326501 +0200 @@ -0,0 +1,17 @@ +Device tree bindings for Zynq's OCM + +The OCM is divided to 4 64kB segments which can be separately configured +to low or high location. Location is controlled via SLCR. + +Required properties: + compatible: Compatibility string. Must be "xlnx,zynq-ocm-1.0". + reg: Specify the base and size of the OCM registers in the memory map. + E.g.: reg = <0xf800c000 0x1000>; + +Example: +ps7_ram_0: ps7-ram@f800c000 { + compatible = "xlnx,zynq-ocm-1.0"; + reg = <0xf800c000 0x1000>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 3 4>; +} ; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/arm/zynq/xlnx,zynq-smc.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/arm/zynq/xlnx,zynq-smc.txt 2014-07-20 22:06:35.102326402 +0200 @@ -0,0 +1,30 @@ +Device tree bindings for Zynq's SMC (PL353) + +The SMC supports NAND, NOR and SRAM memory. The SMC driver handles generic +tasks, while children drivers handle memory type specifics. + +Required properties: + compatible: Compatibility string. Must be "xlnx,ps7-smc". + reg: Specify the base and size of the SMC registers in the memory map. + E.g.: reg = <0xe000e000 0x1000>; + #address-cells: Address cells, must be 1. + #size-cells: Size cells. Must be 1. + ranges + +Child nodes: + For NAND the "xlnx,ps7-nand" and for NOR the "cfi-flash" drivers are supported + as child nodes. + +Example: + ps7_smc_0: ps7-smc@e000e000 { + compatible = "xlnx,ps7-smc"; + reg = <0xe000e000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ps7_nand_0: ps7-nand@e1000000 { + compatible = "xlnx,ps7-nand-1.00.a"; + (...) + }; + }; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/clock/silabs,si570.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/clock/silabs,si570.txt 2014-07-20 22:06:35.113326221 +0200 @@ -0,0 +1,39 @@ +Binding for Silicon Labs 570, 571, 598 and 599 programmable +I2C clock generators. + +Reference +This binding uses the common clock binding[1]. Details about the devices can be +found in the data sheets[2][3]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Si570/571 Data Sheet + http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf +[3] Si598/599 Data Sheet + http://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf + +Required properties: + - compatible: Shall be one of "silabs,si570", "silabs,si571", + "silabs,si598", "silabs,si599" + - reg: I2C device address. + - #clock-cells: From common clock bindings: Shall be 0. + - factory-fout: Factory set default frequency. This frequency is part specific. + The correct frequency for the part used has to be provided in + order to generate the correct output frequencies. For more + details, please refer to the data sheet. + - temperature-stability: Temperature stability of the device in PPM. Should be + one of: 7, 20, 50 or 100. + +Optional properties: + - clock-output-names: From common clock bindings. Recommended to be "si570". + - clock-frequency: Output frequency to generate. This defines the output + frequency set during boot. It can be reprogrammed during + runtime through the common clock framework. + +Example: + si570: clock-generator@5d { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x5d>; + factory-fout = <156250000>; + }; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/clock/zynq-7000.txt =================================================================== --- linux-3.12.24-rt38-xilinx.orig/Documentation/devicetree/bindings/clock/zynq-7000.txt 2014-07-20 22:05:50.329065087 +0200 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/clock/zynq-7000.txt 2014-07-20 22:06:35.121326089 +0200 @@ -22,6 +22,10 @@ Optional properties: - clocks : as described in the clock bindings - clock-names : as described in the clock bindings + - fclk-enable : Bit mask to enable FCLKs in cases no proper CCF compatible + driver is available. Bit [0..3] correspond to FCLK0..FCLK3. The + corresponding FCLK will only be enabled if it is actually + running at boot time. Clock inputs: The following strings are optional parameters to the 'clock-names' property in Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/dma/xilinx/axi-cdma.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/dma/xilinx/axi-cdma.txt 2014-07-20 22:06:35.135325858 +0200 @@ -0,0 +1,18 @@ +Xilinx AXI CDMA engine, it does transfers between memory and memory + +Required properties: +- compatible: Should be "xlnx,axi-cdma" +- reg: Should contain CDMA registers location and length. +- interrupts: Should contain channel CDMA interrupts. + +Example: +++++++++ + +axi_cdma_0: axicdma@40030000 { + compatible = "xlnx,axi-cdma"; + reg = < 0x40030000 0x10000 >; + dma-channel@40030000 { + interrupts = < 0 59 4 >; + } ; +} ; + Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/dma/xilinx/axi-dma.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/dma/xilinx/axi-dma.txt 2014-07-20 22:06:35.141325759 +0200 @@ -0,0 +1,28 @@ +Xilinx AXI DMA engine, it does transfers between memory and device. It can be +configured to have one channel or two channels. If configured as two +channels, one is to transmit to device and another is to receive from +device. + +Required properties: +- compatible: Should be "xlnx,axi-dma" +- reg: Should contain DMA registers location and length. +- interrupts: Should contain per channel DMA interrupts. +- compatible (child node): It should be either "xlnx,axi-dma-mm2s-channel" or + "xlnx,axi-dma-s2mm-channel". It depends on the hardware design and it + can also have both channels. + +Example: +++++++++ + +axi_dma_0: axidma@40400000 { + compatible = "xlnx,axi-dma"; + reg = < 0x40400000 0x10000 >; + dma-channel@40400000 { + compatible = "xlnx,axi-dma-mm2s-channel"; + interrupts = < 0 59 4 >; + } ; + dma-channel@40030030 { + compatible = "xlnx,axi-dma-s2mm-channel"; + interrupts = < 0 58 4 >; + } ; +} ; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/dma/xilinx/axi-vdma.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/dma/xilinx/axi-vdma.txt 2014-07-20 22:06:35.147325660 +0200 @@ -0,0 +1,71 @@ +Xilinx AXI VDMA engine, it does transfers between memory and video devices. +It can be configured to have one channel or two channels. If configured +as two channels, one is to transmit to the video device and another is +to receive from the video device. + +Required properties: +- compatible: Should be "xlnx,axi-vdma" +- #dma-cells: Should be <1>, see "dmas" property below +- reg: Should contain VDMA registers location and length. +- interrupts: Should contain per channel VDMA interrupts. +- compatible (child node): It should be either "xlnx,axi-vdma-mm2s-channel" or + "xlnx,axi-vdma-s2mm-channel". It depends on the hardware design and it + can also have both channels. +- xlnx,device-id: Should contain device number in each channel. It should be + {0,1,2...so on} to the number of VDMA devices configured in hardware. +- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. +- xlnx,data-width: Should contain the stream data width, takes {32,64...so on}. +- xlnx,flush-fsync: (Optional) Tells whether which channel to Flush on Fsync. + It takes following values: + {1}, flush both channels + {2}, flush mm2s channel + {3}, flush s2mm channel +- xlnx,include-sg: (Optional) Tells whether configured for Scatter-mode in + the hardware. +- xlnx,include-dre: (Optional) Tells whether hardware is configured for Data + Realignment Engine. +- xlnx,genlock-mode: (Optional) Tells whether Genlock synchornisation is + enabled/disabled in hardware. + +Example: +++++++++ + +axi_vdma_0: axivdma@40030000 { + compatible = "xlnx,axi-vdma"; + #dma_cells = <1>; + reg = < 0x40030000 0x10000 >; + xlnx,flush-fsync = <0x1>; + dma-channel@40030000 { + compatible = "xlnx,axi-vdma-mm2s-channel"; + interrupts = < 0 54 4 >; + xlnx,num-fstores = <0x8>; + xlnx,device-id = <0x0>; + xlnx,datawidth = <0x40>; + } ; + dma-channel@40030030 { + compatible = "xlnx,axi-vdma-s2mm-channel"; + interrupts = < 0 53 4 >; + xlnx,num-fstores = <0x8>; + xlnx,device-id = <0x0>; + xlnx,datawidth = <0x40>; + } ; +} ; + + +* Xilinx Video DMA client + +Required properties: +- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, + where Channel ID is '0' for write/tx and '1' for read/rx + channel. +- dma-names: a list of DMA channel names, one per "dmas" entry + +VDMA Test Client Example: ++++++++++++++++++++++++++ + +vdmatest_0: vdmatest@0 { + compatible ="xlnx,axi-vdma-test"; + dmas = <&axi_vdma_0 0 + &axi_vdma_0 1>; + dma-names = "vdma0", "vdma1"; +} ; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/dma/xilinx/vdmatest.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/dma/xilinx/vdmatest.txt 2014-07-20 22:06:35.153325561 +0200 @@ -0,0 +1,39 @@ +* Xilinx Video DMA Test client + +Required properties: +- compatible: Should be "xlnx,axi-vdma-test" +- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, + where Channel ID is '0' for write/tx and '1' for read/rx + channel. +- dma-names: a list of DMA channel names, one per "dmas" entry +- xlnx,num-fstores: Should be the number of framebuffers as configured in + VDMA device node. + +Example: +++++++++ + +vdmatest_0: vdmatest@0 { + compatible ="xlnx,axi-vdma-test"; + dmas = <&axi_vdma_0 0 + &axi_vdma_0 1>; + dma-names = "vdma0", "vdma1"; + xlnx,num-fstores = <0x8>; +} ; + + +Xilinx Video DMA Device Node Example +++++++++++++++++++++++++++++++++++++ +axi_vdma_0: axivdma@44A40000 { + compatible = "xlnx,axi-vdma"; + ... + dma-channel@44A40000 { + ... + xlnx,num-fstores = <0x8>; + ... + } ; + dma-channel@44A40030 { + ... + xlnx,num-fstores = <0x8>; + ... + } ; +} ; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/drm/xilinx/cresample.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/drm/xilinx/cresample.txt 2014-07-20 22:06:35.165325363 +0200 @@ -0,0 +1,22 @@ +Device-Tree bindings for Xilinx Chroma Resampler(CRESAMPLE) + +Xilinx CRESAMPLE provides the chroma resampling of YUV formats. + +Required properties: + - compatible: value should be "xlnx,v-cresample-3.01.a" + - reg: base address and size of the CRESAMPLE IP + - xlnx,input-format, xlnx,output-format: the input/output video formats of + CRESAMPLE. The value should be one of following format strings. + + yuv422 + yuv444 + yuv420 + +Example: + + v_cresample_0: v-cresample@40020000 { + compatible = "xlnx,v-cresample-3.01.a"; + reg = <0x40020000 0x10000>; + xlnx,input-format = "yuv444"; + xlnx,output-format = "yuv422"; + }; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/drm/xilinx/osd.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/drm/xilinx/osd.txt 2014-07-20 22:06:35.171325264 +0200 @@ -0,0 +1,19 @@ +Device-Tree bindings for Xilinx Video On Screen Display(OSD) + +Xilinx OSD provides the multiplane support. Some properties can be configured +in IP synthesis. + +Required properties: + - compatible: value should be "xlnx,v-osd-5.01.a" + - reg: base address and size of the OSD IP + - xlnx,num-layers: the number of layers(up to 8) supported by OSD + - xlnx,screen-width: the maximum size(up to 4096) of screen pixel width by OSD + +Example: + + v_osd_0: v-osd@40040000 { + compatible = "xlnx,v-osd-5.01.a"; + reg = <0x40040000 0x10000>; + xlnx,num-layers = <2>; + xlnx,screen-width = <1920>; + }; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/drm/xilinx/rgb2ycrcb.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/drm/xilinx/rgb2ycrcb.txt 2014-07-20 22:06:35.177325165 +0200 @@ -0,0 +1,14 @@ +Device-Tree bindings for Xilinx RGB to YCrCb convertor(RGB2YCRCB) + +Xilinx RGB2YCRCB converts the pixel format from RGB to YCrCb + +Required properties: + - compatible: value should be "xlnx,v-rgb2ycrcb-6.01.a" + - reg: base address and size of the RGB2YCRCB IP + +Example: + + v_rgb2ycrcb_0: v-rgb2ycrcb@40030000 { + compatible = "xlnx,v-rgb2ycrcb-6.01.a"; + reg = <0x40030000 0x10000>; + }; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/drm/xilinx/vtc.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/drm/xilinx/vtc.txt 2014-07-20 22:06:35.183325066 +0200 @@ -0,0 +1,18 @@ +Device-Tree bindings for Xilinx Video Timing Controller(VTC) + +Xilinx VTC provides the timings for Video IPs. + +Required properties: + - compatible: value should be "xlnx,v-tc-5.01.a" + - reg: base address and size of the VTC IP + - interrupts: the interrupt number + - interrupts-parent: the phandle for interrupt controller + +Example: + + v_tc_0: v-tc@40010000 { + compatible = "xlnx,v-tc-5.01.a"; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 54 4>; + reg = <0x40010000 0x10000>; + }; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/drm/xilinx/xilinx_drm.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/drm/xilinx/xilinx_drm.txt 2014-07-20 22:06:35.190324951 +0200 @@ -0,0 +1,71 @@ +Device-Tree bindings for Xilinx DRM + +Xilinx DRM supports the display pipelines with Xilinx soft IPs on FPGA and +IPs on Xilinx boards. + +The example hardware pipeline is depicted below +(*IPs in parentheses() are optional. IPs in brackets[] don't require drivers). +vdma-[remap]-(rgb2yuv)-(cresample)-(osd)-(rgb2yuv)-(cresample)-[axi2vid]-adv7511 +(vdma-[remap]-(rgb2yuv)-(cresample)-|) | + si570 -> vtc + +Required properties: + - compatible: value should be "xlnx,drm". + - osd: the phandle for on screen display IP if used in the hardware design + - rgb2yuv: the phandle for rgb2ycrcb IP if used in the hardware design + - cresample: the phandle for chroma resampler IP if used in the hardware design + - vtc: the phandle for video timing controller IP + - encoder-slave: the phandle for the encoder slave. + - clocks: the phandle for the pixel clock + - planes: the subnode for resources for each plane + +Required plane properties: + - dmas: the phandle list of DMA specifiers + - dma-names: the indentifier strings for DMAs + - rgb2yuv: the phandle for rgb2ycrcb IP if used for plane + - cresample: the phandle for chroma resampler IP if used for plane + +The pipeline can be configured as following examples or more. + - Example 1: +vdma - [remap] - rgb2yuv - cresample - [axi2vid] - adv7511 + | + si570 - vtc + xilinx_drm { + compatible = "xlnx,drm"; + vtc = <&v_tc_0>; + encoder-slave = <&adv7511>; + clocks = <&si570>; + planes { + plane0 { + dma = <&axi_vdma_0>; + dma-names = "vdma"; + rgb2yuv = <&v_rgb2ycrcb_0>; + cresample = <&v_cresample_0>; + }; + }; + }; + + - Example 2: +vdma - [remap] --------- osd - cresample - [axi2vid] - adv7511 +vdma - [remap] - rgb2yuv -| | + si570 - vtc + + xilinx_drm { + compatible = "xlnx,drm"; + osd = <&v_osd_0>; + cresample = <&v_cresample_0>; + vtc = <&v_tc_0>; + encoder-slave = <&adv7511>; + clocks = <&si570>; + planes { + plane0 { + dma = <&axi_vdma_0>; + dma-names = "vdma"; + }; + plane1 { + dma = <&axi_vdma_1>; + dma-names = "vdma"; + rgb2yuv = <&v_rgb2ycrcb_0>; + }; + }; + }; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/edac/zynq_edac.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/edac/zynq_edac.txt 2014-07-20 22:06:35.200324786 +0200 @@ -0,0 +1,18 @@ +Zynq EDAC driver, it does reports the DDR ECC single bit errors that are +corrected and double bit ecc errors that are detected by the DDR ECC controller. +ECC support for DDR is available in half-bus width(16 bit) configuration only. + +Required properties: +- compatible: Should be "xlnx,ps7-ddrc" or "xlnx,ps7-ddrc-1.00.a" +- reg: Should contain DDR controller registers location and length. + +Example: +++++++++ + +ps7_ddrc_0: ps7-ddrc@f8006000 { + compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc"; + reg = <0xf8006000 0x1000>; +}; + +Zynq EDAC driver detects the DDR ECC enable state by reading the appropriate +control register. Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt =================================================================== --- linux-3.12.24-rt38-xilinx.orig/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt 2014-07-20 22:05:50.330065070 +0200 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt 2014-07-20 22:06:35.234324225 +0200 @@ -9,7 +9,9 @@ - compatible : Should be "xlnx,xps-gpio-1.00.a" - reg : Address and length of the register set for the device - #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). + second cell is used to specify channel offset: + 0 - first channel + 8 - second channel - gpio-controller : Marks the device node as a GPIO controller. Optional properties: Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/media/xilinx/video.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/media/xilinx/video.txt 2014-07-20 22:06:35.248323994 +0200 @@ -0,0 +1,39 @@ +DT bindings for Xilinx video IP cores +------------------------------------- + +Xilinx video IP cores process video streams by acting as video sinks and/or +sources. They are connected by links through their input and output ports, +creating a video pipeline. + +Each video IP core is represented by an AMBA bus child node in the device +tree using bindings documented in this directory. Connections between the IP +cores are represented as defined in ../video-interfaces.txt. + +Common properties +----------------- + +The following properties are common to all Xilinx video IP cores. + +- xlnx,axi-video-format: This property represents a video format transmitted + on an AXI bus between video IP cores. How the format relates to the IP core + is decribed in the IP core bindings documentation. The following formats are + supported. + + rbg + xrgb + yuv422 + +- xlnx,axi-video-width: This property qualifies the video format with the + sample width expressed as a number of bits per pixel component. All components + must use the same width. + +The following table lists the supported formats and widths combinations, along +with the corresponding media bus pixel code. + +----------------+-------+------------------------------------------------------- +Format | Width | Media bus code +----------------+-------+------------------------------------------------------- +rbg | 8 | V4L2_MBUS_FMT_RBG888_1X24 +xrgb | 8 | V4L2_MBUS_FMT_RGB888_1X32_PADHI +yuv422 | 8 | V4L2_MBUS_FMT_UYVY8_1X16 +----------------+-------+------------------------------------------------------- Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/media/xilinx/xlnx,axi-remapper.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/media/xilinx/xlnx,axi-remapper.txt 2014-07-20 22:06:35.254323895 +0200 @@ -0,0 +1,57 @@ +Xilinx Video Remapper +--------------------- + +The IP core remaps input pixel components to produce an output pixel with +less, more or the same number of components as the input pixel. + +Required properties: + +- compatible: Must be "xlnx,axi-remapper". + +- xlnx,axi-video-width: Video pixel component width, as defined in video.txt. + +- #xlnx,axi-s-components: Number of components per pixel at the input port + (between 1 and 4 inclusive). + +- #xlnx,axi-m-components: Number of components per pixel at the output port + (between 1 and 4 inclusive). + +- xlnx,axi-component-maps: Remapping configuration represented as an array of + integers. The array contains one entry per output component, in the low to + high order. Each entry corresponds to the zero-based position of the + corresponding input component, or the value 4 to drive a constant value on + the output component. For example, to remap RGB to BGR use <2 1 0>, and to + remap RBG to xRGB use <1 0 2 4>. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The remapper as an input port (0) and and output port (1). + +Example: RBG to xRGB remapper + + axi_remapper_0: axi_remapper { + compatible = "xlnx,axi-remapper"; + + xlnx,axi-video-width = <8>; + + #xlnx,axi-s-components = <3>; + #xlnx,axi-m-components = <4>; + xlnx,axi-component-maps = <1 0 2 4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + remap0_in: endpoint { + remote-endpoint = <&tpg0_out>; + }; + }; + port@1 { + reg = <1>; + remap0_out: endpoint { + remote-endpoint = <&sobel0_in>; + }; + }; + }; + }; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/media/xilinx/xlnx,axi-tpg.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/media/xilinx/xlnx,axi-tpg.txt 2014-07-20 22:06:35.260323796 +0200 @@ -0,0 +1,30 @@ +Xilinx Video Test Pattern Generator (TPG) +----------------------------------------- + +Required properties: + +- compatible: Must be "xlnx,axi-tpg". + +- reg: Physical base address and length of the registers set for the device. + +- xlnx,axi-video-format, xlnx,axi-video-width: Video format and width, as + defined in video.txt. + +- port: Video port, using the DT bindings defined in ../video-interfaces.txt. + The TPG has a single output port numbered 0. + +Example: + + axi_tpg_0: axi_tpg@40050000 { + compatible = "xlnx,axi-tpg"; + reg = <0x40050000 0x10000>; + + xlnx,axi-video-format = "yuv422"; + xlnx,axi-video-width = <8>; + + port { + tpg0_out: endpoint { + remote-endpoint = <&remap0_in>; + }; + }; + }; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/misc/xilinx-axitrafgen.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/misc/xilinx-axitrafgen.txt 2014-07-20 22:06:35.270323631 +0200 @@ -0,0 +1,21 @@ +* Xilinx AXI Traffic generator IP + +Required properties: +- compatible: "xlnx,axi-traffic-gen" +- interrupts: Should contain AXI Traffic Generator interrupts. +- interrupt-parent: Must be core interrupt controller. +- reg: Should contain AXI Traffic Generator registers location and length. +- interrupt-names: Should contain both the intr names of device - error + and completion. +- xlnx,device-id: Device instance Id. + +Example: +++++++++ +axi_traffic_gen_1: axi-traffic-gen@76000000 { + compatible = "xlnx,axi-traffic-gen-1.0", "xlnx,axi-traffic-gen"; + interrupts = <0 2 2 2>; + interrupt-parent = <&axi_intc_1>; + interrupt-names = "err-out", "irq-out"; + reg = <0x76000000 0x800000>; + xlnx,device-id = <0x0>; +} ; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt 2014-07-20 22:06:35.281323450 +0200 @@ -0,0 +1,27 @@ +Device Tree Bindings for the Arasan SDHCI Controller + + The bindings follow the mmc[1], clock[2] and interrupt[3] bindings. Only + deviations are documented here. + + [1] Documentation/devicetree/bindings/mmc/mmc.txt + [2] Documentation/devicetree/bindings/clock/clock-bindings.txt + [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + +Required Properties: + - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' + - reg: From mmc bindings: Register location and length. + - clocks: From clock bindings: Handles to clock inputs. + - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" + - interrupts: Interrupt specifier + - interrupt-parent: Phandle for the interrupt controller that services + interrupts for this device. + +Example: + sdhci@e0100000 { + compatible = "arasan,sdhci-8.9a"; + reg = <0xe0100000 0x1000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + interrupt-parent = <&gic>; + interrupts = <0 24 4>; + } ; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/net/can/xilinx_can.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/net/can/xilinx_can.txt 2014-07-20 22:06:35.300323136 +0200 @@ -0,0 +1,36 @@ +Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings +--------------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,ps7-can" for Zynq CAN controllers and + "xlnx,axi-can-1.00.a" for Axi CAN controllers. +- reg : Physical base address and size of the Axi CAN/Zynq + CANPS registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller +- clock-names : List of input clock names - "ref_clk", "aper_clk" + (See clock bindings for details). +- clocks : Clock phandles (see clock bindings for details). + + +Example: + +For Zynq CANPS Dts file: + ps7_can_0: ps7-can@e0008000 { + compatible = "xlnx,ps7-can"; + clocks = <&clkc 19>, <&clkc 36>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xe0008000 0x1000>; + interrupts = <0 28 4>; + interrupt-parent = <&gic>; + }; +For Axi CAN Dts file: + axi_can_0: axi-can@40000000 { + compatible = "xlnx,axi-can-1.00.a"; + clocks = <&clkc 0>; + clock-names = "ref_clk" ; + reg = <0x40000000 0x10000>; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 59 1>; + }; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/pci/xilinx-axipcie.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/pci/xilinx-axipcie.txt 2014-07-20 22:06:35.311322955 +0200 @@ -0,0 +1,31 @@ +* Xilinx AXI PCIe Root Port Bridge + +Required properties: + compatible: Should be "xlnx,axi-pcie-1.05.a" + reg: Should contain AXI PCIe registers location and length. + interrupts: Should contain AXI PCIe interrupts. + ranges: These are the parameters for each PCIe bar implemented within the IP + The ranges property is < >. + The parent address #address-cells is taken from the parent node. + xlnx, include-rc: Root Port (=1) or End Point(=0) + xlnx,axibar2pciebar-0: Translates address from AXI to PCIe + xlnx,pciebar2axibar-0: Translates address from PCIe to AXI + +Example: +++++++++ + + ps7_axi_interconnect_0: axi@0 { + #address-cells = <1>; + #size-cells = <1>; + pci_express: axi-pcie@50000000 { + #address-cells = <3>; + #size-cells = <2>; + compatible = "xlnx,axi-pcie-1.05.a"; + interrupts = < 0 52 4 >; + ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >; + reg = < 0x50000000 0x10000000 >; + xlnx,include-rc = <0x1>; + xlnx,axibar2pciebar-0 = <0x60000000>; + xlnx,pciebar2axibar-0 = <0x0>; + }; + }; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/remoteproc/mb_remoteproc.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/remoteproc/mb_remoteproc.txt 2014-07-20 22:06:35.321322790 +0200 @@ -0,0 +1,46 @@ +Xilinx ARM-Microblaze remoteproc driver + +This driver requires specific Zynq hardware design where Microblaze is added +to the programmable logic. +Microblaze is connected with PS block via axi bus connected to PS HP port +to ensure access to PS DDR. +Communication channels are done via soft GPIO IP connected to PS block +and to Microblaze. There are also 2 gpio control signals reset and debug +which are used for reseting Microblaze. + +Required properties: +- compatible : Should be "xlnx,mb_remoteproc" +- reg : Address and length of the ddr address space +- bram: Phandle to bram controller which can access Microblaze BRAM +- bram-firmware : Microblaze BRAM bootloader name +- firmware : Default firmware name which can be override by + "firmware" module parameter +- reset : Gpio phandle which reset Microblaze remoteproc +- debug : Gpio phandle which setup Microblaze to debug state +- ipino : Gpio phandle for Microblaze to ARM communication +- vring0 : Gpio phandle for ARM to Microblaze communication vring 0 +- vring1 : Gpio phandle for ARM to Microblaze communication vring 1 + +Microblaze SoC can be also connected to the PS block via a axi bus. +That's why there is the option to allocate interrupts for Microblaze use only. +The driver will allocate interrupts to itself and Microblaze sw has to ensure +that interrupts are properly enabled and handled by Microblaze interrupt +controller. + +Optional properties: + - interrupts : Interrupt mapping for remoteproc + - interrupt-parent : Phandle for the interrupt controller + +Example: +test_mb: mb_remoteproc-test@800000 { + compatible = "xlnx,mb_remoteproc"; + reg = < 0x8000000 0x8000000 >; + bram = <&axi_bram_ctrl_0>; + bram-firmware = "mb.bin"; + firmware = "image.elf"; + reset = <&zynq_gpio_reset 1 0>; + debug = <&zynq_gpio_reset 0 0>; + ipino = <&zynq_gpio_vring 0 0>; + vring0 = <&zynq_gpio_vring 1 0>; + vring1 = <&zynq_gpio_vring 2 0>; +} ; Index: linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/xilinx.txt =================================================================== --- linux-3.12.24-rt38-xilinx.orig/Documentation/devicetree/bindings/xilinx.txt 2014-07-20 22:05:50.332065037 +0200 +++ linux-3.12.24-rt38-xilinx/Documentation/devicetree/bindings/xilinx.txt 2014-07-20 22:06:35.330322642 +0200 @@ -253,6 +253,7 @@ Optional properties: - 8-bit (empty) : Set this property for SystemACE in 8 bit mode + - port-number = : Set port number for particular device iii) Xilinx EMAC and Xilinx TEMAC Index: linux-3.12.24-rt38-xilinx/Documentation/pmods/00-INDEX =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/pmods/00-INDEX 2014-07-20 22:06:35.341322460 +0200 @@ -0,0 +1,8 @@ +Documentation for pmods, a set of peripheral modules provided by Digilent Inc., +which can be plugged to various development boards to add additional functionalities. +These drivers are maintained by Digilent Inc. + +00-INDEX + - this file +pmodoled.txt + - PmodOLED: 128 by 32 pixel 0.9" Organic LED Graphic Display Index: linux-3.12.24-rt38-xilinx/Documentation/pmods/pmodoled.txt =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/Documentation/pmods/pmodoled.txt 2014-07-20 22:06:35.347322361 +0200 @@ -0,0 +1,137 @@ +PmodOLED +======== + +Copyright 2012, Digilent Inc. + + +Description +----------- + +The PmodOLED features an SPI-controlled monochrome OLED display, +perfect for embedded applications requiring small, complex visual output. + +The PmodOLED uses a standard 12-pin connector to display output on +a 128x32 pixel organic LED (OLED) panel. The graphic display panel uses +the Solomon Systech SSD1306 display controller. + +An SPI interface is used to configure the display, +as well as to send the bitmap data to the device. + +The PmodOLED displays the last image drawn on the screen until it is +powered down or a new image is drawn to the display. Refreshing and +updating is handled internally. + +The Reference Manual for PmodOLED display is available online at +Digilent Inc. Website (www.digilentinc.com) + +For more information on the OLED display interface, see the +UG-2832HSWEG04 datasheet available online or from Univisio. + +The OLED display uses a compatible command set from the SSD1306 device. +For more information, see the SSD1306 datasheet available at +www.solomon-systech.com. + + +Interface +--------- + +Signal Description + +CS SPI Chip Select (Slave Select) +SDIN SPI Data In (MOSI) +SCLK SPI Clock +D/C Data/Command Control +RES Power Reset +VBATC VBAT Battery Voltage Control +VDDC VDD Logic Voltage Control + + +Devicetree +---------- + +Required Properties: +- compatible : Should be "dlgnt,pmodoled-gpio" +- vbat-gpio : Should specify the GPIO for VBATC, see "gpios property" in + Documentation/devicetree/gpio.txt. +- vdd-gpio : Should specify the GPIO for VDDC, see "gpios property" in + Documentation/devicetree/gpio.txt. +- res-gpio : Should specify the GPIO for RES, see "gpios property" in + Documentation/devicetree/gpio.txt. +- dc-gpio : Should specify the GPIO for D/C, see "gpios property" in + Documentation/devicetree/gpio.txt. +- spi-bus-num : Should specify the bus number for PmodOLED SPI controller. + This value cannot be shared by any other SPI controller present in the + device tree. +- spi-sclk-gpio : Should specify the GPIO for SCLK, see "gpios property" in + Documentation/devicetree/gpio.txt. +- spi-sdin-gpio : Should specify the GPIO for SDIN, see "gpios property" in + Documentation/devicetree/gpio.txt. + +Optional Properties: +- spi-cs-gpio : Should specify the GPIO for CS, see "gpios property" in + Documentation/devicetree/gpio.txt. If unspecified, CS is assumed to be + tied to ground. + +Examples: + +zed_oled { + compatible = "dglnt,pmodoled-gpio"; + /* GPIO Pins */ + vbat-gpio = <&gpiops 55 0>; + vdd-gpio = <&gpiops 56 0>; + res-gpio = <&gpiops 57 0>; + dc-gpio = <&gpiops 58 0>; + /* SPI-GPIOs */ + spi-bus-num = <2>; + spi-sclk-gpio = <&gpiops 59 0>; + spi-sdin-gpio = <&gpiops 60 0>; +}; + +pmodoled_A { + compatible = "dglnt,pmodoled-gpio"; + vbat-gpio = <&gpiops 88 0>; + vdd-gpio = <&gpiops 89 0>; + res-gpio = <&gpiops 87 0>; + dc-gpio = <&gpiops 86 0>; + spi-bus-num = <3>; + spi-sclk-gpio = <&gpiops 85 0>; + spi-sdin-gpio = <&gpiops 83 0>; + spi-cs-gpio = <&gpiops 82 0>; +}; + + +Configuration +------------- + +The PmodOLED is located in the kernel configuration menu at +Device Drivers -> Pmods -> PmodOLED. The driver can be built into the kernel +by selecting (*) for it, or loadable module by selecting (M) for it. + + +Device Nodes +------------ + +A char device node will be created for each PmodOLED device automatically. +The name of the node is default to the one declared in the device tree. + + +Read/Writes +----------- + +The driver provides a 512 Byte display buffer for the display of PmodOLED. +The Whole screen is divided into four lines, each of them is 128 bits wide +and 8 bits high, as shown in the figure below. + + +--------------------------...----------------------------+ + + Line 4 + + +--------------------------...----------------------------+ + + Line 3 + + +--------------------------...----------------------------+ + + Line 2 + + +--------------------------...----------------------------+ MSB (bit 7) + + Line 1 + + +--------------------------...----------------------------+ LSB (bit 0) +byte 127 byte 0 + +Users can perform read and write functions to the device node to access the data +inside the display buffer. Index: linux-3.12.24-rt38-xilinx/drivers/char/Kconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/char/Kconfig 2014-07-20 22:05:50.188067413 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/char/Kconfig 2014-07-20 22:06:35.363322097 +0200 @@ -378,6 +378,13 @@ If unsure, say N. +config XILINX_DEVCFG + tristate "Xilinx Device Configuration" + depends on ARCH_ZYNQ + help + This option enables support for the Xilinx device configuration driver. + If unsure, say N + config R3964 tristate "Siemens R3964 line discipline" depends on TTY Index: linux-3.12.24-rt38-xilinx/drivers/char/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/char/Makefile 2014-07-20 22:05:50.186067446 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/char/Makefile 2014-07-20 22:06:35.373321932 +0200 @@ -31,6 +31,7 @@ obj-$(CONFIG_EFI_RTC) += efirtc.o obj-$(CONFIG_DS1302) += ds1302.o obj-$(CONFIG_XILINX_HWICAP) += xilinx_hwicap/ +obj-$(CONFIG_XILINX_DEVCFG) += xilinx_devcfg.o ifeq ($(CONFIG_GENERIC_NVRAM),y) obj-$(CONFIG_NVRAM) += generic_nvram.o else Index: linux-3.12.24-rt38-xilinx/drivers/char/xilinx_devcfg.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/char/xilinx_devcfg.c 2014-07-20 22:06:35.396321553 +0200 @@ -0,0 +1,2085 @@ +/* + * Xilinx Zynq Device Config driver + * + * Copyright (c) 2011 - 2013 Xilinx Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void zynq_slcr_init_preload_fpga(void); +extern void zynq_slcr_init_postload_fpga(void); + +#define DRIVER_NAME "xdevcfg" +#define XDEVCFG_DEVICES 1 + +/* An array, which is set to true when the device is registered. */ +static DEFINE_MUTEX(xdevcfg_mutex); + +/* Constant Definitions */ +#define XDCFG_CTRL_OFFSET 0x00 /* Control Register */ +#define XDCFG_LOCK_OFFSET 0x04 /* Lock Register */ +#define XDCFG_INT_STS_OFFSET 0x0C /* Interrupt Status Register */ +#define XDCFG_INT_MASK_OFFSET 0x10 /* Interrupt Mask Register */ +#define XDCFG_STATUS_OFFSET 0x14 /* Status Register */ +#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /* DMA Source Address Register */ +#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /* DMA Destination Address Reg */ +#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /* DMA Source Transfer Length */ +#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /* DMA Destination Transfer */ +#define XDCFG_UNLOCK_OFFSET 0x34 /* Unlock Register */ +#define XDCFG_MCTRL_OFFSET 0x80 /* Misc. Control Register */ + +/* Control Register Bit definitions */ +#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /* Program signal to + * Reset FPGA */ +#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /* Enable PCAP for PR */ +#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /* Enable PCAP */ +#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /* AES Enable Mask */ +#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /* SEU Enable Mask */ +#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /* Secure Non Invasive + * Debug Enable */ +#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /* Secure Invasive + * Debug Enable */ +#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /* Non-Invasive Debug + * Enable */ +#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /* Invasive Debug + * Enable */ +#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /* DAP Enable Mask */ + +/* Lock register bit definitions */ + +#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /* Lock AES_EN update */ +#define XDCFG_LOCK_SEU_MASK 0x00000004 /* Lock SEU_En update */ +#define XDCFG_LOCK_DBG_MASK 0x00000001 /* This bit locks + * security config + * including: DAP_En, + * DBGEN,NIDEN, SPNIEN */ + +/* Miscellaneous Control Register bit definitions */ +#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /* Internal PCAP loopback */ + +/* Status register bit definitions */ +#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /* FPGA init status */ + +/* Interrupt Status/Mask Register Bit definitions */ +#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /* DMA Command Done */ +#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /* FPGA programmed */ +#define XDCFG_IXR_ERROR_FLAGS_MASK 0x00F0F860 +#define XDCFG_IXR_ALL_MASK 0xF8F7F87F +/* Miscellaneous constant values */ +#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /* Invalid DMA address */ + +static const char * const fclk_name[] = { + "fclk0", + "fclk1", + "fclk2", + "fclk3" +}; +#define NUMFCLKS ARRAY_SIZE(fclk_name) + +/** + * struct xdevcfg_drvdata - Device Configuration driver structure + * + * @dev: Pointer to the device structure + * @cdev: Instance of the cdev structure + * @devt: Pointer to the dev_t structure + * @class: Pointer to device class + * @fclk_class: Pointer to fclk device class + * @dma_done: The dma_done status bit for the DMA command completion + * @error_status: The error status captured during the DMA transfer + * @irq: Interrupt number + * @clk: Peripheral clock for devcfg + * @fclk: Array holding references to the FPGA clocks + * @fclk_exported: Flag inidcating whether an FPGA clock is exported + * @is_open: The status bit to indicate whether the device is opened + * @sem: Instance for the mutex + * @lock: Instance of spinlock + * @base_address: The virtual device base address of the device registers + * @is_partial_bitstream: Status bit to indicate partial/full bitstream + */ +struct xdevcfg_drvdata { + struct device *dev; + struct cdev cdev; + dev_t devt; + struct class *class; + struct class *fclk_class; + int irq; + struct clk *clk; + struct clk *fclk[NUMFCLKS]; + u8 fclk_exported[NUMFCLKS]; + volatile bool dma_done; + volatile int error_status; + bool is_open; + struct mutex sem; + spinlock_t lock; + void __iomem *base_address; + int ep107; + bool is_partial_bitstream; + bool endian_swap; + char residue_buf[3]; + int residue_len; +}; + +/** + * struct fclk_data - FPGA clock data + * @clk: Pointer to clock + * @enable: Flag indicating enable status of the clock + * @rate_rnd: Rate to be rounded for round rate operation + */ +struct fclk_data { + struct clk *clk; + int enabled; + unsigned long rate_rnd; +}; + +/* Register read/write access routines */ +#define xdevcfg_writereg(offset, val) __raw_writel(val, offset) +#define xdevcfg_readreg(offset) __raw_readl(offset) + +/** + * xdevcfg_reset_pl() - Reset the programmable logic. + * @base_address: The base address of the device. + * + * Must be called with PCAP clock enabled + */ +static void xdevcfg_reset_pl(void __iomem *base_address) +{ + /* + * Create a rising edge on PCFG_INIT. PCFG_INIT follows PCFG_PROG_B, + * so we need to * poll it after setting PCFG_PROG_B to make sure that + * the rising edge happens. + */ + xdevcfg_writereg(base_address + XDCFG_CTRL_OFFSET, + (xdevcfg_readreg(base_address + XDCFG_CTRL_OFFSET) | + XDCFG_CTRL_PCFG_PROG_B_MASK)); + while (!(xdevcfg_readreg(base_address + XDCFG_STATUS_OFFSET) & + XDCFG_STATUS_PCFG_INIT_MASK)) + ; + + xdevcfg_writereg(base_address + XDCFG_CTRL_OFFSET, + (xdevcfg_readreg(base_address + XDCFG_CTRL_OFFSET) & + ~XDCFG_CTRL_PCFG_PROG_B_MASK)); + while (xdevcfg_readreg(base_address + XDCFG_STATUS_OFFSET) & + XDCFG_STATUS_PCFG_INIT_MASK) + ; + + xdevcfg_writereg(base_address + XDCFG_CTRL_OFFSET, + (xdevcfg_readreg(base_address + XDCFG_CTRL_OFFSET) | + XDCFG_CTRL_PCFG_PROG_B_MASK)); + while (!(xdevcfg_readreg(base_address + XDCFG_STATUS_OFFSET) & + XDCFG_STATUS_PCFG_INIT_MASK)) + ; +} + +/** + * xdevcfg_irq() - The main interrupt handler. + * @irq: The interrupt number. + * @data: Pointer to the driver data structure. + * returns: IRQ_HANDLED after the interrupt is handled. + **/ +static irqreturn_t xdevcfg_irq(int irq, void *data) +{ + u32 intr_status; + struct xdevcfg_drvdata *drvdata = data; + + spin_lock(&drvdata->lock); + + intr_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_INT_STS_OFFSET); + + /* Clear the interrupts */ + xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET, + intr_status); + + if ((intr_status & XDCFG_IXR_DMA_DONE_MASK) == XDCFG_IXR_DMA_DONE_MASK) + drvdata->dma_done = 1; + + if ((intr_status & XDCFG_IXR_ERROR_FLAGS_MASK) == + XDCFG_IXR_ERROR_FLAGS_MASK) + drvdata->error_status = 1; + + spin_unlock(&drvdata->lock); + + return IRQ_HANDLED; +} + +/** + * xdevcfg_write() - The is the driver write function. + * + * @file: Pointer to the file structure. + * @buf: Pointer to the bitstream location. + * @count: The number of bytes to be written. + * @ppos: Pointer to the offset value + * returns: Success or error status. + **/ +static ssize_t +xdevcfg_write(struct file *file, const char __user *buf, size_t count, + loff_t *ppos) +{ + char *kbuf; + int status; + unsigned long timeout; + u32 intr_reg; + dma_addr_t dma_addr; + u32 transfer_length = 0; + struct xdevcfg_drvdata *drvdata = file->private_data; + size_t user_count = count; + int i; + + status = clk_enable(drvdata->clk); + if (status) + return status; + + status = mutex_lock_interruptible(&drvdata->sem); + + if (status) + goto err_clk; + + kbuf = dma_alloc_coherent(drvdata->dev, count + drvdata->residue_len, + &dma_addr, GFP_KERNEL); + if (!kbuf) { + status = -ENOMEM; + goto err_unlock; + } + + /* Collect stragglers from last time (0 to 3 bytes) */ + memcpy(kbuf, drvdata->residue_buf, drvdata->residue_len); + + /* Fetch user data, appending to stragglers */ + if (copy_from_user(kbuf + drvdata->residue_len, buf, count)) { + status = -EFAULT; + goto error; + } + + /* Include stragglers in total bytes to be handled */ + count += drvdata->residue_len; + + /* First block contains a header */ + if (*ppos == 0 && count > 4) { + /* Look for sync word */ + for (i = 0; i < count - 4; i++) { + if (memcmp(kbuf + i, "\x66\x55\x99\xAA", 4) == 0) { + pr_debug("Found normal sync word\n"); + drvdata->endian_swap = 0; + break; + } + if (memcmp(kbuf + i, "\xAA\x99\x55\x66", 4) == 0) { + pr_debug("Found swapped sync word\n"); + drvdata->endian_swap = 1; + break; + } + } + /* Remove the header, aligning the data on word boundary */ + if (i != count - 4) { + count -= i; + memmove(kbuf, kbuf + i, count); + } + } + + /* Save stragglers for next time */ + drvdata->residue_len = count % 4; + count -= drvdata->residue_len; + memcpy(drvdata->residue_buf, kbuf + count, drvdata->residue_len); + + /* Fixup endianess of the data */ + if (drvdata->endian_swap) { + for (i = 0; i < count; i += 4) { + u32 *p = (u32 *)&kbuf[i]; + *p = swab32(*p); + } + } + + /* Enable DMA and error interrupts */ + xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET, + XDCFG_IXR_ALL_MASK); + + + xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET, + (u32) (~(XDCFG_IXR_DMA_DONE_MASK | + XDCFG_IXR_ERROR_FLAGS_MASK))); + + drvdata->dma_done = 0; + drvdata->error_status = 0; + + /* Initiate DMA write command */ + if (count < 0x1000) + xdevcfg_writereg(drvdata->base_address + + XDCFG_DMA_SRC_ADDR_OFFSET, (u32)(dma_addr + 1)); + else + xdevcfg_writereg(drvdata->base_address + + XDCFG_DMA_SRC_ADDR_OFFSET, (u32) dma_addr); + + xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_ADDR_OFFSET, + (u32)XDCFG_DMA_INVALID_ADDRESS); + /* Convert number of bytes to number of words. */ + if (count % 4) + transfer_length = (count / 4 + 1); + else + transfer_length = count / 4; + xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_SRC_LEN_OFFSET, + transfer_length); + xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_LEN_OFFSET, 0); + + timeout = jiffies + msecs_to_jiffies(1000); + + while (!drvdata->dma_done) { + if (time_after(jiffies, timeout)) { + status = -ETIMEDOUT; + goto error; + } + } + + if (drvdata->error_status) + status = drvdata->error_status; + + /* Disable the DMA and error interrupts */ + intr_reg = xdevcfg_readreg(drvdata->base_address + + XDCFG_INT_MASK_OFFSET); + xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET, + intr_reg | (XDCFG_IXR_DMA_DONE_MASK | + XDCFG_IXR_ERROR_FLAGS_MASK)); + + /* If we didn't write correctly, then bail out. */ + if (status) { + status = -EFAULT; + goto error; + } + + *ppos += user_count; + status = user_count; + +error: + dma_free_coherent(drvdata->dev, count, kbuf, dma_addr); +err_unlock: + mutex_unlock(&drvdata->sem); +err_clk: + clk_disable(drvdata->clk); + return status; +} + + +/** + * xdevcfg_read() - The is the driver read function. + * @file: Pointer to the file structure. + * @buf: Pointer to the bitstream location. + * @count: The number of bytes read. + * @ppos: Pointer to the offsetvalue + * returns: Success or error status. + */ +static ssize_t +xdevcfg_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) +{ + u32 *kbuf; + int status; + unsigned long timeout; + dma_addr_t dma_addr; + struct xdevcfg_drvdata *drvdata = file->private_data; + u32 intr_reg; + + status = clk_enable(drvdata->clk); + if (status) + return status; + + status = mutex_lock_interruptible(&drvdata->sem); + if (status) + goto err_clk; + + /* Get new data from the ICAP, and return was requested. */ + kbuf = dma_alloc_coherent(drvdata->dev, count, &dma_addr, GFP_KERNEL); + if (!kbuf) { + status = -ENOMEM; + goto err_unlock; + } + + drvdata->dma_done = 0; + drvdata->error_status = 0; + + /* Enable DMA and error interrupts */ + xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET, + XDCFG_IXR_ALL_MASK); + + xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET, + (u32) (~(XDCFG_IXR_DMA_DONE_MASK | + XDCFG_IXR_ERROR_FLAGS_MASK))); + /* Initiate DMA read command */ + xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_SRC_ADDR_OFFSET, + (u32)XDCFG_DMA_INVALID_ADDRESS); + xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_ADDR_OFFSET, + (u32)dma_addr); + xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_SRC_LEN_OFFSET, 0); + xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_LEN_OFFSET, + count / 4); + + timeout = jiffies + msecs_to_jiffies(1000); + + while (!drvdata->dma_done) { + if (time_after(jiffies, timeout)) { + status = -ETIMEDOUT; + goto error; + } + } + + if (drvdata->error_status) + status = drvdata->error_status; + + /* Disable and clear DMA and error interrupts */ + intr_reg = xdevcfg_readreg(drvdata->base_address + + XDCFG_INT_MASK_OFFSET); + xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET, + intr_reg | (XDCFG_IXR_DMA_DONE_MASK | + XDCFG_IXR_ERROR_FLAGS_MASK)); + + + /* If we didn't read correctly, then bail out. */ + if (status) { + status = -EFAULT; + goto error; + } + + /* If we fail to return the data to the user, then bail out. */ + if (copy_to_user(buf, kbuf, count)) { + status = -EFAULT; + goto error; + } + + status = count; +error: + dma_free_coherent(drvdata->dev, count, kbuf, dma_addr); +err_unlock: + mutex_unlock(&drvdata->sem); +err_clk: + clk_disable(drvdata->clk); + + return status; +} + +/** + * xdevcfg_open() - The is the driver open function. + * @inode: Pointer to the inode structure of this device. + * @file: Pointer to the file structure. + * returns: Success or error status. + */ +static int xdevcfg_open(struct inode *inode, struct file *file) +{ + struct xdevcfg_drvdata *drvdata; + int status; + + drvdata = container_of(inode->i_cdev, struct xdevcfg_drvdata, cdev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + status = mutex_lock_interruptible(&drvdata->sem); + if (status) + goto err_clk; + + if (drvdata->is_open) { + status = -EBUSY; + goto error; + } + + file->private_data = drvdata; + drvdata->is_open = 1; + drvdata->endian_swap = 0; + drvdata->residue_len= 0; + + /* + * If is_partial_bitstream is set, then PROG_B is not asserted + * (xdevcfg_reset_pl function) and also zynq_slcr_init_preload_fpga and + * zynq_slcr_init_postload_fpga functions are not invoked. + */ + if (!drvdata->is_partial_bitstream) + zynq_slcr_init_preload_fpga(); + + /* + * Only do the reset of the PL for Zynq as it causes problems on the + * EP107 and the issue is not understood, but not worth investigating + * as the emulation platform is very different than silicon and not a + * complete implementation. Also, do not reset if it is a partial + * bitstream. + */ + if ((!drvdata->ep107) && (!drvdata->is_partial_bitstream)) + xdevcfg_reset_pl(drvdata->base_address); + + xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET, + XDCFG_IXR_PCFG_DONE_MASK); + +error: + mutex_unlock(&drvdata->sem); +err_clk: + clk_disable(drvdata->clk); + return status; +} + +/** + * xdevcfg_release() - The is the driver release function. + * @inode: Pointer to the inode structure of this device. + * @file: Pointer to the file structure. + * returns: Success. + */ +static int xdevcfg_release(struct inode *inode, struct file *file) +{ + struct xdevcfg_drvdata *drvdata = file->private_data; + + if (!drvdata->is_partial_bitstream) + zynq_slcr_init_postload_fpga(); + + if (drvdata->residue_len) + printk("Did not transfer last %d bytes\n", + drvdata->residue_len); + + drvdata->is_open = 0; + + return 0; +} + +static const struct file_operations xdevcfg_fops = { + .owner = THIS_MODULE, + .write = xdevcfg_write, + .read = xdevcfg_read, + .open = xdevcfg_open, + .release = xdevcfg_release, +}; + +/* + * The following functions are the routines provided to the user to + * set/get the status bit value in the control/lock registers. + */ + +/** + * xdevcfg_set_dap_en() - This function sets the DAP bits in the + * control register with the given value. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * @size: The number of bytes used from the buffer + * returns: negative error if the string could not be converted + * or the size of the buffer. + */ +static ssize_t xdevcfg_set_dap_en(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + u32 ctrl_reg_status; + unsigned long flags; + unsigned long mask_bit; + int status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET); + spin_lock_irqsave(&drvdata->lock, flags); + + status = strict_strtoul(buf, 10, &mask_bit); + + if (status) + goto err_unlock; + + if (mask_bit > 7) { + status = -EINVAL; + goto err_unlock; + } + + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status | + (((u32)mask_bit) & XDCFG_CTRL_DAP_EN_MASK))); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + clk_disable(drvdata->clk); + + return size; + +err_unlock: + spin_unlock_irqrestore(&drvdata->lock, flags); + clk_disable(drvdata->clk); + + return status; +} + +/** + * xdevcfg_show_dap_en_status() - The function returns the DAP_EN bits status in + * the control register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: Size of the buffer. + */ +static ssize_t xdevcfg_show_dap_en_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 dap_en_status; + int status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + dap_en_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET) & XDCFG_CTRL_DAP_EN_MASK; + + clk_disable(drvdata->clk); + + status = sprintf(buf, "%d\n", dap_en_status); + + return status; +} + +static DEVICE_ATTR(enable_dap, 0644, xdevcfg_show_dap_en_status, + xdevcfg_set_dap_en); + +/** + * xdevcfg_set_dbgen() - This function sets the DBGEN bit in the + * control register with the given value. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * @size: The number of bytes used from the buffer + * returns: -EINVAL if invalid parameter is sent or size + */ +static ssize_t xdevcfg_set_dbgen(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + u32 ctrl_reg_status; + unsigned long flags; + unsigned long mask_bit; + int status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET); + + status = strict_strtoul(buf, 10, &mask_bit); + + if (status) + goto err_clk; + + if (mask_bit > 1) { + status = -EINVAL; + goto err_clk; + } + + spin_lock_irqsave(&drvdata->lock, flags); + + if (mask_bit) + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status | XDCFG_CTRL_DBGEN_MASK)); + else + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status & (~XDCFG_CTRL_DBGEN_MASK))); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + clk_disable(drvdata->clk); + + return size; + +err_clk: + clk_disable(drvdata->clk); + + return status; +} + +/** + * xdevcfg_show_dbgen_status() - The function returns the DBGEN bit status in + * the control register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: Size of the buffer. + */ +static ssize_t xdevcfg_show_dbgen_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 dbgen_status; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + dbgen_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET) & XDCFG_CTRL_DBGEN_MASK; + + clk_disable(drvdata->clk); + + status = sprintf(buf, "%d\n", (dbgen_status >> 3)); + + return status; +} + +static DEVICE_ATTR(enable_dbg_in, 0644, xdevcfg_show_dbgen_status, + xdevcfg_set_dbgen); + +/** + * xdevcfg_set_niden() - This function sets the NIDEN bit in the + * control register with the given value. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * @size: The number of bytes used from the buffer + * returns: -EINVAL if invalid parameter is sent or size + */ +static ssize_t xdevcfg_set_niden(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + u32 ctrl_reg_status; + unsigned long flags; + unsigned long mask_bit; + int status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET); + + status = strict_strtoul(buf, 10, &mask_bit); + + if (status) + goto err_clk; + + if (mask_bit > 1) { + status = -EINVAL; + goto err_clk; + } + + spin_lock_irqsave(&drvdata->lock, flags); + + if (mask_bit) + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status | XDCFG_CTRL_NIDEN_MASK)); + else + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status & (~XDCFG_CTRL_NIDEN_MASK))); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + clk_disable(drvdata->clk); + + return size; + +err_clk: + clk_disable(drvdata->clk); + + return status; +} + +/** + * xdevcfg_show_niden_status() - The function returns the NIDEN bit status in + * the control register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: Size of the buffer. + */ +static ssize_t xdevcfg_show_niden_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 niden_status; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + niden_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET) & XDCFG_CTRL_NIDEN_MASK; + + clk_disable(drvdata->clk); + + status = sprintf(buf, "%d\n", (niden_status >> 4)); + + return status; +} + +static DEVICE_ATTR(enable_dbg_nonin, 0644, xdevcfg_show_niden_status, + xdevcfg_set_niden); + +/** + * xdevcfg_set_spiden() - This function sets the SPIDEN bit in the + * control register with the given value. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * @size: The number of bytes used from the buffer + * returns: -EINVAL if invalid parameter is sent or size + */ +static ssize_t xdevcfg_set_spiden(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + u32 ctrl_reg_status; + unsigned long flags; + unsigned long mask_bit; + int status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET); + + status = strict_strtoul(buf, 10, &mask_bit); + + if (status) + goto err_clk; + + if (mask_bit > 1) { + status = -EINVAL; + goto err_clk; + } + + spin_lock_irqsave(&drvdata->lock, flags); + + if (mask_bit) + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status | XDCFG_CTRL_SPIDEN_MASK)); + else + + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status & (~XDCFG_CTRL_SPIDEN_MASK))); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + clk_disable(drvdata->clk); + + return size; + +err_clk: + clk_disable(drvdata->clk); + + return status; +} + +/** + * xdevcfg_show_spiden_status() - The function returns the SPIDEN bit status in + * the control register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: Size of the buffer. + */ +static ssize_t xdevcfg_show_spiden_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 spiden_status; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + spiden_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET) & XDCFG_CTRL_SPIDEN_MASK; + + clk_disable(drvdata->clk); + + status = sprintf(buf, "%d\n", (spiden_status >> 5)); + + return status; +} + +static DEVICE_ATTR(enable_sec_dbg_in, 0644, xdevcfg_show_spiden_status, + xdevcfg_set_spiden); + +/** + * xdevcfg_set_spniden() - This function sets the SPNIDEN bit in the + * control register with the given value. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * @size: The number of bytes used from the buffer + * returns: -EINVAL if invalid parameter is sent or the size of buffer + */ +static ssize_t xdevcfg_set_spniden(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + u32 ctrl_reg_status; + unsigned long flags; + unsigned long mask_bit; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET); + status = strict_strtoul(buf, 10, &mask_bit); + + if (status) + goto err_clk; + + if (mask_bit > 1) { + status = -EINVAL; + goto err_clk; + } + + spin_lock_irqsave(&drvdata->lock, flags); + + if (mask_bit) + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status | XDCFG_CTRL_SPNIDEN_MASK)); + else + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status & (~XDCFG_CTRL_SPNIDEN_MASK))); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + clk_disable(drvdata->clk); + + return size; + +err_clk: + clk_disable(drvdata->clk); + + return status; +} + +/** + * xdevcfg_show_spniden_status() - The function returns the SPNIDEN bit status + * in the control register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: Size of the buffer. + */ +static ssize_t xdevcfg_show_spniden_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 spniden_status; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + spniden_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET) & XDCFG_CTRL_SPNIDEN_MASK; + + clk_disable(drvdata->clk); + + status = sprintf(buf, "%d\n", (spniden_status >> 6)); + + return status; +} + +static DEVICE_ATTR(enable_sec_dbg_nonin, 0644, xdevcfg_show_spniden_status, + xdevcfg_set_spniden); + +/** + * xdevcfg_set_seu() - This function sets the SEU_EN bit in the + * control register with the given value + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * @size: The number of bytes used from the buffer + * returns: -EINVAL if invalid parameter is sent or size + */ +static ssize_t xdevcfg_set_seu(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + u32 ctrl_reg_status; + unsigned long flags; + unsigned long mask_bit; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET); + + status = strict_strtoul(buf, 10, &mask_bit); + + if (status) + goto err_clk; + + if (mask_bit > 1) { + status = -EINVAL; + goto err_clk; + } + + spin_lock_irqsave(&drvdata->lock, flags); + + if (mask_bit) + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status | XDCFG_CTRL_SEU_EN_MASK)); + else + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status & (~XDCFG_CTRL_SEU_EN_MASK))); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + clk_disable(drvdata->clk); + + return size; + +err_clk: + clk_disable(drvdata->clk); + + return status; +} + +/** + * xdevcfg_show_seu_status() - The function returns the SEU_EN bit status + * in the control register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: size of the buffer. + */ +static ssize_t xdevcfg_show_seu_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 seu_status; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + seu_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET) & XDCFG_CTRL_SEU_EN_MASK; + + clk_disable(drvdata->clk); + + status = sprintf(buf, "%d\n", (seu_status > 8)); + + return status; +} + +static DEVICE_ATTR(enable_seu, 0644, xdevcfg_show_seu_status, xdevcfg_set_seu); + +/** + * xdevcfg_set_aes() - This function sets the AES_EN bits in the + * control register with either all 1s or all 0s. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * @size: The number of bytes used from the buffer + * returns: -EINVAL if invalid parameter is sent or size + * + * The user must send only one bit in the buffer to notify whether he wants to + * either set or reset these bits. + */ +static ssize_t xdevcfg_set_aes(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + u32 ctrl_reg_status; + unsigned long flags; + unsigned long mask_bit; + int status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET); + + status = strict_strtoul(buf, 10, &mask_bit); + + if (status < 0) + goto err_clk; + + if (mask_bit > 1) { + status = -EINVAL; + goto err_clk; + } + + + spin_lock_irqsave(&drvdata->lock, flags); + + if (mask_bit) + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status | + XDCFG_CTRL_PCFG_AES_EN_MASK)); + else + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (ctrl_reg_status & + (~XDCFG_CTRL_PCFG_AES_EN_MASK))); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + clk_disable(drvdata->clk); + + return size; + +err_clk: + clk_disable(drvdata->clk); + + return status; +} + +/** + * xdevcfg_show_aes_status() - The function returns the AES_EN bit status + * in the control register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: size of the buffer. + */ +static ssize_t xdevcfg_show_aes_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 aes_status; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + aes_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_CTRL_OFFSET) & XDCFG_CTRL_PCFG_AES_EN_MASK; + + clk_disable(drvdata->clk); + + status = sprintf(buf, "%d\n", (aes_status >> 9)); + + return status; +} + +static DEVICE_ATTR(enable_aes, 0644, xdevcfg_show_aes_status, xdevcfg_set_aes); + +/** + * xdevcfg_set_aes_en_lock() - This function sets the LOCK_AES_EN bit in the + * lock register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * @size: The number of bytes used from the buffer + * returns: -EINVAL if invalid parameter is sent or size + */ +static ssize_t xdevcfg_set_aes_en_lock(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + u32 aes_en_lock_status; + unsigned long flags; + unsigned long mask_bit; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + aes_en_lock_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_LOCK_OFFSET); + + status = strict_strtoul(buf, 10, &mask_bit); + + if (status) + goto err_clk; + + if (mask_bit > 1) { + status = -EINVAL; + goto err_clk; + } + + spin_lock_irqsave(&drvdata->lock, flags); + + if (mask_bit) + xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, + (aes_en_lock_status | XDCFG_LOCK_AES_EN_MASK)); + else + xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, + (aes_en_lock_status & + (~XDCFG_LOCK_AES_EN_MASK))); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + clk_disable(drvdata->clk); + + return size; + +err_clk: + clk_disable(drvdata->clk); + + return status; +} + +/** + * xdevcfg_show_aes_en_lock_status() - The function returns the LOCK_AES_EN bit + * status in the lock register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: size of the buffer. + */ +static ssize_t xdevcfg_show_aes_en_lock_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 aes_en_lock_status; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + aes_en_lock_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_LOCK_OFFSET) & XDCFG_LOCK_AES_EN_MASK; + + clk_disable(drvdata->clk); + + status = sprintf(buf, "%d\n", (aes_en_lock_status >> 3)); + + return status; +} + +static DEVICE_ATTR(aes_en_lock, 0644, xdevcfg_show_aes_en_lock_status, + xdevcfg_set_aes_en_lock); + +/** + * xdevcfg_set_seu_lock() - This function sets the LOCK_SEU bit in the + * lock register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * @size: The number of bytes used from the buffer + * returns: -EINVAL if invalid parameter is sent or size + */ +static ssize_t xdevcfg_set_seu_lock(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + u32 seu_lock_status; + unsigned long flags; + unsigned long mask_bit; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + seu_lock_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_LOCK_OFFSET); + + status = strict_strtoul(buf, 10, &mask_bit); + + if (status) + goto err_clk; + + if (mask_bit > 1) { + status = -EINVAL; + goto err_clk; + } + + spin_lock_irqsave(&drvdata->lock, flags); + + if (mask_bit) + xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, + (seu_lock_status | XDCFG_LOCK_SEU_MASK)); + else + xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, + (seu_lock_status & (~XDCFG_LOCK_SEU_MASK))); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + clk_disable(drvdata->clk); + + return size; + +err_clk: + clk_disable(drvdata->clk); + + return status; +} + +/** + * xdevcfg_show_seu_lock_status() - The function returns the LOCK_SEU bit + * status in the lock register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: size of the buffer. + */ +static ssize_t xdevcfg_show_seu_lock_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 seu_lock_status; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + seu_lock_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_LOCK_OFFSET) & XDCFG_LOCK_SEU_MASK; + + clk_disable(drvdata->clk); + + status = sprintf(buf, "%d\n", (seu_lock_status >> 2)); + + return status; +} + +static DEVICE_ATTR(seu_lock, 0644, xdevcfg_show_seu_lock_status, + xdevcfg_set_seu_lock); + +/** + * xdevcfg_set_dbg_lock() - This function sets the LOCK_DBG bit in the + * lock register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * @size: The number of bytes used from the buffer + * returns: -EINVAL if invalid parameter is sent or size + */ +static ssize_t xdevcfg_set_dbg_lock(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + u32 lock_reg_status; + unsigned long flags; + unsigned long mask_bit; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + lock_reg_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_LOCK_OFFSET); + status = strict_strtoul(buf, 10, &mask_bit); + + if (status) + goto err_clk; + + if (mask_bit > 1) { + status = -EINVAL; + goto err_clk; + } + + spin_lock_irqsave(&drvdata->lock, flags); + + if (mask_bit) + xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, + (lock_reg_status | XDCFG_LOCK_DBG_MASK)); + else + xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, + (lock_reg_status & (~XDCFG_LOCK_DBG_MASK))); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + clk_disable(drvdata->clk); + + return size; + +err_clk: + clk_disable(drvdata->clk); + + return status; +} + +/** + * xdevcfg_show_dbg_lock_status() - The function returns the LOCK_DBG bit + * status in the lock register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: size of the buffer. + */ +static ssize_t xdevcfg_show_dbg_lock_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 dbg_lock_status; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + dbg_lock_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_LOCK_OFFSET) & XDCFG_LOCK_DBG_MASK; + + clk_disable(drvdata->clk); + + status = sprintf(buf, "%d\n", dbg_lock_status); + + return status; +} + +static DEVICE_ATTR(dbg_lock, 0644, xdevcfg_show_dbg_lock_status, + xdevcfg_set_dbg_lock); + +/** + * xdevcfg_show_prog_done_status() - The function returns the PROG_DONE bit + * status in the interrupt status register. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: size of the buffer. + */ +static ssize_t xdevcfg_show_prog_done_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 prog_done_status; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = clk_enable(drvdata->clk); + if (status) + return status; + + prog_done_status = xdevcfg_readreg(drvdata->base_address + + XDCFG_INT_STS_OFFSET) & XDCFG_IXR_PCFG_DONE_MASK; + + clk_disable(drvdata->clk); + + status = sprintf(buf, "%d\n", (prog_done_status >> 2)); + + return status; +} + +static DEVICE_ATTR(prog_done, 0644, xdevcfg_show_prog_done_status, + NULL); + +/** + * xdevcfg_set_is_partial_bitstream() - This function sets the + * is_partial_bitstream variable. If is_partial_bitstream is set, + * then PROG_B is not asserted (xdevcfg_reset_pl) and also + * zynq_slcr_init_preload_fpga and zynq_slcr_init_postload_fpga functions + * are not invoked. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * @size: The number of bytes used from the buffer + * returns: -EINVAL if invalid parameter is sent or size + */ +static ssize_t xdevcfg_set_is_partial_bitstream(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + unsigned long mask_bit; + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = strict_strtoul(buf, 10, &mask_bit); + + if (status) + return status; + + if (mask_bit > 1) + return -EINVAL; + + if (mask_bit) + drvdata->is_partial_bitstream = 1; + else + drvdata->is_partial_bitstream = 0; + + return size; +} + +/** + * xdevcfg_show_is_partial_bitstream_status() - The function returns the + * value of is_partial_bitstream variable. + * @dev: Pointer to the device structure. + * @attr: Pointer to the device attribute structure. + * @buf: Pointer to the buffer location for the configuration + * data. + * returns: size of the buffer. + */ +static ssize_t xdevcfg_show_is_partial_bitstream_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t status; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + status = sprintf(buf, "%d\n", drvdata->is_partial_bitstream); + + return status; +} + +static DEVICE_ATTR(is_partial_bitstream, 0644, + xdevcfg_show_is_partial_bitstream_status, + xdevcfg_set_is_partial_bitstream); + +static const struct attribute *xdevcfg_attrs[] = { + &dev_attr_prog_done.attr, /* PCFG_DONE bit in Intr Status register */ + &dev_attr_dbg_lock.attr, /* Debug lock bit in Lock register */ + &dev_attr_seu_lock.attr, /* SEU lock bit in Lock register */ + &dev_attr_aes_en_lock.attr, /* AES EN lock bit in Lock register */ + &dev_attr_enable_aes.attr, /* AES EN bit in Control register */ + &dev_attr_enable_seu.attr, /* SEU EN bit in Control register */ + &dev_attr_enable_sec_dbg_nonin.attr, /*SPNIDEN bit in Control register*/ + &dev_attr_enable_sec_dbg_in.attr, /*SPIDEN bit in Control register */ + &dev_attr_enable_dbg_nonin.attr, /* NIDEN bit in Control register */ + &dev_attr_enable_dbg_in.attr, /* DBGEN bit in Control register */ + &dev_attr_enable_dap.attr, /* DAP_EN bits in Control register */ + &dev_attr_is_partial_bitstream.attr, /* Flag for partial bitstream */ + NULL, +}; + + +static const struct attribute_group xdevcfg_attr_group = { + .attrs = (struct attribute **) xdevcfg_attrs, +}; + +static ssize_t fclk_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fclk_data *pdata = dev_get_drvdata(dev); + + return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled); +} + +static ssize_t fclk_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + unsigned long enable; + int ret; + struct fclk_data *pdata = dev_get_drvdata(dev); + + ret = kstrtoul(buf, 0, &enable); + if (ret) + return -EINVAL; + + enable = !!enable; + if (enable == pdata->enabled) + return count; + + if (enable) + ret = clk_enable(pdata->clk); + else + clk_disable(pdata->clk); + + if (ret) + return ret; + + pdata->enabled = enable; + return count; +} + +static DEVICE_ATTR(enable, 0644, fclk_enable_show, fclk_enable_store); + +static ssize_t fclk_set_rate_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fclk_data *pdata = dev_get_drvdata(dev); + + return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->clk)); +} + +static ssize_t fclk_set_rate_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int ret = 0; + unsigned long rate; + struct fclk_data *pdata = dev_get_drvdata(dev); + + ret = kstrtoul(buf, 0, &rate); + if (ret) + return -EINVAL; + + rate = clk_round_rate(pdata->clk, rate); + ret = clk_set_rate(pdata->clk, rate); + + return ret ? ret : count; +} + +static DEVICE_ATTR(set_rate, 0644, fclk_set_rate_show, fclk_set_rate_store); + +static ssize_t fclk_round_rate_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fclk_data *pdata = dev_get_drvdata(dev); + + return scnprintf(buf, PAGE_SIZE, "%lu => %lu\n", pdata->rate_rnd, + clk_round_rate(pdata->clk, pdata->rate_rnd)); +} + +static ssize_t fclk_round_rate_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int ret = 0; + unsigned long rate; + struct fclk_data *pdata = dev_get_drvdata(dev); + + ret = kstrtoul(buf, 0, &rate); + if (ret) + return -EINVAL; + + pdata->rate_rnd = rate; + + return count; +} + +static DEVICE_ATTR(round_rate, 0644, fclk_round_rate_show, + fclk_round_rate_store); + +static const struct attribute *fclk_ctrl_attrs[] = { + &dev_attr_enable.attr, + &dev_attr_set_rate.attr, + &dev_attr_round_rate.attr, + NULL, +}; + +static const struct attribute_group fclk_ctrl_attr_grp = { + .attrs = (struct attribute **)fclk_ctrl_attrs, +}; + +static ssize_t xdevcfg_fclk_export_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + int i, ret; + struct device *subdev; + struct fclk_data *fdata; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + for (i = 0; i < NUMFCLKS; i++) { + if (!strncmp(buf, fclk_name[i], strlen(fclk_name[i]))) + break; + } + + if (i < NUMFCLKS && !drvdata->fclk_exported[i]) { + drvdata->fclk_exported[i] = 1; + subdev = device_create(drvdata->fclk_class, dev, MKDEV(0, 0), + NULL, fclk_name[i]); + if (IS_ERR(subdev)) + return PTR_ERR(subdev); + ret = clk_prepare(drvdata->fclk[i]); + if (ret) + return ret; + fdata = kzalloc(sizeof(*fdata), GFP_KERNEL); + if (!fdata) { + ret = -ENOMEM; + goto err_unprepare; + } + fdata->clk = drvdata->fclk[i]; + dev_set_drvdata(subdev, fdata); + ret = sysfs_create_group(&subdev->kobj, &fclk_ctrl_attr_grp); + if (ret) + goto err_free; + } else { + return -EINVAL; + } + + return size; + +err_free: + kfree(fdata); +err_unprepare: + clk_unprepare(drvdata->fclk[i]); + + return ret; +} + +static ssize_t xdevcfg_fclk_export_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int i; + ssize_t count = 0; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + for (i = 0; i < NUMFCLKS; i++) { + if (!drvdata->fclk_exported[i]) + count += scnprintf(buf + count, PAGE_SIZE - count, + "%s\n", fclk_name[i]); + } + return count; +} + +static DEVICE_ATTR(fclk_export, 0644, xdevcfg_fclk_export_show, + xdevcfg_fclk_export_store); + +static int match_fclk(struct device *dev, const void *data) +{ + struct fclk_data *fdata = dev_get_drvdata(dev); + + return fdata->clk == data; +} + +static ssize_t xdevcfg_fclk_unexport_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + int i; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + for (i = 0; i < NUMFCLKS; i++) { + if (!strncmp(buf, fclk_name[i], strlen(fclk_name[i]))) + break; + } + + if (i < NUMFCLKS && drvdata->fclk_exported[i]) { + struct fclk_data *fdata; + struct device *subdev; + + drvdata->fclk_exported[i] = 0; + subdev = class_find_device(drvdata->fclk_class, NULL, + drvdata->fclk[i], match_fclk); + fdata = dev_get_drvdata(subdev); + if (fdata->enabled) + clk_disable(fdata->clk); + clk_unprepare(fdata->clk); + kfree(fdata); + device_unregister(subdev); + put_device(subdev); + } else { + return -EINVAL; + } + + return size; +} + +static ssize_t xdevcfg_fclk_unexport_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int i; + ssize_t count = 0; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + for (i = 0; i < NUMFCLKS; i++) { + if (drvdata->fclk_exported[i]) + count += scnprintf(buf + count, PAGE_SIZE - count, + "%s\n", fclk_name[i]); + } + return count; +} + +static DEVICE_ATTR(fclk_unexport, 0644, xdevcfg_fclk_unexport_show, + xdevcfg_fclk_unexport_store); + +static const struct attribute *fclk_exp_attrs[] = { + &dev_attr_fclk_export.attr, + &dev_attr_fclk_unexport.attr, + NULL, +}; + +static const struct attribute_group fclk_exp_attr_grp = { + .attrs = (struct attribute **)fclk_exp_attrs, +}; + +static void xdevcfg_fclk_init(struct device *dev) +{ + int i; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + for (i = 0; i < NUMFCLKS; i++) { + drvdata->fclk[i] = clk_get(dev, fclk_name[i]); + if (IS_ERR(drvdata->fclk[i])) { + dev_warn(dev, "fclk not found\n"); + return; + } + } + + drvdata->fclk_class = class_create(THIS_MODULE, "fclk"); + if (IS_ERR(drvdata->fclk_class)) { + dev_warn(dev, "failed to create fclk class\n"); + return; + } + sysfs_create_group(&dev->kobj, &fclk_exp_attr_grp); + + return; +} + +static void xdevcfg_fclk_remove(struct device *dev) +{ + int i; + struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); + + for (i = 0; i < NUMFCLKS; i++) { + if (drvdata->fclk_exported[i]) { + struct fclk_data *fdata; + struct device *subdev; + + drvdata->fclk_exported[i] = 0; + subdev = class_find_device(drvdata->fclk_class, NULL, + drvdata->fclk[i], match_fclk); + fdata = dev_get_drvdata(subdev); + if (fdata->enabled) + clk_disable(fdata->clk); + clk_unprepare(fdata->clk); + kfree(fdata); + device_unregister(subdev); + put_device(subdev); + + } + } + + class_destroy(drvdata->fclk_class); + sysfs_remove_group(&dev->kobj, &fclk_exp_attr_grp); + + return; +} + +/** + * xdevcfg_drv_probe - Probe call for the device. + * + * @pdev: handle to the platform device structure. + * Returns 0 on success, negative error otherwise. + * + * It does all the memory allocation and registration for the device. + */ +static int xdevcfg_drv_probe(struct platform_device *pdev) +{ + struct resource *res; + struct xdevcfg_drvdata *drvdata; + dev_t devt; + int retval; + u32 ctrlreg; + struct device_node *np; + const void *prop; + int size; + struct device *dev; + + drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + drvdata->base_address = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(drvdata->base_address)) + return PTR_ERR(drvdata->base_address); + + drvdata->irq = platform_get_irq(pdev, 0); + retval = devm_request_irq(&pdev->dev, drvdata->irq, &xdevcfg_irq, + 0, dev_name(&pdev->dev), drvdata); + if (retval) { + dev_err(&pdev->dev, "No IRQ available"); + return retval; + } + + platform_set_drvdata(pdev, drvdata); + spin_lock_init(&drvdata->lock); + mutex_init(&drvdata->sem); + drvdata->is_open = 0; + drvdata->is_partial_bitstream = 0; + drvdata->dma_done = 0; + drvdata->error_status = 0; + dev_info(&pdev->dev, "ioremap %pa to %p\n", + &res->start, drvdata->base_address); + + drvdata->clk = devm_clk_get(&pdev->dev, "ref_clk"); + if (IS_ERR(drvdata->clk)) { + dev_err(&pdev->dev, "input clock not found\n"); + return PTR_ERR(drvdata->clk); + } + + retval = clk_prepare_enable(drvdata->clk); + if (retval) { + dev_err(&pdev->dev, "unable to enable clock\n"); + return retval; + } + + /* + * Figure out from the device tree if this is running on the EP107 + * emulation platform as it doesn't match the silicon exactly and the + * driver needs to work accordingly. + */ + np = of_get_next_parent(pdev->dev.of_node); + np = of_get_next_parent(np); + prop = of_get_property(np, "compatible", &size); + + if (prop != NULL) { + if ((strcmp((const char *)prop, "xlnx,zynq-ep107")) == 0) + drvdata->ep107 = 1; + else + drvdata->ep107 = 0; + } + + /* Unlock the device */ + xdevcfg_writereg(drvdata->base_address + XDCFG_UNLOCK_OFFSET, + 0x757BDF0D); + + /* + * Set the configuration register with the following options + * - Reset FPGA + * - Enable PCAP interface for Partial reconfiguration + * - Enable the PCAP interface + * - Set the throughput rate for maximum speed + * - Se the CPU in user mode + */ + ctrlreg = xdevcfg_readreg(drvdata->base_address + XDCFG_CTRL_OFFSET); + xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, + (XDCFG_CTRL_PCFG_PROG_B_MASK | + XDCFG_CTRL_PCAP_PR_MASK | + XDCFG_CTRL_PCAP_MODE_MASK | + ctrlreg)); + + /* Ensure internal PCAP loopback is disabled */ + ctrlreg = xdevcfg_readreg(drvdata->base_address + XDCFG_MCTRL_OFFSET); + xdevcfg_writereg(drvdata->base_address + XDCFG_MCTRL_OFFSET, + (~XDCFG_MCTRL_PCAP_LPBK_MASK & + ctrlreg)); + + + retval = alloc_chrdev_region(&devt, 0, XDEVCFG_DEVICES, DRIVER_NAME); + if (retval < 0) + goto failed5; + + drvdata->devt = devt; + + cdev_init(&drvdata->cdev, &xdevcfg_fops); + drvdata->cdev.owner = THIS_MODULE; + retval = cdev_add(&drvdata->cdev, devt, 1); + if (retval) { + dev_err(&pdev->dev, "cdev_add() failed\n"); + goto failed6; + } + + drvdata->class = class_create(THIS_MODULE, DRIVER_NAME); + if (IS_ERR(drvdata->class)) { + dev_err(&pdev->dev, "failed to create class\n"); + goto failed6; + } + + dev = device_create(drvdata->class, &pdev->dev, devt, drvdata, + DRIVER_NAME); + if (IS_ERR(dev)) { + dev_err(&pdev->dev, "unable to create device\n"); + goto failed7; + } + + /* create sysfs files for the device */ + retval = sysfs_create_group(&(pdev->dev.kobj), &xdevcfg_attr_group); + if (retval) { + dev_err(&pdev->dev, "Failed to create sysfs attr group\n"); + cdev_del(&drvdata->cdev); + goto failed8; + } + + xdevcfg_fclk_init(&pdev->dev); + + clk_disable(drvdata->clk); + + return 0; /* Success */ + +failed8: + device_destroy(drvdata->class, drvdata->devt); +failed7: + class_destroy(drvdata->class); +failed6: + /* Unregister char driver */ + unregister_chrdev_region(devt, XDEVCFG_DEVICES); +failed5: + clk_disable_unprepare(drvdata->clk); + + return retval; +} + +/** + * xdevcfg_drv_remove - Remove call for the device. + * + * @pdev: handle to the platform device structure. + * Returns 0 or error status. + * + * Unregister the device after releasing the resources. + */ +static int xdevcfg_drv_remove(struct platform_device *pdev) +{ + struct xdevcfg_drvdata *drvdata; + + drvdata = platform_get_drvdata(pdev); + + if (!drvdata) + return -ENODEV; + + unregister_chrdev_region(drvdata->devt, XDEVCFG_DEVICES); + + sysfs_remove_group(&pdev->dev.kobj, &xdevcfg_attr_group); + + xdevcfg_fclk_remove(&pdev->dev); + device_destroy(drvdata->class, drvdata->devt); + class_destroy(drvdata->class); + cdev_del(&drvdata->cdev); + clk_unprepare(drvdata->clk); + + return 0; /* Success */ +} + +static struct of_device_id xdevcfg_of_match[] = { + { .compatible = "xlnx,ps7-dev-cfg-1.00.a", }, + { /* end of table */} +}; +MODULE_DEVICE_TABLE(of, xdevcfg_of_match); + +/* Driver Structure */ +static struct platform_driver xdevcfg_platform_driver = { + .probe = xdevcfg_drv_probe, + .remove = xdevcfg_drv_remove, + .driver = { + .owner = THIS_MODULE, + .name = DRIVER_NAME, + .of_match_table = xdevcfg_of_match, + }, +}; + +module_platform_driver(xdevcfg_platform_driver); + +MODULE_AUTHOR("Xilinx, Inc"); +MODULE_DESCRIPTION("Xilinx Device Config Driver"); +MODULE_LICENSE("GPL"); Index: linux-3.12.24-rt38-xilinx/drivers/char/xilinx_hwicap/xilinx_hwicap.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/char/xilinx_hwicap/xilinx_hwicap.c 2014-07-20 22:05:50.187067430 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/char/xilinx_hwicap/xilinx_hwicap.c 2014-07-20 22:06:35.412321289 +0200 @@ -731,7 +731,6 @@ iounmap(drvdata->base_address); release_mem_region(drvdata->mem_start, drvdata->mem_size); kfree(drvdata); - dev_set_drvdata(dev, NULL); mutex_lock(&icap_sem); probed_devices[MINOR(dev->devt)-XHWICAP_MINOR] = 0; Index: linux-3.12.24-rt38-xilinx/drivers/clk/clk.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/clk/clk.c 2014-07-20 22:05:50.220066885 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/clk/clk.c 2014-07-20 22:06:35.433320943 +0200 @@ -964,8 +964,9 @@ * @rate: the rate which is to be rounded * * Takes in a rate as input and rounds it to a rate that the clk can actually - * use which is then returned. If clk doesn't support round_rate operation - * then the parent rate is returned. + * use and does not exceed the requested frequency, which is then returned. + * If clk doesn't support round_rate operation then the parent rate + * is returned. */ long clk_round_rate(struct clk *clk, unsigned long rate) { @@ -980,6 +981,27 @@ EXPORT_SYMBOL_GPL(clk_round_rate); /** + * clk_round_rate_nearest - round the given rate for a clk + * @clk: the clk for which we are rounding a rate + * @rate: the rate which is to be rounded + * + * Takes in a rate as input and rounds it to the closest rate that the clk + * can actually use which is then returned. If clk doesn't support + * round_rate operation then the parent rate is returned. + */ +long clk_round_rate_nearest(struct clk *clk, unsigned long rate) +{ + long lower_limit = clk_round_rate(clk, rate); + long upper_limit = clk_round_rate(clk, rate + (rate - lower_limit)); + + if (rate - lower_limit < upper_limit - rate) + return lower_limit; + else + return upper_limit; +} +EXPORT_SYMBOL_GPL(clk_round_rate_nearest); + +/** * __clk_notify - call clk notifier chain * @clk: struct clk * that is changing rate * @msg: clk notifier type (see include/linux/clk.h) Index: linux-3.12.24-rt38-xilinx/drivers/clk/clk-si570.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/clk/clk-si570.c 2014-07-20 22:06:35.446320728 +0200 @@ -0,0 +1,531 @@ +/* + * Driver for Silicon Labs Si570/Si571 Programmable XO/VCXO + * + * Copyright (C) 2010, 2011 Ericsson AB. + * Copyright (C) 2011 Guenter Roeck. + * Copyright (C) 2011 - 2013 Xilinx Inc. + * + * Author: Guenter Roeck + * Sören Brinkmann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +/* Si570 registers */ +#define SI570_REG_HS_N1 7 +#define SI570_REG_N1_RFREQ0 8 +#define SI570_REG_RFREQ1 9 +#define SI570_REG_RFREQ2 10 +#define SI570_REG_RFREQ3 11 +#define SI570_REG_RFREQ4 12 +#define SI570_REG_CONTROL 135 +#define SI570_REG_FREEZE_DCO 137 +#define SI570_DIV_OFFSET_7PPM 6 + +#define HS_DIV_SHIFT 5 +#define HS_DIV_MASK 0xe0 +#define HS_DIV_OFFSET 4 +#define N1_6_2_MASK 0x1f +#define N1_1_0_MASK 0xc0 +#define RFREQ_37_32_MASK 0x3f + +#define SI570_MIN_FREQ 10000000L +#define SI570_MAX_FREQ 1417500000L +#define SI598_MAX_FREQ 525000000L + +#define FDCO_MIN 4850000000LL +#define FDCO_MAX 5670000000LL + +#define SI570_CNTRL_RECALL (1 << 0) +#define SI570_CNTRL_FREEZE_M (1 << 5) +#define SI570_CNTRL_NEWFREQ (1 << 6) + +#define SI570_FREEZE_DCO (1 << 4) + +/** + * struct clk_si570: + * @hw: Clock hw struct + * @regmap: Device's regmap + * @div_offset: Rgister offset for dividers + * @max_freq: Maximum frequency for this device + * @fxtal: Factory xtal frequency + * @n1: Clock divider N1 + * @hs_div: Clock divider HSDIV + * @rfreq: Clock multiplier RFREQ + * @frequency: Current output frequency + * @i2c_client: I2C client pointer + */ +struct clk_si570 { + struct clk_hw hw; + struct regmap *regmap; + unsigned int div_offset; + u64 max_freq; + u64 fxtal; + unsigned int n1; + unsigned int hs_div; + u64 rfreq; + u64 frequency; + struct i2c_client *i2c_client; +}; +#define to_clk_si570(_hw) container_of(_hw, struct clk_si570, hw) + +enum clk_si570_variant { + si57x, + si59x +}; + +/** + * si570_get_divs() - Read clock dividers from HW + * @data: Pointer to struct clk_si570 + * @rfreq: Fractional multiplier (output) + * @n1: Divider N1 (output) + * @hs_div: Divider HSDIV (output) + * Returns 0 on success, negative errno otherwise. + * + * Retrieve clock dividers and multipliers from the HW. + */ +static int si570_get_divs(struct clk_si570 *data, u64 *rfreq, + unsigned int *n1, unsigned int *hs_div) +{ + int err; + u8 reg[6]; + u64 tmp; + + err = regmap_bulk_read(data->regmap, SI570_REG_HS_N1 + data->div_offset, + reg, ARRAY_SIZE(reg)); + if (err) + return err; + + *hs_div = ((reg[0] & HS_DIV_MASK) >> HS_DIV_SHIFT) + HS_DIV_OFFSET; + *n1 = ((reg[0] & N1_6_2_MASK) << 2) + ((reg[1] & N1_1_0_MASK) >> 6) + 1; + /* Handle invalid cases */ + if (*n1 > 1) + *n1 &= ~1; + + tmp = reg[1] & RFREQ_37_32_MASK; + tmp = (tmp << 8) + reg[2]; + tmp = (tmp << 8) + reg[3]; + tmp = (tmp << 8) + reg[4]; + tmp = (tmp << 8) + reg[5]; + *rfreq = tmp; + + return 0; +} + +/** + * si570_get_defaults() - Get default values + * @data: Driver data structure + * @fout: Factory frequency output + * Returns 0 on success, negative errno otherwise. + */ +static int si570_get_defaults(struct clk_si570 *data, u64 fout) +{ + int err; + u64 fdco; + + regmap_write(data->regmap, SI570_REG_CONTROL, SI570_CNTRL_RECALL); + + err = si570_get_divs(data, &data->rfreq, &data->n1, &data->hs_div); + if (err) + return err; + + /* + * Accept optional precision loss to avoid arithmetic overflows. + * Acceptable per Silicon Labs Application Note AN334. + */ + fdco = fout * data->n1 * data->hs_div; + if (fdco >= (1LL << 36)) + data->fxtal = div64_u64(fdco << 24, data->rfreq >> 4); + else + data->fxtal = div64_u64(fdco << 28, data->rfreq); + + data->frequency = fout; + + return 0; +} + +/** + * si570_update_rfreq() - Update clock multiplier + * @data: Driver data structure + * Passes on regmap_bulk_write() return value. + */ +static int si570_update_rfreq(struct clk_si570 *data) +{ + u8 reg[5]; + + reg[0] = ((data->n1 - 1) << 6) | + ((data->rfreq >> 32) & RFREQ_37_32_MASK); + reg[1] = (data->rfreq >> 24) & 0xff; + reg[2] = (data->rfreq >> 16) & 0xff; + reg[3] = (data->rfreq >> 8) & 0xff; + reg[4] = data->rfreq & 0xff; + + return regmap_bulk_write(data->regmap, SI570_REG_N1_RFREQ0 + + data->div_offset, reg, ARRAY_SIZE(reg)); +} + +/** + * si570_calc_divs() - Caluclate clock dividers + * @frequency: Target frequency + * @data: Driver data structure + * @out_rfreq: RFREG fractional multiplier (output) + * @out_n1: Clock divider N1 (output) + * @out_hs_div: Clock divider HSDIV (output) + * Returns 0 on success, negative errno otherwise. + * + * Calculate the clock dividers (@out_hs_div, @out_n1) and clock multiplier + * (@out_rfreq) for a given target @frequency. + */ +static int si570_calc_divs(unsigned long frequency, struct clk_si570 *data, + u64 *out_rfreq, unsigned int *out_n1, unsigned int *out_hs_div) +{ + int i; + unsigned int n1, hs_div; + u64 fdco, best_fdco = ULLONG_MAX; + static const uint8_t si570_hs_div_values[] = { 11, 9, 7, 6, 5, 4 }; + + for (i = 0; i < ARRAY_SIZE(si570_hs_div_values); i++) { + hs_div = si570_hs_div_values[i]; + /* Calculate lowest possible value for n1 */ + n1 = div_u64(div_u64(FDCO_MIN, hs_div), frequency); + if (!n1 || (n1 & 1)) + n1++; + while (n1 <= 128) { + fdco = (u64)frequency * (u64)hs_div * (u64)n1; + if (fdco > FDCO_MAX) + break; + if (fdco >= FDCO_MIN && fdco < best_fdco) { + *out_n1 = n1; + *out_hs_div = hs_div; + *out_rfreq = div64_u64(fdco << 28, data->fxtal); + best_fdco = fdco; + } + n1 += (n1 == 1 ? 1 : 2); + } + } + + if (best_fdco == ULLONG_MAX) + return -EINVAL; + + return 0; +} + +static unsigned long si570_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + int err; + u64 rfreq, rate; + unsigned int n1, hs_div; + struct clk_si570 *data = to_clk_si570(hw); + + err = si570_get_divs(data, &rfreq, &n1, &hs_div); + if (err) { + dev_err(&data->i2c_client->dev, "unable to recalc rate\n"); + return data->frequency; + } + + rfreq = div_u64(rfreq, hs_div * n1); + rate = (data->fxtal * rfreq) >> 28; + + return rate; +} + +static long si570_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + int err; + u64 rfreq; + unsigned int n1, hs_div; + struct clk_si570 *data = to_clk_si570(hw); + + if (!rate) + return 0; + + if (div64_u64(abs(rate - data->frequency) * 10000LL, + data->frequency) < 35) { + rfreq = div64_u64((data->rfreq * rate) + + div64_u64(data->frequency, 2), data->frequency); + n1 = data->n1; + hs_div = data->hs_div; + + } else { + err = si570_calc_divs(rate, data, &rfreq, &n1, &hs_div); + if (err) { + dev_err(&data->i2c_client->dev, + "unable to round rate\n"); + return 0; + } + } + + return rate; +} + +/** + * si570_set_frequency() - Adjust output frequency + * @data: Driver data structure + * @frequency: Target frequency + * Returns 0 on success. + * + * Update output frequency for big frequency changes (> 3,500 ppm). + */ +static int si570_set_frequency(struct clk_si570 *data, unsigned long frequency) +{ + int err; + + err = si570_calc_divs(frequency, data, &data->rfreq, &data->n1, + &data->hs_div); + if (err) + return err; + + /* + * The DCO reg should be accessed with a read-modify-write operation + * per AN334 + */ + regmap_write(data->regmap, SI570_REG_FREEZE_DCO, SI570_FREEZE_DCO); + regmap_write(data->regmap, SI570_REG_HS_N1 + data->div_offset, + ((data->hs_div - HS_DIV_OFFSET) << HS_DIV_SHIFT) | + (((data->n1 - 1) >> 2) & N1_6_2_MASK)); + si570_update_rfreq(data); + regmap_write(data->regmap, SI570_REG_FREEZE_DCO, 0); + regmap_write(data->regmap, SI570_REG_CONTROL, SI570_CNTRL_NEWFREQ); + + /* Applying a new frequency can take up to 10ms */ + usleep_range(10000, 12000); + + return 0; +} + +/** + * si570_set_frequency_small() - Adjust output frequency + * @data: Driver data structure + * @frequency: Target frequency + * Returns 0 on success. + * + * Update output frequency for small frequency changes (< 3,500 ppm). + */ +static int si570_set_frequency_small(struct clk_si570 *data, + unsigned long frequency) +{ + /* + * This is a re-implementation of DIV_ROUND_CLOSEST + * using the div64_u64 function lieu of letting the compiler + * insert EABI calls + */ + data->rfreq = div64_u64((data->rfreq * frequency) + + div_u64(data->frequency, 2), data->frequency); + regmap_write(data->regmap, SI570_REG_CONTROL, SI570_CNTRL_FREEZE_M); + si570_update_rfreq(data); + regmap_write(data->regmap, SI570_REG_CONTROL, 0); + + /* Applying a new frequency (small change) can take up to 100us */ + usleep_range(100, 200); + + return 0; +} + +static int si570_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_si570 *data = to_clk_si570(hw); + struct i2c_client *client = data->i2c_client; + int err; + + if (rate < SI570_MIN_FREQ || rate > data->max_freq) { + dev_err(&client->dev, + "requested frequency %lu Hz is out of range\n", rate); + return -EINVAL; + } + + if (div64_u64(abs(rate - data->frequency) * 10000LL, + data->frequency) < 35) + err = si570_set_frequency_small(data, rate); + else + err = si570_set_frequency(data, rate); + + if (err) + return err; + + data->frequency = rate; + + return 0; +} + +static const struct clk_ops si570_clk_ops = { + .recalc_rate = si570_recalc_rate, + .round_rate = si570_round_rate, + .set_rate = si570_set_rate, +}; + +static bool si570_regmap_is_volatile(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SI570_REG_CONTROL: + return true; + default: + return false; + } +} + +static bool si570_regmap_is_writeable(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SI570_REG_HS_N1 ... (SI570_REG_RFREQ4 + SI570_DIV_OFFSET_7PPM): + case SI570_REG_CONTROL: + case SI570_REG_FREEZE_DCO: + return true; + default: + return false; + } +} + +static struct regmap_config si570_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_RBTREE, + .max_register = 137, + .writeable_reg = si570_regmap_is_writeable, + .volatile_reg = si570_regmap_is_volatile, +}; + +static int si570_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct clk_si570 *data; + struct clk_init_data init; + struct clk *clk; + u32 initial_fout, factory_fout, stability; + int err; + enum clk_si570_variant variant = id->driver_data; + + data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + init.ops = &si570_clk_ops; + init.flags = CLK_IS_ROOT; + init.num_parents = 0; + data->hw.init = &init; + data->i2c_client = client; + + if (variant == si57x) { + err = of_property_read_u32(client->dev.of_node, + "temperature-stability", &stability); + if (err) { + dev_err(&client->dev, + "'temperature-stability' property missing\n"); + return err; + } + /* adjust register offsets for 7ppm devices */ + if (stability == 7) + data->div_offset = SI570_DIV_OFFSET_7PPM; + + data->max_freq = SI570_MAX_FREQ; + } else { + data->max_freq = SI598_MAX_FREQ; + } + + if (of_property_read_string(client->dev.of_node, "clock-output-names", + &init.name)) + init.name = client->dev.of_node->name; + + err = of_property_read_u32(client->dev.of_node, "factory-fout", + &factory_fout); + if (err) { + dev_err(&client->dev, "'factory-fout' property missing\n"); + return err; + } + + data->regmap = devm_regmap_init_i2c(client, &si570_regmap_config); + if (IS_ERR(data->regmap)) { + dev_err(&client->dev, "failed to allocate register map\n"); + return PTR_ERR(data->regmap); + } + + i2c_set_clientdata(client, data); + err = si570_get_defaults(data, factory_fout); + if (err) + return err; + + clk = devm_clk_register(&client->dev, &data->hw); + if (IS_ERR(clk)) { + dev_err(&client->dev, "clock registration failed\n"); + return PTR_ERR(clk); + } + err = of_clk_add_provider(client->dev.of_node, of_clk_src_simple_get, + clk); + if (err) { + dev_err(&client->dev, "unable to add clk provider\n"); + return err; + } + + /* Read the requested initial output frequency from device tree */ + if (!of_property_read_u32(client->dev.of_node, "clock-frequency", + &initial_fout)) { + err = clk_set_rate(clk, initial_fout); + if (err) { + of_clk_del_provider(client->dev.of_node); + return err; + } + } + + /* Display a message indicating that we've successfully registered */ + dev_info(&client->dev, "registered, current frequency %llu Hz\n", + data->frequency); + + return 0; +} + +static int si570_remove(struct i2c_client *client) +{ + of_clk_del_provider(client->dev.of_node); + return 0; +} + +static const struct i2c_device_id si570_id[] = { + { "si570", si57x }, + { "si571", si57x }, + { "si598", si59x }, + { "si599", si59x }, + { } +}; +MODULE_DEVICE_TABLE(i2c, si570_id); + +static const struct of_device_id clk_si570_of_match[] = { + { .compatible = "silabs,si570" }, + { .compatible = "silabs,si571" }, + { .compatible = "silabs,si598" }, + { .compatible = "silabs,si599" }, + { }, +}; +MODULE_DEVICE_TABLE(of, clk_si570_of_match); + +static struct i2c_driver si570_driver = { + .driver = { + .name = "si570", + .of_match_table = of_match_ptr(clk_si570_of_match), + }, + .probe = si570_probe, + .remove = si570_remove, + .id_table = si570_id, +}; +module_i2c_driver(si570_driver); + +MODULE_AUTHOR("Guenter Roeck "); +MODULE_AUTHOR("Soeren Brinkmann #include +#include #include #include #include @@ -46,6 +47,7 @@ #define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160) #define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164) #define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168) +#define SLCR_TOPSW_CLK_CTRL (zynq_slcr_base_priv + 0x16c) #define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170) #define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4) #define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304) @@ -100,11 +102,66 @@ static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"}; static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"}; +#ifdef CONFIG_SUSPEND +unsigned int zynq_clk_suspended; +static struct clk *armpll_save_parent; +static struct clk *iopll_save_parent; + +#define TOPSW_CLK_CTRL_DIS_MASK BIT(0) + +int zynq_clk_suspend_early(void) +{ + int ret; + + zynq_clk_suspended = 1; + + iopll_save_parent = clk_get_parent(clks[iopll]); + armpll_save_parent = clk_get_parent(clks[armpll]); + + ret = clk_set_parent(clks[iopll], ps_clk); + if (ret) + pr_info("%s: reparent iopll failed %d\n", __func__, ret); + + ret = clk_set_parent(clks[armpll], ps_clk); + if (ret) + pr_info("%s: reparent armpll failed %d\n", __func__, ret); + + return 0; +} + +void zynq_clk_resume_late(void) +{ + clk_set_parent(clks[armpll], armpll_save_parent); + clk_set_parent(clks[iopll], iopll_save_parent); + + zynq_clk_suspended = 0; +} + +void zynq_clk_topswitch_enable(void) +{ + u32 reg; + + reg = readl(SLCR_TOPSW_CLK_CTRL); + reg &= ~TOPSW_CLK_CTRL_DIS_MASK; + writel(reg, SLCR_TOPSW_CLK_CTRL); +} + +void zynq_clk_topswitch_disable(void) +{ + u32 reg; + + reg = readl(SLCR_TOPSW_CLK_CTRL); + reg |= TOPSW_CLK_CTRL_DIS_MASK; + writel(reg, SLCR_TOPSW_CLK_CTRL); +} +#endif + static void __init zynq_clk_register_fclk(enum zynq_clk fclk, const char *clk_name, void __iomem *fclk_ctrl_reg, - const char **parents) + const char **parents, int enable) { struct clk *clk; + u32 enable_reg; char *mux_name; char *div0_name; char *div1_name; @@ -141,6 +198,12 @@ clks[fclk] = clk_register_gate(NULL, clk_name, div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); + enable_reg = readl(fclk_gate_reg) & 1; + if (enable && !enable_reg) { + if (clk_prepare_enable(clks[fclk])) + pr_warn("%s: FCLK%u enable failed\n", __func__, + fclk - fclk0); + } kfree(mux_name); kfree(div0_name); kfree(div1_name); @@ -199,6 +262,7 @@ int ret; struct clk *clk; char *clk_name; + unsigned int fclk_enable; const char *clk_output_name[clk_max]; const char *cpu_parents[4]; const char *periph_parents[4]; @@ -233,6 +297,10 @@ ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT, tmp); + ret = of_property_read_u32(np, "fclk-enable", &fclk_enable); + if (ret) + fclk_enable = 0xf; + /* PLLs */ clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, SLCR_PLL_STATUS, 0, &armpll_lock); @@ -264,6 +332,7 @@ clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); + clk_register_clkdev(clks[cpu_6or4x], "cpufreq_clk", NULL); clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, 1, 2); @@ -326,10 +395,12 @@ clk_prepare_enable(clks[dci]); /* Peripheral clocks */ - for (i = fclk0; i <= fclk3; i++) + for (i = fclk0; i <= fclk3; i++) { + int enable = !!(fclk_enable & BIT(i - fclk0)); zynq_clk_register_fclk(i, clk_output_name[i], SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), - periph_parents); + periph_parents, enable); + } zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, SLCR_LQSPI_CLK_CTRL, periph_parents, 0); Index: linux-3.12.24-rt38-xilinx/drivers/clocksource/cadence_ttc_timer.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/clocksource/cadence_ttc_timer.c 2014-07-20 22:05:50.170067710 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/clocksource/cadence_ttc_timer.c 2014-07-20 22:06:35.537319227 +0200 @@ -67,11 +67,13 @@ * struct ttc_timer - This definition defines local timer structure * * @base_addr: Base address of timer + * @freq: Timer input clock frequency * @clk: Associated clock source * @clk_rate_change_nb Notifier block for clock rate changes */ struct ttc_timer { void __iomem *base_addr; + unsigned long freq; struct clk *clk; struct notifier_block clk_rate_change_nb; }; @@ -197,7 +199,7 @@ switch (mode) { case CLOCK_EVT_MODE_PERIODIC: ttc_set_interval(timer, - DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk), + DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ)); break; case CLOCK_EVT_MODE_ONESHOT: @@ -219,43 +221,6 @@ } } -static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, - unsigned long event, void *data) -{ - struct clk_notifier_data *ndata = data; - struct ttc_timer *ttc = to_ttc_timer(nb); - struct ttc_timer_clocksource *ttccs = container_of(ttc, - struct ttc_timer_clocksource, ttc); - - switch (event) { - case POST_RATE_CHANGE: - /* - * Do whatever is necessary to maintain a proper time base - * - * I cannot find a way to adjust the currently used clocksource - * to the new frequency. __clocksource_updatefreq_hz() sounds - * good, but does not work. Not sure what's that missing. - * - * This approach works, but triggers two clocksource switches. - * The first after unregister to clocksource jiffies. And - * another one after the register to the newly registered timer. - * - * Alternatively we could 'waste' another HW timer to ping pong - * between clock sources. That would also use one register and - * one unregister call, but only trigger one clocksource switch - * for the cost of another HW timer used by the OS. - */ - clocksource_unregister(&ttccs->cs); - clocksource_register_hz(&ttccs->cs, - ndata->new_rate / PRESCALE); - /* fall through */ - case PRE_RATE_CHANGE: - case ABORT_RATE_CHANGE: - default: - return NOTIFY_DONE; - } -} - static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) { struct ttc_timer_clocksource *ttccs; @@ -273,13 +238,7 @@ return; } - ttccs->ttc.clk_rate_change_nb.notifier_call = - ttc_rate_change_clocksource_cb; - ttccs->ttc.clk_rate_change_nb.next = NULL; - if (clk_notifier_register(ttccs->ttc.clk, - &ttccs->ttc.clk_rate_change_nb)) - pr_warn("Unable to register clock notifier.\n"); - + ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk); ttccs->ttc.base_addr = base; ttccs->cs.name = "ttc_clocksource"; ttccs->cs.rating = 200; @@ -298,16 +257,14 @@ __raw_writel(CNT_CNTRL_RESET, ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); - err = clocksource_register_hz(&ttccs->cs, - clk_get_rate(ttccs->ttc.clk) / PRESCALE); + err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE); if (WARN_ON(err)) { kfree(ttccs); return; } ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; - setup_sched_clock(ttc_sched_clock_read, 16, - clk_get_rate(ttccs->ttc.clk) / PRESCALE); + setup_sched_clock(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE); } static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, @@ -334,6 +291,13 @@ ndata->new_rate / PRESCALE); local_irq_restore(flags); + /* update cached frequency */ + ttc->freq = ndata->new_rate; + + if (ttcce->ce.mode == CLOCK_EVT_MODE_PERIODIC) + ttc_set_interval(ttc, DIV_ROUND_CLOSEST(ttc->freq, + PRESCALE * HZ)); + /* fall through */ } case PRE_RATE_CHANGE: @@ -367,6 +331,7 @@ if (clk_notifier_register(ttcce->ttc.clk, &ttcce->ttc.clk_rate_change_nb)) pr_warn("Unable to register clock notifier.\n"); + ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk); ttcce->ttc.base_addr = base; ttcce->ce.name = "ttc_clockevent"; @@ -396,7 +361,7 @@ } clockevents_config_and_register(&ttcce->ce, - clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe); + ttcce->ttc.freq / PRESCALE, 1, 0xfffe); } /** @@ -458,3 +423,4 @@ } CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); +CLOCKSOURCE_OF_DECLARE(ttc1, "xlnx,ps7-ttc-1.00.a", ttc_timer_init); Index: linux-3.12.24-rt38-xilinx/drivers/cpufreq/Kconfig.arm =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/cpufreq/Kconfig.arm 2014-07-20 22:05:50.175067628 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/cpufreq/Kconfig.arm 2014-07-20 22:06:35.550319013 +0200 @@ -235,3 +235,13 @@ default y help This adds the CPUFreq driver support for TEGRA SOCs. + +config ARM_ZYNQ_CPUFREQ + bool "Xilinx Zynq" + depends on ARCH_ZYNQ + default n + select CPU_FREQ_TABLE + select PM_OPP + help + This adds the CPUFreq driver for Xilinx Zynq SoCs. + Index: linux-3.12.24-rt38-xilinx/drivers/cpufreq/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/cpufreq/Makefile 2014-07-20 22:05:50.174067644 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/cpufreq/Makefile 2014-07-20 22:06:35.560318848 +0200 @@ -77,6 +77,7 @@ obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o obj-$(CONFIG_ARM_TEGRA_CPUFREQ) += tegra-cpufreq.o +obj-$(CONFIG_ARM_ZYNQ_CPUFREQ) += zynq-cpufreq.o ################################################################################## # PowerPC platform drivers Index: linux-3.12.24-rt38-xilinx/drivers/cpufreq/zynq-cpufreq.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/cpufreq/zynq-cpufreq.c 2014-07-20 22:06:35.575318600 +0200 @@ -0,0 +1,214 @@ +/* + * CPU frequency scaling for Zynq + * + * Based on drivers/cpufreq/omap-cpufreq.c, + * Copyright (C) 2005 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static atomic_t freq_table_users = ATOMIC_INIT(0); +static struct cpufreq_frequency_table *freq_table; +static struct device *mpu_dev; +static struct clk *cpuclk; + +static int zynq_verify_speed(struct cpufreq_policy *policy) +{ + if (!freq_table) + return -EINVAL; + return cpufreq_frequency_table_verify(policy, freq_table); +} + +static unsigned int zynq_getspeed(unsigned int cpu) +{ + unsigned long rate; + + if (cpu >= num_present_cpus()) + return 0; + + rate = clk_get_rate(cpuclk) / 1000; + return rate; +} + +static int zynq_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + unsigned int i; + int ret = 0; + struct cpufreq_freqs freqs; + +#ifdef CONFIG_SUSPEND + if (zynq_clk_suspended) + return -EPERM; +#endif + + if (!freq_table) { + dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__, + policy->cpu); + return -EINVAL; + } + + ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, + relation, &i); + if (ret) { + dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n", + __func__, policy->cpu, target_freq, ret); + return ret; + } + freqs.new = freq_table[i].frequency; + if (!freqs.new) { + dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__, + policy->cpu, target_freq); + return -EINVAL; + } + + freqs.old = zynq_getspeed(policy->cpu); + freqs.cpu = policy->cpu; + + if (freqs.old == freqs.new && policy->cur == freqs.new) + return ret; + + /* notifiers */ + cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); + + dev_dbg(mpu_dev, "cpufreq-zynq: %u MHz --> %u MHz\n", + freqs.old / 1000, freqs.new / 1000); + + ret = clk_set_rate(cpuclk, freqs.new * 1000); + + freqs.new = zynq_getspeed(policy->cpu); + + /* notifiers */ + cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); + + return ret; +} + +static inline void freq_table_free(void) +{ + if (atomic_dec_and_test(&freq_table_users)) + opp_free_cpufreq_table(mpu_dev, &freq_table); +} + +static int __cpuinit zynq_cpu_init(struct cpufreq_policy *policy) +{ + int result = 0; + + cpuclk = devm_clk_get(mpu_dev, "cpufreq_clk"); + if (IS_ERR(cpuclk)) { + dev_err(mpu_dev, "cpufreq_clk clock not found."); + return PTR_ERR(cpuclk); + } + + if (policy->cpu >= num_possible_cpus()) + return -EINVAL; + + policy->cur = policy->min = policy->max = zynq_getspeed(policy->cpu); + + if (!freq_table) + result = opp_init_cpufreq_table(mpu_dev, &freq_table); + + if (result) { + dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n", + __func__, policy->cpu, result); + return result; + } + + atomic_inc(&freq_table_users); + + result = cpufreq_frequency_table_cpuinfo(policy, freq_table); + if (result) { + freq_table_free(); + return result; + } + + cpufreq_frequency_table_get_attr(freq_table, policy->cpu); + + policy->min = policy->cpuinfo.min_freq; + policy->max = policy->cpuinfo.max_freq; + policy->cur = zynq_getspeed(policy->cpu); + + /* + * On Zynq configuartion, both processors share the voltage + * and clock. So both CPUs needs to be scaled together and hence + * needs software co-ordination. Use cpufreq affected_cpus + * interface to handle this scenario. Additional is_smp() check + * is to keep SMP_ON_UP build working. + */ + if (is_smp()) { + policy->shared_type = CPUFREQ_SHARED_TYPE_ANY; + cpumask_setall(policy->cpus); + } + + /* FIXME: what's the actual transition time? */ + policy->cpuinfo.transition_latency = 300 * 1000; + + return 0; +} + +static int zynq_cpu_exit(struct cpufreq_policy *policy) +{ + freq_table_free(); + return 0; +} + +static struct freq_attr *zynq_cpufreq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; + +static struct cpufreq_driver zynq_cpufreq_driver = { + .flags = CPUFREQ_STICKY, + .verify = zynq_verify_speed, + .target = zynq_target, + .get = zynq_getspeed, + .init = zynq_cpu_init, + .exit = zynq_cpu_exit, + .name = "Zynq cpufreq", + .attr = zynq_cpufreq_attr, +}; + +static int __init zynq_cpufreq_init(void) +{ + struct device *dev = get_cpu_device(0); + + if (!dev) { + pr_warn("%s: Error: device not found.", __func__); + return -EINVAL; + } + mpu_dev = dev; + return cpufreq_register_driver(&zynq_cpufreq_driver); +} + +static void __exit zynq_cpufreq_exit(void) +{ + cpufreq_unregister_driver(&zynq_cpufreq_driver); +} + +MODULE_DESCRIPTION("cpufreq driver for Zynq"); +MODULE_LICENSE("GPL"); +module_init(zynq_cpufreq_init); +module_exit(zynq_cpufreq_exit); Index: linux-3.12.24-rt38-xilinx/drivers/dma/dmatest.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/dma/dmatest.c 2014-07-20 22:05:50.149068057 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/dma/dmatest.c 2014-07-20 22:06:35.597318237 +0200 @@ -626,6 +626,7 @@ break; } + align = 3; len = dmatest_random() % params->buf_size + 1; len = (len >> align) << align; if (!len) Index: linux-3.12.24-rt38-xilinx/drivers/dma/Kconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/dma/Kconfig 2014-07-20 22:05:50.163067826 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/dma/Kconfig 2014-07-20 22:06:35.609318040 +0200 @@ -33,6 +33,8 @@ comment "DMA Devices" +source "drivers/dma/xilinx/Kconfig" + config INTEL_MID_DMAC tristate "Intel MID DMA support for Peripheral DMA controllers" depends on PCI && X86 Index: linux-3.12.24-rt38-xilinx/drivers/dma/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/dma/Makefile 2014-07-20 22:05:50.162067842 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/dma/Makefile 2014-07-20 22:06:35.619317875 +0200 @@ -41,3 +41,4 @@ obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o obj-$(CONFIG_TI_CPPI41) += cppi41.o obj-$(CONFIG_K3_DMA) += k3dma.o +obj-$(CONFIG_XILINX_DMA_ENGINES) += xilinx/ Index: linux-3.12.24-rt38-xilinx/drivers/dma/pl330.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/dma/pl330.c 2014-07-20 22:05:50.161067858 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/dma/pl330.c 2014-07-20 22:06:35.639317545 +0200 @@ -2922,16 +2922,23 @@ amba_set_drvdata(adev, pdmac); - irq = adev->irq[0]; - ret = request_irq(irq, pl330_irq_handler, 0, - dev_name(&adev->dev), pi); - if (ret) - return ret; + for (i = 0; i <= AMBA_NR_IRQS; i++) { + irq = adev->irq[i]; + if (irq) { + ret = devm_request_irq(&adev->dev, irq, + pl330_irq_handler, 0, + dev_name(&adev->dev), pi); + if (ret) + return ret; + } else { + break; + } + } pi->pcfg.periph_id = adev->periphid; ret = pl330_add(pi); if (ret) - goto probe_err1; + return ret; INIT_LIST_HEAD(&pdmac->desc_pool); spin_lock_init(&pdmac->pool_lock); @@ -3044,8 +3051,6 @@ } probe_err2: pl330_del(pi); -probe_err1: - free_irq(irq, pi); return ret; } @@ -3055,7 +3060,6 @@ struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev); struct dma_pl330_chan *pch, *_p; struct pl330_info *pi; - int irq; if (!pdmac) return 0; @@ -3082,9 +3086,6 @@ pl330_del(pi); - irq = adev->irq[0]; - free_irq(irq, pi); - return 0; } Index: linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/axidmatest.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/axidmatest.c 2014-07-20 22:06:35.657317248 +0200 @@ -0,0 +1,656 @@ +/* + * XILINX AXI DMA Engine test module + * + * Copyright (C) 2010 Xilinx, Inc. All rights reserved. + * + * Based on Atmel DMA Test Client + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned int test_buf_size = 64; +module_param(test_buf_size, uint, S_IRUGO); +MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer"); + +static unsigned int iterations; +module_param(iterations, uint, S_IRUGO); +MODULE_PARM_DESC(iterations, + "Iterations before stopping test (default: infinite)"); + +/* + * Initialization patterns. All bytes in the source buffer has bit 7 + * set, all bytes in the destination buffer has bit 7 cleared. + * + * Bit 6 is set for all bytes which are to be copied by the DMA + * engine. Bit 5 is set for all bytes which are to be overwritten by + * the DMA engine. + * + * The remaining bits are the inverse of a counter which increments by + * one for each byte address. + */ +#define PATTERN_SRC 0x80 +#define PATTERN_DST 0x00 +#define PATTERN_COPY 0x40 +#define PATTERN_OVERWRITE 0x20 +#define PATTERN_COUNT_MASK 0x1f + +struct dmatest_slave_thread { + struct list_head node; + struct task_struct *task; + struct dma_chan *tx_chan; + struct dma_chan *rx_chan; + u8 **srcs; + u8 **dsts; + enum dma_transaction_type type; +}; + +struct dmatest_chan { + struct list_head node; + struct dma_chan *chan; + struct list_head threads; +}; + +/* + * These are protected by dma_list_mutex since they're only used by + * the DMA filter function callback + */ +static LIST_HEAD(dmatest_channels); +static unsigned int nr_channels; + +static unsigned long dmatest_random(void) +{ + unsigned long buf; + + get_random_bytes(&buf, sizeof(buf)); + return buf; +} + +static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len) +{ + unsigned int i; + u8 *buf; + + for (; (buf = *bufs); bufs++) { + for (i = 0; i < start; i++) + buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK); + for ( ; i < start + len; i++) + buf[i] = PATTERN_SRC | PATTERN_COPY + | (~i & PATTERN_COUNT_MASK); + for ( ; i < test_buf_size; i++) + buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK); + buf++; + } +} + +static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len) +{ + unsigned int i; + u8 *buf; + + for (; (buf = *bufs); bufs++) { + for (i = 0; i < start; i++) + buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK); + for ( ; i < start + len; i++) + buf[i] = PATTERN_DST | PATTERN_OVERWRITE + | (~i & PATTERN_COUNT_MASK); + for ( ; i < test_buf_size; i++) + buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK); + } +} + +static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index, + unsigned int counter, bool is_srcbuf) +{ + u8 diff = actual ^ pattern; + u8 expected = pattern | (~counter & PATTERN_COUNT_MASK); + const char *thread_name = current->comm; + + if (is_srcbuf) + pr_warn( + "%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n", + thread_name, index, expected, actual); + else if ((pattern & PATTERN_COPY) + && (diff & (PATTERN_COPY | PATTERN_OVERWRITE))) + pr_warn( + "%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n", + thread_name, index, expected, actual); + else if (diff & PATTERN_SRC) + pr_warn( + "%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n", + thread_name, index, expected, actual); + else + pr_warn( + "%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n", + thread_name, index, expected, actual); +} + +static unsigned int dmatest_verify(u8 **bufs, unsigned int start, + unsigned int end, unsigned int counter, u8 pattern, + bool is_srcbuf) +{ + unsigned int i; + unsigned int error_count = 0; + u8 actual; + u8 expected; + u8 *buf; + unsigned int counter_orig = counter; + + for (; (buf = *bufs); bufs++) { + counter = counter_orig; + for (i = start; i < end; i++) { + actual = buf[i]; + expected = pattern | (~counter & PATTERN_COUNT_MASK); + if (actual != expected) { + if (error_count < 32) + dmatest_mismatch(actual, pattern, i, + counter, is_srcbuf); + error_count++; + } + counter++; + } + } + + if (error_count > 32) + pr_warn("%s: %u errors suppressed\n", + current->comm, error_count - 32); + + return error_count; +} + +static void dmatest_slave_tx_callback(void *completion) +{ + complete(completion); +} + +static void dmatest_slave_rx_callback(void *completion) +{ + complete(completion); +} + +/* Function for slave transfers + * Each thread requires 2 channels, one for transmit, and one for receive + */ +static int dmatest_slave_func(void *data) +{ + struct dmatest_slave_thread *thread = data; + struct dma_chan *tx_chan; + struct dma_chan *rx_chan; + const char *thread_name; + unsigned int src_off, dst_off, len; + unsigned int error_count; + unsigned int failed_tests = 0; + unsigned int total_tests = 0; + dma_cookie_t tx_cookie; + dma_cookie_t rx_cookie; + enum dma_status status; + enum dma_ctrl_flags flags; + int ret; + int src_cnt; + int dst_cnt; + int bd_cnt = 11; + int i; + struct xilinx_dma_config config; + thread_name = current->comm; + + ret = -ENOMEM; + + /* JZ: limit testing scope here */ + iterations = 5; + test_buf_size = 700; + + smp_rmb(); + tx_chan = thread->tx_chan; + rx_chan = thread->rx_chan; + src_cnt = dst_cnt = bd_cnt; + + thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL); + if (!thread->srcs) + goto err_srcs; + for (i = 0; i < src_cnt; i++) { + thread->srcs[i] = kmalloc(test_buf_size, GFP_KERNEL); + if (!thread->srcs[i]) + goto err_srcbuf; + } + thread->srcs[i] = NULL; + + thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL); + if (!thread->dsts) + goto err_dsts; + for (i = 0; i < dst_cnt; i++) { + thread->dsts[i] = kmalloc(test_buf_size, GFP_KERNEL); + if (!thread->dsts[i]) + goto err_dstbuf; + } + thread->dsts[i] = NULL; + + set_user_nice(current, 10); + + flags = DMA_CTRL_ACK | DMA_COMPL_SKIP_DEST_UNMAP | DMA_PREP_INTERRUPT; + + while (!kthread_should_stop() + && !(iterations && total_tests >= iterations)) { + struct dma_device *tx_dev = tx_chan->device; + struct dma_device *rx_dev = rx_chan->device; + struct dma_async_tx_descriptor *txd = NULL; + struct dma_async_tx_descriptor *rxd = NULL; + dma_addr_t dma_srcs[src_cnt]; + dma_addr_t dma_dsts[dst_cnt]; + struct completion rx_cmp; + struct completion tx_cmp; + unsigned long rx_tmo = + msecs_to_jiffies(300000); /* RX takes longer */ + unsigned long tx_tmo = msecs_to_jiffies(30000); + u8 align = 0; + struct scatterlist tx_sg[bd_cnt]; + struct scatterlist rx_sg[bd_cnt]; + + total_tests++; + + /* honor larger alignment restrictions */ + align = tx_dev->copy_align; + if (rx_dev->copy_align > align) + align = rx_dev->copy_align; + + if (1 << align > test_buf_size) { + pr_err("%u-byte buffer too small for %d-byte alignment\n", + test_buf_size, 1 << align); + break; + } + + len = dmatest_random() % test_buf_size + 1; + len = (len >> align) << align; + if (!len) + len = 1 << align; + src_off = dmatest_random() % (test_buf_size - len + 1); + dst_off = dmatest_random() % (test_buf_size - len + 1); + + src_off = (src_off >> align) << align; + dst_off = (dst_off >> align) << align; + + dmatest_init_srcs(thread->srcs, src_off, len); + dmatest_init_dsts(thread->dsts, dst_off, len); + + for (i = 0; i < src_cnt; i++) { + u8 *buf = thread->srcs[i] + src_off; + + dma_srcs[i] = dma_map_single(tx_dev->dev, buf, len, + DMA_MEM_TO_DEV); + } + + for (i = 0; i < dst_cnt; i++) { + dma_dsts[i] = dma_map_single(rx_dev->dev, + thread->dsts[i], + test_buf_size, + DMA_MEM_TO_DEV); + + dma_unmap_single(rx_dev->dev, dma_dsts[i], + test_buf_size, + DMA_MEM_TO_DEV); + + dma_dsts[i] = dma_map_single(rx_dev->dev, + thread->dsts[i], + test_buf_size, + DMA_DEV_TO_MEM); + } + + sg_init_table(tx_sg, bd_cnt); + sg_init_table(rx_sg, bd_cnt); + + for (i = 0; i < bd_cnt; i++) { + sg_dma_address(&tx_sg[i]) = dma_srcs[i]; + sg_dma_address(&rx_sg[i]) = dma_dsts[i] + dst_off; + + sg_dma_len(&tx_sg[i]) = len; + sg_dma_len(&rx_sg[i]) = len; + + } + + /* Only one interrupt */ + config.coalesc = 1; + config.delay = 0; + rx_dev->device_control(rx_chan, DMA_SLAVE_CONFIG, + (unsigned long)&config); + + config.coalesc = 1; + config.delay = 0; + tx_dev->device_control(tx_chan, DMA_SLAVE_CONFIG, + (unsigned long)&config); + + rxd = rx_dev->device_prep_slave_sg(rx_chan, rx_sg, bd_cnt, + DMA_DEV_TO_MEM, flags, NULL); + + txd = tx_dev->device_prep_slave_sg(tx_chan, tx_sg, bd_cnt, + DMA_MEM_TO_DEV, flags, NULL); + + if (!rxd || !txd) { + for (i = 0; i < src_cnt; i++) + dma_unmap_single(tx_dev->dev, dma_srcs[i], len, + DMA_MEM_TO_DEV); + for (i = 0; i < dst_cnt; i++) + dma_unmap_single(rx_dev->dev, dma_dsts[i], + test_buf_size, + DMA_DEV_TO_MEM); + pr_warn( + "%s: #%u: prep error with src_off=0x%x ", + thread_name, total_tests - 1, src_off); + pr_warn("dst_off=0x%x len=0x%x\n", + dst_off, len); + msleep(100); + failed_tests++; + continue; + } + + init_completion(&rx_cmp); + rxd->callback = dmatest_slave_rx_callback; + rxd->callback_param = &rx_cmp; + rx_cookie = rxd->tx_submit(rxd); + + init_completion(&tx_cmp); + txd->callback = dmatest_slave_tx_callback; + txd->callback_param = &tx_cmp; + tx_cookie = txd->tx_submit(txd); + + if (dma_submit_error(rx_cookie) || + dma_submit_error(tx_cookie)) { + pr_warn( + "%s: #%u: submit error %d/%d with src_off=0x%x ", + thread_name, total_tests - 1, + rx_cookie, tx_cookie, src_off); + pr_warn("dst_off=0x%x len=0x%x\n", + dst_off, len); + msleep(100); + failed_tests++; + continue; + } + dma_async_issue_pending(tx_chan); + dma_async_issue_pending(rx_chan); + + tx_tmo = wait_for_completion_timeout(&tx_cmp, tx_tmo); + + status = dma_async_is_tx_complete(tx_chan, tx_cookie, + NULL, NULL); + + if (tx_tmo == 0) { + pr_warn("%s: #%u: tx test timed out\n", + thread_name, total_tests - 1); + failed_tests++; + continue; + } else if (status != DMA_SUCCESS) { + pr_warn( + "%s: #%u: tx got completion callback, ", + thread_name, total_tests - 1); + pr_warn("but status is \'%s\'\n", + status == DMA_ERROR ? "error" : + "in progress"); + failed_tests++; + continue; + } + + rx_tmo = wait_for_completion_timeout(&rx_cmp, rx_tmo); + status = dma_async_is_tx_complete(rx_chan, rx_cookie, + NULL, NULL); + + if (rx_tmo == 0) { + pr_warn("%s: #%u: rx test timed out\n", + thread_name, total_tests - 1); + failed_tests++; + continue; + } else if (status != DMA_SUCCESS) { + pr_warn( + "%s: #%u: rx got completion callback, ", + thread_name, total_tests - 1); + pr_warn("but status is \'%s\'\n", + status == DMA_ERROR ? "error" : + "in progress"); + failed_tests++; + continue; + } + + /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */ + for (i = 0; i < dst_cnt; i++) + dma_unmap_single(rx_dev->dev, dma_dsts[i], + test_buf_size, DMA_DEV_TO_MEM); + + error_count = 0; + + pr_debug("%s: verifying source buffer...\n", thread_name); + error_count += dmatest_verify(thread->srcs, 0, src_off, + 0, PATTERN_SRC, true); + error_count += dmatest_verify(thread->srcs, src_off, + src_off + len, src_off, + PATTERN_SRC | PATTERN_COPY, true); + error_count += dmatest_verify(thread->srcs, src_off + len, + test_buf_size, src_off + len, + PATTERN_SRC, true); + + pr_debug("%s: verifying dest buffer...\n", + thread->task->comm); + error_count += dmatest_verify(thread->dsts, 0, dst_off, + 0, PATTERN_DST, false); + error_count += dmatest_verify(thread->dsts, dst_off, + dst_off + len, src_off, + PATTERN_SRC | PATTERN_COPY, false); + error_count += dmatest_verify(thread->dsts, dst_off + len, + test_buf_size, dst_off + len, + PATTERN_DST, false); + + if (error_count) { + pr_warn("%s: #%u: %u errors with ", + thread_name, total_tests - 1, error_count); + pr_warn("src_off=0x%x dst_off=0x%x len=0x%x\n", + src_off, dst_off, len); + failed_tests++; + } else { + pr_debug("%s: #%u: No errors with ", + thread_name, total_tests - 1); + pr_debug("src_off=0x%x dst_off=0x%x len=0x%x\n", + src_off, dst_off, len); + } + } + + ret = 0; + for (i = 0; thread->dsts[i]; i++) + kfree(thread->dsts[i]); +err_dstbuf: + kfree(thread->dsts); +err_dsts: + for (i = 0; thread->srcs[i]; i++) + kfree(thread->srcs[i]); +err_srcbuf: + kfree(thread->srcs); +err_srcs: + pr_notice("%s: terminating after %u tests, %u failures (status %d)\n", + thread_name, total_tests, failed_tests, ret); + + if (iterations > 0) + while (!kthread_should_stop()) { + DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_dmatest_exit); + interruptible_sleep_on(&wait_dmatest_exit); + } + + return ret; +} + +static void dmatest_cleanup_channel(struct dmatest_chan *dtc) +{ + struct dmatest_slave_thread *thread; + struct dmatest_slave_thread *_thread; + int ret; + + list_for_each_entry_safe(thread, _thread, &dtc->threads, node) { + ret = kthread_stop(thread->task); + pr_debug("dmatest: thread %s exited with status %d\n", + thread->task->comm, ret); + list_del(&thread->node); + kfree(thread); + } + kfree(dtc); +} + +static int dmatest_add_slave_threads(struct dmatest_chan *tx_dtc, + struct dmatest_chan *rx_dtc) +{ + struct dmatest_slave_thread *thread; + struct dma_chan *tx_chan = tx_dtc->chan; + struct dma_chan *rx_chan = rx_dtc->chan; + + thread = kzalloc(sizeof(struct dmatest_slave_thread), GFP_KERNEL); + if (!thread) { + pr_warn("dmatest: No memory for slave thread %s-%s\n", + dma_chan_name(tx_chan), dma_chan_name(rx_chan)); + + } + + thread->tx_chan = tx_chan; + thread->rx_chan = rx_chan; + thread->type = (enum dma_transaction_type)DMA_SLAVE; + smp_wmb(); + thread->task = kthread_run(dmatest_slave_func, thread, "%s-%s", + dma_chan_name(tx_chan), dma_chan_name(rx_chan)); + if (IS_ERR(thread->task)) { + pr_warn("dmatest: Failed to run thread %s-%s\n", + dma_chan_name(tx_chan), dma_chan_name(rx_chan)); + kfree(thread); + } + + /* srcbuf and dstbuf are allocated by the thread itself */ + + list_add_tail(&thread->node, &tx_dtc->threads); + + /* Added one thread with 2 channels */ + return 1; +} + +static int dmatest_add_slave_channels(struct dma_chan *tx_chan, + struct dma_chan *rx_chan) +{ + struct dmatest_chan *tx_dtc; + struct dmatest_chan *rx_dtc; + unsigned int thread_count = 0; + + tx_dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL); + if (!tx_dtc) { + pr_warn("dmatest: No memory for tx %s\n", + dma_chan_name(tx_chan)); + return -ENOMEM; + } + + rx_dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL); + if (!rx_dtc) { + pr_warn("dmatest: No memory for rx %s\n", + dma_chan_name(rx_chan)); + return -ENOMEM; + } + + tx_dtc->chan = tx_chan; + rx_dtc->chan = rx_chan; + INIT_LIST_HEAD(&tx_dtc->threads); + INIT_LIST_HEAD(&rx_dtc->threads); + + dmatest_add_slave_threads(tx_dtc, rx_dtc); + thread_count += 1; + + pr_info("dmatest: Started %u threads using %s %s\n", + thread_count, dma_chan_name(tx_chan), dma_chan_name(rx_chan)); + + list_add_tail(&tx_dtc->node, &dmatest_channels); + list_add_tail(&rx_dtc->node, &dmatest_channels); + nr_channels += 2; + + return 0; +} + +static bool xdma_filter(struct dma_chan *chan, void *param) +{ + pr_debug("dmatest: Private is %x\n", *((int *)chan->private)); + + if (*((int *)chan->private) == *(int *)param) + return true; + + return false; +} + +static int __init dmatest_init(void) +{ + dma_cap_mask_t mask; + struct dma_chan *chan; + int err = 0; + + /* JZ for slave transfer channels */ + enum dma_data_direction direction; + struct dma_chan *rx_chan; + u32 match, device_id = 0; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE | DMA_PRIVATE, mask); + + for (;;) { + direction = DMA_MEM_TO_DEV; + match = (direction & 0xFF) | XILINX_DMA_IP_DMA | + (device_id << XILINX_DMA_DEVICE_ID_SHIFT); + pr_debug("dmatest: match is %x\n", match); + + chan = dma_request_channel(mask, xdma_filter, (void *)&match); + + if (chan) + pr_debug("dmatest: Found tx device\n"); + else + pr_debug("dmatest: No more tx channels available\n"); + + direction = DMA_DEV_TO_MEM; + match = (direction & 0xFF) | XILINX_DMA_IP_DMA | + (device_id << XILINX_DMA_DEVICE_ID_SHIFT); + rx_chan = dma_request_channel(mask, xdma_filter, &match); + + if (rx_chan) + pr_debug("dmatest: Found rx device\n"); + else + pr_debug("dmatest: No more rx channels available\n"); + + if (chan && rx_chan) { + err = dmatest_add_slave_channels(chan, rx_chan); + if (err) { + dma_release_channel(chan); + dma_release_channel(rx_chan); + } + } else + break; + + device_id++; + } + + return err; +} +/* when compiled-in wait for drivers to load first */ +late_initcall(dmatest_init); + +static void __exit dmatest_exit(void) +{ + struct dmatest_chan *dtc, *_dtc; + struct dma_chan *chan; + + list_for_each_entry_safe(dtc, _dtc, &dmatest_channels, node) { + list_del(&dtc->node); + chan = dtc->chan; + dmatest_cleanup_channel(dtc); + pr_debug("dmatest: dropped channel %s\n", + dma_chan_name(chan)); + dma_release_channel(chan); + } +} +module_exit(dmatest_exit); + +MODULE_AUTHOR("Xilinx, Inc."); +MODULE_DESCRIPTION("Xilinx AXI DMA Test Client"); +MODULE_LICENSE("GPL v2"); Index: linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/cdmatest.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/cdmatest.c 2014-07-20 22:06:35.736315945 +0200 @@ -0,0 +1,644 @@ +/* + * XILINX CDMA Engine test module + * + * Copyright (C) 2012 Xilinx, Inc. All rights reserved. + * + * Based on Atmel DMA Test Client + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned int test_buf_size = 64; +module_param(test_buf_size, uint, S_IRUGO); +MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer"); + +static char test_channel[20]; +module_param_string(channel, test_channel, sizeof(test_channel), S_IRUGO); +MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)"); + +static char test_device[20]; +module_param_string(device, test_device, sizeof(test_device), S_IRUGO); +MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)"); + +static unsigned int threads_per_chan = 1; +module_param(threads_per_chan, uint, S_IRUGO); +MODULE_PARM_DESC(threads_per_chan, + "Number of threads to start per channel (default: 1)"); + +static unsigned int max_channels; +module_param(max_channels, uint, S_IRUGO); +MODULE_PARM_DESC(max_channels, + "Maximum number of channels to use (default: all)"); + +static unsigned int iterations; +module_param(iterations, uint, S_IRUGO); +MODULE_PARM_DESC(iterations, + "Iterations before stopping test (default: infinite)"); + +static unsigned int xor_sources = 3; +module_param(xor_sources, uint, S_IRUGO); +MODULE_PARM_DESC(xor_sources, + "Number of xor source buffers (default: 3)"); + +static unsigned int pq_sources = 3; +module_param(pq_sources, uint, S_IRUGO); +MODULE_PARM_DESC(pq_sources, + "Number of p+q source buffers (default: 3)"); + +/* + * Initialization patterns. All bytes in the source buffer has bit 7 + * set, all bytes in the destination buffer has bit 7 cleared. + * + * Bit 6 is set for all bytes which are to be copied by the DMA + * engine. Bit 5 is set for all bytes which are to be overwritten by + * the DMA engine. + * + * The remaining bits are the inverse of a counter which increments by + * one for each byte address. + */ +#define PATTERN_SRC 0x80 +#define PATTERN_DST 0x00 +#define PATTERN_COPY 0x40 +#define PATTERN_OVERWRITE 0x20 +#define PATTERN_COUNT_MASK 0x1f + +struct cdmatest_thread { + struct list_head node; + struct task_struct *task; + struct dma_chan *chan; + u8 **srcs; + u8 **dsts; + enum dma_transaction_type type; +}; + +struct cdmatest_chan { + struct list_head node; + struct dma_chan *chan; + struct list_head threads; +}; + +/* + * These are protected by dma_list_mutex since they're only used by + * the DMA filter function callback + */ +static LIST_HEAD(cdmatest_channels); +static unsigned int nr_channels; + +static bool cdmatest_match_channel(struct dma_chan *chan) +{ + if (test_channel[0] == '\0') + return true; + return strcmp(dma_chan_name(chan), test_channel) == 0; +} + +static bool cdmatest_match_device(struct dma_device *device) +{ + if (test_device[0] == '\0') + return true; + return strcmp(dev_name(device->dev), test_device) == 0; +} + +static unsigned long cdmatest_random(void) +{ + unsigned long buf; + + get_random_bytes(&buf, sizeof(buf)); + return buf; +} + +static void cdmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len) +{ + unsigned int i; + u8 *buf; + + for (; (buf = *bufs); bufs++) { + for (i = 0; i < start; i++) + buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK); + for ( ; i < start + len; i++) + buf[i] = PATTERN_SRC | PATTERN_COPY + | (~i & PATTERN_COUNT_MASK); + for ( ; i < test_buf_size; i++) + buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK); + buf++; + } +} + +static void cdmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len) +{ + unsigned int i; + u8 *buf; + + for (; (buf = *bufs); bufs++) { + for (i = 0; i < start; i++) + buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK); + for ( ; i < start + len; i++) + buf[i] = PATTERN_DST | PATTERN_OVERWRITE + | (~i & PATTERN_COUNT_MASK); + for ( ; i < test_buf_size; i++) + buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK); + } +} + +static void cdmatest_mismatch(u8 actual, u8 pattern, unsigned int index, + unsigned int counter, bool is_srcbuf) +{ + u8 diff = actual ^ pattern; + u8 expected = pattern | (~counter & PATTERN_COUNT_MASK); + const char *thread_name = current->comm; + + if (is_srcbuf) + pr_warn( + "%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n", + thread_name, index, expected, actual); + else if ((pattern & PATTERN_COPY) + && (diff & (PATTERN_COPY | PATTERN_OVERWRITE))) + pr_warn( + "%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n", + thread_name, index, expected, actual); + else if (diff & PATTERN_SRC) + pr_warn( + "%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n", + thread_name, index, expected, actual); + else + pr_warn( + "%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n", + thread_name, index, expected, actual); +} + +static unsigned int cdmatest_verify(u8 **bufs, unsigned int start, + unsigned int end, unsigned int counter, u8 pattern, + bool is_srcbuf) +{ + unsigned int i; + unsigned int error_count = 0; + u8 actual; + u8 expected; + u8 *buf; + unsigned int counter_orig = counter; + + for (; (buf = *bufs); bufs++) { + counter = counter_orig; + for (i = start; i < end; i++) { + actual = buf[i]; + expected = pattern | (~counter & PATTERN_COUNT_MASK); + if (actual != expected) { + if (error_count < 32) + cdmatest_mismatch(actual, pattern, i, + counter, is_srcbuf); + error_count++; + } + counter++; + } + } + + if (error_count > 32) + pr_warn("%s: %u errors suppressed\n", + current->comm, error_count - 32); + + return error_count; +} + +static void cdmatest_callback(void *completion) +{ + complete(completion); +} + +/* + * This function repeatedly tests DMA transfers of various lengths and + * offsets for a given operation type until it is told to exit by + * kthread_stop(). There may be multiple threads running this function + * in parallel for a single channel, and there may be multiple channels + * being tested in parallel. + * + * Before each test, the source and destination buffer is initialized + * with a known pattern. This pattern is different depending on + * whether it's in an area which is supposed to be copied or + * overwritten, and different in the source and destination buffers. + * So if the DMA engine doesn't copy exactly what we tell it to copy, + * we'll notice. + */ +static int cdmatest_func(void *data) +{ + struct cdmatest_thread *thread = data; + struct dma_chan *chan; + const char *thread_name; + unsigned int src_off, dst_off, len; + unsigned int error_count; + unsigned int failed_tests = 0; + unsigned int total_tests = 0; + dma_cookie_t cookie; + enum dma_status status; + enum dma_ctrl_flags flags; + u8 pq_coefs[pq_sources + 1]; + int ret; + int src_cnt; + int dst_cnt; + int i; + + thread_name = current->comm; + + ret = -ENOMEM; + + /* JZ: limit testing scope here */ + iterations = 5; + + smp_rmb(); + chan = thread->chan; + if (thread->type == DMA_MEMCPY) + src_cnt = dst_cnt = 1; + else if (thread->type == DMA_XOR) { + src_cnt = xor_sources | 1; + /* force odd to ensure dst = src */ + dst_cnt = 1; + } else if (thread->type == DMA_PQ) { + src_cnt = pq_sources | 1; + /* force odd to ensure dst = src */ + dst_cnt = 2; + for (i = 0; i < src_cnt; i++) + pq_coefs[i] = 1; + } else + goto err_srcs; + + thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL); + if (!thread->srcs) + goto err_srcs; + for (i = 0; i < src_cnt; i++) { + thread->srcs[i] = kmalloc(test_buf_size, GFP_KERNEL); + if (!thread->srcs[i]) + goto err_srcbuf; + } + thread->srcs[i] = NULL; + + thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL); + if (!thread->dsts) + goto err_dsts; + for (i = 0; i < dst_cnt; i++) { + thread->dsts[i] = kmalloc(test_buf_size, GFP_KERNEL); + if (!thread->dsts[i]) + goto err_dstbuf; + } + thread->dsts[i] = NULL; + + set_user_nice(current, 10); + + flags = DMA_CTRL_ACK | DMA_COMPL_SKIP_DEST_UNMAP | DMA_PREP_INTERRUPT; + + while (!kthread_should_stop() + && !(iterations && total_tests >= iterations)) { + struct dma_device *dev = chan->device; + struct dma_async_tx_descriptor *tx = NULL; + dma_addr_t dma_srcs[src_cnt]; + dma_addr_t dma_dsts[dst_cnt]; + struct completion cmp; + unsigned long tmo = msecs_to_jiffies(3000); + u8 align = 0; + + total_tests++; + + /* honor alignment restrictions */ + if (thread->type == DMA_MEMCPY) + align = dev->copy_align; + else if (thread->type == DMA_XOR) + align = dev->xor_align; + else if (thread->type == DMA_PQ) + align = dev->pq_align; + + if (1 << align > test_buf_size) { + pr_err("%u-byte buffer too small for %d-byte alignment\n", + test_buf_size, 1 << align); + break; + } + + len = cdmatest_random() % test_buf_size + 1; + len = (len >> align) << align; + if (!len) + len = 1 << align; + src_off = cdmatest_random() % (test_buf_size - len + 1); + dst_off = cdmatest_random() % (test_buf_size - len + 1); + + src_off = (src_off >> align) << align; + dst_off = (dst_off >> align) << align; + + cdmatest_init_srcs(thread->srcs, src_off, len); + cdmatest_init_dsts(thread->dsts, dst_off, len); + + for (i = 0; i < src_cnt; i++) { + u8 *buf = thread->srcs[i] + src_off; + + dma_srcs[i] = dma_map_single(dev->dev, buf, len, + DMA_MEM_TO_DEV); + } + /* map with DMA_MEM_TO_MEM to force writeback/invalidate */ + for (i = 0; i < dst_cnt; i++) { + dma_dsts[i] = dma_map_single(dev->dev, thread->dsts[i], + test_buf_size, + DMA_MEM_TO_MEM); + } + + if (thread->type == DMA_MEMCPY) { + tx = dev->device_prep_dma_memcpy(chan, + dma_dsts[0] + dst_off, + dma_srcs[0], len, + flags); + + } else if (thread->type == DMA_XOR) + tx = dev->device_prep_dma_xor(chan, + dma_dsts[0] + dst_off, + dma_srcs, src_cnt, + len, flags); + else if (thread->type == DMA_PQ) { + dma_addr_t dma_pq[dst_cnt]; + + for (i = 0; i < dst_cnt; i++) + dma_pq[i] = dma_dsts[i] + dst_off; + tx = dev->device_prep_dma_pq(chan, dma_pq, dma_srcs, + src_cnt, pq_coefs, + len, flags); + } + + if (!tx) { + for (i = 0; i < src_cnt; i++) + dma_unmap_single(dev->dev, dma_srcs[i], len, + DMA_MEM_TO_DEV); + for (i = 0; i < dst_cnt; i++) + dma_unmap_single(dev->dev, dma_dsts[i], + test_buf_size, + DMA_MEM_TO_MEM); + pr_warn( + "%s: #%u: prep error with src_off=0x%x ", + thread_name, total_tests - 1, src_off); + pr_warn("dst_off=0x%x len=0x%x\n", + dst_off, len); + msleep(100); + failed_tests++; + continue; + } + + init_completion(&cmp); + tx->callback = cdmatest_callback; + tx->callback_param = &cmp; + cookie = tx->tx_submit(tx); + + if (dma_submit_error(cookie)) { + pr_warn( + "%s: #%u: submit error %d with src_off=0x%x ", + thread_name, total_tests - 1, + cookie, src_off); + pr_warn("dst_off=0x%x len=0x%x\n", + dst_off, len); + msleep(100); + failed_tests++; + continue; + } + dma_async_issue_pending(chan); + + tmo = wait_for_completion_timeout(&cmp, tmo); + status = dma_async_is_tx_complete(chan, cookie, NULL, NULL); + + if (tmo == 0) { + pr_warn("%s: #%u: test timed out\n", + thread_name, total_tests - 1); + failed_tests++; + continue; + } else if (status != DMA_SUCCESS) { + pr_warn( + "%s: #%u: got completion callback, ", + thread_name, total_tests - 1); + pr_warn("but status is \'%s\'\n", + status == DMA_ERROR ? "error" : + "in progress"); + failed_tests++; + continue; + } + + /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */ + for (i = 0; i < dst_cnt; i++) + dma_unmap_single(dev->dev, dma_dsts[i], test_buf_size, + DMA_MEM_TO_MEM); + + error_count = 0; + + pr_debug("%s: verifying source buffer...\n", thread_name); + error_count += cdmatest_verify(thread->srcs, 0, src_off, + 0, PATTERN_SRC, true); + error_count += cdmatest_verify(thread->srcs, src_off, + src_off + len, src_off, + PATTERN_SRC | PATTERN_COPY, true); + error_count += cdmatest_verify(thread->srcs, src_off + len, + test_buf_size, src_off + len, + PATTERN_SRC, true); + + pr_debug("%s: verifying dest buffer...\n", + thread->task->comm); + error_count += cdmatest_verify(thread->dsts, 0, dst_off, + 0, PATTERN_DST, false); + error_count += cdmatest_verify(thread->dsts, dst_off, + dst_off + len, src_off, + PATTERN_SRC | PATTERN_COPY, false); + error_count += cdmatest_verify(thread->dsts, dst_off + len, + test_buf_size, dst_off + len, + PATTERN_DST, false); + + if (error_count) { + pr_warn("%s: #%u: %u errors with ", + thread_name, total_tests - 1, error_count); + pr_warn("src_off=0x%x dst_off=0x%x len=0x%x\n", + src_off, dst_off, len); + failed_tests++; + } else { + pr_debug("%s: #%u: No errors with ", + thread_name, total_tests - 1); + pr_debug("src_off=0x%x dst_off=0x%x len=0x%x\n", + src_off, dst_off, len); + } + } + + ret = 0; + for (i = 0; thread->dsts[i]; i++) + kfree(thread->dsts[i]); +err_dstbuf: + kfree(thread->dsts); +err_dsts: + for (i = 0; thread->srcs[i]; i++) + kfree(thread->srcs[i]); +err_srcbuf: + kfree(thread->srcs); +err_srcs: + pr_notice("%s: terminating after %u tests, %u failures (status %d)\n", + thread_name, total_tests, failed_tests, ret); + + if (iterations > 0) + while (!kthread_should_stop()) { + DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_cdmatest_exit); + interruptible_sleep_on(&wait_cdmatest_exit); + } + + return ret; +} + +static void cdmatest_cleanup_channel(struct cdmatest_chan *dtc) +{ + struct cdmatest_thread *thread; + struct cdmatest_thread *_thread; + int ret; + + list_for_each_entry_safe(thread, _thread, &dtc->threads, node) { + ret = kthread_stop(thread->task); + pr_debug("cdmatest: thread %s exited with status %d\n", + thread->task->comm, ret); + list_del(&thread->node); + kfree(thread); + } + kfree(dtc); +} + +static int cdmatest_add_threads(struct cdmatest_chan *dtc, + enum dma_transaction_type type) +{ + struct cdmatest_thread *thread; + struct dma_chan *chan = dtc->chan; + char *op; + unsigned int i; + + if (type == DMA_MEMCPY) + op = "copy"; + else if (type == DMA_XOR) + op = "xor"; + else if (type == DMA_PQ) + op = "pq"; + else + return -EINVAL; + + for (i = 0; i < threads_per_chan; i++) { + thread = kzalloc(sizeof(struct cdmatest_thread), GFP_KERNEL); + if (!thread) { + pr_warn("cdmatest: No memory for %s-%s%u\n", + dma_chan_name(chan), op, i); + + break; + } + thread->chan = dtc->chan; + thread->type = type; + smp_wmb(); + thread->task = kthread_run(cdmatest_func, thread, "%s-%s%u", + dma_chan_name(chan), op, i); + if (IS_ERR(thread->task)) { + pr_warn("cdmatest: Failed to run thread %s-%s%u\n", + dma_chan_name(chan), op, i); + kfree(thread); + break; + } + + /* srcbuf and dstbuf are allocated by the thread itself */ + + list_add_tail(&thread->node, &dtc->threads); + } + + return i; +} + +static int cdmatest_add_channel(struct dma_chan *chan) +{ + struct cdmatest_chan *dtc; + struct dma_device *dma_dev = chan->device; + unsigned int thread_count = 0; + int cnt; + + dtc = kmalloc(sizeof(struct cdmatest_chan), GFP_KERNEL); + if (!dtc) { + pr_warn("cdmatest: No memory for %s\n", dma_chan_name(chan)); + return -ENOMEM; + } + + dtc->chan = chan; + INIT_LIST_HEAD(&dtc->threads); + + if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { + cnt = cdmatest_add_threads(dtc, DMA_MEMCPY); + thread_count += cnt > 0 ? cnt : 0; + } + if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { + cnt = cdmatest_add_threads(dtc, DMA_XOR); + thread_count += cnt > 0 ? cnt : 0; + } + if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { + cnt = cdmatest_add_threads(dtc, DMA_PQ); + thread_count += cnt > 0 ? cnt : 0; + } + + pr_info("cdmatest: Started %u threads using %s\n", + thread_count, dma_chan_name(chan)); + + list_add_tail(&dtc->node, &cdmatest_channels); + nr_channels++; + + return 0; +} + +static bool filter(struct dma_chan *chan, void *param) +{ + if (!cdmatest_match_channel(chan) || + !cdmatest_match_device(chan->device)) + return false; + + return true; +} + +static int __init cdmatest_init(void) +{ + dma_cap_mask_t mask; + struct dma_chan *chan; + int err = 0; + + dma_cap_zero(mask); + dma_cap_set(DMA_MEMCPY, mask); + for (;;) { + chan = dma_request_channel(mask, filter, NULL); + + if (chan) { + err = cdmatest_add_channel(chan); + if (err) { + dma_release_channel(chan); + break; /* add_channel failed, punt */ + } + } else + break; /* no more channels available */ + if (max_channels && nr_channels >= max_channels) + break; /* we have all we need */ + } + + return err; +} +/* when compiled-in wait for drivers to load first */ +late_initcall(cdmatest_init); + +static void __exit cdmatest_exit(void) +{ + struct cdmatest_chan *dtc, *_dtc; + struct dma_chan *chan; + + list_for_each_entry_safe(dtc, _dtc, &cdmatest_channels, node) { + list_del(&dtc->node); + chan = dtc->chan; + cdmatest_cleanup_channel(dtc); + pr_debug("cdmatest: dropped channel %s\n", + dma_chan_name(chan)); + dma_release_channel(chan); + } +} +module_exit(cdmatest_exit); + +MODULE_AUTHOR("Xilinx, Inc."); +MODULE_DESCRIPTION("Xilinx AXI CDMA Test Client"); +MODULE_LICENSE("GPL v2"); Index: linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/Kconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/Kconfig 2014-07-20 22:06:35.748315747 +0200 @@ -0,0 +1,53 @@ +# +# XILINX DMA Engines configuration +# + +menuconfig XILINX_DMA_ENGINES + bool "Xilinx DMA Engines" + help + Enable support for the Xilinx DMA controllers. It supports three DMA + engines: Axi Central DMA (memory to memory transfer), Axi DMA (memory and + device transfer), and Axi VDMA (memory and video device transfer). + +if XILINX_DMA_ENGINES + +config XILINX_AXIDMA + tristate "Xilinx AXI DMA Engine" + select DMA_ENGINE + help + Enable support for Xilinx Axi DMA (memory and device transfer). + +config XILINX_DMATEST + tristate "DMA Test client for AXI DMA" + depends on XILINX_AXIDMA + help + Simple DMA test client. Say N unless you're debugging a + DMA Device driver. + +config XILINX_AXIVDMA + tristate "Xilinx AXI VDMA Engine" + select DMA_ENGINE + help + Enable support for Xilinx Axi VDMA (memory and video device transfer). + +config XILINX_VDMATEST + tristate "DMA Test client for VDMA" + depends on XILINX_AXIVDMA + help + Simple DMA test client. Say N unless you're debugging a + DMA Device driver. + +config XILINX_AXICDMA + tristate "Xilinx AXI CDMA Engine" + select DMA_ENGINE + help + Enable support for Xilinx Axi Central DMA (memory to memory transfer). + +config XILINX_CDMATEST + tristate "DMA Test client for CDMA" + depends on XILINX_AXICDMA + help + Simple DMA test client. Say N unless you're debugging a + DMA Device driver. + +endif # XILINX_DMA_ENGINES Index: linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/Makefile =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/Makefile 2014-07-20 22:06:35.753315664 +0200 @@ -0,0 +1,6 @@ +obj-$(CONFIG_XILINX_AXIDMA) += xilinx_axidma.o +obj-$(CONFIG_XILINX_DMATEST) += axidmatest.o +obj-$(CONFIG_XILINX_AXIVDMA) += xilinx_axivdma.o +obj-$(CONFIG_XILINX_VDMATEST) += vdmatest.o +obj-$(CONFIG_XILINX_AXICDMA) += xilinx_axicdma.o +obj-$(CONFIG_XILINX_CDMATEST) += cdmatest.o Index: linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/vdmatest.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/vdmatest.c 2014-07-20 22:06:35.767315433 +0200 @@ -0,0 +1,630 @@ +/* + * XILINX VDMA Engine test client driver + * + * Copyright (C) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Based on Atmel DMA Test Client + * + * Description: + * This is a simple Xilinx VDMA test client for AXI VDMA driver. + * This test assumes both the channels of VDMA are enabled in the + * hardware design and configured in back-to-back connection. Test + * starts by pumping the data onto one channel (MM2S) and then + * compares the data that is received on the other channel (S2MM). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned int test_buf_size = 64; +module_param(test_buf_size, uint, S_IRUGO); +MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer"); + +static unsigned int iterations; +module_param(iterations, uint, S_IRUGO); +MODULE_PARM_DESC(iterations, + "Iterations before stopping test (default: infinite)"); + +/* + * Initialization patterns. All bytes in the source buffer has bit 7 + * set, all bytes in the destination buffer has bit 7 cleared. + * + * Bit 6 is set for all bytes which are to be copied by the DMA + * engine. Bit 5 is set for all bytes which are to be overwritten by + * the DMA engine. + * + * The remaining bits are the inverse of a counter which increments by + * one for each byte address. + */ +#define PATTERN_SRC 0x80 +#define PATTERN_DST 0x00 +#define PATTERN_COPY 0x40 +#define PATTERN_OVERWRITE 0x20 +#define PATTERN_COUNT_MASK 0x1f + +/* Maximum number of frame buffers */ +#define MAX_NUM_FRAMES 32 + +/** + * struct vdmatest_slave_thread - VDMA test thread + * @node: Thread node + * @task: Task structure pointer + * @tx_chan: Tx channel pointer + * @rx_chan: Rx Channel pointer + * @srcs: Source buffer + * @dsts: Destination buffer + * @type: DMA transaction type + */ +struct xilinx_vdmatest_slave_thread { + struct list_head node; + struct task_struct *task; + struct dma_chan *tx_chan; + struct dma_chan *rx_chan; + u8 **srcs; + u8 **dsts; + enum dma_transaction_type type; +}; + +/** + * struct vdmatest_chan - VDMA Test channel + * @node: Channel node + * @chan: DMA channel pointer + * @threads: List of VDMA test threads + */ +struct xilinx_vdmatest_chan { + struct list_head node; + struct dma_chan *chan; + struct list_head threads; +}; + +/* Global variables */ +static LIST_HEAD(xilinx_vdmatest_channels); +static unsigned int nr_channels; +static unsigned int frm_cnt; +static dma_addr_t dma_srcs[MAX_NUM_FRAMES]; +static dma_addr_t dma_dsts[MAX_NUM_FRAMES]; +static struct scatterlist tx_sg[MAX_NUM_FRAMES]; +static struct scatterlist rx_sg[MAX_NUM_FRAMES]; + +static void xilinx_vdmatest_init_srcs(u8 **bufs, unsigned int start, + unsigned int len) +{ + unsigned int i; + u8 *buf; + + for (; (buf = *bufs); bufs++) { + for (i = 0; i < start; i++) + buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK); + for (; i < start + len; i++) + buf[i] = PATTERN_SRC | PATTERN_COPY + | (~i & PATTERN_COUNT_MASK); + for (; i < test_buf_size; i++) + buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK); + buf++; + } +} + +static void xilinx_vdmatest_init_dsts(u8 **bufs, unsigned int start, + unsigned int len) +{ + unsigned int i; + u8 *buf; + + for (; (buf = *bufs); bufs++) { + for (i = 0; i < start; i++) + buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK); + for (; i < start + len; i++) + buf[i] = PATTERN_DST | PATTERN_OVERWRITE + | (~i & PATTERN_COUNT_MASK); + for (; i < test_buf_size; i++) + buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK); + } +} + +static void xilinx_vdmatest_mismatch(u8 actual, u8 pattern, unsigned int index, + unsigned int counter, bool is_srcbuf) +{ + u8 diff = actual ^ pattern; + u8 expected = pattern | (~counter & PATTERN_COUNT_MASK); + const char *thread_name = current->comm; + + if (is_srcbuf) + pr_warn( + "%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n", + thread_name, index, expected, actual); + else if ((pattern & PATTERN_COPY) + && (diff & (PATTERN_COPY | PATTERN_OVERWRITE))) + pr_warn( + "%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n", + thread_name, index, expected, actual); + else if (diff & PATTERN_SRC) + pr_warn( + "%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n", + thread_name, index, expected, actual); + else + pr_warn( + "%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n", + thread_name, index, expected, actual); +} + +static unsigned int xilinx_vdmatest_verify(u8 **bufs, unsigned int start, + unsigned int end, unsigned int counter, u8 pattern, + bool is_srcbuf) +{ + unsigned int i, error_count = 0; + u8 actual, expected, *buf; + unsigned int counter_orig = counter; + + for (; (buf = *bufs); bufs++) { + counter = counter_orig; + for (i = start; i < end; i++) { + actual = buf[i]; + expected = pattern | (~counter & PATTERN_COUNT_MASK); + if (actual != expected) { + if (error_count < 32) + xilinx_vdmatest_mismatch(actual, + pattern, i, + counter, is_srcbuf); + error_count++; + } + counter++; + } + } + + if (error_count > 32) + pr_warn("%s: %u errors suppressed\n", + current->comm, error_count - 32); + + return error_count; +} + +static void xilinx_vdmatest_slave_tx_callback(void *completion) +{ + pr_debug("Got tx callback\n"); + complete(completion); +} + +static void xilinx_vdmatest_slave_rx_callback(void *completion) +{ + pr_debug("Got rx callback\n"); + complete(completion); +} + +/* + * Function for slave transfers + * Each thread requires 2 channels, one for transmit, and one for receive + */ +static int xilinx_vdmatest_slave_func(void *data) +{ + struct xilinx_vdmatest_slave_thread *thread = data; + struct dma_chan *tx_chan, *rx_chan; + const char *thread_name; + unsigned int len, error_count; + unsigned int failed_tests = 0, total_tests = 0; + dma_cookie_t tx_cookie, rx_cookie; + enum dma_status status; + enum dma_ctrl_flags flags; + int ret = -ENOMEM, i; + int hsize = 64, vsize = 32; + struct xilinx_vdma_config config; + + thread_name = current->comm; + + /* Limit testing scope here */ + iterations = 1; + test_buf_size = hsize * vsize; + + /* This barrier ensures 'thread' is initialized and + * we get valid DMA channels + */ + smp_rmb(); + tx_chan = thread->tx_chan; + rx_chan = thread->rx_chan; + + thread->srcs = kcalloc(frm_cnt+1, sizeof(u8 *), GFP_KERNEL); + if (!thread->srcs) + goto err_srcs; + for (i = 0; i < frm_cnt; i++) { + thread->srcs[i] = kmalloc(test_buf_size, GFP_KERNEL); + if (!thread->srcs[i]) + goto err_srcbuf; + } + + thread->dsts = kcalloc(frm_cnt+1, sizeof(u8 *), GFP_KERNEL); + if (!thread->dsts) + goto err_dsts; + for (i = 0; i < frm_cnt; i++) { + thread->dsts[i] = kmalloc(test_buf_size, GFP_KERNEL); + if (!thread->dsts[i]) + goto err_dstbuf; + } + + set_user_nice(current, 10); + + flags = DMA_CTRL_ACK | DMA_COMPL_SKIP_DEST_UNMAP | DMA_PREP_INTERRUPT; + + while (!kthread_should_stop() + && !(iterations && total_tests >= iterations)) { + struct dma_device *tx_dev = tx_chan->device; + struct dma_device *rx_dev = rx_chan->device; + struct dma_async_tx_descriptor *txd = NULL; + struct dma_async_tx_descriptor *rxd = NULL; + struct completion rx_cmp, tx_cmp; + unsigned long rx_tmo = + msecs_to_jiffies(30000); /* RX takes longer */ + unsigned long tx_tmo = msecs_to_jiffies(30000); + u8 align = 0; + + total_tests++; + + /* honor larger alignment restrictions */ + align = tx_dev->copy_align; + if (rx_dev->copy_align > align) + align = rx_dev->copy_align; + + if (1 << align > test_buf_size) { + pr_err("%u-byte buffer too small for %d-byte alignment\n", + test_buf_size, 1 << align); + break; + } + + len = test_buf_size; + xilinx_vdmatest_init_srcs(thread->srcs, 0, len); + xilinx_vdmatest_init_dsts(thread->dsts, 0, len); + + sg_init_table(tx_sg, frm_cnt); + sg_init_table(rx_sg, frm_cnt); + + for (i = 0; i < frm_cnt; i++) { + u8 *buf = thread->srcs[i]; + + dma_srcs[i] = dma_map_single(tx_dev->dev, buf, len, + DMA_MEM_TO_DEV); + pr_debug("src buf %x dma %x\n", (unsigned int)buf, + (unsigned int)dma_srcs[i]); + sg_dma_address(&tx_sg[i]) = dma_srcs[i]; + sg_dma_len(&tx_sg[i]) = len; + } + + for (i = 0; i < frm_cnt; i++) { + dma_dsts[i] = dma_map_single(rx_dev->dev, + thread->dsts[i], + test_buf_size, + DMA_DEV_TO_MEM); + pr_debug("dst %x dma %x\n", + (unsigned int)thread->dsts[i], + (unsigned int)dma_dsts[i]); + sg_dma_address(&rx_sg[i]) = dma_dsts[i]; + sg_dma_len(&rx_sg[i]) = len; + } + + /* Zero out configuration */ + memset(&config, 0, sizeof(struct xilinx_vdma_config)); + + /* Set up hardware configuration information */ + config.vsize = vsize; + config.hsize = hsize; + config.stride = hsize; + config.frm_cnt_en = 1; + config.coalesc = frm_cnt * 10; + config.park = 1; + tx_dev->device_control(tx_chan, DMA_SLAVE_CONFIG, + (unsigned long)&config); + + config.park = 0; + rx_dev->device_control(rx_chan, DMA_SLAVE_CONFIG, + (unsigned long)&config); + + rxd = rx_dev->device_prep_slave_sg(rx_chan, rx_sg, frm_cnt, + DMA_DEV_TO_MEM, flags, NULL); + + txd = tx_dev->device_prep_slave_sg(tx_chan, tx_sg, frm_cnt, + DMA_MEM_TO_DEV, flags, NULL); + + if (!rxd || !txd) { + for (i = 0; i < frm_cnt; i++) + dma_unmap_single(tx_dev->dev, dma_srcs[i], len, + DMA_MEM_TO_DEV); + for (i = 0; i < frm_cnt; i++) + dma_unmap_single(rx_dev->dev, dma_dsts[i], + test_buf_size, + DMA_DEV_TO_MEM); + pr_warn("%s: #%u: prep error with len=0x%x ", + thread_name, total_tests - 1, len); + msleep(100); + failed_tests++; + continue; + } + + init_completion(&rx_cmp); + rxd->callback = xilinx_vdmatest_slave_rx_callback; + rxd->callback_param = &rx_cmp; + rx_cookie = rxd->tx_submit(rxd); + + init_completion(&tx_cmp); + txd->callback = xilinx_vdmatest_slave_tx_callback; + txd->callback_param = &tx_cmp; + tx_cookie = txd->tx_submit(txd); + + if (dma_submit_error(rx_cookie) || + dma_submit_error(tx_cookie)) { + pr_warn("%s: #%u: submit error %d/%d with len=0x%x ", + thread_name, total_tests - 1, + rx_cookie, tx_cookie, len); + msleep(100); + failed_tests++; + continue; + } + dma_async_issue_pending(tx_chan); + dma_async_issue_pending(rx_chan); + + tx_tmo = wait_for_completion_timeout(&tx_cmp, tx_tmo); + + status = dma_async_is_tx_complete(tx_chan, tx_cookie, + NULL, NULL); + + if (tx_tmo == 0) { + pr_warn("%s: #%u: tx test timed out\n", + thread_name, total_tests - 1); + failed_tests++; + continue; + } else if (status != DMA_SUCCESS) { + pr_warn( + "%s: #%u: tx got completion callback, ", + thread_name, total_tests - 1); + pr_warn("but status is \'%s\'\n", + status == DMA_ERROR ? "error" : + "in progress"); + failed_tests++; + continue; + } + + rx_tmo = wait_for_completion_timeout(&rx_cmp, rx_tmo); + status = dma_async_is_tx_complete(rx_chan, rx_cookie, + NULL, NULL); + + if (rx_tmo == 0) { + pr_warn("%s: #%u: rx test timed out\n", + thread_name, total_tests - 1); + failed_tests++; + continue; + } else if (status != DMA_SUCCESS) { + pr_warn( + "%s: #%u: rx got completion callback, ", + thread_name, total_tests - 1); + pr_warn("but status is \'%s\'\n", + status == DMA_ERROR ? "error" : + "in progress"); + failed_tests++; + continue; + } + + /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */ + for (i = 0; i < frm_cnt; i++) + dma_unmap_single(rx_dev->dev, dma_dsts[i], + test_buf_size, DMA_DEV_TO_MEM); + + error_count = 0; + + pr_debug("%s: verifying source buffer...\n", thread_name); + error_count += xilinx_vdmatest_verify(thread->srcs, 0, 0, + 0, PATTERN_SRC, true); + error_count += xilinx_vdmatest_verify(thread->srcs, 0, + len, 0, PATTERN_SRC | PATTERN_COPY, true); + error_count += xilinx_vdmatest_verify(thread->srcs, len, + test_buf_size, len, PATTERN_SRC, true); + + pr_debug("%s: verifying dest buffer...\n", + thread->task->comm); + error_count += xilinx_vdmatest_verify(thread->dsts, 0, 0, + 0, PATTERN_DST, false); + error_count += xilinx_vdmatest_verify(thread->dsts, 0, + len, 0, PATTERN_SRC | PATTERN_COPY, false); + error_count += xilinx_vdmatest_verify(thread->dsts, len, + test_buf_size, len, PATTERN_DST, false); + + if (error_count) { + pr_warn("%s: #%u: %u errors with len=0x%x\n", + thread_name, total_tests - 1, error_count, len); + failed_tests++; + } else { + pr_debug("%s: #%u: No errors with len=0x%x\n", + thread_name, total_tests - 1, len); + } + } + + ret = 0; + for (i = 0; thread->dsts[i]; i++) + kfree(thread->dsts[i]); +err_dstbuf: + kfree(thread->dsts); +err_dsts: + for (i = 0; thread->srcs[i]; i++) + kfree(thread->srcs[i]); +err_srcbuf: + kfree(thread->srcs); +err_srcs: + pr_notice("%s: terminating after %u tests, %u failures (status %d)\n", + thread_name, total_tests, failed_tests, ret); + + if (iterations > 0) + while (!kthread_should_stop()) { + DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_vdmatest_exit); + interruptible_sleep_on(&wait_vdmatest_exit); + } + + return ret; +} + +static void xilinx_vdmatest_cleanup_channel(struct xilinx_vdmatest_chan *dtc) +{ + struct xilinx_vdmatest_slave_thread *thread, *_thread; + int ret; + + list_for_each_entry_safe(thread, _thread, + &dtc->threads, node) { + ret = kthread_stop(thread->task); + pr_info("xilinx_vdmatest: thread %s exited with status %d\n", + thread->task->comm, ret); + list_del(&thread->node); + kfree(thread); + } + kfree(dtc); +} + +static int +xilinx_vdmatest_add_slave_threads(struct xilinx_vdmatest_chan *tx_dtc, + struct xilinx_vdmatest_chan *rx_dtc) +{ + struct xilinx_vdmatest_slave_thread *thread; + struct dma_chan *tx_chan = tx_dtc->chan; + struct dma_chan *rx_chan = rx_dtc->chan; + + thread = kzalloc(sizeof(struct xilinx_vdmatest_slave_thread), + GFP_KERNEL); + if (!thread) + pr_warn("xilinx_vdmatest: No memory for slave thread %s-%s\n", + dma_chan_name(tx_chan), dma_chan_name(rx_chan)); + + thread->tx_chan = tx_chan; + thread->rx_chan = rx_chan; + thread->type = (enum dma_transaction_type)DMA_SLAVE; + + /* This barrier ensures the DMA channels in the 'thread' + * are initialized + */ + smp_wmb(); + thread->task = kthread_run(xilinx_vdmatest_slave_func, thread, "%s-%s", + dma_chan_name(tx_chan), dma_chan_name(rx_chan)); + if (IS_ERR(thread->task)) { + pr_warn("xilinx_vdmatest: Failed to run thread %s-%s\n", + dma_chan_name(tx_chan), dma_chan_name(rx_chan)); + kfree(thread); + } + + list_add_tail(&thread->node, &tx_dtc->threads); + + /* Added one thread with 2 channels */ + return 1; +} + +static int xilinx_vdmatest_add_slave_channels(struct dma_chan *tx_chan, + struct dma_chan *rx_chan) +{ + struct xilinx_vdmatest_chan *tx_dtc, *rx_dtc; + unsigned int thread_count = 0; + + tx_dtc = kmalloc(sizeof(struct xilinx_vdmatest_chan), GFP_KERNEL); + if (!tx_dtc) + return -ENOMEM; + + rx_dtc = kmalloc(sizeof(struct xilinx_vdmatest_chan), GFP_KERNEL); + if (!rx_dtc) + return -ENOMEM; + + tx_dtc->chan = tx_chan; + rx_dtc->chan = rx_chan; + INIT_LIST_HEAD(&tx_dtc->threads); + INIT_LIST_HEAD(&rx_dtc->threads); + + xilinx_vdmatest_add_slave_threads(tx_dtc, rx_dtc); + thread_count += 1; + + pr_info("xilinx_vdmatest: Started %u threads using %s %s\n", + thread_count, dma_chan_name(tx_chan), dma_chan_name(rx_chan)); + + list_add_tail(&tx_dtc->node, &xilinx_vdmatest_channels); + list_add_tail(&rx_dtc->node, &xilinx_vdmatest_channels); + nr_channels += 2; + + return 0; +} + +static int xilinx_vdmatest_probe(struct platform_device *pdev) +{ + struct dma_chan *chan, *rx_chan; + int err; + + err = of_property_read_u32(pdev->dev.of_node, + "xlnx,num-fstores", &frm_cnt); + if (err < 0) { + pr_err("xilinx_vdmatest: missing xlnx,num-fstores property\n"); + return err; + } + + chan = dma_request_slave_channel(&pdev->dev, "vdma0"); + if (IS_ERR(chan)) { + pr_err("xilinx_vdmatest: No Tx channel\n"); + return PTR_ERR(chan); + } + + rx_chan = dma_request_slave_channel(&pdev->dev, "vdma1"); + if (IS_ERR(rx_chan)) { + err = PTR_ERR(rx_chan); + pr_err("xilinx_vdmatest: No Rx channel\n"); + goto free_tx; + } + + err = xilinx_vdmatest_add_slave_channels(chan, rx_chan); + if (err) { + pr_err("xilinx_vdmatest: Unable to add channels\n"); + goto free_rx; + } + return 0; + +free_rx: + dma_release_channel(rx_chan); +free_tx: + dma_release_channel(chan); + + return err; +} + +static int xilinx_vdmatest_remove(struct platform_device *pdev) +{ + struct xilinx_vdmatest_chan *dtc, *_dtc; + struct dma_chan *chan; + + list_for_each_entry_safe(dtc, _dtc, &xilinx_vdmatest_channels, node) { + list_del(&dtc->node); + chan = dtc->chan; + xilinx_vdmatest_cleanup_channel(dtc); + pr_info("xilinx_vdmatest: dropped channel %s\n", + dma_chan_name(chan)); + dma_release_channel(chan); + } + return 0; +} + +static const struct of_device_id xilinx_vdmatest_of_ids[] = { + { .compatible = "xlnx,axi-vdma-test",}, + {} +}; + +static struct platform_driver xilinx_vdmatest_driver = { + .driver = { + .name = "xilinx_vdmatest", + .owner = THIS_MODULE, + .of_match_table = xilinx_vdmatest_of_ids, + }, + .probe = xilinx_vdmatest_probe, + .remove = xilinx_vdmatest_remove, +}; + +module_platform_driver(xilinx_vdmatest_driver); + +MODULE_AUTHOR("Xilinx, Inc."); +MODULE_DESCRIPTION("Xilinx AXI VDMA Test Client"); +MODULE_LICENSE("GPL v2"); Index: linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/xilinx_axicdma.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/xilinx_axicdma.c 2014-07-20 22:06:35.781315202 +0200 @@ -0,0 +1,1010 @@ +/* + * Xilinx Central DMA Engine support + * + * Copyright (C) 2010 - 2013 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * . Axi CDMA engine, it does transfers between memory and memory + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Hw specific definitions */ +#define XILINX_CDMA_MAX_TRANS_LEN 0x7FFFFF /* Max transfer length */ + +/* Register Offsets */ +#define XILINX_CDMA_CONTROL_OFFSET 0x00 /* Control Reg */ +#define XILINX_CDMA_STATUS_OFFSET 0x04 /* Status Reg */ +#define XILINX_CDMA_CDESC_OFFSET 0x08 /* Current descriptor Reg */ +#define XILINX_CDMA_TDESC_OFFSET 0x10 /* Tail descriptor Reg */ +#define XILINX_CDMA_SRCADDR_OFFSET 0x18 /* Source Address Reg */ +#define XILINX_CDMA_DSTADDR_OFFSET 0x20 /* Dest Address Reg */ +#define XILINX_CDMA_BTT_OFFSET 0x28 /* Bytes to transfer Reg */ + +/* General register bits definitions */ +#define XILINX_CDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ + +#define XILINX_CDMA_SR_IDLE_MASK 0x00000002 /* DMA channel idle */ + +#define XILINX_CDMA_XR_IRQ_IOC_MASK 0x00001000 /* Completion interrupt */ +#define XILINX_CDMA_XR_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ +#define XILINX_CDMA_XR_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */ +#define XILINX_CDMA_XR_IRQ_ALL_MASK 0x00007000 /* All interrupts */ + +#define XILINX_CDMA_XR_DELAY_MASK 0xFF000000 /* Delay timeout counter */ +#define XILINX_CDMA_XR_COALESCE_MASK 0x00FF0000 /* Coalesce counter */ + +#define XILINX_CDMA_DELAY_SHIFT 24 /* Delay counter shift */ +#define XILINX_CDMA_COALESCE_SHIFT 16 /* Coaelsce counter shift */ + +#define XILINX_CDMA_DELAY_MAX 0xFF /* Maximum delay counter value */ +/* Maximum coalescing counter value */ +#define XILINX_CDMA_COALESCE_MAX 0xFF + +#define XILINX_CDMA_CR_SGMODE_MASK 0x00000008 /* Scatter gather mode */ + +/* BD definitions for Axi Cdma */ +#define XILINX_CDMA_BD_STS_ALL_MASK 0xF0000000 + +/* Feature encodings */ +#define XILINX_CDMA_FTR_DATA_WIDTH_MASK 0x000000FF /* Data width mask, 1024 */ +#define XILINX_CDMA_FTR_HAS_SG 0x00000100 /* Has SG */ +#define XILINX_CDMA_FTR_HAS_SG_SHIFT 8 /* Has SG shift */ + +/* Delay loop counter to prevent hardware failure */ +#define XILINX_CDMA_RESET_LOOP 1000000 +#define XILINX_CDMA_HALT_LOOP 1000000 + +/* Hardware descriptor */ +struct xilinx_cdma_desc_hw { + u32 next_desc; /* 0x00 */ + u32 pad1; /* 0x04 */ + u32 src_addr; /* 0x08 */ + u32 pad2; /* 0x0C */ + u32 dest_addr; /* 0x10 */ + u32 pad3; /* 0x14 */ + u32 control; /* 0x18 */ + u32 status; /* 0x1C */ +} __aligned(64); + +/* Software descriptor */ +struct xilinx_cdma_desc_sw { + struct xilinx_cdma_desc_hw hw; + struct list_head node; + struct list_head tx_list; + struct dma_async_tx_descriptor async_tx; +} __aligned(64); + +/* Per DMA specific operations should be embedded in the channel structure */ +struct xilinx_cdma_chan { + void __iomem *regs; /* Control status registers */ + dma_cookie_t completed_cookie; /* Maximum cookie completed */ + dma_cookie_t cookie; /* The current cookie */ + spinlock_t lock; /* Descriptor operation lock */ + bool sg_waiting; /* SG transfer waiting */ + struct list_head active_list; /* Active descriptors */ + struct list_head pending_list; /* Descriptors waiting */ + struct dma_chan common; /* DMA common channel */ + struct dma_pool *desc_pool; /* Descriptors pool */ + struct device *dev; /* The dma device */ + int irq; /* Channel IRQ */ + int id; /* Channel ID */ + enum dma_transfer_direction direction; /* Transfer direction */ + int max_len; /* Max data len per transfer */ + bool is_lite; /* Whether is light build */ + bool has_sg; /* Support scatter transfers */ + bool has_dre; /* For unaligned transfers */ + int err; /* Channel has errors */ + struct tasklet_struct tasklet; /* Cleanup work after irq */ + u32 feature; /* IP feature */ + u32 private; /* Match info for + channel request */ + void (*start_transfer)(struct xilinx_cdma_chan *chan); + struct xilinx_cdma_config config; /* Device configuration info */ +}; + +struct xilinx_cdma_device { + void __iomem *regs; + struct device *dev; + struct dma_device common; + struct xilinx_cdma_chan *chan; + u32 feature; +}; + +#define to_xilinx_chan(chan) \ + container_of(chan, struct xilinx_cdma_chan, common) + +/* IO accessors */ +static inline void +cdma_write(struct xilinx_cdma_chan *chan, u32 reg, u32 val) +{ + writel(val, chan->regs + reg); +} + +static inline u32 cdma_read(struct xilinx_cdma_chan *chan, u32 reg) +{ + return readl(chan->regs + reg); +} + +/* Required functions */ + +static int xilinx_cdma_alloc_chan_resources(struct dma_chan *dchan) +{ + struct xilinx_cdma_chan *chan = to_xilinx_chan(dchan); + + /* Has this channel already been allocated? */ + if (chan->desc_pool) + return 1; + + /* + * We need the descriptor to be aligned to 64bytes + * for meeting Xilinx DMA specification requirement. + */ + chan->desc_pool = + dma_pool_create("xilinx_cdma_desc_pool", + chan->dev, + sizeof(struct xilinx_cdma_desc_sw), + __alignof__(struct xilinx_cdma_desc_sw), 0); + if (!chan->desc_pool) { + dev_err(chan->dev, + "unable to allocate channel %d descriptor pool\n", + chan->id); + return -ENOMEM; + } + + chan->completed_cookie = 1; + chan->cookie = 1; + + /* there is at least one descriptor free to be allocated */ + return 1; +} + +static void xilinx_cdma_free_desc_list(struct xilinx_cdma_chan *chan, + struct list_head *list) +{ + struct xilinx_cdma_desc_sw *desc, *_desc; + + list_for_each_entry_safe(desc, _desc, list, node) { + list_del(&desc->node); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); + } +} + +static void xilinx_cdma_free_desc_list_reverse(struct xilinx_cdma_chan *chan, + struct list_head *list) +{ + struct xilinx_cdma_desc_sw *desc, *_desc; + + list_for_each_entry_safe_reverse(desc, _desc, list, node) { + list_del(&desc->node); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); + } +} + +static void xilinx_cdma_free_chan_resources(struct dma_chan *dchan) +{ + struct xilinx_cdma_chan *chan = to_xilinx_chan(dchan); + unsigned long flags; + + dev_dbg(chan->dev, "Free all channel resources.\n"); + spin_lock_irqsave(&chan->lock, flags); + xilinx_cdma_free_desc_list(chan, &chan->active_list); + xilinx_cdma_free_desc_list(chan, &chan->pending_list); + spin_unlock_irqrestore(&chan->lock, flags); + + dma_pool_destroy(chan->desc_pool); + chan->desc_pool = NULL; +} + +static enum dma_status xilinx_cdma_desc_status(struct xilinx_cdma_chan *chan, + struct xilinx_cdma_desc_sw *desc) +{ + return dma_async_is_complete(desc->async_tx.cookie, + chan->completed_cookie, + chan->cookie); +} + +static void xilinx_cdma_chan_desc_cleanup(struct xilinx_cdma_chan *chan) +{ + struct xilinx_cdma_desc_sw *desc, *_desc; + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + + list_for_each_entry_safe(desc, _desc, &chan->active_list, node) { + dma_async_tx_callback callback; + void *callback_param; + + if (xilinx_cdma_desc_status(chan, desc) == DMA_IN_PROGRESS) + break; + + /* Remove from the list of running transactions */ + list_del(&desc->node); + + /* Run the link descriptor callback function */ + callback = desc->async_tx.callback; + callback_param = desc->async_tx.callback_param; + if (callback) { + spin_unlock_irqrestore(&chan->lock, flags); + callback(callback_param); + spin_lock_irqsave(&chan->lock, flags); + } + + /* Run any dependencies, then free the descriptor */ + dma_run_dependencies(&desc->async_tx); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); + } + + spin_unlock_irqrestore(&chan->lock, flags); +} + +static enum dma_status xilinx_tx_status(struct dma_chan *dchan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct xilinx_cdma_chan *chan = to_xilinx_chan(dchan); + dma_cookie_t last_used; + dma_cookie_t last_complete; + + xilinx_cdma_chan_desc_cleanup(chan); + + last_used = dchan->cookie; + last_complete = chan->completed_cookie; + + dma_set_tx_state(txstate, last_complete, last_used, 0); + + return dma_async_is_complete(cookie, last_complete, last_used); +} + +static int cdma_is_idle(struct xilinx_cdma_chan *chan) +{ + return cdma_read(chan, XILINX_CDMA_STATUS_OFFSET) & + XILINX_CDMA_SR_IDLE_MASK; +} + +/* Only needed for Axi CDMA v2_00_a or earlier core */ +static void cdma_sg_toggle(struct xilinx_cdma_chan *chan) +{ + cdma_write(chan, XILINX_CDMA_CONTROL_OFFSET, + cdma_read(chan, XILINX_CDMA_CONTROL_OFFSET) & + ~XILINX_CDMA_CR_SGMODE_MASK); + + cdma_write(chan, XILINX_CDMA_CONTROL_OFFSET, + cdma_read(chan, XILINX_CDMA_CONTROL_OFFSET) | + XILINX_CDMA_CR_SGMODE_MASK); +} + +static void xilinx_cdma_start_transfer(struct xilinx_cdma_chan *chan) +{ + unsigned long flags; + struct xilinx_cdma_desc_sw *desch, *desct; + struct xilinx_cdma_desc_hw *hw; + + if (chan->err) + return; + + spin_lock_irqsave(&chan->lock, flags); + + if (list_empty(&chan->pending_list)) + goto out_unlock; + + /* If hardware is busy, cannot submit */ + if (!cdma_is_idle(chan)) { + dev_dbg(chan->dev, "DMA controller still busy %x\n", + cdma_read(chan, XILINX_CDMA_STATUS_OFFSET)); + goto out_unlock; + } + + /* Enable interrupts */ + cdma_write(chan, XILINX_CDMA_CONTROL_OFFSET, + cdma_read(chan, XILINX_CDMA_CONTROL_OFFSET) | + XILINX_CDMA_XR_IRQ_ALL_MASK); + + desch = list_first_entry(&chan->pending_list, + struct xilinx_cdma_desc_sw, node); + + if (chan->has_sg) { + + /* If hybrid mode, append pending list to active list */ + desct = container_of(chan->pending_list.prev, + struct xilinx_cdma_desc_sw, node); + + list_splice_tail_init(&chan->pending_list, &chan->active_list); + + /* + * If hardware is idle, then all descriptors on the active list + * are done, start new transfers + */ + cdma_sg_toggle(chan); + + cdma_write(chan, XILINX_CDMA_CDESC_OFFSET, + desch->async_tx.phys); + + /* Update tail ptr register and start the transfer */ + cdma_write(chan, XILINX_CDMA_TDESC_OFFSET, + desch->async_tx.phys); + goto out_unlock; + } + + /* In simple mode */ + list_del(&desch->node); + list_add_tail(&desch->node, &chan->active_list); + + hw = &desch->hw; + + cdma_write(chan, XILINX_CDMA_SRCADDR_OFFSET, hw->src_addr); + cdma_write(chan, XILINX_CDMA_DSTADDR_OFFSET, hw->dest_addr); + + /* Start the transfer */ + cdma_write(chan, XILINX_CDMA_BTT_OFFSET, + hw->control & XILINX_CDMA_MAX_TRANS_LEN); + +out_unlock: + spin_unlock_irqrestore(&chan->lock, flags); +} + +/* + * If sg mode, link the pending list to running list; if simple mode, get the + * head of the pending list and submit it to hw + */ +static void xilinx_cdma_issue_pending(struct dma_chan *dchan) +{ + struct xilinx_cdma_chan *chan = to_xilinx_chan(dchan); + + xilinx_cdma_start_transfer(chan); +} + +/** + * xilinx_cdma_update_completed_cookie - Update the completed cookie. + * @chan : xilinx DMA channel + * + * CONTEXT: hardirq + */ +static void xilinx_cdma_update_completed_cookie(struct xilinx_cdma_chan *chan) +{ + struct xilinx_cdma_desc_sw *desc = NULL; + struct xilinx_cdma_desc_hw *hw = NULL; + unsigned long flags; + dma_cookie_t cookie = -EBUSY; + int done = 0; + + spin_lock_irqsave(&chan->lock, flags); + + if (list_empty(&chan->active_list)) { + dev_dbg(chan->dev, "no running descriptors\n"); + goto out_unlock; + } + + /* Get the last completed descriptor, update the cookie to that */ + list_for_each_entry(desc, &chan->active_list, node) { + if (chan->has_sg) { + hw = &desc->hw; + + /* If a BD has no status bits set, hw has it */ + if (!(hw->status & XILINX_CDMA_BD_STS_ALL_MASK)) { + break; + } else { + done = 1; + cookie = desc->async_tx.cookie; + } + } else { + /* In non-SG mode, all active entries are done */ + done = 1; + cookie = desc->async_tx.cookie; + } + } + + if (done) + chan->completed_cookie = cookie; + +out_unlock: + spin_unlock_irqrestore(&chan->lock, flags); +} + +/* Reset hardware */ +static int cdma_reset(struct xilinx_cdma_chan *chan) +{ + int loop = XILINX_CDMA_RESET_LOOP; + u32 tmp; + + cdma_write(chan, XILINX_CDMA_CONTROL_OFFSET, + cdma_read(chan, XILINX_CDMA_CONTROL_OFFSET) | + XILINX_CDMA_CR_RESET_MASK); + + tmp = cdma_read(chan, XILINX_CDMA_CONTROL_OFFSET) & + XILINX_CDMA_CR_RESET_MASK; + + /* Wait for the hardware to finish reset */ + while (loop && tmp) { + tmp = cdma_read(chan, XILINX_CDMA_CONTROL_OFFSET) & + XILINX_CDMA_CR_RESET_MASK; + loop -= 1; + } + + if (!loop) { + dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", + cdma_read(chan, XILINX_CDMA_CONTROL_OFFSET), + cdma_read(chan, XILINX_CDMA_STATUS_OFFSET)); + return -EBUSY; + } + + /* For Axi CDMA, always do sg transfers if sg mode is built in */ + if (chan->has_sg) + cdma_write(chan, XILINX_CDMA_CONTROL_OFFSET, + tmp | XILINX_CDMA_CR_SGMODE_MASK); + + return 0; +} + + +static irqreturn_t cdma_intr_handler(int irq, void *data) +{ + struct xilinx_cdma_chan *chan = data; + int update_cookie = 0; + int to_transfer = 0; + u32 stat, reg; + + reg = cdma_read(chan, XILINX_CDMA_CONTROL_OFFSET); + + /* Disable intr */ + cdma_write(chan, XILINX_CDMA_CONTROL_OFFSET, + reg & ~XILINX_CDMA_XR_IRQ_ALL_MASK); + + stat = cdma_read(chan, XILINX_CDMA_STATUS_OFFSET); + if (!(stat & XILINX_CDMA_XR_IRQ_ALL_MASK)) + return IRQ_NONE; + + /* Ack the interrupts */ + cdma_write(chan, XILINX_CDMA_STATUS_OFFSET, + XILINX_CDMA_XR_IRQ_ALL_MASK); + + /* Check for only the interrupts which are enabled */ + stat &= (reg & XILINX_CDMA_XR_IRQ_ALL_MASK); + + if (stat & XILINX_CDMA_XR_IRQ_ERROR_MASK) { + dev_err(chan->dev, + "Channel %x has errors %x, cdr %x tdr %x\n", + (u32)chan, + (u32)cdma_read(chan, XILINX_CDMA_STATUS_OFFSET), + (u32)cdma_read(chan, XILINX_CDMA_CDESC_OFFSET), + (u32)cdma_read(chan, XILINX_CDMA_TDESC_OFFSET)); + chan->err = 1; + } + + /* + * Device takes too long to do the transfer when user requires + * responsiveness + */ + if (stat & XILINX_CDMA_XR_IRQ_DELAY_MASK) + dev_dbg(chan->dev, "Inter-packet latency too long\n"); + + if (stat & XILINX_CDMA_XR_IRQ_IOC_MASK) { + update_cookie = 1; + to_transfer = 1; + } + + if (update_cookie) + xilinx_cdma_update_completed_cookie(chan); + + if (to_transfer) + chan->start_transfer(chan); + + tasklet_schedule(&chan->tasklet); + return IRQ_HANDLED; +} + +static void cdma_do_tasklet(unsigned long data) +{ + struct xilinx_cdma_chan *chan = (struct xilinx_cdma_chan *)data; + + xilinx_cdma_chan_desc_cleanup(chan); +} + +/* Append the descriptor list to the pending list */ +static void append_desc_queue(struct xilinx_cdma_chan *chan, + struct xilinx_cdma_desc_sw *desc) +{ + struct xilinx_cdma_desc_sw *tail = + container_of(chan->pending_list.prev, + struct xilinx_cdma_desc_sw, node); + struct xilinx_cdma_desc_hw *hw; + + if (list_empty(&chan->pending_list)) + goto out_splice; + + /* + * Add the hardware descriptor to the chain of hardware descriptors + * that already exists in memory. + */ + hw = &(tail->hw); + hw->next_desc = (u32)desc->async_tx.phys; + + /* + * Add the software descriptor and all children to the list + * of pending transactions + */ +out_splice: + list_splice_tail_init(&desc->tx_list, &chan->pending_list); +} + +/* + * Assign cookie to each descriptor, and append the descriptors to the pending + * list + */ +static dma_cookie_t xilinx_cdma_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct xilinx_cdma_chan *chan = to_xilinx_chan(tx->chan); + struct xilinx_cdma_desc_sw *desc = + container_of(tx, struct xilinx_cdma_desc_sw, async_tx); + struct xilinx_cdma_desc_sw *child; + unsigned long flags; + dma_cookie_t cookie = -EBUSY; + + if (chan->err) { + /* + * If reset fails, need to hard reset the system. + * Channel is no longer functional + */ + if (!cdma_reset(chan)) + chan->err = 0; + else + return cookie; + } + + spin_lock_irqsave(&chan->lock, flags); + + /* + * assign cookies to all of the software descriptors + * that make up this transaction + */ + cookie = chan->cookie; + list_for_each_entry(child, &desc->tx_list, node) { + cookie++; + if (cookie < 0) + cookie = DMA_MIN_COOKIE; + + child->async_tx.cookie = cookie; + } + + chan->cookie = cookie; + + /* put this transaction onto the tail of the pending queue */ + append_desc_queue(chan, desc); + + spin_unlock_irqrestore(&chan->lock, flags); + + return cookie; +} + +static struct xilinx_cdma_desc_sw *xilinx_cdma_alloc_descriptor( + struct xilinx_cdma_chan *chan) +{ + struct xilinx_cdma_desc_sw *desc; + dma_addr_t pdesc; + + desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); + if (!desc) { + dev_dbg(chan->dev, "out of memory for desc\n"); + return NULL; + } + + memset(desc, 0, sizeof(*desc)); + INIT_LIST_HEAD(&desc->tx_list); + dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); + desc->async_tx.tx_submit = xilinx_cdma_tx_submit; + desc->async_tx.phys = pdesc; + + return desc; +} + +/** + * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction + * @dchan: DMA channel + * @dma_dst: destination address + * @dma_src: source address + * @len: transfer length + * @flags: transfer ack flags + */ +static struct dma_async_tx_descriptor *xilinx_cdma_prep_memcpy( + struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, + size_t len, unsigned long flags) +{ + struct xilinx_cdma_chan *chan; + struct xilinx_cdma_desc_sw *first = NULL, *prev = NULL, *new; + struct xilinx_cdma_desc_hw *hw, *prev_hw; + size_t copy; + dma_addr_t src = dma_src; + dma_addr_t dst = dma_dst; + + if (!dchan) + return NULL; + + if (!len) + return NULL; + + chan = to_xilinx_chan(dchan); + + if (chan->err) { + + /* + * If reset fails, need to hard reset the system. + * Channel is no longer functional + */ + if (!cdma_reset(chan)) + chan->err = 0; + else + return NULL; + } + + /* + * If build does not have Data Realignment Engine (DRE), + * src has to be aligned + */ + if (!chan->has_dre) { + if ((dma_src & + (chan->feature & XILINX_CDMA_FTR_DATA_WIDTH_MASK)) || + (dma_dst & + (chan->feature & XILINX_CDMA_FTR_DATA_WIDTH_MASK))) { + + dev_err(chan->dev, + "Src/Dest address not aligned when no DRE\n"); + + return NULL; + } + } + + do { + /* Allocate descriptor from DMA pool */ + new = xilinx_cdma_alloc_descriptor(chan); + if (!new) { + dev_err(chan->dev, + "No free memory for link descriptor\n"); + goto fail; + } + + copy = min_t(size_t, len, chan->max_len); + + /* if lite build, transfer cannot cross page boundary */ + if (chan->is_lite) + copy = min(copy, (size_t)(PAGE_MASK - + (src & PAGE_MASK))); + + if (!copy) { + dev_err(chan->dev, + "Got zero transfer length for %x\n", + (unsigned int)src); + goto fail; + } + + hw = &(new->hw); + hw->control = + (hw->control & ~XILINX_CDMA_MAX_TRANS_LEN) | copy; + hw->src_addr = src; + hw->dest_addr = dst; + + if (!first) + first = new; + else { + prev_hw = &(prev->hw); + prev_hw->next_desc = new->async_tx.phys; + } + + new->async_tx.cookie = 0; + async_tx_ack(&new->async_tx); + + prev = new; + len -= copy; + src += copy; + dst += copy; + + /* Insert the descriptor to the list */ + list_add_tail(&new->node, &first->tx_list); + } while (len); + + /* Link the last BD with the first BD */ + hw->next_desc = first->async_tx.phys; + + new->async_tx.flags = flags; /* client is in control of this ack */ + new->async_tx.cookie = -EBUSY; + + return &first->async_tx; + +fail: + if (!first) + return NULL; + + xilinx_cdma_free_desc_list_reverse(chan, &first->tx_list); + return NULL; +} + +/* Run-time device configuration for Axi CDMA */ +static int xilinx_cdma_device_control(struct dma_chan *dchan, + enum dma_ctrl_cmd cmd, unsigned long arg) +{ + struct xilinx_cdma_chan *chan; + unsigned long flags; + + if (!dchan) + return -EINVAL; + + chan = to_xilinx_chan(dchan); + + if (cmd == DMA_TERMINATE_ALL) { + spin_lock_irqsave(&chan->lock, flags); + + /* Remove and free all of the descriptors in the lists */ + xilinx_cdma_free_desc_list(chan, &chan->pending_list); + xilinx_cdma_free_desc_list(chan, &chan->active_list); + + spin_unlock_irqrestore(&chan->lock, flags); + return 0; + } else if (cmd == DMA_SLAVE_CONFIG) { + /* + * Configure interrupt coalescing and delay counter + * Use value XILINX_CDMA_NO_CHANGE to signal no change + */ + struct xilinx_cdma_config *cfg = + (struct xilinx_cdma_config *)arg; + u32 reg = cdma_read(chan, XILINX_CDMA_CONTROL_OFFSET); + + if (cfg->coalesc <= XILINX_CDMA_COALESCE_MAX) { + reg &= ~XILINX_CDMA_XR_COALESCE_MASK; + reg |= cfg->coalesc << XILINX_CDMA_COALESCE_SHIFT; + + chan->config.coalesc = cfg->coalesc; + } + + if (cfg->delay <= XILINX_CDMA_DELAY_MAX) { + reg &= ~XILINX_CDMA_XR_DELAY_MASK; + reg |= cfg->delay << XILINX_CDMA_DELAY_SHIFT; + chan->config.delay = cfg->delay; + } + + cdma_write(chan, XILINX_CDMA_CONTROL_OFFSET, reg); + + return 0; + } + + return -ENXIO; +} + +static void xilinx_cdma_free_channels(struct xilinx_cdma_device *xdev) +{ + + list_del(&xdev->chan->common.device_node); + tasklet_kill(&xdev->chan->tasklet); + irq_dispose_mapping(xdev->chan->irq); +} + +/* + * Probing channels + * + * . Get channel features from the device tree entry + * . Initialize special channel handling routines + */ +static int xilinx_cdma_chan_probe(struct xilinx_cdma_device *xdev, + struct device_node *node, u32 feature) +{ + struct xilinx_cdma_chan *chan; + int err; + u32 device_id, value, width = 0; + + /* alloc channel */ + chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + chan->feature = feature; + chan->max_len = XILINX_CDMA_MAX_TRANS_LEN; + + chan->has_dre = of_property_read_bool(node, "xlnx,include-dre"); + + err = of_property_read_u32(node, "xlnx,datawidth", &value); + if (err) { + dev_err(xdev->dev, "unable to read datawidth property"); + return err; + } else { + width = value >> 3; /* convert bits to bytes */ + + /* If data width is greater than 8 bytes, DRE is not in hw */ + if (width > 8) + chan->has_dre = 0; + + chan->feature |= width - 1; + } + + err = of_property_read_u32(node, "xlnx,device-id", &device_id); + if (err) { + dev_err(xdev->dev, "unable to read device id property"); + return err; + } + + chan->direction = DMA_MEM_TO_MEM; + chan->start_transfer = xilinx_cdma_start_transfer; + + chan->has_sg = (xdev->feature & XILINX_CDMA_FTR_HAS_SG) >> + XILINX_CDMA_FTR_HAS_SG_SHIFT; + + chan->is_lite = of_property_read_bool(node, "xlnx,lite-mode"); + if (chan->is_lite) { + err = of_property_read_u32(node, "xlnx,max-burst-len", &value); + if (err) { + dev_err(xdev->dev, "unable to read max burstlen property"); + return err; + } + if (value) { + if (!width) { + dev_err(xdev->dev, + "Lite mode w/o data width property\n"); + return -EPERM; + } + chan->max_len = width * value; + } + } + + chan->regs = xdev->regs; + + /* + * Used by dmatest channel matching in slave transfers + * Can change it to be a structure to have more matching information + */ + chan->private = (chan->direction & 0xFF) | XILINX_DMA_IP_CDMA | + (device_id << XILINX_DMA_DEVICE_ID_SHIFT); + chan->common.private = (void *)&(chan->private); + + if (!chan->has_dre) + xdev->common.copy_align = fls(width - 1); + + chan->dev = xdev->dev; + xdev->chan = chan; + + /* Initialize the channel */ + err = cdma_reset(chan); + if (err) { + dev_err(xdev->dev, "Reset channel failed\n"); + return err; + } + + spin_lock_init(&chan->lock); + INIT_LIST_HEAD(&chan->pending_list); + INIT_LIST_HEAD(&chan->active_list); + + chan->common.device = &xdev->common; + + /* Find the IRQ line, if it exists in the device tree */ + chan->irq = irq_of_parse_and_map(node, 0); + err = devm_request_irq(xdev->dev, chan->irq, cdma_intr_handler, + IRQF_SHARED, + "xilinx-cdma-controller", chan); + if (err) { + dev_err(xdev->dev, "unable to request IRQ\n"); + return err; + } + + tasklet_init(&chan->tasklet, cdma_do_tasklet, (unsigned long)chan); + + /* Add the channel to DMA device channel list */ + list_add_tail(&chan->common.device_node, &xdev->common.channels); + + return 0; +} + +static int xilinx_cdma_probe(struct platform_device *pdev) +{ + struct xilinx_cdma_device *xdev; + struct device_node *child, *node; + struct resource *res; + int ret; + u32 value; + + xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); + if (!xdev) + return -ENOMEM; + + xdev->dev = &(pdev->dev); + INIT_LIST_HEAD(&xdev->common.channels); + + node = pdev->dev.of_node; + + /* iomap registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + xdev->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(xdev->regs)) + return PTR_ERR(xdev->regs); + + /* Check if SG is enabled */ + value = of_property_read_bool(node, "xlnx,include-sg"); + if (value) + xdev->feature |= XILINX_CDMA_FTR_HAS_SG; + + /* Axi CDMA only does memcpy */ + dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); + xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; + + xdev->common.device_control = xilinx_cdma_device_control; + xdev->common.device_issue_pending = xilinx_cdma_issue_pending; + xdev->common.device_alloc_chan_resources = + xilinx_cdma_alloc_chan_resources; + xdev->common.device_free_chan_resources = + xilinx_cdma_free_chan_resources; + xdev->common.device_tx_status = xilinx_tx_status; + xdev->common.dev = &pdev->dev; + + platform_set_drvdata(pdev, xdev); + + for_each_child_of_node(node, child) { + ret = xilinx_cdma_chan_probe(xdev, child, xdev->feature); + if (ret) { + dev_err(&pdev->dev, "Probing channels failed\n"); + goto free_chan_resources; + } + } + + ret = dma_async_device_register(&xdev->common); + if (ret) { + dev_err(&pdev->dev, "CDMA device registration failed\n"); + goto free_chan_resources; + } + + dev_info(&pdev->dev, "Probing xilinx axi cdma engine...Successful\n"); + + return 0; + +free_chan_resources: + xilinx_cdma_free_channels(xdev); + + return ret; +} + +static int xilinx_cdma_remove(struct platform_device *pdev) +{ + struct xilinx_cdma_device *xdev; + + xdev = platform_get_drvdata(pdev); + dma_async_device_unregister(&xdev->common); + + xilinx_cdma_free_channels(xdev); + + return 0; +} + +static const struct of_device_id xilinx_cdma_of_match[] = { + { .compatible = "xlnx,axi-cdma", }, + {} +}; +MODULE_DEVICE_TABLE(of, xilinx_cdma_of_match); + +static struct platform_driver xilinx_cdma_driver = { + .driver = { + .name = "xilinx-cdma", + .owner = THIS_MODULE, + .of_match_table = xilinx_cdma_of_match, + }, + .probe = xilinx_cdma_probe, + .remove = xilinx_cdma_remove, +}; + +module_platform_driver(xilinx_cdma_driver); + +MODULE_AUTHOR("Xilinx, Inc."); +MODULE_DESCRIPTION("Xilinx CDMA driver"); +MODULE_LICENSE("GPL v2"); Index: linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/xilinx_axidma.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/xilinx_axidma.c 2014-07-20 22:06:35.799314906 +0200 @@ -0,0 +1,1109 @@ +/* + * Xilinx AXI DMA Engine support + * + * Copyright (C) 2012 - 2013 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * . Axi DMA engine, it does transfers between memory and device. It can be + * configured to have one channel or two channels. If configured as two + * channels, one is to transmit to a device and another is to receive from + * a device. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Hw specific definitions */ +#define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2 /* Max no of channels */ +#define XILINX_DMA_MAX_TRANS_LEN 0x7FFFFF /* Max transfer length */ + +/* Register Offsets */ +#define XILINX_DMA_CONTROL_OFFSET 0x00 /* Control Reg */ +#define XILINX_DMA_STATUS_OFFSET 0x04 /* Status Reg */ +#define XILINX_DMA_CDESC_OFFSET 0x08 /* Current descriptor Reg */ +#define XILINX_DMA_TDESC_OFFSET 0x10 /* Tail descriptor Reg */ +#define XILINX_DMA_SRCADDR_OFFSET 0x18 /* Source Address Reg */ +#define XILINX_DMA_DSTADDR_OFFSET 0x20 /* Dest Address Reg */ +#define XILINX_DMA_BTT_OFFSET 0x28 /* Bytes to transfer Reg */ + +/* General register bits definitions */ +#define XILINX_DMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ +#define XILINX_DMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA engine */ + +#define XILINX_DMA_SR_HALTED_MASK 0x00000001 /* DMA channel halted */ +#define XILINX_DMA_SR_IDLE_MASK 0x00000002 /* DMA channel idle */ + +#define XILINX_DMA_XR_IRQ_IOC_MASK 0x00001000 /* Completion interrupt */ +#define XILINX_DMA_XR_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ +#define XILINX_DMA_XR_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */ +#define XILINX_DMA_XR_IRQ_ALL_MASK 0x00007000 /* All interrupts */ + +#define XILINX_DMA_XR_DELAY_MASK 0xFF000000 /* Delay timeout counter */ +#define XILINX_DMA_XR_COALESCE_MASK 0x00FF0000 /* Coalesce counter */ + +#define XILINX_DMA_DELAY_SHIFT 24 /* Delay timeout counter shift */ +#define XILINX_DMA_COALESCE_SHIFT 16 /* Coalesce counter shift */ + +#define XILINX_DMA_DELAY_MAX 0xFF /* Maximum delay counter value */ +#define XILINX_DMA_COALESCE_MAX 0xFF /* Max coalescing counter value */ + +#define XILINX_DMA_RX_CHANNEL_OFFSET 0x30 /* S2MM Channel Offset */ + +/* BD definitions for AXI Dma */ +#define XILINX_DMA_BD_STS_ALL_MASK 0xF0000000 +#define XILINX_DMA_BD_SOP 0x08000000 /* Start of packet bit */ +#define XILINX_DMA_BD_EOP 0x04000000 /* End of packet bit */ + +/* Feature encodings */ +#define XILINX_DMA_FTR_HAS_SG 0x00000100 /* Has SG */ +#define XILINX_DMA_FTR_HAS_SG_SHIFT 8 /* Has SG shift */ +/* Optional feature for dma */ +#define XILINX_DMA_FTR_STSCNTRL_STRM 0x00010000 + + +/* Delay loop counter to prevent hardware failure */ +#define XILINX_DMA_RESET_LOOP 1000000 +#define XILINX_DMA_HALT_LOOP 1000000 + +#if defined(CONFIG_XILINX_DMATEST) || defined(CONFIG_XILINX_DMATEST_MODULE) +# define TEST_DMA_WITH_LOOPBACK +#endif + +/* Hardware descriptor */ +struct xilinx_dma_desc_hw { + u32 next_desc; /* 0x00 */ + u32 pad1; /* 0x04 */ + u32 buf_addr; /* 0x08 */ + u32 pad2; /* 0x0C */ + u32 pad3; /* 0x10 */ + u32 pad4; /* 0x14 */ + u32 control; /* 0x18 */ + u32 status; /* 0x1C */ + u32 app_0; /* 0x20 */ + u32 app_1; /* 0x24 */ + u32 app_2; /* 0x28 */ + u32 app_3; /* 0x2C */ + u32 app_4; /* 0x30 */ +} __aligned(64); + +/* Software descriptor */ +struct xilinx_dma_desc_sw { + struct xilinx_dma_desc_hw hw; + struct list_head node; + struct list_head tx_list; + struct dma_async_tx_descriptor async_tx; +} __aligned(64); + +/* Per DMA specific operations should be embedded in the channel structure */ +struct xilinx_dma_chan { + void __iomem *regs; /* Control status registers */ + dma_cookie_t completed_cookie; /* The maximum cookie completed */ + dma_cookie_t cookie; /* The current cookie */ + spinlock_t lock; /* Descriptor operation lock */ + bool sg_waiting; /* Scatter gather transfer waiting */ + struct list_head active_list; /* Active descriptors */ + struct list_head pending_list; /* Descriptors waiting */ + struct dma_chan common; /* DMA common channel */ + struct dma_pool *desc_pool; /* Descriptors pool */ + struct device *dev; /* The dma device */ + int irq; /* Channel IRQ */ + int id; /* Channel ID */ + enum dma_transfer_direction direction; + /* Transfer direction */ + int max_len; /* Maximum data len per transfer */ + bool has_sg; /* Support scatter transfers */ + bool has_dre; /* Support unaligned transfers */ + int err; /* Channel has errors */ + struct tasklet_struct tasklet; /* Cleanup work after irq */ + u32 feature; /* IP feature */ + u32 private; /* Match info for channel request */ + void (*start_transfer)(struct xilinx_dma_chan *chan); + struct xilinx_dma_config config; + /* Device configuration info */ +}; + +/* DMA Device Structure */ +struct xilinx_dma_device { + void __iomem *regs; + struct device *dev; + struct dma_device common; + struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE]; + u32 feature; +}; + +#define to_xilinx_chan(chan) \ + container_of(chan, struct xilinx_dma_chan, common) + +/* IO accessors */ +static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 val) +{ + writel(val, chan->regs + reg); +} + +static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) +{ + return readl(chan->regs + reg); +} + +static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) +{ + struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); + + /* Has this channel already been allocated? */ + if (chan->desc_pool) + return 1; + + /* + * We need the descriptor to be aligned to 64bytes + * for meeting Xilinx DMA specification requirement. + */ + chan->desc_pool = + dma_pool_create("xilinx_dma_desc_pool", chan->dev, + sizeof(struct xilinx_dma_desc_sw), + __alignof__(struct xilinx_dma_desc_sw), 0); + if (!chan->desc_pool) { + dev_err(chan->dev, + "unable to allocate channel %d descriptor pool\n", + chan->id); + return -ENOMEM; + } + + chan->completed_cookie = 1; + chan->cookie = 1; + + /* There is at least one descriptor free to be allocated */ + return 1; +} + +static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan, + struct list_head *list) +{ + struct xilinx_dma_desc_sw *desc, *_desc; + + list_for_each_entry_safe(desc, _desc, list, node) { + list_del(&desc->node); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); + } +} + +static void xilinx_dma_free_desc_list_reverse(struct xilinx_dma_chan *chan, + struct list_head *list) +{ + struct xilinx_dma_desc_sw *desc, *_desc; + + list_for_each_entry_safe_reverse(desc, _desc, list, node) { + list_del(&desc->node); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); + } +} + +static void xilinx_dma_free_chan_resources(struct dma_chan *dchan) +{ + struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); + unsigned long flags; + + dev_dbg(chan->dev, "Free all channel resources.\n"); + spin_lock_irqsave(&chan->lock, flags); + xilinx_dma_free_desc_list(chan, &chan->active_list); + xilinx_dma_free_desc_list(chan, &chan->pending_list); + spin_unlock_irqrestore(&chan->lock, flags); + + dma_pool_destroy(chan->desc_pool); + chan->desc_pool = NULL; +} + +static enum dma_status xilinx_dma_desc_status(struct xilinx_dma_chan *chan, + struct xilinx_dma_desc_sw *desc) +{ + return dma_async_is_complete(desc->async_tx.cookie, + chan->completed_cookie, + chan->cookie); +} + +static void xilinx_chan_desc_cleanup(struct xilinx_dma_chan *chan) +{ + struct xilinx_dma_desc_sw *desc, *_desc; + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + + list_for_each_entry_safe(desc, _desc, &chan->active_list, node) { + dma_async_tx_callback callback; + void *callback_param; + + if (xilinx_dma_desc_status(chan, desc) == DMA_IN_PROGRESS) + break; + + /* Remove from the list of running transactions */ + list_del(&desc->node); + + /* Run the link descriptor callback function */ + callback = desc->async_tx.callback; + callback_param = desc->async_tx.callback_param; + if (callback) { + spin_unlock_irqrestore(&chan->lock, flags); + callback(callback_param); + spin_lock_irqsave(&chan->lock, flags); + } + + /* Run any dependencies, then free the descriptor */ + dma_run_dependencies(&desc->async_tx); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); + } + + spin_unlock_irqrestore(&chan->lock, flags); +} + +static enum dma_status xilinx_tx_status(struct dma_chan *dchan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); + dma_cookie_t last_used; + dma_cookie_t last_complete; + + xilinx_chan_desc_cleanup(chan); + + last_used = dchan->cookie; + last_complete = chan->completed_cookie; + + dma_set_tx_state(txstate, last_complete, last_used, 0); + + return dma_async_is_complete(cookie, last_complete, last_used); +} + +static int dma_is_running(struct xilinx_dma_chan *chan) +{ + return !(dma_read(chan, XILINX_DMA_STATUS_OFFSET) & + XILINX_DMA_SR_HALTED_MASK) && + (dma_read(chan, XILINX_DMA_CONTROL_OFFSET) & + XILINX_DMA_CR_RUNSTOP_MASK); +} + +static int dma_is_idle(struct xilinx_dma_chan *chan) +{ + return dma_read(chan, XILINX_DMA_STATUS_OFFSET) & + XILINX_DMA_SR_IDLE_MASK; +} + +/* Stop the hardware, the ongoing transfer will be finished */ +static void dma_halt(struct xilinx_dma_chan *chan) +{ + int loop = XILINX_DMA_HALT_LOOP; + + dma_write(chan, XILINX_DMA_CONTROL_OFFSET, + dma_read(chan, XILINX_DMA_CONTROL_OFFSET) & + ~XILINX_DMA_CR_RUNSTOP_MASK); + + /* Wait for the hardware to halt */ + while (loop) { + if (!(dma_read(chan, XILINX_DMA_CONTROL_OFFSET) & + XILINX_DMA_CR_RUNSTOP_MASK)) + break; + + loop -= 1; + } + + if (!loop) { + pr_debug("Cannot stop channel %x: %x\n", + (unsigned int)chan, + (unsigned int)dma_read(chan, + XILINX_DMA_CONTROL_OFFSET)); + chan->err = 1; + } +} + +/* Start the hardware. Transfers are not started yet */ +static void dma_start(struct xilinx_dma_chan *chan) +{ + int loop = XILINX_DMA_HALT_LOOP; + + dma_write(chan, XILINX_DMA_CONTROL_OFFSET, + dma_read(chan, XILINX_DMA_CONTROL_OFFSET) | + XILINX_DMA_CR_RUNSTOP_MASK); + + /* Wait for the hardware to start */ + while (loop) { + if (dma_read(chan, XILINX_DMA_CONTROL_OFFSET) & + XILINX_DMA_CR_RUNSTOP_MASK) + break; + + loop -= 1; + } + + if (!loop) { + pr_debug("Cannot start channel %x: %x\n", + (unsigned int)chan, + (unsigned int)dma_read(chan, + XILINX_DMA_CONTROL_OFFSET)); + + chan->err = 1; + } +} + +static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) +{ + unsigned long flags; + struct xilinx_dma_desc_sw *desch, *desct; + struct xilinx_dma_desc_hw *hw; + + if (chan->err) + return; + + spin_lock_irqsave(&chan->lock, flags); + + if (list_empty(&chan->pending_list)) + goto out_unlock; + + /* If hardware is busy, cannot submit */ + if (dma_is_running(chan) && !dma_is_idle(chan)) { + dev_dbg(chan->dev, "DMA controller still busy\n"); + goto out_unlock; + } + + /* + * If hardware is idle, then all descriptors on active list are + * done, start new transfers + */ + dma_halt(chan); + + if (chan->err) + goto out_unlock; + + if (chan->has_sg) { + desch = list_first_entry(&chan->pending_list, + struct xilinx_dma_desc_sw, node); + + desct = container_of(chan->pending_list.prev, + struct xilinx_dma_desc_sw, node); + + dma_write(chan, XILINX_DMA_CDESC_OFFSET, desch->async_tx.phys); + + dma_start(chan); + + if (chan->err) + goto out_unlock; + list_splice_tail_init(&chan->pending_list, &chan->active_list); + + /* Enable interrupts */ + dma_write(chan, XILINX_DMA_CONTROL_OFFSET, + dma_read(chan, XILINX_DMA_CONTROL_OFFSET) | + XILINX_DMA_XR_IRQ_ALL_MASK); + + /* Update tail ptr register and start the transfer */ + dma_write(chan, XILINX_DMA_TDESC_OFFSET, desct->async_tx.phys); + goto out_unlock; + } + + /* In simple mode */ + dma_halt(chan); + + if (chan->err) + goto out_unlock; + + pr_info("xilinx_dma_start_transfer::simple DMA mode\n"); + + desch = list_first_entry(&chan->pending_list, + struct xilinx_dma_desc_sw, node); + + list_del(&desch->node); + list_add_tail(&desch->node, &chan->active_list); + + dma_start(chan); + + if (chan->err) + goto out_unlock; + + hw = &desch->hw; + + /* Enable interrupts */ + dma_write(chan, XILINX_DMA_CONTROL_OFFSET, + dma_read(chan, XILINX_DMA_CONTROL_OFFSET) | + XILINX_DMA_XR_IRQ_ALL_MASK); + + dma_write(chan, XILINX_DMA_SRCADDR_OFFSET, hw->buf_addr); + + /* Start the transfer */ + dma_write(chan, XILINX_DMA_BTT_OFFSET, + hw->control & XILINX_DMA_MAX_TRANS_LEN); + +out_unlock: + spin_unlock_irqrestore(&chan->lock, flags); +} + +static void xilinx_dma_issue_pending(struct dma_chan *dchan) +{ + struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); + + xilinx_dma_start_transfer(chan); +} + +/** + * xilinx_dma_update_completed_cookie - Update the completed cookie. + * @chan : xilinx DMA channel + * + * CONTEXT: hardirq + */ +static void xilinx_dma_update_completed_cookie(struct xilinx_dma_chan *chan) +{ + struct xilinx_dma_desc_sw *desc = NULL; + struct xilinx_dma_desc_hw *hw = NULL; + unsigned long flags; + dma_cookie_t cookie = -EBUSY; + int done = 0; + + spin_lock_irqsave(&chan->lock, flags); + + if (list_empty(&chan->active_list)) { + dev_dbg(chan->dev, "no running descriptors\n"); + goto out_unlock; + } + + /* Get the last completed descriptor, update the cookie to that */ + list_for_each_entry(desc, &chan->active_list, node) { + if (chan->has_sg) { + hw = &desc->hw; + + /* If a BD has no status bits set, hw has it */ + if (!(hw->status & XILINX_DMA_BD_STS_ALL_MASK)) { + break; + } else { + done = 1; + cookie = desc->async_tx.cookie; + } + } else { + /* In non-SG mode, all active entries are done */ + done = 1; + cookie = desc->async_tx.cookie; + } + } + + if (done) + chan->completed_cookie = cookie; + +out_unlock: + spin_unlock_irqrestore(&chan->lock, flags); +} + +/* Reset hardware */ +static int dma_reset(struct xilinx_dma_chan *chan) +{ + int loop = XILINX_DMA_RESET_LOOP; + u32 tmp; + + dma_write(chan, XILINX_DMA_CONTROL_OFFSET, + dma_read(chan, XILINX_DMA_CONTROL_OFFSET) | + XILINX_DMA_CR_RESET_MASK); + + tmp = dma_read(chan, XILINX_DMA_CONTROL_OFFSET) & + XILINX_DMA_CR_RESET_MASK; + + /* Wait for the hardware to finish reset */ + while (loop && tmp) { + tmp = dma_read(chan, XILINX_DMA_CONTROL_OFFSET) & + XILINX_DMA_CR_RESET_MASK; + loop -= 1; + } + + if (!loop) { + dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", + dma_read(chan, XILINX_DMA_CONTROL_OFFSET), + dma_read(chan, XILINX_DMA_STATUS_OFFSET)); + return -EBUSY; + } + + return 0; +} + +static irqreturn_t dma_intr_handler(int irq, void *data) +{ + struct xilinx_dma_chan *chan = data; + int update_cookie = 0; + int to_transfer = 0; + u32 stat, reg; + + reg = dma_read(chan, XILINX_DMA_CONTROL_OFFSET); + + /* Disable intr */ + dma_write(chan, XILINX_DMA_CONTROL_OFFSET, + reg & ~XILINX_DMA_XR_IRQ_ALL_MASK); + + stat = dma_read(chan, XILINX_DMA_STATUS_OFFSET); + if (!(stat & XILINX_DMA_XR_IRQ_ALL_MASK)) + return IRQ_NONE; + + /* Ack the interrupts */ + dma_write(chan, XILINX_DMA_STATUS_OFFSET, + XILINX_DMA_XR_IRQ_ALL_MASK); + + /* Check for only the interrupts which are enabled */ + stat &= (reg & XILINX_DMA_XR_IRQ_ALL_MASK); + + if (stat & XILINX_DMA_XR_IRQ_ERROR_MASK) { + dev_err(chan->dev, + "Channel %x has errors %x, cdr %x tdr %x\n", + (unsigned int)chan, + (unsigned int)dma_read(chan, XILINX_DMA_STATUS_OFFSET), + (unsigned int)dma_read(chan, XILINX_DMA_CDESC_OFFSET), + (unsigned int)dma_read(chan, XILINX_DMA_TDESC_OFFSET)); + chan->err = 1; + } + + /* + * Device takes too long to do the transfer when user requires + * responsiveness + */ + if (stat & XILINX_DMA_XR_IRQ_DELAY_MASK) + dev_dbg(chan->dev, "Inter-packet latency too long\n"); + + if (stat & XILINX_DMA_XR_IRQ_IOC_MASK) { + update_cookie = 1; + to_transfer = 1; + } + + if (update_cookie) + xilinx_dma_update_completed_cookie(chan); + + if (to_transfer) + chan->start_transfer(chan); + + tasklet_schedule(&chan->tasklet); + return IRQ_HANDLED; +} + +static void dma_do_tasklet(unsigned long data) +{ + struct xilinx_dma_chan *chan = (struct xilinx_dma_chan *)data; + + xilinx_chan_desc_cleanup(chan); +} + +/* Append the descriptor list to the pending list */ +static void append_desc_queue(struct xilinx_dma_chan *chan, + struct xilinx_dma_desc_sw *desc) +{ + struct xilinx_dma_desc_sw *tail = + container_of(chan->pending_list.prev, + struct xilinx_dma_desc_sw, node); + struct xilinx_dma_desc_hw *hw; + + if (list_empty(&chan->pending_list)) + goto out_splice; + + /* + * Add the hardware descriptor to the chain of hardware descriptors + * that already exists in memory. + */ + hw = &(tail->hw); + hw->next_desc = (u32)desc->async_tx.phys; + + /* + * Add the software descriptor and all children to the list + * of pending transactions + */ +out_splice: + list_splice_tail_init(&desc->tx_list, &chan->pending_list); +} + +/* + * Assign cookie to each descriptor, and append the descriptors to the pending + * list + */ +static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); + struct xilinx_dma_desc_sw *desc; + struct xilinx_dma_desc_sw *child; + unsigned long flags; + dma_cookie_t cookie = -EBUSY; + + desc = container_of(tx, struct xilinx_dma_desc_sw, async_tx); + + if (chan->err) { + /* + * If reset fails, need to hard reset the system. + * Channel is no longer functional + */ + if (!dma_reset(chan)) + chan->err = 0; + else + return cookie; + } + + spin_lock_irqsave(&chan->lock, flags); + + /* + * Assign cookies to all of the software descriptors + * that make up this transaction + */ + cookie = chan->cookie; + list_for_each_entry(child, &desc->tx_list, node) { + cookie++; + if (cookie < 0) + cookie = DMA_MIN_COOKIE; + + child->async_tx.cookie = cookie; + } + + chan->cookie = cookie; + + /* Put this transaction onto the tail of the pending queue */ + append_desc_queue(chan, desc); + + spin_unlock_irqrestore(&chan->lock, flags); + + return cookie; +} + +static struct +xilinx_dma_desc_sw *xilinx_dma_alloc_descriptor(struct xilinx_dma_chan *chan) +{ + struct xilinx_dma_desc_sw *desc; + dma_addr_t pdesc; + + desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); + if (!desc) { + dev_dbg(chan->dev, "out of memory for desc\n"); + return NULL; + } + + memset(desc, 0, sizeof(*desc)); + INIT_LIST_HEAD(&desc->tx_list); + dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); + desc->async_tx.tx_submit = xilinx_dma_tx_submit; + desc->async_tx.phys = pdesc; + + return desc; +} + +/** + * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction + * @chan: DMA channel + * @sgl: scatterlist to transfer to/from + * @sg_len: number of entries in @scatterlist + * @direction: DMA direction + * @flags: transfer ack flags + */ +static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( + struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, + enum dma_transfer_direction direction, unsigned long flags, + void *context) +{ + struct xilinx_dma_chan *chan; + struct xilinx_dma_desc_sw *first = NULL, *prev = NULL, *new = NULL; + struct xilinx_dma_desc_hw *hw = NULL, *prev_hw = NULL; + + size_t copy; + + int i; + struct scatterlist *sg; + size_t sg_used; + dma_addr_t dma_src; + +#ifdef TEST_DMA_WITH_LOOPBACK + int total_len; +#endif + if (!dchan) + return NULL; + + chan = to_xilinx_chan(dchan); + + if (chan->direction != direction) + return NULL; + +#ifdef TEST_DMA_WITH_LOOPBACK + total_len = 0; + + for_each_sg(sgl, sg, sg_len, i) { + total_len += sg_dma_len(sg); + } +#endif + /* Build transactions using information in the scatter gather list */ + for_each_sg(sgl, sg, sg_len, i) { + sg_used = 0; + + /* Loop until the entire scatterlist entry is used */ + while (sg_used < sg_dma_len(sg)) { + + /* Allocate the link descriptor from DMA pool */ + new = xilinx_dma_alloc_descriptor(chan); + if (!new) { + dev_err(chan->dev, + "No free memory for link descriptor\n"); + goto fail; + } + + /* + * Calculate the maximum number of bytes to transfer, + * making sure it is less than the hw limit + */ + copy = min((size_t)(sg_dma_len(sg) - sg_used), + (size_t)chan->max_len); + hw = &(new->hw); + + dma_src = sg_dma_address(sg) + sg_used; + + hw->buf_addr = dma_src; + + /* Fill in the descriptor */ + hw->control = copy; + + /* + * If this is not the first descriptor, chain the + * current descriptor after the previous descriptor + * + * For the first DMA_MEM_TO_DEV transfer, set SOP + */ + if (!first) { + first = new; + if (direction == DMA_MEM_TO_DEV) { + hw->control |= XILINX_DMA_BD_SOP; +#ifdef TEST_DMA_WITH_LOOPBACK + hw->app_4 = total_len; +#endif + } + } else { + prev_hw = &(prev->hw); + prev_hw->next_desc = new->async_tx.phys; + } + + new->async_tx.cookie = 0; + async_tx_ack(&new->async_tx); + + prev = new; + sg_used += copy; + + /* Insert the link descriptor into the LD ring */ + list_add_tail(&new->node, &first->tx_list); + } + } + + /* Link the last BD with the first BD */ + hw->next_desc = first->async_tx.phys; + + if (direction == DMA_MEM_TO_DEV) + hw->control |= XILINX_DMA_BD_EOP; + + /* All scatter gather list entries has length == 0 */ + if (!first || !new) + return NULL; + + new->async_tx.flags = flags; + new->async_tx.cookie = -EBUSY; + + /* Set EOP to the last link descriptor of new list */ + hw->control |= XILINX_DMA_BD_EOP; + + return &first->async_tx; + +fail: + /* + * If first was not set, then we failed to allocate the very first + * descriptor, and we're done + */ + if (!first) + return NULL; + + /* + * First is set, so all of the descriptors we allocated have been added + * to first->tx_list, INCLUDING "first" itself. Therefore we + * must traverse the list backwards freeing each descriptor in turn + */ + xilinx_dma_free_desc_list_reverse(chan, &first->tx_list); + + return NULL; +} + +/* Run-time device configuration for Axi DMA */ +static int xilinx_dma_device_control(struct dma_chan *dchan, + enum dma_ctrl_cmd cmd, unsigned long arg) +{ + struct xilinx_dma_chan *chan; + unsigned long flags; + + if (!dchan) + return -EINVAL; + + chan = to_xilinx_chan(dchan); + + if (cmd == DMA_TERMINATE_ALL) { + /* Halt the DMA engine */ + dma_halt(chan); + + spin_lock_irqsave(&chan->lock, flags); + + /* Remove and free all of the descriptors in the lists */ + xilinx_dma_free_desc_list(chan, &chan->pending_list); + xilinx_dma_free_desc_list(chan, &chan->active_list); + + spin_unlock_irqrestore(&chan->lock, flags); + return 0; + } else if (cmd == DMA_SLAVE_CONFIG) { + /* + * Configure interrupt coalescing and delay counter + * Use value XILINX_DMA_NO_CHANGE to signal no change + */ + struct xilinx_dma_config *cfg = (struct xilinx_dma_config *)arg; + u32 reg = dma_read(chan, XILINX_DMA_CONTROL_OFFSET); + + if (cfg->coalesc <= XILINX_DMA_COALESCE_MAX) { + reg &= ~XILINX_DMA_XR_COALESCE_MASK; + reg |= cfg->coalesc << XILINX_DMA_COALESCE_SHIFT; + + chan->config.coalesc = cfg->coalesc; + } + + if (cfg->delay <= XILINX_DMA_DELAY_MAX) { + reg &= ~XILINX_DMA_XR_DELAY_MASK; + reg |= cfg->delay << XILINX_DMA_DELAY_SHIFT; + chan->config.delay = cfg->delay; + } + + dma_write(chan, XILINX_DMA_CONTROL_OFFSET, reg); + + return 0; + } else + return -ENXIO; +} + +static void xilinx_dma_free_channels(struct xilinx_dma_device *xdev) +{ + int i; + + for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++) { + list_del(&xdev->chan[i]->common.device_node); + tasklet_kill(&xdev->chan[i]->tasklet); + irq_dispose_mapping(xdev->chan[i]->irq); + } +} + +/* + * Probing channels + * + * . Get channel features from the device tree entry + * . Initialize special channel handling routines + */ +static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, + struct device_node *node, u32 feature) +{ + struct xilinx_dma_chan *chan; + int err; + u32 device_id, value, width = 0; + + /* alloc channel */ + chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + chan->feature = feature; + chan->max_len = XILINX_DMA_MAX_TRANS_LEN; + + chan->has_dre = of_property_read_bool(node, "xlnx,include-dre"); + + err = of_property_read_u32(node, "xlnx,datawidth", &value); + if (err) { + dev_err(xdev->dev, "unable to read datawidth property"); + return err; + } else { + width = value >> 3; /* convert bits to bytes */ + + /* If data width is greater than 8 bytes, DRE is not in hw */ + if (width > 8) + chan->has_dre = 0; + + chan->feature |= width - 1; + } + + err = of_property_read_u32(node, "xlnx,device-id", &device_id); + if (err) { + dev_err(xdev->dev, "unable to read device id property"); + return err; + } + + chan->has_sg = (xdev->feature & XILINX_DMA_FTR_HAS_SG) >> + XILINX_DMA_FTR_HAS_SG_SHIFT; + + chan->start_transfer = xilinx_dma_start_transfer; + + if (of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel")) + chan->direction = DMA_MEM_TO_DEV; + + if (of_device_is_compatible(node, "xlnx,axi-dma-s2mm-channel")) + chan->direction = DMA_DEV_TO_MEM; + + chan->regs = xdev->regs; + + if (chan->direction == DMA_DEV_TO_MEM) { + chan->regs = (xdev->regs + XILINX_DMA_RX_CHANNEL_OFFSET); + chan->id = 1; + } + + /* + * Used by dmatest channel matching in slave transfers + * Can change it to be a structure to have more matching information + */ + chan->private = (chan->direction & 0xFF) | XILINX_DMA_IP_DMA | + (device_id << XILINX_DMA_DEVICE_ID_SHIFT); + chan->common.private = (void *)&(chan->private); + + if (!chan->has_dre) + xdev->common.copy_align = fls(width - 1); + + chan->dev = xdev->dev; + xdev->chan[chan->id] = chan; + + /* Initialize the channel */ + err = dma_reset(chan); + if (err) { + dev_err(xdev->dev, "Reset channel failed\n"); + return err; + } + + spin_lock_init(&chan->lock); + INIT_LIST_HEAD(&chan->pending_list); + INIT_LIST_HEAD(&chan->active_list); + + chan->common.device = &xdev->common; + + /* find the IRQ line, if it exists in the device tree */ + chan->irq = irq_of_parse_and_map(node, 0); + err = devm_request_irq(xdev->dev, chan->irq, dma_intr_handler, + IRQF_SHARED, + "xilinx-dma-controller", chan); + if (err) { + dev_err(xdev->dev, "unable to request IRQ\n"); + return err; + } + + tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); + + /* Add the channel to DMA device channel list */ + list_add_tail(&chan->common.device_node, &xdev->common.channels); + + return 0; +} + +static int xilinx_dma_probe(struct platform_device *pdev) +{ + struct xilinx_dma_device *xdev; + struct device_node *child, *node; + struct resource *res; + int ret; + u32 value; + + xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); + if (!xdev) + return -ENOMEM; + + xdev->dev = &(pdev->dev); + INIT_LIST_HEAD(&xdev->common.channels); + + node = pdev->dev.of_node; + + /* iomap registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + xdev->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(xdev->regs)) + return PTR_ERR(xdev->regs); + + /* Check if SG is enabled */ + value = of_property_read_bool(node, "xlnx,include-sg"); + if (value) + xdev->feature |= XILINX_DMA_FTR_HAS_SG; + + /* Check if status control streams are enabled */ + value = of_property_read_bool(node, + "xlnx,sg-include-stscntrl-strm"); + if (value) + xdev->feature |= XILINX_DMA_FTR_STSCNTRL_STRM; + + /* Axi DMA only do slave transfers */ + dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); + dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); + xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; + xdev->common.device_control = xilinx_dma_device_control; + xdev->common.device_issue_pending = xilinx_dma_issue_pending; + xdev->common.device_alloc_chan_resources = + xilinx_dma_alloc_chan_resources; + xdev->common.device_free_chan_resources = + xilinx_dma_free_chan_resources; + xdev->common.device_tx_status = xilinx_tx_status; + xdev->common.dev = &pdev->dev; + + platform_set_drvdata(pdev, xdev); + + for_each_child_of_node(node, child) { + ret = xilinx_dma_chan_probe(xdev, child, xdev->feature); + if (ret) { + dev_err(&pdev->dev, "Probing channels failed\n"); + goto free_chan_resources; + } + } + + ret = dma_async_device_register(&xdev->common); + if (ret) { + dev_err(&pdev->dev, "DMA device registration failed\n"); + goto free_chan_resources; + } + + dev_info(&pdev->dev, "Probing xilinx axi dma engine...Successful\n"); + + return 0; + +free_chan_resources: + xilinx_dma_free_channels(xdev); + + return ret; +} + +static int xilinx_dma_remove(struct platform_device *pdev) +{ + struct xilinx_dma_device *xdev; + + xdev = platform_get_drvdata(pdev); + dma_async_device_unregister(&xdev->common); + + xilinx_dma_free_channels(xdev); + + return 0; +} + +static const struct of_device_id xilinx_dma_of_match[] = { + { .compatible = "xlnx,axi-dma", }, + {} +}; +MODULE_DEVICE_TABLE(of, xilinx_dma_of_match); + +static struct platform_driver xilinx_dma_driver = { + .driver = { + .name = "xilinx-dma", + .owner = THIS_MODULE, + .of_match_table = xilinx_dma_of_match, + }, + .probe = xilinx_dma_probe, + .remove = xilinx_dma_remove, +}; + +module_platform_driver(xilinx_dma_driver); + +MODULE_AUTHOR("Xilinx, Inc."); +MODULE_DESCRIPTION("Xilinx DMA driver"); +MODULE_LICENSE("GPL v2"); Index: linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/xilinx_axivdma.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/dma/xilinx/xilinx_axivdma.c 2014-07-20 22:06:35.817314609 +0200 @@ -0,0 +1,1494 @@ +/* + * DMA driver for Xilinx Video DMA Engine + * + * Copyright (C) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Based on the Freescale DMA driver. + * + * Description: + * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP + * core that provides high-bandwidth direct memory access between memory + * and AXI4-Stream type video target peripherals. The core provides efficient + * two dimensional DMA operations with independent asynchronous read (S2MM) + * and write (MM2S) channel operation. It can be configured to have either + * one channel or two channels. If configured as two channels, one is to + * transmit to the video device (MM2S) and another is to receive from the + * video device (S2MM). Initialization, status, interrupt and management + * registers are accessed through an AXI4-Lite slave interface. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register/Descriptor Offsets */ +#define XILINX_VDMA_MM2S_CTRL_OFFSET 0x0000 +#define XILINX_VDMA_S2MM_CTRL_OFFSET 0x0030 +#define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050 +#define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0 + +/* Control Registers */ +#define XILINX_VDMA_REG_DMACR 0x0000 +#define XILINX_VDMA_DMACR_DELAY_MAX 0xff +#define XILINX_VDMA_DMACR_DELAY_SHIFT 24 +#define XILINX_VDMA_DMACR_FRAME_COUNT_MAX 0xff +#define XILINX_VDMA_DMACR_FRAME_COUNT_SHIFT 16 +#define XILINX_VDMA_DMACR_ERR_IRQ (1 << 14) +#define XILINX_VDMA_DMACR_DLY_CNT_IRQ (1 << 13) +#define XILINX_VDMA_DMACR_FRM_CNT_IRQ (1 << 12) +#define XILINX_VDMA_DMACR_MASTER_SHIFT 8 +#define XILINX_VDMA_DMACR_FSYNCSRC_SHIFT 5 +#define XILINX_VDMA_DMACR_FRAMECNT_EN (1 << 4) +#define XILINX_VDMA_DMACR_GENLOCK_EN (1 << 3) +#define XILINX_VDMA_DMACR_RESET (1 << 2) +#define XILINX_VDMA_DMACR_CIRC_EN (1 << 1) +#define XILINX_VDMA_DMACR_RUNSTOP (1 << 0) +#define XILINX_VDMA_DMACR_DELAY_MASK \ + (XILINX_VDMA_DMACR_DELAY_MAX << \ + XILINX_VDMA_DMACR_DELAY_SHIFT) +#define XILINX_VDMA_DMACR_FRAME_COUNT_MASK \ + (XILINX_VDMA_DMACR_FRAME_COUNT_MAX << \ + XILINX_VDMA_DMACR_FRAME_COUNT_SHIFT) +#define XILINX_VDMA_DMACR_MASTER_MASK \ + (0xf << XILINX_VDMA_DMACR_MASTER_SHIFT) +#define XILINX_VDMA_DMACR_FSYNCSRC_MASK \ + (3 << XILINX_VDMA_DMACR_FSYNCSRC_SHIFT) + +#define XILINX_VDMA_REG_DMASR 0x0004 +#define XILINX_VDMA_DMASR_DELAY_SHIFT 24 +#define XILINX_VDMA_DMASR_FRAME_COUNT_SHIFT 16 +#define XILINX_VDMA_DMASR_EOL_LATE_ERR (1 << 15) +#define XILINX_VDMA_DMASR_ERR_IRQ (1 << 14) +#define XILINX_VDMA_DMASR_DLY_CNT_IRQ (1 << 13) +#define XILINX_VDMA_DMASR_FRM_CNT_IRQ (1 << 12) +#define XILINX_VDMA_DMASR_SOF_LATE_ERR (1 << 11) +#define XILINX_VDMA_DMASR_SG_DEC_ERR (1 << 10) +#define XILINX_VDMA_DMASR_SG_SLV_ERR (1 << 9) +#define XILINX_VDMA_DMASR_EOF_EARLY_ERR (1 << 8) +#define XILINX_VDMA_DMASR_SOF_EARLY_ERR (1 << 7) +#define XILINX_VDMA_DMASR_DMA_DEC_ERR (1 << 6) +#define XILINX_VDMA_DMASR_DMA_SLAVE_ERR (1 << 5) +#define XILINX_VDMA_DMASR_DMA_INT_ERR (1 << 4) +#define XILINX_VDMA_DMASR_IDLE (1 << 1) +#define XILINX_VDMA_DMASR_HALTED (1 << 0) +#define XILINX_VDMA_DMASR_DELAY_MASK \ + (0xff << XILINX_VDMA_DMASR_DELAY_SHIFT) +#define XILINX_VDMA_DMASR_FRAME_COUNT_MASK \ + (0xff << XILINX_VDMA_DMASR_FRAME_COUNT_SHIFT) + +#define XILINX_VDMA_REG_CURDESC 0x0008 +#define XILINX_VDMA_REG_TAILDESC 0x0010 +#define XILINX_VDMA_REG_REG_INDEX 0x0014 +#define XILINX_VDMA_REG_FRMSTORE 0x0018 +#define XILINX_VDMA_REG_THRESHOLD 0x001c +#define XILINX_VDMA_REG_FRMPTR_STS 0x0024 +#define XILINX_VDMA_REG_PARK_PTR 0x0028 +#define XILINX_VDMA_PARK_PTR_WR_REF_SHIFT 8 +#define XILINX_VDMA_PARK_PTR_RD_REF_SHIFT 0 +#define XILINX_VDMA_REG_VDMA_VERSION 0x002c + +/* Register Direct Mode Registers */ +#define XILINX_VDMA_REG_VSIZE 0x0000 +#define XILINX_VDMA_REG_HSIZE 0x0004 + +#define XILINX_VDMA_REG_FRMDLY_STRIDE 0x0008 +#define XILINX_VDMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24 +#define XILINX_VDMA_FRMDLY_STRIDE_STRIDE_SHIFT 0 +#define XILINX_VDMA_FRMDLY_STRIDE_FRMDLY_MASK \ + (0x1f << \ + XILINX_VDMA_FRMDLY_STRIDE_FRMDLY_SHIFT) +#define XILINX_VDMA_FRMDLY_STRIDE_STRIDE_MASK \ + (0xffff << \ + XILINX_VDMA_FRMDLY_STRIDE_STRIDE_MASK) + +#define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n)) + +/* Hw specific definitions */ +#define XILINX_VDMA_MAX_CHANS_PER_DEVICE 0x2 + +#define XILINX_VDMA_DMAXR_ALL_IRQ_MASK (XILINX_VDMA_DMASR_FRM_CNT_IRQ | \ + XILINX_VDMA_DMASR_DLY_CNT_IRQ | \ + XILINX_VDMA_DMASR_ERR_IRQ) + +#define XILINX_VDMA_DMASR_ALL_ERR_MASK (XILINX_VDMA_DMASR_EOL_LATE_ERR | \ + XILINX_VDMA_DMASR_SOF_LATE_ERR | \ + XILINX_VDMA_DMASR_SG_DEC_ERR | \ + XILINX_VDMA_DMASR_SG_SLV_ERR | \ + XILINX_VDMA_DMASR_EOF_EARLY_ERR | \ + XILINX_VDMA_DMASR_SOF_EARLY_ERR | \ + XILINX_VDMA_DMASR_DMA_DEC_ERR | \ + XILINX_VDMA_DMASR_DMA_SLAVE_ERR | \ + XILINX_VDMA_DMASR_DMA_INT_ERR) + +/* + * Recoverable errors are DMA Internal error, SOF Early, EOF Early and SOF Late. + * They are only recoverable when C_FLUSH_ON_FSYNC is enabled in the h/w system. + */ +#define XILINX_VDMA_DMASR_ERR_RECOVER_MASK \ + (XILINX_VDMA_DMASR_SOF_LATE_ERR | \ + XILINX_VDMA_DMASR_EOF_EARLY_ERR | \ + XILINX_VDMA_DMASR_SOF_EARLY_ERR | \ + XILINX_VDMA_DMASR_DMA_INT_ERR) + +/* Axi VDMA Flush on Fsync bits */ +#define XILINX_VDMA_FLUSH_S2MM 3 +#define XILINX_VDMA_FLUSH_MM2S 2 +#define XILINX_VDMA_FLUSH_BOTH 1 + +/* Delay loop counter to prevent hardware failure */ +#define XILINX_VDMA_LOOP_COUNT 1000000 + +/** + * struct xilinx_vdma_desc_hw - Hardware Descriptor + * @next_desc: Next Descriptor Pointer @0x00 + * @pad1: Reserved @0x04 + * @buf_addr: Buffer address @0x08 + * @pad2: Reserved @0x0C + * @vsize: Vertical Size @0x10 + * @hsize: Horizontal Size @0x14 + * @stride: Number of bytes between the first + * pixels of each horizontal line @0x18 + */ +struct xilinx_vdma_desc_hw { + u32 next_desc; + u32 pad1; + u32 buf_addr; + u32 pad2; + u32 vsize; + u32 hsize; + u32 stride; +} __aligned(64); + +/** + * struct xilinx_vdma_tx_segment - Descriptor segment + * @hw: Hardware descriptor + * @node: Node in the descriptor segments list + * @cookie: Segment cookie + * @phys: Physical address of segment + */ +struct xilinx_vdma_tx_segment { + struct xilinx_vdma_desc_hw hw; + struct list_head node; + dma_cookie_t cookie; + dma_addr_t phys; +} __aligned(64); + +/** + * struct xilinx_vdma_tx_descriptor - Per Transaction structure + * @async_tx: Async transaction descriptor + * @segments: TX segments list + * @node: Node in the channel descriptors list + */ +struct xilinx_vdma_tx_descriptor { + struct dma_async_tx_descriptor async_tx; + struct list_head segments; + struct list_head node; +}; + +#define to_vdma_tx_descriptor(tx) \ + container_of(tx, struct xilinx_vdma_tx_descriptor, async_tx) + +/** + * struct xilinx_vdma_chan - Driver specific VDMA channel structure + * @xdev: Driver specific device structure + * @ctrl_offset: Control registers offset + * @desc_offset: TX descriptor registers offset + * @completed_cookie: Maximum cookie completed + * @cookie: The current cookie + * @lock: Descriptor operation lock + * @pending_list: Descriptors waiting + * @active_desc: Active descriptor + * @done_list: Complete descriptors + * @common: DMA common channel + * @desc_pool: Descriptors pool + * @dev: The dma device + * @irq: Channel IRQ + * @id: Channel ID + * @direction: Transfer direction + * @num_frms: Number of frames + * @has_sg: Support scatter transfers + * @genlock: Support genlock mode + * @err: Channel has errors + * @tasklet: Cleanup work after irq + * @private: Match info for channel request + * @config: Device configuration info + * @flush_on_fsync: Flush on Frame sync + */ +struct xilinx_vdma_chan { + struct xilinx_vdma_device *xdev; + u32 ctrl_offset; + u32 desc_offset; + dma_cookie_t completed_cookie; + dma_cookie_t cookie; + spinlock_t lock; + struct list_head pending_list; + struct xilinx_vdma_tx_descriptor *active_desc; + struct list_head done_list; + struct dma_chan common; + struct dma_pool *desc_pool; + struct device *dev; + int irq; + int id; + enum dma_transfer_direction direction; + int num_frms; + bool has_sg; + bool genlock; + bool err; + struct tasklet_struct tasklet; + u32 private; + struct xilinx_vdma_config config; + bool flush_on_fsync; +}; + +/** + * struct xilinx_vdma_device - VDMA device structure + * @regs: I/O mapped base address + * @dev: Device Structure + * @common: DMA device structure + * @chan: Driver specific VDMA channel + * @has_sg: Specifies whether Scatter-Gather is present or not + * @flush_on_fsync: Flush on frame sync + */ +struct xilinx_vdma_device { + void __iomem *regs; + struct device *dev; + struct dma_device common; + struct xilinx_vdma_chan *chan[XILINX_VDMA_MAX_CHANS_PER_DEVICE]; + bool has_sg; + u32 flush_on_fsync; +}; + +#define to_xilinx_chan(chan) \ + container_of(chan, struct xilinx_vdma_chan, common) + +/* IO accessors */ +static inline u32 vdma_read(struct xilinx_vdma_chan *chan, u32 reg) +{ + return ioread32(chan->xdev->regs + reg); +} + +static inline void vdma_write(struct xilinx_vdma_chan *chan, u32 reg, u32 value) +{ + iowrite32(value, chan->xdev->regs + reg); +} + +static inline void vdma_desc_write(struct xilinx_vdma_chan *chan, u32 reg, + u32 value) +{ + vdma_write(chan, chan->desc_offset + reg, value); +} + +static inline u32 vdma_ctrl_read(struct xilinx_vdma_chan *chan, u32 reg) +{ + return vdma_read(chan, chan->ctrl_offset + reg); +} + +static inline void vdma_ctrl_write(struct xilinx_vdma_chan *chan, u32 reg, + u32 value) +{ + vdma_write(chan, chan->ctrl_offset + reg, value); +} + +static inline void vdma_ctrl_clr(struct xilinx_vdma_chan *chan, u32 reg, + u32 clr) +{ + vdma_ctrl_write(chan, reg, vdma_ctrl_read(chan, reg) & ~clr); +} + +static inline void vdma_ctrl_set(struct xilinx_vdma_chan *chan, u32 reg, + u32 set) +{ + vdma_ctrl_write(chan, reg, vdma_ctrl_read(chan, reg) | set); +} + +/* ----------------------------------------------------------------------------- + * Descriptors and segments alloc and free + */ + +/** + * xilinx_vdma_alloc_tx_segment - Allocate transaction segment + * @chan: Driver specific VDMA channel + * + * Return the allocated segment on success and NULL on failure. + */ +static struct xilinx_vdma_tx_segment * +xilinx_vdma_alloc_tx_segment(struct xilinx_vdma_chan *chan) +{ + struct xilinx_vdma_tx_segment *segment; + dma_addr_t phys; + + segment = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &phys); + if (!segment) + return NULL; + + memset(segment, 0, sizeof(*segment)); + segment->phys = phys; + + return segment; +} + +/** + * xilinx_vdma_free_tx_segment - Free transaction segment + * @chan: Driver specific VDMA channel + * @segment: VDMA transaction segment + */ +static void xilinx_vdma_free_tx_segment(struct xilinx_vdma_chan *chan, + struct xilinx_vdma_tx_segment *segment) +{ + dma_pool_free(chan->desc_pool, segment, segment->phys); +} + +/** + * xilinx_vdma_tx_descriptor - Allocate transaction descriptor + * @chan: Driver specific VDMA channel + * + * Return the allocated descriptor on success and NULL on failure. + */ +static struct xilinx_vdma_tx_descriptor * +xilinx_vdma_alloc_tx_descriptor(struct xilinx_vdma_chan *chan) +{ + struct xilinx_vdma_tx_descriptor *desc; + + desc = kzalloc(sizeof(*desc), GFP_KERNEL); + if (!desc) + return NULL; + + INIT_LIST_HEAD(&desc->segments); + + return desc; +} + +/** + * xilinx_vdma_free_tx_descriptor - Free transaction descriptor + * @chan: Driver specific VDMA channel + * @desc: VDMA transaction descriptor + */ +static void +xilinx_vdma_free_tx_descriptor(struct xilinx_vdma_chan *chan, + struct xilinx_vdma_tx_descriptor *desc) +{ + struct xilinx_vdma_tx_segment *segment, *next; + + if (!desc) + return; + + list_for_each_entry_safe(segment, next, &desc->segments, node) { + list_del(&segment->node); + xilinx_vdma_free_tx_segment(chan, segment); + } + + kfree(desc); +} + +/* Required functions */ + +/** + * xilinx_vdma_free_descriptors - Free descriptors list + * @chan: Driver specific VDMA channel + * @list: List to parse and delete the descriptor + */ +static void xilinx_vdma_free_desc_list(struct xilinx_vdma_chan *chan, + struct list_head *list) +{ + struct xilinx_vdma_tx_descriptor *desc, *next; + + list_for_each_entry_safe(desc, next, list, node) { + list_del(&desc->node); + xilinx_vdma_free_tx_descriptor(chan, desc); + } +} + +/** + * xilinx_vdma_free_descriptors - Free channel descriptors + * @chan: Driver specific VDMA channel + */ +static void xilinx_vdma_free_descriptors(struct xilinx_vdma_chan *chan) +{ + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + + xilinx_vdma_free_desc_list(chan, &chan->pending_list); + xilinx_vdma_free_desc_list(chan, &chan->done_list); + + xilinx_vdma_free_tx_descriptor(chan, chan->active_desc); + chan->active_desc = NULL; + + spin_unlock_irqrestore(&chan->lock, flags); +} + +/** + * xilinx_vdma_free_chan_resources - Free channel resources + * @dchan: DMA channel + */ +static void xilinx_vdma_free_chan_resources(struct dma_chan *dchan) +{ + struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan); + + dev_dbg(chan->dev, "Free all channel resources.\n"); + + tasklet_kill(&chan->tasklet); + xilinx_vdma_free_descriptors(chan); + dma_pool_destroy(chan->desc_pool); + chan->desc_pool = NULL; +} + +/** + * xilinx_vdma_chan_desc_cleanup - Clean channel descriptors + * @chan: Driver specific VDMA channel + */ +static void xilinx_vdma_chan_desc_cleanup(struct xilinx_vdma_chan *chan) +{ + struct xilinx_vdma_tx_descriptor *desc, *next; + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + + list_for_each_entry_safe(desc, next, &chan->done_list, node) { + dma_async_tx_callback callback; + void *callback_param; + + /* Remove from the list of running transactions */ + list_del(&desc->node); + + /* Run the link descriptor callback function */ + callback = desc->async_tx.callback; + callback_param = desc->async_tx.callback_param; + if (callback) { + spin_unlock_irqrestore(&chan->lock, flags); + callback(callback_param); + spin_lock_irqsave(&chan->lock, flags); + } + + /* Run any dependencies, then free the descriptor */ + dma_run_dependencies(&desc->async_tx); + xilinx_vdma_free_tx_descriptor(chan, desc); + } + + spin_unlock_irqrestore(&chan->lock, flags); +} + +/** + * xilinx_vdma_do_tasklet - Schedule completion tasklet + * @data: Pointer to the Xilinx VDMA channel structure + */ +static void xilinx_vdma_do_tasklet(unsigned long data) +{ + struct xilinx_vdma_chan *chan = (struct xilinx_vdma_chan *)data; + + xilinx_vdma_chan_desc_cleanup(chan); +} + +/** + * xilinx_vdma_alloc_chan_resources - Allocate channel resources + * @dchan: DMA channel + * + * Returns '1' on success and failure value on error + */ +static int xilinx_vdma_alloc_chan_resources(struct dma_chan *dchan) +{ + struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan); + + /* Has this channel already been allocated? */ + if (chan->desc_pool) + return 1; + + /* + * We need the descriptor to be aligned to 64bytes + * for meeting Xilinx VDMA specification requirement. + */ + chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", + chan->dev, + sizeof(struct xilinx_vdma_tx_segment), + __alignof__(struct xilinx_vdma_tx_segment), 0); + if (!chan->desc_pool) { + dev_err(chan->dev, + "unable to allocate channel %d descriptor pool\n", + chan->id); + return -ENOMEM; + } + + tasklet_init(&chan->tasklet, xilinx_vdma_do_tasklet, + (unsigned long)chan); + + chan->completed_cookie = DMA_MIN_COOKIE; + chan->cookie = DMA_MIN_COOKIE; + + /* There is at least one descriptor free to be allocated */ + return 1; +} + +/** + * xilinx_vdma_tx_status - Get VDMA transaction status + * @dchan: DMA channel + * @cookie: Transaction identifier + * @txstate: Transaction state + * + * Returns DMA transaction status + */ +static enum dma_status xilinx_vdma_tx_status(struct dma_chan *dchan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan); + dma_cookie_t last_used; + dma_cookie_t last_complete; + + xilinx_vdma_chan_desc_cleanup(chan); + + last_used = dchan->cookie; + last_complete = chan->completed_cookie; + + dma_set_tx_state(txstate, last_complete, last_used, 0); + + return dma_async_is_complete(cookie, last_complete, last_used); +} + +/** + * xilinx_vdma_is_running - Check if VDMA channel is running + * @chan: Driver specific VDMA channel + * + * Returns '1' if running, '0' if not. + */ +static int xilinx_vdma_is_running(struct xilinx_vdma_chan *chan) +{ + return !(vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR) & + XILINX_VDMA_DMASR_HALTED) && + (vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR) & + XILINX_VDMA_DMACR_RUNSTOP); +} + +/** + * xilinx_vdma_is_idle - Check if VDMA channel is idle + * @chan: Driver specific VDMA channel + * + * Returns '1' if idle, '0' if not. + */ +static int xilinx_vdma_is_idle(struct xilinx_vdma_chan *chan) +{ + return vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR) & + XILINX_VDMA_DMASR_IDLE; +} + +/** + * xilinx_vdma_halt - Halt VDMA channel + * @chan: Driver specific VDMA channel + */ +static void xilinx_vdma_halt(struct xilinx_vdma_chan *chan) +{ + int loop = XILINX_VDMA_LOOP_COUNT + 1; + + vdma_ctrl_clr(chan, XILINX_VDMA_REG_DMACR, XILINX_VDMA_DMACR_RUNSTOP); + + /* Wait for the hardware to halt */ + while (loop--) + if (vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR) & + XILINX_VDMA_DMASR_HALTED) + break; + + if (!loop) { + dev_err(chan->dev, "Cannot stop channel %p: %x\n", + chan, vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR)); + chan->err = true; + } + + return; +} + +/** + * xilinx_vdma_start - Start VDMA channel + * @chan: Driver specific VDMA channel + */ +static void xilinx_vdma_start(struct xilinx_vdma_chan *chan) +{ + int loop = XILINX_VDMA_LOOP_COUNT + 1; + + vdma_ctrl_set(chan, XILINX_VDMA_REG_DMACR, XILINX_VDMA_DMACR_RUNSTOP); + + /* Wait for the hardware to start */ + while (loop) + if (!(vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR) & + XILINX_VDMA_DMASR_HALTED)) + break; + + if (!loop) { + dev_err(chan->dev, "Cannot start channel %p: %x\n", + chan, vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR)); + + chan->err = true; + } + + return; +} + +/** + * xilinx_vdma_start_transfer - Starts VDMA transfer + * @chan: Driver specific channel struct pointer + */ +static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan) +{ + struct xilinx_vdma_config *config = &chan->config; + struct xilinx_vdma_tx_descriptor *desc; + unsigned long flags; + u32 reg; + struct xilinx_vdma_tx_segment *head, *tail = NULL; + + if (chan->err) + return; + + spin_lock_irqsave(&chan->lock, flags); + + /* There's already an active descriptor, bail out. */ + if (chan->active_desc) + goto out_unlock; + + if (list_empty(&chan->pending_list)) + goto out_unlock; + + desc = list_first_entry(&chan->pending_list, + struct xilinx_vdma_tx_descriptor, node); + + /* If it is SG mode and hardware is busy, cannot submit */ + if (chan->has_sg && xilinx_vdma_is_running(chan) && + !xilinx_vdma_is_idle(chan)) { + dev_dbg(chan->dev, "DMA controller still busy\n"); + goto out_unlock; + } + + if (chan->err) + goto out_unlock; + + /* + * If hardware is idle, then all descriptors on the running lists are + * done, start new transfers + */ + if (chan->has_sg) { + head = list_first_entry(&desc->segments, + struct xilinx_vdma_tx_segment, node); + tail = list_entry(desc->segments.prev, + struct xilinx_vdma_tx_segment, node); + + vdma_ctrl_write(chan, XILINX_VDMA_REG_CURDESC, head->phys); + } + + /* Configure the hardware using info in the config structure */ + reg = vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR); + + if (config->frm_cnt_en) + reg |= XILINX_VDMA_DMACR_FRAMECNT_EN; + else + reg &= ~XILINX_VDMA_DMACR_FRAMECNT_EN; + + /* + * With SG, start with circular mode, so that BDs can be fetched. + * In direct register mode, if not parking, enable circular mode + */ + if (chan->has_sg || !config->park) + reg |= XILINX_VDMA_DMACR_CIRC_EN; + + if (config->park) + reg &= ~XILINX_VDMA_DMACR_CIRC_EN; + + vdma_ctrl_write(chan, XILINX_VDMA_REG_DMACR, reg); + + if (config->park && (config->park_frm >= 0) && + (config->park_frm < chan->num_frms)) { + if (chan->direction == DMA_MEM_TO_DEV) + vdma_write(chan, XILINX_VDMA_REG_PARK_PTR, + config->park_frm << + XILINX_VDMA_PARK_PTR_RD_REF_SHIFT); + else + vdma_write(chan, XILINX_VDMA_REG_PARK_PTR, + config->park_frm << + XILINX_VDMA_PARK_PTR_WR_REF_SHIFT); + } + + /* Start the hardware */ + xilinx_vdma_start(chan); + + if (chan->err) + goto out_unlock; + + /* Start the transfer */ + if (chan->has_sg) { + vdma_ctrl_write(chan, XILINX_VDMA_REG_TAILDESC, tail->phys); + } else { + struct xilinx_vdma_tx_segment *segment; + int i = 0; + + list_for_each_entry(segment, &desc->segments, node) + vdma_desc_write(chan, + XILINX_VDMA_REG_START_ADDRESS(i++), + segment->hw.buf_addr); + + vdma_desc_write(chan, XILINX_VDMA_REG_HSIZE, config->hsize); + vdma_desc_write(chan, XILINX_VDMA_REG_FRMDLY_STRIDE, + (config->frm_dly << + XILINX_VDMA_FRMDLY_STRIDE_FRMDLY_SHIFT) | + (config->stride << + XILINX_VDMA_FRMDLY_STRIDE_STRIDE_SHIFT)); + vdma_desc_write(chan, XILINX_VDMA_REG_VSIZE, config->vsize); + } + + list_del(&desc->node); + chan->active_desc = desc; + +out_unlock: + spin_unlock_irqrestore(&chan->lock, flags); +} + +/** + * xilinx_vdma_issue_pending - Issue pending transactions + * @dchan: DMA channel + */ +static void xilinx_vdma_issue_pending(struct dma_chan *dchan) +{ + struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan); + + xilinx_vdma_start_transfer(chan); +} + +/** + * xilinx_vdma_complete_descriptor - Mark the active descriptor as complete + * @chan : xilinx DMA channel + * + * CONTEXT: hardirq + */ +static void xilinx_vdma_complete_descriptor(struct xilinx_vdma_chan *chan) +{ + struct xilinx_vdma_tx_descriptor *desc; + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + + desc = chan->active_desc; + if (!desc) { + dev_dbg(chan->dev, "no running descriptors\n"); + goto out_unlock; + } + + list_add_tail(&desc->node, &chan->done_list); + + /* Update the completed cookie and reset the active descriptor. */ + chan->completed_cookie = desc->async_tx.cookie; + chan->active_desc = NULL; + +out_unlock: + spin_unlock_irqrestore(&chan->lock, flags); +} + +/** + * xilinx_vdma_reset - Reset VDMA channel + * @chan: Driver specific VDMA channel + * + * Returns '0' on success and failure value on error + */ +static int xilinx_vdma_reset(struct xilinx_vdma_chan *chan) +{ + int loop = XILINX_VDMA_LOOP_COUNT + 1; + u32 tmp; + + vdma_ctrl_set(chan, XILINX_VDMA_REG_DMACR, XILINX_VDMA_DMACR_RESET); + + tmp = vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR) & + XILINX_VDMA_DMACR_RESET; + + /* Wait for the hardware to finish reset */ + while (loop-- && tmp) + tmp = vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR) & + XILINX_VDMA_DMACR_RESET; + + if (!loop) { + dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", + vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR), + vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR)); + return -ETIMEDOUT; + } + + chan->err = false; + + return 0; +} + +/** + * xilinx_vdma_chan_reset - Reset VDMA channel and enable interrupts + * @chan: Driver specific VDMA channel + * + * Returns '0' on success and failure value on error + */ +static int xilinx_vdma_chan_reset(struct xilinx_vdma_chan *chan) +{ + int err; + + /* Reset VDMA */ + err = xilinx_vdma_reset(chan); + if (err) + return err; + + /* Enable interrupts */ + vdma_ctrl_set(chan, XILINX_VDMA_REG_DMACR, + XILINX_VDMA_DMAXR_ALL_IRQ_MASK); + + return 0; +} + +/** + * xilinx_vdma_irq_handler - VDMA Interrupt handler + * @irq: IRQ number + * @data: Pointer to the Xilinx VDMA channel structure + * + * Returns IRQ_HANDLED/IRQ_NONE + */ +static irqreturn_t xilinx_vdma_irq_handler(int irq, void *data) +{ + struct xilinx_vdma_chan *chan = data; + u32 status; + + /* Read the status and ack the interrupts. */ + status = vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR); + if (!(status & XILINX_VDMA_DMAXR_ALL_IRQ_MASK)) + return IRQ_NONE; + + vdma_ctrl_write(chan, XILINX_VDMA_REG_DMASR, + status & XILINX_VDMA_DMAXR_ALL_IRQ_MASK); + + if (status & XILINX_VDMA_DMASR_ERR_IRQ) { + /* + * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the + * error is recoverable, ignore it. Otherwise flag the error. + * + * Only recoverable errors can be cleared in the DMASR register, + * make sure not to write to other error bits to 1. + */ + u32 errors = status & XILINX_VDMA_DMASR_ALL_ERR_MASK; + vdma_ctrl_write(chan, XILINX_VDMA_REG_DMASR, + errors & XILINX_VDMA_DMASR_ERR_RECOVER_MASK); + + if (!chan->flush_on_fsync || + (errors & ~XILINX_VDMA_DMASR_ERR_RECOVER_MASK)) { + dev_err(chan->dev, + "Channel %p has errors %x, cdr %x tdr %x\n", + chan, errors, + vdma_ctrl_read(chan, XILINX_VDMA_REG_CURDESC), + vdma_ctrl_read(chan, XILINX_VDMA_REG_TAILDESC)); + chan->err = 1; + } + } + + if (status & XILINX_VDMA_DMASR_DLY_CNT_IRQ) { + /* + * Device takes too long to do the transfer when user requires + * responsiveness. + */ + dev_dbg(chan->dev, "Inter-packet latency too long\n"); + } + + if (status & XILINX_VDMA_DMASR_FRM_CNT_IRQ) { + xilinx_vdma_complete_descriptor(chan); + xilinx_vdma_start_transfer(chan); + } + + tasklet_schedule(&chan->tasklet); + return IRQ_HANDLED; +} + +/** + * xilinx_vdma_tx_submit - Submit DMA transaction + * @tx: Async transaction descriptor + * + * Returns cookie value on success and failure value on error + */ +static dma_cookie_t xilinx_vdma_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct xilinx_vdma_tx_descriptor *desc = to_vdma_tx_descriptor(tx); + struct xilinx_vdma_chan *chan = to_xilinx_chan(tx->chan); + struct xilinx_vdma_tx_segment *segment; + dma_cookie_t cookie; + unsigned long flags; + int err; + + if (chan->err) { + /* + * If reset fails, need to hard reset the system. + * Channel is no longer functional + */ + err = xilinx_vdma_chan_reset(chan); + if (err < 0) + return err; + } + + spin_lock_irqsave(&chan->lock, flags); + + /* Assign cookies to all of the segments that make up this transaction. + * Use the cookie of the last segment as the transaction cookie. + */ + cookie = chan->cookie; + + list_for_each_entry(segment, &desc->segments, node) { + if (cookie < DMA_MAX_COOKIE) + cookie++; + else + cookie = DMA_MIN_COOKIE; + + segment->cookie = cookie; + } + + tx->cookie = cookie; + chan->cookie = cookie; + + /* Append the transaction to the pending transactions queue. */ + list_add_tail(&desc->node, &chan->pending_list); + + spin_unlock_irqrestore(&chan->lock, flags); + + return cookie; +} + +/** + * xilinx_vdma_prep_slave_sg - prepare a descriptor for a DMA_SLAVE transaction + * @dchan: DMA channel + * @sgl: scatterlist to transfer to/from + * @sg_len: number of entries in @sgl + * @dir: DMA direction + * @flags: transfer ack flags + * @context: unused + */ +static struct dma_async_tx_descriptor * +xilinx_vdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction dir, + unsigned long flags, void *context) +{ + struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan); + struct xilinx_vdma_tx_descriptor *desc; + struct xilinx_vdma_tx_segment *segment; + struct xilinx_vdma_tx_segment *prev = NULL; + struct scatterlist *sg; + int i; + + if (chan->direction != dir || sg_len == 0) + return NULL; + + /* Enforce one sg entry for one frame. */ + if (sg_len != chan->num_frms) { + dev_err(chan->dev, + "number of entries %d not the same as num stores %d\n", + sg_len, chan->num_frms); + return NULL; + } + + /* Allocate a transaction descriptor. */ + desc = xilinx_vdma_alloc_tx_descriptor(chan); + if (!desc) + return NULL; + + dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); + desc->async_tx.tx_submit = xilinx_vdma_tx_submit; + desc->async_tx.cookie = 0; + async_tx_ack(&desc->async_tx); + + /* Build the list of transaction segments. */ + for_each_sg(sgl, sg, sg_len, i) { + struct xilinx_vdma_desc_hw *hw; + + /* Allocate the link descriptor from DMA pool */ + segment = xilinx_vdma_alloc_tx_segment(chan); + if (!segment) + goto error; + + /* Fill in the hardware descriptor */ + hw = &segment->hw; + hw->buf_addr = sg_dma_address(sg); + hw->vsize = chan->config.vsize; + hw->hsize = chan->config.hsize; + hw->stride = (chan->config.frm_dly << + XILINX_VDMA_FRMDLY_STRIDE_FRMDLY_SHIFT) | + (chan->config.stride << + XILINX_VDMA_FRMDLY_STRIDE_STRIDE_SHIFT); + if (prev) + prev->hw.next_desc = segment->phys; + + /* Insert the segment into the descriptor segments list. */ + list_add_tail(&segment->node, &desc->segments); + + prev = segment; + } + + /* Link the last hardware descriptor with the first. */ + segment = list_first_entry(&desc->segments, + struct xilinx_vdma_tx_segment, node); + prev->hw.next_desc = segment->phys; + + return &desc->async_tx; + +error: + xilinx_vdma_free_tx_descriptor(chan, desc); + return NULL; +} + +/** + * xilinx_vdma_terminate_all - Halt the channel and free descriptors + * @chan: Driver specific VDMA Channel pointer + */ +static void xilinx_vdma_terminate_all(struct xilinx_vdma_chan *chan) +{ + /* Halt the DMA engine */ + xilinx_vdma_halt(chan); + + /* Remove and free all of the descriptors in the lists */ + xilinx_vdma_free_descriptors(chan); +} + +/** + * xilinx_vdma_slave_config - Configure VDMA channel + * Run-time configuration for Axi VDMA, supports: + * . halt the channel + * . configure interrupt coalescing and inter-packet delay threshold + * . start/stop parking + * . enable genlock + * . set transfer information using config struct + * + * @chan: Driver specific VDMA Channel pointer + * @cfg: Channel configuration pointer + * + * Returns '0' on success and failure value on error + */ +static int xilinx_vdma_slave_config(struct xilinx_vdma_chan *chan, + struct xilinx_vdma_config *cfg) +{ + u32 dmacr; + + if (cfg->reset) + return xilinx_vdma_chan_reset(chan); + + dmacr = vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR); + + /* If vsize is -1, it is park-related operations */ + if (cfg->vsize == -1) { + if (cfg->park) + dmacr &= ~XILINX_VDMA_DMACR_CIRC_EN; + else + dmacr |= XILINX_VDMA_DMACR_CIRC_EN; + + vdma_ctrl_write(chan, XILINX_VDMA_REG_DMACR, dmacr); + return 0; + } + + /* If hsize is -1, it is interrupt threshold settings */ + if (cfg->hsize == -1) { + if (cfg->coalesc <= XILINX_VDMA_DMACR_FRAME_COUNT_MAX) { + dmacr &= ~XILINX_VDMA_DMACR_FRAME_COUNT_MASK; + dmacr |= cfg->coalesc << + XILINX_VDMA_DMACR_FRAME_COUNT_SHIFT; + chan->config.coalesc = cfg->coalesc; + } + + if (cfg->delay <= XILINX_VDMA_DMACR_DELAY_MAX) { + dmacr &= ~XILINX_VDMA_DMACR_DELAY_MASK; + dmacr |= cfg->delay << XILINX_VDMA_DMACR_DELAY_SHIFT; + chan->config.delay = cfg->delay; + } + + vdma_ctrl_write(chan, XILINX_VDMA_REG_DMACR, dmacr); + return 0; + } + + /* Transfer information */ + chan->config.vsize = cfg->vsize; + chan->config.hsize = cfg->hsize; + chan->config.stride = cfg->stride; + chan->config.frm_dly = cfg->frm_dly; + chan->config.park = cfg->park; + + /* genlock settings */ + chan->config.gen_lock = cfg->gen_lock; + chan->config.master = cfg->master; + + if (cfg->gen_lock && chan->genlock) { + dmacr |= XILINX_VDMA_DMACR_GENLOCK_EN; + dmacr |= cfg->master << XILINX_VDMA_DMACR_MASTER_SHIFT; + } + + chan->config.frm_cnt_en = cfg->frm_cnt_en; + if (cfg->park) + chan->config.park_frm = cfg->park_frm; + else + chan->config.park_frm = -1; + + chan->config.coalesc = cfg->coalesc; + chan->config.delay = cfg->delay; + if (cfg->coalesc <= XILINX_VDMA_DMACR_FRAME_COUNT_MAX) { + dmacr |= cfg->coalesc << XILINX_VDMA_DMACR_FRAME_COUNT_SHIFT; + chan->config.coalesc = cfg->coalesc; + } + + if (cfg->delay <= XILINX_VDMA_DMACR_DELAY_MAX) { + dmacr |= cfg->delay << XILINX_VDMA_DMACR_DELAY_SHIFT; + chan->config.delay = cfg->delay; + } + + /* FSync Source selection */ + dmacr &= ~XILINX_VDMA_DMACR_FSYNCSRC_MASK; + dmacr |= cfg->ext_fsync << XILINX_VDMA_DMACR_FSYNCSRC_SHIFT; + + vdma_ctrl_write(chan, XILINX_VDMA_REG_DMACR, dmacr); + return 0; +} + +/** + * xilinx_vdma_device_control - Configure DMA channel of the device + * @dchan: DMA Channel pointer + * @cmd: DMA control command + * @arg: Channel configuration + * + * Returns '0' on success and failure value on error + */ +static int xilinx_vdma_device_control(struct dma_chan *dchan, + enum dma_ctrl_cmd cmd, unsigned long arg) +{ + struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan); + + switch (cmd) { + case DMA_TERMINATE_ALL: + xilinx_vdma_terminate_all(chan); + return 0; + case DMA_SLAVE_CONFIG: + return xilinx_vdma_slave_config(chan, + (struct xilinx_vdma_config *)arg); + default: + return -ENXIO; + } +} + +/* ----------------------------------------------------------------------------- + * Probe and remove + */ + +/** + * xilinx_vdma_chan_remove - Per Channel remove function + * @chan: Driver specific VDMA channel + */ +static void xilinx_vdma_chan_remove(struct xilinx_vdma_chan *chan) +{ + /* Disable all interrupts */ + vdma_ctrl_clr(chan, XILINX_VDMA_REG_DMACR, + XILINX_VDMA_DMAXR_ALL_IRQ_MASK); + + list_del(&chan->common.device_node); +} + +/** + * xilinx_vdma_chan_probe - Per Channel Probing + * It get channel features from the device tree entry and + * initialize special channel handling routines + * + * @xdev: Driver specific device structure + * @node: Device node + * + * Returns '0' on success and failure value on error + */ +static int xilinx_vdma_chan_probe(struct xilinx_vdma_device *xdev, + struct device_node *node) +{ + struct xilinx_vdma_chan *chan; + bool has_dre = false; + u32 device_id; + u32 value; + int err; + + /* Allocate and initialize the channel structure */ + chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + chan->dev = xdev->dev; + chan->xdev = xdev; + chan->has_sg = xdev->has_sg; + + spin_lock_init(&chan->lock); + INIT_LIST_HEAD(&chan->pending_list); + INIT_LIST_HEAD(&chan->done_list); + + /* Retrieve the channel properties from the device tree */ + has_dre = of_property_read_bool(node, "xlnx,include-dre"); + + chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); + + err = of_property_read_u32(node, "xlnx,datawidth", &value); + if (!err) { + u32 width = value >> 3; /* Convert bits to bytes */ + + /* If data width is greater than 8 bytes, DRE is not in hw */ + if (width > 8) + has_dre = false; + + if (!has_dre) + xdev->common.copy_align = fls(width - 1); + } + + err = of_property_read_u32(node, "xlnx,device-id", &device_id); + if (err < 0) { + dev_err(xdev->dev, "missing xlnx,device-id property\n"); + return err; + } + + if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel")) { + chan->direction = DMA_MEM_TO_DEV; + chan->id = 0; + + chan->ctrl_offset = XILINX_VDMA_MM2S_CTRL_OFFSET; + chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; + + if (xdev->flush_on_fsync == XILINX_VDMA_FLUSH_BOTH || + xdev->flush_on_fsync == XILINX_VDMA_FLUSH_MM2S) + chan->flush_on_fsync = true; + } else if (of_device_is_compatible(node, + "xlnx,axi-vdma-s2mm-channel")) { + chan->direction = DMA_DEV_TO_MEM; + chan->id = 1; + + chan->ctrl_offset = XILINX_VDMA_S2MM_CTRL_OFFSET; + chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; + + if (xdev->flush_on_fsync == XILINX_VDMA_FLUSH_BOTH || + xdev->flush_on_fsync == XILINX_VDMA_FLUSH_S2MM) + chan->flush_on_fsync = true; + } else { + dev_err(xdev->dev, "Invalid channel compatible node\n"); + return -EINVAL; + } + + /* + * Used by DMA clients who doesnt have a device node and can request + * the channel by passing this as a filter to 'dma_request_channel()'. + */ + chan->private = (chan->direction & 0xff) | + XILINX_DMA_IP_VDMA | + (device_id << XILINX_DMA_DEVICE_ID_SHIFT); + + /* Request the interrupt */ + chan->irq = irq_of_parse_and_map(node, 0); + err = devm_request_irq(xdev->dev, chan->irq, xilinx_vdma_irq_handler, + IRQF_SHARED, "xilinx-vdma-controller", chan); + if (err) { + dev_err(xdev->dev, "unable to request IRQ\n"); + return err; + } + + /* Initialize the DMA channel and add it to the DMA engine channels + * list. + */ + chan->common.device = &xdev->common; + chan->common.private = (void *)&(chan->private); + + list_add_tail(&chan->common.device_node, &xdev->common.channels); + xdev->chan[chan->id] = chan; + + /* Reset the channel */ + err = xilinx_vdma_chan_reset(chan); + if (err < 0) { + dev_err(xdev->dev, "Reset channel failed\n"); + return err; + } + + return 0; +} + +/** + * struct of_dma_filter_xilinx_args - Channel filter args + * @dev: DMA device structure + * @chan_id: Channel id + */ +struct of_dma_filter_xilinx_args { + struct dma_device *dev; + u32 chan_id; +}; + +/** + * xilinx_vdma_dt_filter - VDMA channel filter function + * @chan: DMA channel pointer + * @param: Filter match value + * + * Returns true/false based on the result + */ +static bool xilinx_vdma_dt_filter(struct dma_chan *chan, void *param) +{ + struct of_dma_filter_xilinx_args *args = param; + + return chan->device == args->dev && chan->chan_id == args->chan_id; +} + +/** + * of_dma_xilinx_xlate - Translation function + * @dma_spec: Pointer to DMA specifier as found in the device tree + * @ofdma: Pointer to DMA controller data + * + * Returns DMA channel pointer on success and NULL on error + */ +static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct of_dma_filter_xilinx_args args; + dma_cap_mask_t cap; + + args.dev = ofdma->of_dma_data; + if (!args.dev) + return NULL; + + if (dma_spec->args_count != 1) + return NULL; + + dma_cap_zero(cap); + dma_cap_set(DMA_SLAVE, cap); + + args.chan_id = dma_spec->args[0]; + + return dma_request_channel(cap, xilinx_vdma_dt_filter, &args); +} + +/** + * xilinx_vdma_probe - Driver probe function + * @pdev: Pointer to the platform_device structure + * + * Returns '0' on success and failure value on error + */ +static int xilinx_vdma_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct xilinx_vdma_device *xdev; + struct device_node *child; + struct resource *io; + int num_frames, i, err; + + dev_info(&pdev->dev, "Probing xilinx axi vdma engine\n"); + + /* Allocate and initialize the DMA engine structure */ + xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); + if (!xdev) + return -ENOMEM; + + xdev->dev = &pdev->dev; + + /* Request and map I/O memory */ + io = platform_get_resource(pdev, IORESOURCE_MEM, 0); + xdev->regs = devm_ioremap_resource(&pdev->dev, io); + if (IS_ERR(xdev->regs)) + return PTR_ERR(xdev->regs); + + /* Retrieve the DMA engine properties from the device tree */ + xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg"); + + err = of_property_read_u32(node, "xlnx,num-fstores", &num_frames); + if (err < 0) { + dev_err(xdev->dev, "missing xlnx,num-fstores property\n"); + return err; + } + + of_property_read_u32(node, "xlnx,flush-fsync", &xdev->flush_on_fsync); + + /* Initialize the DMA engine */ + xdev->common.dev = &pdev->dev; + + INIT_LIST_HEAD(&xdev->common.channels); + dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); + dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); + + xdev->common.device_alloc_chan_resources = + xilinx_vdma_alloc_chan_resources; + xdev->common.device_free_chan_resources = + xilinx_vdma_free_chan_resources; + xdev->common.device_prep_slave_sg = xilinx_vdma_prep_slave_sg; + xdev->common.device_control = xilinx_vdma_device_control; + xdev->common.device_tx_status = xilinx_vdma_tx_status; + xdev->common.device_issue_pending = xilinx_vdma_issue_pending; + + platform_set_drvdata(pdev, xdev); + + /* Initialize the channels */ + for_each_child_of_node(node, child) { + err = xilinx_vdma_chan_probe(xdev, child); + if (err < 0) + goto error; + } + + for (i = 0; i < XILINX_VDMA_MAX_CHANS_PER_DEVICE; i++) { + if (xdev->chan[i]) + xdev->chan[i]->num_frms = num_frames; + } + + /* Register the DMA engine with the core */ + dma_async_device_register(&xdev->common); + + err = of_dma_controller_register(node, of_dma_xilinx_xlate, + &xdev->common); + if (err < 0) + dev_err(&pdev->dev, "Unable to register DMA to DT\n"); + + return 0; + +error: + for (i = 0; i < XILINX_VDMA_MAX_CHANS_PER_DEVICE; i++) { + if (xdev->chan[i]) + xilinx_vdma_chan_remove(xdev->chan[i]); + } + + return err; +} + +/** + * xilinx_vdma_remove - Driver remove function + * @pdev: Pointer to the platform_device structure + * + * Always returns '0' + */ +static int xilinx_vdma_remove(struct platform_device *pdev) +{ + struct xilinx_vdma_device *xdev; + int i; + + of_dma_controller_free(pdev->dev.of_node); + + xdev = platform_get_drvdata(pdev); + dma_async_device_unregister(&xdev->common); + + for (i = 0; i < XILINX_VDMA_MAX_CHANS_PER_DEVICE; i++) { + if (xdev->chan[i]) + xilinx_vdma_chan_remove(xdev->chan[i]); + } + + return 0; +} + +static const struct of_device_id xilinx_vdma_of_ids[] = { + { .compatible = "xlnx,axi-vdma",}, + {} +}; + +static struct platform_driver xilinx_vdma_driver = { + .driver = { + .name = "xilinx-vdma", + .owner = THIS_MODULE, + .of_match_table = xilinx_vdma_of_ids, + }, + .probe = xilinx_vdma_probe, + .remove = xilinx_vdma_remove, +}; + +module_platform_driver(xilinx_vdma_driver); + +MODULE_AUTHOR("Xilinx, Inc."); +MODULE_DESCRIPTION("Xilinx VDMA driver"); +MODULE_LICENSE("GPL v2"); Index: linux-3.12.24-rt38-xilinx/drivers/edac/Kconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/edac/Kconfig 2014-07-20 22:05:50.172067677 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/edac/Kconfig 2014-07-20 22:06:35.830314394 +0200 @@ -326,6 +326,13 @@ Support for error detection and correction on the Tilera memory controller. +config EDAC_ZYNQ + tristate "ZYNQ DDR Memory Controller" + depends on EDAC_MM_EDAC && ARCH_ZYNQ + help + This enables support for EDAC on the ECC memory used + with the ZYNQ DDR memory controller. + config EDAC_HIGHBANK_MC tristate "Highbank Memory Controller" depends on EDAC_MM_EDAC && ARCH_HIGHBANK Index: linux-3.12.24-rt38-xilinx/drivers/edac/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/edac/Makefile 2014-07-20 22:05:50.171067694 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/edac/Makefile 2014-07-20 22:06:35.840314229 +0200 @@ -64,3 +64,4 @@ obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o obj-$(CONFIG_EDAC_OCTEON_LMC) += octeon_edac-lmc.o obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o +obj-$(CONFIG_EDAC_ZYNQ) += zynq_edac.o Index: linux-3.12.24-rt38-xilinx/drivers/edac/zynq_edac.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/edac/zynq_edac.c 2014-07-20 22:06:35.853314015 +0200 @@ -0,0 +1,613 @@ +/* + * Xilinx Zynq DDR ECC Driver + * This driver is based on ppc4xx_edac.c drivers + * + * Copyright (C) 2012 - 2013 Xilinx, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include "edac_core.h" + +/* Number of cs_rows needed per memory controller */ +#define ZYNQ_EDAC_NR_CSROWS 1 + +/* Number of channels per memory controller */ +#define ZYNQ_EDAC_NR_CHANS 1 + +/* Granularity of reported error in bytes */ +#define ZYNQ_EDAC_ERROR_GRAIN 1 + +#define ZYNQ_EDAC_MESSAGE_SIZE 256 + +/* Zynq DDR memory controller registers that are relevant to ECC */ +#define ZYNQ_DDRC_CONTROL_REG_OFFSET 0x0 /* Control regsieter */ +#define ZYNQ_DDRC_T_ZQ_REG_OFFSET 0xA4 /* ZQ register */ + +/* ECC control register */ +#define ZYNQ_DDRC_ECC_CONTROL_REG_OFFSET 0xC4 +/* ECC log register */ +#define ZYNQ_DDRC_ECC_CE_LOG_REG_OFFSET 0xC8 +/* ECC address register */ +#define ZYNQ_DDRC_ECC_CE_ADDR_REG_OFFSET 0xCC +/* ECC data[31:0] register */ +#define ZYNQ_DDRC_ECC_CE_DATA_31_0_REG_OFFSET 0xD0 + +/* Uncorrectable error info regsisters */ +#define ZYNQ_DDRC_ECC_UE_LOG_REG_OFFSET 0xDC /* ECC control register */ +#define ZYNQ_DDRC_ECC_UE_ADDR_REG_OFFSET 0xE0 /* ECC log register */ +#define ZYNQ_DDRC_ECC_UE_DATA_31_0_REG_OFFSET 0xE4 /* ECC address register */ + +#define ZYNQ_DDRC_ECC_STAT_REG_OFFSET 0xF0 /* ECC statistics register */ +#define ZYNQ_DDRC_ECC_SCRUB_REG_OFFSET 0xF4 /* ECC scrub register */ + +/* Control regsiter bitfield definitions */ +#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC +#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2 + +#define ZYNQ_DDRCTL_WDTH_16 1 +#define ZYNQ_DDRCTL_WDTH_32 0 + +/* ZQ register bitfield definitions */ +#define ZYNQ_DDRC_T_ZQ_REG_DDRMODE_MASK 0x2 + +/* ECC control register bitfield definitions */ +#define ZYNQ_DDRC_ECCCTRL_CLR_CE_ERR 0x2 +#define ZYNQ_DDRC_ECCCTRL_CLR_UE_ERR 0x1 + +/* ECC correctable/uncorrectable error log register definitions */ +#define ZYNQ_DDRC_ECC_CE_LOGREG_VALID 0x1 +#define ZYNQ_DDRC_ECC_CE_LOGREG_BITPOS_MASK 0xFE +#define ZYNQ_DDRC_ECC_CE_LOGREG_BITPOS_SHIFT 1 + +/* ECC correctable/uncorrectable error address register definitions */ +#define ZYNQ_DDRC_ECC_ADDRREG_COL_MASK 0xFFF +#define ZYNQ_DDRC_ECC_ADDRREG_ROW_MASK 0xFFFF000 +#define ZYNQ_DDRC_ECC_ADDRREG_ROW_SHIFT 12 +#define ZYNQ_DDRC_ECC_ADDRREG_BANK_MASK 0x70000000 +#define ZYNQ_DDRC_ECC_ADDRREG_BANK_SHIFT 28 + +/* ECC statistic regsiter definitions */ +#define ZYNQ_DDRC_ECC_STATREG_UECOUNT_MASK 0xFF +#define ZYNQ_DDRC_ECC_STATREG_CECOUNT_MASK 0xFF00 +#define ZYNQ_DDRC_ECC_STATREG_CECOUNT_SHIFT 8 + +/* ECC scrub regsiter definitions */ +#define ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK 0x7 +#define ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED 0x4 + +/** + * struct ecc_error_info - ECC error log information + * @row: Row number + * @col: Column number + * @bank: Bank number + * @bitpos: Bit position + * @data: Data causing the error + */ +struct ecc_error_info { + u32 row; + u32 col; + u32 bank; + u32 bitpos; + u32 data; +}; + +/** + * struct zynq_ecc_status - ECC status information to report + * @ce_count: Correctable error count + * @ue_count: Uncorrectable error count + * @ceinfo: Correctable error log information + * @ueinfo: Uncorrectable error log information + */ +struct zynq_ecc_status { + u32 ce_count; + u32 ue_count; + struct ecc_error_info ceinfo; + struct ecc_error_info ueinfo; +}; + +/** + * struct zynq_edac_priv - Zynq DDR memory controller private instance data + * @baseaddr: Base address of the DDR controller + * @ce_count: Correctable Error count + * @ue_count: Uncorrectable Error count + */ +struct zynq_edac_priv { + void __iomem *baseaddr; + u32 ce_count; + u32 ue_count; +}; + +/** + * zynq_edac_geterror_info - Get the current ecc error info + * @base: Pointer to the base address of the ddr memory controller + * @perrstatus: Pointer to the zynq ecc status structure + * + * This routine determines there is any ecc error or not + * + * Returns zero if there is no error otherwise returns 1 + */ +static int zynq_edac_geterror_info(void __iomem *base, + struct zynq_ecc_status *perrstatus) +{ + u32 regval; + u32 clearval = 0; + + regval = readl(base + ZYNQ_DDRC_ECC_STAT_REG_OFFSET) & + (ZYNQ_DDRC_ECC_STATREG_UECOUNT_MASK | + ZYNQ_DDRC_ECC_STATREG_CECOUNT_MASK); + + if (regval == 0) + return 0; + + memset(perrstatus, 0, sizeof(struct zynq_ecc_status)); + + perrstatus->ce_count = (regval & ZYNQ_DDRC_ECC_STATREG_CECOUNT_MASK) >> + ZYNQ_DDRC_ECC_STATREG_CECOUNT_SHIFT; + perrstatus->ue_count = (regval & ZYNQ_DDRC_ECC_STATREG_UECOUNT_MASK); + + if (perrstatus->ce_count) { + regval = readl(base + ZYNQ_DDRC_ECC_CE_LOG_REG_OFFSET); + if (regval & ZYNQ_DDRC_ECC_CE_LOGREG_VALID) { + perrstatus->ceinfo.bitpos = (regval & + ZYNQ_DDRC_ECC_CE_LOGREG_BITPOS_MASK) >> + ZYNQ_DDRC_ECC_CE_LOGREG_BITPOS_SHIFT; + regval = readl(base + + ZYNQ_DDRC_ECC_CE_ADDR_REG_OFFSET); + perrstatus->ceinfo.row = (regval & + ZYNQ_DDRC_ECC_ADDRREG_ROW_MASK) >> + ZYNQ_DDRC_ECC_ADDRREG_ROW_SHIFT; + perrstatus->ceinfo.col = (regval & + ZYNQ_DDRC_ECC_ADDRREG_COL_MASK); + perrstatus->ceinfo.bank = (regval & + ZYNQ_DDRC_ECC_ADDRREG_BANK_MASK) >> + ZYNQ_DDRC_ECC_ADDRREG_BANK_SHIFT; + perrstatus->ceinfo.data = readl(base + + ZYNQ_DDRC_ECC_CE_DATA_31_0_REG_OFFSET); + edac_dbg(3, "ce bitposition: %d data: %d\n", + perrstatus->ceinfo.bitpos, + perrstatus->ceinfo.data); + } + clearval = ZYNQ_DDRC_ECCCTRL_CLR_CE_ERR; + } + + if (perrstatus->ue_count) { + regval = readl(base + ZYNQ_DDRC_ECC_UE_LOG_REG_OFFSET); + if (regval & ZYNQ_DDRC_ECC_CE_LOGREG_VALID) { + regval = readl(base + + ZYNQ_DDRC_ECC_UE_ADDR_REG_OFFSET); + perrstatus->ueinfo.row = (regval & + ZYNQ_DDRC_ECC_ADDRREG_ROW_MASK) >> + ZYNQ_DDRC_ECC_ADDRREG_ROW_SHIFT; + perrstatus->ueinfo.col = (regval & + ZYNQ_DDRC_ECC_ADDRREG_COL_MASK); + perrstatus->ueinfo.bank = (regval & + ZYNQ_DDRC_ECC_ADDRREG_BANK_MASK) >> + ZYNQ_DDRC_ECC_ADDRREG_BANK_SHIFT; + perrstatus->ueinfo.data = readl(base + + ZYNQ_DDRC_ECC_UE_DATA_31_0_REG_OFFSET); + } + clearval |= ZYNQ_DDRC_ECCCTRL_CLR_UE_ERR; + } + + writel(clearval, base + ZYNQ_DDRC_ECC_CONTROL_REG_OFFSET); + writel(0x0, base + ZYNQ_DDRC_ECC_CONTROL_REG_OFFSET); + + return 1; +} + +/** + * zynq_edac_generate_message - Generate interpreted ECC status message + * @mci: Pointer to the edac memory controller instance + * @perrstatus: Pointer to the zynq ecc status structure + * @buffer: Pointer to the buffer in which to generate the + * message + * @size: The size, in bytes, of space available in buffer + * + * This routine generates to the provided buffer the portion of the + * driver-unique report message associated with the ECC register of + * the specified ECC status. + */ +static void zynq_edac_generate_message(const struct mem_ctl_info *mci, + struct zynq_ecc_status *perrstatus, char *buffer, + size_t size) +{ + struct ecc_error_info *pinfo = NULL; + + if (perrstatus->ce_count > 0) + pinfo = &perrstatus->ceinfo; + else + pinfo = &perrstatus->ueinfo; + + snprintf(buffer, ZYNQ_EDAC_MESSAGE_SIZE, + "DDR ECC error type :%s Row %d Bank %d Col %d ", + (perrstatus->ce_count > 0) ? "CE" : "UE", pinfo->row, + pinfo->bank, pinfo->col); +} + +/** + * zynq_edac_handle_error - Handle controller error types CE and UE + * @mci: Pointer to the edac memory controller instance + * @perrstatus: Pointer to the zynq ecc status structure + * + * This routine handles an xilinx,ps7-ddrc controller ECC correctable error. + */ +static void zynq_edac_handle_error(struct mem_ctl_info *mci, + struct zynq_ecc_status *perrstatus) +{ + char message[ZYNQ_EDAC_MESSAGE_SIZE]; + + zynq_edac_generate_message(mci, perrstatus, &message[0], + ZYNQ_EDAC_MESSAGE_SIZE); + + if (perrstatus->ce_count) + edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, + perrstatus->ce_count, 0, 0, 0, 0, 0, -1, + &message[0], ""); + else + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, + perrstatus->ue_count, 0, 0, 0, 0, 0, -1, + &message[0], ""); +} + +/** + * zynq_edac_check - Check controller for ECC errors + * @mci: Pointer to the edac memory controller instance + * + * This routine is used to check and post ECC errors and is called by + * the EDAC polling thread + */ +static void zynq_edac_check(struct mem_ctl_info *mci) +{ + struct zynq_edac_priv *priv = mci->pvt_info; + struct zynq_ecc_status errstatus; + int status; + + status = zynq_edac_geterror_info(priv->baseaddr, &errstatus); + if (status) { + priv->ce_count += errstatus.ce_count; + priv->ue_count += errstatus.ue_count; + + if (errstatus.ce_count) { + zynq_edac_handle_error(mci, &errstatus); + errstatus.ce_count = 0; + } + if (errstatus.ue_count) { + zynq_edac_handle_error(mci, &errstatus); + errstatus.ue_count = 0; + } + edac_dbg(3, "total error count ce %d ue %d\n", + priv->ce_count, priv->ue_count); + } +} + +/** + * zynq_edac_get_dtype - Return the controller memory width + * @base: Pointer to the ddr memory contoller base address + * + * This routine returns the EDAC device type width appropriate for the + * current controller configuration. + * + * Returns a device type width enumeration. + */ +static enum dev_type zynq_edac_get_dtype(void __iomem *base) +{ + enum dev_type dt; + u32 width; + + width = readl(base + ZYNQ_DDRC_CONTROL_REG_OFFSET); + width = (width & ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK) >> + ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT; + + switch (width) { + case ZYNQ_DDRCTL_WDTH_16: + dt = DEV_X2; + break; + case ZYNQ_DDRCTL_WDTH_32: + dt = DEV_X4; + break; + default: + dt = DEV_UNKNOWN; + } + + return dt; +} + +/** + * zynq_edac_get_eccstate - Return the controller ecc enable/disable status + * @base: Pointer to the ddr memory contoller base address + * + * This routine returns the ECC enable/diable status for the xlnx,ps7-ddrc + * controller + * + * Returns a ecc status boolean i.e true/false - enabled/disabled. + */ +static bool zynq_edac_get_eccstate(void __iomem *base) +{ + enum dev_type dt; + u32 ecctype; + bool state = false; + + dt = zynq_edac_get_dtype(base); + + ecctype = (readl(base + ZYNQ_DDRC_ECC_SCRUB_REG_OFFSET) & + ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK); + + if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) + && (dt == DEV_X2)) { + state = true; + writel(0x0, base + ZYNQ_DDRC_ECC_CONTROL_REG_OFFSET); + } else { + state = false; + } + + return state; +} + +/** + * zynq_edac_get_memsize - Return the size of the attched mmeory device + * + * This routine returns the size of the system memory by reading the sysinfo + * information + * + * Returns the memory size in bytes + */ +static u32 zynq_edac_get_memsize(void) +{ + struct sysinfo inf; + + /* Reading the system memory size from the global meminfo structure */ + si_meminfo(&inf); + + return inf.totalram * inf.mem_unit; +} + +/** + * zynq_edac_get_mtype - Returns controller memory type + * @base: pointer to the zynq ecc status structure + * + * This routine returns the EDAC memory type appropriate for the + * current controller configuration. + * + * Returns a memory type enumeration. + */ +static enum mem_type zynq_edac_get_mtype(void __iomem *base) +{ + enum mem_type mt; + u32 memtype; + + memtype = readl(base + ZYNQ_DDRC_T_ZQ_REG_OFFSET); + + if (memtype & ZYNQ_DDRC_T_ZQ_REG_DDRMODE_MASK) + mt = MEM_DDR3; + else + mt = MEM_DDR2; + + return mt; +} + +/** + * zynq_edac_init_csrows - Initialize the cs row data + * @mci: Pointer to the edac memory controller instance + * + * This routine initializes the chip select rows associated + * with the EDAC memory controller instance + * + * Returns 0 if OK; otherwise, -EINVAL if the memory bank size + * configuration cannot be determined. + */ +static int zynq_edac_init_csrows(struct mem_ctl_info *mci) +{ + struct csrow_info *csi; + struct dimm_info *dimm; + struct zynq_edac_priv *priv = mci->pvt_info; + u32 size; + int row, j; + + for (row = 0; row < mci->nr_csrows; row++) { + csi = mci->csrows[row]; + size = zynq_edac_get_memsize(); + + for (j = 0; j < csi->nr_channels; j++) { + dimm = csi->channels[j]->dimm; + dimm->edac_mode = EDAC_FLAG_SECDED; + dimm->mtype = zynq_edac_get_mtype(priv->baseaddr); + dimm->nr_pages = + (size >> PAGE_SHIFT) / csi->nr_channels; + dimm->grain = ZYNQ_EDAC_ERROR_GRAIN; + dimm->dtype = zynq_edac_get_dtype(priv->baseaddr); + } + + } + + return 0; +} + +/** + * zynq_edac_mc_init - Initialize driver instance + * @mci: Pointer to the edac memory controller instance + * @pdev: Pointer to the platform_device struct + * + * This routine performs initialization of the EDAC memory controller + * instance and related driver-private data associated with the + * xlnx,ps7-ddrc memory controller the instance is bound to. + * + * Returns 0 if OK; otherwise, < 0 on error. + */ +static int zynq_edac_mc_init(struct mem_ctl_info *mci, + struct platform_device *pdev) +{ + int status; + struct zynq_edac_priv *priv; + + /* Initial driver pointers and private data */ + mci->pdev = &pdev->dev; + priv = mci->pvt_info; + platform_set_drvdata(pdev, mci); + + /* Initialize controller capabilities and configuration */ + mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; + mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; + mci->scrub_cap = SCRUB_HW_SRC; + /* Check the scrub setting from the controller */ + mci->scrub_mode = SCRUB_NONE; + + mci->edac_cap = EDAC_FLAG_SECDED; + /* Initialize strings */ + mci->ctl_name = "zynq_ddr_controller"; + mci->dev_name = dev_name(&pdev->dev); + mci->mod_name = "zynq_edac"; + mci->mod_ver = "1"; + + /* Initialize callbacks */ + edac_op_state = EDAC_OPSTATE_POLL; + mci->edac_check = zynq_edac_check; + mci->ctl_page_to_phys = NULL; + + /* + * Initialize the MC control structure 'csrows' table + * with the mapping and control information. + */ + status = zynq_edac_init_csrows(mci); + if (status) + pr_err("Failed to initialize rows!\n"); + + return status; +} + +/** + * zynq_edac_mc_probe - Check controller and bind driver + * @pdev: Pointer to the platform_device struct + * + * This routine probes a specific xilinx,ps7-ddrc controller + * instance for binding with the driver. + * + * Returns 0 if the controller instance was successfully bound to the + * driver; otherwise, < 0 on error. + */ +static int zynq_edac_mc_probe(struct platform_device *pdev) +{ + struct mem_ctl_info *mci; + struct edac_mc_layer layers[2]; + struct zynq_edac_priv *priv; + int rc; + struct resource *res; + void __iomem *baseaddr; + + /* Get the data from the platform device */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + baseaddr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(baseaddr)) + return PTR_ERR(baseaddr); + + /* Check for the ecc enable status */ + if (zynq_edac_get_eccstate(baseaddr) == false) { + dev_err(&pdev->dev, "ecc not enabled\n"); + return -ENXIO; + } + + /* + * At this point, we know ECC is enabled, allocate an EDAC + * controller instance and perform the appropriate + * initialization. + */ + layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; + layers[0].size = ZYNQ_EDAC_NR_CSROWS; + layers[0].is_virt_csrow = true; + layers[1].type = EDAC_MC_LAYER_CHANNEL; + layers[1].size = ZYNQ_EDAC_NR_CHANS; + layers[1].is_virt_csrow = false; + + mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, + sizeof(struct zynq_edac_priv)); + if (mci == NULL) { + pr_err("Failed memory allocation for mci instance!\n"); + return -ENOMEM; + } + + priv = mci->pvt_info; + priv->baseaddr = baseaddr; + rc = zynq_edac_mc_init(mci, pdev); + if (rc) { + pr_err("Failed to initialize instance!\n"); + goto free_edac_mc; + } + + /* + * We have a valid, initialized EDAC instance bound to the + * controller. Attempt to register it with the EDAC subsystem + */ + rc = edac_mc_add_mc(mci); + if (rc) { + dev_err(&pdev->dev, "failed to register with EDAC core\n"); + goto del_edac_mc; + } + + return rc; + +del_edac_mc: + edac_mc_del_mc(&pdev->dev); +free_edac_mc: + edac_mc_free(mci); + + return rc; +} + +/** + * zynq_edac_mc_remove - Unbind driver from controller + * @pdev: Pointer to the platform_device struct + * + * This routine unbinds the EDAC memory controller instance associated + * with the specified xilinx,ps7-ddrc controller described by the + * OpenFirmware device tree node passed as a parameter. + * + * Unconditionally returns 0. + */ +static int zynq_edac_mc_remove(struct platform_device *pdev) +{ + struct mem_ctl_info *mci = platform_get_drvdata(pdev); + + edac_mc_del_mc(&pdev->dev); + edac_mc_free(mci); + + return 0; +} + +/* Device tree node type and compatible tuples this driver can match on */ +static struct of_device_id zynq_edac_match[] = { + { .compatible = "xlnx,ps7-ddrc-1.00.a", }, + { /* end of table */ } +}; + +MODULE_DEVICE_TABLE(of, zynq_edac_match); + +static struct platform_driver zynq_edac_mc_driver = { + .driver = { + .name = "zynq-edac", + .owner = THIS_MODULE, + .of_match_table = zynq_edac_match, + }, + .probe = zynq_edac_mc_probe, + .remove = zynq_edac_mc_remove, +}; + +module_platform_driver(zynq_edac_mc_driver); + +MODULE_AUTHOR("Xilinx, Inc."); +MODULE_DESCRIPTION("Zynq DDR ECC driver"); +MODULE_LICENSE("GPL v2"); Index: linux-3.12.24-rt38-xilinx/drivers/gpio/gpio-xilinx.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/gpio/gpio-xilinx.c 2014-07-20 22:05:50.185067463 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/gpio/gpio-xilinx.c 2014-07-20 22:06:35.868313767 +0200 @@ -17,15 +17,25 @@ #include #include #include +#include #include #include +#include #include +#include +#include +#include #include #include /* Register Offset Definitions */ -#define XGPIO_DATA_OFFSET (0x0) /* Data register */ -#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ +#define XGPIO_DATA_OFFSET 0x0 /* Data register */ +#define XGPIO_TRI_OFFSET 0x4 /* I/O direction register */ +#define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ +#define XGPIO_GIER_IE BIT(31) + +#define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */ +#define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */ #define XGPIO_CHANNEL_OFFSET 0x8 @@ -40,18 +50,24 @@ /** * struct xgpio_instance - Stores information about GPIO device - * struct of_mm_gpio_chip mmchip: OF GPIO chip for memory mapped banks - * gpio_state: GPIO state shadow register - * gpio_dir: GPIO direction shadow register - * offset: GPIO channel offset - * gpio_lock: Lock used for synchronization + * @mmchip: OF GPIO chip for memory mapped banks + * @gpio_state: GPIO state shadow register + * @gpio_dir: GPIO direction shadow register + * @offset: GPIO channel offset + * @irq_base: GPIO channel irq base address + * @irq_enable: GPIO irq enable/disable bitfield + * @gpio_lock: Lock used for synchronization + * @irq_domain: irq_domain of the controller */ struct xgpio_instance { struct of_mm_gpio_chip mmchip; u32 gpio_state; u32 gpio_dir; u32 offset; + int irq_base; + u32 irq_enable; spinlock_t gpio_lock; + struct irq_domain *irq_domain; }; /** @@ -59,8 +75,11 @@ * @gc: Pointer to gpio_chip device structure. * @gpio: GPIO signal number. * - * This function reads the specified signal of the GPIO device. It returns 0 if - * the signal clear, 1 if signal is set or negative value on error. + * This function reads the specified signal of the GPIO device. + * + * Return: + * 0 if direction of GPIO signals is set as input otherwise it + * returns negative error value. */ static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) { @@ -110,8 +129,10 @@ * @gpio: GPIO signal number. * * This function sets the direction of specified GPIO signal as input. - * It returns 0 if direction of GPIO signals is set as input otherwise it - * returns negative error value. + * + * Return: + * 0 - if direction of GPIO signals is set as input + * otherwise it returns negative error value. */ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { @@ -138,8 +159,10 @@ * @gpio: GPIO signal number. * @val: Value to be written to specified signal. * - * This function sets the direction of specified GPIO signal as output. If all - * GPIO signals of GPIO chip is configured as input then it returns + * This function sets the direction of specified GPIO signal as output. + * + * Return: + * If all GPIO signals of GPIO chip is configured as input then it returns * error otherwise it returns 0. */ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) @@ -171,7 +194,7 @@ /** * xgpio_save_regs - Set initial values of GPIO pins - * @mm_gc: pointer to memory mapped GPIO chip structure + * @mm_gc: Pointer to memory mapped GPIO chip structure */ static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc) { @@ -185,20 +208,245 @@ } /** + * xgpio_xlate - Set initial values of GPIO pins + * @gc: Pointer to gpio_chip device structure. + * @gpiospec: gpio specifier as found in the device tree + * @flags: A flags pointer based on binding + * + * Return: + * irq number otherwise -EINVAL + */ +static int xgpio_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, u32 *flags) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct xgpio_instance *chip = container_of(mm_gc, struct xgpio_instance, + mmchip); + + if (gpiospec->args[1] == chip->offset) + return gpiospec->args[0]; + + return -EINVAL; +} + +/** + * xgpio_irq_mask - Write the specified signal of the GPIO device. + * @irq_data: per irq and chip data passed down to chip functions + */ +static void xgpio_irq_mask(struct irq_data *irq_data) +{ + unsigned long flags; + struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); + struct of_mm_gpio_chip *mm_gc = &chip->mmchip; + u32 offset = irq_data->irq - chip->irq_base; + u32 temp; + + pr_debug("%s: Disable %d irq, irq_enable_mask 0x%x\n", + __func__, offset, chip->irq_enable); + + spin_lock_irqsave(&chip->gpio_lock, flags); + + chip->irq_enable &= ~BIT(offset); + + if (!chip->irq_enable) { + /* Enable per channel interrupt */ + temp = xgpio_readreg(mm_gc->regs + XGPIO_IPIER_OFFSET); + temp &= chip->offset / XGPIO_CHANNEL_OFFSET + 1; + xgpio_writereg(mm_gc->regs + XGPIO_IPIER_OFFSET, temp); + + /* Disable global interrupt if channel interrupts are unused */ + temp = xgpio_readreg(mm_gc->regs + XGPIO_IPIER_OFFSET); + if (!temp) + xgpio_writereg(mm_gc->regs + XGPIO_GIER_OFFSET, + ~XGPIO_GIER_IE); + + } + spin_unlock_irqrestore(&chip->gpio_lock, flags); +} + +/** + * xgpio_irq_unmask - Write the specified signal of the GPIO device. + * @irq_data: per irq and chip data passed down to chip functions + */ +static void xgpio_irq_unmask(struct irq_data *irq_data) +{ + unsigned long flags; + struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); + struct of_mm_gpio_chip *mm_gc = &chip->mmchip; + u32 offset = irq_data->irq - chip->irq_base; + u32 temp; + + pr_debug("%s: Enable %d irq, irq_enable_mask 0x%x\n", + __func__, offset, chip->irq_enable); + + /* Setup pin as input */ + xgpio_dir_in(&mm_gc->gc, offset); + + spin_lock_irqsave(&chip->gpio_lock, flags); + + chip->irq_enable |= BIT(offset); + + if (chip->irq_enable) { + + /* Enable per channel interrupt */ + temp = xgpio_readreg(mm_gc->regs + XGPIO_IPIER_OFFSET); + temp |= chip->offset / XGPIO_CHANNEL_OFFSET + 1; + xgpio_writereg(mm_gc->regs + XGPIO_IPIER_OFFSET, temp); + + /* Enable global interrupts */ + xgpio_writereg(mm_gc->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); + } + + spin_unlock_irqrestore(&chip->gpio_lock, flags); +} + +/** + * xgpio_set_irq_type - Write the specified signal of the GPIO device. + * @irq_data: Per irq and chip data passed down to chip functions + * @type: Interrupt type that is to be set for the gpio pin + * + * Return: + * 0 if interrupt type is supported otherwise otherwise -EINVAL + */ +static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) +{ + /* Only rising edge case is supported now */ + if (type == IRQ_TYPE_EDGE_RISING) + return 0; + + return -EINVAL; +} + +/* irq chip descriptor */ +static struct irq_chip xgpio_irqchip = { + .name = "xgpio", + .irq_mask = xgpio_irq_mask, + .irq_unmask = xgpio_irq_unmask, + .irq_set_type = xgpio_set_irq_type, +}; + +/** + * xgpio_to_irq - Find out gpio to Linux irq mapping + * @gc: Pointer to gpio_chip device structure. + * @offset: Gpio pin offset + * + * Return: + * irq number otherwise -EINVAL + */ +static int xgpio_to_irq(struct gpio_chip *gc, unsigned offset) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct xgpio_instance *chip = container_of(mm_gc, struct xgpio_instance, + mmchip); + + return irq_find_mapping(chip->irq_domain, offset); +} + +/** + * xgpio_irqhandler - Gpio interrupt service routine + * @irq: gpio irq number + * @desc: Pointer to interrupt description + */ +static void xgpio_irqhandler(unsigned int irq, struct irq_desc *desc) +{ + struct xgpio_instance *chip = (struct xgpio_instance *) + irq_get_handler_data(irq); + struct of_mm_gpio_chip *mm_gc = &chip->mmchip; + struct irq_chip *irqchip = irq_desc_get_chip(desc); + int offset; + unsigned long val; + + chained_irq_enter(irqchip, desc); + + val = xgpio_readreg(mm_gc->regs + chip->offset); + /* Only rising edge is supported */ + val &= chip->irq_enable; + + for_each_set_bit(offset, &val, chip->mmchip.gc.ngpio) { + generic_handle_irq(chip->irq_base + offset); + } + + xgpio_writereg(mm_gc->regs + XGPIO_IPISR_OFFSET, + chip->offset / XGPIO_CHANNEL_OFFSET + 1); + + chained_irq_exit(irqchip, desc); +} + +static struct lock_class_key gpio_lock_class; + +/** + * xgpio_irq_setup - Allocate irq for gpio and setup appropriate functions + * @np: Device node of the GPIO chip + * @chip: Pointer to private gpio channel structure + * + * Return: + * 0 if success, otherwise -1 + */ +static int xgpio_irq_setup(struct device_node *np, struct xgpio_instance *chip) +{ + u32 pin_num; + struct resource res; + + int ret = of_irq_to_resource(np, 0, &res); + if (!ret) { + pr_info("GPIO IRQ not connected\n"); + return 0; + } + + chip->mmchip.gc.of_xlate = xgpio_xlate; + chip->mmchip.gc.of_gpio_n_cells = 2; + chip->mmchip.gc.to_irq = xgpio_to_irq; + + chip->irq_base = irq_alloc_descs(-1, 0, chip->mmchip.gc.ngpio, 0); + if (chip->irq_base < 0) { + pr_err("Couldn't allocate IRQ numbers\n"); + return -1; + } + chip->irq_domain = irq_domain_add_legacy(np, chip->mmchip.gc.ngpio, + chip->irq_base, 0, + &irq_domain_simple_ops, NULL); + + /* + * set the irq chip, handler and irq chip data for callbacks for + * each pin + */ + for (pin_num = 0; pin_num < chip->mmchip.gc.ngpio; pin_num++) { + u32 gpio_irq = irq_find_mapping(chip->irq_domain, pin_num); + irq_set_lockdep_class(gpio_irq, &gpio_lock_class); + pr_debug("IRQ Base: %d, Pin %d = IRQ %d\n", + chip->irq_base, pin_num, gpio_irq); + irq_set_chip_and_handler(gpio_irq, &xgpio_irqchip, + handle_simple_irq); + irq_set_chip_data(gpio_irq, (void *)chip); +#ifdef CONFIG_ARCH_ZYNQ + set_irq_flags(gpio_irq, IRQF_VALID); +#endif + } + irq_set_handler_data(res.start, (void *)chip); + irq_set_chained_handler(res.start, xgpio_irqhandler); + + return 0; +} + +/** * xgpio_of_probe - Probe method for the GPIO device. * @np: pointer to device tree node * * This function probes the GPIO device in the device tree. It initializes the - * driver data structure. It returns 0, if the driver is bound to the GPIO - * device, or a negative value if there is an error. + * driver data structure. + * + * Return: + * It returns 0, if the driver is bound to the GPIO device, or + * a negative value if there is an error. */ -static int xgpio_of_probe(struct device_node *np) +static int xgpio_of_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; struct xgpio_instance *chip; int status = 0; const u32 *tree_info; - chip = kzalloc(sizeof(*chip), GFP_KERNEL); + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; @@ -230,18 +478,24 @@ /* Call the OF gpio helper to setup and register the GPIO device */ status = of_mm_gpiochip_add(np, &chip->mmchip); if (status) { - kfree(chip); pr_err("%s: error in probe function with status %d\n", np->full_name, status); return status; } + status = xgpio_irq_setup(np, chip); + if (status) { + pr_err("%s: GPIO IRQ initialization failed %d\n", + np->full_name, status); + return status; + } + pr_info("XGpio: %s: registered, base is %d\n", np->full_name, chip->mmchip.gc.base); tree_info = of_get_property(np, "xlnx,is-dual", NULL); if (tree_info && be32_to_cpup(tree_info)) { - chip = kzalloc(sizeof(*chip), GFP_KERNEL); + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; @@ -274,12 +528,18 @@ chip->mmchip.save_regs = xgpio_save_regs; + status = xgpio_irq_setup(np, chip); + if (status) { + pr_err("%s: GPIO IRQ initialization failed %d\n", + np->full_name, status); + return status; + } + /* Call the OF gpio helper to setup and register the GPIO dev */ status = of_mm_gpiochip_add(np, &chip->mmchip); if (status) { - kfree(chip); pr_err("%s: error in probe function with status %d\n", - np->full_name, status); + np->full_name, status); return status; } pr_info("XGpio: %s: dual channel registered, base is %d\n", @@ -293,15 +553,20 @@ { .compatible = "xlnx,xps-gpio-1.00.a", }, { /* end of list */ }, }; +MODULE_DEVICE_TABLE(of, xgpio_of_match); + +static struct platform_driver xilinx_gpio_driver = { + .probe = xgpio_of_probe, + .driver = { + .owner = THIS_MODULE, + .name = "xilinx-gpio", + .of_match_table = xgpio_of_match, + }, +}; static int __init xgpio_init(void) { - struct device_node *np; - - for_each_matching_node(np, xgpio_of_match) - xgpio_of_probe(np); - - return 0; + return platform_driver_register(&xilinx_gpio_driver); } /* Make sure we get initialized before anyone else tries to use us */ Index: linux-3.12.24-rt38-xilinx/drivers/gpio/gpio-zynq.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/gpio/gpio-zynq.c 2014-07-20 22:06:35.883313520 +0200 @@ -0,0 +1,695 @@ +/* + * Xilinx PS GPIO device driver + * + * 2009-2011 (c) Xilinx, Inc. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any later + * version. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 675 Mass + * Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "zynq_gpio" +#define ZYNQ_GPIO_NR_GPIOS 118 + +static struct irq_domain *irq_domain; + +/* Register offsets for the GPIO device */ + +#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) /* LSW Mask & + Data -WO */ +#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) /* MSW Mask & + Data -WO */ +#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK)) /* Data Register + -RW */ +#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) /* Direction + mode reg-RW */ +#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) /* Output + enable reg-RW + */ +#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) /* Interrupt + mask reg-RO */ +#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) /* Interrupt + enable reg-WO + */ +#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) /* Interrupt + disable reg-WO + */ +#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) /* Interrupt + status reg-RO + */ +#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) /* Interrupt + type reg-RW + */ +#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) /* Interrupt + polarity reg + -RW */ +#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) /* Interrupt on + any, reg-RW */ + +/* Read/Write access to the GPIO PS registers */ +#define zynq_gpio_readreg(offset) __raw_readl(offset) +#define zynq_gpio_writereg(val, offset) __raw_writel(val, offset) + +static unsigned int zynq_gpio_pin_table[] = { + 31, /* 0 - 31 */ + 53, /* 32 - 53 */ + 85, /* 54 - 85 */ + 117 /* 86 - 117 */ +}; + +/** + * struct zynq_gpio - gpio device private data structure + * @chip: instance of the gpio_chip + * @base_addr: base address of the GPIO device + * @gpio_lock: lock used for synchronization + */ +struct zynq_gpio { + struct gpio_chip chip; + void __iomem *base_addr; + unsigned int irq; + unsigned int irq_base; + struct clk *clk; + spinlock_t gpio_lock; +}; + +/** + * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank + * for a given pin in the GPIO device + * @pin_num: gpio pin number within the device + * @bank_num: an output parameter used to return the bank number of the gpio + * pin + * @bank_pin_num: an output parameter used to return pin number within a bank + * for the given gpio pin + * + * Returns the bank number. + */ +static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, + unsigned int *bank_num, + unsigned int *bank_pin_num) +{ + for (*bank_num = 0; *bank_num < 4; (*bank_num)++) + if (pin_num <= zynq_gpio_pin_table[*bank_num]) + break; + + if (*bank_num == 0) + *bank_pin_num = pin_num; + else + *bank_pin_num = pin_num % (zynq_gpio_pin_table[*bank_num - 1] + + 1); +} + +/** + * zynq_gpio_get_value - Get the state of the specified pin of GPIO device + * @chip: gpio_chip instance to be worked on + * @pin: gpio pin number within the device + * + * This function reads the state of the specified pin of the GPIO device. + * It returns 0 if the pin is low, 1 if pin is high. + */ +static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin) +{ + unsigned int bank_num, bank_pin_num; + struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); + + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); + + return (zynq_gpio_readreg(gpio->base_addr + + ZYNQ_GPIO_DATA_OFFSET(bank_num)) >> + bank_pin_num) & 1; +} + +/** + * zynq_gpio_set_value - Modify the state of the pin with specified value + * @chip: gpio_chip instance to be worked on + * @pin: gpio pin number within the device + * @state: value used to modify the state of the specified pin + * + * This function calculates the register offset (i.e to lower 16 bits or + * upper 16 bits) based on the given pin number and sets the state of a + * gpio pin to the specified value. The state is either 0 or non-zero. + */ +static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, + int state) +{ + unsigned long flags; + unsigned int reg_offset; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); + + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); + + if (bank_pin_num >= 16) { + bank_pin_num -= 16; /* only 16 data bits in bit maskable reg */ + reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); + } else { + reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); + } + + /* + * get the 32 bit value to be written to the mask/data register where + * the upper 16 bits is the mask and lower 16 bits is the data + */ + if (state) + state = 1; + state = ~(1 << (bank_pin_num + 16)) & ((state << bank_pin_num) | + 0xFFFF0000); + + spin_lock_irqsave(&gpio->gpio_lock, flags); + zynq_gpio_writereg(state, gpio->base_addr + reg_offset); + spin_unlock_irqrestore(&gpio->gpio_lock, flags); +} + +/** + * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input + * @chip: gpio_chip instance to be worked on + * @pin: gpio pin number within the device + * + * This function uses the read-modify-write sequence to set the direction of + * the gpio pin as input. Returns 0 always. + */ +static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) +{ + unsigned int reg, bank_num, bank_pin_num; + struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); + + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); + /* clear the bit in direction mode reg to set the pin as input */ + reg = zynq_gpio_readreg(gpio->base_addr + + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + reg &= ~(1 << bank_pin_num); + zynq_gpio_writereg(reg, gpio->base_addr + + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + + return 0; +} + +/** + * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output + * @chip: gpio_chip instance to be worked on + * @pin: gpio pin number within the device + * @state: value to be written to specified pin + * + * This function sets the direction of specified GPIO pin as output, configures + * the Output Enable register for the pin and uses zynq_gpio_set to set + * the state of the pin to the value specified. Returns 0 always. + */ +static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, + int state) +{ + struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); + unsigned int reg, bank_num, bank_pin_num; + + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); + + /* set the GPIO pin as output */ + reg = zynq_gpio_readreg(gpio->base_addr + + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + reg |= 1 << bank_pin_num; + zynq_gpio_writereg(reg, gpio->base_addr + + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + + /* configure the output enable reg for the pin */ + reg = zynq_gpio_readreg(gpio->base_addr + + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); + reg |= 1 << bank_pin_num; + zynq_gpio_writereg(reg, gpio->base_addr + + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); + + /* set the state of the pin */ + zynq_gpio_set_value(chip, pin, state); + return 0; +} + +static int zynq_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return irq_find_mapping(irq_domain, offset); +} + +/** + * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin + * @irq_data: irq data containing irq number of gpio pin for the interrupt + * to ack + * + * This function calculates gpio pin number from irq number and sets the bit + * in the Interrupt Status Register of the corresponding bank, to ACK the irq. + */ +static void zynq_gpio_irq_ack(struct irq_data *irq_data) +{ + struct zynq_gpio *gpio = (struct zynq_gpio *) + irq_data_get_irq_chip_data(irq_data); + unsigned int device_pin_num, bank_num, bank_pin_num; + + device_pin_num = irq_data->hwirq; + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); + zynq_gpio_writereg(1 << bank_pin_num, gpio->base_addr + + (ZYNQ_GPIO_INTSTS_OFFSET(bank_num))); +} + +/** + * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin + * @irq: irq number of gpio pin for which interrupt is to be disabled + * + * This function calculates gpio pin number from irq number and sets the + * bit in the Interrupt Disable register of the corresponding bank to disable + * interrupts for that pin. + */ +static void zynq_gpio_irq_mask(struct irq_data *irq_data) +{ + struct zynq_gpio *gpio = (struct zynq_gpio *) + irq_data_get_irq_chip_data(irq_data); + unsigned int device_pin_num, bank_num, bank_pin_num; + + device_pin_num = irq_data->hwirq; + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); + zynq_gpio_writereg(1 << bank_pin_num, + gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); +} + +/** + * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin + * @irq_data: irq data containing irq number of gpio pin for the interrupt + * to enable + * + * This function calculates the gpio pin number from irq number and sets the + * bit in the Interrupt Enable register of the corresponding bank to enable + * interrupts for that pin. + */ +static void zynq_gpio_irq_unmask(struct irq_data *irq_data) +{ + struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data); + unsigned int device_pin_num, bank_num, bank_pin_num; + + device_pin_num = irq_data->hwirq; + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); + zynq_gpio_writereg(1 << bank_pin_num, + gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); +} + +/** + * zynq_gpio_set_irq_type - Set the irq type for a gpio pin + * @irq_data: irq data containing irq number of gpio pin + * @type: interrupt type that is to be set for the gpio pin + * + * This function gets the gpio pin number and its bank from the gpio pin number + * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers. Returns 0, + * negative error otherwise. + * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0; + * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0; + * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1; + * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA; + * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA + */ +static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type) +{ + struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data); + unsigned int device_pin_num, bank_num, bank_pin_num; + unsigned int int_type, int_pol, int_any; + + device_pin_num = irq_data->hwirq; + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); + + int_type = zynq_gpio_readreg(gpio->base_addr + + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); + int_pol = zynq_gpio_readreg(gpio->base_addr + + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); + int_any = zynq_gpio_readreg(gpio->base_addr + + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); + + /* + * based on the type requested, configure the INT_TYPE, INT_POLARITY + * and INT_ANY registers + */ + switch (type) { + case IRQ_TYPE_EDGE_RISING: + int_type |= (1 << bank_pin_num); + int_pol |= (1 << bank_pin_num); + int_any &= ~(1 << bank_pin_num); + break; + case IRQ_TYPE_EDGE_FALLING: + int_type |= (1 << bank_pin_num); + int_pol &= ~(1 << bank_pin_num); + int_any &= ~(1 << bank_pin_num); + break; + case IRQ_TYPE_EDGE_BOTH: + int_type |= (1 << bank_pin_num); + int_any |= (1 << bank_pin_num); + break; + case IRQ_TYPE_LEVEL_HIGH: + int_type &= ~(1 << bank_pin_num); + int_pol |= (1 << bank_pin_num); + break; + case IRQ_TYPE_LEVEL_LOW: + int_type &= ~(1 << bank_pin_num); + int_pol &= ~(1 << bank_pin_num); + break; + default: + return -EINVAL; + } + + zynq_gpio_writereg(int_type, + gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); + zynq_gpio_writereg(int_pol, + gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); + zynq_gpio_writereg(int_any, + gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); + return 0; +} + +static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on) +{ + if (on) + zynq_gpio_irq_unmask(data); + else + zynq_gpio_irq_mask(data); + + return 0; +} + +/* irq chip descriptor */ +static struct irq_chip zynq_gpio_irqchip = { + .name = DRIVER_NAME, + .irq_ack = zynq_gpio_irq_ack, + .irq_mask = zynq_gpio_irq_mask, + .irq_unmask = zynq_gpio_irq_unmask, + .irq_set_type = zynq_gpio_set_irq_type, + .irq_set_wake = zynq_gpio_set_wake, +}; + +/** + * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device + * @irq: irq number of the gpio bank where interrupt has occurred + * @desc: irq descriptor instance of the 'irq' + * + * This function reads the Interrupt Status Register of each bank to get the + * gpio pin number which has triggered an interrupt. It then acks the triggered + * interrupt and calls the pin specific handler set by the higher layer + * application for that pin. + * Note: A bug is reported if no handler is set for the gpio pin. + */ +static void zynq_gpio_irqhandler(unsigned int irq, struct irq_desc *desc) +{ + struct zynq_gpio *gpio = (struct zynq_gpio *)irq_get_handler_data(irq); + int gpio_irq = gpio->irq_base; + unsigned int int_sts, int_enb, bank_num; + struct irq_desc *gpio_irq_desc; + struct irq_chip *chip = irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + + for (bank_num = 0; bank_num < 4; bank_num++) { + int_sts = zynq_gpio_readreg(gpio->base_addr + + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); + int_enb = zynq_gpio_readreg(gpio->base_addr + + ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); + int_sts &= ~int_enb; + + for (; int_sts != 0; int_sts >>= 1, gpio_irq++) { + if ((int_sts & 1) == 0) + continue; + gpio_irq_desc = irq_to_desc(gpio_irq); + BUG_ON(!gpio_irq_desc); + chip = irq_desc_get_chip(gpio_irq_desc); + BUG_ON(!chip); + chip->irq_ack(&gpio_irq_desc->irq_data); + + /* call the pin specific handler */ + generic_handle_irq(gpio_irq); + } + /* shift to first virtual irq of next bank */ + gpio_irq = gpio->irq_base + zynq_gpio_pin_table[bank_num] + 1; + } + + chip = irq_desc_get_chip(desc); + chained_irq_exit(chip, desc); +} + +#ifdef CONFIG_PM_SLEEP +static int zynq_gpio_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct zynq_gpio *gpio = platform_get_drvdata(pdev); + + if (!device_may_wakeup(dev)) { + if (!pm_runtime_suspended(dev)) + clk_disable(gpio->clk); + return 0; + } + + return 0; +} + +static int zynq_gpio_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct zynq_gpio *gpio = platform_get_drvdata(pdev); + + if (!device_may_wakeup(dev)) { + if (!pm_runtime_suspended(dev)) + return clk_enable(gpio->clk); + } + + return 0; +} +#endif + +#ifdef CONFIG_PM_RUNTIME +static int zynq_gpio_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct zynq_gpio *gpio = platform_get_drvdata(pdev); + + clk_disable(gpio->clk); + + return 0; +} + +static int zynq_gpio_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct zynq_gpio *gpio = platform_get_drvdata(pdev); + + return clk_enable(gpio->clk); +} + +static int zynq_gpio_idle(struct device *dev) +{ + return pm_schedule_suspend(dev, 1); +} + +static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + int ret; + + ret = pm_runtime_get_sync(chip->dev); + + /* + * If the device is already active pm_runtime_get() will return 1 on + * success, but gpio_request still needs to return 0. + */ + return ret < 0 ? ret : 0; +} + +static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pm_runtime_put_sync(chip->dev); +} + +static void zynq_gpio_pm_runtime_init(struct platform_device *pdev) +{ + struct zynq_gpio *gpio = platform_get_drvdata(pdev); + + clk_disable(gpio->clk); + pm_runtime_enable(&pdev->dev); +} + +#else /* ! CONFIG_PM_RUNTIME */ +#define zynq_gpio_request NULL +#define zynq_gpio_free NULL +static void zynq_gpio_pm_runtime_init(struct platform_device *pdev) {} +#endif /* ! CONFIG_PM_RUNTIME */ + +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) +static const struct dev_pm_ops zynq_gpio_dev_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume) + SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend, zynq_gpio_runtime_resume, + zynq_gpio_idle) +}; +#define ZYNQ_GPIO_PM (&zynq_gpio_dev_pm_ops) + +#else /*! CONFIG_PM_RUNTIME || ! CONFIG_PM_SLEEP */ +#define ZYNQ_GPIO_PM NULL +#endif /*! CONFIG_PM_RUNTIME */ + +/** + * zynq_gpio_probe - Initialization method for a zynq_gpio device + * @pdev: platform device instance + * + * This function allocates memory resources for the gpio device and registers + * all the banks of the device. It will also set up interrupts for the gpio + * pins. + * Note: Interrupts are disabled for all the banks during initialization. + * Returns 0 on success, negative error otherwise. + */ +static int zynq_gpio_probe(struct platform_device *pdev) +{ + int ret; + unsigned int irq_num; + struct zynq_gpio *gpio; + struct gpio_chip *chip; + struct resource *res; + int pin_num, bank_num, gpio_irq; + + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) + return -ENOMEM; + + spin_lock_init(&gpio->gpio_lock); + + platform_set_drvdata(pdev, gpio); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + gpio->base_addr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(gpio->base_addr)) + return PTR_ERR(gpio->base_addr); + + irq_num = platform_get_irq(pdev, 0); + gpio->irq = irq_num; + + /* configure the gpio chip */ + chip = &gpio->chip; + chip->label = "zynq_gpio"; + chip->owner = THIS_MODULE; + chip->dev = &pdev->dev; + chip->get = zynq_gpio_get_value; + chip->set = zynq_gpio_set_value; + chip->request = zynq_gpio_request; + chip->free = zynq_gpio_free; + chip->direction_input = zynq_gpio_dir_in; + chip->direction_output = zynq_gpio_dir_out; + chip->to_irq = zynq_gpio_to_irq; + chip->dbg_show = NULL; + chip->base = 0; /* default pin base */ + chip->ngpio = ZYNQ_GPIO_NR_GPIOS; + chip->can_sleep = 0; + + gpio->irq_base = irq_alloc_descs(-1, 0, chip->ngpio, 0); + if (gpio->irq_base < 0) { + dev_err(&pdev->dev, "Couldn't allocate IRQ numbers\n"); + return -ENODEV; + } + + irq_domain = irq_domain_add_legacy(pdev->dev.of_node, + chip->ngpio, gpio->irq_base, 0, + &irq_domain_simple_ops, NULL); + + /* report a bug if gpio chip registration fails */ + ret = gpiochip_add(chip); + if (ret < 0) + return ret; + + dev_info(&pdev->dev, "gpio at 0x%08lx mapped to 0x%08lx\n", + (unsigned long)res->start, (unsigned long)gpio->base_addr); + + /* Enable GPIO clock */ + gpio->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(gpio->clk)) { + dev_err(&pdev->dev, "input clock not found.\n"); + gpiochip_remove(chip); + return PTR_ERR(gpio->clk); + } + ret = clk_prepare_enable(gpio->clk); + if (ret) { + dev_err(&pdev->dev, "Unable to enable clock.\n"); + gpiochip_remove(chip); + return ret; + } + + /* disable interrupts for all banks */ + for (bank_num = 0; bank_num < 4; bank_num++) { + zynq_gpio_writereg(0xffffffff, gpio->base_addr + + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); + } + + /* + * set the irq chip, handler and irq chip data for callbacks for + * each pin + */ + for (pin_num = 0; pin_num < min_t(int, ZYNQ_GPIO_NR_GPIOS, + (int)chip->ngpio); pin_num++) { + gpio_irq = irq_find_mapping(irq_domain, pin_num); + irq_set_chip_and_handler(gpio_irq, &zynq_gpio_irqchip, + handle_simple_irq); + irq_set_chip_data(gpio_irq, (void *)gpio); + set_irq_flags(gpio_irq, IRQF_VALID); + } + + irq_set_handler_data(irq_num, (void *)gpio); + irq_set_chained_handler(irq_num, zynq_gpio_irqhandler); + + zynq_gpio_pm_runtime_init(pdev); + + device_set_wakeup_capable(&pdev->dev, 1); + + return 0; + + + return ret; +} + +static int zynq_gpio_remove(struct platform_device *pdev) +{ + struct zynq_gpio *gpio = platform_get_drvdata(pdev); + + clk_disable_unprepare(gpio->clk); + device_set_wakeup_capable(&pdev->dev, 0); + return 0; +} + +static struct of_device_id zynq_gpio_of_match[] = { + { .compatible = "xlnx,ps7-gpio-1.00.a", }, + { /* end of table */} +}; +MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); + +static struct platform_driver zynq_gpio_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .pm = ZYNQ_GPIO_PM, + .of_match_table = zynq_gpio_of_match, + }, + .probe = zynq_gpio_probe, + .remove = zynq_gpio_remove, +}; + +/** + * zynq_gpio_init - Initial driver registration call + */ +static int __init zynq_gpio_init(void) +{ + return platform_driver_register(&zynq_gpio_driver); +} + +postcore_initcall(zynq_gpio_init); Index: linux-3.12.24-rt38-xilinx/drivers/gpio/Kconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/gpio/Kconfig 2014-07-20 22:05:50.183067495 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/gpio/Kconfig 2014-07-20 22:06:35.893313355 +0200 @@ -278,8 +278,16 @@ config GPIO_XILINX bool "Xilinx GPIO support" depends on PPC_OF || MICROBLAZE || ARCH_ZYNQ + select GENERIC_IRQ_CHIP help - Say yes here to support the Xilinx FPGA GPIO device + Say yes here to support the Xilinx AXI/XPS GPIO device + +config GPIO_ZYNQ + tristate "Xilinx ZYNQ GPIO support" + depends on ARCH_ZYNQ + select GENERIC_IRQ_CHIP + help + Say yes here to support Xilinx ZYNQ GPIO controller. config GPIO_VR41XX tristate "NEC VR4100 series General-purpose I/O Uint support" Index: linux-3.12.24-rt38-xilinx/drivers/gpio/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/gpio/Makefile 2014-07-20 22:05:50.182067512 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/gpio/Makefile 2014-07-20 22:06:35.974312019 +0200 @@ -92,3 +92,4 @@ obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o +obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/drm_edid.c =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/gpu/drm/drm_edid.c 2014-07-20 22:05:50.197067264 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/drm_edid.c 2014-07-20 22:06:36.004311524 +0200 @@ -1097,9 +1097,10 @@ * Try to fetch EDID information by calling i2c driver function. */ static int -drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf, +drm_do_probe_ddc_edid(void *data, unsigned char *buf, int block, int len) { + struct i2c_adapter *adapter = data; unsigned char start = block * EDID_LENGTH; unsigned char segment = block >> 1; unsigned char xfers = segment ? 3 : 2; @@ -1155,8 +1156,8 @@ return true; } -static u8 * -drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) +struct edid *drm_do_get_edid(struct drm_connector *connector, + int (*get_edid_block)(void *, unsigned char *buf, int, int), void *data) { int i, j = 0, valid_extensions = 0; u8 *block, *new; @@ -1167,7 +1168,7 @@ /* base block fetch */ for (i = 0; i < 4; i++) { - if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH)) + if (get_edid_block(data, block, 0, EDID_LENGTH)) goto out; if (drm_edid_block_valid(block, 0, print_bad_edid)) break; @@ -1181,7 +1182,7 @@ /* if there's no extensions, we're done */ if (block[0x7e] == 0) - return block; + return (struct edid *)block; new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); if (!new) @@ -1190,7 +1191,7 @@ for (j = 1; j <= block[0x7e]; j++) { for (i = 0; i < 4; i++) { - if (drm_do_probe_ddc_edid(adapter, + if (get_edid_block(data, block + (valid_extensions + 1) * EDID_LENGTH, j, EDID_LENGTH)) goto out; @@ -1218,7 +1219,7 @@ block = new; } - return block; + return (struct edid *)block; carp: if (print_bad_edid) { @@ -1231,6 +1232,7 @@ kfree(block); return NULL; } +EXPORT_SYMBOL_GPL(drm_do_get_edid); /** * Probe DDC presence. @@ -1263,7 +1265,8 @@ struct edid *edid = NULL; if (drm_probe_ddc(adapter)) - edid = (struct edid *)drm_do_get_edid(connector, adapter); + edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, + adapter); return edid; } Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/i2c/adv7511_audio.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/i2c/adv7511_audio.c 2014-07-20 22:06:36.020311260 +0200 @@ -0,0 +1,319 @@ +/* + * Analog Devices ADV7511 HDMI transmitter driver + * + * Copyright 2012 Analog Devices Inc. + * + * Licensed under the GPL-2. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static const struct snd_soc_dapm_widget adv7511_dapm_widgets[] = { + SND_SOC_DAPM_OUTPUT("TMDS"), + SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", 0, SND_SOC_NOPM, 0, 0), +}; + +static const struct snd_soc_dapm_route adv7511_routes[] = { + { "TMDS", NULL, "AIFIN" }, +}; + +static void adv7511_calc_cts_n(unsigned int f_tmds, unsigned int fs, + unsigned int *cts, unsigned int *n) +{ + switch (fs) { + case 32000: + *n = 4096; + break; + case 44100: + *n = 6272; + break; + case 48000: + *n = 6144; + break; + } + + *cts = ((f_tmds * *n) / (128 * fs)) * 1000; +} + +static int adv7511_update_cts_n(struct adv7511 *adv7511) +{ + unsigned int cts = 0; + unsigned int n = 0; + + adv7511_calc_cts_n(adv7511->f_tmds, adv7511->f_audio, &cts, &n); + + regmap_write(adv7511->regmap, ADV7511_REG_N0, (n >> 16) & 0xf); + regmap_write(adv7511->regmap, ADV7511_REG_N1, (n >> 8) & 0xff); + regmap_write(adv7511->regmap, ADV7511_REG_N2, n & 0xff); + + regmap_write(adv7511->regmap, ADV7511_REG_CTS_MANUAL0, + (cts >> 16) & 0xf); + regmap_write(adv7511->regmap, ADV7511_REG_CTS_MANUAL1, + (cts >> 8) & 0xff); + regmap_write(adv7511->regmap, ADV7511_REG_CTS_MANUAL2, + cts & 0xff); + + return 0; +} + +static int adv7511_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_codec *codec = rtd->codec; + struct adv7511 *adv7511 = snd_soc_codec_get_drvdata(codec); + unsigned int rate; + unsigned int len; + + switch (params_rate(params)) { + case 32000: + rate = ADV7511_SAMPLE_FREQ_32000; + break; + case 44100: + rate = ADV7511_SAMPLE_FREQ_44100; + break; + case 48000: + rate = ADV7511_SAMPLE_FREQ_48000; + break; + case 88200: + rate = ADV7511_SAMPLE_FREQ_88200; + break; + case 96000: + rate = ADV7511_SAMPLE_FREQ_96000; + break; + case 176400: + rate = ADV7511_SAMPLE_FREQ_176400; + break; + case 192000: + rate = ADV7511_SAMPLE_FREQ_192000; + break; + default: + return -EINVAL; + } + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + len = ADV7511_I2S_SAMPLE_LEN_16; + break; + case SNDRV_PCM_FORMAT_S18_3LE: + len = ADV7511_I2S_SAMPLE_LEN_18; + break; + case SNDRV_PCM_FORMAT_S20_3LE: + len = ADV7511_I2S_SAMPLE_LEN_20; + break; + case SNDRV_PCM_FORMAT_S24_LE: + len = ADV7511_I2S_SAMPLE_LEN_24; + break; + default: + return -EINVAL; + } + + adv7511->f_audio = params_rate(params); + + adv7511_update_cts_n(adv7511); + + regmap_update_bits(adv7511->regmap, ADV7511_REG_AUDIO_CFG3, + ADV7511_AUDIO_CFG3_LEN_MASK, len); + regmap_update_bits(adv7511->regmap, ADV7511_REG_I2C_FREQ_ID_CFG, + ADV7511_I2C_FREQ_ID_CFG_RATE_MASK, rate << 4); + + return 0; +} + +static int adv7511_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct adv7511 *adv7511 = snd_soc_codec_get_drvdata(codec); + unsigned int audio_source, i2s_format = 0; + unsigned int invert_clock; + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + audio_source = ADV7511_AUDIO_SOURCE_I2S; + i2s_format = ADV7511_I2S_FORMAT_I2S; + break; + case SND_SOC_DAIFMT_RIGHT_J: + audio_source = ADV7511_AUDIO_SOURCE_I2S; + i2s_format = ADV7511_I2S_FORMAT_RIGHT_J; + break; + case SND_SOC_DAIFMT_LEFT_J: + audio_source = ADV7511_AUDIO_SOURCE_I2S; + i2s_format = ADV7511_I2S_FORMAT_LEFT_J; + break; + case SND_SOC_DAIFMT_SPDIF: + audio_source = ADV7511_AUDIO_SOURCE_SPDIF; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + invert_clock = 0; + break; + case SND_SOC_DAIFMT_IB_NF: + invert_clock = 1; + break; + default: + return -EINVAL; + } + + regmap_update_bits(adv7511->regmap, ADV7511_REG_AUDIO_SOURCE, 0x70, + audio_source << 4); + regmap_update_bits(adv7511->regmap, ADV7511_REG_AUDIO_CONFIG, BIT(6), + invert_clock << 6); + regmap_update_bits(adv7511->regmap, ADV7511_REG_I2S_CONFIG, 0x03, + i2s_format); + + adv7511->audio_source = audio_source; + + return 0; +} + +static int adv7511_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct adv7511 *adv7511 = snd_soc_codec_get_drvdata(codec); + + switch (level) { + case SND_SOC_BIAS_ON: + switch (adv7511->audio_source) { + case ADV7511_AUDIO_SOURCE_I2S: + break; + case ADV7511_AUDIO_SOURCE_SPDIF: + regmap_update_bits(adv7511->regmap, + ADV7511_REG_AUDIO_CONFIG, BIT(7), + BIT(7)); + break; + } + break; + case SND_SOC_BIAS_PREPARE: + if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { + adv7511_packet_enable(adv7511, + ADV7511_PACKET_ENABLE_AUDIO_SAMPLE); + adv7511_packet_enable(adv7511, + ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME); + adv7511_packet_enable(adv7511, + ADV7511_PACKET_ENABLE_N_CTS); + } else { + adv7511_packet_disable(adv7511, + ADV7511_PACKET_ENABLE_AUDIO_SAMPLE); + adv7511_packet_disable(adv7511, + ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME); + adv7511_packet_disable(adv7511, + ADV7511_PACKET_ENABLE_N_CTS); + } + break; + case SND_SOC_BIAS_STANDBY: + regmap_update_bits(adv7511->regmap, ADV7511_REG_AUDIO_CONFIG, + BIT(7), 0); + break; + case SND_SOC_BIAS_OFF: + break; + } + codec->dapm.bias_level = level; + return 0; +} + +#define ADV7511_RATES (SNDRV_PCM_RATE_32000 |\ + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000) + +#define ADV7511_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE |\ + SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE) + +static const struct snd_soc_dai_ops adv7511_dai_ops = { + .hw_params = adv7511_hw_params, + /*.set_sysclk = adv7511_set_dai_sysclk,*/ + .set_fmt = adv7511_set_dai_fmt, +}; + +static struct snd_soc_dai_driver adv7511_dai = { + .name = "adv7511", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 2, + .rates = ADV7511_RATES, + .formats = ADV7511_FORMATS, + }, + .ops = &adv7511_dai_ops, +}; + +static int adv7511_suspend(struct snd_soc_codec *codec) +{ + return adv7511_set_bias_level(codec, SND_SOC_BIAS_OFF); +} + +static int adv7511_resume(struct snd_soc_codec *codec) +{ + return adv7511_set_bias_level(codec, SND_SOC_BIAS_STANDBY); +} + +static int adv7511_probe(struct snd_soc_codec *codec) +{ + int ret; + + ret = snd_soc_codec_set_cache_io(codec, 0, 0, SND_SOC_REGMAP); + if (ret < 0) { + dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); + return ret; + } + + return adv7511_set_bias_level(codec, SND_SOC_BIAS_STANDBY); +} + +static int adv7511_remove(struct snd_soc_codec *codec) +{ + adv7511_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static struct snd_soc_codec_driver adv7511_codec_driver = { + .probe = adv7511_probe, + .remove = adv7511_remove, + .suspend = adv7511_suspend, + .resume = adv7511_resume, + .set_bias_level = adv7511_set_bias_level, + + .dapm_widgets = adv7511_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(adv7511_dapm_widgets), + .dapm_routes = adv7511_routes, + .num_dapm_routes = ARRAY_SIZE(adv7511_routes), +}; + +int adv7511_audio_init(struct device *dev) +{ + return snd_soc_register_codec(dev, &adv7511_codec_driver, + &adv7511_dai, 1); +} + +void adv7511_audio_exit(struct device *dev) +{ + snd_soc_unregister_codec(dev); +} Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/i2c/adv7511_core.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/i2c/adv7511_core.c 2014-07-20 22:06:36.034311029 +0200 @@ -0,0 +1,950 @@ +/* + * Analog Devices ADV7511 HDMI transmitter driver + * + * Copyright 2012 Analog Devices Inc. + * + * Licensed under the GPL-2. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +static const uint8_t adv7511_register_defaults[] = { + 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00 */ + 0x00, 0x00, 0x01, 0x0e, 0xbc, 0x18, 0x01, 0x13, + 0x25, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 10 */ + 0x46, 0x62, 0x04, 0xa8, 0x00, 0x00, 0x1c, 0x84, + 0x1c, 0xbf, 0x04, 0xa8, 0x1e, 0x70, 0x02, 0x1e, /* 20 */ + 0x00, 0x00, 0x04, 0xa8, 0x08, 0x12, 0x1b, 0xac, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 */ + 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0xb0, + 0x00, 0x50, 0x90, 0x7e, 0x79, 0x70, 0x00, 0x00, /* 40 */ + 0x00, 0xa8, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x0d, 0x00, 0x00, 0x00, 0x00, /* 50 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 60 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 70 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 80 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, /* 90 */ + 0x0b, 0x02, 0x00, 0x18, 0x5a, 0x60, 0x00, 0x00, + 0x00, 0x00, 0x80, 0x80, 0x08, 0x04, 0x00, 0x00, /* a0 */ + 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x40, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* b0 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* c0 */ + 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x01, 0x04, + 0x30, 0xff, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, /* d0 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, + 0x80, 0x75, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, /* e0 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x11, 0x00, /* f0 */ + 0x00, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +/* ADI recommanded values for proper operation. */ +static const struct reg_default adv7511_fixed_registers[] = { + { 0x98, 0x03 }, + { 0x9a, 0xe0 }, + { 0x9c, 0x30 }, + { 0x9d, 0x61 }, + { 0xa2, 0xa4 }, + { 0xa3, 0xa4 }, + { 0xe0, 0xd0 }, + { 0xf9, 0x00 }, + { 0x55, 0x02 }, +}; + +static struct adv7511 *encoder_to_adv7511(struct drm_encoder *encoder) +{ + return to_encoder_slave(encoder)->slave_priv; +} + +static void adv7511_set_colormap(struct adv7511 *adv7511, bool enable, + const uint16_t *coeff, + unsigned int scaling_factor) +{ + unsigned int i; + + regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(1), + ADV7511_CSC_UPDATE_MODE, ADV7511_CSC_UPDATE_MODE); + + if (enable) { + for (i = 0; i < 12; ++i) { + regmap_update_bits(adv7511->regmap, + ADV7511_REG_CSC_UPPER(i), + 0x1f, coeff[i] >> 8); + regmap_write(adv7511->regmap, + ADV7511_REG_CSC_LOWER(i), + coeff[i] & 0xff); + } + } + + if (enable) + regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(0), + 0xe0, 0x80 | (scaling_factor << 5)); + else + regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(0), + 0x80, 0x00); + + regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(1), + ADV7511_CSC_UPDATE_MODE, 0); +} + +#define ADV7511_HDMI_CFG_MODE_MASK 0x2 +#define ADV7511_HDMI_CFG_MODE_DVI 0x0 +#define ADV7511_HDMI_CFG_MODE_HDMI 0x2 + +#define ADV7511_PACKET_MEM_SPD 0 +#define ADV7511_PACKET_MEM_MPEG 1 +#define ADV7511_PACKET_MEM_ACP 2 +#define ADV7511_PACKET_MEM_ISRC1 3 +#define ADV7511_PACKET_MEM_ISRC2 4 +#define ADV7511_PACKET_MEM_GM 5 +#define ADV7511_PACKET_MEM_SPARE1 6 +#define ADV7511_PACKET_MEM_SPARE2 7 + +#define ADV7511_PACKET_MEM_DATA_REG(x) ((x) * 0x20) +#define ADV7511_PACKET_MEM_UPDATE_REG(x) ((x) * 0x20 + 0x1f) +#define ADV7511_PACKET_MEM_UPDATE_ENABLE BIT(7) + +static void adv7511_set_config(struct drm_encoder *encoder, void *c) +{ + struct adv7511 *adv7511 = encoder_to_adv7511(encoder); + struct adv7511_video_config *config = c; + bool output_format_422, output_format_ycbcr; + unsigned int mode; + uint8_t infoframe[17]; + + if (config->hdmi_mode) { + mode = ADV7511_HDMI_CFG_MODE_HDMI; + + switch (config->avi_infoframe.colorspace) { + case HDMI_COLORSPACE_YUV444: + output_format_422 = false; + output_format_ycbcr = true; + break; + case HDMI_COLORSPACE_YUV422: + output_format_422 = true; + output_format_ycbcr = true; + break; + default: + output_format_422 = false; + output_format_ycbcr = false; + break; + } + } else { + mode = ADV7511_HDMI_CFG_MODE_DVI; + output_format_422 = false; + output_format_ycbcr = false; + } + + adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME); + + adv7511_set_colormap(adv7511, config->csc_enable, + config->csc_coefficents, + config->csc_scaling_factor); + + regmap_update_bits(adv7511->regmap, ADV7511_REG_VIDEO_INPUT_CFG1, 0x81, + (output_format_422 << 7) | output_format_ycbcr); + + regmap_update_bits(adv7511->regmap, ADV7511_REG_HDCP_HDMI_CFG, + ADV7511_HDMI_CFG_MODE_MASK, mode); + + hdmi_avi_infoframe_pack(&config->avi_infoframe, infoframe, + sizeof(infoframe)); + + /* The AVI infoframe id is not configurable */ + regmap_bulk_write(adv7511->regmap, ADV7511_REG_AVI_INFOFRAME_VERSION, + infoframe + 1, sizeof(infoframe) - 1); + + adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME); +} + +static void adv7511_set_link_config(struct adv7511 *adv7511, + const struct adv7511_link_config *config) +{ + enum adv7511_input_sync_pulse sync_pulse; + + switch (config->id) { + case ADV7511_INPUT_ID_12_15_16BIT_RGB444_YCbCr444: + sync_pulse = ADV7511_INPUT_SYNC_PULSE_NONE; + break; + default: + sync_pulse = config->sync_pulse; + break; + } + + switch (config->id) { + case ADV7511_INPUT_ID_16_20_24BIT_YCbCr422_EMBEDDED_SYNC: + case ADV7511_INPUT_ID_8_10_12BIT_YCbCr422_EMBEDDED_SYNC: + adv7511->embedded_sync = true; + break; + default: + adv7511->embedded_sync = false; + break; + } + + regmap_update_bits(adv7511->regmap, ADV7511_REG_I2C_FREQ_ID_CFG, 0xf, + config->id); + regmap_update_bits(adv7511->regmap, ADV7511_REG_VIDEO_INPUT_CFG1, 0x7e, + (config->input_color_depth << 4) | + (config->input_style << 2)); + regmap_write(adv7511->regmap, ADV7511_REG_VIDEO_INPUT_CFG2, + (config->reverse_bitorder << 6) | + (config->bit_justification << 3)); + regmap_write(adv7511->regmap, ADV7511_REG_TIMING_GEN_SEQ, + (sync_pulse << 2) | (config->timing_gen_seq << 1)); + regmap_write(adv7511->regmap, 0xba, (config->clock_delay << 5)); + + regmap_update_bits(adv7511->regmap, ADV7511_REG_TMDS_CLOCK_INV, 0x08, + config->tmds_clock_inversion << 3); + + adv7511->hsync_polarity = config->hsync_polarity; + adv7511->vsync_polarity = config->vsync_polarity; +} + +int adv7511_packet_enable(struct adv7511 *adv7511, unsigned int packet) +{ + if (packet & 0xff) + regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE0, + packet, 0xff); + + if (packet & 0xff00) { + packet >>= 8; + regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE1, + packet, 0xff); + } + + return 0; +} + +int adv7511_packet_disable(struct adv7511 *adv7511, unsigned int packet) +{ + if (packet & 0xff) + regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE0, + packet, 0x00); + + if (packet & 0xff00) { + packet >>= 8; + regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE1, + packet, 0x00); + } + + return 0; +} + +static bool adv7511_register_volatile(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ADV7511_REG_SPDIF_FREQ: + case ADV7511_REG_CTS_AUTOMATIC1: + case ADV7511_REG_CTS_AUTOMATIC2: + case ADV7511_REG_VIC_DETECTED: + case ADV7511_REG_VIC_SEND: + case ADV7511_REG_AUX_VIC_DETECTED: + case ADV7511_REG_STATUS: + case ADV7511_REG_GC(1): + case ADV7511_REG_INT(0): + case ADV7511_REG_INT(1): + case ADV7511_REG_PLL_STATUS: + case ADV7511_REG_AN(0): + case ADV7511_REG_AN(1): + case ADV7511_REG_AN(2): + case ADV7511_REG_AN(3): + case ADV7511_REG_AN(4): + case ADV7511_REG_AN(5): + case ADV7511_REG_AN(6): + case ADV7511_REG_AN(7): + case ADV7511_REG_HDCP_STATUS: + case ADV7511_REG_BCAPS: + case ADV7511_REG_BKSV(0): + case ADV7511_REG_BKSV(1): + case ADV7511_REG_BKSV(2): + case ADV7511_REG_BKSV(3): + case ADV7511_REG_BKSV(4): + case ADV7511_REG_DDC_STATUS: + case ADV7511_REG_BSTATUS(0): + case ADV7511_REG_BSTATUS(1): + case ADV7511_REG_CHIP_ID_HIGH: + case ADV7511_REG_CHIP_ID_LOW: + return true; + } + + return false; +} + +static bool adv7511_hpd(struct adv7511 *adv7511) +{ + unsigned int irq0; + int ret; + + ret = regmap_read(adv7511->regmap, ADV7511_REG_INT(0), &irq0); + if (ret < 0) + return false; + + if (irq0 & ADV7511_INT0_HDP) { + regmap_write(adv7511->regmap, ADV7511_REG_INT(0), + ADV7511_INT0_HDP); + return true; + } + + return false; +} + +static irqreturn_t adv7511_irq_handler(int irq, void *devid) +{ + struct adv7511 *adv7511 = devid; + + if (adv7511_hpd(adv7511)) + drm_helper_hpd_irq_event(adv7511->encoder->dev); + + wake_up_all(&adv7511->wq); + + return IRQ_HANDLED; +} + +static unsigned int adv7511_is_interrupt_pending(struct adv7511 *adv7511, + unsigned int irq) +{ + unsigned int irq0, irq1; + unsigned int pending; + int ret; + + ret = regmap_read(adv7511->regmap, ADV7511_REG_INT(0), &irq0); + if (ret < 0) + return 0; + ret = regmap_read(adv7511->regmap, ADV7511_REG_INT(1), &irq1); + if (ret < 0) + return 0; + + pending = (irq1 << 8) | irq0; + + return pending & irq; +} + +static int adv7511_wait_for_interrupt(struct adv7511 *adv7511, int irq, + int timeout) +{ + unsigned int pending = 0; + int ret; + + if (adv7511->i2c_main->irq) { + ret = wait_event_interruptible_timeout(adv7511->wq, + adv7511_is_interrupt_pending(adv7511, irq), + msecs_to_jiffies(timeout)); + if (ret <= 0) + return 0; + pending = adv7511_is_interrupt_pending(adv7511, irq); + } else { + if (timeout < 25) + timeout = 25; + do { + pending = adv7511_is_interrupt_pending(adv7511, irq); + if (pending) + break; + msleep(25); + timeout -= 25; + } while (timeout >= 25); + } + + return pending; +} + +static int adv7511_get_edid_block(void *data, unsigned char *buf, int block, + int len) +{ + struct drm_encoder *encoder = data; + struct adv7511 *adv7511 = encoder_to_adv7511(encoder); + struct i2c_msg xfer[2]; + uint8_t offset; + int i; + int ret; + + if (len > 128) + return -EINVAL; + + if (adv7511->current_edid_segment != block / 2) { + unsigned int status; + + ret = regmap_read(adv7511->regmap, ADV7511_REG_DDC_STATUS, + &status); + if (ret < 0) + return ret; + + if (status != 2) { + regmap_write(adv7511->regmap, ADV7511_REG_EDID_SEGMENT, + block); + ret = adv7511_wait_for_interrupt(adv7511, + ADV7511_INT0_EDID_READY | + ADV7511_INT1_DDC_ERROR, 200); + + if (!(ret & ADV7511_INT0_EDID_READY)) + return -EIO; + } + + regmap_write(adv7511->regmap, ADV7511_REG_INT(0), + ADV7511_INT0_EDID_READY | ADV7511_INT1_DDC_ERROR); + + /* Break this apart, hopefully more I2C controllers will + * support 64 byte transfers than 256 byte transfers + */ + + xfer[0].addr = adv7511->i2c_edid->addr; + xfer[0].flags = 0; + xfer[0].len = 1; + xfer[0].buf = &offset; + xfer[1].addr = adv7511->i2c_edid->addr; + xfer[1].flags = I2C_M_RD; + xfer[1].len = 64; + xfer[1].buf = adv7511->edid_buf; + + offset = 0; + + for (i = 0; i < 4; ++i) { + ret = i2c_transfer(adv7511->i2c_edid->adapter, xfer, + ARRAY_SIZE(xfer)); + if (ret < 0) + return ret; + else if (ret != 2) + return -EIO; + + xfer[1].buf += 64; + offset += 64; + } + + adv7511->current_edid_segment = block / 2; + } + + if (block % 2 == 0) + memcpy(buf, adv7511->edid_buf, len); + else + memcpy(buf, adv7511->edid_buf + 128, len); + + return 0; +} + +static int adv7511_get_modes(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct adv7511 *adv7511 = encoder_to_adv7511(encoder); + struct edid *edid; + unsigned int count; + + /* Reading the EDID only works if the device is powered */ + if (adv7511->dpms_mode != DRM_MODE_DPMS_ON) { + regmap_write(adv7511->regmap, ADV7511_REG_INT(0), + ADV7511_INT0_EDID_READY | ADV7511_INT1_DDC_ERROR); + regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, + ADV7511_POWER_POWER_DOWN, 0); + adv7511->current_edid_segment = -1; + } + + edid = drm_do_get_edid(connector, adv7511_get_edid_block, encoder); + + if (adv7511->dpms_mode != DRM_MODE_DPMS_ON) + regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, + ADV7511_POWER_POWER_DOWN, + ADV7511_POWER_POWER_DOWN); + + adv7511->edid = edid; + if (!edid) + return 0; + + drm_mode_connector_update_edid_property(connector, edid); + count = drm_add_edid_modes(connector, edid); + + kfree(adv7511->edid); + + return count; +} + +struct edid *adv7511_get_edid(struct drm_encoder *encoder) +{ + struct adv7511 *adv7511 = encoder_to_adv7511(encoder); + + if (!adv7511->edid) + return NULL; + + return kmemdup(adv7511->edid, sizeof(*adv7511->edid) + + adv7511->edid->extensions * 128, GFP_KERNEL); +} +EXPORT_SYMBOL_GPL(adv7511_get_edid); + +static void adv7511_encoder_dpms(struct drm_encoder *encoder, int mode) +{ + struct adv7511 *adv7511 = encoder_to_adv7511(encoder); + + switch (mode) { + case DRM_MODE_DPMS_ON: + adv7511->current_edid_segment = -1; + + regmap_write(adv7511->regmap, ADV7511_REG_INT(0), + ADV7511_INT0_EDID_READY | ADV7511_INT1_DDC_ERROR); + regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, + ADV7511_POWER_POWER_DOWN, 0); + /* + * Per spec it is allowed to pulse the HDP signal to indicate + * that the EDID information has changed. Some monitors do this + * when they wakeup from standby or are enabled. When the HDP + * goes low the adv7511 is reset and the outputs are disabled + * which might cause the monitor to go to standby again. To + * avoid this we ignore the HDP pin for the first few seconds + * after enabeling the output. + */ + regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2, + ADV7511_REG_POWER2_HDP_SRC_MASK, + ADV7511_REG_POWER2_HDP_SRC_NONE); + /* Most of the registers are reset during power down or + * when HPD is low + */ + regcache_sync(adv7511->regmap); + break; + default: + /* TODO: setup additional power down modes */ + regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, + ADV7511_POWER_POWER_DOWN, + ADV7511_POWER_POWER_DOWN); + regcache_mark_dirty(adv7511->regmap); + break; + } + + adv7511->dpms_mode = mode; +} + +static enum drm_connector_status +adv7511_encoder_detect(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct adv7511 *adv7511 = encoder_to_adv7511(encoder); + enum drm_connector_status status; + unsigned int val; + bool hpd; + int ret; + + ret = regmap_read(adv7511->regmap, ADV7511_REG_STATUS, &val); + if (ret < 0) + return connector_status_disconnected; + + if (val & ADV7511_STATUS_HPD) + status = connector_status_connected; + else + status = connector_status_disconnected; + + hpd = adv7511_hpd(adv7511); + + /* The chip resets itself when the cable is disconnected, so in case + * there is a pending HPD interrupt and the cable is connected there was + * at least on transition from disconnected to connected and the chip + * has to be reinitialized. */ + if (status == connector_status_connected && hpd && + adv7511->dpms_mode == DRM_MODE_DPMS_ON) { + regcache_mark_dirty(adv7511->regmap); + adv7511_encoder_dpms(encoder, adv7511->dpms_mode); + adv7511_get_modes(encoder, connector); + status = connector_status_disconnected; + } else { + /* Renable HDP sensing */ + regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2, + ADV7511_REG_POWER2_HDP_SRC_MASK, + ADV7511_REG_POWER2_HDP_SRC_BOTH); + } + + adv7511->status = status; + return status; +} + +static void adv7511_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + struct adv7511 *adv7511 = encoder_to_adv7511(encoder); + unsigned int low_refresh_rate; + unsigned int hsync_polarity = 0; + unsigned int vsync_polarity = 0; + + if (adv7511->embedded_sync) { + unsigned int hsync_offset, hsync_len; + unsigned int vsync_offset, vsync_len; + + hsync_offset = adj_mode->crtc_hsync_start - + adj_mode->crtc_hdisplay; + vsync_offset = adj_mode->crtc_vsync_start - + adj_mode->crtc_vdisplay; + hsync_len = adj_mode->crtc_hsync_end - + adj_mode->crtc_hsync_start; + vsync_len = adj_mode->crtc_vsync_end - + adj_mode->crtc_vsync_start; + + /* The hardware vsync generator has a off-by-one bug */ + vsync_offset += 1; + + regmap_write(adv7511->regmap, ADV7511_REG_HSYNC_PLACEMENT_MSB, + ((hsync_offset >> 10) & 0x7) << 5); + regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(0), + (hsync_offset >> 2) & 0xff); + regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(1), + ((hsync_offset & 0x3) << 6) | + ((hsync_len >> 4) & 0x3f)); + regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(2), + ((hsync_len & 0xf) << 4) | + ((vsync_offset >> 6) & 0xf)); + regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(3), + ((vsync_offset & 0x3f) << 2) | + ((vsync_len >> 8) & 0x3)); + regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(4), + vsync_len & 0xff); + + hsync_polarity = !(adj_mode->flags & DRM_MODE_FLAG_PHSYNC); + vsync_polarity = !(adj_mode->flags & DRM_MODE_FLAG_PVSYNC); + } else { + enum adv7511_sync_polarity mode_hsync_polarity; + enum adv7511_sync_polarity mode_vsync_polarity; + + /** + * If the input signal is always low or always high we want to + * invert or let it passthrough depending on the polarity of the + * current mode. + **/ + if (adj_mode->flags & DRM_MODE_FLAG_NHSYNC) + mode_hsync_polarity = ADV7511_SYNC_POLARITY_LOW; + else + mode_hsync_polarity = ADV7511_SYNC_POLARITY_HIGH; + + if (adj_mode->flags & DRM_MODE_FLAG_NVSYNC) + mode_vsync_polarity = ADV7511_SYNC_POLARITY_LOW; + else + mode_vsync_polarity = ADV7511_SYNC_POLARITY_HIGH; + + if (adv7511->hsync_polarity != mode_hsync_polarity && + adv7511->hsync_polarity != + ADV7511_SYNC_POLARITY_PASSTHROUGH) + hsync_polarity = 1; + + if (adv7511->vsync_polarity != mode_vsync_polarity && + adv7511->vsync_polarity != + ADV7511_SYNC_POLARITY_PASSTHROUGH) + vsync_polarity = 1; + } + + if (mode->vrefresh <= 24000) + low_refresh_rate = ADV7511_LOW_REFRESH_RATE_24HZ; + else if (mode->vrefresh <= 25000) + low_refresh_rate = ADV7511_LOW_REFRESH_RATE_25HZ; + else if (mode->vrefresh <= 30000) + low_refresh_rate = ADV7511_LOW_REFRESH_RATE_30HZ; + else + low_refresh_rate = ADV7511_LOW_REFRESH_RATE_NONE; + + regmap_update_bits(adv7511->regmap, 0xfb, + 0x6, low_refresh_rate << 1); + regmap_update_bits(adv7511->regmap, 0x17, + 0x60, (vsync_polarity << 6) | (hsync_polarity << 5)); + + adv7511->f_tmds = mode->clock; +} + +static struct drm_encoder_slave_funcs adv7511_encoder_funcs = { + .set_config = adv7511_set_config, + .dpms = adv7511_encoder_dpms, + /* .destroy = adv7511_encoder_destroy,*/ + .mode_set = adv7511_encoder_mode_set, + .detect = adv7511_encoder_detect, + .get_modes = adv7511_get_modes, +}; + +static const struct regmap_config adv7511_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = 0xff, + .cache_type = REGCACHE_RBTREE, + .reg_defaults_raw = adv7511_register_defaults, + .num_reg_defaults_raw = ARRAY_SIZE(adv7511_register_defaults), + + .volatile_reg = adv7511_register_volatile, +}; + +/* + adi,input-id - + 0x00: + 0x01: + 0x02: + 0x03: + 0x04: + 0x05: + adi,sync-pulse - Selects the sync pulse + 0x00: Use the DE signal as sync pulse + 0x01: Use the HSYNC signal as sync pulse + 0x02: Use the VSYNC signal as sync pulse + 0x03: No external sync pulse + adi,bit-justification - + 0x00: Evently + 0x01: Right + 0x02: Left + adi,up-conversion - + 0x00: zero-order up conversion + 0x01: first-order up conversion + adi,timing-generation-sequence - + 0x00: Sync adjustment first, then DE generation + 0x01: DE generation first then sync adjustment + adi,vsync-polarity - Polarity of the vsync signal + 0x00: Passthrough + 0x01: Active low + 0x02: Active high + adi,hsync-polarity - Polarity of the hsync signal + 0x00: Passthrough + 0x01: Active low + 0x02: Active high + adi,reverse-bitorder - If set the bitorder is reveresed + adi,tmds-clock-inversion - If set use tdms clock inversion + adi,clock-delay - Clock delay for the video data clock + 0x00: -1200 ps + 0x01: -800 ps + 0x02: -400 ps + 0x03: no dealy + 0x04: 400 ps + 0x05: 800 ps + 0x06: 1200 ps + 0x07: 1600 ps + adi,input-style - Specifies the input style used + 0x02: Use input style 1 + 0x01: Use input style 2 + 0x03: Use Input style 3 + adi,input-color-depth - Selects the input format color depth + 0x03: 8-bit per channel + 0x01: 10-bit per channel + 0x02: 12-bit per channel +*/ + +static int adv7511_parse_dt(struct device_node *np, + struct adv7511_link_config *config) +{ + int ret; + + ret = of_property_read_u32(np, "adi,input-id", &config->id); + if (ret < 0) + return ret; + + config->sync_pulse = ADV7511_INPUT_SYNC_PULSE_NONE; + of_property_read_u32(np, "adi,sync-pulse", &config->sync_pulse); + + ret = of_property_read_u32(np, "adi,bit-justification", + &config->bit_justification); + if (ret < 0) + return ret; + + config->up_conversion = ADV7511_UP_CONVERSION_ZERO_ORDER; + of_property_read_u32(np, "adi,up-conversion", &config->up_conversion); + + ret = of_property_read_u32(np, "adi,timing-generation-sequence", + &config->timing_gen_seq); + if (ret < 0) + return ret; + + ret = of_property_read_u32(np, "adi,vsync-polarity", + &config->vsync_polarity); + if (ret < 0) + return ret; + + ret = of_property_read_u32(np, "adi,hsync-polarity", + &config->hsync_polarity); + if (ret < 0) + return ret; + + config->reverse_bitorder = of_property_read_bool(np, + "adi,reverse-bitorder"); + config->tmds_clock_inversion = of_property_read_bool(np, + "adi,tmds-clock-inversion"); + + ret = of_property_read_u32(np, "adi,clock-delay", + &config->clock_delay); + if (ret) + return ret; + + ret = of_property_read_u32(np, "adi,input-style", + &config->input_style); + if (ret) + return ret; + + ret = of_property_read_u32(np, "adi,input-color-depth", + &config->input_color_depth); + if (ret) + return ret; + + config->gpio_pd = of_get_gpio(np, 0); + if (config->gpio_pd == -EPROBE_DEFER) + return -EPROBE_DEFER; + + return 0; +} + +static const int edid_i2c_addr = 0x7e; +static const int packet_i2c_addr = 0x70; +static const int cec_i2c_addr = 0x78; + +static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id) +{ + struct adv7511_link_config link_config; + struct adv7511 *adv7511; + struct device *dev = &i2c->dev; + unsigned int val; + int ret; + + if (dev->of_node) { + ret = adv7511_parse_dt(dev->of_node, &link_config); + if (ret) + return ret; + } else { + if (!dev->platform_data) + return -EINVAL; + link_config = *(struct adv7511_link_config *)dev->platform_data; + } + + adv7511 = devm_kzalloc(dev, sizeof(*adv7511), GFP_KERNEL); + if (!adv7511) + return -ENOMEM; + + adv7511->gpio_pd = link_config.gpio_pd; + + if (gpio_is_valid(adv7511->gpio_pd)) { + ret = devm_gpio_request_one(dev, adv7511->gpio_pd, + GPIOF_OUT_INIT_HIGH, "PD"); + if (ret) + return ret; + mdelay(5); + gpio_set_value_cansleep(adv7511->gpio_pd, 0); + } + + adv7511->regmap = devm_regmap_init_i2c(i2c, &adv7511_regmap_config); + if (IS_ERR(adv7511->regmap)) + return PTR_ERR(adv7511->regmap); + + ret = regmap_read(adv7511->regmap, ADV7511_REG_CHIP_REVISION, &val); + if (ret) + return ret; + dev_dbg(dev, "Rev. %d\n", val); + + ret = regmap_register_patch(adv7511->regmap, adv7511_fixed_registers, + ARRAY_SIZE(adv7511_fixed_registers)); + if (ret) + return ret; + + regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR, edid_i2c_addr); + regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR, + packet_i2c_addr); + regmap_write(adv7511->regmap, ADV7511_REG_CEC_I2C_ADDR, cec_i2c_addr); + adv7511_packet_disable(adv7511, 0xffff); + + adv7511->i2c_main = i2c; + adv7511->i2c_edid = i2c_new_dummy(i2c->adapter, edid_i2c_addr >> 1); + adv7511->i2c_packet = i2c_new_dummy(i2c->adapter, packet_i2c_addr >> 1); + if (!adv7511->i2c_edid) + return -ENOMEM; + + if (i2c->irq) { + ret = request_threaded_irq(i2c->irq, NULL, adv7511_irq_handler, + IRQF_ONESHOT, dev_name(dev), + adv7511); + if (ret) + goto err_i2c_unregister_device; + + init_waitqueue_head(&adv7511->wq); + } + + /* CEC is unused for now */ + regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL, + ADV7511_CEC_CTRL_POWER_DOWN); + + regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, + ADV7511_POWER_POWER_DOWN, ADV7511_POWER_POWER_DOWN); + + adv7511->current_edid_segment = -1; + + i2c_set_clientdata(i2c, adv7511); + adv7511_audio_init(dev); + + adv7511_set_link_config(adv7511, &link_config); + + return 0; + +err_i2c_unregister_device: + i2c_unregister_device(adv7511->i2c_edid); + + return ret; +} + +static int adv7511_remove(struct i2c_client *i2c) +{ + struct adv7511 *adv7511 = i2c_get_clientdata(i2c); + + i2c_unregister_device(adv7511->i2c_edid); + + if (i2c->irq) + free_irq(i2c->irq, adv7511); + kfree(adv7511->edid); + + return 0; +} + +static int adv7511_encoder_init(struct i2c_client *i2c, struct drm_device *dev, + struct drm_encoder_slave *encoder) +{ + + struct adv7511 *adv7511 = i2c_get_clientdata(i2c); + + encoder->slave_priv = adv7511; + encoder->slave_funcs = &adv7511_encoder_funcs; + + adv7511->encoder = &encoder->base; + + return 0; +} + +static const struct i2c_device_id adv7511_ids[] = { + { "adv7511", 0 }, + {} +}; + +static struct drm_i2c_encoder_driver adv7511_driver = { + .i2c_driver = { + .driver = { + .name = "adv7511", + }, + .id_table = adv7511_ids, + .probe = adv7511_probe, + .remove = adv7511_remove, + }, + + .encoder_init = adv7511_encoder_init, +}; + +static int adv7511_init(void) +{ + return drm_i2c_encoder_register(THIS_MODULE, &adv7511_driver); +} +module_init(adv7511_init); + +static void adv7511_exit(void) +{ + drm_i2c_encoder_unregister(&adv7511_driver); +} +module_exit(adv7511_exit); + +MODULE_AUTHOR("Lars-Peter Clausen "); +MODULE_DESCRIPTION("ADV7511 HDMI transmitter driver"); +MODULE_LICENSE("GPL"); Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/i2c/Kconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/gpu/drm/i2c/Kconfig 2014-07-20 22:05:50.199067232 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/i2c/Kconfig 2014-07-20 22:06:36.042310897 +0200 @@ -25,4 +25,12 @@ help Support for NXP Semiconductors TDA998X HDMI encoders. +config DRM_ENCODER_ADV7511 + tristate "ADV7511 encoder" + depends on SOUND + depends on SND + depends on SND_SOC + select REGMAP_I2C + select HDMI + endmenu Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/i2c/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/gpu/drm/i2c/Makefile 2014-07-20 22:05:50.198067248 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/i2c/Makefile 2014-07-20 22:06:36.052310732 +0200 @@ -8,3 +8,6 @@ tda998x-y := tda998x_drv.o obj-$(CONFIG_DRM_I2C_NXP_TDA998X) += tda998x.o + +adv7511-y := adv7511_core.o adv7511_audio.o +obj-$(CONFIG_DRM_ENCODER_ADV7511) += adv7511.o Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/Kconfig =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/gpu/drm/Kconfig 2014-07-20 22:05:50.196067281 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/Kconfig 2014-07-20 22:06:36.062310567 +0200 @@ -236,3 +236,5 @@ source "drivers/gpu/drm/qxl/Kconfig" source "drivers/gpu/drm/msm/Kconfig" + +source "drivers/gpu/drm/xilinx/Kconfig" Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/Makefile =================================================================== --- linux-3.12.24-rt38-xilinx.orig/drivers/gpu/drm/Makefile 2014-07-20 22:05:50.195067298 +0200 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/Makefile 2014-07-20 22:06:36.071310419 +0200 @@ -55,4 +55,5 @@ obj-$(CONFIG_DRM_TILCDC) += tilcdc/ obj-$(CONFIG_DRM_QXL) += qxl/ obj-$(CONFIG_DRM_MSM) += msm/ +obj-$(CONFIG_DRM_XILINX) += xilinx/ obj-y += i2c/ Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/Kconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/Kconfig 2014-07-20 22:06:36.084310204 +0200 @@ -0,0 +1,10 @@ +config DRM_XILINX + tristate "Xilinx DRM" + depends on DRM && ARCH_ZYNQ && HAVE_CLK + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + select DRM_GEM_CMA_HELPER + select DRM_ENCODER_ADV7511 + select XILINX_AXIVDMA + help + DRM display driver for Xilinx IP based pipelines. Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/Makefile =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/Makefile 2014-07-20 22:06:36.089310122 +0200 @@ -0,0 +1,9 @@ +# +# Makefile for the drm device driver. This driver provides support for the +# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. + +xilinx_drm-y := xilinx_drm_drv.o xilinx_drm_crtc.o xilinx_drm_plane.o \ + xilinx_drm_encoder.o xilinx_drm_connector.o +xilinx_drm-y += xilinx_cresample.o xilinx_rgb2yuv.o xilinx_osd.o xilinx_vtc.o + +obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/xilinx_cresample.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/xilinx_cresample.c 2014-07-20 22:06:36.096310006 +0200 @@ -0,0 +1,140 @@ +/* + * Xilinx Chroma Resampler support for Xilinx DRM KMS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * Author: Hyun Woo Kwon + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include "xilinx_drm_drv.h" + +/* registers */ +/* general control registers */ +#define CRESAMPLE_CONTROL 0x0000 + +/* horizontal and vertical active frame size */ +#define CRESAMPLE_ACTIVE_SIZE 0x0020 + +/* control register bit definition */ +#define CRESAMPLE_CTL_EN (1 << 0) /* enable */ +#define CRESAMPLE_CTL_RU (1 << 1) /* reg update */ +#define CRESAMPLE_CTL_RESET (1 << 31) /* instant reset */ + +struct xilinx_cresample { + void __iomem *base; + const char *input_format_name; + const char *output_format_name; +}; + +/* enable cresample */ +void xilinx_cresample_enable(struct xilinx_cresample *cresample) +{ + u32 reg; + + reg = xilinx_drm_readl(cresample->base, CRESAMPLE_CONTROL); + xilinx_drm_writel(cresample->base, CRESAMPLE_CONTROL, + reg | CRESAMPLE_CTL_EN); +} + +/* disable cresample */ +void xilinx_cresample_disable(struct xilinx_cresample *cresample) +{ + u32 reg; + + reg = xilinx_drm_readl(cresample->base, CRESAMPLE_CONTROL); + xilinx_drm_writel(cresample->base, CRESAMPLE_CONTROL, + reg & ~CRESAMPLE_CTL_EN); +} + +/* configure cresample */ +void xilinx_cresample_configure(struct xilinx_cresample *cresample, + int hactive, int vactive) +{ + /* configure hsize and vsize */ + xilinx_drm_writel(cresample->base, CRESAMPLE_ACTIVE_SIZE, + (vactive << 16) | hactive); +} + +/* reset cresample */ +void xilinx_cresample_reset(struct xilinx_cresample *cresample) +{ + u32 reg; + + xilinx_drm_writel(cresample->base, CRESAMPLE_CONTROL, + CRESAMPLE_CTL_RESET); + + /* enable register update */ + reg = xilinx_drm_readl(cresample->base, CRESAMPLE_CONTROL); + xilinx_drm_writel(cresample->base, CRESAMPLE_CONTROL, + reg | CRESAMPLE_CTL_RU); +} + +/* get an input format */ +const char * +xilinx_cresample_get_input_format_name(struct xilinx_cresample *cresample) +{ + return cresample->input_format_name; +} + +/* get an output format */ +const char * +xilinx_cresample_get_output_format_name(struct xilinx_cresample *cresample) +{ + return cresample->output_format_name; +} + +struct xilinx_cresample *xilinx_cresample_probe(struct device *dev, + struct device_node *node) +{ + struct xilinx_cresample *cresample; + struct resource res; + int ret; + + cresample = devm_kzalloc(dev, sizeof(*cresample), GFP_KERNEL); + if (!cresample) + return ERR_PTR(-ENOMEM); + + ret = of_address_to_resource(node, 0, &res); + if (ret) { + dev_err(dev, "failed to of_address_to_resource\n"); + return ERR_PTR(ret); + } + + cresample->base = devm_ioremap_resource(dev, &res); + if (IS_ERR(cresample->base)) + return ERR_CAST(cresample->base); + + ret = of_property_read_string(node, "xlnx,input-format", + &cresample->input_format_name); + if (ret) { + dev_warn(dev, "failed to get an input format prop\n"); + return ERR_PTR(ret); + } + + ret = of_property_read_string(node, "xlnx,output-format", + &cresample->output_format_name); + if (ret) { + dev_warn(dev, "failed to get an output format prop\n"); + return ERR_PTR(ret); + } + + xilinx_cresample_reset(cresample); + + return cresample; +} Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/xilinx_cresample.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/xilinx_cresample.h 2014-07-20 22:06:36.102309908 +0200 @@ -0,0 +1,40 @@ +/* + * Xilinx Chroma Resampler Header for Xilinx DRM KMS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * Author: Hyun Woo Kwon + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _XILINX_CRESAMPLE_H_ +#define _XILINX_CRESAMPLE_H_ + +struct xilinx_cresample; + +void xilinx_cresample_configure(struct xilinx_cresample *cresample, + int hactive, int vactive); +void xilinx_cresample_reset(struct xilinx_cresample *cresample); +void xilinx_cresample_enable(struct xilinx_cresample *cresample); +void xilinx_cresample_disable(struct xilinx_cresample *cresample); + +const char * +xilinx_cresample_get_input_format_name(struct xilinx_cresample *cresample); +const char * +xilinx_cresample_get_output_format_name(struct xilinx_cresample *cresample); + +struct device; +struct device_node; + +struct xilinx_cresample *xilinx_cresample_probe(struct device *dev, + struct device_node *node); + +#endif /* _XILINX_CRESAMPLE_H_ */ Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/xilinx_drm_connector.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/xilinx_drm_connector.c 2014-07-20 22:06:36.179308638 +0200 @@ -0,0 +1,168 @@ +/* + * Xilinx DRM connector driver for Xilinx + * + * Copyright (C) 2013 Xilinx, Inc. + * + * Author: Hyun Woo Kwon + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include + +#include "xilinx_drm_drv.h" + +struct xilinx_drm_connector { + struct drm_connector base; + struct drm_encoder *encoder; +}; + +#define to_xilinx_connector(x) \ + container_of(x, struct xilinx_drm_connector, base) + +/* get mode list */ +static int xilinx_drm_connector_get_modes(struct drm_connector *base_connector) +{ + struct xilinx_drm_connector *connector = + to_xilinx_connector(base_connector); + struct drm_encoder *encoder = connector->encoder; + struct drm_encoder_slave *encoder_slave = to_encoder_slave(encoder); + struct drm_encoder_slave_funcs *encoder_sfuncs = + encoder_slave->slave_funcs; + int count = 0; + + if (encoder_sfuncs->get_modes) + count = encoder_sfuncs->get_modes(encoder, base_connector); + + return count; +} + +/* check if mode is valid */ +static int xilinx_drm_connector_mode_valid(struct drm_connector *base_connector, + struct drm_display_mode *mode) +{ + if (mode->clock > 165000) + return MODE_CLOCK_HIGH; + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + return MODE_NO_INTERLACE; + + return MODE_OK; +} + +/* find best encoder: return stored encoder */ +static struct drm_encoder * +xilinx_drm_connector_best_encoder(struct drm_connector *base_connector) +{ + struct xilinx_drm_connector *connector = + to_xilinx_connector(base_connector); + + return connector->encoder; +} + +static struct drm_connector_helper_funcs xilinx_drm_connector_helper_funcs = { + .get_modes = xilinx_drm_connector_get_modes, + .mode_valid = xilinx_drm_connector_mode_valid, + .best_encoder = xilinx_drm_connector_best_encoder, +}; + +static enum drm_connector_status +xilinx_drm_connector_detect(struct drm_connector *base_connector, bool force) +{ + struct xilinx_drm_connector *connector = + to_xilinx_connector(base_connector); + enum drm_connector_status status = connector_status_unknown; + struct drm_encoder *encoder = connector->encoder; + struct drm_encoder_slave *encoder_slave = to_encoder_slave(encoder); + struct drm_encoder_slave_funcs *encoder_sfuncs = + encoder_slave->slave_funcs; + + if (encoder_sfuncs->detect) + status = encoder_sfuncs->detect(encoder, base_connector); + + /* some connector ignores the first hpd, so try again if forced */ + if (force && (status != connector_status_connected)) + status = encoder_sfuncs->detect(encoder, base_connector); + + DRM_DEBUG_KMS("status: %d\n", status); + + return status; +} + +/* destroy connector */ +void xilinx_drm_connector_destroy(struct drm_connector *base_connector) +{ + drm_sysfs_connector_remove(base_connector); + drm_connector_cleanup(base_connector); +} + +static struct drm_connector_funcs xilinx_drm_connector_funcs = { + .dpms = drm_helper_connector_dpms, + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = xilinx_drm_connector_detect, + .destroy = xilinx_drm_connector_destroy, +}; + +/* create connector */ +struct drm_connector * +xilinx_drm_connector_create(struct drm_device *drm, + struct drm_encoder *base_encoder) +{ + struct xilinx_drm_connector *connector; + int ret; + + connector = devm_kzalloc(drm->dev, sizeof(*connector), GFP_KERNEL); + if (!connector) + return ERR_PTR(-ENOMEM); + + connector->base.polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; + + ret = drm_connector_init(drm, &connector->base, + &xilinx_drm_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + if (ret) { + DRM_ERROR("failed to initialize connector\n"); + return ERR_PTR(ret); + } + + drm_connector_helper_add(&connector->base, + &xilinx_drm_connector_helper_funcs); + + /* add sysfs entry for connector */ + ret = drm_sysfs_connector_add(&connector->base); + if (ret) { + DRM_ERROR("failed to add to sysfs\n"); + goto err_sysfs; + } + + /* connect connector and encoder */ + connector->base.encoder = base_encoder; + ret = drm_mode_connector_attach_encoder(&connector->base, base_encoder); + if (ret) { + DRM_ERROR("failed to attach connector to encoder\n"); + goto err_attach; + } + connector->encoder = base_encoder; + + return &connector->base; + +err_attach: + drm_sysfs_connector_remove(&connector->base); +err_sysfs: + drm_connector_cleanup(&connector->base); + return ERR_PTR(ret); +} Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/xilinx_drm_connector.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/xilinx_drm_connector.h 2014-07-20 22:06:36.185308539 +0200 @@ -0,0 +1,29 @@ +/* + * Xilinx DRM connector header for Xilinx + * + * Copyright (C) 2013 Xilinx, Inc. + * + * Author: Hyun Woo Kwon + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _XILINX_DRM_CONNECTOR_H_ +#define _XILINX_DRM_CONNECTOR_H_ + +struct drm_device; +struct drm_connector; + +struct drm_connector * +xilinx_drm_connector_create(struct drm_device *drm, + struct drm_encoder *base_encoder); +void xilinx_drm_connector_destroy(struct drm_connector *base_connector); + +#endif /* _XILINX_DRM_CONNECTOR_H_ */ Index: linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.12.24-rt38-xilinx/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c 2014-07-20 22:06:36.195308374 +0200 @@ -0,0 +1,473 @@ +/* + * Xilinx DRM crtc driver for Xilinx + * + * Copyright (C) 2013 Xilinx, Inc. + * + * Author: Hyun Woo Kwon + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include