From 7dd7062ac8da2e562027a5f79f3072939f939cf5 Mon Sep 17 00:00:00 2001 From: Brian Viele <viele@zee.aero> Date: Fri, 16 Nov 2012 21:40:46 -0800 Subject: [PATCH 1/5] ARM: imx: Enable UART1 for Sabrelite This updates the device tree for the sabrelite to enable UART1 pads in the USDHC3 configuration Signed-off-by: Brian Viele <viele@zee.aero> Signed-off-by: Robert Nelson <robertcnelson@gmail.com> --- arch/arm/boot/dts/imx6q-sabrelite.dts | 6 ++++++ arch/arm/boot/dts/imx6qdl.dtsi | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index f004913..e437606 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -163,6 +163,12 @@ status = "okay"; }; +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>; +}; + &uart2 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 59154dc..71b18f8 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1056,6 +1056,13 @@ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 >; }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x1b0b1 + >; + }; }; uart2 { -- 1.8.4.rc3