diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6dl.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6dl.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl.dtsi 2024-06-19 12:33:57.912185931 +0200 @@ -38,9 +38,13 @@ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; + <&clks IMX6QDL_CLK_PLL1_SYS>, + <&clks IMX6QDL_CLK_PLL1>, + <&clks IMX6QDL_PLL1_BYPASS>, + <&clks IMX6QDL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; @@ -80,29 +84,104 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + soc: soc { - ocram: sram@900000 { + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>, + <&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>, + <&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> , + <&clks IMX6QDL_CLK_PLL3_PFD1_540M>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", + "pll3_usb_otg", "periph", "periph_pre", "periph_clk2", + "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", + "pll3_pfd1_540m"; + interrupts = <0 107 0x4>, <0 112 0x4>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + fsl,max_ddr_freq = <400000000>; + }; + + ocram: sram@905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - ranges = <0 0x00900000 0x20000>; + reg = <0x905000 0x1B000>; + ranges = <0 0x905000 0x1B000>; #address-cells = <1>; #size-cells = <1>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; + ocram_optee: sram@918000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x918000 0x8000>; + overw_reg = <&ocram 0x905000 0x13000>; + }; + + gpu: gpu@00130000 { + compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x10000000 0x0>, <0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_DUMMY>; + clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk", + "gpu2d_clk", "gpu3d_clk", + "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>; + reset-names = "gpu3d", "gpu2d"; + power-domains = <&pd_pu>; + }; + aips1: bus@2000000 { pxp: pxp@20f0000 { - reg = <0x020f0000 0x4000>; + compatible = "fsl,imx6dl-pxp-dma"; + reg = <0x20f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; epdc: epdc@20f4000 { - reg = <0x020f4000 0x4000>; + compatible = "fsl,imx6dl-epdc"; + reg = <0x20f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>; + clock-names = "epdc_axi", "epdc_pix"; }; }; aips2: bus@2100000 { + mipi_dsi: mipi@21e0000 { + compatible = "fsl,imx6dl-mipi-dsi"; + reg = <0x21e0000 0x4000>; + interrupts = <0 102 0x4>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; + }; + i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; @@ -126,6 +205,12 @@ }; }; +&dcic2 { + clocks = <&clks IMX6QDL_CLK_DCIC1 >, + <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/ + clock-names = "dcic", "disp-axi"; +}; + &gpio1 { gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>, <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>, @@ -308,12 +393,19 @@ }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb"; + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; + clock-names = "ldb_di0", "ldb_di1", "di0_sel", "di1_sel", - "di0", "di1"; + "di2_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel"; }; &mipi_csi { @@ -395,3 +487,7 @@ &vpu { compatible = "fsl,imx6dl-vpu", "cnm,coda960"; }; + +&vpu_fsl { + iramsize = <0>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto.dts 2024-06-19 12:33:57.908185862 +0200 @@ -26,3 +26,21 @@ 396000 1175000 >; }; + +&ldb { + lvds-channel@0 { + crtc = "ipu1-di0"; + }; + + lvds-channel@1 { + crtc = "ipu1-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts 2024-06-19 12:33:57.908185862 +0200 @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + + +#include "imx6dl-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto-enetirq.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto-enetirq.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto-enetirq.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto-enetirq.dts 2024-06-19 12:33:57.908185862 +0200 @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2013 Freescale Semiconductor, Inc. +// Copyright 2019 NXP + +#include "imx6dl-sabreauto.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; +}; + +&mlb { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts 2024-06-19 12:33:57.908185862 +0200 @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabreauto.dts" + +&can1{ + status = "okay"; +}; + +&fec { + /* pin conflict with flexcan1 */ + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts 2024-06-19 12:33:57.908185862 +0200 @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + + +#include "imx6dl-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + fsl,use-minimum-ecc; + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto-pcie.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto-pcie.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabreauto-pcie.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabreauto-pcie.dts 2024-06-19 12:33:57.908185862 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6dl-sabreauto.dts" + +&pcie { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-btwifi.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-btwifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-btwifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-btwifi.dts 2024-06-19 12:33:57.908185862 +0200 @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabresd.dts" +#include "imx6qdl-sabresd-btwifi.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd.dts 2024-06-19 12:33:57.908185862 +0200 @@ -12,7 +12,163 @@ compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; }; +&battery { + offset-charger = <1485>; + offset-discharger = <1464>; + offset-usb-charger = <1285>; +}; + +&iomuxc { + epdc { + pinctrl_epdc_elan_touch: epdc_elan_touch_grp { + fsl,pins = < + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000 + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 + >; + }; + + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000 + MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000 + MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000 + MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000 + MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000 + MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000 + MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000 + MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000 + MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000 + MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000 + MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000 + MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000 + MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000 + MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000 + MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000 + MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000 + MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000 + MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000 + MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000 + MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000 + >; + }; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&i2c3 { + elan@10 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_elan_touch>; + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio3>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + gpio_elan_cs = <&gpio2 18 0>; + gpio_elan_rst = <&gpio3 8 0>; + gpio_intr = <&gpio3 28 0>; + status = "okay"; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <1>; + vpos_pwrup = <2>; + gvdd_pwrup = <1>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <1>; + vneg_pwrdn = <1>; + SENSOR-supply = <®_sensors>; + gpio_pmic_pwrgood = <&gpio2 21 0>; + gpio_pmic_vcom_ctrl = <&gpio3 17 0>; + gpio_pmic_wakeup = <&gpio3 20 0>; + gpio_pmic_v3p3 = <&gpio2 20 0>; + gpio_pmic_intr = <&gpio2 25 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + &ipu1_csi1_from_ipu1_csi1_mux { clock-lanes = <0>; data-lanes = <1 2>; }; + +&ldb { + lvds-channel@0 { + crtc = "ipu1-di0"; + }; + + lvds-channel@1 { + crtc = "ipu1-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&pxp { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts 2024-06-19 12:33:57.908185862 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. +// Copyright 2019 NXP + +#include "imx6dl-sabresd.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 0x4>, <&gpc 0 119 0x4>; + fsl,err006687-workaround-present; +}; + +&i2c3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts 2024-06-19 12:33:57.908185862 +0200 @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&battery { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts 2024-06-19 12:33:57.908185862 +0200 @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-pcie.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-pcie.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-pcie.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-pcie.dts 2024-06-19 12:33:57.908185862 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6dl-sabresd.dts" + +&pcie { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-pcie-ep.dts linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-pcie-ep.dts --- linux-6.1.55/arch/arm/boot/dts/imx6dl-sabresd-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6dl-sabresd-pcie-ep.dts 2024-06-19 12:33:57.908185862 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6dl-sabresd.dts" + +&pcie{ + status = "disabled"; +}; + +&pcie_ep{ + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qdl.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6qdl.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6qdl.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qdl.dtsi 2024-06-19 12:33:57.932186273 +0200 @@ -150,6 +150,11 @@ interrupt-parent = <&gpc>; ranges; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x4000>; + }; + dma_apbh: dma-apbh@110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; @@ -212,6 +217,45 @@ }; }; + hdmi_core: hdmi_core@120000 { + compatible = "fsl,imx6q-hdmi-core"; + reg = <0x120000 0x9000>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_video: hdmi_video@20e0000 { + compatible = "fsl,imx6q-hdmi-video"; + reg = <0x20e0000 0x1000>; + reg-names = "hdmi_gpr"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_audio: hdmi_audio@120000 { + compatible = "fsl,imx6q-hdmi-audio"; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + dmas = <&sdma 2 26 0>; + dma-names = "tx"; + status = "disabled"; + }; + + hdmi_cec: hdmi_cec@120000 { + compatible = "fsl,imx6q-hdmi-cec"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + gpu_3d: gpu@130000 { compatible = "vivante,gc"; reg = <0x00130000 0x4000>; @@ -222,6 +266,7 @@ clock-names = "bus", "core", "shader"; power-domains = <&pd_pu>; #cooling-cells = <2>; + status = "disabled"; }; gpu_2d: gpu@134000 { @@ -233,6 +278,19 @@ clock-names = "bus", "core"; power-domains = <&pd_pu>; #cooling-cells = <2>; + status = "disabled"; + }; + + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; }; timer@a00600 { @@ -290,6 +348,20 @@ status = "disabled"; }; + pcie_ep: pcie_ep@1ffc000 { + compatible = "fsl,imx6q-pcie-ep"; + reg = <0x01ffc000 0x04000>, <0x01000000 0xf00000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, + <&clks IMX6QDL_CLK_LVDS1_GATE>, + <&clks IMX6QDL_CLK_PCIE_REF_125M>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + aips1: bus@2000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -314,7 +386,7 @@ clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, - <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, + <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; clock-names = "core", "rxtx0", "rxtx1", "rxtx2", @@ -498,6 +570,24 @@ power-domains = <&pd_pu>; resets = <&src 1>; iram = <&ocram>; + status = "disabled"; + }; + + vpu_fsl: vpu_fsl@2040000 { + compatible = "fsl,imx6-vpu"; + reg = <0x2040000 0x3c000>; + reg-names = "vpu_regs"; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq"; + clocks = <&clks IMX6QDL_CLK_VPU_AXI>, + <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, + <&clks IMX6QDL_CLK_OCRAM>; + clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram"; + iramsize = <0x21000>; + iram = <&ocram>; + resets = <&src 1>; + power-domains = <&pd_pu>; }; aipstz@207c000 { /* AIPSTZ1 */ @@ -755,6 +845,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_pu: regulator-vddpu { @@ -772,6 +863,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_soc: regulator-vddsoc { @@ -789,6 +881,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; tempmon: tempmon { @@ -819,6 +912,20 @@ fsl,anatop = <&anatop>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@20cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x20cc000 0x4000>; + }; + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -920,13 +1027,23 @@ }; dcic1: dcic@20e4000 { - reg = <0x020e4000 0x4000>; + compatible = "fsl,imx6q-dcic"; + reg = <0x20e4000 0x4000>; interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; }; dcic2: dcic@20e8000 { - reg = <0x020e8000 0x4000>; + compatible = "fsl,imx6q-dcic"; + reg = <0x20e8000 0x4000>; interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; }; sdma: dma-controller@20ec000 { @@ -1052,15 +1169,23 @@ <&clks IMX6QDL_CLK_ENET_REF>, <&clks IMX6QDL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp", "enet_out"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>; + assigned-clock-rates = <125000000>; fsl,stop-mode = <&gpr 0x34 27>; + fsl,wakeup_irq = <0>; status = "disabled"; }; - mlb@218c000 { + mlb: mlb@218c000 { + compatible = "fsl,imx6q-mlb150"; reg = <0x0218c000 0x4000>; interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, <0 117 IRQ_TYPE_LEVEL_HIGH>, <0 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_MLB>; + clock-names = "mlb"; + iram = <&ocram>; + status = "disabled"; }; usdhc1: mmc@2190000 { @@ -1145,6 +1270,11 @@ reg = <0x021ac000 0x4000>; }; + mmdc0-1@021b0000 { /* MMDC0-1 */ + compatible = "fsl,imx6q-mmdc-combine"; + reg = <0x021b0000 0x8000>; + }; + mmdc0: memory-controller@21b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; @@ -1205,15 +1335,15 @@ }; mipi_csi: mipi@21dc000 { - compatible = "fsl,imx6-mipi-csi2"; + compatible = "fsl,imx6q-mipi-csi2"; reg = <0x021dc000 0x4000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 100 0x04>, <0 101 0x04>; clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>, - <&clks IMX6QDL_CLK_EIM_PODF>; - clock-names = "dphy", "ref", "pix"; + <&clks IMX6QDL_CLK_EIM_SEL>; + clock-names = "dphy_clk", "cfg_clk", "pixel_clk"; status = "disabled"; }; @@ -1248,6 +1378,7 @@ reg = <0x021e4000 0x4000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_VDOA>; + iram = <&ocram>; }; uart2: serial@21e8000 { @@ -1307,10 +1438,15 @@ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, <0 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, - <&clks IMX6QDL_CLK_IPU1_DI1>; - clock-names = "bus", "di0", "di1"; + <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; resets = <&src 2>; + bypass_reset = <0>; ipu1_csi0: port@0 { reg = <0>; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi 2024-06-19 12:33:57.928186205 +0200 @@ -11,7 +11,14 @@ stdout-path = &uart4; }; - memory@10000000 { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + memory: memory@10000000 { device_type = "memory"; reg = <0x10000000 0x80000000>; }; @@ -84,6 +91,14 @@ regulator-always-on; }; + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_usb_h1_vbus: regulator-usb-h1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_h1_vbus"; @@ -121,6 +136,89 @@ vin-supply = <®_can_en>; }; + reg_si4763_vio1: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vio1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_vio2: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vio2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_vd: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_va: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "va"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_hdmi: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi-5v-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + hdmi-5v-supply = <&swbst_reg>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + sound-cs42888 { compatible = "fsl,imx6-sabreauto-cs42888", "fsl,imx-audio-cs42888"; @@ -143,6 +241,22 @@ "AIN2R", "Line In Jack"; }; + sound-hdmi { + compatible = "fsl,imx6qdl-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + sound-fm { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si4763"; + audio-cpu = <&ssi2>; + audio-codec = <&si476x_codec>; + mux-int-port = <2>; + mux-ext-port = <5>; + }; + sound-spdif { compatible = "fsl,imx-audio-spdif", "fsl,imx-sabreauto-spdif"; @@ -174,19 +288,22 @@ #size-cells = <0>; reg = <1>; - adv7180: camera@21 { - compatible = "adi,adv7180"; + adv7180: adv7180@21 { + compatible = "adv,adv7180"; reg = <0x21>; - powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio1>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_1>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + pwn-gpios = <&max7310_b 2 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + cvbs = <1>; }; max7310_a: gpio@30 { @@ -216,6 +333,7 @@ light-sensor@44 { compatible = "isil,isl29023"; reg = <0x44>; + rext = <499>; interrupt-parent = <&gpio5>; interrupts = <17 IRQ_TYPE_EDGE_FALLING>; }; @@ -237,6 +355,25 @@ }; }; }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; }; &ipu1_csi0_from_ipu1_csi0_mux { @@ -244,7 +381,10 @@ }; &ipu1_csi0_mux_from_parallel_sensor { + /* Downstream driver doesn't use endpoints */ + /* remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; + */ bus-width = <8>; }; @@ -261,11 +401,23 @@ <&clks IMX6QDL_CLK_PLL4_POST_DIV>; assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, <&clks IMX6QDL_PLL4_BYPASS_SRC>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; }; +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds0"; + status = "okay"; +}; + &ecspi1 { cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -296,8 +448,7 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; /delete-property/ interrupts; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,magic-packet; fsl,err006687-workaround-present; fsl,magic-packet; status = "okay"; @@ -306,6 +457,7 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */ xceiver-supply = <®_can_stby>; status = "disabled"; /* pin conflict with fec */ }; @@ -320,13 +472,31 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; + /* enable at -gpmi-weim.dts due to pin conflict */ + status = "disabled"; + nand-on-flash-bbt; +}; + +&hdmi_audio { status = "okay"; }; -&hdmi { +&hdmi_cec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x294>; + fsl,phy_reg_cksymtx = <0x800d>; + HDMI-supply = <®_hdmi>; status = "okay"; }; @@ -455,6 +625,25 @@ interrupts = <28 IRQ_TYPE_EDGE_FALLING>; wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; }; + + si4763: si4763@63 { + compatible = "si4761"; + reg = <0x63>; + va-supply = <®_si4763_va>; + vd-supply = <®_si4763_vd>; + vio1-supply = <®_si4763_vio1>; + vio2-supply = <®_si4763_vio2>; + revision-a10; /* set to default A10 compatible command set */ + + si476x_codec: si476x-codec { + compatible = "si476x-codec"; + }; + }; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &i2c3 { @@ -476,6 +665,14 @@ >; }; + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 @@ -513,6 +710,12 @@ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; @@ -597,6 +800,30 @@ >; }; + pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 @@ -638,6 +865,14 @@ >; }; + pinctrl_mlb: mlb { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000 + MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000 + MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000 + >; + }; + pinctrl_pwm3: pwm1grp { fsl,pins = < MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 @@ -662,6 +897,24 @@ >; }; + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 + >; + }; + pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 @@ -675,6 +928,17 @@ >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -782,6 +1046,7 @@ lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; + primary; status = "okay"; display-timings { @@ -799,6 +1064,33 @@ }; }; }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + status = "okay"; }; &pwm3 { @@ -808,14 +1100,30 @@ status = "okay"; }; -&pcie { +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; status = "okay"; }; -&spdif { +&ssi2 { + assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>; + fsl,mode = "i2s-master"; + status = "okay"; +}; + +&uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; + pinctrl-0 = <&pinctrl_uart3_1>; + pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */ + <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */ + fsl,uart-has-rtscts; status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ }; &uart4 { @@ -836,6 +1144,14 @@ status = "okay"; }; +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qdl-sabresd-btwifi.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6qdl-sabresd-btwifi.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6qdl-sabresd-btwifi.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qdl-sabresd-btwifi.dtsi 2024-06-19 12:33:57.928186205 +0200 @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * NOTE: This DTS file is wrote for plugging in Murata 1MW M.2 + * into SD2 slot by using Murata uSD-to-M.2 Adapter. + * + * By default, OOB IRQ is enabled with below HW rework. + * HW rework: + * Install R209,R210,R211,R212,R213,R214,R215 on SDB board. + */ + +/ { + leds { + compatible = "gpio-leds"; + status = "disabled"; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + }; +}; + +&ecspi1 { + status = "disabled"; +}; + +&iomuxc { + imx6qdl-sabresd-murata-v2 { + pinctrl_btreg: btreggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + /* add MUXing entry for SD2 4-bit interface and configure control pins */ + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x13069 /* WL_REG_ON */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0b001 /* WL_HOST_WAKE */ + >; + }; + }; +}; + +&pinctrl_gpio_leds { + fsl,pins = < + >; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_1 + &pinctrl_btreg>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc1_pwrseq>; + pm-ignore-notify; + cap-power-off-card; + /delete-property/ enable-sdio-wakeup; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qdl-sabresd.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6qdl-sabresd.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6qdl-sabresd.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qdl-sabresd.dtsi 2024-06-19 12:33:57.928186205 +0200 @@ -8,11 +8,31 @@ #include / { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + chosen { stdout-path = &uart1; }; - memory@10000000 { + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio2 24 1>; + uok_input = <&gpio1 27 1>; + chg_input = <&gpio3 23 1>; + flt_input = <&gpio5 2 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,usb_valid; + status = "okay"; + }; + + memory: memory@10000000 { device_type = "memory"; reg = <0x10000000 0x40000000>; }; @@ -66,6 +86,22 @@ enable-active-high; }; + reg_hdmi: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi-5v-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + hdmi-5v-supply = <&swbst_reg>; + }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio6 14 0>; + enable-active-high; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -117,6 +153,64 @@ mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; }; + sound-hdmi { + compatible = "fsl,imx6qdl-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "okay"; + }; + backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; @@ -132,19 +226,31 @@ led-red { gpios = <&gpio1 2 0>; - default-state = "on"; + linux,default-trigger = "max8903-charger-charging"; + retain-state-suspended; + default-state = "off"; }; }; - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; }; }; @@ -156,7 +262,9 @@ }; &ipu1_csi0_mux_from_parallel_sensor { +#if 0 remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; +#endif }; &ipu1_csi0 { @@ -167,6 +275,11 @@ &mipi_csi { status = "okay"; + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; +#if 0 port@0 { reg = <0>; @@ -176,6 +289,17 @@ data-lanes = <1 2>; }; }; +#endif +}; + +&mipi_dsi { + dev_id = <0>; + disp_id = <1>; + lcd_panel = "TRULY-WVGA"; + disp-power-on-supply = <®_mipi_dsi_pwr_on>; + reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + reset-delay-us = <50>; + status = "okay"; }; &audmux { @@ -187,8 +311,20 @@ &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds1"; + status = "okay"; }; &ecspi1 { @@ -227,17 +363,40 @@ }; }; -&hdmi { +&gpc { + fsl,ldo-bypass = <1>; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x294>; + fsl,phy_reg_cksymtx = <0x800d>; +/* HDMI-supply = <®_hdmi>; */ status = "okay"; }; &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; status = "okay"; codec: wm8962@1a { @@ -273,6 +432,7 @@ vddio-supply = <®_sensors>; }; +#if 0 ov5642: camera@3c { compatible = "ovti,ov5642"; pinctrl-names = "default"; @@ -297,12 +457,32 @@ }; }; }; +#endif + ov564x: ov564x@3c { + compatible = "ovti,ov564x"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_2>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3, on rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */ + rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; status = "okay"; touchscreen@4 { @@ -315,6 +495,15 @@ wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; }; + max11801@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <26 2>; + work-mode = <1>;/*DCM mode*/ + }; + +#if 0 ov5640: camera@3c { compatible = "ovti,ov5640"; pinctrl-names = "default"; @@ -337,6 +526,22 @@ }; }; }; +#endif + + ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */ + compatible = "ovti,ov564x_mipi"; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v rev C board is VGEN3 rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */ + rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */ + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + }; pmic: pfuze100@8 { compatible = "fsl,pfuze100"; @@ -438,12 +643,20 @@ }; }; }; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; status = "okay"; egalax_ts@4 { @@ -468,6 +681,7 @@ light-sensor@44 { compatible = "isil,isl29023"; reg = <0x44>; + rext = <499>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3_isl29023_int>; interrupt-parent = <&gpio3>; @@ -492,6 +706,11 @@ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 >; }; @@ -534,6 +753,12 @@ >; }; + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + pinctrl_gpio_keys: gpio_keysgrp { fsl,pins = < MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 @@ -544,7 +769,14 @@ pinctrl_hdmi_cec: hdmicecgrp { fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_hdmi_hdcp: hdmihdcpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 >; }; @@ -562,6 +794,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1_gpio_grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b8b0 + >; + }; + pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp { fsl,pins = < MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1 @@ -575,6 +814,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2_gpio_grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b8b0 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 + >; + }; + pinctrl_i2c2_egalax_int: i2c2egalaxintgrp { fsl,pins = < MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 @@ -588,6 +834,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3_gpio_grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b8b0 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + >; + }; + pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp { fsl,pins = < MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 @@ -600,6 +853,59 @@ >; }; + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 + >; + }; + pinctrl_ipu1_csi0: ipu1csi0grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 @@ -661,6 +967,24 @@ >; }; + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 @@ -731,16 +1055,45 @@ &ldb { status = "okay"; - lvds-channel@1 { + lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; - port@4 { - reg = <4>; + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; }; }; }; @@ -751,7 +1104,6 @@ pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie>; - status = "okay"; }; &pwm1 { @@ -785,11 +1137,14 @@ status = "okay"; }; -&snvs_pwrkey { - status = "okay"; -}; - &ssi2 { + assigned-clocks = <&clks IMX6QDL_CLK_PLL4>, + <&clks IMX6QDL_PLL4_BYPASS>, + <&clks IMX6QDL_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_PLL4>, + <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <737280000>, <0>, <0>; status = "okay"; }; @@ -836,6 +1191,7 @@ bus-width = <8>; non-removable; no-1-8-v; + auto-cmd23-broken; status = "okay"; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6q.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6q.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q.dtsi 2024-06-19 12:33:57.920186067 +0200 @@ -43,9 +43,13 @@ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; + <&clks IMX6QDL_CLK_PLL1_SYS>, + <&clks IMX6QDL_CLK_PLL1>, + <&clks IMX6QDL_PLL1_BYPASS>, + <&clks IMX6QDL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; @@ -159,16 +163,47 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + soc: soc { - ocram: sram@900000 { + busfreq: busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, + <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc"; + interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + fsl,max_ddr_freq = <528000000>; + }; + + ocram: sram@905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x40000>; - ranges = <0 0x00900000 0x40000>; + reg = <0x905000 0x3B000>; + ranges = <0 0x905000 0x3B000>; #address-cells = <1>; #size-cells = <1>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; + ocram_optee: sram@938000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x938000 0x8000>; + overw_reg = <&ocram 0x905000 0x33000>; + }; + aips1: bus@2000000 { /* AIPS1 */ spba-bus@2000000 { ecspi5: spi@2018000 { @@ -187,6 +222,18 @@ }; }; + bus@2100000 { /* AIPS2 */ + mipi_dsi: mipi@21e0000 { + compatible = "fsl,imx6q-mipi-dsi"; + reg = <0x21e0000 0x4000>; + interrupts = <0 102 0x4>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; + }; + }; + sata: sata@2200000 { compatible = "fsl,imx6q-ahci"; reg = <0x02200000 0x4000>; @@ -207,6 +254,30 @@ clock-names = "bus", "core"; power-domains = <&pd_pu>; #cooling-cells = <2>; + status = "disabled"; + }; + + gpu: gpu@00130000 { + compatible = "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x02204000 0x4000>, <0x10000000 0x0>, + <0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "iobase_vg", "phys_baseaddr", + "contiguous_mem"; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d", "irq_vg"; + clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>; + clock-names = "gpu2d_axi_clk", "openvg_axi_clk", + "gpu3d_axi_clk", "gpu2d_clk", + "gpu3d_clk", "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>, <&src 3>; + reset-names = "gpu3d", "gpu2d", "gpuvg"; + power-domains = <&pd_pu>; }; ipu2: ipu@2800000 { @@ -218,9 +289,17 @@ <0 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI0>, - <&clks IMX6QDL_CLK_IPU2_DI1>; - clock-names = "bus", "di0", "di1"; + <&clks IMX6QDL_CLK_IPU2_DI1>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, + <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; resets = <&src 4>; + bypass_reset = <0>; ipu2_csi0: port@0 { reg = <0>; @@ -439,13 +518,19 @@ }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; + clock-names = "ldb_di0", "ldb_di1", + "di0_sel", "di1_sel", + "di2_sel", "di3_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel"; lvds-channel@0 { port@2 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qp.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6qp.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6qp.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qp.dtsi 2024-06-19 12:33:57.932186273 +0200 @@ -5,6 +5,15 @@ #include "imx6q.dtsi" / { + aliases { + pre0 = &pre1; + pre1 = &pre2; + pre2 = &pre3; + pre3 = &pre4; + prg0 = &prg1; + prg1 = &prg2; + }; + soc { ocram2: sram@940000 { compatible = "mmio-sram"; @@ -26,57 +35,63 @@ bus@2100000 { pre1: pre@21c8000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021c8000 0x1000>; interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE0>; clock-names = "axi"; - fsl,iram = <&ocram2>; + ocram = <&ocram2>; + status = "disabled"; }; pre2: pre@21c9000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021c9000 0x1000>; interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE1>; clock-names = "axi"; - fsl,iram = <&ocram2>; + ocram = <&ocram2>; + status = "disabled"; }; pre3: pre@21ca000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021ca000 0x1000>; interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE2>; clock-names = "axi"; - fsl,iram = <&ocram3>; + ocram = <&ocram3>; + status = "disabled"; }; pre4: pre@21cb000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021cb000 0x1000>; interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE3>; clock-names = "axi"; - fsl,iram = <&ocram3>; + ocram = <&ocram3>; + status = "disabled"; }; prg1: prg@21cc000 { - compatible = "fsl,imx6qp-prg"; + compatible = "fsl,imx6q-prg"; reg = <0x021cc000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRG0_APB>, <&clks IMX6QDL_CLK_PRG0_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre1>, <&pre2>, <&pre3>; + clock-names = "apb", "axi"; + gpr = <&gpr>; + status = "disabled"; }; prg2: prg@21cd000 { - compatible = "fsl,imx6qp-prg"; + compatible = "fsl,imx6q-prg"; reg = <0x021cd000 0x1000>; clocks = <&clks IMX6QDL_CLK_PRG1_APB>, <&clks IMX6QDL_CLK_PRG1_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre4>, <&pre2>, <&pre3>; + clock-names = "apb", "axi"; + gpr = <&gpr>; + status = "disabled"; }; }; }; @@ -93,22 +108,34 @@ &ipu1 { compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + clocks = <&clks IMX6QDL_CLK_IPU1>, + <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG0_APB>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", "prg"; fsl,prg = <&prg1>; }; &ipu2 { compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + clocks = <&clks IMX6QDL_CLK_IPU2>, + <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG1_APB>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", "prg"; fsl,prg = <&prg2>; }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; + compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb"; }; &mmdc0 { @@ -118,3 +145,7 @@ &pcie { compatible = "fsl,imx6qp-pcie"; }; + +&pcie_ep { + compatible = "fsl,imx6qp-pcie-ep"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qp-sabreauto.dts linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabreauto.dts --- linux-6.1.55/arch/arm/boot/dts/imx6qp-sabreauto.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabreauto.dts 2024-06-19 12:33:57.932186273 +0200 @@ -12,6 +12,62 @@ compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; }; +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; + +&mxcfb1 { + prefetch; + status = "okay"; +}; + +&mxcfb2 { + prefetch; + status = "okay"; +}; + +&mxcfb3 { + prefetch; + status = "okay"; +}; + +&mxcfb4 { + prefetch; + status = "okay"; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + &i2c2 { max7322: gpio@68 { compatible = "maxim,max7322"; @@ -21,31 +77,6 @@ }; }; -&iomuxc { - imx6qdl-sabreauto { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - }; -}; - &pcie { reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; status = "okay"; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qp-sabreauto-ecspi.dts linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabreauto-ecspi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6qp-sabreauto-ecspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabreauto-ecspi.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + + +#include "imx6qp-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qp-sabreauto-flexcan1.dts linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabreauto-flexcan1.dts --- linux-6.1.55/arch/arm/boot/dts/imx6qp-sabreauto-flexcan1.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabreauto-flexcan1.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabreauto.dts" + +&can1{ + status = "okay"; +}; + +&fec { + /* pin conflict with flexcan1 */ + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qp-sabreauto-gpmi-weim.dts linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabreauto-gpmi-weim.dts --- linux-6.1.55/arch/arm/boot/dts/imx6qp-sabreauto-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabreauto-gpmi-weim.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +#include "imx6qp-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + compatible = "fsl,imx6qp-gpmi-nand"; + fsl,use-minimum-ecc; + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qp-sabresd-btwifi.dts linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabresd-btwifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6qp-sabresd-btwifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabresd-btwifi.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabresd.dts" +#include "imx6qdl-sabresd-btwifi.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qp-sabresd.dts linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabresd.dts --- linux-6.1.55/arch/arm/boot/dts/imx6qp-sabresd.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabresd.dts 2024-06-19 12:33:57.932186273 +0200 @@ -54,6 +54,16 @@ regulator-always-on; }; +&ov564x { + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DOVDD-supply = <&sw4_reg>; /* 1.8v */ +}; + +&ov564x_mipi { + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DOVDD-supply = <&sw4_reg>; /* 1.8v */ +}; + &pcie { status = "okay"; }; @@ -61,3 +71,59 @@ &sata { status = "okay"; }; + +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; + +&mxcfb1 { + prefetch; + status = "okay"; +}; + +&mxcfb2 { + prefetch; + status = "okay"; +}; + +&mxcfb3 { + prefetch; + status = "okay"; +}; + +&mxcfb4 { + prefetch; + status = "okay"; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qp-sabresd-hdcp.dts linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabresd-hdcp.dts --- linux-6.1.55/arch/arm/boot/dts/imx6qp-sabresd-hdcp.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabresd-hdcp.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,43 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6qp-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&battery { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qp-sabresd-ldo.dts linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabresd-ldo.dts --- linux-6.1.55/arch/arm/boot/dts/imx6qp-sabresd-ldo.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabresd-ldo.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabresd.dts" + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6qp-sabresd-pcie-ep.dts linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabresd-pcie-ep.dts --- linux-6.1.55/arch/arm/boot/dts/imx6qp-sabresd-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6qp-sabresd-pcie-ep.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6qp-sabresd.dts" + +&pcie{ + status = "disabled"; +}; + +&pcie_ep{ + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto.dts 2024-06-19 12:33:57.920186067 +0200 @@ -13,6 +13,31 @@ compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; }; +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + &sata { status = "okay"; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + +#include "imx6q-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto-enetirq.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto-enetirq.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto-enetirq.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto-enetirq.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2019 NXP + +#include "imx6q-sabreauto.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; +}; + +&mlb { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabreauto.dts" + +&can1{ + status = "okay"; +}; + +&fec { + /* pin conflict with flexcan1 */ + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + + +#include "imx6q-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + fsl,use-minimum-ecc; + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto-pcie.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto-pcie.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabreauto-pcie.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabreauto-pcie.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6q-sabreauto.dts" + +&pcie { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-btwifi.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-btwifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-btwifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-btwifi.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd.dts" +#include "imx6qdl-sabresd-btwifi.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd.dts 2024-06-19 12:33:57.920186067 +0200 @@ -13,6 +13,38 @@ compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; }; +&battery { + offset-charger = <1900>; + offset-discharger = <1694>; + offset-usb-charger = <1685>; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + &sata { status = "okay"; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. +// Copyright 2019 NXP + +#include "imx6q-sabresd.dts" + +&fec { + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>; + interrupts-extended = <&gpio1 6 0x4>, <&gpc 0 119 0x4>; + fsl,err006687-workaround-present; +}; + +&i2c3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,44 @@ +/* + * Copyright 2012-2014 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6q-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&battery { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-ldo.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-ldo.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-ldo.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-ldo.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-pcie.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-pcie.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-pcie.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-pcie.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6q-sabresd.dts" + +&pcie { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-pcie-ep.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-pcie-ep.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-pcie-ep.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6q-sabresd.dts" + +&pcie{ + status = "disabled"; +}; + +&pcie_ep{ + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-uart.dts linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-uart.dts --- linux-6.1.55/arch/arm/boot/dts/imx6q-sabresd-uart.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6q-sabresd-uart.dts 2024-06-19 12:33:57.920186067 +0200 @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd.dts" + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_1>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ +}; + +&ecspi1 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sl.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6sl.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6sl.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sl.dtsi 2024-06-19 12:33:57.932186273 +0200 @@ -67,11 +67,17 @@ <396000 1175000>; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; - clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, - <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, - <&clks IMX6SL_CLK_PLL1_SYS>; + clocks = <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_STEP>, + <&clks IMX6SL_CLK_PLL1_SW>, + <&clks IMX6SL_CLK_PLL1_SYS>, + <&clks IMX6SL_CLK_PLL1>, + <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", + "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; @@ -112,15 +118,54 @@ interrupt-parent = <&gpc>; ranges; - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - ranges = <0 0x00900000 0x20000>; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>, + <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>, + <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>, + <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>, + <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM_PODF>, + <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>, + <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>, + <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>, + <&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", + "ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src", + "pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@900000 { + compatible = "fsl,lpm-sram"; + reg = <0x900000 0x4000>; + ranges = <0 0x900000 0x4000>; #address-cells = <1>; #size-cells = <1>; clocks = <&clks IMX6SL_CLK_OCRAM>; }; + ocrams_ddr: sram@904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x904000 0x1000>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + + ocram: sram@905000 { + compatible = "mmio-sram"; + reg = <0x905000 0x1B000>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + + ocram_optee: sram@918000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x918000 0x8000>; + overw_reg = <&ocram 0x905000 0x13000>; + }; + intc: interrupt-controller@a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -588,6 +633,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_pu: regulator-vddpu { @@ -604,6 +650,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_soc: regulator-vddsoc { @@ -621,6 +668,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; tempmon: tempmon { @@ -741,8 +789,14 @@ }; csi: csi@20e4000 { - reg = <0x020e4000 0x4000>; + compatible = "fsl,imx6sl-csi"; + reg = <0x20e4000 0x4000>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; }; spdc: spdc@20e8000 { @@ -763,13 +817,20 @@ }; pxp: pxp@20f0000 { - reg = <0x020f0000 0x4000>; + compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; + reg = <0x20f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; epdc: epdc@20f4000 { - reg = <0x020f4000 0x4000>; + compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc"; + reg = <0x20f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; }; lcdif: lcdif@20f8000 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sl-evk-btwifi.dts linux-imx-phytec/arch/arm/boot/dts/imx6sl-evk-btwifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sl-evk-btwifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sl-evk-btwifi.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* NOTE: This DTS file is written for plugging in Murata Wi-Fi/BT EVK into SD1 + * slot using Murata i.MX InterConnect Ver 1.0 Adapter AND wiring in control + * signals with SD Card Extender on SD3 slot. + * Bluetooth UART connect via SD1 EMMC/MMC Plus pinout. + * WL_REG_ON/BT_REG_ON/WL_HOST_WAKE are connected from SD Card Extender on SD3 + * slot. + */ +#include "imx6sl-evk.dts" + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 16 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + imx6sl-evk-murata-v1_sdext { + /* Only MUX SD1_DAT0..3 lines so UART4 can be MUXed on higher data lines. */ + pinctrl_btreg: btreggrp { + fsl,pins = < + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x13069 /* BT_REG_ON */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x13069 /* WL_HOST_WAKE */ + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x13069 /* WL_REG_ON */ + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + >; + }; + }; +}; +/* Murata: declare UART4 interface for Bluetooth. */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_1 + &pinctrl_btreg>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart4dte_1>; */ +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc1_pwrseq>; + pm-ignore-notify; + cap-power-off-card; + /delete-property/ enable-sdio-wakeup; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + bus-width = <1>; + no-1-8-v; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sl-evk-csi.dts linux-imx-phytec/arch/arm/boot/dts/imx6sl-evk-csi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sl-evk-csi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sl-evk-csi.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +// +//Copyright (C) 2013 Freescale Semiconductor, Inc. + +#include "imx6sl-evk.dts" + +&csi { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&epdc { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sl-evk.dts linux-imx-phytec/arch/arm/boot/dts/imx6sl-evk.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sl-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sl-evk.dts 2024-06-19 12:33:57.932186273 +0200 @@ -12,6 +12,19 @@ model = "Freescale i.MX6 SoloLite EVK Board"; compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio4 13 1>; + uok_input = <&gpio4 13 1>; + chg_input = <&gpio4 15 1>; + flt_input = <&gpio4 14 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,adc_disable; + status = "okay"; + }; + chosen { stdout-path = &uart1; }; @@ -21,6 +34,19 @@ reg = <0x80000000 0x40000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + backlight_display: backlight_display { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; @@ -40,6 +66,11 @@ }; }; + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; @@ -97,7 +128,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hp>; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + audio-cpu = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -131,6 +162,14 @@ status = "okay"; }; +&csi { + port { + csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + &ecspi1 { cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -146,6 +185,15 @@ }; }; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + &fec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec>; @@ -154,6 +202,10 @@ status = "okay"; }; +&gpc { + fsl,ldo-bypass = <1>; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -260,6 +312,89 @@ }; }; }; + + elan@10 { + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio2>; + interrupts = <10 2>; + gpio_elan_cs = <&gpio2 9 0>; + gpio_elan_rst = <&gpio4 4 0>; + gpio_intr = <&gpio2 10 0>; + status = "okay"; + }; + + ma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; + }; &i2c2 { @@ -283,6 +418,34 @@ }; }; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_0>; + clocks = <&clks IMX6SL_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 25 1>; + rst-gpios = <&gpio1 26 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi_ep>; + }; + }; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -298,6 +461,12 @@ MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x17000 + MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000 + MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0 + MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 >; }; @@ -319,6 +488,39 @@ >; }; + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x80000000 + MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x80000000 + MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x80000000 + MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x80000000 + MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x80000000 + MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x80000000 + MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x80000000 + MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x80000000 + MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x80000000 + MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x80000000 + MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000 + MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000 + MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000 + MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000 + MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000 + MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000 + MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000 + MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x80000000 + MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x80000000 + MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x80000000 + MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000 + MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x80000000 + MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x80000000 + MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000 + MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x80000000 + MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000 + MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000 + MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000 + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 @@ -367,6 +569,13 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1 + MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_kpp: kppgrp { fsl,pins = < MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 @@ -436,6 +645,24 @@ >; }; + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x1b0b1 + MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4dte_1: uart4dtegrp-1 { + fsl,pins = < + MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x1b0b1 + MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x1b0b1 + >; + }; + pinctrl_usbotg1: usbotg1grp { fsl,pins = < MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 @@ -552,9 +779,34 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 >; }; + + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0 + MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0 + MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0 + MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0 + MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0 + MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0 + MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0 + MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0 + MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0 + MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0 + MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0 + MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0 + MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0 + MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0 + MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; }; }; +&pxp { + status = "okay"; +}; + &kpp { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_kpp>; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sl-evk-ldo.dts linux-imx-phytec/arch/arm/boot/dts/imx6sl-evk-ldo.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sl-evk-ldo.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sl-evk-ldo.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sl-evk.dts" + +&gpc { + /* use ldo-enable, u-boot will check it and configure */ + fsl,ldo-bypass = <0>; +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_pu { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sl-evk-uart.dts linux-imx-phytec/arch/arm/boot/dts/imx6sl-evk-uart.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sl-evk-uart.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sl-evk-uart.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sl-evk.dts" + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_1>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart4dte_1>; */ +}; + +&usdhc1 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sll.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6sll.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6sll.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sll.dtsi 2024-06-19 12:33:57.932186273 +0200 @@ -65,13 +65,18 @@ <198000 1175000>; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; + fsl,low-power-run; clocks = <&clks IMX6SLL_CLK_ARM>, <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_PLL1_SW>, - <&clks IMX6SLL_CLK_PLL1_SYS>; + <&clks IMX6SLL_CLK_PLL1_SYS>, + <&clks IMX6SLL_CLK_PLL1>, + <&clks IMX6SLL_PLL1_BYPASS>, + <&clks IMX6SLL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", + "pll1_bypass_src"; nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; }; @@ -112,14 +117,50 @@ interrupt-parent = <&gpc>; ranges; - ocram: sram@900000 { + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>, + <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>, + <&clks IMX6SLL_CLK_PLL3_USB_OTG>, <&clks IMX6SLL_CLK_PERIPH>, + <&clks IMX6SLL_CLK_PERIPH_PRE>, <&clks IMX6SLL_CLK_PERIPH_CLK2>, + <&clks IMX6SLL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SLL_CLK_OSC>, + <&clks IMX6SLL_CLK_AHB>, <&clks IMX6SLL_CLK_AXI_PODF>, + <&clks IMX6SLL_CLK_PERIPH2>, <&clks IMX6SLL_CLK_PERIPH2_PRE>, + <&clks IMX6SLL_CLK_PERIPH2_CLK2>, <&clks IMX6SLL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_MMDC_P0_FAST>, <&clks IMX6SLL_PLL1_BYPASS_SRC>, + <&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>, + <&clks IMX6SLL_CLK_PLL1>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@900000 { + compatible = "fsl,lpm-sram"; + reg = <0x900000 0x4000>; + }; + + ocrams_ddr: sram@904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x904000 0x1000>; + }; + + ocram: sram@905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - ranges = <0 0x00900000 0x20000>; + reg = <0x905000 0x1B000>; + ranges = <0 0x905000 0x1B000>; #address-cells = <1>; #size-cells = <1>; }; + ocram_optee: sram@918000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x918000 0x8000>; + overw_reg = <&ocram 0x905000 0x13000>; + }; + intc: interrupt-controller@a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -178,7 +219,7 @@ }; ecspi1: spi@2008000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + compatible ="fsl,imx6ul-ecspi"; reg = <0x02008000 0x4000>; interrupts = ; dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; @@ -190,7 +231,7 @@ }; ecspi2: spi@200c000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx6ul-ecspi"; reg = <0x0200c000 0x4000>; interrupts = ; dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; @@ -202,7 +243,7 @@ }; ecspi3: spi@2010000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx6ul-ecspi"; reg = <0x02010000 0x4000>; interrupts = ; dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; @@ -214,7 +255,7 @@ }; ecspi4: spi@2014000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx6ul-ecspi"; reg = <0x02014000 0x4000>; interrupts = ; dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; @@ -601,6 +642,7 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; }; iomuxc: pinctrl@20e0000 { @@ -626,7 +668,7 @@ }; sdma: dma-controller@20ec000 { - compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma"; + compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_IPG>, @@ -638,12 +680,25 @@ }; pxp: pxp@20f0000 { - compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp"; + compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma"; reg = <0x20f0000 0x4000>; interrupts = , ; - clocks = <&clks IMX6SLL_CLK_PXP>; - clock-names = "axi"; + clocks = <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_PXP>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + epdc: epdc@20f4000 { + compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc"; + reg = <0x20f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_EPDC_AXI>, + <&clks IMX6SLL_CLK_EPDC_PIX>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "epdc_axi", "epdc_pix", "epdc_ahb"; + status = "disabled"; }; lcdif: lcd-controller@20f8000 { @@ -712,7 +767,7 @@ }; usdhc1: mmc@2190000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02190000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC1>, @@ -726,7 +781,7 @@ }; usdhc2: mmc@2194000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02194000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC2>, @@ -740,7 +795,7 @@ }; usdhc3: mmc@2198000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02198000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC3>, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sll-evk-btwifi.dts linux-imx-phytec/arch/arm/boot/dts/imx6sll-evk-btwifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sll-evk-btwifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sll-evk-btwifi.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sll-evk.dts" + +/ { + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + }; +}; + +&epdc { + status = "disabled"; +}; + +&iomuxc { + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130b9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + + MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x17059 /* WL_REG_ON */ + >; + }; +}; + +&lcdif { + status = "disabled"; +}; + +®_sd3_vmmc { + regulator-always-on; +}; + +&uart5 { + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc1_pwrseq>; + /delete-property/ cd-gpios; + /delete-property/ vmmc-supply; + /delete-property/ enable-sdio-wakeup; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sll-evk.dts linux-imx-phytec/arch/arm/boot/dts/imx6sll-evk.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sll-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sll-evk.dts 2024-06-19 12:33:57.932186273 +0200 @@ -24,6 +24,19 @@ reg = <0x80000000 0x80000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + backlight_display: backlight-display { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; @@ -32,6 +45,19 @@ status = "okay"; }; + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio4 13 1>; + uok_input = <&gpio4 13 1>; + chg_input = <&gpio4 15 1>; + flt_input = <&gpio4 14 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,adc_disable; + status = "okay"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -44,6 +70,11 @@ }; }; + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + reg_usb_otg1_vbus: regulator-otg1-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -106,9 +137,18 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; + reg_sd2_vmmc: regulator-sd2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC-VCCQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + reg_sd3_vmmc: regulator-sd3-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -117,22 +157,10 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - sound { compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; pinctrl-names = "default"; @@ -164,6 +192,19 @@ soc-supply = <&sw1c_reg>; }; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -270,6 +311,76 @@ }; }; }; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "okay"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; }; &i2c3 { @@ -298,9 +409,30 @@ pinctrl-0 = <&pinctrl_lcd>; status = "okay"; - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; }; }; }; @@ -312,6 +444,10 @@ status = "okay"; }; +&pxp { + status = "okay"; +}; + &snvs_poweroff { status = "okay"; }; @@ -330,6 +466,16 @@ status = "okay"; }; +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -343,6 +489,17 @@ status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + vqmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; pinctrl-names = "default"; @@ -380,6 +537,18 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */ + MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 + >; + }; + pinctrl_audmux3: audmux3grp { fsl,pins = < MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 @@ -390,6 +559,46 @@ >; }; + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1 + MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1 + MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1 + MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1 + MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1 + MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1 + MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1 + MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1 + MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1 + MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1 + MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1 + MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1 + MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1 + MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1 + MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1 + MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1 + MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1 + MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1 + MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1 + MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1 + MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1 + MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1 + MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1 + MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1 + MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */ + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */ + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */ + MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */ + MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */ + >; + }; + pinctrl_hp: hpgrp { fsl,pins = < MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ @@ -433,6 +642,24 @@ >; }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1 + MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1 + MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 @@ -466,6 +693,54 @@ >; }; + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9 + >; + }; + pinctrl_usbotg1: usbotg1grp { fsl,pins = < MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sll-evk-reva.dts linux-imx-phytec/arch/arm/boot/dts/imx6sll-evk-reva.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sll-evk-reva.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sll-evk-reva.dts 2024-06-19 12:33:57.932186273 +0200 @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP. + * + */ + +/dts-v1/; + +#include "imx6sll-evk.dts" + +&usdhc2 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6sx.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6sx.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx.dtsi 2024-06-19 12:33:57.936186342 +0200 @@ -85,9 +85,13 @@ <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_PLL1_SW>, - <&clks IMX6SX_CLK_PLL1_SYS>; + <&clks IMX6SX_CLK_PLL1_SYS>, + <&clks IMX6SX_CLK_PLL1>, + <&clks IMX6SX_PLL1_BYPASS>, + <&clks IMX6SX_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; soc-supply = <®_soc>; nvmem-cells = <&cpu_speed_grade>; @@ -95,6 +99,20 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + ckil: clock-ckil { compatible = "fixed-clock"; #clock-cells = <0>; @@ -161,24 +179,67 @@ interrupt-parent = <&gpc>; ranges; - ocram_s: sram@8f8000 { - compatible = "mmio-sram"; - reg = <0x008f8000 0x4000>; - ranges = <0 0x008f8000 0x4000>; + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>, + <&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>, + <&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>, + <&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>, + <&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>, + <&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>, + <&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM_PODF>, + <&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>, + <&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>, + <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_PODF>, + <&clks IMX6SX_CLK_M4>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", + "pll3_usb_otg", "periph", "periph_pre", "periph_clk2", + "periph_clk2_sel", "osc", "pll1_sys", "periph2", + "ahb", "ocram", "pll1_sw", "periph2_pre", + "periph2_clk2_sel", "periph2_clk2", "step", "mmdc", + "m4"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@8f8000 { + compatible = "fsl,lpm-sram"; + reg = <0x8f8000 0x4000>; + ranges = <0 0x8f8000 0x4000>; #address-cells = <1>; #size-cells = <1>; clocks = <&clks IMX6SX_CLK_OCRAM_S>; }; - ocram: sram@900000 { + ocrams_ddr: sram@900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x900000 0x1000>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + ocram: sram@901000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - ranges = <0 0x00900000 0x20000>; + reg = <0x901000 0x1F000>; + ranges = <0 0x901000 0x1F000>; #address-cells = <1>; #size-cells = <1>; clocks = <&clks IMX6SX_CLK_OCRAM>; }; + ocram_mf: sram-mf@900000 { + compatible = "fsl,mega-fast-sram"; + reg = <0x900000 0x20000>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + ocram_optee { + compatible = "fsl,optee-lpm-sram"; + reg = <0x8f8000 0x4000>; + overw_reg = <&ocrams_ddr 0x904000 0x1000>, + <&ocram 0x905000 0x1b000>, + <&ocrams 0x900000 0x4000>; + overw_clock = <&ocrams &clks IMX6SX_CLK_OCRAM>; + }; + intc: interrupt-controller@a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -207,6 +268,23 @@ <&clks IMX6SX_CLK_GPU>; clock-names = "bus", "core", "shader"; power-domains = <&pd_pu>; + status = "disabled"; + }; + + gpu3d: gpu3d@1800000 { + compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu"; + reg = <0x1800000 0x4000>, <0x80000000 0x0>, + <0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = ; + interrupt-names = "irq_3d"; + clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>, + <&clks 0>; + clock-names = "gpu3d_axi_clk", "gpu3d_clk", + "gpu3d_shader_clk"; + resets = <&src 0>; + reset-names = "gpu3d"; + power-domains = <&pd_pu>; }; dma_apbh: dma-apbh@1804000 { @@ -222,6 +300,11 @@ clocks = <&clks IMX6SX_CLK_APBH_DMA>; }; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + gpmi: nand-controller@1806000{ compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; @@ -743,6 +826,20 @@ fsl,anatop = <&anatop>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@20cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x20cc000 0x4000>; + }; + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -798,6 +895,7 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>; clocks = <&clks IMX6SX_CLK_IPG>; clock-names = "ipg"; @@ -848,6 +946,30 @@ reg = <0x020e4000 0x4000>; }; + ldb: ldb@20e0014 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb"; + gpr = <&gpr>; + status = "disabled"; + clocks = <&clks IMX6SX_CLK_LDB_DI0>, + <&clks IMX6SX_CLK_LCDIF1_SEL>, + <&clks IMX6SX_CLK_LCDIF2_SEL>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_7>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>; + clock-names = "ldb_di0", + "di0_sel", + "di1_sel", + "ldb_di0_div_3_5", + "ldb_di0_div_7", + "ldb_di0_div_sel"; + lvds-channel@0 { + reg = <0>; + status = "disabled"; + }; + }; + sdma: dma-controller@20ec000 { compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; @@ -870,6 +992,7 @@ crypto: crypto@2100000 { compatible = "fsl,sec-v4.0"; + entropy-delay = <12000>; #address-cells = <1>; #size-cells = <1>; reg = <0x2100000 0x10000>; @@ -960,6 +1083,7 @@ fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; fsl,stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <0>; status = "disabled"; }; @@ -1023,6 +1147,8 @@ <&clks IMX6SX_CLK_USDHC4>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; @@ -1076,6 +1202,9 @@ clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,stop-mode = <&gpr 0x10 4>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <0>; status = "disabled"; }; @@ -1168,6 +1297,12 @@ status = "disabled"; }; + qspi_m4: qspi-m4 { + compatible = "fsl,imx6sx-qspi-m4-restore"; + reg = <0x021e4000 0x4000>; + status = "disabled"; + }; + uart2: serial@21e8000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; @@ -1246,21 +1381,46 @@ ranges; csi1: csi@2214000 { + compatible = "fsl,imx6s-csi"; reg = <0x02214000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, <&clks IMX6SX_CLK_CSI>, <&clks IMX6SX_CLK_DCIC1>; - clock-names = "disp-axi", "csi_mclk", "dcic"; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + power-domains = <&pd_disp>; + status = "disabled"; + }; + + dcic1: dcic@220c000 { + compatible = "fsl,imx6sx-dcic"; + reg = <0x220c000 0x4000>; + interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_DCIC1>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; + }; + + dcic2: dcic@2210000 { + compatible = "fsl,imx6sx-dcic"; + reg = <0x2210000 0x4000>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_DCIC2>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; status = "disabled"; }; pxp: pxp@2218000 { - compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; + compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; reg = <0x02218000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_PXP_AXI>; - clock-names = "axi"; + clocks = <&clks IMX6SX_CLK_PXP_AXI>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pxp-axi", "disp-axi"; power-domains = <&pd_disp>; status = "disabled"; }; @@ -1316,6 +1476,7 @@ interrupts = ; clocks = <&clks IMX6SX_CLK_IPG>; clock-names = "adc"; + num-channels = <4>; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; @@ -1327,6 +1488,7 @@ interrupts = ; clocks = <&clks IMX6SX_CLK_IPG>; clock-names = "adc"; + num-channels = <4>; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; @@ -1352,6 +1514,27 @@ status = "disabled"; }; + sema4: sema4@02290000 { /* sema4 */ + compatible = "fsl,imx6sx-sema4"; + reg = <0x02290000 0x4000>; + interrupts = <0 116 0x04>; + status = "okay"; + }; + + mu: mu@02294000 { /* mu */ + compatible = "fsl,imx6sx-mu"; + reg = <0x02294000 0x4000>; + interrupts = <0 90 0x04>; + #mbox-cells = <2>; + }; + + mu_lp: mu_lp@02294000 { /* mu */ + compatible = "fsl,imx6sx-mu-lp"; + reg = <0x02294000 0x4000>; + interrupts = <0 90 0x04>; + status = "okay"; + }; + uart6: serial@22a0000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; @@ -1434,5 +1617,36 @@ power-domain-names = "pcie", "pcie_phy"; status = "disabled"; }; + + pcie_ep: pcie_ep@8ffc000 { + compatible = "fsl,imx6sx-pcie-ep"; + reg = <0x08ffc000 0x04000>, <0x08000000 0xf00000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + clocks = <&clks IMX6SX_CLK_PCIE_AXI>, + <&clks IMX6SX_CLK_LVDS1_OUT>, + <&clks IMX6SX_CLK_PCIE_REF_125M>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + power-domains = <&pd_disp>, <&pd_pci>; + power-domain-names = "pcie", "pcie_phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx6sx-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx-pinfunc.h linux-imx-phytec/arch/arm/boot/dts/imx6sx-pinfunc.h --- linux-6.1.55/arch/arm/boot/dts/imx6sx-pinfunc.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx-pinfunc.h 2024-06-19 12:33:57.936186342 +0200 @@ -67,6 +67,7 @@ #define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS 0x002C 0x0374 0x082C 0x4 0x0 #define MX6SX_PAD_GPIO1_IO06__UART1_DTE_CTS 0x002C 0x0374 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART1_CTS_B 0x002C 0x0374 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 @@ -77,6 +78,7 @@ #define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS 0x0030 0x0378 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO07__UART1_DTE_RTS 0x0030 0x0378 0x082C 0x4 0x1 +#define MX6SX_PAD_GPIO1_IO07__UART1_RTS_B 0x0030 0x0378 0x082C 0x4 0x1 #define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 @@ -87,6 +89,7 @@ #define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 #define MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS 0x0034 0x037C 0x0834 0x4 0x0 #define MX6SX_PAD_GPIO1_IO08__UART2_DTE_CTS 0x0034 0x037C 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO08__UART2_CTS_B 0x0034 0x037C 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 @@ -97,6 +100,7 @@ #define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS 0x0038 0x0380 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO09__UART2_DTE_RTS 0x0038 0x0380 0x0834 0x4 0x1 +#define MX6SX_PAD_GPIO1_IO09__UART2_RTS_B 0x0038 0x0380 0x0834 0x4 0x1 #define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 @@ -205,6 +209,7 @@ #define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 #define MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x0064 0x03AC 0x0854 0x4 0x0 #define MX6SX_PAD_CSI_DATA06__UART6_DTE_CTS 0x0064 0x03AC 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA06__UART6_CTS_B 0x0064 0x03AC 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 @@ -216,6 +221,7 @@ #define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 #define MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x0068 0x03B0 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_DATA07__UART6_DTE_RTS 0x0068 0x03B0 0x0854 0x4 0x1 +#define MX6SX_PAD_CSI_DATA07__UART6_RTS_B 0x0068 0x03B0 0x0854 0x4 0x1 #define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 @@ -226,6 +232,7 @@ #define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 #define MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS 0x006C 0x03B4 0x0844 0x3 0x2 #define MX6SX_PAD_CSI_HSYNC__UART4_DTE_CTS 0x006C 0x03B4 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_HSYNC__UART4_CTS_B 0x006C 0x03B4 0x0000 0x3 0x0 #define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 @@ -259,6 +266,7 @@ #define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 #define MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS 0x0078 0x03C0 0x0000 0x3 0x0 #define MX6SX_PAD_CSI_VSYNC__UART4_DTE_RTS 0x0078 0x03C0 0x0844 0x3 0x3 +#define MX6SX_PAD_CSI_VSYNC__UART4_RTS_B 0x0078 0x03C0 0x0844 0x3 0x3 #define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 @@ -362,6 +370,7 @@ #define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 #define MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS 0x009C 0x03E4 0x082C 0x3 0x2 #define MX6SX_PAD_ENET2_RX_CLK__UART1_DTE_CTS 0x009C 0x03E4 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_RX_CLK__UART1_CTS_B 0x009C 0x03E4 0x0000 0x3 0x0 #define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 #define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 @@ -373,6 +382,7 @@ #define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 #define MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS 0x00A0 0x03E8 0x0000 0x3 0x0 #define MX6SX_PAD_ENET2_TX_CLK__UART1_DTE_RTS 0x00A0 0x03E8 0x082C 0x3 0x3 +#define MX6SX_PAD_ENET2_TX_CLK__UART1_RTS_B 0x00A0 0x03E8 0x082C 0x3 0x3 #define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 #define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 @@ -383,6 +393,7 @@ #define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 #define MX6SX_PAD_KEY_COL0__UART6_DCE_RTS 0x00A4 0x03EC 0x0854 0x2 0x2 #define MX6SX_PAD_KEY_COL0__UART6_DTE_CTS 0x00A4 0x03EC 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL0__UART6_CTS_B 0x00A4 0x03EC 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 #define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 #define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 @@ -402,6 +413,7 @@ #define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 #define MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x00AC 0x03F4 0x084C 0x2 0x2 #define MX6SX_PAD_KEY_COL2__UART5_DTE_CTS 0x00AC 0x03F4 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x00AC 0x03F4 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 #define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 #define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 @@ -428,6 +440,7 @@ #define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 #define MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS 0x00B8 0x0400 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_ROW0__UART6_DTE_RTS 0x00B8 0x0400 0x0854 0x2 0x3 +#define MX6SX_PAD_KEY_ROW0__UART6_RTS_B 0x00B8 0x0400 0x0854 0x2 0x3 #define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 #define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 #define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 @@ -448,6 +461,7 @@ #define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 #define MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x00C0 0x0408 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_ROW2__UART5_DTE_RTS 0x00C0 0x0408 0x084C 0x2 0x3 +#define MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x00C0 0x0408 0x084C 0x2 0x3 #define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 #define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 #define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 @@ -831,6 +845,7 @@ #define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 #define MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS 0x0160 0x04A8 0x083C 0x3 0x0 #define MX6SX_PAD_NAND_DATA04__UART3_DTE_CTS 0x0160 0x04A8 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA04__UART3_CTS_B 0x0160 0x04A8 0x0000 0x3 0x0 #define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 #define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 @@ -842,6 +857,7 @@ #define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 #define MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS 0x0164 0x04AC 0x0000 0x3 0x0 #define MX6SX_PAD_NAND_DATA05__UART3_DTE_RTS 0x0164 0x04AC 0x083C 0x3 0x1 +#define MX6SX_PAD_NAND_DATA05__UART3_RTS_B 0x0164 0x04AC 0x083C 0x3 0x1 #define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 #define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 @@ -985,6 +1001,7 @@ #define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS 0x01A0 0x04E8 0x0000 0x1 0x0 #define MX6SX_PAD_QSPI1B_DATA0__UART3_DTE_RTS 0x01A0 0x04E8 0x083C 0x1 0x4 +#define MX6SX_PAD_QSPI1B_DATA0__UART3_RTS_B 0x01A0 0x04E8 0x083C 0x1 0x4 #define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 @@ -994,6 +1011,7 @@ #define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS 0x01A4 0x04EC 0x083C 0x1 0x5 #define MX6SX_PAD_QSPI1B_DATA1__UART3_DTE_CTS 0x01A4 0x04EC 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_DATA1__UART3_CTS_B 0x01A4 0x04EC 0x0000 0x1 0x0 #define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 @@ -1266,6 +1284,7 @@ #define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 #define MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS 0x0230 0x0578 0x0000 0x4 0x0 #define MX6SX_PAD_SD1_DATA2__UART2_DTE_RTS 0x0230 0x0578 0x0834 0x4 0x2 +#define MX6SX_PAD_SD1_DATA2__UART2_RTS_B 0x0230 0x0578 0x0834 0x4 0x2 #define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 @@ -1276,6 +1295,7 @@ #define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 #define MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS 0x0234 0x057C 0x0834 0x4 0x3 #define MX6SX_PAD_SD1_DATA3__UART2_DTE_CTS 0x0234 0x057C 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA3__UART2_CTS_B 0x0234 0x057C 0x0000 0x4 0x0 #define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 @@ -1347,6 +1367,7 @@ #define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_CLK__UART4_DCE_CTS 0x0250 0x0598 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_CLK__UART4_DTE_RTS 0x0250 0x0598 0x0844 0x1 0x0 +#define MX6SX_PAD_SD3_CLK__UART4_RTS_B 0x0250 0x0598 0x0844 0x1 0x0 #define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 #define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 #define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 @@ -1387,6 +1408,7 @@ #define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS 0x0260 0x05A8 0x0844 0x1 0x1 #define MX6SX_PAD_SD3_DATA2__UART4_DTE_CTS 0x0260 0x05A8 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_DATA2__UART4_CTS_B 0x0260 0x05A8 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 #define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 #define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 @@ -1433,6 +1455,7 @@ #define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 #define MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x0270 0x05B8 0x083C 0x3 0x2 #define MX6SX_PAD_SD3_DATA6__UART3_DTE_CTS 0x0270 0x05B8 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA6__UART3_CTS_B 0x0270 0x05B8 0x0000 0x3 0x0 #define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 @@ -1444,6 +1467,7 @@ #define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 #define MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x0274 0x05BC 0x0000 0x3 0x0 #define MX6SX_PAD_SD3_DATA7__UART3_DTE_RTS 0x0274 0x05BC 0x083C 0x3 0x3 +#define MX6SX_PAD_SD3_DATA7__UART3_RTS_B 0x0274 0x05BC 0x083C 0x3 0x3 #define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 @@ -1536,6 +1560,7 @@ #define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 #define MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS 0x0298 0x05E0 0x084C 0x2 0x0 #define MX6SX_PAD_SD4_DATA6__UART5_DTE_CTS 0x0298 0x05E0 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA6__UART5_CTS_B 0x0298 0x05E0 0x0000 0x2 0x0 #define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 #define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 @@ -1547,6 +1572,7 @@ #define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 #define MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS 0x029C 0x05E4 0x0000 0x2 0x0 #define MX6SX_PAD_SD4_DATA7__UART5_DTE_RTS 0x029C 0x05E4 0x084C 0x2 0x1 +#define MX6SX_PAD_SD4_DATA7__UART5_RTS_B 0x029C 0x05E4 0x084C 0x2 0x1 #define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 #define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx-sabreauto.dts linux-imx-phytec/arch/arm/boot/dts/imx6sx-sabreauto.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sx-sabreauto.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx-sabreauto.dts 2024-06-19 12:33:57.936186342 +0200 @@ -75,6 +75,45 @@ regulator-always-on; }; + reg_vref_3v3: regulator-adc-verf { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + si4763_vio1: vio1_tnr { + compatible = "regulator-fixed"; + regulator-name = "vio1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vio2: vio2_tnr { + compatible = "regulator-fixed"; + regulator-name = "vio2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vd: f3v3_tnr { + compatible = "regulator-fixed"; + regulator-name = "vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_va: f5v_tnr { + compatible = "regulator-fixed"; + regulator-name = "va"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + sound-cs42888 { compatible = "fsl,imx6-sabreauto-cs42888", "fsl,imx-audio-cs42888"; @@ -97,6 +136,17 @@ "AIN2R", "Line In Jack"; }; + sound-fm { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si4763"; + + ssi-controller = <&ssi2>; + fm-controller = <&si476x_codec>; + mux-int-port = <2>; + mux-ext-port = <5>; + }; + sound-spdif { compatible = "fsl,imx-audio-spdif"; model = "imx-spdif"; @@ -105,10 +155,26 @@ }; }; +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + &anaclk2 { clock-frequency = <24576000>; }; +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_3>; + status = "okay"; +}; + &clks { assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, <&clks IMX6SX_PLL4_BYPASS>, @@ -118,6 +184,32 @@ assigned-clock-rates = <0>, <0>, <24576000>; }; +&ssi2 { + fsl,mode = "i2s-master"; + status = "okay"; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; +}; + &esai { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esai>; @@ -125,7 +217,6 @@ <&clks IMX6SX_CLK_ESAI_EXTAL>; assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <0>, <24576000>; - status = "okay"; }; &fec1 { @@ -143,11 +234,13 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + qca,disable-smarteee; }; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + qca,disable-smarteee; }; }; }; @@ -175,12 +268,62 @@ status = "okay"; }; +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + nand-on-flash-bbt; + status = "okay"; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + }; + + flash1: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <2>; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -207,6 +350,14 @@ }; &iomuxc { + pinctrl_audmux_3: audmux-3 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0 + MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0 + >; + }; + pinctrl_egalax_int: egalax-intgrp { fsl,pins = < MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0 @@ -278,6 +429,27 @@ >; }; + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 @@ -304,6 +476,23 @@ >; }; + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 @@ -311,6 +500,31 @@ >; }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 @@ -401,6 +615,20 @@ VLC-supply = <®_cs42888>; }; + si4763: si4763@63 { + compatible = "si4761"; + reg = <0x63>; + va-supply = <&si4763_va>; + vd-supply = <&si4763_vd>; + vio1-supply = <&si4763_vio1>; + vio2-supply = <&si4763_vio2>; + revision-a10; /* set to default A10 compatible command set */ + + si476x_codec: si476x-codec { + compatible = "si476x-codec"; + }; + }; + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; @@ -540,6 +768,31 @@ gpio-controller; #gpio-cells = <2>; }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <7>; + interrupt-parent = <&gpio3>; + interrupts = <24 8>; + interrupt-route = <1>; + }; + + mag3110@e { + compatible = "fsl,mag3110"; + reg = <0xe>; + position = <2>; + interrupt-parent = <&gpio6>; + interrupts = <6 1>; + }; + + isl29023@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio3>; + interrupts = <23 2>; + }; }; &spdif { @@ -550,6 +803,17 @@ status = "okay"; }; +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-btwifi.dts linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-btwifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-btwifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-btwifi.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * NOTE: This DTS file is wrote for plugging in Murata 1MW M.2 + * into SD2 slot by using Murata uSD-to-M.2 Adapter. + * + * By default, OOB IRQ is not enabled since i.MX6SX SDB board needs to rework. + * How to enable OOB IRQ ? + * HW rework: + * Install R328 on i.MX6SX SDB board. + * SW change: + * pinctrl_wifi: wifigrp { + * fsl,pins = < + * MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x0b001 + * >; + * }; + * brcmf: bcrmf@1 { + * reg = <1>; + * compatible = "brcm,bcm4329-fmac"; + * interrupt-parent = <&gpio2>; + * interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + * interrupt-names = "host-wake"; + * }; + */ + +#include "imx6sx-sdb.dts" + +/ { + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + }; +}; + +&iomuxc { + imx6sx-sdb-murata-wifibt { + pinctrl_bt: btgrp { + fsl,pins = < + MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x13069 /* BT_REG_ON */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + >; + }; + }; +}; + +&uart5 { /* for bluetooth */ + pinctrl-0 = <&pinctrl_uart5 &pinctrl_bt>; + resets = <&modem_reset>; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi>; + bus-width = <4>; + no-1-8-v; /* force 3.3V VIO */ + non-removable; + mmc-pwrseq = <&usdhc2_pwrseq>; + pm-ignore-notify; + cap-power-off-card; + /delete-property/ wakeup-source; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb.dts linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb.dts 2024-06-19 12:33:57.936186342 +0200 @@ -103,6 +103,23 @@ }; }; +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + + fsl,arm-soc-shared = <1>; +}; + &qspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi2>; @@ -131,10 +148,12 @@ ®_arm { vin-supply = <&sw1a_reg>; + regulator-allow-bypass; }; ®_soc { vin-supply = <&sw1a_reg>; + regulator-allow-bypass; }; ®_vdd1p1 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb.dtsi 2024-06-19 12:33:57.936186342 +0200 @@ -28,6 +28,14 @@ default-brightness-level = <6>; }; + backlight2 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif1"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -56,6 +64,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -93,6 +102,7 @@ regulator-name = "lcd-3v3"; gpio = <&gpio3 27 0>; enable-active-high; + status = "disabled"; }; reg_peri_3v3: regulator-peri-3v3 { @@ -151,12 +161,24 @@ regulator-max-microvolt = <3300000>; }; + reg_vref_3v3: regulator-adc-verf { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + sound { compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hp>; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + audio-cpu = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -170,19 +192,6 @@ hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; }; - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - sound-spdif { compatible = "fsl,imx-audio-spdif", "fsl,imx6sx-sdb-spdif"; @@ -191,6 +200,23 @@ spdif-out; }; + sii902x_reset: sii902x-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 27 1>; + reset-delay-us = <100000>; + #reset-cells = <0>; + status = "disabled"; + }; +}; + +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; }; &audmux { @@ -199,6 +225,41 @@ status = "okay"; }; +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -215,10 +276,12 @@ ethphy1: ethernet-phy@1 { reg = <1>; + qca,disable-smarteee; }; ethphy2: ethernet-phy@2 { reg = <2>; + qca,disable-smarteee; }; }; }; @@ -246,11 +309,99 @@ status = "okay"; }; +&gpc { + fsl,ldo-bypass = <1>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_0>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio3 28 1>; + rst-gpios = <&gpio3 27 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; + + sii902x@39 { + compatible = "SiI,sii902x"; + interrupt-parent = <&gpio4>; + interrupts = <21 2>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + resets = <&sii902x_reset>; + reg = <0x39>; + status = "disabled"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + egalax_ts@4 { + compatible = "eeti,egalax_ts"; + reg = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio4>; + interrupts = <19 2>; + wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + }; +}; + + &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + isl29023@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio6>; + interrupts = <5 1>; + shared-interrupt; + }; + + mag3110@e { + compatible = "fsl,mag3110"; + reg = <0xe>; + position = <2>; + interrupt-parent = <&gpio6>; + interrupts = <5 1>; + shared-interrupt; + }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <1>; + interrupt-parent = <&gpio6>; + interrupts = <2 8>; + interrupt-route = <2>; + }; }; &i2c4 { @@ -285,11 +436,65 @@ &lcdif1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + status = "disabled"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; status = "okay"; + display1: display@1 { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; +&ldb { + status = "okay"; + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "lcdif2"; + status = "okay"; + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; }; }; }; @@ -301,6 +506,17 @@ status = "okay"; }; +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + &snvs_poweroff { status = "okay"; }; @@ -320,6 +536,13 @@ }; &ssi2 { + assigned-clocks = <&clks IMX6SX_CLK_PLL4>, + <&clks IMX6SX_PLL4_BYPASS>, + <&clks IMX6SX_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6SX_CLK_OSC>, + <&clks IMX6SX_CLK_PLL4>, + <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <737280000>, <0>, <0>; status = "okay"; }; @@ -334,6 +557,9 @@ pinctrl-0 = <&pinctrl_uart5>; uart-has-rtscts; status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ }; &usbotg1 { @@ -397,6 +623,24 @@ &iomuxc { imx6x-sdb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059 + MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000 + MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 + >; + }; + + pinctrl_can_gpios: can-gpios { + fsl,pins = < + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + >; + }; + pinctrl_audmux: audmuxgrp { fsl,pins = < MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 @@ -407,11 +651,38 @@ >; }; + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 @@ -486,6 +757,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 @@ -565,6 +843,12 @@ >; }; + pinctrl_pwm4: pwm4grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + pinctrl_qspi2: qspi2grp { fsl,pins = < MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 @@ -620,6 +904,15 @@ >; }; + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usb_otg1: usbotg1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 @@ -709,6 +1002,51 @@ >; }; + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 @@ -716,3 +1054,14 @@ }; }; }; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-emmc.dts linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-emmc.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-emmc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-emmc.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,33 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include "imx6sx-sdb.dts" + +/* + * The eMMC chip on imx6sx sdb board is DNP by default. + * Need do hw rework to burn the eMMC4.5 chip on the eMMC socket on uSDHC4 + * and connect eMMC signals as well as disconnect BOOT SD CARD slot signals + */ +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + pinctrl-1 = <&pinctrl_usdhc4_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_1_200mhz>; + bus-width = <8>; + auto-cmd23-broken; + /* + * overwrite cd-gpios and wp-gpios since they are reused as eMMC DATA + * signals after rework + */ + cd-gpios = <>; + wp-gpios = <>; + non-removable; + status = "okay"; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ + +#include "imx6sx-sdb.dts" + +/ { + sii902x_reset: sii902x-reset { + status = "okay"; + }; +}; + +&csi1 { + status = "disabled"; +}; + +&lcdif1 { + status = "okay"; +}; + +&i2c1 { + sii902x@39 { + status = "okay"; + }; +}; + +&ov5640 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-ldo.dts linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-ldo.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-ldo.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-ldo.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb.dts" + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <0>; +}; + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-m4.dts linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-m4.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-m4.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-m4.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb.dts" + +/{ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + m4_reserved: m4@9ff00000 { + no-map; + reg = <0x9ff00000 0x100000>; + }; + + rpmsg_reserved: rpmsg@bff00000 { + no-map; + reg = <0xbff00000 0x100000>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; +}; + +/* + * The flollowing modules are conflicting with M4, disable them when m4 + * is running. + */ +&adc1 { + status = "disabled"; +}; + +&adc2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +&qspi2 { + status = "disabled"; +}; + +&qspi_m4 { + status = "okay"; +}; + +&rpmsg{ + vdev-nums = <1>; + reg = <0xbfff0000 0x10000>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&clks { + fsl,shared-clks-number = <0x23>; + fsl,shared-clks-index = ; + fsl,shared-mem-addr = <0x91F000>; + fsl,shared-mem-size = <0x1000>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-pcie-ep.dts linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-pcie-ep.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-pcie-ep.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx6sx-sdb.dts" + +&pcie{ + status = "disabled"; +}; + +&pcie_ep{ + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts --- linux-6.1.55/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb-reva.dts" + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi.dts linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-btwifi.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-csi.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +#include "imx6ul-14x14-evk.dts" + + +&csi { + status = "okay"; +}; + +&ov5640 { + status = "okay"; +}; + +&sim2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi 2024-06-19 12:33:57.936186342 +0200 @@ -12,7 +12,20 @@ reg = <0x80000000 0x20000000>; }; - backlight_display: backlight-display { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0xa000000>; + linux,cma-default; + }; + }; + + backlight-display { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -20,6 +33,10 @@ status = "okay"; }; + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; @@ -27,6 +44,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -100,21 +118,11 @@ #gpio-cells = <2>; reg = <0>; registers-number = <1>; + registers-default = /bits/ 8 <0x57>; spi-max-frequency = <100000>; enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; }; }; - - panel { - compatible = "innolux,at043tn24"; - backlight = <&backlight_display>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; }; &clks { @@ -122,6 +130,16 @@ assigned-clock-rates = <786432000>; }; +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -139,40 +157,26 @@ clock-names = "mclk"; }; - camera@3c { + ov5640: ov5640@3c { compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_camera_clock>; + pinctrl-0 = <&pinctrl_csi1 &pinctrl_camera_clock>; clocks = <&clks IMX6UL_CLK_CSI>; - clock-names = "xclk"; - powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; - + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; port { - ov5640_to_parallel: endpoint { - remote-endpoint = <¶llel_from_ov5640>; - bus-width = <8>; - data-shift = <2>; /* lines 9:2 are used */ - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; }; }; }; -}; -&csi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi1>; - status = "okay"; - - port { - parallel_from_ov5640: endpoint { - remote-endpoint = <&ov5640_to_parallel>; - bus-type = <5>; /* Parallel bus */ - }; - }; }; &fec1 { @@ -256,6 +260,15 @@ reg = <0x0e>; vdd-supply = <®_peri_3v3>; vddio-supply = <®_peri_3v3>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; }; }; @@ -265,11 +278,31 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + display = <&display0>; status = "okay"; - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; }; }; }; @@ -281,6 +314,10 @@ status = "okay"; }; +&pxp { + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; @@ -316,6 +353,22 @@ status = "okay"; }; +&sim2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim2>; + assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; + assigned-clock-rates = <240000000>; + /* GPIO_ACTIVE_HIGH/LOW:sim card voltage control + * NCN8025:Vcc = ACTIVE_HIGH?5V:3V + * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V + */ + pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + port = <1>; + sven_low_active; + status = "okay"; +}; + &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; @@ -335,7 +388,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; }; &usbotg1 { @@ -374,8 +434,7 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - broken-cd; + non-removable; keep-power-in-suspend; wakeup-source; status = "okay"; @@ -587,6 +646,15 @@ >; }; + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + pinctrl_usb_otg1: usbotg1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 @@ -596,7 +664,7 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 @@ -641,6 +709,51 @@ >; }; + pinctrl_usdhc2_8bit: usdhc2grp_8bit { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi.dts linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2018 NXP + +/* + * DTS file for ECSPI Certification at i.mx6ul 14x14 evk board. + * NOTE: Because Ethernet2 use the same pins with ecspi4, so disable + * fec1/fec2 for ECSPI4 test. + */ + +#include "imx6ul-14x14-evk.dts" + +&iomuxc { + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x70a1 + MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x70a1 + MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x70a1 + MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x70a1 + >; + }; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <20000000>; + }; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi-slave.dts linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi-slave.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-ecspi-slave.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2018 NXP + +/* + * DTS file for ECSPI Slave Certification at i.mx6ul 14x14 evk board. + * NOTE: Because Ethernet2 use the same pins with ecspi4, so disable + * fec1/fec2 for ECSPI4 test. + */ + +#include "imx6ul-14x14-evk-ecspi.dts" + +/delete-node/&spidev0; + +&ecspi4 { + #address-cells = <0>; + spi-slave; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-emmc.dts linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-emmc.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-emmc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-emmc.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,21 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include "imx6ul-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-gpmi-weim.dts linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-gpmi-weim.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-gpmi-weim.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +#include "imx6ul-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; + fsl,use-minimum-ecc; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-reve.dts linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-reve.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ul-14x14-evk-reve.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-14x14-evk-reve.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include + +/dts-v1/; +/plugin/; + +&{/} { + sound-wm8960 { + status = "disabled"; + }; + + reg_audio: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai2>; + audio-codec = <&wm8962>; + audio-asrc = <&asrc>; + hp-det-gpio = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "IN1L", "Mic Jack", + "IN3L", "Mic Jack", + "Mic Jack", "MICBIAS", + "AMIC", "MICBIAS", + "IN1R", "AMIC", + "IN2R", "AMIC"; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + fxls8974@18 { + compatible = "nxp,fxls8974cf"; + reg = <0x18>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&codec { + status = "disabled"; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi.dts linux-imx-phytec/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-9x9-evk-btwifi.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-9x9-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-9x9-evk.dts linux-imx-phytec/arch/arm/boot/dts/imx6ul-9x9-evk.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ul-9x9-evk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-9x9-evk.dts 2024-06-19 12:33:57.940186410 +0200 @@ -0,0 +1,806 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 9x9 EVK Board"; + compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0xa000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai2>; + audio-codec = <&codec>; + audio-asrc = <&asrc>; + hp-det-gpio = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "AMIC", + "RINPUT2", "AMIC", + "Mic Jack", "MICB", + "AMIC", "MICB"; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0xf>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + mag3110@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <3 2 3>; + wlf,gpio-cfg = <1 3>; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* used for lcd reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + + pinctrl_sim2_1: sim2grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sim2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim2_1>; + assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; + assigned-clock-rates = <240000000>; + pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + port = <1>; + sven_low_active; + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure_delay_time = <0xffff>; + pre_charge_time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts linux-imx-phytec/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-9x9-evk-ldo.dts 2024-06-19 12:33:57.936186342 +0200 @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-9x9-evk.dts" + +&cpu0 { + operating-points = < + /* kHz uV */ + 696000 1275000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 696000 1275000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <0>; +}; + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6ul.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6ul.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul.dtsi 2024-06-19 12:33:57.944186478 +0200 @@ -82,10 +82,15 @@ <&clks IMX6UL_CA7_SECONDARY_SEL>, <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_PLL1_SW>, - <&clks IMX6UL_CLK_PLL1_SYS>; + <&clks IMX6UL_CLK_PLL1_SYS>, + <&clks IMX6UL_PLL1_BYPASS>, + <&clks IMX6UL_CLK_PLL1>, + <&clks IMX6UL_PLL1_BYPASS_SRC>, + <&clks IMX6UL_CLK_OSC>; clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step", "pll1_sw", - "pll1_sys"; + "pll1_sys", "pll1_bypass", "pll1", + "pll1_bypass_src", "osc"; arm-supply = <®_arm>; soc-supply = <®_soc>; nvmem-cells = <&cpu_speed_grade>; @@ -144,14 +149,48 @@ interrupt-parent = <&gpc>; ranges; - ocram: sram@900000 { + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>, + <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>, + <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>, + <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>, + <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>, + <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@900000 { + compatible = "fsl,lpm-sram"; + reg = <0x900000 0x4000>; + }; + + ocrams_ddr: sram@904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x904000 0x1000>; + }; + + ocram: sram@905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x00905000 0x1B000>; ranges = <0 0x00900000 0x20000>; #address-cells = <1>; #size-cells = <1>; }; + ocram_optee: sram@918000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x918000 0x8000>; + overw_reg = <&ocram 0x905000 0x13000>; + }; + intc: interrupt-controller@a01000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupts = ; @@ -177,6 +216,11 @@ clocks = <&clks IMX6UL_CLK_APBHDMA>; }; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + gpmi: nand-controller@1806000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; @@ -275,6 +319,8 @@ clocks = <&clks IMX6UL_CLK_UART7_IPG>, <&clks IMX6UL_CLK_UART7_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 43 4 0>, <&sdma 44 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -297,6 +343,8 @@ clocks = <&clks IMX6UL_CLK_UART8_IPG>, <&clks IMX6UL_CLK_UART8_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 45 4 0>, <&sdma 46 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -540,6 +588,7 @@ fsl,num-rx-queues = <1>; fsl,stop-mode = <&gpr 0x10 4>; fsl,magic-packet; + fsl,wakeup_irq = <0>; status = "disabled"; }; @@ -661,6 +710,20 @@ fsl,anatop = <&anatop>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@20cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x20cc000 0x4000>; + }; + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -721,6 +784,7 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; }; iomuxc: pinctrl@20e0000 { @@ -888,6 +952,14 @@ fsl,num-rx-queues = <1>; fsl,stop-mode = <&gpr 0x10 3>; fsl,magic-packet; + fsl,wakeup_irq = <0>; + status = "disabled"; + }; + + sim1: sim@0218c000 { + compatible = "fsl,imx6ul-sim"; + reg = <0x0218c000 0x4000>; + interrupts = ; status = "disabled"; }; @@ -966,6 +1038,15 @@ clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; }; + sim2: sim@021b4000 { + compatible = "fsl,imx6ul-sim"; + reg = <0x021b4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SIM2>; + clock-names = "sim"; + status = "disabled"; + }; + weim: weim@21b8000 { #address-cells = <2>; #size-cells = <1>; @@ -998,16 +1079,18 @@ }; csi: csi@21c4000 { - compatible = "fsl,imx6ul-csi"; + compatible = "fsl,imx6ul-csi", "fsl,imx7-csi", "fsl,imx6s-csi"; reg = <0x021c4000 0x4000>; interrupts = ; - clocks = <&clks IMX6UL_CLK_CSI>; - clock-names = "mclk"; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_CSI>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; status = "disabled"; }; lcdif: lcdif@21c8000 { - compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif"; + compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; reg = <0x021c8000 0x4000>; interrupts = ; clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, @@ -1018,11 +1101,13 @@ }; pxp: pxp@21cc000 { - compatible = "fsl,imx6ul-pxp"; - reg = <0x021cc000 0x4000>; + compatible = "fsl,imx6ul-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; + reg = <0x21cc000 0x4000>; interrupts = ; - clocks = <&clks IMX6UL_CLK_PXP>; - clock-names = "axi"; + clocks = <&clks IMX6UL_CLK_PXP>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; qspi: spi@21e0000 { @@ -1054,6 +1139,8 @@ clocks = <&clks IMX6UL_CLK_UART2_IPG>, <&clks IMX6UL_CLK_UART2_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1065,6 +1152,8 @@ clocks = <&clks IMX6UL_CLK_UART3_IPG>, <&clks IMX6UL_CLK_UART3_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1076,6 +1165,8 @@ clocks = <&clks IMX6UL_CLK_UART4_IPG>, <&clks IMX6UL_CLK_UART4_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1087,6 +1178,8 @@ clocks = <&clks IMX6UL_CLK_UART5_IPG>, <&clks IMX6UL_CLK_UART5_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1108,6 +1201,8 @@ clocks = <&clks IMX6UL_CLK_UART6_IPG>, <&clks IMX6UL_CLK_UART6_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi 2024-06-19 12:33:57.940186410 +0200 @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021-2023 NXP + */ + +/* + * NOTE: This DTS file is written for the wifi chips that supporting 1.8V + * SDIO3.0, and also 3.3V SDIO2.0 + */ + + +/ { + usdhc1_pwrseq: usdhc1_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + }; + + + reg_nvcc_sd_sel: regulator-nvcc-sd-vsel { + compatible = "regulator-gpio"; + regulator-name = "NVCC SD VSEL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 0>, <1800000 1>; + }; +}; + +&iomuxc { + pinctrl_wifi: wifigrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x03029 + >; + }; +}; + +&pinctrl_usdhc1 { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; +}; + +&pinctrl_usdhc1_100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x170b9 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x170b9 /* SD1 RESET */ + >; +}; + +&pinctrl_usdhc1_200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x170f9 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x170f9 /* SD1 RESET */ + >; +}; + +®_sd1_vmmc { + regulator-always-on; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + fsl,sdio-async-interrupt-enabled; + non-removable; + mmc-pwrseq = <&usdhc1_pwrseq>; + + /* Here config the vsel pad as an normal gpio, and use + * the vqmmc(gpio-regulator) method to do the IO voltage switch. + * set gpio to low level select 3.3v, and high level select 1.8v + * If not, when config this pin as vsel specific function, + * though work normal when sdio boot up and in SDIO 3.0 mode, + * but will meet issue after system resume back from mem + * mode, because after system suspend in mem mode, usdhc + * will lost power, so when resume back, all register + * return to default state, need driver to re-config. + * But for sdio wifi device, we config this device with + * flag keep-power-in-suspend, so sdio wifi do nothing + * during system PM, only mark re-tuning flag. When + * system resume back, the original vsel bit lost, which + * means the IO voltage change to 3.3v, but sdio wifi still + * in SDIO3.0 mode, expect the IO voltage in 1.8v, IO + * voltage mismatch happened, data transfer in this time + * will meet CRC/Timeout issue. + */ + vqmmc-supply = <®_nvcc_sd_sel>; + /delete-property/ enable-sdio-wakeup; + /delete-property/ cd-gpios; +}; + +&gpio_spi { + /* Murata: modify default setting so that BT_nPWD/BT_REG_ON + * is low (0V) during kernel boot. + */ + registers-default = /bits/ 8 <0x47>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi.dts linux-imx-phytec/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ull-14x14-evk-btwifi.dts 2024-06-19 12:33:57.944186478 +0200 @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ull-14x14-evk.dts linux-imx-phytec/arch/arm/boot/dts/imx6ull-14x14-evk.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ull-14x14-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ull-14x14-evk.dts 2024-06-19 12:33:57.944186478 +0200 @@ -8,11 +8,22 @@ #include "imx6ul-14x14-evk.dtsi" / { - model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board"; + model = "Freescale i.MX6 ULL 14x14 EVK Board"; compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; }; &clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; - assigned-clock-rates = <320000000>; + assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>, + <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <320000000>, <786432000>; }; + +&csi { + status = "okay"; +}; + +&ov5640 { + status = "okay"; +}; + +/delete-node/ &sim2; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts linux-imx-phytec/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts 2024-06-19 12:33:57.944186478 +0200 @@ -0,0 +1,21 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include "imx6ull-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ull-14x14-evk-gpmi-weim.dts linux-imx-phytec/arch/arm/boot/dts/imx6ull-14x14-evk-gpmi-weim.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ull-14x14-evk-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ull-14x14-evk-gpmi-weim.dts 2024-06-19 12:33:57.944186478 +0200 @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2016 Freescale Semiconductor, Inc. + +#include "imx6ull-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; + fsl,use-minimum-ecc; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi.dts linux-imx-phytec/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ull-9x9-evk-btwifi.dts 2024-06-19 12:33:57.944186478 +0200 @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-9x9-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ull-9x9-evk.dts linux-imx-phytec/arch/arm/boot/dts/imx6ull-9x9-evk.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ull-9x9-evk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ull-9x9-evk.dts 2024-06-19 12:33:57.944186478 +0200 @@ -0,0 +1,802 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ull.dtsi" + +/ { + model = "Freescale i.MX6 ULL 9x9 EVK Board"; + compatible = "fsl,imx6ull-9x9-evk", "fsl,imx6ull"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0xa000000>; + linux,cma-default; + }; + }; + + pxp_v4l2 { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + }; + + sound { + compatible = "fsl,imx6ul-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai2>; + audio-codec = <&codec>; + audio-asrc = <&asrc>; + hp-det-gpio = <&gpio5 4 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "AMIC", + "RINPUT2", "AMIC", + "Mic Jack", "MICB", + "AMIC", "MICB"; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&csi { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0xf>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + mag3110@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <3 2 3>; + wlf,gpio-cfg = <1 3>; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6UL_CLK_CSI>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio_spi 6 1>; + rst-gpios = <&gpio_spi 5 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default_snvs"; + pinctrl-0 = <&pinctrl_hog_2>; + imx6ull-evk { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_lcdif_reset: lcdifresetgrp { + fsl,pins = < + /* used for lcd reset */ + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_sai2_hp_det_b: sai2_hp_det_grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl + &pinctrl_lcdif_reset>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2 + &pinctrl_sai2_hp_det_b>; + + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure_delay_time = <0xffff>; + pre_charge_time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ull-9x9-evk-ldo.dts linux-imx-phytec/arch/arm/boot/dts/imx6ull-9x9-evk-ldo.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ull-9x9-evk-ldo.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ull-9x9-evk-ldo.dts 2024-06-19 12:33:57.944186478 +0200 @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-9x9-evk.dts" +&cpu0 { + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <0>; +}; + +&gpc { + fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */ +}; + +®_arm { + /delete-property/ vin-supply; +}; + +®_soc { + /delete-property/ vin-supply; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ull.dtsi linux-imx-phytec/arch/arm/boot/dts/imx6ull.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx6ull.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ull.dtsi 2024-06-19 12:33:57.944186478 +0200 @@ -13,6 +13,7 @@ &cpu0 { clock-frequency = <900000000>; + fsl,low-power-run; operating-points = < /* kHz uV */ 900000 1275000 @@ -35,22 +36,55 @@ compatible = "fsl,imx6ull-ocotp", "syscon"; }; +&gpc { + fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>; +}; + &pxp { - compatible = "fsl,imx6ull-pxp"; + compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma"; interrupts = , - ; + ; + clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; }; &usdhc1 { compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; }; &usdhc2 { compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; }; / { soc: soc { + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>, + <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>, + <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>, + <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>, + <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>, + <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>, + <&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>, + <&clks IMX6UL_CLK_PLL1>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1"; + fsl,max_ddr_freq = <400000000>; + }; + aips3: bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -88,6 +122,21 @@ clocks = <&clks IMX6UL_CLK_UART8_IPG>, <&clks IMX6UL_CLK_UART8_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 45 4 0>, <&sdma 46 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + epdc: epdc@228c000 { + compatible = "fsl,imx7d-epdc"; + interrupts = ; + reg = <0x228c000 0x4000>; + clocks = <&clks IMX6ULL_CLK_EPDC_ACLK>, + <&clks IMX6ULL_CLK_EPDC_PIX>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "epdc_axi", "epdc_pix", "epdc_ahb"; + /* Need to fix epdc-ram */ + /* epdc-ram = <&gpr 0x4 30>; */ status = "disabled"; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ulz-14x14-evk-btwifi.dts linux-imx-phytec/arch/arm/boot/dts/imx6ulz-14x14-evk-btwifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ulz-14x14-evk-btwifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ulz-14x14-evk-btwifi.dts 2024-06-19 12:33:57.944186478 +0200 @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx6ulz-14x14-evk.dts" +#include "imx6ul-evk-btwifi.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ulz-14x14-evk.dts linux-imx-phytec/arch/arm/boot/dts/imx6ulz-14x14-evk.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ulz-14x14-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ulz-14x14-evk.dts 2024-06-19 12:33:57.944186478 +0200 @@ -1,17 +1,20 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) // -// Copyright 2018 NXP. +// Copyright 2018-2021 NXP. /dts-v1/; #include "imx6ulz.dtsi" #include "imx6ul-14x14-evk.dtsi" +/delete-node/ &csi; /delete-node/ &fec1; /delete-node/ &fec2; /delete-node/ &can1; /delete-node/ &can2; /delete-node/ &lcdif; +/delete-node/ &ov5640; +/delete-node/ &pxp; /delete-node/ &tsc; / { @@ -19,4 +22,22 @@ compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz"; /delete-node/ panel; + /delete-node/ pxp_v4l2; }; + +&iomuxc { + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ulz-14x14-evk-emmc.dts linux-imx-phytec/arch/arm/boot/dts/imx6ulz-14x14-evk-emmc.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ulz-14x14-evk-emmc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ulz-14x14-evk-emmc.dts 2024-06-19 12:33:57.944186478 +0200 @@ -0,0 +1,25 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx6ulz-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx6ulz-14x14-evk-gpmi-weim.dts linux-imx-phytec/arch/arm/boot/dts/imx6ulz-14x14-evk-gpmi-weim.dts --- linux-6.1.55/arch/arm/boot/dts/imx6ulz-14x14-evk-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx6ulz-14x14-evk-gpmi-weim.dts 2024-06-19 12:33:57.944186478 +0200 @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2018 NXP + +#include "imx6ulz-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; + fsl,use-minimum-ecc; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-12x12-lpddr3-val.dts linux-imx-phytec/arch/arm/boot/dts/imx7d-12x12-lpddr3-val.dts --- linux-6.1.55/arch/arm/boot/dts/imx7d-12x12-lpddr3-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-12x12-lpddr3-val.dts 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,1038 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7D LPDDR3 12x12 Validation Board"; + compatible = "fsl,imx7d-12x12-lpddr3-val", "fsl,imx7d"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_gpio_keys>; + pinctrl-1 = <&pinctrl_gpio_keys_sleep>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_aud_1v8: aud_1v8 { + compatible = "regulator-fixed"; + regulator-name = "AUD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_3v3: can1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + reg_coedc_5v: coedc_5v { + compatible = "regulator-fixed"; + regulator-name = "CODEC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&epdc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_epdc_0>; + pinctrl-1 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&epxp { + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 19 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + pinctrl-1 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "disabled"; + + spi_flash1: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-1 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-1 = <&pinctrl_enet2>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-1 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x8>; + fsl,lpsr-mode; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 31 0>; + gpio_pmic_vcom_ctrl = <&gpio4 14 0>; + gpio_pmic_wakeup = <&gpio4 23 0>; + gpio_pmic_v3p3 = <&gpio4 20 0>; + gpio_pmic_intr = <&gpio4 18 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; + + codec: wm8958@1a { + compatible = "wlf,wm8958"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "MCLK1", "MCLK2"; + + DBVDD1-supply = <®_aud_1v8>; + DBVDD2-supply = <®_aud_1v8>; + DBVDD3-supply = <®_aud_1v8>; + AVDD2-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_coedc_5v>; + SPKVDD2-supply = <®_coedc_5v>; + wlf,ldo1ena; + wlf,ldo2ena; + wlf,gpio-cfg = <0x8102 0xa101 0xa101 0xa101 0xa101 0xa101 + 0xa101 0xa101 0xa101 0xa101 0xa101>; + }; +}; + +&iomuxc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + + imx7d-12x12-lpddr3-arm2 { + + pinctrl_bt: btgrp-1 { + fsl,pins = < + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* BT REG on */ + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x2 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x2 + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x2 + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x2 + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x80000000 /* pwr int */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59 + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59 + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x59 /* STBY */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59 + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59 + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x59 /* STBY */ + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_gpio_keys_sleep: gpio_keysgrp_sleep { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x80000000 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x80000000 + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x80000000 + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x80000000 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_hog_mipi: hoggrp_mipi { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x59 + >; + }; + + pinctrl_hog_sd2_vselect: hoggrp_sd2vselect { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x59 + >; + }; + + pinctrl_hog_headphone_det: hoggrp_headphone_det { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0 + MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x2 + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x2 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x1f + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + pinctrl_sim1_1: sim1grp-1 { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x77 + MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x77 + MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x77 + MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x73 + MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x73 + >; + }; + + }; +}; + +&iomuxc_lpsr { + imx7d-12x12-lpddr3-arm2 { + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + }; + + imx7d-sdb { + pinctrl_usbotg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + pinctrl-1 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ocrams { + fsl,enable-lpsr; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 21 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio6 19 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&sim1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sim1_1>; + pinctrl-1 = <&pinctrl_sim1_1>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-1 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart3_1 + &pinctrl_bt>; + pinctrl-1 = <&pinctrl_uart3_1 + &pinctrl_bt>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1_1>; + pinctrl-1 = <&pinctrl_usdhc1_1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_1>; + cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_1>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + auto-cmd23-broken; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-12x12-lpddr3-val-sai.dts linux-imx-phytec/arch/arm/boot/dts/imx7d-12x12-lpddr3-val-sai.dts --- linux-6.1.55/arch/arm/boot/dts/imx7d-12x12-lpddr3-val-sai.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-12x12-lpddr3-val-sai.dts 2024-06-19 12:33:57.944186478 +0200 @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#include "imx7d-12x12-lpddr3-val.dts" + +/ { + sound { + compatible = "fsl,imx-audio-wm8958"; + model = "wm8958-audio"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + hp-det-gpio = <&gpio1 12 1>; + audio-routing = + "Headphone Jack", "HPOUT1L", + "Headphone Jack", "HPOUT1R", + "Ext Spk", "SPKOUTLP", + "Ext Spk", "SPKOUTLN", + "Ext Spk", "SPKOUTRP", + "Ext Spk", "SPKOUTRN", + "IN1LN", "MICBIAS2"; + }; +}; + +&iomuxc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_headphone_det>; + pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect>; +}; + +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sdma { + status = "okay"; +}; + +&sim1 { + status = "disabled"; +}; + +&usdhc2 { + no-1-8-v; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d.dtsi linux-imx-phytec/arch/arm/boot/dts/imx7d.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx7d.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d.dtsi 2024-06-19 12:33:57.952186615 +0200 @@ -29,7 +29,6 @@ clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; - cpu-idle-states = <&cpu_sleep_wait>; }; }; @@ -79,6 +78,56 @@ }; soc: soc { + busfreq { + compatible = "fsl,imx_busfreq"; + fsl,max_ddr_freq = <533000000>; + clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>, + <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>, + <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>, + <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>, + <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_DIV>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>; + clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", + "dram_alt_sel", "pll_dram", "dram_alt_root", "pfd2_270m", + "pfd1_332m", "ahb", "axi"; + interrupts = <0 112 0x04>, <0 113 0x04>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + }; + + ocrams_ddr: sram@900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x900000 0x1000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocram: sram@901000 { + compatible = "mmio-sram"; + reg = <0x901000 0x1f000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocrams: sram@180000 { + compatible = "fsl,lpm-sram"; + reg = <0x180000 0x8000>; + clocks = <&clks IMX7D_OCRAM_S_CLK>; + status = "disabled"; + }; + + ocram_optee { + compatible = "fsl,optee-lpm-sram"; + reg = <0x180000 0x8000>; + overw_reg = <&ocrams_ddr 0x904000 0x1000>, + <&ocram 0x905000 0x1b000>, + <&ocrams 0x900000 0x4000>; + overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>; + }; + + ocrams_mf: sram-mf@900000 { + compatible = "fsl,mega-fast-sram"; + reg = <0x900000 0x20000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + etm@3007d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x3007d000 0x1000>; @@ -159,15 +208,157 @@ }; }; +/delete-node/&csi; +/delete-node/&video_mux; + &aips2 { pcie_phy: pcie-phy@306d0000 { compatible = "fsl,imx7d-pcie-phy"; reg = <0x306d0000 0x10000>; status = "disabled"; }; + + system_counter_rd: system-counter-rd@306a0000 { + compatible = "fsl,imx7d-system-counter-rd"; + reg = <0x306a0000 0x10000>; + status = "disabled"; + }; + + system_counter_cmp: system-counter-cmp@306b0000 { + compatible = "fsl,imx7d-system-counter-cmp"; + reg = <0x306b0000 0x10000>; + status = "disabled"; + }; + + system_counter_ctrl: system-counter-ctrl@306c0000 { + compatible = "fsl,imx7d-system-counter-ctrl"; + reg = <0x306c0000 0x10000>; + interrupts = , + ; + status = "disabled"; + }; + + epdc: epdc@306f0000 { + compatible = "fsl,imx7d-epdc"; + interrupts = ; + reg = <0x306f0000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "epdc_axi", "epdc_pix", "epdc_ahb"; + epdc-ram = <&gpr 0x4 30>; + qos = <&qosc>; + status = "disabled"; + }; + + epxp: epxp@30700000 { + compatible = "fsl,imx7d-pxp-dma"; + interrupts = , + ; + reg = <0x30700000 0x10000>; + clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + csi1: csi1@30710000 { + compatible = "fsl,imx7d-csi", "fsl,imx6s-csi"; + reg = <0x30710000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7d-mipi-csi"; + reg = <0x30750000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_clk", "phy_clk"; + mipi-phy-supply = <®_1p0d>; + csis-phy-reset = <&src 0x28 2>; + bus-width = <4>; + status = "disabled"; + /delete-node/ ports; + }; + + mipi_dsi: mipi-dsi@30760000 { + compatible = "fsl,imx7d-mipi-dsi"; + reg = <0x30760000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_cfg_clk", "mipi_pllref_clk"; + power-domains = <&pgc_mipi_phy>; + status = "disabled"; + }; + + qosc: qosc@307f0000 { + compatible = "fsl,imx7d-qosc", "syscon"; + reg = <0x307f0000 0x4000>; + }; }; &aips3 { + mu: mu@30aa0000 { + compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + + mu_lp: mu_lp@30aa0000 { + compatible = "fsl,imx7d-mu-lp", "fsl,imx6sx-mu-lp"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + clock-names = "mu"; + status = "okay"; + }; + + sema4: sema4@30ac0000 { + compatible = "fsl,imx7d-sema4"; + reg = <0x30ac0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>; + clock-names = "sema4"; + status = "okay"; + }; + + sim1: sim@30b90000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30b90000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SIM1_ROOT_CLK>; + clock-names = "sim"; + status = "disabled"; + }; + + qspi1: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + sim2: sim@30ba0000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30ba0000 0x10000>; + interrupts = ; + status = "disabled"; + }; + usbotg2: usb@30b20000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b20000 0x200>; @@ -197,7 +388,7 @@ <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET2_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; @@ -205,6 +396,46 @@ fsl,stop-mode = <&gpr 0x10 4>; status = "disabled"; }; + + pcie_ep: pcie_ep@33800000 { + compatible = "fsl,imx7d-pcie-ep"; + reg = <0x33800000 0x4000>, <0x40000000 0x10000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, + <&clks IMX7D_PCIE_PHY_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie_phy>; + resets = <&src IMX7_RESET_PCIEPHY>, + <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx7d-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + status = "disabled"; + }; }; &ca_funnel_in_ports { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb.dts linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb.dts --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb.dts 2024-06-19 12:33:57.948186547 +0200 @@ -19,6 +19,26 @@ reg = <0x80000000 0x80000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -56,6 +76,7 @@ #gpio-cells = <2>; reg = <0>; registers-number = <1>; + registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ spi-max-frequency = <100000>; }; }; @@ -87,16 +108,15 @@ regulator-max-microvolt = <1800000>; }; - reg_brcm: regulator-brcm { + reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "brcm_reg"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-name = "VDD_SD1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; startup-delay-us = <200000>; + off-on-delay-us = <20000>; + enable-active-high; }; reg_lcd_3v3: regulator-lcd-3v3 { @@ -135,16 +155,9 @@ status = "okay"; }; - panel { - compatible = "innolux,at043tn24"; - backlight = <&backlight>; - power-supply = <®_lcd_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; }; sound { @@ -171,6 +184,13 @@ audio-cpu = <&sai3>; hdmi-out; }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + }; }; &adc1 { @@ -191,6 +211,18 @@ cpu-supply = <&sw1a_reg>; }; +&csi1 { + csi-mux-mipi = <&gpr 0x14 4>; + fsl,mipi-mode; + status = "okay"; + + port { + csi_ep: endpoint { + remote-endpoint = <&csi_mipi_ep>; + }; + }; +}; + &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; @@ -211,13 +243,32 @@ }; }; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0 &pinctrl_enet2_reg>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + en-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&epxp { + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; phy-mode = "rgmii"; phy-handle = <ðphy0>; fsl,magic-packet; @@ -241,10 +292,15 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; phy-mode = "rgmii"; phy-handle = <ðphy1>; phy-supply = <®_fec2_3v3>; @@ -259,6 +315,31 @@ status = "okay"; }; +&mipi_csi { + clock-frequency = <240000000>; + status = "okay"; + port { + mipi_sensor_ep: endpoint@1 { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + + csi_mipi_ep: endpoint@2 { + remote-endpoint = <&csi_ep>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -360,6 +441,16 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + fxas2100x@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + }; + + fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; + mpl3115@60 { compatible = "fsl,mpl3115"; reg = <0x60>; @@ -370,6 +461,88 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + sii902x: sii902x@39 { + compatible = "SiI,sii902x"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sii902x>; + interrupt-parent = <&gpio2>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + reg = <0x39>; + status = "okay"; + }; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "disabled"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 31 0>; + gpio_pmic_vcom_ctrl = <&gpio4 14 0>; + gpio_pmic_wakeup = <&gpio2 23 0>; + gpio_pmic_v3p3 = <&gpio2 30 0>; + gpio_pmic_intr = <&gpio2 22 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; }; &i2c4 { @@ -391,16 +564,54 @@ assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; assigned-clock-rates = <0>, <884736000>, <12288000>; }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + clocks = <&clks IMX7D_CLK_DUMMY>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&extended_io 6 GPIO_ACTIVE_HIGH>; + AVDD-supply = <&vgen6_reg>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_sensor_ep>; + }; + }; + }; }; &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; status = "okay"; - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; }; }; }; @@ -440,6 +651,18 @@ status = "okay"; }; +&sim1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim1_1>; + port = <0>; + sven_low_active; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -448,7 +671,18 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ status = "okay"; }; @@ -458,6 +692,7 @@ assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; uart-has-rtscts; + resets = <&modem_reset>; status = "okay"; }; @@ -473,26 +708,35 @@ }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - wakeup-source; - keep-power-in-suspend; + vmmc-supply = <®_sd1_vmmc>; status = "okay"; }; &usdhc2 { + #address-cells = <1>; + #size-cells = <0>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - wakeup-source; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz &pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz &pinctrl_wifi>; keep-power-in-suspend; non-removable; - vmmc-supply = <®_brcm>; + mmc-pwrseq = <&usdhc2_pwrseq>; fsl,tuning-step = <2>; + pm-ignore-notify; + cap-power-off-card; status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; }; &usdhc3 { @@ -503,8 +747,8 @@ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; assigned-clock-rates = <400000000>; bus-width = <8>; - fsl,tuning-step = <2>; non-removable; + auto-cmd23-broken; status = "okay"; }; @@ -525,6 +769,19 @@ >; }; + pinctrl_epdc_elan_touch: epdc_elan_touch_grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x59 + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x80000000 + >; + }; + pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b + >; + }; + pinctrl_ecspi3: ecspi3grp { fsl,pins = < MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 @@ -570,9 +827,34 @@ >; }; - pinctrl_enet2_reg: enet2reggrp { + pinctrl_epdc0: epdcgrp0 { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 >; }; @@ -596,6 +878,27 @@ >; }; + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + pinctrl_hog: hoggrp { fsl,pins = < MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ @@ -692,6 +995,15 @@ >; }; + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pwrgood */ + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 /* vcom_ctrl */ + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x80000000 /* wakeup */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x80000000 /* v3p3 */ + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x80000000 /* pwr int */ + >; + }; pinctrl_spi4: spi4grp { fsl,pins = < MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 @@ -706,6 +1018,22 @@ >; }; + pinctrl_sii902x: hdmigrp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 + >; + }; + + pinctrl_sim1_1: sim1grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x77 + MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x77 + MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x77 + MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x73 + MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x73 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 @@ -717,8 +1045,13 @@ fsl,pins = < MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 - MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 - MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 >; }; @@ -731,6 +1064,15 @@ >; }; + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 @@ -739,9 +1081,28 @@ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b >; }; @@ -826,6 +1187,12 @@ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b >; }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ + >; + }; }; }; @@ -836,6 +1203,12 @@ }; &iomuxc_lpsr { + pinctrl_enet2_reg: enet2reggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x80000000 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-epdc.dts linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-epdc.dts --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-epdc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-epdc.dts 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-epdc.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-epdc.dtsi linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-epdc.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-epdc.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-epdc.dtsi 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ + +&epdc { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "disabled"; +}; + +®_can2_3v3 { + status = "disabled"; +}; + +®_fec2_3v3 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&max17135 { + status = "okay"; +}; + +&sii902x { + status = "disabled"; +}; + +&sim1 { + status = "disabled"; +}; + +&uart5 { + status = "disabled"; +}; + +&i2c3 { + elan@10 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_elan_touch>; + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio6>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + gpio_elan_cs = <&gpio6 13 0>; + gpio_elan_rst = <&gpio6 15 0>; + gpio_intr = <&gpio6 12 0>; + status = "okay"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-gpmi-weim.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&gpmi{ + status = "okay"; + fsl,use-minimum-ecc; +}; + +/* &sai1{ */ + /* status = "disabled"; */ +/* }; */ + +&usdhc3{ + status = "disabled"; +}; + +&uart5{ + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-m4.dts linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-m4.dts --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-m4.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-m4.dts 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-m4.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-m4.dtsi linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-m4.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-m4.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-m4.dtsi 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + m4_reserved: m4@9ff00000 { + no-map; + reg = <0x9ff00000 0x100000>; + }; + + rpmsg_reserved: rpmsg@bff00000 { + no-map; + reg = <0xbff00000 0x100000>; + }; + }; + m4_tcm: tcml@7f8000 { + compatible = "fsl, m4_tcml"; + reg = <0x007f8000 0x8000>; + }; +}; + +&adc1 { + status = "disabled"; +}; + +&adc2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +&gpt3 { + status = "disabled"; +}; + +&gpt4 { + status = "disabled"; +}; + +&ocram { + reg = <0x00901000 0xf000>; +}; + +®_can2_3v3 { + status = "disabled"; +}; + +&rpmsg{ + vdev-nums = <1>; + reg = <0xbfff0000 0x10000>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&wdog3{ + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-mipi-dsi.dts 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-sdb.dts" + +/ { + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; +}; + +&lcdif { + disp-dev = "mipi_dsi_samsung"; + disp-videomode = "TRUULY-WVGA-SYNC-LOW"; +}; + +&mipi_dsi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-mqs.dts linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-mqs.dts --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-mqs.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-mqs.dts 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright NXP 2021 + +#include "imx7d-sdb.dts" + +/ { + mqs: mqs { + #sound-dai-cells = <0>; + compatible = "fsl,imx6sx-mqs"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + clocks = <&clks IMX7D_SAI1_ROOT_CLK>; + clock-names = "mclk"; + gpr = <&gpr>; + status = "okay"; + }; + + sound { + status = "disabled"; + }; + + sound-mqs { + compatible = "simple-audio-card"; + simple-audio-card,name = "simple-mqs-audio"; + + simple-audio-card,dai-link@0 { + format = "left_j"; + bitclock-master = <&sndcpu>; + frame-master = <&sndcpu>; + + sndcpu: cpu { + sound-dai = <&sai1 0>; + }; + codec { + sound-dai = <&mqs 0>; + }; + }; + }; +}; + +&i2c4 { + status = "disabled"; +}; + +&iomuxc { + imx7d-sdb { + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x120b0 + MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x120b0 + >; + }; + }; +}; + +&mipi_csi { + status = "disabled"; +}; + +&sai1 { + #sound-dai-cells = <0>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <24576000>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-pcie-ep.dts linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-pcie-ep.dts --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-pcie-ep.dts 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx7d-sdb.dts" + +&pcie{ + status = "disabled"; +}; + +&pcie_ep{ + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-qspi.dts linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-qspi.dts --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-qspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-qspi.dts 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "imx7d-sdb.dts" +#include "imx7d-sdb-qspi.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-qspi.dtsi linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-qspi.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-qspi.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-qspi.dtsi 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<0>; + + flash0: mx25l51245g@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + reg = <0>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-usd-wifi.dts linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-usd-wifi.dts --- linux-6.1.55/arch/arm/boot/dts/imx7d-sdb-usd-wifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7d-sdb-usd-wifi.dts 2024-06-19 12:33:57.948186547 +0200 @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx7d-sdb.dts" + +/ { + reg_sd2_vmmc: regulator-sd2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_sd1_io_sel: regulator-sd1-vsel { + compatible = "regulator-gpio"; + regulator-name = "SD1 VSEL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 0>, <1800000 1>; + }; +}; + +®_sd1_vmmc { + regulator-always-on; +}; + +&iomuxc { + imx7d-sdb { + pinctrl_usdhc1_vsel_gpio: usdhc1_gpiovselgrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x59 /* VSELECT */ + >; + }; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_vsel_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_vsel_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_vsel_gpio>; + /delete-property/ cd-gpios; + /delete-property/ wp-gpios; + fsl,sdio-async-interrupt-enabled; + /* + * Here config the vsel pad as an normal gpio, and use + * the vqmmc(gpio-regulator) method to do the IO voltage switch. + * set gpio to low level select 3.3v, and high level select 1.8v + * If not, when config this pin as vsel specific function, + * though work normal when sdio boot up and in SDIO 3.0 mode, + * but will meet issue after system resume back from mem + * mode, because after system suspend in mem mode, usdhc + * will lost power, so when resume back, all register + * return to default state, need driver to re-config. + * But for sdio wifi device, we config this device with + * flag keep-power-in-suspend, so sdio wifi do nothing + * during system PM, only mark re-tuning flag. When + * system resume back, the original vsel bit lost, which + * means the IO voltage change to 3.3v, but sdio wifi still + * in SDIO3.0 mode, expect the IO voltage in 1.8v, IO + * voltage mismatch happened, data transfer in this time + * will meet CRC/Timeout issue. + */ + vqmmc-supply = <®_sd1_io_sel>; + keep-power-in-suspend; + non-removable; + wakeup-source; +}; + +&usdhc2 { + status = "disabled"; +}; + +&usdhc2_pwrseq { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7s.dtsi linux-imx-phytec/arch/arm/boot/dts/imx7s.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx7s.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx7s.dtsi 2024-06-19 12:33:57.952186615 +0200 @@ -55,19 +55,6 @@ #address-cells = <1>; #size-cells = <0>; - idle-states { - entry-method = "psci"; - - cpu_sleep_wait: cpu-sleep-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <100>; - exit-latency-us = <50>; - min-residency-us = <1000>; - }; - }; - cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; @@ -75,23 +62,6 @@ clock-frequency = <792000000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; - cpu-idle-states = <&cpu_sleep_wait>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - nvmem-cells = <&fuse_grade>; - nvmem-cell-names = "speed_grade"; - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-792000000 { - opp-hz = /bits/ 64 <792000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <150000>; - opp-supported-hw = <0xf>, <0xf>; }; }; @@ -166,16 +136,6 @@ }; }; - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupt-parent = <&intc>; - interrupts = , - , - , - ; - }; - soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -225,6 +185,11 @@ }; }; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + funnel@30083000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x30083000 0x1000>; @@ -325,6 +290,17 @@ <0x31006000 0x2000>; }; + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + clock-frequency = <8000000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -458,8 +434,9 @@ reg = <0x302d0000 0x10000>; interrupts = ; clocks = <&clks IMX7D_GPT1_ROOT_CLK>, - <&clks IMX7D_GPT1_ROOT_CLK>; - clock-names = "ipg", "per"; + <&clks IMX7D_GPT1_ROOT_CLK>, + <&clks IMX7D_GPT_3M_CLK>; + clock-names = "ipg", "per", "osc_per"; }; gpt2: timer@302e0000 { @@ -608,6 +585,20 @@ }; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -622,6 +613,15 @@ clock-names = "snvs-rtc"; }; + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + value = <0x60>; + mask = <0x60>; + status = "disabled"; + }; + snvs_pwrkey: snvs-powerkey { compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; @@ -658,6 +658,7 @@ interrupts = ; #interrupt-cells = <3>; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x54410000 0xc00 0x0 0x1040640>; #power-domain-cells = <1>; pgc { @@ -721,6 +722,8 @@ clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, <&clks IMX7D_ECSPI4_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 6 7 1>, <&sdma 7 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -818,8 +821,11 @@ reg = <0x30730000 0x10000>; interrupts = ; clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, - <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; - clock-names = "pix", "axi"; + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>; + clock-names = "pix", "axi", "disp_axi"; status = "disabled"; }; @@ -853,6 +859,11 @@ }; }; }; + + ddrc: ddrc@307a0000 { + compatible = "fsl,imx7-ddrc"; + reg = <0x307a0000 0x10000>; + }; }; aips3: bus@30800000 { @@ -878,6 +889,8 @@ clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, <&clks IMX7D_ECSPI1_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 0 7 1>, <&sdma 1 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -890,6 +903,8 @@ clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, <&clks IMX7D_ECSPI2_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 2 7 1>, <&sdma 3 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -902,6 +917,8 @@ clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, <&clks IMX7D_ECSPI3_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 4 7 1>, <&sdma 5 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -924,6 +941,8 @@ clocks = <&clks IMX7D_UART2_ROOT_CLK>, <&clks IMX7D_UART2_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 24 4 0>, <&sdma 25 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -935,6 +954,8 @@ clocks = <&clks IMX7D_UART3_ROOT_CLK>, <&clks IMX7D_UART3_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 26 4 0>, <&sdma 27 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1084,6 +1105,8 @@ clocks = <&clks IMX7D_UART4_ROOT_CLK>, <&clks IMX7D_UART4_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 28 4 0>, <&sdma 29 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1095,6 +1118,8 @@ clocks = <&clks IMX7D_UART5_ROOT_CLK>, <&clks IMX7D_UART5_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 30 4 0>, <&sdma 31 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1106,6 +1131,8 @@ clocks = <&clks IMX7D_UART6_ROOT_CLK>, <&clks IMX7D_UART6_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 32 4 0>, <&sdma 33 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1117,6 +1144,8 @@ clocks = <&clks IMX7D_UART7_ROOT_CLK>, <&clks IMX7D_UART7_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 34 4 0>, <&sdma 35 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1253,7 +1282,7 @@ <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp.dtsi linux-imx-phytec/arch/arm/boot/dts/imx7ulp.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx7ulp.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp.dtsi 2024-06-19 12:33:57.952186615 +0200 @@ -41,9 +41,52 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf00>; + clocks = <&smc1 IMX7ULP_CLK_ARM>, + <&scg1 IMX7ULP_CLK_CORE>, + <&scg1 IMX7ULP_CLK_SYS_SEL>, + <&scg1 IMX7ULP_CLK_HSRUN_CORE>, + <&scg1 IMX7ULP_CLK_HSRUN_SYS_SEL>, + <&scg1 IMX7ULP_CLK_FIRC>; + clock-names = "arm", "core", "scs_sel", + "hsrun_core", "hsrun_scs_sel", + "firc"; + operating-points-v2 = <&cpu0_opp_table>; }; }; + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-500210000 { + opp-hz = /bits/ 64 <500210000>; + opp-microvolt = <1025000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1125000>; + clock-latency-ns = <150000>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0xC000000>; + alignment = <0x2000>; + linux,cma-default; + }; + }; + intc: interrupt-controller@40021000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; @@ -87,6 +130,16 @@ #clock-cells = <0>; }; + sram: sram@20000000 { + compatible = "fsl,lpm-sram"; + reg = <0x1fffc000 0x4000>; + }; + + caam_sm: caam-sm@26000000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x26000000 0x8000>; + }; + ahbbridge0: bus@40000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -122,6 +175,62 @@ <&pcc2 IMX7ULP_CLK_DMA_MUX1>; }; + mu: mu@40220000 { + compatible = "fsl,imx7ulp-mu"; + reg = <0x40220000 0x1000>; + interrupts = ; + #mbox-cells = <2>; + }; + + nmi: nmi@40220000 { + compatible = "fsl,imx7ulp-nmi"; + reg = <0x40220000 0x1000>; + interrupts = ; + status = "okay"; + }; + + mu_lp: mu_lp@40220000 { + compatible = "fsl,imx7ulp-mu-lp", "fsl,imx6sx-mu-lp"; + reg = <0x40220000 0x1000>; + interrupts = , + ; + status = "okay"; + }; + + lpspi2: spi@40290000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7ulp-spi"; + reg = <0x40290000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPSPI2>, + <&pcc2 IMX7ULP_CLK_DUMMY>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPSPI2>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + assigned-clock-rates = <48000000>; + dmas = <&edma1 0 26>, <&edma1 0 25>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi3: spi@402A0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7ulp-spi"; + reg = <0x402A0000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPSPI3>, + <&pcc2 IMX7ULP_CLK_DUMMY>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPSPI3>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + assigned-clock-rates = <48000000>; + dmas = <&edma1 0 28>, <&edma1 0 27>; + dma-names = "tx","rx"; + status = "disabled"; + }; + crypto: crypto@40240000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; @@ -145,6 +254,35 @@ }; }; + lpi2c4: lpi2c4@402b0000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x402b0000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPI2C4>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPI2C4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + assigned-clock-rates = <48000000>; + dmas = <&edma1 0 10>, <&edma1 0 9>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c5: lpi2c5@402c0000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x402c0000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPI2C5>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPI2C5>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + assigned-clock-rates = <48000000>; + dmas = <&edma1 0 12>, <&edma1 0 11>; + dma-names = "tx","rx"; + }; + lpuart4: serial@402d0000 { compatible = "fsl,imx7ulp-lpuart"; reg = <0x402d0000 0x1000>; @@ -164,8 +302,10 @@ clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; clock-names = "ipg"; assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; + dmas = <&edma1 0 20>, <&edma1 0 19>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -213,6 +353,7 @@ interrupts = ; clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; #phy-cells = <0>; + nxp,sim = <&sim>; }; usdhc0: mmc@40370000 { @@ -260,6 +401,21 @@ clocks = <&pcc2 IMX7ULP_CLK_WDG1>; assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + /* + * As the 1KHz LPO clock rate is not trimed,the actually clock + * is about 667Hz, so the init timeout 60s should set 40*1000 + * in the TOVAL register. + */ + timeout-sec = <40>; + }; + + wdog2: wdog@40430000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x40430000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_WDG2>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>; + assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; timeout-sec = <40>; }; @@ -286,6 +442,11 @@ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; }; + pmc1: pmc1@40400000 { + compatible = "fsl,imx7ulp-pmc1"; + reg = <0x40400000 0x1000>; + }; + smc1: clock-controller@40410000 { compatible = "fsl,imx7ulp-smc1"; reg = <0x40410000 0x1000>; @@ -332,8 +493,10 @@ <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; clock-names = "per", "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; + dmas = <&edma1 0 14>, <&edma1 0 13>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -345,8 +508,10 @@ <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; clock-names = "per", "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; + dmas = <&edma1 0 16>, <&edma1 0 15>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -357,8 +522,10 @@ clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; clock-names = "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; + dmas = <&edma1 0 22>, <&edma1 0 21>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -369,8 +536,38 @@ clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; clock-names = "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; + dmas = <&edma1 0 24>, <&edma1 0 23>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + mipi_dsi: mipi_dsi@40a90000 { + compatible = "fsl,imx7ulp-mipi-dsi"; + reg = <0x40a90000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_DSI>; + clock-names = "mipi_dsi_clk"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_DSI>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; + data-lanes-num = <2>; + phy-ref-clkfreq = <24000000>; + max-data-rate = <800000000>; + sim = <&sim>; + status = "disabled"; + }; + + lcdif: lcdif@40aa0000 { + compatible = "fsl,imx7ulp-lcdif"; + reg = <0x40aa0000 0x1000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_DUMMY>, + <&pcc3 IMX7ULP_CLK_LCDIF>, + <&scg1 IMX7ULP_CLK_DUMMY>; + clock-names = "axi", "pix", "disp_axi"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LCDIF>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; status = "disabled"; }; @@ -440,6 +637,28 @@ clock-names = "gpio", "port"; gpio-ranges = <&iomuxc1 0 96 20>; }; + + gpu: gpu@41800000 { + compatible = "fsl,imx7ulp-gpu", "fsl,imx6q-gpu"; + reg = <0x41800000 0x80000>, <0x41880000 0x80000>, + <0x60000000 0x40000000>, <0x0 0x4000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = , + ; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&pcc3 IMX7ULP_CLK_GPU3D>, + <&scg1 IMX7ULP_CLK_DUMMY>, + <&scg1 IMX7ULP_CLK_GPU_DIV>, + <&pcc3 IMX7ULP_CLK_GPU2D>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", + "gpu3d_axi_clk", "gpu2d_clk", + "gpu2d_axi_clk"; + assigned-clocks = <&scg1 IMX7ULP_CLK_APLL_PFD2>, <&pcc3 IMX7ULP_CLK_GPU3D>, <&pcc3 IMX7ULP_CLK_GPU2D>; + assigned-clock-parents = <0>, <&scg1 IMX7ULP_CLK_APLL_PFD2>, <&scg1 IMX7ULP_CLK_APLL_PFD2>; + assigned-clock-rates = <400000000>, <400000000>, <400000000>; + }; }; m4aips1: bus@41080000 { @@ -449,6 +668,11 @@ reg = <0x41080000 0x80000>; ranges; + pmc0: pmc0@410a1000 { + compatible = "fsl,imx7ulp-pmc0"; + reg = <0x410a1000 0x1000>; + }; + sim: sim@410a3000 { compatible = "fsl,imx7ulp-sim", "syscon"; reg = <0x410a3000 0x1000>; @@ -460,4 +684,13 @@ clocks = <&scg1 IMX7ULP_CLK_DUMMY>; }; }; + + heartbeat-rpmsg { + compatible = "fsl,heartbeat-rpmsg"; + }; + + rtc-rpmsg { + compatible = "fsl,imx-rpmsg-rtc"; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb.dts 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,34 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +/ { + model = "NXP i.MX7ULP EVKB"; + compatible = "fsl,imx7ulp-evkb", "fsl,imx7ulp", "Generic DT based system"; + + regulators { + reg_sd1_vmmc: sd1_regulator { + status = "disabled"; + }; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&rpmsg_gpio0 14 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <80>; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/ vmmc-supply; + mmc-pwrseq = <&usdhc1_pwrseq>; + wakeup-source; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-emmc.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-emmc.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-emmc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-emmc.dts 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,26 @@ +/* + * Copyright 2019 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb.dts" + +/* To support eMMC HS200/HS400, need to do the following reowrk: + * 1,remove TF sd slot, replace eMMC chip + * 2,fix eMMC I/O voltage to 1.8v, remove R183, short TP3 and TP89 + * 3,add R107, make eMMC boot work + */ +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0_8bit>; + pinctrl-1 = <&pinctrl_usdhc0_8bit>; + pinctrl-2 = <&pinctrl_usdhc0_8bit>; + pinctrl-3 = <&pinctrl_usdhc0_8bit>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-lpuart.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-lpuart.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-lpuart.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-lpuart.dts 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,17 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb.dts" + +&lpi2c7 { + status = "disabled"; +}; + +&lpuart7 { /* Uart test */ + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-mipi.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-mipi.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-mipi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-mipi.dts 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,25 @@ +/* + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb.dts" +#include "imx7ulp-evk-mipi.dtsi" + +&lpi2c7 { + focaltech@38 { + status = "disabled"; + }; + + goodix@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio_ptf>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio_ptf 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio_ptf 1 GPIO_ACTIVE_HIGH>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-rm68191-qhd.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-rm68191-qhd.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-rm68191-qhd.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-rm68191-qhd.dts 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,13 @@ +/* + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb-mipi.dts" + +&mipi_dsi { + lcd_panel = "ROCKTECH-QHD-RK055IQH042"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-rm68200-wxga.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-rm68200-wxga.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-rm68200-wxga.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-rm68200-wxga.dts 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,13 @@ +/* + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb-mipi.dts" + +&mipi_dsi { + lcd_panel = "ROCKTECH-WXGA-RK055AHD042"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-sd1.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-sd1.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-sd1.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-sd1.dts 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,45 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb.dts" + +/ { + regulators { + reg_vsd_3v3b: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3B"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_pte 11 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + }; +}; + +&lpuart6 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + pinctrl-1 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + pinctrl-2 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_usdhc1_rst>; + cd-gpios = <&gpio_pte 13 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio_pte 12 GPIO_ACTIVE_HIGH>; + fsl,delay-line = <15>; + vmmc-supply = <®_vsd_3v3b>; + /delete-property/non-removable; + /delete-property/pm-ignore-notify; + /delete-property/keep-power-in-suspend; + /delete-property/non-removable; + /delete-property/no-1-8-v; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-sensors-to-i2c5.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-sensors-to-i2c5.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-sensors-to-i2c5.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-sensors-to-i2c5.dts 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,21 @@ + +#include "imx7ulp-evkb.dts" + +&lpi2c5 { + + fxas2100x@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + }; + + fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-spi-slave.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-spi-slave.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evkb-spi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evkb-spi-slave.dts 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,30 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evkb.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi3 { + fsl,pins = < + IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0 + IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0 + IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0 + IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0 + >; +}; + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + /delete-property/ cs-gpios; + + spi-slave; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evk.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evk.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evk.dts 2024-06-19 12:33:57.952186615 +0200 @@ -8,11 +8,17 @@ /dts-v1/; #include "imx7ulp.dtsi" +#include / { model = "NXP i.MX7ULP EVK"; compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; + aliases { + gpio4 = &rpmsg_gpio0; + gpio5 = &rpmsg_gpio1; + }; + chosen { stdout-path = &lpuart4; }; @@ -22,6 +28,38 @@ reg = <0x60000000 0x40000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rsc_table: rsc-table@1fff8000{ + reg = <0x1fff8000 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@9ff00000 { + reg = <0x9ff00000 0x8000>; + no-map; + }; + vdev0vring1: vdev0vring1@9ff08000 { + reg = <0x9ff08000 0x8000>; + no-map; + }; + vdev1vring0: vdev1vring0@9ff10000 { + reg = <0x9ff10000 0x8000>; + no-map; + }; + vdev1vring1: vdev1vring1@9ff18000 { + reg = <0x9ff18000 0x8000>; + no-map; + }; + vdev1vring3 { + reg = <0x9ff20000 0xe0000>; + no-map; + }; + }; + backlight { compatible = "pwm-backlight"; pwms = <&tpm4 1 50000 0>; @@ -30,35 +68,348 @@ status = "okay"; }; - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; - enable-active-high; + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio_ptc 19 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&rpmsg_gpio0 15 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + pf1550-rpmsg { + compatible = "fsl,pf1550-rpmsg"; + sw1_reg: SW1 { + regulator-name = "SW1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: SW2 { + regulator-name = "SW2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: SW3 { + regulator-name = "SW3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: VREFDDR { + regulator-name = "VREFDDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cell = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + pinctrl-1 = <&pinctrl_usbotg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vsd_3v3: regulator-vsd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0_rst>; + gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_regulator { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&rpmsg_gpio0 14 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + off-on-delay-us = <20000>; + enable-active-high; + }; + }; + + rpmsg_gpio0: rpmsg-gpio0 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <0>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio0>; + status = "okay"; }; - reg_vsd_3v3: regulator-vsd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + rpmsg_gpio1: rpmsg-gpio1 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <1>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio1>; + status = "okay"; + }; + + rpmsg_keys: rpmsg-keys { + compatible = "fsl,rpmsg-keys"; + + volume-up { + label = "Volume Up"; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + linux,code = ; + }; + + power-on { + label = "PowerOn"; + linux,code = ; + rpmsg-key,wakeup; + }; + }; + + rpmsg_sensor: rpmsg-sensor { + compatible = "nxp,rpmsg-iio-pedometer", "fsl,rpmsg-input"; + }; + + rpmsg_audio: rpmsg_audio { + compatible = "fsl,imx7ulp-rpmsg-audio"; + model = "wm8960-audio"; + fsl,rpmsg-out; + fsl,rpmsg-in; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + }; + + imx7ulp-cm4 { + compatible = "fsl,imx7ulp-cm4"; + ipc-only; + rsc-da=<0x1fff8000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + }; +}; + +&cpu0 { + cpu-supply= <&sw1_reg>; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + }; +}; + +&lpi2c5 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5>; + status = "okay"; + + adv7535: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; /* PD pin is low */ pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc0_rst>; - gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; - enable-active-high; + pinctrl-0 = <&pinctrl_dsi_hdmi>; + interrupt-parent = <&gpio_ptc>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + video-mode = <1>; /* + * Only support CEA modes. + * Reference mxc_edid.c + */ + dsi-traffic-mode = <0>; + bpp = <24>; + status = "disabled"; + }; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; }; }; &lpuart4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_lpuart4>; + pinctrl-1 = <&pinctrl_lpuart4>; status = "okay"; }; +&lpuart6 { /* BT */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart6>; + pinctrl-1 = <&pinctrl_lpuart6>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart7 { /* Uart test */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart7>; + pinctrl-1 = <&pinctrl_lpuart7>; + status = "disabled"; +}; + +&lpi2c7 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c7 &pinctrl_touch_io>; + pinctrl-1 = <&pinctrl_lpi2c7 &pinctrl_touch_io>; + status = "okay"; + + focaltech@38 { + compatible = "focaltech,fts"; + reg = <0x38>; + interrupt-parent = <&gpio_ptf>; + interrupts = <0 0x2>; + focaltech,panel-type = ; + focaltech,reset-gpio = <&gpio_ptf 1 0x1>; + focaltech,irq-gpio = <&gpio_ptf 0 0x2>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 480 854>; + + focaltech,have-key; + focaltech,key-number = <3>; + focaltech,keys = <139 102 158>; + focaltech,key-y-coord = <2000>; + focaltech,key-x-coords = <200 600 800>; + }; +}; + +&adv7535 { + status = "okay"; + + port { + dsi_to_hdmi: endpoint { + remote-endpoint = <&mipi_dsi_ep>; + }; + }; +}; + +&mipi_dsi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + pinctrl-1 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + status = "okay"; + + port { + mipi_dsi_ep: endpoint { + remote-endpoint = <&dsi_to_hdmi>; + }; + }; +}; + &tpm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0>; @@ -67,8 +418,9 @@ &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_usbotg1_id>; + pinctrl-1 = <&pinctrl_usbotg1_id>; srp-disable; hnp-disable; adp-disable; @@ -76,17 +428,55 @@ status = "okay"; }; +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + &usdhc0 { - assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; - pinctrl-names = "default"; + assigned-clocks = <&scg1 IMX7ULP_CLK_APLL_PFD1>, <&pcc2 IMX7ULP_CLK_USDHC0>; + assigned-clock-parents = <0>, <&scg1 IMX7ULP_CLK_APLL_PFD1>; + assigned-clock-rates = <0>, <352800000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + fsl,delay-line = <15>; cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; vmmc-supply = <®_vsd_3v3>; + vqmmc-supply = <&vldo2_reg>; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&scg1 IMX7ULP_CLK_APLL_PFD1>, <&pcc2 IMX7ULP_CLK_USDHC1>; + assigned-clock-parents = <0>, <&scg1 IMX7ULP_CLK_APLL_PFD1>; + assigned-clock-rates = <0>, <352800000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + bus-width = <4>; + no-1-8-v; + vmmc-supply = <®_sd1_vmmc>; + keep-power-in-suspend; + non-removable; status = "okay"; }; &iomuxc1 { + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27 + IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27 + >; + }; + + pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { + fsl,pins = < + IMX7ULP_PAD_PTC19__PTC19 0x20003 + >; + }; + pinctrl_lpuart4: lpuart4grp { fsl,pins = < IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 @@ -95,12 +485,54 @@ bias-pull-up; }; + pinctrl_lpuart6: lpuart6grp { + fsl,pins = < + IMX7ULP_PAD_PTE10__LPUART6_TX 0x3 + IMX7ULP_PAD_PTE11__LPUART6_RX 0x3 + IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3 + IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3 + IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */ + >; + }; + + pinctrl_lpuart7: lpuart7grp { + fsl,pins = < + IMX7ULP_PAD_PTF14__LPUART7_TX 0x3 + IMX7ULP_PAD_PTF15__LPUART7_RX 0x3 + IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3 + IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3 + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27 + IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27 + >; + }; + + pinctrl_touch_io: touchiogrp { + fsl,pins = < + IMX7ULP_PAD_PTF0__PTF0 0x10043 + IMX7ULP_PAD_PTF1__PTF1 0x20043 + >; + }; + pinctrl_pwm0: pwm0grp { fsl,pins = < IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 >; }; + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0 + IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0 + IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0 + IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0 + >; + }; + pinctrl_usbotg1_vbus: otg1vbusgrp { fsl,pins = < IMX7ULP_PAD_PTC0__PTC0 0x20000 @@ -125,9 +557,51 @@ >; }; + pinctrl_usdhc0_8bit: usdhc0grp_8bit { + fsl,pins = < + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 + IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 + IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 + IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 + IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 + >; + }; + pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp { fsl,pins = < IMX7ULP_PAD_PTD0__PTD0 0x3 >; }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43 + IMX7ULP_PAD_PTE2__SDHC1_CLK 0x10042 + IMX7ULP_PAD_PTE1__SDHC1_D0 0x43 + IMX7ULP_PAD_PTE0__SDHC1_D1 0x43 + IMX7ULP_PAD_PTE5__SDHC1_D2 0x43 + IMX7ULP_PAD_PTE4__SDHC1_D3 0x43 + >; + }; + + pinctrl_usdhc1_rst: usdhc1grp_rst { + fsl,pins = < + IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */ + IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */ + IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */ + IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */ + >; + }; + + pinctrl_dsi_hdmi: dsi_hdmi_grp { + fsl,pins = < + IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */ + >; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evk-ft5416.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evk-ft5416.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evk-ft5416.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evk-ft5416.dts 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,15 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" +&lpi2c7 { + focaltech@38 { + focaltech,panel-type = ; + focaltech,swap-xy; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evk-mipi.dts linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evk-mipi.dts --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evk-mipi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evk-mipi.dts 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,10 @@ +/* + * Copyright 2017-2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" +#include "imx7ulp-evk-mipi.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/imx7ulp-evk-mipi.dtsi linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evk-mipi.dtsi --- linux-6.1.55/arch/arm/boot/dts/imx7ulp-evk-mipi.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/boot/dts/imx7ulp-evk-mipi.dtsi 2024-06-19 12:33:57.952186615 +0200 @@ -0,0 +1,23 @@ +/* + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&adv7535 { + status = "disabled"; + + /delete-node/ port; +}; + +&mipi_dsi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + pinctrl-1 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + + /delete-node/ port; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/ls1021a.dtsi linux-imx-phytec/arch/arm/boot/dts/ls1021a.dtsi --- linux-6.1.55/arch/arm/boot/dts/ls1021a.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/ls1021a.dtsi 2024-06-19 12:33:57.968186889 +0200 @@ -321,7 +321,7 @@ }; i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1021a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; @@ -333,7 +333,7 @@ }; i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1021a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; @@ -341,11 +341,12 @@ clocks = <&clockgen 4 1>; dma-names = "rx", "tx"; dmas = <&edma0 1 36>, <&edma0 1 37>; + scl-gpios = <&gpio3 27 0>; status = "disabled"; }; i2c2: i2c@21a0000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1021a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x21a0000 0x0 0x10000>; @@ -353,6 +354,7 @@ clocks = <&clockgen 4 1>; dma-names = "rx", "tx"; dmas = <&edma0 1 34>, <&edma0 1 35>; + scl-gpios = <&gpio1 11 0>; status = "disabled"; }; @@ -808,7 +810,9 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + usb3-lpm-capable; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; pcie@3400000 { @@ -816,7 +820,9 @@ reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ + interrupts = , + ; /* aer interrupt */ + interrupt-names = "pme", "aer"; fsl,pcie-scfg = <&scfg 0>; #address-cells = <3>; #size-cells = <2>; @@ -840,7 +846,9 @@ reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */ <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = ; + interrupts = , + ; /* aer interrupt */ + interrupt-names = "pme", "aer"; fsl,pcie-scfg = <&scfg 1>; #address-cells = <3>; #size-cells = <2>; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/boot/dts/Makefile linux-imx-phytec/arch/arm/boot/dts/Makefile --- linux-6.1.55/arch/arm/boot/dts/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/boot/dts/Makefile 2024-06-19 12:33:57.828184494 +0200 @@ -529,8 +529,19 @@ imx6dl-rex-basic.dtb \ imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ + imx6dl-sabreauto-enetirq.dtb \ + imx6dl-sabreauto-flexcan1.dtb \ + imx6dl-sabreauto-ecspi.dtb \ + imx6dl-sabreauto-gpmi-weim.dtb \ + imx6dl-sabreauto-pcie.dtb \ imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ + imx6dl-sabresd-ldo.dtb \ + imx6dl-sabresd-btwifi.dtb \ + imx6dl-sabresd-hdcp.dtb \ + imx6dl-sabresd-enetirq.dtb \ + imx6dl-sabresd-pcie.dtb \ + imx6dl-sabresd-pcie-ep.dtb \ imx6dl-savageboard.dtb \ imx6dl-skov-revc-lt2.dtb \ imx6dl-skov-revc-lt6.dtb \ @@ -635,8 +646,20 @@ imx6q-prtwd2.dtb \ imx6q-rex-pro.dtb \ imx6q-sabreauto.dtb \ + imx6q-sabreauto-enetirq.dtb \ + imx6q-sabreauto-flexcan1.dtb \ + imx6q-sabreauto-ecspi.dtb \ + imx6q-sabreauto-gpmi-weim.dtb \ + imx6q-sabreauto-pcie.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ + imx6q-sabresd-ldo.dtb \ + imx6q-sabresd-btwifi.dtb \ + imx6q-sabresd-hdcp.dtb \ + imx6q-sabresd-uart.dtb \ + imx6q-sabresd-enetirq.dtb \ + imx6q-sabresd-pcie.dtb \ + imx6q-sabresd-pcie-ep.dtb \ imx6q-savageboard.dtb \ imx6q-sbc6x.dtb \ imx6q-skov-revc-lt2.dtb \ @@ -670,7 +693,14 @@ imx6qp-phytec-mira-rdk-nand.dtb \ imx6qp-prtwd3.dtb \ imx6qp-sabreauto.dtb \ + imx6qp-sabreauto-flexcan1.dtb \ + imx6qp-sabreauto-ecspi.dtb \ + imx6qp-sabreauto-gpmi-weim.dtb \ imx6qp-sabresd.dtb \ + imx6qp-sabresd-ldo.dtb \ + imx6qp-sabresd-btwifi.dtb \ + imx6qp-sabresd-hdcp.dtb \ + imx6qp-sabresd-pcie-ep.dtb \ imx6qp-tx6qp-8037.dtb \ imx6qp-tx6qp-8037-mb7.dtb \ imx6qp-tx6qp-8137.dtb \ @@ -682,27 +712,49 @@ imx6s-dhcom-drc02.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ + imx6sl-evk-ldo.dtb \ + imx6sl-evk-csi.dtb \ + imx6sl-evk-uart.dtb \ + imx6sl-evk-btwifi.dtb \ imx6sl-tolino-shine2hd.dtb \ imx6sl-tolino-shine3.dtb \ imx6sl-tolino-vision5.dtb \ imx6sl-warp.dtb dtb-$(CONFIG_SOC_IMX6SLL) += \ imx6sll-evk.dtb \ + imx6sll-evk-reva.dtb \ + imx6sll-evk-btwifi.dtb \ imx6sll-kobo-clarahd.dtb \ imx6sll-kobo-librah2o.dtb dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-nitrogen6sx.dtb \ imx6sx-sabreauto.dtb \ imx6sx-sdb-reva.dtb \ + imx6sx-sdb-reva-ldo.dtb \ imx6sx-sdb-sai.dtb \ imx6sx-sdb.dtb \ + imx6sx-sdb-ldo.dtb \ + imx6sx-sdb-emmc.dtb \ + imx6sx-sdb-lcdif1.dtb \ + imx6sx-sdb-m4.dtb \ imx6sx-sdb-mqs.dtb \ + imx6sx-sdb-btwifi.dtb \ + imx6sx-sdb-pcie-ep.dtb \ imx6sx-softing-vining-2000.dtb \ imx6sx-udoo-neo-basic.dtb \ imx6sx-udoo-neo-extended.dtb \ imx6sx-udoo-neo-full.dtb dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-14x14-evk.dtb \ + imx6ul-14x14-evk-csi.dtb \ + imx6ul-14x14-evk-emmc.dtb \ + imx6ul-14x14-evk-btwifi.dtb \ + imx6ul-14x14-evk-ecspi-slave.dtb \ + imx6ul-14x14-evk-ecspi.dtb \ + imx6ul-14x14-evk-gpmi-weim.dtb \ + imx6ul-9x9-evk.dtb \ + imx6ul-9x9-evk-ldo.dtb \ + imx6ul-9x9-evk-btwifi.dtb \ imx6ul-ccimx6ulsbcexpress.dtb \ imx6ul-ccimx6ulsbcpro.dtb \ imx6ul-geam.dtb \ @@ -725,6 +777,12 @@ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ imx6ull-14x14-evk.dtb \ + imx6ull-14x14-evk-emmc.dtb \ + imx6ull-14x14-evk-btwifi.dtb \ + imx6ull-14x14-evk-gpmi-weim.dtb \ + imx6ull-9x9-evk.dtb \ + imx6ull-9x9-evk-ldo.dtb \ + imx6ull-9x9-evk-btwifi.dtb \ imx6ull-colibri-aster.dtb \ imx6ull-colibri-emmc-aster.dtb \ imx6ull-colibri-emmc-eval-v3.dtb \ @@ -749,7 +807,43 @@ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ + imx6ulz-14x14-evk-btwifi.dtb \ + imx6ulz-14x14-evk-emmc.dtb \ + imx6ulz-14x14-evk-gpmi-weim.dtb \ imx6ulz-bsh-smm-m2.dtb + +imx6ul-14x14-evk-reve-dtbs := imx6ul-14x14-evk.dtb imx6ul-14x14-evk-reve.dtbo +imx6ul-14x14-evk-reve-csi-dtbs := imx6ul-14x14-evk-csi.dtb imx6ul-14x14-evk-reve.dtbo +imx6ul-14x14-evk-reve-emmc-dtbs := imx6ul-14x14-evk-emmc.dtb imx6ul-14x14-evk-reve.dtbo +imx6ul-14x14-evk-reve-btwifi-dtbs := imx6ul-14x14-evk-btwifi.dtb imx6ul-14x14-evk-reve.dtbo +imx6ul-14x14-evk-reve-ecspi-slave-dtbs := imx6ul-14x14-evk-ecspi-slave.dtb imx6ul-14x14-evk-reve.dtbo +imx6ul-14x14-evk-reve-ecspi-dtbs := imx6ul-14x14-evk-ecspi.dtb imx6ul-14x14-evk-reve.dtbo +imx6ul-14x14-evk-reve-gpmi-weim-dtbs := imx6ul-14x14-evk-gpmi-weim.dtb imx6ul-14x14-evk-reve.dtbo +imx6ull-14x14-evk-reve-dtbs := imx6ull-14x14-evk.dtb imx6ul-14x14-evk-reve.dtbo +imx6ull-14x14-evk-reve-emmc-dtbs := imx6ull-14x14-evk-emmc.dtb imx6ul-14x14-evk-reve.dtbo +imx6ull-14x14-evk-reve-btwifi-dtbs := imx6ull-14x14-evk-btwifi.dtb imx6ul-14x14-evk-reve.dtbo +imx6ull-14x14-evk-reve-gpmi-weim-dtbs := imx6ull-14x14-evk-gpmi-weim.dtb imx6ul-14x14-evk-reve.dtbo +imx6ulz-14x14-evk-reve-dtbs := imx6ulz-14x14-evk.dtb imx6ul-14x14-evk-reve.dtbo +imx6ulz-14x14-evk-reve-btwifi-dtbs := imx6ulz-14x14-evk-btwifi.dtb imx6ul-14x14-evk-reve.dtbo +imx6ulz-14x14-evk-reve-emmc-dtbs := imx6ulz-14x14-evk-emmc.dtb imx6ul-14x14-evk-reve.dtbo +imx6ulz-14x14-evk-reve-gpmi-weim-dtbs := imx6ulz-14x14-evk-gpmi-weim.dtb imx6ul-14x14-evk-reve.dtbo +dtb-$(CONFIG_SOC_IMX6UL) += \ + imx6ul-14x14-evk-reve.dtb \ + imx6ul-14x14-evk-reve-csi.dtb \ + imx6ul-14x14-evk-reve-emmc.dtb \ + imx6ul-14x14-evk-reve-btwifi.dtb \ + imx6ul-14x14-evk-reve-ecspi-slave.dtb \ + imx6ul-14x14-evk-reve-ecspi.dtb \ + imx6ul-14x14-evk-reve-gpmi-weim.dtb \ + imx6ull-14x14-evk-reve.dtb \ + imx6ull-14x14-evk-reve-emmc.dtb \ + imx6ull-14x14-evk-reve-btwifi.dtb \ + imx6ull-14x14-evk-reve-gpmi-weim.dtb \ + imx6ulz-14x14-evk-reve.dtb \ + imx6ulz-14x14-evk-reve-btwifi.dtb \ + imx6ulz-14x14-evk-reve-emmc.dtb \ + imx6ulz-14x14-evk-reve-gpmi-weim.dtb + dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-aster.dtb \ @@ -772,9 +866,19 @@ imx7d-remarkable2.dtb \ imx7d-sbc-imx7.dtb \ imx7d-sdb.dtb \ + imx7d-sdb-epdc.dtb \ + imx7d-sdb-mipi-dsi.dtb \ + imx7d-sdb-gpmi-weim.dtb \ + imx7d-sdb-m4.dtb \ + imx7d-sdb-mqs.dtb \ + imx7d-sdb-qspi.dtb \ imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ + imx7d-sdb-usd-wifi.dtb \ + imx7d-sdb-pcie-ep.dtb \ imx7d-smegw01.dtb \ + imx7d-12x12-lpddr3-val.dtb \ + imx7d-12x12-lpddr3-val-sai.dtb \ imx7d-zii-rmu2.dtb \ imx7d-zii-rpu2.dtb \ imx7s-colibri-aster.dtb \ @@ -785,7 +889,19 @@ imx7s-warp.dtb dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-com.dtb \ - imx7ulp-evk.dtb + imx7ulp-evk.dtb \ + imx7ulp-evk-ft5416.dtb \ + imx7ulp-evk-mipi.dtb \ + imx7ulp-evkb.dtb \ + imx7ulp-evkb-emmc.dtb \ + imx7ulp-evkb-sd1.dtb \ + imx7ulp-evkb-spi-slave.dtb \ + imx7ulp-evkb-sensors-to-i2c5.dtb \ + imx7ulp-evkb-lpuart.dtb \ + imx7ulp-evkb-mipi.dtb \ + imx7ulp-evkb-rm68200-wxga.dtb \ + imx7ulp-evkb-rm68200-wxga.dtb \ + imx7ulp-evkb-rm68191-qhd.dtb dtb-$(CONFIG_SOC_IMXRT) += \ imxrt1050-evk.dtb dtb-$(CONFIG_SOC_LAN966) += \ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/configs/imx_v6_v7_defconfig linux-imx-phytec/arch/arm/configs/imx_v6_v7_defconfig --- linux-6.1.55/arch/arm/configs/imx_v6_v7_defconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/configs/imx_v6_v7_defconfig 2024-06-19 12:33:58.068188599 +0200 @@ -1,14 +1,20 @@ -CONFIG_KERNEL_LZO=y CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y CONFIG_BPF_SYSCALL=y -CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_PREEMPT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y CONFIG_CGROUP_BPF=y +CONFIG_MEMCG=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y @@ -28,6 +34,13 @@ CONFIG_SOC_IMX7D=y CONFIG_SOC_IMX7ULP=y CONFIG_SOC_VF610=y +CONFIG_FXAS21002C=y +CONFIG_FXOS8700_I2C=y +CONFIG_RPMSG_IIO_PEDOMETER=m +CONFIG_SENSORS_ISL29018=y +CONFIG_MAG3110=y +CONFIG_MPL3115=y +CONFIG_MMA8452=y CONFIG_SMP=y CONFIG_ARM_PSCI=y CONFIG_HIGHMEM=y @@ -43,6 +56,7 @@ CONFIG_CPUFREQ_DT=y CONFIG_ARM_IMX6Q_CPUFREQ=y CONFIG_ARM_IMX_CPUFREQ_DT=y +CONFIG_ARM_IMX7ULP_CPUFREQ=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y @@ -57,26 +71,46 @@ CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_BINFMT_MISC=m # CONFIG_COMPAT_BRK is not set +CONFIG_CMA=y +CONFIG_SECCOMP=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y +CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_NETFILTER=y +CONFIG_VLAN_8021Q=m +CONFIG_LLC2=y CONFIG_CAN=y CONFIG_BT=y -CONFIG_BT_BNEP=m +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIBTUSB=y CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIVHCI=y +CONFIG_BT_MRVL=y +CONFIG_BT_MRVL_SDIO=y CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=y -CONFIG_RFKILL=y -CONFIG_RFKILL_INPUT=y CONFIG_PCI=y CONFIG_PCI_MSI=y -CONFIG_PCI_IMX6=y +CONFIG_PCI_IMX6_HOST=y +CONFIG_PCI_IMX6_EP=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set @@ -101,9 +135,11 @@ CONFIG_MTD_NAND_VF610_NFC=y CONFIG_MTD_NAND_MXC=y CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_BLOCK=y +CONFIG_OF_OVERLAY=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=65536 @@ -119,6 +155,10 @@ CONFIG_SATA_AHCI_PLATFORM=y CONFIG_AHCI_IMX=y CONFIG_PATA_IMX=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_BROADCOM is not set CONFIG_CS89x0_PLATFORM=y @@ -146,10 +186,7 @@ CONFIG_USB_NET_MCS7830=y CONFIG_ATH10K=m CONFIG_ATH10K_SDIO=m -CONFIG_BRCMFMAC=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_SDIO=m -CONFIG_MWIFIEX_PCIE=m +CONFIG_HOSTAP=y CONFIG_WL12XX=m CONFIG_WL18XX=m CONFIG_WLCORE_SDIO=m @@ -157,6 +194,7 @@ CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_RPMSG=y CONFIG_KEYBOARD_SNVS_PWRKEY=y CONFIG_KEYBOARD_IMX=y CONFIG_MOUSE_PS2=m @@ -170,6 +208,8 @@ CONFIG_TOUCHSCREEN_EGALAX=y CONFIG_TOUCHSCREEN_GOODIX=y CONFIG_TOUCHSCREEN_ILI210X=y +CONFIG_TOUCHSCREEN_ELAN_TS=y +CONFIG_TOUCHSCREEN_FTS=y CONFIG_TOUCHSCREEN_MAX11801=y CONFIG_TOUCHSCREEN_IMX6UL_TSC=y CONFIG_TOUCHSCREEN_EDT_FT5X06=y @@ -197,17 +237,20 @@ CONFIG_I2C_ALGOPCA=m CONFIG_I2C_GPIO=y CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y CONFIG_SPI=y CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_FSL_LPSPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y CONFIG_SPI_FSL_DSPI=y -CONFIG_PINCTRL_IMX8MM=y -CONFIG_PINCTRL_IMX8MN=y -CONFIG_PINCTRL_IMX8MP=y -CONFIG_PINCTRL_IMX8MQ=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MXC=y +CONFIG_GPIO_IMX_RPMSG=y CONFIG_GPIO_SIOX=m CONFIG_GPIO_MAX732X=y CONFIG_GPIO_PCA953X=y @@ -217,15 +260,19 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_POWER_SUPPLY=y CONFIG_RN5T618_POWER=m +CONFIG_SABRESD_MAX8903=y +CONFIG_PCI_ENDPOINT_TEST=y CONFIG_SENSORS_MC13783_ADC=y CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_MAX17135=y CONFIG_SENSORS_IIO_HWMON=y +CONFIG_THERMAL=y CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y CONFIG_WATCHDOG=y CONFIG_DA9063_WATCHDOG=m CONFIG_DA9062_WATCHDOG=y @@ -237,7 +284,9 @@ CONFIG_MFD_DA9063=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=y +CONFIG_MFD_MAX17135=y CONFIG_MFD_RN5T618=y +CONFIG_MFD_SI476X_CORE=y CONFIG_MFD_STMPE=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y @@ -246,26 +295,41 @@ CONFIG_REGULATOR_DA9063=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_LTC3676=y +CONFIG_REGULATOR_MAX17135=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_PF1550_RPMSG=y CONFIG_REGULATOR_PFUZE100=y CONFIG_REGULATOR_RN5T618=y CONFIG_RC_CORE=y CONFIG_RC_DEVICES=y CONFIG_IR_GPIO_CIR=y CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_MUX=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_VADC=m +CONFIG_MXC_MIPI_CSI=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5640_V2=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y CONFIG_VIDEO_CODA=m CONFIG_VIDEO_IMX_PXP=y CONFIG_VIDEO_OV2680=m -CONFIG_VIDEO_OV5640=m CONFIG_VIDEO_OV5645=m CONFIG_VIDEO_ADV7180=m -CONFIG_IMX_IPUV3_CORE=y +CONFIG_RADIO_SI476X=y CONFIG_DRM=y CONFIG_DRM_MSM=y CONFIG_DRM_PANEL_LVDS=y @@ -273,17 +337,24 @@ CONFIG_DRM_PANEL_EDP=y CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_TI_TFP410=y -CONFIG_DRM_DW_HDMI_AHB_AUDIO=m -CONFIG_DRM_DW_HDMI_CEC=y -CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_TVE=y -CONFIG_DRM_IMX_LDB=y -CONFIG_DRM_IMX_HDMI=y -CONFIG_DRM_ETNAVIV=y -CONFIG_DRM_MXSFB=y CONFIG_FB=y -CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_EINK_PANEL=y +CONFIG_FB_MXC_EINK_V2_PANEL=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_MIPI_DSI_NORTHWEST=y +CONFIG_FB_MXC_MIPI_DSI_SAMSUNG=y +CONFIG_FB_MXC_ADV7535=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_TRULY_PANEL_TFT3P5581E=y +CONFIG_FB_MXC_RK_PANEL_RK055AHD042=y +CONFIG_FB_MXC_RK_PANEL_RK055IQH042=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_OVERLAY=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXS_SII902X=y +CONFIG_FB_MXC_DCIC=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y @@ -296,24 +367,36 @@ CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=y CONFIG_SND_SOC_FSL_ASRC=y +CONFIG_SND_SOC_FSL_MQS=y +CONFIG_SND_SOC_FSL_RPMSG=y CONFIG_SND_IMX_SOC=y CONFIG_SND_SOC_EUKREA_TLV320=y +CONFIG_SND_SOC_IMX_SII902X=y +CONFIG_SND_SOC_IMX_WM8958=y +CONFIG_SND_SOC_IMX_RPMSG=y CONFIG_SND_SOC_IMX_ES8328=y CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_MQS=y CONFIG_SND_SOC_IMX_SPDIF=y -CONFIG_SND_SOC_FSL_ASOC_CARD=y +CONFIG_SND_SOC_IMX_SI476X=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_SND_SOC_IMX6QDL_HDMI=y CONFIG_SND_SOC_AC97_CODEC=y -CONFIG_SND_SOC_CS42XX8_I2C=y CONFIG_SND_SOC_TLV320AIC3X_I2C=y +CONFIG_SND_SOC_FSL_ASOC_CARD=y +CONFIG_SND_SOC_CS42XX8_I2C=y CONFIG_SND_SOC_WM8960=y CONFIG_SND_SOC_WM8962=y +CONFIG_SND_SOC_RPMSG_WM8960=y CONFIG_SND_SIMPLE_CARD=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_WACOM=y CONFIG_I2C_HID_OF=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG_WHITELIST=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HCD_TEST_MODE=y CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y @@ -358,11 +441,10 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_ESDHC_IMX=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y +CONFIG_MXC_SIM=y +CONFIG_MXC_SIMv2=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y -CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y @@ -383,33 +465,33 @@ CONFIG_RTC_DRV_MXC=y CONFIG_RTC_DRV_MXC_V2=y CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_IMX_RPMSG=y CONFIG_DMADEVICES=y CONFIG_FSL_EDMA=y CONFIG_IMX_SDMA=m CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_V3=y CONFIG_DMATEST=m CONFIG_STAGING=y CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_IMX_MEDIA=y CONFIG_COMMON_CLK_PWM=y -CONFIG_CLK_IMX8MM=y -CONFIG_CLK_IMX8MN=y -CONFIG_CLK_IMX8MP=y -CONFIG_CLK_IMX8MQ=y -CONFIG_SOC_IMX8M=y +CONFIG_EXTCON_USB_GPIO=y CONFIG_IIO=y -CONFIG_MMA8452=y CONFIG_IMX7D_ADC=y CONFIG_RN5T618_ADC=y CONFIG_STMPE_ADC=y CONFIG_VF610_ADC=y -CONFIG_SENSORS_ISL29018=y -CONFIG_MAG3110=y -CONFIG_MPL3115=y CONFIG_PWM=y CONFIG_PWM_FSL_FTM=y CONFIG_PWM_IMX27=y CONFIG_PWM_IMX_TPM=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y +CONFIG_MAILBOX=y +CONFIG_IMX_MBOX=y +CONFIG_REMOTEPROC=y +CONFIG_IMX_REMOTEPROC=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_VF610_OCOTP=y CONFIG_NVMEM_SNVS_LPGPR=y @@ -418,6 +500,12 @@ CONFIG_MUX_MMIO=y CONFIG_SIOX=m CONFIG_SIOX_BUS_GPIO=m +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_IPU_V3_PRE=y +CONFIG_MXC_MLB150=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_MXC_HDMI_CEC=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y @@ -430,12 +518,14 @@ # CONFIG_PRINT_QUOTA_WARNING is not set CONFIG_AUTOFS4_FS=y CONFIG_FUSE_FS=y +CONFIG_OVERLAY_FS=y CONFIG_ISO9660_FS=m CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=y +CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_JFFS2_FS=y CONFIG_UBIFS_FS=y @@ -452,14 +542,57 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_UTF8=y CONFIG_SECURITYFS=y -CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_TLS=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_XXHASH=m +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_DEV_FSL_CAAM=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m CONFIG_CRYPTO_DEV_SAHARA=y CONFIG_CRYPTO_DEV_MXS_DCP=y -CONFIG_CRC_CCITT=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_SHA1=m CONFIG_CRC_T10DIF=y CONFIG_CRC7=m CONFIG_LIBCRC32C=m -CONFIG_CMA_SIZE_MBYTES=64 +CONFIG_DMA_CMA=y CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y @@ -471,3 +604,12 @@ # CONFIG_SCHED_DEBUG is not set CONFIG_PROVE_LOCKING=y # CONFIG_FTRACE is not set + +# enable AF_ALG +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_AEAD=m + +# enable KTLS +CONFIG_TLS=y +CONFIG_TLS_DEVICE=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/configs/imx_v7_defconfig linux-imx-phytec/arch/arm/configs/imx_v7_defconfig --- linux-6.1.55/arch/arm/configs/imx_v7_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/configs/imx_v7_defconfig 2024-06-19 12:33:58.072188667 +0200 @@ -0,0 +1,596 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PERF_EVENTS=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SLL=y +CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX6UL=y +CONFIG_SOC_IMX7D=y +CONFIG_SOC_IMX7ULP=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_ARM_PSCI=y +CONFIG_HIGHMEM=y +CONFIG_ARCH_FORCE_MAX_ORDER=14 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_IMX_CPUFREQ_DT=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BINFMT_MISC=m +# CONFIG_COMPAT_BRK is not set +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_TLS=y +CONFIG_TLS_DEVICE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_NETFILTER=y +CONFIG_VLAN_8021Q=m +CONFIG_LLC2=y +CONFIG_CAN=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIBTUSB=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIVHCI=y +CONFIG_BT_MRVL=y +CONFIG_BT_MRVL_SDIO=y +CONFIG_BT_NXPUART=m +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6_HOST=y +CONFIG_PCI_IMX6_EP=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_MXC=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_BLK_DEV_NVME=y +CONFIG_PCI_ENDPOINT_TEST=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_NETDEVICES=y +CONFIG_TUN=y +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_CS89x0_PLATFORM=y +# CONFIG_NET_VENDOR_FARADAY is not set +CONFIG_E1000E=y +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMC91X=y +CONFIG_SMC911X=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_MICREL_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_CAN_FLEXCAN=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_MCS7830=y +CONFIG_ATH10K=m +CONFIG_ATH10K_SDIO=m +CONFIG_HOSTAP=y +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_RPMSG=y +CONFIG_KEYBOARD_IMX=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +CONFIG_TOUCHSCREEN_AD7879=y +CONFIG_TOUCHSCREEN_AD7879_I2C=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=y +CONFIG_TOUCHSCREEN_DA9052=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_ELAN_TS=y +CONFIG_TOUCHSCREEN_GOODIX=y +CONFIG_TOUCHSCREEN_ILI210X=y +CONFIG_TOUCHSCREEN_MAX11801=y +CONFIG_TOUCHSCREEN_IMX6UL_TSC=y +CONFIG_TOUCHSCREEN_EDT_FT5X06=y +CONFIG_TOUCHSCREEN_MC13783=y +CONFIG_TOUCHSCREEN_TSC2004=y +CONFIG_TOUCHSCREEN_TSC2007=y +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_TOUCHSCREEN_SX8654=y +CONFIG_TOUCHSCREEN_COLIBRI_VF50=y +CONFIG_TOUCHSCREEN_FTS=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_MMA8450=y +CONFIG_SERIO_SERPORT=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_I2C_SLAVE_EEPROM=y +CONFIG_SPI=y +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_IMX_RPMSG=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_SIOX=m +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCF857X=y +CONFIG_GPIO_STMPE=y +CONFIG_GPIO_74X164=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +CONFIG_SABRESD_MAX8903=y +CONFIG_RN5T618_POWER=m +CONFIG_SENSORS_MC13783_ADC=y +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_IIO_HWMON=y +CONFIG_SENSORS_MAX17135=y +CONFIG_THERMAL=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_DA9063_WATCHDOG=m +CONFIG_DA9062_WATCHDOG=y +CONFIG_RN5T618_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_IMX7ULP_WDT=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_DA9062=y +CONFIG_MFD_DA9063=y +CONFIG_MFD_MC13XXX_SPI=y +CONFIG_MFD_MC13XXX_I2C=y +CONFIG_MFD_MAX17135=y +CONFIG_MFD_RN5T618=y +CONFIG_MFD_SI476X_CORE=y +CONFIG_MFD_STMPE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_DA9052=y +CONFIG_REGULATOR_DA9062=y +CONFIG_REGULATOR_DA9063=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_LTC3676=y +CONFIG_REGULATOR_MAX17135=y +CONFIG_REGULATOR_MC13783=y +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_PF1550_RPMSG=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_RN5T618=y +CONFIG_RC_CORE=y +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_RADIO_SI476X=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MUX=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_VADC=m +CONFIG_MXC_MIPI_CSI=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5640_V2=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_VIDEO_CODA=m +CONFIG_VIDEO_IMX_PXP=y +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_ADV7180=m +CONFIG_DRM=y +CONFIG_DRM_PANEL_LVDS=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_TI_TFP410=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_OVERLAY=y +CONFIG_FB_MXC_MIPI_DSI_NORTHWEST=y +CONFIG_FB_MXC_ADV7535=y +CONFIG_FB_MXC_TRULY_PANEL_TFT3P5581E=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_RK_PANEL_RK055AHD042=y +CONFIG_FB_MXC_RK_PANEL_RK055IQH042=y +CONFIG_FB_MXC_MIPI_DSI_SAMSUNG=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_EINK_PANEL=y +CONFIG_FB_MXC_EINK_V2_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXS_SII902X=y +CONFIG_FB_MXC_DCIC=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_SOC_FSL_ASRC=y +CONFIG_SND_SOC_FSL_MQS=y +CONFIG_SND_SOC_FSL_RPMSG=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_EUKREA_TLV320=y +CONFIG_SND_SOC_IMX_ES8328=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_FSL_ASOC_CARD=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_SND_SOC_IMX6QDL_HDMI=y +CONFIG_SND_SOC_AC97_CODEC=y +CONFIG_SND_SOC_CS42XX8_I2C=y +CONFIG_SND_SOC_WM8960=y +CONFIG_SND_SOC_WM8962=y +CONFIG_SND_SOC_RPMSG_WM8960=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_HID_MULTITOUCH=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_PCF8523=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_DRV_M41T80=y +CONFIG_RTC_DRV_RC5T619=y +CONFIG_RTC_DRV_DA9063=y +CONFIG_RTC_DRV_MC13XXX=y +CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_MXC_V2=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_IMX_RPMSG=y +CONFIG_DMADEVICES=y +CONFIG_FSL_EDMA=y +CONFIG_IMX_SDMA=y +CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_V3=y +CONFIG_DMATEST=m +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_REMOTEPROC=y +CONFIG_IMX_REMOTEPROC=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_IIO=y +CONFIG_FXLS8962AF_I2C=y +CONFIG_MMA8452=y +CONFIG_IMX7D_ADC=y +CONFIG_RN5T618_ADC=y +CONFIG_VF610_ADC=y +CONFIG_FXAS21002C=y +CONFIG_FXOS8700_I2C=y +CONFIG_RPMSG_IIO_PEDOMETER=m +CONFIG_SENSORS_ISL29018=y +CONFIG_MAG3110=y +CONFIG_MPL3115=y +CONFIG_PWM=y +CONFIG_PWM_FSL_FTM=y +CONFIG_PWM_IMX27=y +CONFIG_PWM_IMX_TPM=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_SNVS_LPGPR=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_MUX_MMIO=y +CONFIG_SIOX=m +CONFIG_SIOX_BUS_GPIO=m +CONFIG_MXC_SIM=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_SIMv2=y +CONFIG_MXC_MLB150=y +CONFIG_MXC_IPU_V3_PRE=y +CONFIG_MXC_HDMI_CEC=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_OVERLAY_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_TLS=m +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XXHASH=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m +CONFIG_CRYPTO_DEV_FSL_CAAM=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_SAHARA=y +CONFIG_CRYPTO_DEV_MXS_DCP=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_DMA_CMA=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_PRINTK_TIME=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set + +#enable trust based hardware key +CONFIG_TRUSTED_KEYS=m +CONFIG_TRUSTED_KEYS_TPM=n +CONFIG_TRUSTED_KEYS_TEE=n +CONFIG_TRUSTED_KEYS_CAAM=n +CONFIG_TRUSTED_KEYS_DCP=y +CONFIG_CRYPTO_SM3_GENERIC=m +CONFIG_CRYPTO_SM4_GENERIC=m +CONFIG_CRYPTO_ARIA=m +CONFIG_CRYPTO_POLYVAL_ARM64_CE=m diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/configs/lsdk.config linux-imx-phytec/arch/arm/configs/lsdk.config --- linux-6.1.55/arch/arm/configs/lsdk.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/configs/lsdk.config 2024-06-19 12:33:58.072188667 +0200 @@ -0,0 +1,91 @@ +# general +CONFIG_ARM_MODULE_PLTS=y +CONFIG_CHECKPOINT_RESTORE=y + +# virtualization +CONFIG_KVM=y +CONFIG_KVM_ARM_MAX_VCPUS=8 +CONFIG_VHOST_NET=y +CONFIG_BRIDGE=y +CONFIG_TUN=y + +# containers +CONFIG_UNIX_DIAG=y +CONFIG_PACKET_DIAG=y +CONFIG_NETLINK_DIAG=y +CONFIG_OVERLAY_FS=y + +# network and misc +CONFIG_INET_ESP=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_VETH=y +CONFIG_NETFILTER=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_NAT_IPV4=y +CONFIG_NF_NAT_IPV6=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y +CONFIG_MACVLAN=y +CONFIG_MACVTAP=y +CONFIG_VLAN_8021Q=y + +# namespaces +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y + +# cgroups +CONFIG_CPUSETS=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_MEMCG=y +CONFIG_CGROUP_FREEZER=y + +# iptables +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_IP_NF_FILTER=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_IP_VS=y +CONFIG_NETFILTER_XT_MATCH_IPVS=y +CONFIG_POSIX_MQUEUE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_NAT=y +CONFIG_IP6_NF_FILTER=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y + +# filesystems +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FUSE_FS=y + +# crypto +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m + +# /proc/config.gz +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y + +# disable unneeded options and override default options set by defconfig to deduce the size of modules +# CONFIG_DRM_TEGRA is not set +# CONFIG_DRM_EXYNOS is not set +# CONFIG_DRM_MSM is not set +# CONFIG_DRM_VC4 is not set +# CONFIG_DRM_ROCKCHIP is not set +# CONFIG_DRM_RCAR_DU is not set +# CONFIG_USB_RENESAS_USBHS is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_SND_SOC_ROCKCHIP is not set diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/configs/multi_v7_defconfig linux-imx-phytec/arch/arm/configs/multi_v7_defconfig --- linux-6.1.55/arch/arm/configs/multi_v7_defconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/configs/multi_v7_defconfig 2024-06-19 12:33:58.072188667 +0200 @@ -142,6 +142,8 @@ CONFIG_CRYPTO_GHASH_ARM_CE=m CONFIG_CRYPTO_CRC32_ARM_CE=m CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_VIRTUALIZATION=y +CONFIG_VHOST_NET=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y @@ -191,6 +193,7 @@ CONFIG_PCI_RCAR_GEN2=y CONFIG_PCIE_RCAR_HOST=y CONFIG_PCI_DRA7XX_EP=y +CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y CONFIG_PCI_EPF_TEST=m @@ -207,9 +210,15 @@ CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y CONFIG_MTD_RAW_NAND=y CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_OMAP2=y @@ -218,6 +227,7 @@ CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_BRCMNAND=y CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_NAND_VF610_NFC=y CONFIG_MTD_NAND_DAVINCI=y CONFIG_MTD_NAND_STM32_FMC2=y @@ -240,6 +250,7 @@ CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y @@ -249,6 +260,8 @@ CONFIG_AHCI_IMX=y CONFIG_AHCI_SUNXI=y CONFIG_AHCI_TEGRA=y +CONFIG_AHCI_QORIQ=y +CONFIG_SATA_SIL24=y CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_RCAR=y @@ -266,7 +279,10 @@ CONFIG_MACB=y CONFIG_NET_CALXEDA_XGMAC=y CONFIG_FTGMAC100=m +CONFIG_FSL_RCPM=y +CONFIG_FSL_XGMAC_MDIO=y CONFIG_GIANFAR=y +CONFIG_FSL_SDK_DPAA_ETH=y CONFIG_HIX5HD2_GMAC=y CONFIG_E1000E=y CONFIG_IGB=y @@ -286,12 +302,15 @@ CONFIG_TI_CPTS=y CONFIG_XILINX_EMACLITE=y CONFIG_SFP=m +CONFIG_AQUANTIA_PHY=y CONFIG_BROADCOM_PHY=y CONFIG_ICPLUS_PHY=y CONFIG_MARVELL_PHY=y CONFIG_AT803X_PHY=y +CONFIG_NATIONAL_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_DP83867_PHY=y +CONFIG_VITESSE_PHY=y CONFIG_CAN_AT91=m CONFIG_CAN_FLEXCAN=m CONFIG_CAN_SUN4I=y @@ -714,7 +733,7 @@ CONFIG_DRM_SUN4I=m CONFIG_DRM_MSM=m CONFIG_DRM_FSL_DCU=m -CONFIG_DRM_TEGRA=y +# CONFIG_DRM_TEGRA=y CONFIG_DRM_STM=m CONFIG_DRM_STM_DSI=m CONFIG_DRM_PANEL_LVDS=m @@ -752,6 +771,7 @@ CONFIG_DRM_PANFROST=m CONFIG_DRM_ASPEED_GFX=m CONFIG_FB=y +CONFIG_FB_ARMCLCD=y CONFIG_FB_EFI=y CONFIG_FB_WM8505=y CONFIG_FB_SH_MOBILE_LCDC=y @@ -761,6 +781,7 @@ CONFIG_BACKLIGHT_GPIO=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y CONFIG_SOUND=m CONFIG_SND=m CONFIG_SND_HDA_TEGRA=m @@ -970,6 +991,7 @@ CONFIG_RTC_DRV_RX8581=m CONFIG_RTC_DRV_EM3027=y CONFIG_RTC_DRV_S5M=m +CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DA9063=m CONFIG_RTC_DRV_EFI=m CONFIG_RTC_DRV_DIGICOLOR=m @@ -988,6 +1010,7 @@ CONFIG_RTC_DRV_STM32=y CONFIG_RTC_DRV_CPCAP=m CONFIG_RTC_DRV_ASPEED=m +CONFIG_RTC_DRV_FSL_FTM_ALARM=y CONFIG_DMADEVICES=y CONFIG_AT_HDMAC=y CONFIG_AT_XDMAC=y @@ -1022,6 +1045,7 @@ CONFIG_NVEC_PAZ00=y CONFIG_STAGING_BOARD=y CONFIG_CHROME_PLATFORMS=y +CONFIG_FSL_SDK_DPA=y CONFIG_CROS_EC=m CONFIG_CROS_EC_I2C=m CONFIG_CROS_EC_SPI=m diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/configs/multi_v7_lpae.config linux-imx-phytec/arch/arm/configs/multi_v7_lpae.config --- linux-6.1.55/arch/arm/configs/multi_v7_lpae.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/configs/multi_v7_lpae.config 2024-06-19 12:33:58.072188667 +0200 @@ -0,0 +1,2 @@ +# Support for the Large Physical Address Extension +CONFIG_ARM_LPAE=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/configs/multi_v8.config linux-imx-phytec/arch/arm/configs/multi_v8.config --- linux-6.1.55/arch/arm/configs/multi_v8.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/configs/multi_v8.config 2024-06-19 12:33:58.072188667 +0200 @@ -0,0 +1,23 @@ +# ppfe +CONFIG_FSL_PPFE=y +CONFIG_FSL_PPFE_UTIL_DISABLED=y +# DPAA 1 +CONFIG_HAS_FSL_QBMAN=y +# network +CONFIG_BRIDGE=m +CONFIG_MACVLAN=y +CONFIG_FSL_SDK_FMAN=y +CONFIG_FMAN_ARM=y +CONFIG_FSL_SDK_DPAA_ETH=y +# mdio +CONFIG_FSL_XGMAC_MDIO=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +# phy +CONFIG_AQUANTIA_PHY=y +CONFIG_VITESSE_PHY=y +# NVMe +CONFIG_BLK_DEV_NVME=y +# vfio +CONFIG_VFIO=y +CONFIG_VFIO_PCI=y +CONFIG_VFIO_FSL_MC=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/include/asm/domain.h linux-imx-phytec/arch/arm/include/asm/domain.h --- linux-6.1.55/arch/arm/include/asm/domain.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/include/asm/domain.h 2024-06-19 12:33:58.084188872 +0200 @@ -112,6 +112,19 @@ } #endif +#ifdef CONFIG_CPU_USE_DOMAINS +#define modify_domain(dom,type) \ + do { \ + unsigned int domain = get_domain(); \ + domain &= ~domain_mask(dom); \ + domain = domain | domain_val(dom, type); \ + set_domain(domain); \ + } while (0) + +#else +static inline void modify_domain(unsigned dom, unsigned type) { } +#endif + /* * Generate the T (user) versions of the LDR/STR and related * instructions (inline assembly) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/include/asm/io.h linux-imx-phytec/arch/arm/include/asm/io.h --- linux-6.1.55/arch/arm/include/asm/io.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/include/asm/io.h 2024-06-19 12:33:58.084188872 +0200 @@ -123,6 +123,7 @@ #define MT_DEVICE_NONSHARED 1 #define MT_DEVICE_CACHED 2 #define MT_DEVICE_WC 3 +#define MT_MEMORY_RW_NS 4 /* * types 4 onwards can be found in asm/mach/map.h and are undefined * for ioremap @@ -378,6 +379,8 @@ #define ioremap_wc ioremap_wc #define ioremap_wt ioremap_wc +void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size); + void iounmap(volatile void __iomem *io_addr); #define iounmap iounmap diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/include/asm/mach/map.h linux-imx-phytec/arch/arm/include/asm/mach/map.h --- linux-6.1.55/arch/arm/include/asm/mach/map.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/include/asm/mach/map.h 2024-06-19 12:33:58.088188940 +0200 @@ -18,9 +18,9 @@ unsigned int type; }; -/* types 0-3 are defined in asm/io.h */ +/* types 0-4 are defined in asm/io.h */ enum { - MT_UNCACHED = 4, + MT_UNCACHED = 5, MT_CACHECLEAN, MT_MINICLEAN, MT_LOW_VECTORS, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/include/asm/pgtable.h linux-imx-phytec/arch/arm/include/asm/pgtable.h --- linux-6.1.55/arch/arm/include/asm/pgtable.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/include/asm/pgtable.h 2024-06-19 12:33:58.088188940 +0200 @@ -115,6 +115,13 @@ #define pgprot_noncached(prot) \ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED) +#define pgprot_cached(prot) \ + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED) + +#define pgprot_cached_ns(prot) \ + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \ + L_PTE_MT_DEV_NONSHARED) + #define pgprot_writecombine(prot) \ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/include/asm/ptrace.h linux-imx-phytec/arch/arm/include/asm/ptrace.h --- linux-6.1.55/arch/arm/include/asm/ptrace.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/include/asm/ptrace.h 2024-06-19 12:33:58.088188940 +0200 @@ -19,6 +19,7 @@ struct svc_pt_regs { struct pt_regs regs; u32 dacr; + u32 addr_limit; }; #define to_svc_pt_regs(r) container_of(r, struct svc_pt_regs, regs) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/include/asm/thread_info.h linux-imx-phytec/arch/arm/include/asm/thread_info.h --- linux-6.1.55/arch/arm/include/asm/thread_info.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/include/asm/thread_info.h 2024-06-19 12:33:58.092189009 +0200 @@ -41,6 +41,8 @@ #include +typedef unsigned long mm_segment_t; + struct cpu_context_save { __u32 r4; __u32 r5; @@ -62,6 +64,7 @@ struct thread_info { unsigned long flags; /* low level flags */ int preempt_count; /* 0 => preemptable, <0 => bug */ + mm_segment_t addr_limit; /* address limit */ __u32 cpu; /* cpu */ __u32 cpu_domain; /* cpu domain */ struct cpu_context_save cpu_context; /* cpu context */ @@ -79,6 +82,7 @@ { \ .flags = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ + .addr_limit = KERNEL_DS, \ } static inline struct task_struct *thread_task(struct thread_info* ti) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/include/asm/uaccess-asm.h linux-imx-phytec/arch/arm/include/asm/uaccess-asm.h --- linux-6.1.55/arch/arm/include/asm/uaccess-asm.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/include/asm/uaccess-asm.h 2024-06-19 12:33:58.092189009 +0200 @@ -84,8 +84,12 @@ * if \disable is set. */ .macro uaccess_entry, tsk, tmp0, tmp1, tmp2, disable + ldr \tmp1, [\tsk, #TI_ADDR_LIMIT] + ldr \tmp2, =TASK_SIZE + str \tmp2, [\tsk, #TI_ADDR_LIMIT] DACR( mrc p15, 0, \tmp0, c3, c0, 0) DACR( str \tmp0, [sp, #SVC_DACR]) + str \tmp1, [sp, #SVC_ADDR_LIMIT] .if \disable && IS_ENABLED(CONFIG_CPU_SW_DOMAIN_PAN) /* kernel=client, user=no access */ mov \tmp2, #DACR_UACCESS_DISABLE @@ -102,7 +106,9 @@ /* Restore the user access state previously saved by uaccess_entry */ .macro uaccess_exit, tsk, tmp0, tmp1 + ldr \tmp1, [sp, #SVC_ADDR_LIMIT] DACR( ldr \tmp0, [sp, #SVC_DACR]) + str \tmp1, [\tsk, #TI_ADDR_LIMIT] DACR( mcr p15, 0, \tmp0, c3, c0, 0) .endm diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/include/asm/uaccess.h linux-imx-phytec/arch/arm/include/asm/uaccess.h --- linux-6.1.55/arch/arm/include/asm/uaccess.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/include/asm/uaccess.h 2024-06-19 12:33:58.092189009 +0200 @@ -53,8 +53,32 @@ extern int __get_user_bad(void); extern int __put_user_bad(void); +/* + * Note that this is actually 0x1,0000,0000 + */ +#define KERNEL_DS 0x00000000 + #ifdef CONFIG_MMU +#define USER_DS TASK_SIZE +#define get_fs() (current_thread_info()->addr_limit) + +static inline void set_fs(mm_segment_t fs) +{ + current_thread_info()->addr_limit = fs; + + /* + * Prevent a mispredicted conditional call to set_fs from forwarding + * the wrong address limit to access_ok under speculation. + */ + dsb(nsh); + isb(); + + modify_domain(DOMAIN_KERNEL, fs ? DOMAIN_CLIENT : DOMAIN_MANAGER); +} + +#define uaccess_kernel() (get_fs() == KERNEL_DS) + /* * This is a type: either unsigned long, if the argument fits into * that type, or otherwise unsigned long long. @@ -82,7 +106,7 @@ " subshs %1, %1, %2\n" " movlo %0, #0\n" : "+r" (safe_ptr), "=&r" (tmp) - : "r" (size), "r" (TASK_SIZE) + : "r" (size), "r" (current_thread_info()->addr_limit) : "cc"); csdb(); @@ -156,7 +180,7 @@ #define __get_user_check(x, p) \ ({ \ - unsigned long __limit = TASK_SIZE - 1; \ + unsigned long __limit = current_thread_info()->addr_limit - 1; \ register typeof(*(p)) __user *__p asm("r0") = (p); \ register __inttype(x) __r2 asm("r2"); \ register unsigned long __l asm("r1") = __limit; \ @@ -209,7 +233,7 @@ #define __put_user_check(__pu_val, __ptr, __err, __s) \ ({ \ - unsigned long __limit = TASK_SIZE - 1; \ + unsigned long __limit = current_thread_info()->addr_limit - 1; \ register typeof(__pu_val) __r2 asm("r2") = __pu_val; \ register const void __user *__p asm("r0") = __ptr; \ register unsigned long __l asm("r1") = __limit; \ @@ -226,6 +250,18 @@ #else /* CONFIG_MMU */ +/* + * uClinux has only one addr space, so has simplified address limits. + */ +#define USER_DS KERNEL_DS + +#define uaccess_kernel() (true) +#define get_fs() (KERNEL_DS) + +static inline void set_fs(mm_segment_t fs) +{ +} + #define get_user(x, p) __get_user(x, p) #define __put_user_check __put_user_nocheck @@ -233,6 +269,9 @@ #include +#define user_addr_max() \ + (uaccess_kernel() ? ~0UL : get_fs()) + #ifdef CONFIG_CPU_SPECTRE /* * When mitigating Spectre variant 1, it is not worth fixing the non- diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/Kconfig linux-imx-phytec/arch/arm/Kconfig --- linux-6.1.55/arch/arm/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/Kconfig 2024-06-19 12:33:57.824184426 +0200 @@ -134,6 +134,7 @@ select PERF_USE_VMALLOC select RTC_LIB select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) + select SET_FS select SYS_SUPPORTS_APM_EMULATION select THREAD_INFO_IN_TASK select TIMER_OF if OF diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/kernel/armksyms.c linux-imx-phytec/arch/arm/kernel/armksyms.c --- linux-6.1.55/arch/arm/kernel/armksyms.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/kernel/armksyms.c 2024-06-19 12:33:58.096189077 +0200 @@ -16,6 +16,7 @@ #include #include +#include /* * libgcc functions - functions that are used internally by the @@ -175,3 +176,7 @@ EXPORT_SYMBOL(__arm_smccc_smc); EXPORT_SYMBOL(__arm_smccc_hvc); #endif + +#ifdef CONFIG_ARM_VIRT_EXT +EXPORT_SYMBOL_GPL(__boot_cpu_mode); +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/kernel/asm-offsets.c linux-imx-phytec/arch/arm/kernel/asm-offsets.c --- linux-6.1.55/arch/arm/kernel/asm-offsets.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/kernel/asm-offsets.c 2024-06-19 12:33:58.096189077 +0200 @@ -43,6 +43,7 @@ BLANK(); DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); + DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit)); DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); DEFINE(TI_CPU_DOMAIN, offsetof(struct thread_info, cpu_domain)); DEFINE(TI_CPU_SAVE, offsetof(struct thread_info, cpu_context)); @@ -83,6 +84,7 @@ DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0)); DEFINE(PT_REGS_SIZE, sizeof(struct pt_regs)); DEFINE(SVC_DACR, offsetof(struct svc_pt_regs, dacr)); + DEFINE(SVC_ADDR_LIMIT, offsetof(struct svc_pt_regs, addr_limit)); DEFINE(SVC_REGS_SIZE, sizeof(struct svc_pt_regs)); BLANK(); DEFINE(SIGFRAME_RC3_OFFSET, offsetof(struct sigframe, retcode[3])); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/kernel/bios32.c linux-imx-phytec/arch/arm/kernel/bios32.c --- linux-6.1.55/arch/arm/kernel/bios32.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/kernel/bios32.c 2024-06-19 12:33:58.096189077 +0200 @@ -12,11 +12,14 @@ #include #include #include +#include #include #include #include +#include "../../../drivers/pci/pcie/portdrv.h" + static int debug_pci; /* @@ -65,6 +68,47 @@ } /* + * Check device tree if the service interrupts are there + */ +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask) +{ + int ret, count = 0; + struct device_node *np = NULL; + + if (dev->bus->dev.of_node) + np = dev->bus->dev.of_node; + + if (np == NULL) + return 0; + + if (!IS_ENABLED(CONFIG_OF_IRQ)) + return 0; + + /* If root port doesn't support MSI/MSI-X/INTx in RC mode, + * request irq for aer + */ + if (mask & PCIE_PORT_SERVICE_AER) { + ret = of_irq_get_byname(np, "aer"); + if (ret > 0) { + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret; + count++; + } + } + + if (mask & PCIE_PORT_SERVICE_PME) { + ret = of_irq_get_byname(np, "pme"); + if (ret > 0) { + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret; + count++; + } + } + + /* TODO: add more service interrupts if there it is in the device tree*/ + + return count; +} + +/* * We don't use this to fix the device, but initialisation of it. * It's not the correct use for this, but it works. * Note that the arbiter/ISA bridge appears to be buggy, specifically in diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/kernel/entry-common.S linux-imx-phytec/arch/arm/kernel/entry-common.S --- linux-6.1.55/arch/arm/kernel/entry-common.S 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/kernel/entry-common.S 2024-06-19 12:33:58.096189077 +0200 @@ -51,6 +51,10 @@ UNWIND(.fnstart ) UNWIND(.cantunwind ) disable_irq_notrace @ disable interrupts + ldr r2, [tsk, #TI_ADDR_LIMIT] + ldr r1, =TASK_SIZE + cmp r2, r1 + blne addr_limit_check_failed ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing movs r1, r1, lsl #16 bne fast_work_pending @@ -85,6 +89,10 @@ bl do_rseq_syscall #endif disable_irq_notrace @ disable interrupts + ldr r2, [tsk, #TI_ADDR_LIMIT] + ldr r1, =TASK_SIZE + cmp r2, r1 + blne addr_limit_check_failed ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing movs r1, r1, lsl #16 beq no_work_pending @@ -124,6 +132,10 @@ #endif disable_irq_notrace @ disable interrupts ENTRY(ret_to_user_from_irq) + ldr r2, [tsk, #TI_ADDR_LIMIT] + ldr r1, =TASK_SIZE + cmp r2, r1 + blne addr_limit_check_failed ldr r1, [tsk, #TI_FLAGS] movs r1, r1, lsl #16 bne slow_work_pending diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/kernel/hyp-stub.S linux-imx-phytec/arch/arm/kernel/hyp-stub.S --- linux-6.1.55/arch/arm/kernel/hyp-stub.S 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/kernel/hyp-stub.S 2024-06-19 12:33:58.100189145 +0200 @@ -236,4 +236,3 @@ __hyp_stub_irq: W(b) . __hyp_stub_fiq: W(b) . ENDPROC(__hyp_stub_vectors) - diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/kernel/process.c linux-imx-phytec/arch/arm/kernel/process.c --- linux-6.1.55/arch/arm/kernel/process.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/kernel/process.c 2024-06-19 12:33:58.100189145 +0200 @@ -115,7 +115,7 @@ unsigned long flags; char buf[64]; #ifndef CONFIG_CPU_V7M - unsigned int domain; + unsigned int domain, fs; #ifdef CONFIG_CPU_SW_DOMAIN_PAN /* * Get the domain register for the parent context. In user @@ -124,11 +124,14 @@ */ if (user_mode(regs)) { domain = DACR_UACCESS_ENABLE; + fs = get_fs(); } else { domain = to_svc_pt_regs(regs)->dacr; + fs = to_svc_pt_regs(regs)->addr_limit; } #else domain = get_domain(); + fs = get_fs(); #endif #endif @@ -164,6 +167,8 @@ if ((domain & domain_mask(DOMAIN_USER)) == domain_val(DOMAIN_USER, DOMAIN_NOACCESS)) segment = "none"; + else if (fs == KERNEL_DS) + segment = "kernel"; else segment = "user"; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/kernel/signal.c linux-imx-phytec/arch/arm/kernel/signal.c --- linux-6.1.55/arch/arm/kernel/signal.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/kernel/signal.c 2024-06-19 12:33:58.104189214 +0200 @@ -668,6 +668,14 @@ return page; } +/* Defer to generic check */ +asmlinkage void addr_limit_check_failed(void) +{ +#ifdef CONFIG_MMU + addr_limit_user_check(); +#endif +} + #ifdef CONFIG_DEBUG_RSEQ asmlinkage void do_rseq_syscall(struct pt_regs *regs) { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/lib/copy_from_user.S linux-imx-phytec/arch/arm/lib/copy_from_user.S --- linux-6.1.55/arch/arm/lib/copy_from_user.S 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/lib/copy_from_user.S 2024-06-19 12:33:58.108189283 +0200 @@ -106,7 +106,8 @@ ENTRY(arm_copy_from_user) #ifdef CONFIG_CPU_SPECTRE - ldr r3, =TASK_SIZE + get_thread_info r3 + ldr r3, [r3, #TI_ADDR_LIMIT] uaccess_mask_range_ptr r1, r2, r3, ip #endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/lib/copy_to_user.S linux-imx-phytec/arch/arm/lib/copy_to_user.S --- linux-6.1.55/arch/arm/lib/copy_to_user.S 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/lib/copy_to_user.S 2024-06-19 12:33:58.108189283 +0200 @@ -106,7 +106,8 @@ ENTRY(__copy_to_user_std) WEAK(arm_copy_to_user) #ifdef CONFIG_CPU_SPECTRE - ldr r3, =TASK_SIZE + get_thread_info r3 + ldr r3, [r3, #TI_ADDR_LIMIT] uaccess_mask_range_ptr r0, r2, r3, ip #endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/anatop.c linux-imx-phytec/arch/arm/mach-imx/anatop.c --- linux-6.1.55/arch/arm/mach-imx/anatop.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/anatop.c 2024-06-19 12:33:58.124189556 +0200 @@ -4,6 +4,7 @@ * Copyright 2017-2018 NXP. */ +#include #include #include #include @@ -16,34 +17,59 @@ #define REG_SET 0x4 #define REG_CLR 0x8 +#define ANADIG_ARM_PLL 0x60 +#define ANADIG_DDR_PLL 0x70 +#define ANADIG_SYS_PLL 0xb0 +#define ANADIG_ENET_PLL 0xe0 +#define ANADIG_AUDIO_PLL 0xf0 +#define ANADIG_VIDEO_PLL 0x130 + #define ANADIG_REG_2P5 0x130 #define ANADIG_REG_CORE 0x140 #define ANADIG_ANA_MISC0 0x150 +#define ANADIG_ANA_MISC2 0x170 #define ANADIG_DIGPROG 0x260 #define ANADIG_DIGPROG_IMX6SL 0x280 #define ANADIG_DIGPROG_IMX7D 0x800 -#define SRC_SBMR2 0x1c - #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8 #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 +#define BM_ANADIG_REG_CORE_REG1 (0x1f << 9) +#define BM_ANADIG_REG_CORE_REG2 (0x1f << 18) +#define BP_ANADIG_REG_CORE_REG2 (18) #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000 +#define BM_ANADIG_ANA_MISC0_V2_STOP_MODE_CONFIG 0x800 +#define BM_ANADIG_ANA_MISC0_V3_STOP_MODE_CONFIG 0xc00 +#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME (0x3 << 26) +#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME (26) /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */ #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000 +/* Since i.MX6SX, DISCON_HIGH_SNVS is changed to bit 12 */ +#define BM_ANADIG_ANA_MISC0_V2_DISCON_HIGH_SNVS 0x1000 + +#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */ +#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */ static struct regmap *anatop; static void imx_anatop_enable_weak2p5(bool enable) { - u32 reg, val; + u32 reg, val, mask; regmap_read(anatop, ANADIG_ANA_MISC0, &val); + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + mask = BM_ANADIG_ANA_MISC0_V3_STOP_MODE_CONFIG; + else if (cpu_is_imx6sl()) + mask = BM_ANADIG_ANA_MISC0_V2_STOP_MODE_CONFIG; + else + mask = BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG; + /* can only be enabled when stop_mode_config is clear. */ reg = ANADIG_REG_2P5; - reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? - REG_SET : REG_CLR; + reg += (enable && (val & mask) == 0) ? REG_SET : REG_CLR; regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG); } @@ -61,33 +87,88 @@ static inline void imx_anatop_disconnect_high_snvs(bool enable) { - regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), - BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS); + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + regmap_write(anatop, ANADIG_ANA_MISC0 + + (enable ? REG_SET : REG_CLR), + BM_ANADIG_ANA_MISC0_V2_DISCON_HIGH_SNVS); + else + regmap_write(anatop, ANADIG_ANA_MISC0 + + (enable ? REG_SET : REG_CLR), + BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS); +} + +static void imx_anatop_disable_pu(bool off) +{ + u32 val, soc, delay; + if (off) { + regmap_read(anatop, ANADIG_REG_CORE, &val); + val &= ~BM_ANADIG_REG_CORE_REG1; + regmap_write(anatop, ANADIG_REG_CORE, val); + } else { + /* track vddpu with vddsoc */ + regmap_read(anatop, ANADIG_REG_CORE, &val); + soc = val & BM_ANADIG_REG_CORE_REG2; + val &= ~BM_ANADIG_REG_CORE_REG1; + val |= soc >> 9; + regmap_write(anatop, ANADIG_REG_CORE, val); + /* wait PU LDO ramp */ + regmap_read(anatop, ANADIG_ANA_MISC2, &val); + val &= BM_ANADIG_ANA_MISC2_REG1_STEP_TIME; + val >>= BP_ANADIG_ANA_MISC2_REG1_STEP_TIME; + delay = (soc >> BP_ANADIG_REG_CORE_REG2) * + (LDO_RAMP_UP_UNIT_IN_CYCLES << val) / + LDO_RAMP_UP_FREQ_IN_MHZ + 1; + udelay(delay); + } } void imx_anatop_pre_suspend(void) { - if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) - imx_anatop_enable_2p5_pulldown(true); - else - imx_anatop_enable_weak2p5(true); + if (cpu_is_imx7d()) { + /* PLL and PFDs overwrite set */ + regmap_write(anatop, ANADIG_ARM_PLL + REG_SET, 1 << 20); + regmap_write(anatop, ANADIG_DDR_PLL + REG_SET, 1 << 19); + regmap_write(anatop, ANADIG_SYS_PLL + REG_SET, 0x1ff << 17); + regmap_write(anatop, ANADIG_ENET_PLL + REG_SET, 1 << 13); + regmap_write(anatop, ANADIG_AUDIO_PLL + REG_SET, 1 << 24); + regmap_write(anatop, ANADIG_VIDEO_PLL + REG_SET, 1 << 24); + return; + } + + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + imx_anatop_disable_pu(true); + imx_anatop_enable_weak2p5(true); imx_anatop_enable_fet_odrive(true); - if (cpu_is_imx6sl()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) imx_anatop_disconnect_high_snvs(true); } void imx_anatop_post_resume(void) { - if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) - imx_anatop_enable_2p5_pulldown(false); - else - imx_anatop_enable_weak2p5(false); + if (cpu_is_imx7d()) { + /* PLL and PFDs overwrite clear */ + regmap_write(anatop, ANADIG_ARM_PLL + REG_CLR, 1 << 20); + regmap_write(anatop, ANADIG_DDR_PLL + REG_CLR, 1 << 19); + regmap_write(anatop, ANADIG_SYS_PLL + REG_CLR, 0x1ff << 17); + regmap_write(anatop, ANADIG_ENET_PLL + REG_CLR, 1 << 13); + regmap_write(anatop, ANADIG_AUDIO_PLL + REG_CLR, 1 << 24); + regmap_write(anatop, ANADIG_VIDEO_PLL + REG_CLR, 1 << 24); + return; + } + + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + imx_anatop_disable_pu(false); + + imx_anatop_enable_weak2p5(false); imx_anatop_enable_fet_odrive(false); - if (cpu_is_imx6sl()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) imx_anatop_disconnect_high_snvs(false); } @@ -95,10 +176,11 @@ { struct device_node *np, *src_np; void __iomem *anatop_base; + void __iomem *src_base; unsigned int revision; - u32 digprog; + u32 digprog, sbmr2 = 0; u16 offset = ANADIG_DIGPROG; - u8 major_part, minor_part; + u16 major_part, minor_part; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = of_iomap(np, 0); @@ -110,6 +192,21 @@ digprog = readl_relaxed(anatop_base + offset); iounmap(anatop_base); + if ((digprog >> 16) == MXC_CPU_IMX6ULL) { + src_np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-src"); + if (src_np) { + src_base = of_iomap(src_np, 0); + WARN_ON(!src_base); + of_node_put(src_np); + sbmr2 = readl_relaxed(src_base + 0x1c); + iounmap(src_base); + } + if (sbmr2 & (1 << 6)) { + digprog &= ~(0xff << 16); + digprog |= (MXC_CPU_IMX6ULZ << 16); + } + } + /* * On i.MX7D digprog value match linux version format, so * it needn't map again and we can use register value directly. @@ -129,25 +226,6 @@ major_part = (digprog >> 8) & 0xf; minor_part = digprog & 0xf; revision = ((major_part + 1) << 4) | minor_part; - - if ((digprog >> 16) == MXC_CPU_IMX6ULL) { - void __iomem *src_base; - u32 sbmr2; - - src_np = of_find_compatible_node(NULL, NULL, - "fsl,imx6ul-src"); - src_base = of_iomap(src_np, 0); - of_node_put(src_np); - WARN_ON(!src_base); - sbmr2 = readl_relaxed(src_base + SRC_SBMR2); - iounmap(src_base); - - /* src_sbmr2 bit 6 is to identify if it is i.MX6ULZ */ - if (sbmr2 & (1 << 6)) { - digprog &= ~(0xff << 16); - digprog |= (MXC_CPU_IMX6ULZ << 16); - } - } } of_node_put(np); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/busfreq_ddr3.c linux-imx-phytec/arch/arm/mach-imx/busfreq_ddr3.c --- linux-6.1.55/arch/arm/mach-imx/busfreq_ddr3.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/busfreq_ddr3.c 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,772 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file busfreq_ddr3.c + * + * @brief iMX6 DDR3 frequency change specific file. + * + * @ingroup PM + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hardware.h" +#include "common.h" + +#define SMP_WFE_CODE_SIZE 0x400 + +#define MIN_DLL_ON_FREQ 333000000 +#define MAX_DLL_OFF_FREQ 125000000 +#define MMDC0_MPMUR0 0x8b8 +#define MMDC0_MPMUR0_OFFSET 16 +#define MMDC0_MPMUR0_MASK 0x3ff + +/* + * This structure is for passing necessary data for low level ocram + * busfreq code(arch/arm/mach-imx/ddr3_freq_imx6.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/ddr3_freq_imx6.S must be also changed accordingly, + * otherwise, the busfreq change function will be broken! + * + * This structure will be placed in front of the asm code on ocram. + */ +struct imx6_busfreq_info { + u32 freq; + void *ddr_settings; + u32 dll_off; + void *iomux_offsets; + u32 mu_delay_val; +} __aligned(8); + +static struct imx6_busfreq_info *imx6_busfreq_info; + +/* DDR settings */ +static unsigned long (*iram_ddr_settings)[2]; +static unsigned long (*normal_mmdc_settings)[2]; +static unsigned long (*iram_iomux_settings)[2]; + +static void __iomem *mmdc_base; +static void __iomem *iomux_base; +static void __iomem *gic_dist_base; + +static int ddr_settings_size; +static int iomux_settings_size; +static int curr_ddr_rate; + +void (*imx6_up_change_ddr_freq)(struct imx6_busfreq_info *busfreq_info); +extern void imx6_up_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info); +void (*imx7d_change_ddr_freq)(u32 freq) = NULL; +extern void imx7d_ddr3_freq_change(u32 freq); +extern void imx_lpddr3_freq_change(u32 freq); + +void (*mx6_change_ddr_freq)(u32 freq, void *ddr_settings, + bool dll_mode, void *iomux_offsets) = NULL; + +extern unsigned int ddr_normal_rate; +extern int low_bus_freq_mode; +extern int audio_bus_freq_mode; +extern void mx6_ddr3_freq_change(u32 freq, void *ddr_settings, + bool dll_mode, void *iomux_offsets); + +extern unsigned long save_ttbr1(void); +extern void restore_ttbr1(unsigned long ttbr1); +extern unsigned long ddr_freq_change_iram_base; + +extern unsigned long ddr_freq_change_total_size; +extern unsigned long iram_tlb_phys_addr; + +extern unsigned long mx6_ddr3_freq_change_start asm("mx6_ddr3_freq_change_start"); +extern unsigned long mx6_ddr3_freq_change_end asm("mx6_ddr3_freq_change_end"); +extern unsigned long imx6_up_ddr3_freq_change_start asm("imx6_up_ddr3_freq_change_start"); +extern unsigned long imx6_up_ddr3_freq_change_end asm("imx6_up_ddr3_freq_change_end"); + +#ifdef CONFIG_SMP +static unsigned long wfe_freq_change_iram_base; +volatile u32 *wait_for_ddr_freq_update; +static unsigned int online_cpus; +static u32 *irqs_used; + +void (*wfe_change_ddr_freq)(u32 cpuid, u32 *ddr_freq_change_done); +void (*imx7_wfe_change_ddr_freq)(u32 cpuid, u32 ocram_base); +extern void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done); +extern void imx7_smp_wfe(u32 cpuid, u32 ocram_base); +extern unsigned long wfe_smp_freq_change_start asm("wfe_smp_freq_change_start"); +extern unsigned long wfe_smp_freq_change_end asm("wfe_smp_freq_change_end"); +extern void __iomem *scu_base; +#endif + +unsigned long ddr3_dll_mx6sx[][2] = { + {0x0c, 0x0}, + {0x10, 0x0}, + {0x1C, 0x04008032}, + {0x1C, 0x00048031}, + {0x1C, 0x05208030}, + {0x1C, 0x04008040}, + {0x818, 0x0}, + {0x18, 0x0}, +}; + +unsigned long ddr3_calibration_mx6sx[][2] = { + {0x83c, 0x0}, + {0x840, 0x0}, + {0x848, 0x0}, + {0x850, 0x0}, +}; + +unsigned long iomux_offsets_mx6sx[][2] = { + {0x330, 0x0}, + {0x334, 0x0}, + {0x338, 0x0}, + {0x33c, 0x0}, +}; + +unsigned long iomux_offsets_mx6ul[][2] = { + {0x280, 0x0}, + {0x284, 0x0}, +}; + +unsigned long ddr3_dll_mx6q[][2] = { + {0x0c, 0x0}, + {0x10, 0x0}, + {0x1C, 0x04088032}, + {0x1C, 0x0408803a}, + {0x1C, 0x08408030}, + {0x1C, 0x08408038}, + {0x818, 0x0}, + {0x18, 0x0}, +}; + +unsigned long ddr3_calibration[][2] = { + {0x83c, 0x0}, + {0x840, 0x0}, + {0x483c, 0x0}, + {0x4840, 0x0}, + {0x848, 0x0}, + {0x4848, 0x0}, + {0x850, 0x0}, + {0x4850, 0x0}, +}; + +unsigned long iomux_offsets_mx6q[][2] = { + {0x5A8, 0x0}, + {0x5B0, 0x0}, + {0x524, 0x0}, + {0x51C, 0x0}, + {0x518, 0x0}, + {0x50C, 0x0}, + {0x5B8, 0x0}, + {0x5C0, 0x0}, +}; + +unsigned long ddr3_dll_mx6dl[][2] = { + {0x0c, 0x0}, + {0x10, 0x0}, + {0x1C, 0x04008032}, + {0x1C, 0x0400803a}, + {0x1C, 0x07208030}, + {0x1C, 0x07208038}, + {0x818, 0x0}, + {0x18, 0x0}, +}; + +unsigned long iomux_offsets_mx6dl[][2] = { + {0x4BC, 0x0}, + {0x4C0, 0x0}, + {0x4C4, 0x0}, + {0x4C8, 0x0}, + {0x4CC, 0x0}, + {0x4D0, 0x0}, + {0x4D4, 0x0}, + {0x4D8, 0x0}, +}; + +int can_change_ddr_freq(void) +{ + return 1; +} + +#ifdef CONFIG_SMP +/* + * each active core apart from the one changing + * the DDR frequency will execute this function. + * the rest of the cores have to remain in WFE + * state until the frequency is changed. + */ +static irqreturn_t wait_in_wfe_irq(int irq, void *dev_id) +{ + u32 me; + + me = smp_processor_id(); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, + &me); +#endif + if (cpu_is_imx7d()) + imx7_wfe_change_ddr_freq(0x8 * me, + (u32)ddr_freq_change_iram_base); + else + wfe_change_ddr_freq(0xff << (me * 8), + (u32 *)&iram_iomux_settings[0][1]); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, + &me); +#endif + + return IRQ_HANDLED; +} +#endif + +/* change the DDR frequency. */ +int update_ddr_freq_imx_smp(int ddr_rate) +{ + int me = 0; + unsigned long ttbr1; + bool dll_off = false; + int i; +#ifdef CONFIG_SMP + unsigned int reg = 0; + int cpu = 0; +#endif + int mode = get_bus_freq_mode(); + + if (!can_change_ddr_freq()) + return -1; + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate); + + if (cpu_is_imx6()) { + if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO)) + dll_off = true; + + iram_ddr_settings[0][0] = ddr_settings_size; + iram_iomux_settings[0][0] = iomux_settings_size; + if (ddr_rate == ddr_normal_rate) { + for (i = 0; i < iram_ddr_settings[0][0]; i++) { + iram_ddr_settings[i + 1][0] = + normal_mmdc_settings[i][0]; + iram_ddr_settings[i + 1][1] = + normal_mmdc_settings[i][1]; + } + } + } + + /* ensure that all Cores are in WFE. */ + local_irq_disable(); + +#ifdef CONFIG_SMP + me = smp_processor_id(); + + /* Make sure all the online cores are active */ + while (1) { + bool not_exited_busfreq = false; + u32 reg = 0; + + for_each_online_cpu(cpu) { + if (cpu_is_imx7d()) + reg = *(wait_for_ddr_freq_update + 1); + else if (cpu_is_imx6()) + reg = __raw_readl(scu_base + 0x08); + + if (reg & (0x02 << (cpu * 8))) + not_exited_busfreq = true; + } + if (!not_exited_busfreq) + break; + } + + wmb(); + *wait_for_ddr_freq_update = 1; + dsb(); + if (cpu_is_imx7d()) + online_cpus = *(wait_for_ddr_freq_update + 1); + else if (cpu_is_imx6()) + online_cpus = readl_relaxed(scu_base + 0x08); + for_each_online_cpu(cpu) { + *((char *)(&online_cpus) + (u8)cpu) = 0x02; + if (cpu != me) { + /* set the interrupt to be pending in the GIC. */ + reg = 1 << (irqs_used[cpu] % 32); + writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET + + (irqs_used[cpu] / 32) * 4); + } + } + /* Wait for the other active CPUs to idle */ + while (1) { + u32 reg = 0; + + if (cpu_is_imx7d()) + reg = *(wait_for_ddr_freq_update + 1); + else if (cpu_is_imx6()) + reg = readl_relaxed(scu_base + 0x08); + reg |= (0x02 << (me * 8)); + if (reg == online_cpus) + break; + } +#endif + + /* Ensure iram_tlb_phys_addr is flushed to DDR. */ + __cpuc_flush_dcache_area(&iram_tlb_phys_addr, + sizeof(iram_tlb_phys_addr)); + if (cpu_is_imx6()) + outer_clean_range(__pa(&iram_tlb_phys_addr), + __pa(&iram_tlb_phys_addr + 1)); + + ttbr1 = save_ttbr1(); + /* Now we can change the DDR frequency. */ + if (cpu_is_imx7d()) + imx7d_change_ddr_freq(ddr_rate); + else if (cpu_is_imx6()) + mx6_change_ddr_freq(ddr_rate, iram_ddr_settings, + dll_off, iram_iomux_settings); + restore_ttbr1(ttbr1); + curr_ddr_rate = ddr_rate; + +#ifdef CONFIG_SMP + wmb(); + /* DDR frequency change is done . */ + *wait_for_ddr_freq_update = 0; + dsb(); + + /* wake up all the cores. */ + sev(); +#endif + + local_irq_enable(); + + printk(KERN_DEBUG "Bus freq set to %d done! cpu=%d\n", ddr_rate, me); + + return 0; +} + +/* Used by i.MX6SX/i.MX6UL for updating the ddr frequency */ +int update_ddr_freq_imx6_up(int ddr_rate) +{ + int i; + bool dll_off = false; + unsigned long ttbr1; + int mode = get_bus_freq_mode(); + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate); + + if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO)) + dll_off = true; + + imx6_busfreq_info->dll_off = dll_off; + iram_ddr_settings[0][0] = ddr_settings_size; + iram_iomux_settings[0][0] = iomux_settings_size; + for (i = 0; i < iram_ddr_settings[0][0]; i++) { + iram_ddr_settings[i + 1][0] = + normal_mmdc_settings[i][0]; + iram_ddr_settings[i + 1][1] = + normal_mmdc_settings[i][1]; + } + + local_irq_disable(); + + ttbr1 = save_ttbr1(); + imx6_busfreq_info->freq = ddr_rate; + imx6_busfreq_info->ddr_settings = iram_ddr_settings; + imx6_busfreq_info->iomux_offsets = iram_iomux_settings; + imx6_busfreq_info->mu_delay_val = ((readl_relaxed(mmdc_base + MMDC0_MPMUR0) + >> MMDC0_MPMUR0_OFFSET) & MMDC0_MPMUR0_MASK); + + imx6_up_change_ddr_freq(imx6_busfreq_info); + restore_ttbr1(ttbr1); + curr_ddr_rate = ddr_rate; + + local_irq_enable(); + + printk(KERN_DEBUG "Bus freq set to %d done!\n", ddr_rate); + + return 0; +} + +int init_ddrc_ddr_settings(struct platform_device *busfreq_pdev) +{ + int ddr_type = imx_ddrc_get_ddr_type(); +#ifdef CONFIG_SMP + struct device_node *node; + u32 cpu; + struct device *dev = &busfreq_pdev->dev; + int err; + struct irq_data *d; + + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a7-gic"); + if (!node) { + printk(KERN_ERR "failed to find imx7d-a7-gic device tree data!\n"); + return -EINVAL; + } + gic_dist_base = of_iomap(node, 0); + WARN(!gic_dist_base, "unable to map gic dist registers\n"); + + irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(), + GFP_KERNEL); + for_each_online_cpu(cpu) { + int irq; + /* + * set up a reserved interrupt to get all + * the active cores into a WFE state + * before changing the DDR frequency. + */ + irq = platform_get_irq(busfreq_pdev, cpu); + err = request_irq(irq, wait_in_wfe_irq, + IRQF_PERCPU, "ddrc", NULL); + if (err) { + dev_err(dev, + "Busfreq:request_irq failed %d, err = %d\n", + irq, err); + return err; + } + err = irq_set_affinity(irq, cpumask_of(cpu)); + if (err) { + dev_err(dev, + "Busfreq: Cannot set irq affinity irq=%d\n", + irq); + return err; + } + d = irq_get_irq_data(irq); + irqs_used[cpu] = d->hwirq + 32; + } + + /* Store the variable used to communicate between cores */ + wait_for_ddr_freq_update = (u32 *)ddr_freq_change_iram_base; + imx7_wfe_change_ddr_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base + 0x8, + &imx7_smp_wfe, SMP_WFE_CODE_SIZE - 0x8); +#endif + if (ddr_type == IMX_DDR_TYPE_DDR3) + imx7d_change_ddr_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base + SMP_WFE_CODE_SIZE, + &imx7d_ddr3_freq_change, + MX7_BUSFREQ_OCRAM_SIZE - SMP_WFE_CODE_SIZE); + else if (ddr_type == IMX_DDR_TYPE_LPDDR3 + || ddr_type == IMX_DDR_TYPE_LPDDR2) + imx7d_change_ddr_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base + + SMP_WFE_CODE_SIZE, + &imx_lpddr3_freq_change, + MX7_BUSFREQ_OCRAM_SIZE - SMP_WFE_CODE_SIZE); + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} + +/* Used by i.MX6SX/i.MX6UL for mmdc setting init. */ +int init_mmdc_ddr3_settings_imx6_up(struct platform_device *busfreq_pdev) +{ + int i; + struct device_node *node; + unsigned long ddr_code_size; + + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc"); + if (!node) { + printk(KERN_ERR "failed to find mmdc device tree data!\n"); + return -EINVAL; + } + mmdc_base = of_iomap(node, 0); + WARN(!mmdc_base, "unable to map mmdc registers\n"); + + if (cpu_is_imx6sx()) + node = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-iomuxc"); + else + node = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-iomuxc"); + if (!node) { + printk(KERN_ERR "failed to find iomuxc device tree data!\n"); + return -EINVAL; + } + iomux_base = of_iomap(node, 0); + WARN(!iomux_base, "unable to map iomux registers\n"); + + ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6sx) + + ARRAY_SIZE(ddr3_calibration_mx6sx); + + normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL); + memcpy(normal_mmdc_settings, ddr3_dll_mx6sx, + sizeof(ddr3_dll_mx6sx)); + memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6sx)), + ddr3_calibration_mx6sx, sizeof(ddr3_calibration_mx6sx)); + + /* store the original DDR settings at boot. */ + for (i = 0; i < ddr_settings_size; i++) { + /* + * writes via command mode register cannot be read back. + * hence hardcode them in the initial static array. + * this may require modification on a per customer basis. + */ + if (normal_mmdc_settings[i][0] != 0x1C) + normal_mmdc_settings[i][1] = + readl_relaxed(mmdc_base + + normal_mmdc_settings[i][0]); + } + + if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz()) + iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6ul); + else + iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6sx); + + ddr_code_size = (&imx6_up_ddr3_freq_change_end -&imx6_up_ddr3_freq_change_start) *4 + + sizeof(*imx6_busfreq_info); + imx6_busfreq_info = (struct imx6_busfreq_info *)ddr_freq_change_iram_base; + + imx6_up_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base + sizeof(*imx6_busfreq_info), + &imx6_up_ddr3_freq_change, ddr_code_size - sizeof(*imx6_busfreq_info)); + + /* + * Store the size of the array in iRAM also, + * increase the size by 8 bytes. + */ + iram_iomux_settings = (void *)(ddr_freq_change_iram_base + ddr_code_size); + iram_ddr_settings = iram_iomux_settings + (iomux_settings_size * 8) + 8; + + if ((ddr_code_size + (iomux_settings_size + ddr_settings_size) * 8 + 16) + > ddr_freq_change_total_size) { + printk(KERN_ERR "Not enough memory allocated for DDR Frequency change code.\n"); + return EINVAL; + } + + for (i = 0; i < iomux_settings_size; i++) { + if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz()) { + iomux_offsets_mx6ul[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6ul[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6ul[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6ul[i][1]; + } else { + iomux_offsets_mx6sx[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6sx[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6sx[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6sx[i][1]; + } + } + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} + +int init_mmdc_ddr3_settings_imx6_smp(struct platform_device *busfreq_pdev) +{ + int i; + struct device_node *node; + unsigned long ddr_code_size; + unsigned long wfe_code_size = 0; +#ifdef CONFIG_SMP + u32 cpu; + struct device *dev = &busfreq_pdev->dev; + int err; + struct irq_data *d; +#endif + + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc-combine"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-mmdc device tree data!\n"); + return -EINVAL; + } + mmdc_base = of_iomap(node, 0); + WARN(!mmdc_base, "unable to map mmdc registers\n"); + + node = NULL; + if (cpu_is_imx6q()) + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-iomuxc"); + if (cpu_is_imx6dl()) + node = of_find_compatible_node(NULL, NULL, + "fsl,imx6dl-iomuxc"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-iomux device tree data!\n"); + return -EINVAL; + } + iomux_base = of_iomap(node, 0); + WARN(!iomux_base, "unable to map iomux registers\n"); + + node = NULL; + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-a9-gic device tree data!\n"); + return -EINVAL; + } + gic_dist_base = of_iomap(node, 0); + WARN(!gic_dist_base, "unable to map gic dist registers\n"); + + if (cpu_is_imx6q()) + ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6q) + + ARRAY_SIZE(ddr3_calibration); + if (cpu_is_imx6dl()) + ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6dl) + + ARRAY_SIZE(ddr3_calibration); + + normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL); + if (cpu_is_imx6q()) { + memcpy(normal_mmdc_settings, ddr3_dll_mx6q, + sizeof(ddr3_dll_mx6q)); + memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6q)), + ddr3_calibration, sizeof(ddr3_calibration)); + } + if (cpu_is_imx6dl()) { + memcpy(normal_mmdc_settings, ddr3_dll_mx6dl, + sizeof(ddr3_dll_mx6dl)); + memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6dl)), + ddr3_calibration, sizeof(ddr3_calibration)); + } + /* store the original DDR settings at boot. */ + for (i = 0; i < ddr_settings_size; i++) { + /* + * writes via command mode register cannot be read back. + * hence hardcode them in the initial static array. + * this may require modification on a per customer basis. + */ + if (normal_mmdc_settings[i][0] != 0x1C) + normal_mmdc_settings[i][1] = + readl_relaxed(mmdc_base + + normal_mmdc_settings[i][0]); + } + +#ifdef CONFIG_SMP + irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(), + GFP_KERNEL); + + for_each_online_cpu(cpu) { + int irq; + + /* + * set up a reserved interrupt to get all + * the active cores into a WFE state + * before changing the DDR frequency. + */ + irq = platform_get_irq(busfreq_pdev, cpu); + err = request_irq(irq, wait_in_wfe_irq, + IRQF_PERCPU, "mmdc_1", NULL); + if (err) { + dev_err(dev, + "Busfreq:request_irq failed %d, err = %d\n", + irq, err); + return err; + } + err = irq_set_affinity(irq, cpumask_of(cpu)); + if (err) { + dev_err(dev, + "Busfreq: Cannot set irq affinity irq=%d,\n", + irq); + return err; + } + d = irq_get_irq_data(irq); + irqs_used[cpu] = d->hwirq + 32; + } +#endif + iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6q); + + ddr_code_size = (&mx6_ddr3_freq_change_end - + &mx6_ddr3_freq_change_start) * 4; + + mx6_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base, + &mx6_ddr3_freq_change, ddr_code_size); + + /* + * Store the size of the array in iRAM also, + * increase the size by 8 bytes. + */ + iram_iomux_settings = (void *)(ddr_freq_change_iram_base + + ddr_code_size); + iram_ddr_settings = iram_iomux_settings + (iomux_settings_size * 8) + 8; +#ifdef CONFIG_SMP + wfe_freq_change_iram_base = (unsigned long)((u32 *)iram_ddr_settings + + (ddr_settings_size * 8) + 8); + + if (wfe_freq_change_iram_base & (FNCPY_ALIGN - 1)) + wfe_freq_change_iram_base += FNCPY_ALIGN - + ((uintptr_t)wfe_freq_change_iram_base % (FNCPY_ALIGN)); + + wfe_code_size = (&wfe_smp_freq_change_end - + &wfe_smp_freq_change_start) *4; + + wfe_change_ddr_freq = (void *)fncpy((void *)wfe_freq_change_iram_base, + &wfe_smp_freq_change, wfe_code_size); + + /* + * Store the variable used to communicate + * between cores in a non-cacheable IRAM area + */ + wait_for_ddr_freq_update = (u32 *)&iram_iomux_settings[0][1]; +#endif + + if ((ddr_code_size + wfe_code_size + (iomux_settings_size + + ddr_settings_size) * 8 + 16) + > ddr_freq_change_total_size) { + printk(KERN_ERR "Not enough memory for DDR Freq scale.\n"); + return EINVAL; + } + + if (cpu_is_imx6q()) { + /* store the IOMUX settings at boot. */ + for (i = 0; i < iomux_settings_size; i++) { + iomux_offsets_mx6q[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6q[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6q[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6q[i][1]; + } + } + + if (cpu_is_imx6dl()) { + for (i = 0; i < iomux_settings_size; i++) { + iomux_offsets_mx6dl[i][1] = + readl_relaxed(iomux_base + + iomux_offsets_mx6dl[i][0]); + iram_iomux_settings[i + 1][0] = + iomux_offsets_mx6dl[i][0]; + iram_iomux_settings[i + 1][1] = + iomux_offsets_mx6dl[i][1]; + } + } + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/busfreq-imx.c linux-imx-phytec/arch/arm/mach-imx/busfreq-imx.c --- linux-6.1.55/arch/arm/mach-imx/busfreq-imx.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/busfreq-imx.c 2024-06-19 12:33:58.124189556 +0200 @@ -0,0 +1,1443 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP. + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "hardware.h" +#include "common.h" + +#define LPAPM_CLK 24000000 +#define LOW_AUDIO_CLK 50000000 +#define HIGH_AUDIO_CLK 100000000 + +#define LOW_POWER_RUN_VOLTAGE 950000 + +#define MMDC_MDMISC_DDR_TYPE_DDR3 0 +#define MMDC_MDMISC_DDR_TYPE_LPDDR2 1 + +unsigned int ddr_med_rate; +unsigned int ddr_normal_rate; +unsigned long ddr_freq_change_total_size; +unsigned long ddr_freq_change_iram_base; +unsigned long ddr_freq_change_iram_phys; + +static int ddr_type; +static int low_bus_freq_mode; +static int audio_bus_freq_mode; +static int ultra_low_bus_freq_mode; +static int high_bus_freq_mode; +static int med_bus_freq_mode; +static int bus_freq_scaling_initialized; +static bool cancel_reduce_bus_freq; +static struct device *busfreq_dev; +static int busfreq_suspended; +static int bus_freq_scaling_is_active; +static int high_bus_count, med_bus_count, audio_bus_count, low_bus_count; +static unsigned int ddr_low_rate; +static int cur_bus_freq_mode; +static u32 org_arm_rate; + +extern unsigned long iram_tlb_phys_addr; +extern int unsigned long iram_tlb_base_addr; + +/* + * Bus frequency management by Linux + */ +extern int init_mmdc_lpddr2_settings(struct platform_device *dev); +extern int init_mmdc_lpddr2_settings_mx6q(struct platform_device *dev); +extern int init_mmdc_ddr3_settings_imx6_up(struct platform_device *dev); +extern int init_mmdc_ddr3_settings_imx6_smp(struct platform_device *dev); +extern int init_ddrc_ddr_settings(struct platform_device *dev); +extern int update_ddr_freq_imx_smp(int ddr_rate); +extern int update_ddr_freq_imx6_up(int ddr_rate); +extern int update_lpddr2_freq(int ddr_rate); +extern int update_lpddr2_freq_smp(int ddr_rate); + +#ifdef CONFIG_OPTEE +/* + * Bus frequency management by OPTEE OS + */ +extern int update_freq_optee(int ddr_rate); +extern int init_freq_optee(struct platform_device *busfreq_pdev); +#endif + +/** + * @brief Functions to init and update the busfreq function of + * device and memory type + */ +static struct busfreq_func { + int (*init)(struct platform_device *dev); + int (*update)(int ddr_rate); +} busfreq_func = {NULL, NULL}; + +DEFINE_MUTEX(bus_freq_mutex); + +static struct clk *osc_clk; +static struct clk *ahb_clk; +static struct clk *axi_sel_clk; +static struct clk *dram_root; +static struct clk *dram_alt_sel; +static struct clk *dram_alt_root; +static struct clk *pfd0_392m; +static struct clk *pfd2_270m; +static struct clk *pfd1_332m; +static struct clk *pll_dram; +static struct clk *ahb_sel_clk; +static struct clk *axi_clk; + +static struct clk *m4_clk; +static struct clk *pll3_clk; +static struct clk *pll2_400_clk; +static struct clk *periph_clk2_sel_clk; +static struct clk *periph_pre_clk; +static struct clk *pll2_200_clk; +static struct clk *periph_clk; +static struct clk *mmdc_clk; +static struct clk *periph_clk2_clk; +static struct clk *pll2_bus_clk; + +static struct clk *pll2_bypass_src_clk; +static struct clk *pll2_bypass_clk; +static struct clk *pll2_clk; +static struct clk *arm_clk; +static struct clk *step_clk; +static struct clk *pll1_clk; +static struct clk *pll1_bypass_src_clk; +static struct clk *pll1_bypass_clk; +static struct clk *pll1_sys_clk; +static struct clk *pll1_sw_clk; + +static struct clk *axi_alt_sel_clk; +static struct clk *pll3_pfd1_540m_clk; + +static struct clk *ocram_clk; +static struct clk *periph2_clk; +static struct clk *periph2_pre_clk; +static struct clk *periph2_clk2_clk; +static struct clk *periph2_clk2_sel_clk; + +static struct delayed_work low_bus_freq_handler; +static struct delayed_work bus_freq_daemon; + +static RAW_NOTIFIER_HEAD(busfreq_notifier_chain); + +static bool check_m4_sleep(void) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(500); + + while (imx_gpc_is_m4_sleeping() == 0) + if (time_after(jiffies, timeout)) + return false; + return true; +} + +static bool busfreq_notified_low = false; + +static int busfreq_notify(enum busfreq_event event) +{ + int ret; + + if (event == LOW_BUSFREQ_ENTER) { + WARN_ON(busfreq_notified_low); + busfreq_notified_low = true; + } else if (event == LOW_BUSFREQ_EXIT) { + WARN_ON(!busfreq_notified_low); + busfreq_notified_low = false; + } + ret = raw_notifier_call_chain(&busfreq_notifier_chain, event, NULL); + + return notifier_to_errno(ret); +} + +#if defined(CONFIG_HAVE_IMX_BUSFREQ) + +int register_busfreq_notifier(struct notifier_block *nb) +{ + return raw_notifier_chain_register(&busfreq_notifier_chain, nb); +} +EXPORT_SYMBOL(register_busfreq_notifier); + +int unregister_busfreq_notifier(struct notifier_block *nb) +{ + return raw_notifier_chain_unregister(&busfreq_notifier_chain, nb); +} +EXPORT_SYMBOL(unregister_busfreq_notifier); + +#endif /* CONFIG_HAVE_IMX_BUSFREQ */ + +static struct clk *origin_step_parent; + +/* + * on i.MX6ULL, when entering low bus mode, the ARM core + * can run at 24MHz to support the low power run mode per + * to design team. + */ +static void imx6ull_lower_cpu_rate(bool enter) +{ + if (enter) { + org_arm_rate = clk_get_rate(arm_clk); + } + + clk_set_parent(pll1_bypass_clk, pll1_bypass_src_clk); + clk_set_parent(pll1_sw_clk, pll1_sys_clk); + + if (enter) { + origin_step_parent = clk_get_parent(step_clk); + clk_set_parent(step_clk, osc_clk); + clk_set_parent(pll1_sw_clk, step_clk); + clk_set_rate(arm_clk, LPAPM_CLK); + } else { + clk_set_parent(step_clk, origin_step_parent); + clk_set_parent(pll1_sw_clk, step_clk); + clk_set_rate(arm_clk, org_arm_rate); + clk_set_parent(pll1_bypass_clk, pll1_clk); + } +} + +/* + * enter_lpm_imx6_up and exit_lpm_imx6_up is used by + * i.MX6SX/i.MX6UL for entering and exiting lpm mode. + */ +static void enter_lpm_imx6_up(void) +{ + if (cpu_is_imx6sx() && imx_src_is_m4_enabled()) + if (!check_m4_sleep()) + pr_err("M4 is NOT in sleep!!!\n"); + + /* set periph_clk2 to source from OSC for periph */ + clk_set_parent(periph_clk2_sel_clk, osc_clk); + clk_set_parent(periph_clk, periph_clk2_clk); + /* set ahb/ocram to 24MHz */ + clk_set_rate(ahb_clk, LPAPM_CLK); + clk_set_rate(ocram_clk, LPAPM_CLK); + + if (audio_bus_count) { + /* Need to ensure that PLL2_PFD_400M is kept ON. */ + clk_prepare_enable(pll2_400_clk); + if (ddr_type == IMX_DDR_TYPE_DDR3) + busfreq_func.update(LOW_AUDIO_CLK); + else if (ddr_type == IMX_DDR_TYPE_LPDDR2 || + ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) + busfreq_func.update(HIGH_AUDIO_CLK); + clk_set_parent(periph2_clk2_sel_clk, pll3_clk); + clk_set_parent(periph2_pre_clk, pll2_400_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + /* + * As periph2_clk's parent is not changed from + * high mode to audio mode, so clk framework + * will not update its children's freq, but we + * change the mmdc's podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. + */ + if (high_bus_freq_mode) { + if (ddr_type == IMX_DDR_TYPE_DDR3) + clk_set_rate(mmdc_clk, LOW_AUDIO_CLK); + else if (ddr_type == IMX_DDR_TYPE_LPDDR2 || + ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) + clk_set_rate(mmdc_clk, HIGH_AUDIO_CLK); + } + + if ((cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) && low_bus_freq_mode) + imx6ull_lower_cpu_rate(false); + + audio_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + busfreq_func.update(LPAPM_CLK); + + clk_set_parent(periph2_clk2_sel_clk, osc_clk); + clk_set_parent(periph2_clk, periph2_clk2_clk); + + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); + + if (cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) + imx6ull_lower_cpu_rate(true); + + low_bus_freq_mode = 1; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_LOW; + } +} + +static void enter_lpm_imx6_smp(void) +{ + if (cpu_is_imx6dl()) + /* Set axi to periph_clk */ + clk_set_parent(axi_sel_clk, periph_clk); + + if (audio_bus_count) { + /* Need to ensure that PLL2_PFD_400M is kept ON. */ + clk_prepare_enable(pll2_400_clk); + if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + busfreq_func.update(LOW_AUDIO_CLK); + else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) + busfreq_func.update(HIGH_AUDIO_CLK); + /* Make sure periph clk's parent also got updated */ + clk_set_parent(periph_clk2_sel_clk, pll3_clk); + if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + clk_set_parent(periph_pre_clk, pll2_200_clk); + else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) + clk_set_parent(periph_pre_clk, pll2_400_clk); + clk_set_parent(periph_clk, periph_pre_clk); + + /* + * As periph_pre_clk's parent is not changed from + * high mode to audio mode on lpddr2, the clk framework + * will not update its children's freq, but we + * change the mmdc_ch0_axi podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. Calling get_rate will only call + * the .rate_recalc which is all we need. + */ + if (high_bus_freq_mode && mmdc_clk) + if (ddr_type == IMX_DDR_TYPE_LPDDR2) + clk_get_rate(mmdc_clk); + + audio_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + busfreq_func.update(LPAPM_CLK); + + /* Make sure periph clk's parent also got updated */ + clk_set_parent(periph_clk2_sel_clk, osc_clk); + /* Set periph_clk parent to OSC via periph_clk2_sel */ + clk_set_parent(periph_clk, periph_clk2_clk); + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); + low_bus_freq_mode = 1; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_LOW; + } +} + +static void exit_lpm_imx6_up(void) +{ + if ((cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) && low_bus_freq_mode) + imx6ull_lower_cpu_rate(false); + + clk_prepare_enable(pll2_400_clk); + + /* + * lower ahb/ocram's freq first to avoid too high + * freq during parent switch from OSC to pll3. + */ + if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz() + || cpu_is_imx6sll()) + clk_set_rate(ahb_clk, LPAPM_CLK / 4); + else + clk_set_rate(ahb_clk, LPAPM_CLK / 3); + + clk_set_rate(ocram_clk, LPAPM_CLK / 2); + /* set periph clk to from pll2_bus on i.MX6UL */ + if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) + clk_set_parent(periph_pre_clk, pll2_bus_clk); + /* set periph clk to from pll2_400 */ + else + clk_set_parent(periph_pre_clk, pll2_400_clk); + clk_set_parent(periph_clk, periph_pre_clk); + /* set periph_clk2 to pll3 */ + clk_set_parent(periph_clk2_sel_clk, pll3_clk); + + busfreq_func.update(ddr_normal_rate); + + /* correct parent info after ddr freq change in asm code */ + clk_set_parent(periph2_pre_clk, pll2_400_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + clk_set_parent(periph2_clk2_sel_clk, pll3_clk); + + /* + * As periph2_clk's parent is not changed from + * audio mode to high mode, so clk framework + * will not update its children's freq, but we + * change the mmdc's podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. + */ + if (audio_bus_freq_mode) + clk_set_rate(mmdc_clk, ddr_normal_rate); + + clk_disable_unprepare(pll2_400_clk); + + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); +} + +static void exit_lpm_imx6_smp(void) +{ + struct clk *periph_clk_parent; + + if (cpu_is_imx6q() && ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) + periph_clk_parent = pll2_bus_clk; + else + periph_clk_parent = pll2_400_clk; + + clk_prepare_enable(pll2_400_clk); + + busfreq_func.update(ddr_normal_rate); + + /* Make sure periph clk's parent also got updated */ + clk_set_parent(periph_clk2_sel_clk, pll3_clk); + clk_set_parent(periph_pre_clk, periph_clk_parent); + clk_set_parent(periph_clk, periph_pre_clk); + if (cpu_is_imx6dl()) { + /* Set axi to pll3_pfd1_540m */ + clk_set_parent(axi_alt_sel_clk, pll3_pfd1_540m_clk); + clk_set_parent(axi_sel_clk, axi_alt_sel_clk); + } + /* + * As periph_pre_clk's parent is not changed from + * high mode to audio mode on lpddr2, the clk framework + * will not update its children's freq, but we + * change the mmdc_ch0_axi podf in asm code, so here + * need to update mmdc rate to make sure clk + * tree is right, although it will not do any + * change to hardware. Calling get_rate will only call + * the .rate_recalc which is all we need. + */ + if (audio_bus_freq_mode && mmdc_clk) + if (ddr_type == IMX_DDR_TYPE_LPDDR2) + clk_get_rate(mmdc_clk); + + clk_disable_unprepare(pll2_400_clk); + if (audio_bus_freq_mode) + clk_disable_unprepare(pll2_400_clk); +} + +static void enter_lpm_imx6sl(void) +{ + if (high_bus_freq_mode) { + /* Set periph_clk to be sourced from OSC_CLK */ + clk_set_parent(periph_clk2_sel_clk, osc_clk); + clk_set_parent(periph_clk, periph_clk2_clk); + /* Ensure AHB/AXI clks are at 24MHz. */ + clk_set_rate(ahb_clk, LPAPM_CLK); + clk_set_rate(ocram_clk, LPAPM_CLK); + } + if (audio_bus_count) { + /* Set AHB to 8MHz to lower pwer.*/ + clk_set_rate(ahb_clk, LPAPM_CLK / 3); + + /* Set up DDR to 100MHz. */ + busfreq_func.update(HIGH_AUDIO_CLK); + + /* Fix the clock tree in kernel */ + clk_set_parent(periph2_pre_clk, pll2_200_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + + if (low_bus_freq_mode || ultra_low_bus_freq_mode) { + /* + * Fix the clock tree in kernel, make sure + * pll2_bypass is updated as it is + * sourced from PLL2. + */ + clk_set_parent(pll2_bypass_clk, pll2_clk); + /* + * Swtich ARM to run off PLL2_PFD2_400MHz + * since DDR is anyway at 100MHz. + */ + clk_set_parent(step_clk, pll2_400_clk); + clk_set_parent(pll1_sw_clk, step_clk); + + /* + * Need to ensure that PLL1 is bypassed and enabled + * before ARM-PODF is set. + */ + clk_set_parent(pll1_bypass_clk, pll1_bypass_src_clk); + + /* + * Ensure that the clock will be + * at original speed. + */ + clk_set_rate(arm_clk, org_arm_rate); + } + low_bus_freq_mode = 0; + ultra_low_bus_freq_mode = 0; + audio_bus_freq_mode = 1; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + u32 arm_div, pll1_rate; + org_arm_rate = clk_get_rate(arm_clk); + if (org_arm_rate == 0) { + WARN_ON(1); + return; + } + if (low_bus_freq_mode && low_bus_count == 0) { + /* + * We are already in DDR @ 24MHz state, but + * no one but ARM needs the DDR. In this case, + * we can lower the DDR freq to 1MHz when ARM + * enters WFI in this state. Keep track of this state. + */ + ultra_low_bus_freq_mode = 1; + low_bus_freq_mode = 0; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_ULTRA_LOW; + } else { + if (!ultra_low_bus_freq_mode && !low_bus_freq_mode) { + /* + * Anyway, make sure the AHB is running at 24MHz + * in low_bus_freq_mode. + */ + if (audio_bus_freq_mode) + clk_set_rate(ahb_clk, LPAPM_CLK); + /* + * Set DDR to 24MHz. + * Since we are going to bypass PLL2, + * we need to move ARM clk off PLL2_PFD2 + * to PLL1. Make sure the PLL1 is running + * at the lowest possible freq. + * To work well with CPUFREQ we want to ensure that + * the CPU freq does not change, so attempt to + * get a freq as close to 396MHz as possible. + */ + clk_set_rate(pll1_clk, + clk_round_rate(pll1_clk, (org_arm_rate * 2))); + pll1_rate = clk_get_rate(pll1_clk); + arm_div = pll1_rate / org_arm_rate; + if (pll1_rate / arm_div > org_arm_rate) + arm_div++; + /* + * Need to ensure that PLL1 is bypassed and enabled + * before ARM-PODF is set. + */ + clk_set_parent(pll1_bypass_clk, pll1_clk); + /* + * Ensure ARM CLK is lower before + * changing the parent. + */ + clk_set_rate(arm_clk, org_arm_rate / arm_div); + /* Now set the ARM clk parent to PLL1_SYS. */ + clk_set_parent(pll1_sw_clk, pll1_sys_clk); + + /* + * Set STEP_CLK back to OSC to save power and + * also to maintain the parent.The WFI iram code + * will switch step_clk to osc, but the clock API + * is not aware of the change and when a new request + * to change the step_clk parent to pll2_pfd2_400M + * is requested sometime later, the change is ignored. + */ + clk_set_parent(step_clk, osc_clk); + + /* Now set DDR to 24MHz. */ + busfreq_func.update(LPAPM_CLK); + + /* + * Fix the clock tree in kernel. + * Make sure PLL2 rate is updated as it gets + * bypassed in the DDR freq change code. + */ + clk_set_parent(pll2_bypass_clk, pll2_bypass_src_clk); + clk_set_parent(periph2_clk2_sel_clk, pll2_bus_clk); + clk_set_parent(periph2_clk, periph2_clk2_clk); + } + if (low_bus_count == 0) { + ultra_low_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_ULTRA_LOW; + } else { + ultra_low_bus_freq_mode = 0; + low_bus_freq_mode = 1; + cur_bus_freq_mode = BUS_FREQ_LOW; + } + audio_bus_freq_mode = 0; + } + } +} + +static void exit_lpm_imx6sl(void) +{ + /* Change DDR freq in IRAM. */ + busfreq_func.update(ddr_normal_rate); + + /* + * Fix the clock tree in kernel. + * Make sure PLL2 rate is updated as it gets + * un-bypassed in the DDR freq change code. + */ + clk_set_parent(pll2_bypass_clk, pll2_clk); + clk_set_parent(periph2_pre_clk, pll2_400_clk); + clk_set_parent(periph2_clk, periph2_pre_clk); + + /* Ensure that periph_clk is sourced from PLL2_400. */ + clk_set_parent(periph_pre_clk, pll2_400_clk); + /* + * Before switching the perhiph_clk, ensure that the + * AHB/AXI will not be too fast. + */ + clk_set_rate(ahb_clk, LPAPM_CLK / 3); + clk_set_rate(ocram_clk, LPAPM_CLK / 2); + clk_set_parent(periph_clk, periph_pre_clk); + + if (low_bus_freq_mode || ultra_low_bus_freq_mode) { + /* Move ARM from PLL1_SW_CLK to PLL2_400. */ + clk_set_parent(step_clk, pll2_400_clk); + clk_set_parent(pll1_sw_clk, step_clk); + /* + * Need to ensure that PLL1 is bypassed and enabled + * before ARM-PODF is set. + */ + clk_set_parent(pll1_bypass_clk, pll1_bypass_src_clk); + clk_set_rate(arm_clk, org_arm_rate); + ultra_low_bus_freq_mode = 0; + } +} + +static void enter_lpm_imx7d(void) +{ + /* + * The AHB clock parent switch and divider change + * needs to keep previous/current parent enabled + * per design requirement, but when we switch the + * clock parent, previous AHB clock parent may be + * disabled by common clock framework, so here we + * have to make sure AHB's previous parent pfd2_270m + * is enabled during AHB set rate. + */ + clk_prepare_enable(pfd2_270m); + if (audio_bus_count) { + clk_prepare_enable(pfd0_392m); + busfreq_func.update(HIGH_AUDIO_CLK); + + clk_set_parent(dram_alt_sel, pfd0_392m); + clk_set_parent(dram_root, dram_alt_root); + if (high_bus_freq_mode) { + clk_set_parent(axi_sel_clk, osc_clk); + clk_set_parent(ahb_sel_clk, osc_clk); + clk_set_rate(ahb_clk, LPAPM_CLK); + } + clk_disable_unprepare(pfd0_392m); + audio_bus_freq_mode = 1; + low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_AUDIO; + } else { + busfreq_func.update(LPAPM_CLK); + + clk_set_parent(dram_alt_sel, osc_clk); + clk_set_parent(dram_root, dram_alt_root); + if (high_bus_freq_mode) { + clk_set_parent(axi_sel_clk, osc_clk); + clk_set_parent(ahb_sel_clk, osc_clk); + clk_set_rate(ahb_clk, LPAPM_CLK); + } + low_bus_freq_mode = 1; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_LOW; + } + clk_disable_unprepare(pfd2_270m); +} + +static void exit_lpm_imx7d(void) +{ + clk_set_parent(axi_sel_clk, pfd1_332m); + clk_set_rate(ahb_clk, LPAPM_CLK / 2); + clk_set_parent(ahb_sel_clk, pfd2_270m); + + busfreq_func.update(ddr_normal_rate); + + clk_set_parent(dram_root, pll_dram); +} + +static void reduce_bus_freq(void) +{ + if (cpu_is_imx6()) + clk_prepare_enable(pll3_clk); + + if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode)) + busfreq_notify(LOW_BUSFREQ_EXIT); + else if (!audio_bus_count) + busfreq_notify(LOW_BUSFREQ_ENTER); + + if (cpu_is_imx7d()) + enter_lpm_imx7d(); + else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + enter_lpm_imx6_up(); + else if (cpu_is_imx6q() || cpu_is_imx6dl()) + enter_lpm_imx6_smp(); + else if (cpu_is_imx6sl()) + enter_lpm_imx6sl(); + + med_bus_freq_mode = 0; + high_bus_freq_mode = 0; + + if (cpu_is_imx6()) + clk_disable_unprepare(pll3_clk); + + if (audio_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to audio mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); + if (low_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to low mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); +} + +static inline void cancel_low_bus_freq_handler(void) +{ + cancel_delayed_work(&low_bus_freq_handler); + cancel_reduce_bus_freq = true; +} + +static void reduce_bus_freq_handler(struct work_struct *work) +{ + mutex_lock(&bus_freq_mutex); + + if (!cancel_reduce_bus_freq) { + reduce_bus_freq(); + cancel_low_bus_freq_handler(); + } + + mutex_unlock(&bus_freq_mutex); +} + +/* + * Set the DDR, AHB to 24MHz. + * This mode will be activated only when none of the modules that + * need a higher DDR or AHB frequency are active. + */ +static int set_low_bus_freq(void) +{ + if (busfreq_suspended) + return 0; + + if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active) + return 0; + + cancel_reduce_bus_freq = false; + + /* + * Check to see if we need to got from + * low bus freq mode to audio bus freq mode. + * If so, the change needs to be done immediately. + */ + if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode)) + reduce_bus_freq(); + else + /* + * Don't lower the frequency immediately. Instead + * scheduled a delayed work and drop the freq if + * the conditions still remain the same. + */ + schedule_delayed_work(&low_bus_freq_handler, + usecs_to_jiffies(3000000)); + return 0; +} + +/* + * Set the DDR to either 528MHz or 400MHz for iMX6qd + * or 400MHz for iMX6dl. + */ +static int set_high_bus_freq(int high_bus_freq) +{ + if (bus_freq_scaling_initialized && bus_freq_scaling_is_active) + cancel_low_bus_freq_handler(); + + if (busfreq_suspended) + return 0; + + if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active) + return 0; + + if (high_bus_freq_mode) + return 0; + + /* medium bus freq is only supported for MX6DQ */ + if (med_bus_freq_mode && !high_bus_freq) + return 0; + + if (low_bus_freq_mode || ultra_low_bus_freq_mode) + busfreq_notify(LOW_BUSFREQ_EXIT); + + if (cpu_is_imx6()) + clk_prepare_enable(pll3_clk); + + if (cpu_is_imx7d()) + exit_lpm_imx7d(); + else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + exit_lpm_imx6_up(); + else if (cpu_is_imx6q() || cpu_is_imx6dl()) + exit_lpm_imx6_smp(); + else if (cpu_is_imx6sl()) + exit_lpm_imx6sl(); + + high_bus_freq_mode = 1; + med_bus_freq_mode = 0; + low_bus_freq_mode = 0; + audio_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_HIGH; + + if (cpu_is_imx6()) + clk_disable_unprepare(pll3_clk); + + if (high_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to high mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); + if (med_bus_freq_mode) + dev_dbg(busfreq_dev, + "Bus freq set to med mode. Count: high %d, med %d, audio %d\n", + high_bus_count, med_bus_count, audio_bus_count); + + return 0; +} + +#if defined(CONFIG_HAVE_IMX_BUSFREQ) +void request_bus_freq(enum bus_freq_mode mode) +{ + mutex_lock(&bus_freq_mutex); + + if (mode == BUS_FREQ_ULTRA_LOW) { + dev_dbg(busfreq_dev, "This mode cannot be requested!\n"); + mutex_unlock(&bus_freq_mutex); + return; + } + + if (mode == BUS_FREQ_HIGH) + high_bus_count++; + else if (mode == BUS_FREQ_MED) + med_bus_count++; + else if (mode == BUS_FREQ_AUDIO) + audio_bus_count++; + else if (mode == BUS_FREQ_LOW) + low_bus_count++; + + if (busfreq_suspended || !bus_freq_scaling_initialized || + !bus_freq_scaling_is_active) { + mutex_unlock(&bus_freq_mutex); + return; + } + + cancel_low_bus_freq_handler(); + + if ((mode == BUS_FREQ_HIGH) && (!high_bus_freq_mode)) { + set_high_bus_freq(1); + mutex_unlock(&bus_freq_mutex); + return; + } + + if ((mode == BUS_FREQ_MED) && (!high_bus_freq_mode) && + (!med_bus_freq_mode)) { + set_high_bus_freq(0); + mutex_unlock(&bus_freq_mutex); + return; + } + if ((mode == BUS_FREQ_AUDIO) && (!high_bus_freq_mode) && + (!med_bus_freq_mode) && (!audio_bus_freq_mode)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + mutex_unlock(&bus_freq_mutex); +} +EXPORT_SYMBOL(request_bus_freq); + +void release_bus_freq(enum bus_freq_mode mode) +{ + mutex_lock(&bus_freq_mutex); + + if (mode == BUS_FREQ_ULTRA_LOW) { + dev_dbg(busfreq_dev, + "This mode cannot be released!\n"); + mutex_unlock(&bus_freq_mutex); + return; + } + + if (mode == BUS_FREQ_HIGH) { + if (high_bus_count == 0) { + dev_err(busfreq_dev, "high bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + high_bus_count--; + } else if (mode == BUS_FREQ_MED) { + if (med_bus_count == 0) { + dev_err(busfreq_dev, "med bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + med_bus_count--; + } else if (mode == BUS_FREQ_AUDIO) { + if (audio_bus_count == 0) { + dev_err(busfreq_dev, "audio bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + audio_bus_count--; + } else if (mode == BUS_FREQ_LOW) { + if (low_bus_count == 0) { + dev_err(busfreq_dev, "low bus count mismatch!\n"); + dump_stack(); + mutex_unlock(&bus_freq_mutex); + return; + } + low_bus_count--; + } + + if (busfreq_suspended || !bus_freq_scaling_initialized || + !bus_freq_scaling_is_active) { + mutex_unlock(&bus_freq_mutex); + return; + } + + if ((!audio_bus_freq_mode) && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count != 0)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + if ((!low_bus_freq_mode) && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count == 0) && + (low_bus_count != 0)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + if ((!ultra_low_bus_freq_mode) && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count == 0) && + (low_bus_count == 0)) { + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); + return; + } + + mutex_unlock(&bus_freq_mutex); +} +EXPORT_SYMBOL(release_bus_freq); + +int get_bus_freq_mode(void) +{ + return cur_bus_freq_mode; +} +EXPORT_SYMBOL(get_bus_freq_mode); + +#endif /* CONFIG_HAVE_IMX_BUSFREQ */ + +static struct map_desc ddr_iram_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +static int __init imx_dt_find_ddr_sram(unsigned long node, + const char *uname, int depth, void *data) +{ + unsigned long ddr_iram_addr; + const __be32 *prop; + + if (of_flat_dt_is_compatible(node, "fsl,ddr-lpm-sram")) { + unsigned int len; + + prop = of_get_flat_dt_prop(node, "reg", &len); + if (prop == NULL || len != (sizeof(unsigned long) * 2)) + return -EINVAL; + ddr_iram_addr = be32_to_cpu(prop[0]); + ddr_freq_change_total_size = be32_to_cpu(prop[1]); + ddr_freq_change_iram_phys = ddr_iram_addr; + + /* Make sure ddr_freq_change_iram_phys is 8 byte aligned. */ + if ((uintptr_t)(ddr_freq_change_iram_phys) & (FNCPY_ALIGN - 1)) + ddr_freq_change_iram_phys += FNCPY_ALIGN - + ((uintptr_t)ddr_freq_change_iram_phys % + (FNCPY_ALIGN)); + } + return 0; +} + +void __init imx_busfreq_map_io(void) +{ + /* + * Get the address of IRAM to be used by the ddr frequency + * change code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx_dt_find_ddr_sram, NULL)); + if (ddr_freq_change_iram_phys) { + ddr_freq_change_iram_base = IMX_IO_P2V( + ddr_freq_change_iram_phys); + if ((iram_tlb_phys_addr & 0xFFF00000) != + (ddr_freq_change_iram_phys & 0xFFF00000)) { + /* We need to create a 1M page table entry. */ + ddr_iram_io_desc.virtual = IMX_IO_P2V( + ddr_freq_change_iram_phys & 0xFFF00000); + ddr_iram_io_desc.pfn = __phys_to_pfn( + ddr_freq_change_iram_phys & 0xFFF00000); + iotable_init(&ddr_iram_io_desc, 1); + } + memset((void *)ddr_freq_change_iram_base, 0, + ddr_freq_change_total_size); + } +} + +static void bus_freq_daemon_handler(struct work_struct *work) +{ + mutex_lock(&bus_freq_mutex); + if ((!low_bus_freq_mode) && (!ultra_low_bus_freq_mode) + && (high_bus_count == 0) && + (med_bus_count == 0) && (audio_bus_count == 0)) + set_low_bus_freq(); + mutex_unlock(&bus_freq_mutex); +} + +static ssize_t bus_freq_scaling_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (bus_freq_scaling_is_active) + return sprintf(buf, "Bus frequency scaling is enabled\n"); + else + return sprintf(buf, "Bus frequency scaling is disabled\n"); +} + +static ssize_t bus_freq_scaling_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strncmp(buf, "1", 1) == 0) { + bus_freq_scaling_is_active = 1; + set_high_bus_freq(1); + /* + * We set bus freq to highest at the beginning, + * so we use this daemon thread to make sure system + * can enter low bus mode if + * there is no high bus request pending + */ + schedule_delayed_work(&bus_freq_daemon, + usecs_to_jiffies(5000000)); + } else if (strncmp(buf, "0", 1) == 0) { + if (bus_freq_scaling_is_active) + set_high_bus_freq(1); + bus_freq_scaling_is_active = 0; + } + return size; +} + +static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event, + void *dummy) +{ + mutex_lock(&bus_freq_mutex); + + if (event == PM_SUSPEND_PREPARE) { + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) + imx_mu_lpm_ready(false); + high_bus_count++; + set_high_bus_freq(1); + busfreq_suspended = 1; + } else if (event == PM_POST_SUSPEND) { + busfreq_suspended = 0; + high_bus_count--; + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) + imx_mu_lpm_ready(true); + schedule_delayed_work(&bus_freq_daemon, + usecs_to_jiffies(5000000)); + } + + mutex_unlock(&bus_freq_mutex); + + return NOTIFY_OK; +} + +static int busfreq_reboot_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + /* System is rebooting. Set the system into high_bus_freq_mode. */ + request_bus_freq(BUS_FREQ_HIGH); + + return 0; +} + +static struct notifier_block imx_bus_freq_pm_notifier = { + .notifier_call = bus_freq_pm_notify, +}; + +static struct notifier_block imx_busfreq_reboot_notifier = { + .notifier_call = busfreq_reboot_notifier_event, +}; + + +static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show, + bus_freq_scaling_enable_store); + +/*! + * This is the probe routine for the bus frequency driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ + +static int busfreq_probe(struct platform_device *pdev) +{ + u32 err; +#ifdef CONFIG_OPTEE + struct device_node *node_optee = 0; + uint32_t busfreq_val; +#endif + + busfreq_dev = &pdev->dev; + + /* Return if no IRAM space is allocated for ddr freq change code. */ + if (!ddr_freq_change_iram_base) + return -ENOMEM; + + if (cpu_is_imx6()) { + osc_clk = devm_clk_get(&pdev->dev, "osc"); + pll2_400_clk = devm_clk_get(&pdev->dev, "pll2_pfd2_396m"); + pll2_200_clk = devm_clk_get(&pdev->dev, "pll2_198m"); + pll2_bus_clk = devm_clk_get(&pdev->dev, "pll2_bus"); + pll3_clk = devm_clk_get(&pdev->dev, "pll3_usb_otg"); + periph_clk = devm_clk_get(&pdev->dev, "periph"); + periph_pre_clk = devm_clk_get(&pdev->dev, "periph_pre"); + periph_clk2_clk = devm_clk_get(&pdev->dev, "periph_clk2"); + periph_clk2_sel_clk = devm_clk_get(&pdev->dev, + "periph_clk2_sel"); + if (IS_ERR(osc_clk) || IS_ERR(pll2_400_clk) + || IS_ERR(pll2_200_clk) || IS_ERR(pll2_bus_clk) + || IS_ERR(pll3_clk) || IS_ERR(periph_clk) + || IS_ERR(periph_pre_clk) || IS_ERR(periph_clk2_clk) + || IS_ERR(periph_clk2_sel_clk)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6dl()) { + axi_alt_sel_clk = devm_clk_get(&pdev->dev, "axi_alt_sel"); + axi_sel_clk = devm_clk_get(&pdev->dev, "axi_sel"); + pll3_pfd1_540m_clk = devm_clk_get(&pdev->dev, "pll3_pfd1_540m"); + if (IS_ERR(axi_alt_sel_clk) || IS_ERR(axi_sel_clk) + || IS_ERR(pll3_pfd1_540m_clk)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6sx() || cpu_is_imx6sl() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) { + ahb_clk = devm_clk_get(&pdev->dev, "ahb"); + ocram_clk = devm_clk_get(&pdev->dev, "ocram"); + periph2_clk = devm_clk_get(&pdev->dev, "periph2"); + periph2_pre_clk = devm_clk_get(&pdev->dev, "periph2_pre"); + periph2_clk2_clk = devm_clk_get(&pdev->dev, "periph2_clk2"); + periph2_clk2_sel_clk = + devm_clk_get(&pdev->dev, "periph2_clk2_sel"); + if (IS_ERR(ahb_clk) || IS_ERR(ocram_clk) + || IS_ERR(periph2_clk) || IS_ERR(periph2_pre_clk) + || IS_ERR(periph2_clk2_clk) + || IS_ERR(periph2_clk2_sel_clk)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk for imx6ul/sx/sl.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) { + mmdc_clk = devm_clk_get(&pdev->dev, "mmdc"); + if (IS_ERR(mmdc_clk)) { + dev_err(busfreq_dev, + "%s: failed to get mmdc clk for imx6sx/ul.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6q()) { + mmdc_clk = devm_clk_get(&pdev->dev, "mmdc"); + if (IS_ERR(mmdc_clk)) { + mmdc_clk = NULL; + } + } + + if (cpu_is_imx6sx()) { + m4_clk = devm_clk_get(&pdev->dev, "m4"); + if (IS_ERR(m4_clk)) { + dev_err(busfreq_dev, "%s: failed to get m4 clk.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6sl()) { + pll2_bypass_src_clk = devm_clk_get(&pdev->dev, "pll2_bypass_src"); + pll2_bypass_clk = devm_clk_get(&pdev->dev, "pll2_bypass"); + pll2_clk = devm_clk_get(&pdev->dev, "pll2"); + if (IS_ERR(pll2_bypass_src_clk) || IS_ERR(pll2_bypass_clk) + || IS_ERR(pll2_clk)) { + dev_err(busfreq_dev, + "%s failed to get busfreq clk for imx6sl.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx6sl() || cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) { + arm_clk = devm_clk_get(&pdev->dev, "arm"); + step_clk = devm_clk_get(&pdev->dev, "step"); + pll1_clk = devm_clk_get(&pdev->dev, "pll1"); + pll1_bypass_src_clk = devm_clk_get(&pdev->dev, "pll1_bypass_src"); + pll1_bypass_clk = devm_clk_get(&pdev->dev, "pll1_bypass"); + pll1_sys_clk = devm_clk_get(&pdev->dev, "pll1_sys"); + pll1_sw_clk = devm_clk_get(&pdev->dev, "pll1_sw"); + if (IS_ERR(arm_clk) || IS_ERR(step_clk) || IS_ERR(pll1_clk) + || IS_ERR(pll1_bypass_src_clk) || IS_ERR(pll1_bypass_clk) + || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk)) { + dev_err(busfreq_dev, "%s failed to get busfreq clk for imx6ull/sl.\n", __func__); + return -EINVAL; + } + } + + if (cpu_is_imx7d()) { + osc_clk = devm_clk_get(&pdev->dev, "osc"); + axi_sel_clk = devm_clk_get(&pdev->dev, "axi_sel"); + ahb_sel_clk = devm_clk_get(&pdev->dev, "ahb_sel"); + pfd0_392m = devm_clk_get(&pdev->dev, "pfd0_392m"); + dram_root = devm_clk_get(&pdev->dev, "dram_root"); + dram_alt_sel = devm_clk_get(&pdev->dev, "dram_alt_sel"); + pll_dram = devm_clk_get(&pdev->dev, "pll_dram"); + dram_alt_root = devm_clk_get(&pdev->dev, "dram_alt_root"); + pfd1_332m = devm_clk_get(&pdev->dev, "pfd1_332m"); + pfd2_270m = devm_clk_get(&pdev->dev, "pfd2_270m"); + ahb_clk = devm_clk_get(&pdev->dev, "ahb"); + axi_clk = devm_clk_get(&pdev->dev, "axi"); + if (IS_ERR(osc_clk) || IS_ERR(axi_sel_clk) || IS_ERR(ahb_clk) + || IS_ERR(pfd0_392m) || IS_ERR(dram_root) + || IS_ERR(dram_alt_sel) || IS_ERR(pll_dram) + || IS_ERR(dram_alt_root) || IS_ERR(pfd1_332m) + || IS_ERR(ahb_clk) || IS_ERR(axi_clk) + || IS_ERR(pfd2_270m)) { + dev_err(busfreq_dev, + "%s: failed to get busfreq clk\n", __func__); + return -EINVAL; + } + } + + err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr); + if (err) { + dev_err(busfreq_dev, + "Unable to register sysdev entry for BUSFREQ"); + return err; + } + + if (of_property_read_u32(pdev->dev.of_node, "fsl,max_ddr_freq", + &ddr_normal_rate)) { + dev_err(busfreq_dev, "max_ddr_freq entry missing\n"); + return -EINVAL; + } + + high_bus_freq_mode = 1; + med_bus_freq_mode = 0; + low_bus_freq_mode = 0; + audio_bus_freq_mode = 0; + ultra_low_bus_freq_mode = 0; + cur_bus_freq_mode = BUS_FREQ_HIGH; + + bus_freq_scaling_is_active = 1; + bus_freq_scaling_initialized = 1; + + ddr_low_rate = LPAPM_CLK; + + INIT_DELAYED_WORK(&low_bus_freq_handler, reduce_bus_freq_handler); + INIT_DELAYED_WORK(&bus_freq_daemon, bus_freq_daemon_handler); + register_pm_notifier(&imx_bus_freq_pm_notifier); + register_reboot_notifier(&imx_busfreq_reboot_notifier); + + /* enter low bus mode if no high speed device enabled */ + schedule_delayed_work(&bus_freq_daemon, + msecs_to_jiffies(20000)); + + /* + * Need to make sure to an entry for the ddr freq change code + * address in the IRAM page table. + * This is only required if the DDR freq code and suspend/idle + * code are in different OCRAM spaces. + */ + if ((iram_tlb_phys_addr & 0xFFF00000) != + (ddr_freq_change_iram_phys & 0xFFF00000)) { + unsigned long i; + + /* + * Make sure the ddr_iram virtual address has a mapping + * in the IRAM page table. + */ + i = ((IMX_IO_P2V(ddr_freq_change_iram_phys) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (ddr_freq_change_iram_phys & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + if (cpu_is_imx7d()) { + ddr_type = imx_ddrc_get_ddr_type(); + /* reduce ddr3 normal rate to 400M due to CKE issue on TO1.1 */ + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_1 && + ddr_type == IMX_DDR_TYPE_DDR3) { + ddr_normal_rate = 400000000; + pr_info("ddr3 normal rate changed to 400MHz for TO1.1.\n"); + } + busfreq_func.init = &init_ddrc_ddr_settings; + busfreq_func.update = &update_ddr_freq_imx_smp; + + } else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz() || + cpu_is_imx6sll()) { + ddr_type = imx_mmdc_get_ddr_type(); + if (ddr_type == IMX_DDR_TYPE_DDR3) { + busfreq_func.init = &init_mmdc_ddr3_settings_imx6_up; + busfreq_func.update = &update_ddr_freq_imx6_up; + } else if (ddr_type == IMX_DDR_TYPE_LPDDR2 || + ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) { + busfreq_func.init = &init_mmdc_lpddr2_settings; + busfreq_func.update = &update_lpddr2_freq; + } + } else if (cpu_is_imx6q() || cpu_is_imx6dl()) { + ddr_type = imx_mmdc_get_ddr_type(); + if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) { + busfreq_func.init = &init_mmdc_ddr3_settings_imx6_smp; + busfreq_func.update = &update_ddr_freq_imx_smp; + } else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) { + busfreq_func.init = &init_mmdc_lpddr2_settings_mx6q; + busfreq_func.update = &update_lpddr2_freq_smp; + } + } else if (cpu_is_imx6sl()) { + busfreq_func.init = &init_mmdc_lpddr2_settings; + busfreq_func.update = &update_lpddr2_freq; + } + +#ifdef CONFIG_OPTEE + /* + * Find the OPTEE node in the DT and look for the + * busfreq property. + * If property present and set to 1, busfreq is done by + * calling the OPTEE OS + */ + node_optee = of_find_compatible_node(NULL, NULL, "linaro,optee-tz"); + + if (node_optee) { + if (of_property_read_u32(node_optee, "busfreq", + &busfreq_val) == 0) { + pr_info("OPTEE busfreq %s", + (busfreq_val ? "Supported" : "Not Supported")); + if (busfreq_val) { + busfreq_func.init = &init_freq_optee; + busfreq_func.update = &update_freq_optee; + } + } + } +#endif + + if (busfreq_func.init) + err = busfreq_func.init(pdev); + else + err = -EINVAL; + + if (!err) { + if (cpu_is_imx6sx()) { + /* + * If M4 is enabled and rate > 24MHz, + * add high bus count + */ + if (imx_src_is_m4_enabled() && + (clk_get_rate(m4_clk) > LPAPM_CLK)) + high_bus_count++; + } + + if (cpu_is_imx7d() && imx_src_is_m4_enabled()) { + high_bus_count++; + imx_mu_lpm_ready(true); + } + } + + if (err) { + dev_err(busfreq_dev, "Busfreq init of ddr controller failed\n"); + return err; + } + + return 0; +} + +static const struct of_device_id imx_busfreq_ids[] = { + { .compatible = "fsl,imx_busfreq", }, + { /* sentinel */ } +}; + +static struct platform_driver busfreq_driver = { + .driver = { + .name = "imx_busfreq", + .owner = THIS_MODULE, + .of_match_table = imx_busfreq_ids, + }, + .probe = busfreq_probe, +}; + +/*! + * Initialise the busfreq_driver. + * + * @return The function always returns 0. + */ + +static int __init busfreq_init(void) +{ +#ifndef CONFIG_MX6_VPU_352M + if (platform_driver_register(&busfreq_driver) != 0) + return -ENODEV; + + pr_info("Bus freq driver module loaded\n"); +#endif + return 0; +} + +static void __exit busfreq_cleanup(void) +{ + sysfs_remove_file(&busfreq_dev->kobj, &dev_attr_enable.attr); + + /* Unregister the device structure */ + platform_driver_unregister(&busfreq_driver); + bus_freq_scaling_initialized = 0; +} + +module_init(busfreq_init); +module_exit(busfreq_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("BusFreq driver"); +MODULE_LICENSE("GPL"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/busfreq_lpddr2.c linux-imx-phytec/arch/arm/mach-imx/busfreq_lpddr2.c --- linux-6.1.55/arch/arm/mach-imx/busfreq_lpddr2.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/busfreq_lpddr2.c 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,374 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file busfreq_lpddr2.c + * + * @brief iMX6 LPDDR2 frequency change specific file. + * + * @ingroup PM + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "hardware.h" + +static struct device *busfreq_dev; +static int curr_ddr_rate; +static DEFINE_SPINLOCK(freq_lock); + +void (*mx6_change_lpddr2_freq)(u32 ddr_freq, int bus_freq_mode) = NULL; + +extern unsigned int ddr_normal_rate; +extern void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode); +extern void imx6_up_lpddr2_freq_change(u32 freq, int bus_freq_mode); +extern void imx6sll_lpddr2_freq_change(u32 freq, int bus_freq_mode); +extern unsigned long save_ttbr1(void); +extern void restore_ttbr1(unsigned long ttbr1); +extern void mx6q_lpddr2_freq_change(u32 freq, void *ddr_settings); +extern unsigned long ddr_freq_change_iram_base; +extern unsigned long imx6_lpddr2_freq_change_start asm("imx6_lpddr2_freq_change_start"); +extern unsigned long imx6_lpddr2_freq_change_end asm("imx6_lpddr2_freq_change_end"); +extern unsigned long mx6q_lpddr2_freq_change_start asm("mx6q_lpddr2_freq_change_start"); +extern unsigned long mx6q_lpddr2_freq_change_end asm("mx6q_lpddr2_freq_change_end"); +extern unsigned long iram_tlb_phys_addr; + +struct mmdc_settings_info { + u32 size; + void *settings; + int freq; +} __aligned(8); +static struct mmdc_settings_info *mmdc_settings_info; +void (*mx6_change_lpddr2_freq_smp)(u32 ddr_freq, struct mmdc_settings_info + *mmdc_settings_info) = NULL; + +static int mmdc_settings_size; +static unsigned long (*mmdc_settings)[2]; +static unsigned long (*iram_mmdc_settings)[2]; +static unsigned long *iram_settings_size; +static unsigned long *iram_ddr_freq_chage; +unsigned long mmdc_timing_settings[][2] = { + {0x0C, 0x0}, /* mmdc_mdcfg0 */ + {0x10, 0x0}, /* mmdc_mdcfg1 */ + {0x14, 0x0}, /* mmdc_mdcfg2 */ + {0x18, 0x0}, /* mmdc_mdmisc */ + {0x38, 0x0}, /* mmdc_mdcfg3lp */ +}; + +#ifdef CONFIG_SMP +volatile u32 *wait_for_lpddr2_freq_update; +static unsigned int online_cpus; +static u32 *irqs_used; +void (*wfe_change_lpddr2_freq)(u32 cpuid, u32 *ddr_freq_change_done); +extern void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done); +extern unsigned long wfe_smp_freq_change_start asm("wfe_smp_freq_change_start"); +extern unsigned long wfe_smp_freq_change_end asm("wfe_smp_freq_change_end"); +extern void __iomem *scu_base; +static void __iomem *gic_dist_base; +#endif + +#ifdef CONFIG_SMP +static irqreturn_t wait_in_wfe_irq(int irq, void *dev_id) +{ + u32 me; + + me = smp_processor_id(); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &me); +#endif + wfe_change_lpddr2_freq(0xff << (me * 8), + (u32 *)ddr_freq_change_iram_base); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &me); +#endif + return IRQ_HANDLED; +} +#endif + +/* change the DDR frequency. */ +int update_lpddr2_freq(int ddr_rate) +{ + unsigned long ttbr1, flags; + int mode = get_bus_freq_mode(); + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate); + + spin_lock_irqsave(&freq_lock, flags); + /* + * Flush the TLB, to ensure no TLB maintenance occurs + * when DDR is in self-refresh. + */ + ttbr1 = save_ttbr1(); + + /* Now change DDR frequency. */ + if (cpu_is_imx6sl()) + mx6_change_lpddr2_freq(ddr_rate, + (mode == BUS_FREQ_LOW || mode == BUS_FREQ_ULTRA_LOW) ? 1 : 0); + else + mx6_change_lpddr2_freq(ddr_rate, + (mode == BUS_FREQ_LOW || mode == BUS_FREQ_AUDIO) ? 1 : 0); + + restore_ttbr1(ttbr1); + + curr_ddr_rate = ddr_rate; + spin_unlock_irqrestore(&freq_lock, flags); + + printk(KERN_DEBUG "\nBus freq set to %d done...\n", ddr_rate); + + return 0; +} + +int init_mmdc_lpddr2_settings(struct platform_device *busfreq_pdev) +{ + unsigned long ddr_code_size; + busfreq_dev = &busfreq_pdev->dev; + + ddr_code_size = SZ_4K; + + if (cpu_is_imx6sl()) + mx6_change_lpddr2_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base, + &mx6_lpddr2_freq_change, ddr_code_size); + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz()) + mx6_change_lpddr2_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base, + &imx6_up_lpddr2_freq_change, ddr_code_size); + if (cpu_is_imx6sll()) + mx6_change_lpddr2_freq = (void *)fncpy( + (void *)ddr_freq_change_iram_base, + &imx6sll_lpddr2_freq_change, ddr_code_size); + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} + +int update_lpddr2_freq_smp(int ddr_rate) +{ + unsigned long ttbr1; + int i, me = 0; +#ifdef CONFIG_SMP + int cpu = 0; + u32 reg = 0; +#endif + + if (ddr_rate == curr_ddr_rate) + return 0; + + printk(KERN_DEBUG "Bus freq set to %d start...\n", ddr_rate); + + for (i=0; i < mmdc_settings_size; i++) { + iram_mmdc_settings[i][0] = mmdc_settings[i][0]; + iram_mmdc_settings[i][1] = mmdc_settings[i][1]; + } + + mmdc_settings_info->size = mmdc_settings_size; + mmdc_settings_info->settings = iram_mmdc_settings; + mmdc_settings_info->freq = curr_ddr_rate; + + /* ensure that all Cores are in WFE. */ + local_irq_disable(); + +#ifdef CONFIG_SMP + me = smp_processor_id(); + + /* Make sure all the online cores are active */ + while (1) { + bool not_exited_busfreq = false; + for_each_online_cpu(cpu) { + reg = __raw_readl(scu_base + 0x08); + if (reg & (0x02 << (cpu * 8))) + not_exited_busfreq = true; + } + if (!not_exited_busfreq) + break; + } + + wmb(); + *wait_for_lpddr2_freq_update = 1; + dsb(); + online_cpus = readl_relaxed(scu_base + 0x08); + for_each_online_cpu(cpu) { + *((char *)(&online_cpus) + (u8)cpu) = 0x02; + if (cpu != me) { + reg = 1 << (irqs_used[cpu] % 32); + writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET + + (irqs_used[cpu] / 32) * 4); + } + } + + /* Wait for the other active CPUs to idle */ + while (1) { + reg = 0; + reg = readl_relaxed(scu_base + 0x08); + reg |= (0x02 << (me * 8)); + if (reg == online_cpus) + break; + } +#endif + + /* Ensure iram_tlb_phys_addr is flushed to DDR. */ + __cpuc_flush_dcache_area(&iram_tlb_phys_addr, + sizeof(iram_tlb_phys_addr)); + outer_clean_range(__pa(&iram_tlb_phys_addr), + __pa(&iram_tlb_phys_addr + 1)); + /* + * Flush the TLB, to ensure no TLB maintenance occurs + * when DDR is in self-refresh. + */ + ttbr1 = save_ttbr1(); + + curr_ddr_rate = ddr_rate; + + /* Now change DDR frequency. */ + mx6_change_lpddr2_freq_smp(ddr_rate, mmdc_settings_info); + + restore_ttbr1(ttbr1); + +#ifdef CONFIG_SMP + wmb(); + /* DDR frequency change is done . */ + *wait_for_lpddr2_freq_update = 0; + dsb(); + /* wake up all the cores. */ + sev(); +#endif + + local_irq_enable(); + + printk(KERN_DEBUG "Bus freq set to %d done! cpu=%d\n", ddr_rate, me); + + return 0; +} + +int init_mmdc_lpddr2_settings_mx6q(struct platform_device *busfreq_pdev) +{ + struct device *dev = &busfreq_pdev->dev; + unsigned long ddr_code_size = 0; + unsigned long wfe_code_size = 0; + struct device_node *node; + void __iomem *mmdc_base; + int i; +#ifdef CONFIG_SMP + struct irq_data *d; + u32 cpu; + int err; +#endif + + node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc"); + if (!node) { + printk(KERN_ERR "failed to find mmdc device tree data!\n"); + return -EINVAL; + } + + mmdc_base = of_iomap(node, 0); + if (!mmdc_base) { + dev_err(dev, "unable to map mmdc registers\n"); + return -EINVAL; + } + + mmdc_settings_size = ARRAY_SIZE(mmdc_timing_settings); + mmdc_settings = kmalloc((mmdc_settings_size * 8), GFP_KERNEL); + memcpy(mmdc_settings, mmdc_timing_settings, + sizeof(mmdc_timing_settings)); + +#ifdef CONFIG_SMP + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); + if (!node) { + printk(KERN_ERR "failed to find imx6q-a9-gic device tree data!\n"); + return -EINVAL; + } + + gic_dist_base = of_iomap(node, 0); + WARN(!gic_dist_base, "unable to map gic dist registers\n"); + + irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(), + GFP_KERNEL); + + for_each_online_cpu(cpu) { + int irq = platform_get_irq(busfreq_pdev, cpu); + err = request_irq(irq, wait_in_wfe_irq, IRQF_PERCPU, + "mmdc_1", NULL); + if (err) { + dev_err(dev, + "Busfreq:request_irq failed %d, err = %d\n", + irq, err); + return err; + } + err = irq_set_affinity(irq, cpumask_of(cpu)); + if (err) { + dev_err(dev, + "Busfreq: Cannot set irq affinity irq=%d,\n", + irq); + return err; + } + d = irq_get_irq_data(irq); + irqs_used[cpu] = d->hwirq + 32; + } + + /* Stoange_iram_basee the variable used to communicate between cores in + * a non-cacheable IRAM area */ + wait_for_lpddr2_freq_update = (u32 *)ddr_freq_change_iram_base; + wfe_code_size = (&wfe_smp_freq_change_end - &wfe_smp_freq_change_start) *4; + + wfe_change_lpddr2_freq = (void *)fncpy((void *)ddr_freq_change_iram_base + 0x8, + &wfe_smp_freq_change, wfe_code_size); +#endif + iram_settings_size = (void *)ddr_freq_change_iram_base + wfe_code_size + 0x8; + iram_mmdc_settings = (void *)iram_settings_size + sizeof(*mmdc_settings_info); + iram_ddr_freq_chage = (void *)iram_mmdc_settings + (mmdc_settings_size * 8) + 0x8; + mmdc_settings_info = (struct mmdc_settings_info *)iram_settings_size; + + ddr_code_size = (&mx6q_lpddr2_freq_change_end -&mx6q_lpddr2_freq_change_start) *4; + + mx6_change_lpddr2_freq_smp = (void *)fncpy(iram_ddr_freq_chage, + &mx6q_lpddr2_freq_change, ddr_code_size); + + /* save initial mmdc boot timing settings */ + for (i=0; i < mmdc_settings_size; i++) + mmdc_settings[i][1] = readl_relaxed(mmdc_base + + mmdc_settings[i][0]); + + curr_ddr_rate = ddr_normal_rate; + + return 0; +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/busfreq_optee.c linux-imx-phytec/arch/arm/mach-imx/busfreq_optee.c --- linux-6.1.55/arch/arm/mach-imx/busfreq_optee.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/busfreq_optee.c 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 NXP + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file busfreq_optee.c + * + * @brief iMX.6 and i.MX7 Bus Frequency change.\n + * Call OPTEE busfreq function regardless memory type and device. + * + * @ingroup PM + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hardware.h" +#include "smc_sip.h" + + +extern unsigned int ddr_normal_rate; +static int curr_ddr_rate; + +#ifdef CONFIG_SMP +/* + * External declaration + */ +extern void imx_smp_wfe_optee(u32 cpuid, u32 status_addr); +extern unsigned long imx_smp_wfe_start asm("imx_smp_wfe_optee"); +extern unsigned long imx_smp_wfe_end asm("imx_smp_wfe_optee_end"); + +extern unsigned long ddr_freq_change_iram_base; + + +/** + * @brief Definition of the synchronization status + * structure used to control to CPUs status + * and on-going frequency change + */ +struct busfreq_sync { + uint32_t change_ongoing; + uint32_t wfe_status[NR_CPUS]; +} __aligned(8); + +static struct busfreq_sync *pSync; + +static void (*wfe_change_freq)(uint32_t *wfe_status, uint32_t *freq_done); + +static uint32_t *irqs_for_wfe; +static void __iomem *gic_dist_base; + +/** + * @brief Switch all active cores, except the one changing the + * bus frequency, in WFE mode until completion of the + * frequency change + * + * @param[in] irq Interrupt ID - not used + * @param[in] dev_id Client data - not used + * + * @retval IRQ_HANDLED Interrupt handled + */ +static irqreturn_t wait_in_wfe_irq(int irq, void *dev_id) +{ + uint32_t me; + + me = smp_processor_id(); +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, + &me); +#endif + + wfe_change_freq(&pSync->wfe_status[me], &pSync->change_ongoing); + +#ifdef CONFIG_LOCAL_TIMERS + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, + &me); +#endif + + return IRQ_HANDLED; +} +#endif + +/** + * @brief Request OPTEE OS to change the memory bus frequency + * to \a ddr_rate value + * + * @param[in] rate Bus Frequency + * + * @retval 0 Success + */ +int update_freq_optee(int ddr_rate) +{ + struct arm_smccc_res res; + + uint32_t me = 0; + uint32_t dll_off = 0; + int mode = get_bus_freq_mode(); + +#ifdef CONFIG_SMP + uint32_t reg = 0; + uint32_t cpu = 0; + uint32_t online_cpus = 0; + uint32_t all_cpus = 0; +#endif + + pr_info("\nBusfreq OPTEE set from %d to %d start...\n", + curr_ddr_rate, ddr_rate); + + if (ddr_rate == curr_ddr_rate) + return 0; + + if (cpu_is_imx6()) { + if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO)) + dll_off = 1; + } + + local_irq_disable(); + +#ifdef CONFIG_SMP + me = smp_processor_id(); + + /* Make sure all the online cores to be active */ + do { + all_cpus = 0; + + for_each_online_cpu(cpu) + all_cpus |= (pSync->wfe_status[cpu] << cpu); + } while (all_cpus); + + pSync->change_ongoing = 1; + dsb(); + + for_each_online_cpu(cpu) { + if (cpu != me) { + online_cpus |= (1 << cpu); + /* Set the interrupt to be pending in the GIC. */ + reg = 1 << (irqs_for_wfe[cpu] % 32); + writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET + + (irqs_for_wfe[cpu] / 32) * 4); + } + } + + /* Wait for all active CPUs to be in WFE */ + do { + all_cpus = 0; + + for_each_online_cpu(cpu) + all_cpus |= (pSync->wfe_status[cpu] << cpu); + } while (all_cpus != online_cpus); + +#endif + + /* Now we can change the DDR frequency. */ + /* Call the TEE SiP */ + arm_smccc_smc(OPTEE_SMC_FAST_CALL_SIP_VAL(IMX_SIP_BUSFREQ_CHANGE), + ddr_rate, dll_off, 0, 0, 0, 0, 0, &res); + + curr_ddr_rate = ddr_rate; + +#ifdef CONFIG_SMP + /* DDR frequency change is done */ + pSync->change_ongoing = 0; + dsb(); + + /* wake up all the cores. */ + sev(); +#endif + + local_irq_enable(); + + pr_info("Busfreq OPTEE set to %d done! cpu=%d\n", + ddr_rate, me); + + return 0; +} + +#ifdef CONFIG_SMP +static int init_freq_optee_smp(struct platform_device *busfreq_pdev) +{ + struct device_node *node = 0; + struct device *dev = &busfreq_pdev->dev; + uint32_t cpu; + int err; + int irq; + struct irq_data *irq_data; + unsigned long wfe_iram_base; + + if (cpu_is_imx6()) { + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); + if (!node) { + if (cpu_is_imx6q()) + pr_debug("failed to find imx6q-a9-gic device tree data!\n"); + + return -EINVAL; + } + } else { + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a7-gic"); + if (!node) { + pr_debug("failed to find imx7d-a7-gic device tree data!\n"); + return -EINVAL; + } + } + + gic_dist_base = of_iomap(node, 0); + WARN(!gic_dist_base, "unable to map gic dist registers\n"); + + irqs_for_wfe = devm_kzalloc(dev, sizeof(uint32_t) * num_present_cpus(), + GFP_KERNEL); + + for_each_online_cpu(cpu) { + /* + * set up a reserved interrupt to get all + * the active cores into a WFE state + * before changing the DDR frequency. + */ + irq = platform_get_irq(busfreq_pdev, cpu); + + if (cpu_is_imx6()) { + err = request_irq(irq, wait_in_wfe_irq, + IRQF_PERCPU, "mmdc_1", NULL); + } else { + err = request_irq(irq, wait_in_wfe_irq, + IRQF_PERCPU, "ddrc", NULL); + } + + if (err) { + dev_err(dev, + "Busfreq:request_irq failed %d, err = %d\n", + irq, err); + return err; + } + + err = irq_set_affinity(irq, cpumask_of(cpu)); + if (err) { + dev_err(dev, + "Busfreq: Cannot set irq affinity irq=%d,\n", + irq); + return err; + } + + irq_data = irq_get_irq_data(irq); + irqs_for_wfe[cpu] = irq_data->hwirq + 32; + } + + /* Store the variable used to communicate between cores */ + pSync = (void *)ddr_freq_change_iram_base; + + memset(pSync, 0, sizeof(*pSync)); + + wfe_iram_base = ddr_freq_change_iram_base + sizeof(*pSync); + + if (wfe_iram_base & (FNCPY_ALIGN - 1)) + wfe_iram_base += FNCPY_ALIGN - + ((uintptr_t)wfe_iram_base % (FNCPY_ALIGN)); + + wfe_change_freq = (void *)fncpy((void *)wfe_iram_base, + &imx_smp_wfe_optee, + ((&imx_smp_wfe_end -&imx_smp_wfe_start) *4)); + + return 0; + +} + +int init_freq_optee(struct platform_device *busfreq_pdev) +{ + int err = -EINVAL; + struct device *dev = &busfreq_pdev->dev; + + if (num_present_cpus() <= 1) { + wfe_change_freq = NULL; + + /* Allocate the cores synchronization variables (not used) */ + pSync = devm_kzalloc(dev, sizeof(*pSync), GFP_KERNEL); + + if (pSync) + err = 0; + } else { + err = init_freq_optee_smp(busfreq_pdev); + } + + if (err == 0) + curr_ddr_rate = ddr_normal_rate; + + return err; +} +#else +int init_freq_optee(struct platform_device *busfreq_pdev) +{ + curr_ddr_rate = ddr_normal_rate; + return 0; +} +#endif + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/common.c linux-imx-phytec/arch/arm/mach-imx/common.c --- linux-6.1.55/arch/arm/mach-imx/common.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/common.c 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include + +#include "hardware.h" + +unsigned long iram_tlb_base_addr; +unsigned long iram_tlb_phys_addr; + +unsigned long save_ttbr1(void) +{ + unsigned long lttbr1; + asm volatile( + ".align 4\n" + "mrc p15, 0, %0, c2, c0, 1\n" + : "=r" (lttbr1) + ); + return lttbr1; +} + +void restore_ttbr1(unsigned long ttbr1) +{ + asm volatile( + ".align 4\n" + "mcr p15, 0, %0, c2, c0, 1\n" + : : "r" (ttbr1) + ); +} + +#define OCOTP_MAC_OFF (cpu_is_imx7d() ? 0x640 : 0x620) +#define OCOTP_MACn(n) (OCOTP_MAC_OFF + (n) * 0x10) +void __init imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat) +{ + struct device_node *ocotp_np, *enet_np, *from = NULL; + void __iomem *base; + struct property *newmac; + unsigned char tmpaddr[ETH_ALEN]; + u32 macaddr_low; + u32 macaddr_high = 0; + u32 macaddr1_high = 0; + u8 *macaddr; + int i, id; + + for (i = 0; i < 2; i++) { + enet_np = of_find_compatible_node(from, NULL, enet_compat); + if (!enet_np) + return; + + from = enet_np; + + if (!of_get_mac_address(enet_np, tmpaddr)) + goto put_enet_node; + + id = of_alias_get_id(enet_np, "ethernet"); + if (id < 0) + id = i; + + ocotp_np = of_find_compatible_node(NULL, NULL, ocotp_compat); + if (!ocotp_np) { + pr_warn("failed to find ocotp node\n"); + goto put_enet_node; + } + + base = of_iomap(ocotp_np, 0); + if (!base) { + pr_warn("failed to map ocotp\n"); + goto put_ocotp_node; + } + + macaddr_low = readl_relaxed(base + OCOTP_MACn(1)); + if (id) + macaddr1_high = readl_relaxed(base + OCOTP_MACn(2)); + else + macaddr_high = readl_relaxed(base + OCOTP_MACn(0)); + + newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL); + if (!newmac) + goto put_ocotp_node; + + newmac->value = newmac + 1; + newmac->length = 6; + newmac->name = kstrdup("local-mac-address", GFP_KERNEL); + if (!newmac->name) { + kfree(newmac); + goto put_ocotp_node; + } + + macaddr = newmac->value; + if (id) { + macaddr[5] = (macaddr_low >> 16) & 0xff; + macaddr[4] = (macaddr_low >> 24) & 0xff; + macaddr[3] = macaddr1_high & 0xff; + macaddr[2] = (macaddr1_high >> 8) & 0xff; + macaddr[1] = (macaddr1_high >> 16) & 0xff; + macaddr[0] = (macaddr1_high >> 24) & 0xff; + } else { + macaddr[5] = macaddr_high & 0xff; + macaddr[4] = (macaddr_high >> 8) & 0xff; + macaddr[3] = (macaddr_high >> 16) & 0xff; + macaddr[2] = (macaddr_high >> 24) & 0xff; + macaddr[1] = macaddr_low & 0xff; + macaddr[0] = (macaddr_low >> 8) & 0xff; + } + + of_update_property(enet_np, newmac); + +put_ocotp_node: + of_node_put(ocotp_np); +put_enet_node: + of_node_put(enet_np); + } +} + +#ifndef CONFIG_HAVE_IMX_GPC +int imx_gpc_mf_request_on(unsigned int irq, unsigned int on) { return 0; } +EXPORT_SYMBOL_GPL(imx_gpc_mf_request_on); +#endif + +#if !defined(CONFIG_SOC_IMX6SL) +u32 imx6_lpddr2_freq_change_start, imx6_lpddr2_freq_change_end; +void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode) {} +#endif + +#if !defined(CONFIG_SOC_IMX6SLL) +void imx6sll_lpddr2_freq_change(u32 freq, int bus_freq_mode) {} +#endif + +#if !defined(CONFIG_SOC_IMX6SX) && !defined(CONFIG_SOC_IMX6UL) +u32 imx6_up_ddr3_freq_change_start, imx6_up_ddr3_freq_change_end; +struct imx6_busfreq_info { +} __aligned(8); +void imx6_up_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info) {} +void imx6_up_lpddr2_freq_change(u32 freq, int bus_freq_mode) {} +#endif + +#if !defined(CONFIG_SOC_IMX6Q) +u32 mx6_ddr3_freq_change_start, mx6_ddr3_freq_change_end; +u32 mx6q_lpddr2_freq_change_start, mx6q_lpddr2_freq_change_end; +u32 wfe_smp_freq_change_start, wfe_smp_freq_change_end; +void mx6_ddr3_freq_change(u32 freq, void *ddr_settings, + bool dll_mode, void *iomux_offsets) {} +void mx6q_lpddr2_freq_change(u32 freq, void *ddr_settings) {} +void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done) {} +#endif + +#if !defined(CONFIG_SOC_IMX7D) +void imx7_smp_wfe(u32 cpuid, u32 ocram_base) {} +void imx7d_ddr3_freq_change(u32 freq) {} +#endif + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/common.h linux-imx-phytec/arch/arm/mach-imx/common.h --- linux-6.1.55/arch/arm/mach-imx/common.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/common.h 2024-06-19 12:33:58.128189625 +0200 @@ -8,6 +8,7 @@ #define __ASM_ARCH_MXC_COMMON_H__ #include +#include struct irq_data; struct platform_device; @@ -39,9 +40,19 @@ void imx_gpc_set_l2_mem_power_in_lpm(bool power_off); void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); +void imx_gpcv2_pre_suspend(bool arm_power_off); +void imx_gpcv2_post_resume(void); +unsigned int imx_gpcv2_is_mf_mix_off(void); +void imx_gpcv2_enable_wakeup_for_m4(void); +void imx_gpcv2_disable_wakeup_for_m4(void); void imx25_pm_init(void); void imx27_pm_init(void); void imx5_pmu_init(void); +#ifdef CONFIG_HAVE_IMX_MU +int imx_mu_lpm_ready(bool ready); +#else +static inline int imx_mu_lpm_ready(bool ready) { return 0; } +#endif enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ @@ -72,44 +83,106 @@ static inline void imx_scu_map_io(void) {} static inline void imx_smp_prepare(void) {} #endif +void imx6sx_set_m4_highfreq(bool high_freq); +void imx_mu_enable_m4_irqs_in_gic(bool enable); +#ifdef CONFIG_HAVE_IMX_GPC +void imx_gpc_add_m4_wake_up_irq(u32 irq, bool enable); +unsigned int imx_gpc_is_m4_sleeping(void); +#else +static inline void imx_gpc_add_m4_wake_up_irq(u32 irq, bool enable) {} +static inline unsigned int imx_gpc_is_m4_sleeping(void) { return 0; } +#endif +#ifdef CONFIG_HAVE_IMX_GPCV2 +int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on); +void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn); +void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable); +#else +static inline int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on) { return 0; } +static inline void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) {} +static inline void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable) {} +#endif +void imx_gpc_hold_m4_in_sleep(void); +void imx_gpc_release_m4_in_sleep(void); +void __init imx_gpcv2_check_dt(void); +void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode); +void imx_gpcv2_set_cpu_power_gate_in_idle(bool pdn); +void imx_gpcv2_enable_rbc(bool enable); +bool imx_mu_is_m4_in_low_freq(void); +bool imx_mu_is_m4_in_stop(void); +void imx_mu_set_m4_run_mode(void); void imx_src_init(void); -void imx7_src_init(void); void imx_gpc_pre_suspend(bool arm_power_off); void imx_gpc_post_resume(void); +void imx_gpc_switch_pupscr_clk(bool flag); void imx_gpc_mask_all(void); void imx_gpc_restore_all(void); void imx_gpc_hwirq_mask(unsigned int hwirq); void imx_gpc_hwirq_unmask(unsigned int hwirq); -void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn); +unsigned int imx_gpc_is_mf_mix_off(void); void imx_anatop_init(void); void imx_anatop_pre_suspend(void); void imx_anatop_post_resume(void); int imx6_set_lpm(enum mxc_cpu_pwr_mode mode); void imx6_set_int_mem_clk_lpm(bool enable); +void imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat); +void imx6sl_low_power_idle(void); +void imx6sll_low_power_idle(void); +void imx6sx_low_power_idle(void); +void imx6ul_low_power_idle(void); +void imx6ull_low_power_idle(void); +void imx7d_low_power_idle(void); +#ifdef CONFIG_HAVE_IMX_MMDC int imx_mmdc_get_ddr_type(void); +int imx_mmdc_get_lpddr2_2ch_mode(void); +#else +static inline int imx_mmdc_get_ddr_type(void) { return 0; } +static inline int imx_mmdc_get_lpddr2_2ch_mode(void) { return 0; } +#endif int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode); +u32 imx7ulp_get_mode(void); +void imx_busfreq_map_io(void); +void imx7_pm_map_io(void); +void imx6_pm_map_io(void); +void imx7ulp_pm_map_io(void); +void imx7ulp_enable_nmi(void); +void imx7ulp_poweroff(void); void imx_cpu_die(unsigned int cpu); int imx_cpu_kill(unsigned int cpu); #ifdef CONFIG_SUSPEND +void ca7_cpu_resume(void); void imx53_suspend(void __iomem *ocram_vbase); extern const u32 imx53_suspend_sz; void imx6_suspend(void __iomem *ocram_vbase); +void imx7_suspend(void __iomem *ocram_vbase); +void imx7ulp_cpu_resume(void); +void imx7ulp_suspend(void __iomem *ocram_vbase); #else +static inline void ca7_cpu_resume(void) {} static inline void imx53_suspend(void __iomem *ocram_vbase) {} static const u32 imx53_suspend_sz; static inline void imx6_suspend(void __iomem *ocram_vbase) {} +static inline void imx7_suspend(void __iomem *ocram_vbase) {} +static inline void imx7ulp_cpu_resume(void) {} +static inline void imx7ulp_suspend(void __iomem *ocram_vbase) {} #endif void v7_cpu_resume(void); +#ifdef CONFIG_HAVE_IMX_DDRC +int imx_ddrc_get_ddr_type(void); +#else +static inline int imx_ddrc_get_ddr_type(void) { return 0; } +#endif + void imx6_pm_ccm_init(const char *ccm_compat); void imx6q_pm_init(void); void imx6dl_pm_init(void); void imx6sl_pm_init(void); void imx6sx_pm_init(void); void imx6ul_pm_init(void); +void imx7d_pm_init(void); void imx7ulp_pm_init(void); #ifdef CONFIG_PM @@ -133,7 +206,7 @@ #endif extern const struct smp_operations imx_smp_ops; -extern const struct smp_operations imx7_smp_ops; extern const struct smp_operations ls1021a_smp_ops; +extern bool uart_from_osc; #endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/cpuidle.h linux-imx-phytec/arch/arm/mach-imx/cpuidle.h --- linux-6.1.55/arch/arm/mach-imx/cpuidle.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/cpuidle.h 2024-06-19 12:33:58.128189625 +0200 @@ -8,7 +8,11 @@ extern int imx5_cpuidle_init(void); extern int imx6q_cpuidle_init(void); extern int imx6sl_cpuidle_init(void); +extern int imx6sll_cpuidle_init(void); extern int imx6sx_cpuidle_init(void); +extern int imx6ul_cpuidle_init(void); +extern int imx7d_cpuidle_init(void); +extern int imx7d_enable_rcosc(void); extern int imx7ulp_cpuidle_init(void); #else static inline int imx5_cpuidle_init(void) @@ -23,10 +27,26 @@ { return 0; } +static inline int imx6sll_cpuidle_init(void) +{ + return 0; +} static inline int imx6sx_cpuidle_init(void) { return 0; } +static inline int imx6ul_cpuidle_init(void) +{ + return 0; +} +static inline int imx7d_cpuidle_init(void) +{ + return 0; +} +static inline int imx7d_enable_rcosc(void) +{ + return 0; +} static inline int imx7ulp_cpuidle_init(void) { return 0; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/cpuidle-imx6sl.c linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx6sl.c --- linux-6.1.55/arch/arm/mach-imx/cpuidle-imx6sl.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx6sl.c 2024-06-19 12:33:58.128189625 +0200 @@ -1,27 +1,105 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. */ #include +#include #include #include +#include +#include +#include +#include +#include +#include +#include #include +#include +#include + +#include #include "common.h" #include "cpuidle.h" +#include "hardware.h" + +#define MAX_MMDC_IO_NUM 19 + +static void __iomem *wfi_iram_base; +extern unsigned long iram_tlb_base_addr; + +#ifdef CONFIG_CPU_FREQ +extern unsigned long mx6sl_lpm_wfi_start asm("mx6sl_lpm_wfi_start"); +extern unsigned long mx6sl_lpm_wfi_end asm("mx6sl_lpm_wfi_end"); +#endif + +struct imx6_cpuidle_pm_info { + u32 pm_info_size; /* Size of pm_info */ + u32 ttbr; + void __iomem *mmdc_base; + void __iomem *iomuxc_base; + void __iomem *ccm_base; + void __iomem *l2_base; + void __iomem *anatop_base; + u32 mmdc_io_num; /*Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static const u32 imx6sl_mmdc_io_offset[] __initconst = { + 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ + 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ + 0x300, 0x31c, 0x338, 0x5ac, /*CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x33c, 0x340, 0x5b0, 0x5c0, /*SODT0, SODT1, ,MODE_CTL, MODE */ + 0x330, 0x334, 0x320, /*SDCKE0, SDCK1, RESET */ +}; + +static struct regulator *vbus_ldo; +static struct regulator_dev *ldo2p5_dummy_regulator_rdev; +static struct regulator_init_data ldo2p5_dummy_initdata = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; +static int ldo2p5_dummy_enable; + +static void (*imx6sl_wfi_in_iram_fn)(void __iomem *iram_vbase, + int audio_mode, bool vbus_ldo); + +#define MX6SL_POWERDWN_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) static int imx6sl_enter_wait(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { + int mode = get_bus_freq_mode(); + imx6_set_lpm(WAIT_UNCLOCKED); - /* - * Software workaround for ERR005311, see function - * description for details. - */ - imx6sl_set_wait_clk(true); - cpu_do_idle(); - imx6sl_set_wait_clk(false); + + if ((mode == BUS_FREQ_AUDIO) || (mode == BUS_FREQ_ULTRA_LOW)) { + /* + * bit 2 used for low power mode; + * bit 1 used for the ldo2p5_dummmy enable + */ + if (psci_ops.cpu_suspend) { + psci_ops.cpu_suspend((MX6SL_POWERDWN_IDLE_PARAM | ((mode == BUS_FREQ_AUDIO ? 1 : 0) << 2) | + (ldo2p5_dummy_enable ? 1 : 0) << 1), __pa(cpu_resume)); + } else { + imx6sl_wfi_in_iram_fn(wfi_iram_base, (mode == BUS_FREQ_AUDIO) ? 1 : 0, + ldo2p5_dummy_enable); + } + } else { + /* + * Software workaround for ERR005311, see function + * description for details. + */ + imx6sl_set_wait_clk(true); + cpu_do_idle(); + imx6sl_set_wait_clk(false); + } imx6_set_lpm(WAIT_CLOCKED); return index; @@ -49,5 +127,109 @@ int __init imx6sl_cpuidle_init(void) { + +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + vbus_ldo = regulator_get(NULL, "ldo2p5-dummy"); + if (IS_ERR(vbus_ldo)) + vbus_ldo = NULL; + + wfi_iram_base = (void *)(iram_tlb_base_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wif_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base) & (FNCPY_ALIGN - 1)) + wfi_iram_base += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base % (FNCPY_ALIGN)); + + pm_info = wfi_iram_base; + pm_info->pm_info_size = sizeof(*pm_info); + pm_info->mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset); + mmdc_offset_array = imx6sl_mmdc_io_offset; + pm_info->mmdc_base = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + pm_info->ccm_base = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + pm_info->anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + pm_info->iomuxc_base = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + pm_info->l2_base = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + /* Only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < pm_info->mmdc_io_num; i++) + pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + /* calculate the wfi code size */ + wfi_code_size = (&mx6sl_lpm_wfi_end -&mx6sl_lpm_wfi_start) *4; + + imx6sl_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*pm_info), + &imx6sl_low_power_idle, wfi_code_size); +#endif + return cpuidle_register(&imx6sl_cpuidle_driver, NULL); } + +static int imx_ldo2p5_dummy_enable(struct regulator_dev *rdev) +{ + ldo2p5_dummy_enable = 1; + return 0; +} + +static int imx_ldo2p5_dummy_disable(struct regulator_dev *rdev) +{ + ldo2p5_dummy_enable = 0; + return 0; +} + +static int imx_ldo2p5_dummy_is_enable(struct regulator_dev *rdev) +{ + return ldo2p5_dummy_enable; +} + +static struct regulator_ops ldo2p5_dummy_ops = { + .enable = imx_ldo2p5_dummy_enable, + .disable = imx_ldo2p5_dummy_disable, + .is_enabled = imx_ldo2p5_dummy_is_enable, +}; + +static struct regulator_desc ldo2p5_dummy_desc = { + .name = "ldo2p5-dummy", + .id = -1, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, + .ops = &ldo2p5_dummy_ops, +}; + +static int ldo2p5_dummy_probe(struct platform_device *pdev) +{ + struct regulator_config config = { }; + int ret; + + config.dev = &pdev->dev; + config.init_data = &ldo2p5_dummy_initdata; + config.of_node = pdev->dev.of_node; + + ldo2p5_dummy_regulator_rdev = regulator_register(&pdev->dev, &ldo2p5_dummy_desc, &config); + if (IS_ERR(ldo2p5_dummy_regulator_rdev)) { + ret = PTR_ERR(ldo2p5_dummy_regulator_rdev); + dev_err(&pdev->dev, "Failed to register dummy ldo2p5 regulator: %d\n", ret); + return ret; + } + return 0; +} + +static const struct of_device_id imx_ldo2p5_dummy_ids[] = { + { .compatible = "fsl,imx6-dummy-ldo2p5", }, + { }, +}; +MODULE_DEVICE_TABLE(ofm, imx_ldo2p5_dummy_ids); + +static struct platform_driver ldo2p5_dummy_driver = { + .probe = ldo2p5_dummy_probe, + .driver = { + .name = "ldo2p5-dummy", + .owner = THIS_MODULE, + .of_match_table = imx_ldo2p5_dummy_ids, + }, +}; + +module_platform_driver(ldo2p5_dummy_driver); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/cpuidle-imx6sll.c linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx6sll.c --- linux-6.1.55/arch/arm/mach-imx/cpuidle-imx6sll.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx6sll.c 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,277 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +#define MAX_MMDC_IO_NUM 14 + +#define PMU_LOW_PWR_CTRL 0x270 +#define XTALOSC24M_OSC_CONFIG0 0x2a0 +#define XTALOSC24M_OSC_CONFIG1 0x2b0 +#define XTALOSC24M_OSC_CONFIG2 0x2c0 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +extern unsigned long iram_tlb_phys_addr; +static void __iomem *wfi_iram_base; + +#ifdef CONFIG_CPU_FREQ +static void __iomem *wfi_iram_base_phys; +extern unsigned long mx6sll_lpm_wfi_start asm("mx6sll_lpm_wfi_start"); +extern unsigned long mx6sll_lpm_wfi_end asm("mx6sll_lpm_wfi_end"); +#endif + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx6_cpuidle_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + u32 ttbr; + struct imx6_pm_base mmdc_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base anatop_base; + struct imx6_pm_base src_base; + struct imx6_pm_base l2_base; + u32 saved_diagnostic; /* To save disagnostic register */ + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static const u32 imx6sll_mmdc_io_offset[] __initconst = { + 0x294, 0x298, 0x29c, 0x2a0, /* DQM0, DQM1, RAS, CAS */ + 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ + 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK0, GPR_ADDS */ + 0x2a4, 0x2a8, /* SDCKE0, SDCKE1 */ +}; + +static void (*imx6sll_wfi_in_iram_fn)(void __iomem *iram_vbase); + +#define MX6SLL_POWERDWN_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +static int imx6sll_idle_finish(unsigned long val) +{ + if (psci_ops.cpu_suspend) + psci_ops.cpu_suspend(MX6SLL_POWERDWN_IDLE_PARAM, + __pa(cpu_resume)); + else + imx6sll_wfi_in_iram_fn(wfi_iram_base); + + return 0; +} + +static int imx6sll_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int mode = get_bus_freq_mode(); + + imx6_set_lpm(WAIT_UNCLOCKED); + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + index = 1; + cpu_do_idle(); + } else { + imx_gpc_switch_pupscr_clk(true); + /* Need to notify there is a cpu pm operation. */ + cpu_pm_enter(); + cpu_cluster_pm_enter(); + + cpu_suspend(0, imx6sll_idle_finish); + + cpu_cluster_pm_exit(); + cpu_pm_exit(); + imx6_enable_rbc(false); + + imx_gpc_switch_pupscr_clk(false); + } + + imx6_set_lpm(WAIT_CLOCKED); + + return index; +} + +static struct cpuidle_driver imx6sll_cpuidle_driver = { + .name = "imx6sll_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .enter = imx6sll_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + /* + * RBC 130us + ARM gating 43us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 700us. + */ + .exit_latency = 700, + .target_residency = 1000, + .enter = imx6sll_enter_wait, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + } + }, + .state_count = 3, + .safe_state_index = 0, +}; + +int __init imx6sll_cpuidle_init(void) +{ + void __iomem *anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + u32 val; +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *cpuidle_pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(v7_cpu_resume); + cpuidle_pm_info->mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset); + mmdc_offset_array = imx6sll_mmdc_io_offset; + + cpuidle_pm_info->mmdc_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + cpuidle_pm_info->mmdc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + cpuidle_pm_info->iomuxc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); + + cpuidle_pm_info->l2_base.pbase = MX6Q_L2_BASE_ADDR; + cpuidle_pm_info->l2_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + /* Only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < cpuidle_pm_info->mmdc_io_num; i++) + cpuidle_pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + wfi_code_size = (&mx6sll_lpm_wfi_end -&mx6sll_lpm_wfi_start) *4; + + imx6sll_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6sll_low_power_idle, wfi_code_size); +#endif + + imx6_set_int_mem_clk_lpm(true); + + /* + * enable RC-OSC here, as it needs at least 4ms for RC-OSC to + * be stable, low power idle flow can NOT endure this big + * latency, so we make RC-OSC self-tuning enabled here. + */ + val = readl_relaxed(anatop_base + PMU_LOW_PWR_CTRL); + val |= 0x1; + writel_relaxed(val, anatop_base + PMU_LOW_PWR_CTRL); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait 4ms according to hardware design */ + msleep(4); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + + return cpuidle_register(&imx6sll_cpuidle_driver, NULL); +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/cpuidle-imx6sx.c linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx6sx.c --- linux-6.1.55/arch/arm/mach-imx/cpuidle-imx6sx.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx6sx.c 2024-06-19 12:33:58.128189625 +0200 @@ -1,20 +1,97 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. */ +#include #include #include +#include +#include +#include #include +#include #include #include +#include +#include +#include #include +#include + +#include #include "common.h" #include "cpuidle.h" #include "hardware.h" -static int imx6sx_idle_finish(unsigned long val) +#define MX6_MAX_MMDC_IO_NUM 19 + +#define PMU_LOW_PWR_CTRL 0x270 +#define XTALOSC24M_OSC_CONFIG0 0x2a0 +#define XTALOSC24M_OSC_CONFIG1 0x2b0 +#define XTALOSC24M_OSC_CONFIG2 0x2c0 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +extern unsigned long iram_tlb_phys_addr; + +static void __iomem *wfi_iram_base; +#ifdef CONFIG_CPU_FREQ +static void __iomem *wfi_iram_base_phys; +extern unsigned long mx6sx_lpm_wfi_start asm("mx6sx_lpm_wfi_start"); +extern unsigned long mx6sx_lpm_wfi_end asm("mx6sx_lpm_wfi_end"); +#endif + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +static const u32 imx6sx_mmdc_io_offset[] __initconst = { + 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ + 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ + 0x60c, 0x610, 0x61c, 0x620, /* B0DS ~ B3DS */ + 0x5f8, 0x608, 0x310, 0x314, /* CTL, MODE, SODT0, SODT1 */ + 0x300, 0x2fc, 0x32c, /* CAS, RAS, SDCLK_0 */ +}; + +struct imx6_cpuidle_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + u32 ttbr; + struct imx6_pm_base mmdc_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base l2_base; + struct imx6_pm_base anatop_base; + struct imx6_pm_base src_base; + struct imx6_pm_base sema4_base; + u32 saved_diagnostic; /* To save disagnostic register */ + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static void (*imx6sx_wfi_in_iram_fn)(void __iomem *iram_vbase); + +#define MX6SX_POWERDWN_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +static int imx6_idle_finish(unsigned long val) { /* * for Cortex-A7 which has an internal L2 @@ -25,7 +102,11 @@ * just call flush_cache_all() is fine. */ flush_cache_all(); - cpu_do_idle(); + if (psci_ops.cpu_suspend) + psci_ops.cpu_suspend(MX6SX_POWERDWN_IDLE_PARAM, + __pa(cpu_resume)); + else + imx6sx_wfi_in_iram_fn(wfi_iram_base); return 0; } @@ -33,29 +114,22 @@ static int imx6sx_enter_wait(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - imx6_set_lpm(WAIT_UNCLOCKED); + int mode = get_bus_freq_mode(); - switch (index) { - case 1: + imx6_set_lpm(WAIT_UNCLOCKED); + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + index = 1; cpu_do_idle(); - break; - case 2: - imx6_enable_rbc(true); - imx_gpc_set_arm_power_in_lpm(true); - imx_set_cpu_jump(0, v7_cpu_resume); - /* Need to notify there is a cpu pm operation. */ - cpu_pm_enter(); - cpu_cluster_pm_enter(); - - cpu_suspend(0, imx6sx_idle_finish); - - cpu_cluster_pm_exit(); - cpu_pm_exit(); - imx_gpc_set_arm_power_in_lpm(false); - imx6_enable_rbc(false); - break; - default: - break; + } else { + /* Need to notify there is a cpu pm operation. */ + cpu_pm_enter(); + cpu_cluster_pm_enter(); + + cpu_suspend(0, imx6_idle_finish); + + cpu_cluster_pm_exit(); + cpu_pm_exit(); + imx6_enable_rbc(false); } imx6_set_lpm(WAIT_CLOCKED); @@ -69,25 +143,23 @@ .states = { /* WFI */ ARM_CPUIDLE_WFI_STATE, - /* WAIT */ + /* WAIT MODE */ { .exit_latency = 50, .target_residency = 75, - .flags = CPUIDLE_FLAG_TIMER_STOP, .enter = imx6sx_enter_wait, .name = "WAIT", .desc = "Clock off", }, - /* WAIT + ARM power off */ + /* LOW POWER IDLE */ { /* - * ARM gating 31us * 5 + RBC clear 65us - * and some margin for SW execution, here set it - * to 300us. + * RBC 130us + ARM gating 93us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 800us. */ - .exit_latency = 300, - .target_residency = 500, - .flags = CPUIDLE_FLAG_TIMER_STOP, + .exit_latency = 800, + .target_residency = 1000, .enter = imx6sx_enter_wait, .name = "LOW-POWER-IDLE", .desc = "ARM power off", @@ -99,17 +171,119 @@ int __init imx6sx_cpuidle_init(void) { + void __iomem *anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + u32 val; +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *cpuidle_pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(v7_cpu_resume); + cpuidle_pm_info->mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset); + mmdc_offset_array = imx6sx_mmdc_io_offset; + + cpuidle_pm_info->mmdc_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + cpuidle_pm_info->mmdc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + cpuidle_pm_info->iomuxc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + + cpuidle_pm_info->l2_base.pbase = MX6Q_L2_BASE_ADDR; + cpuidle_pm_info->l2_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); + + cpuidle_pm_info->sema4_base.pbase = MX6Q_SEMA4_BASE_ADDR; + cpuidle_pm_info->sema4_base.vbase = + (void __iomem *)IMX_IO_P2V(MX6Q_SEMA4_BASE_ADDR); + + /* only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < cpuidle_pm_info->mmdc_io_num; i++) + cpuidle_pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + /* code size should include cpuidle_pm_info size */ + wfi_code_size = (&mx6sx_lpm_wfi_end -&mx6sx_lpm_wfi_start) *4 + sizeof(*cpuidle_pm_info); + imx6sx_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6sx_low_power_idle, wfi_code_size); +#endif + imx6_set_int_mem_clk_lpm(true); - imx6_enable_rbc(false); - imx_gpc_set_l2_mem_power_in_lpm(false); - /* - * set ARM power up/down timing to the fastest, - * sw2iso and sw can be set to one 32K cycle = 31us - * except for power up sw2iso which need to be - * larger than LDO ramp up time. - */ - imx_gpc_set_arm_power_up_timing(cpu_is_imx6sx() ? 0xf : 0x2, 1); - imx_gpc_set_arm_power_down_timing(1, 1); + + if (imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) { + /* + * enable RC-OSC here, as it needs at least 4ms for RC-OSC to + * be stable, low power idle flow can NOT endure this big + * latency, so we make RC-OSC self-tuning enabled here. + */ + val = readl_relaxed(anatop_base + PMU_LOW_PWR_CTRL); + val |= 0x1; + writel_relaxed(val, anatop_base + PMU_LOW_PWR_CTRL); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait 4ms according to hardware design */ + msleep(4); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG1); + } return cpuidle_register(&imx6sx_cpuidle_driver, NULL); } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/cpuidle-imx6ul.c linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx6ul.c --- linux-6.1.55/arch/arm/mach-imx/cpuidle-imx6ul.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx6ul.c 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,327 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +#define MAX_MMDC_IO_NUM 14 + +#define PMU_LOW_PWR_CTRL 0x270 +#define XTALOSC24M_OSC_CONFIG0 0x2a0 +#define XTALOSC24M_OSC_CONFIG1 0x2b0 +#define XTALOSC24M_OSC_CONFIG2 0x2c0 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +extern unsigned long iram_tlb_phys_addr; +static void __iomem *wfi_iram_base; + +#ifdef CONFIG_CPU_FREQ +static void __iomem *wfi_iram_base_phys; +extern unsigned long mx6ul_lpm_wfi_start asm("mx6ul_lpm_wfi_start"); +extern unsigned long mx6ul_lpm_wfi_end asm("mx6ul_lpm_wfi_end"); +extern unsigned long mx6ull_lpm_wfi_start asm("mx6ull_lpm_wfi_start"); +extern unsigned long mx6ull_lpm_wfi_end asm("mx6ull_lpm_wfi_end"); +#endif + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx6_cpuidle_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + u32 ttbr; + struct imx6_pm_base mmdc_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base anatop_base; + struct imx6_pm_base src_base; + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static const u32 imx6ul_mmdc_io_offset[] __initconst = { + 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ + 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ + 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */ + 0x494, 0x4b0, /* MODE_CTL, MODE, */ +}; + +static void (*imx6ul_wfi_in_iram_fn)(void __iomem *iram_vbase); + +#define MX6UL_POWERDWN_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +static int imx6ul_idle_finish(unsigned long val) +{ + if (psci_ops.cpu_suspend) + psci_ops.cpu_suspend(MX6UL_POWERDWN_IDLE_PARAM, + __pa(cpu_resume)); + else + imx6ul_wfi_in_iram_fn(wfi_iram_base); + + return 0; +} + +static int imx6ul_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int mode = get_bus_freq_mode(); + + imx6_set_lpm(WAIT_UNCLOCKED); + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + cpu_do_idle(); + index = 1; + } else { + /* + * i.MX6UL TO1.0 ARM power up uses IPG/2048 as clock source, + * from TO1.1, PGC_CPU_PUPSCR bit [5] is re-defined to switch + * clock to IPG/32, enable this bit to speed up the ARM power + * up process in low power idle case. + */ + if (cpu_is_imx6ul() && imx_get_soc_revision() > + IMX_CHIP_REVISION_1_0) + imx_gpc_switch_pupscr_clk(true); + /* Need to notify there is a cpu pm operation. */ + cpu_pm_enter(); + cpu_cluster_pm_enter(); + + cpu_suspend(0, imx6ul_idle_finish); + + cpu_cluster_pm_exit(); + cpu_pm_exit(); + imx6_enable_rbc(false); + + if (cpu_is_imx6ul() && imx_get_soc_revision() > + IMX_CHIP_REVISION_1_0) + imx_gpc_switch_pupscr_clk(false); + } + + imx6_set_lpm(WAIT_CLOCKED); + + return index; +} + +static struct cpuidle_driver imx6ul_cpuidle_driver_v2 = { + .name = "imx6ul_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .enter = imx6ul_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + /* + * RBC 130us + ARM gating 43us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 700us. + */ + .exit_latency = 700, + .target_residency = 1000, + .enter = imx6ul_enter_wait, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + } + }, + .state_count = 3, + .safe_state_index = 0, +}; + +static struct cpuidle_driver imx6ul_cpuidle_driver = { + .name = "imx6ul_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .enter = imx6ul_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + /* + * RBC 130us + ARM gating 1370us + RBC clear 65us + * + PLL2 relock 450us and some margin, here set + * it to 2100us. + */ + .exit_latency = 2100, + .target_residency = 2500, + .enter = imx6ul_enter_wait, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + } + }, + .state_count = 3, + .safe_state_index = 0, +}; + +int __init imx6ul_cpuidle_init(void) +{ + void __iomem *anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + u32 val; +#ifdef CONFIG_CPU_FREQ + struct imx6_cpuidle_pm_info *cpuidle_pm_info; + int i; + const u32 *mmdc_offset_array; + u32 wfi_code_size; + + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(v7_cpu_resume); + cpuidle_pm_info->mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset); + mmdc_offset_array = imx6ul_mmdc_io_offset; + + cpuidle_pm_info->mmdc_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + cpuidle_pm_info->mmdc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + cpuidle_pm_info->iomuxc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); + + /* Only save mmdc io offset, settings will be saved in asm code */ + for (i = 0; i < cpuidle_pm_info->mmdc_io_num; i++) + cpuidle_pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i]; + + /* calculate the wfi code size */ + if (cpu_is_imx6ul()) { + wfi_code_size = (&mx6ul_lpm_wfi_end -&mx6ul_lpm_wfi_start) *4; + + imx6ul_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6ul_low_power_idle, wfi_code_size); + } else { + wfi_code_size = (&mx6ull_lpm_wfi_end -&mx6ull_lpm_wfi_start) *4; + + imx6ul_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info), + &imx6ull_low_power_idle, wfi_code_size); + } +#endif + + imx6_set_int_mem_clk_lpm(true); + + /* + * enable RC-OSC here, as it needs at least 4ms for RC-OSC to + * be stable, low power idle flow can NOT endure this big + * latency, so we make RC-OSC self-tuning enabled here. + */ + val = readl_relaxed(anatop_base + PMU_LOW_PWR_CTRL); + val |= 0x1; + writel_relaxed(val, anatop_base + PMU_LOW_PWR_CTRL); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait 4ms according to hardware design */ + msleep(4); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + + /* ARM power up time is reduced since TO1.1 */ + if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_0) + return cpuidle_register(&imx6ul_cpuidle_driver_v2, NULL); + else + return cpuidle_register(&imx6ul_cpuidle_driver, NULL); +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/cpuidle-imx7d.c linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx7d.c --- linux-6.1.55/arch/arm/mach-imx/cpuidle-imx7d.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx7d.c 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,396 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +#define XTALOSC24M_OSC_CONFIG0 0x10 +#define XTALOSC24M_OSC_CONFIG1 0x20 +#define XTALOSC24M_OSC_CONFIG2 0x30 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 + +#define XTALOSC_CTRL_24M 0x0 +#define XTALOSC_CTRL_24M_RC_OSC_EN_SHIFT 13 +#define REG_SET 0x4 + +static void __iomem *wfi_iram_base; +static void __iomem *wfi_iram_base_phys; +extern unsigned long iram_tlb_phys_addr; + +struct imx7_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx7_cpuidle_pm_info { + phys_addr_t vbase; /* The virtual address of pm_info. */ + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; + u32 ttbr; + u32 num_online_cpus; + u32 num_lpi_cpus; + atomic_t val; + atomic_t flag0; + atomic_t flag1; + struct imx7_pm_base ddrc_base; + struct imx7_pm_base ccm_base; + struct imx7_pm_base anatop_base; + struct imx7_pm_base src_base; + struct imx7_pm_base iomuxc_gpr_base; + struct imx7_pm_base gpc_base; + struct imx7_pm_base gic_dist_base; +} __aligned(8); + +static atomic_t master_lpi = ATOMIC_INIT(0); +static atomic_t master_wait = ATOMIC_INIT(0); + +static void (*imx7d_wfi_in_iram_fn)(void __iomem *iram_vbase); +static struct imx7_cpuidle_pm_info *cpuidle_pm_info; + +#define MX7D_POWERDWN_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +#define MX7D_STANDBY_IDLE_PARAM \ + ((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_STANDBY << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +/* Mapped for the kernel, unlike cpuidle_pm_info->gic_dist_base.vbase */ +static void __iomem *imx7d_cpuidle_gic_base; + +static void imx_pen_lock(int cpu) +{ + if (cpu == 0) { + atomic_set(&cpuidle_pm_info->flag0, 1); + dsb(); + atomic_set(&cpuidle_pm_info->val, cpu); + do { + dsb(); + } while (atomic_read(&cpuidle_pm_info->flag1) == 1 + && atomic_read(&cpuidle_pm_info->val) == cpu) + ; + } else { + atomic_set(&cpuidle_pm_info->flag1, 1); + dsb(); + atomic_set(&cpuidle_pm_info->val, cpu); + do { + dsb(); + } while (atomic_read(&cpuidle_pm_info->flag0) == 1 + && atomic_read(&cpuidle_pm_info->val) == cpu) + ; + } +} + +static void imx_pen_unlock(int cpu) +{ + dsb(); + if (cpu == 0) + atomic_set(&cpuidle_pm_info->flag0, 0); + else + atomic_set(&cpuidle_pm_info->flag1, 0); +} + +static int imx7d_idle_finish(unsigned long val) +{ + if (psci_ops.cpu_suspend) + psci_ops.cpu_suspend(MX7D_POWERDWN_IDLE_PARAM, __pa(cpu_resume)); + else + imx7d_wfi_in_iram_fn(wfi_iram_base); + + return 0; +} + +static bool imx7d_gic_sgis_pending(void) +{ + void __iomem *sgip_base = imx7d_cpuidle_gic_base + 0x1f20; + + return (readl_relaxed(sgip_base + 0x0) | + readl_relaxed(sgip_base + 0x4) | + readl_relaxed(sgip_base + 0x8) | + readl_relaxed(sgip_base + 0xc)); +} + +static DEFINE_SPINLOCK(psci_lock); +static int imx7d_enter_low_power_idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int mode = get_bus_freq_mode(); + + + if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) { + index = 1; + if (atomic_inc_return(&master_wait) == num_online_cpus()) + imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED); + + ct_idle_enter(); + cpu_do_idle(); + ct_idle_exit(); + + atomic_dec(&master_wait); + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + } else { + if (psci_ops.cpu_suspend) { + cpu_pm_enter(); + spin_lock(&psci_lock); + if (atomic_inc_return(&master_lpi) == num_online_cpus()) { + if (imx7d_gic_sgis_pending()) { + atomic_dec(&master_lpi); + index = -1; + goto psci_skip_lpi_flow; + } + + imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED); + imx_gpcv2_set_cpu_power_gate_in_idle(true); + + cpu_cluster_pm_enter(); + } + spin_unlock(&psci_lock); + + ct_idle_enter(); + cpu_suspend(0, imx7d_idle_finish); + ct_idle_exit(); + + spin_lock(&psci_lock); + if (atomic_read(&master_lpi) == num_online_cpus()) { + cpu_cluster_pm_exit(); + imx_gpcv2_set_cpu_power_gate_in_idle(false); + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + } + + atomic_dec(&master_lpi); +psci_skip_lpi_flow: + spin_unlock(&psci_lock); + cpu_pm_exit(); + } else { + imx_pen_lock(dev->cpu); + cpuidle_pm_info->num_online_cpus = num_online_cpus(); + ++cpuidle_pm_info->num_lpi_cpus; + cpu_pm_enter(); + if (cpuidle_pm_info->num_lpi_cpus == + cpuidle_pm_info->num_online_cpus) { + /* + * GPC will not wake on SGIs so check for them + * manually here. At this point we know the other cpu + * is in wfi or waiting for the lock and can't send + * any additional IPIs. + */ + if (imx7d_gic_sgis_pending()) { + index = -1; + goto skip_lpi_flow; + } + imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED); + imx_gpcv2_set_cpu_power_gate_in_idle(true); + cpu_cluster_pm_enter(); + } else { + imx_set_cpu_jump(dev->cpu, ca7_cpu_resume); + } + + ct_idle_enter(); + cpu_suspend(0, imx7d_idle_finish); + ct_idle_exit(); + + if (cpuidle_pm_info->num_lpi_cpus == + cpuidle_pm_info->num_online_cpus) { + cpu_cluster_pm_exit(); + imx_gpcv2_set_cpu_power_gate_in_idle(false); + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + } + +skip_lpi_flow: + cpu_pm_exit(); + --cpuidle_pm_info->num_lpi_cpus; + imx_pen_unlock(dev->cpu); + } + } + + return index; +} + +static struct cpuidle_driver imx7d_cpuidle_driver = { + .name = "imx7d_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT MODE */ + { + .exit_latency = 50, + .target_residency = 75, + .flags = CPUIDLE_FLAG_TIMER_STOP | CPUIDLE_FLAG_RCU_IDLE, + .enter = imx7d_enter_low_power_idle, + .name = "WAIT", + .desc = "Clock off", + }, + /* LOW POWER IDLE */ + { + .exit_latency = 12000, + .target_residency = 22000, + .flags = CPUIDLE_FLAG_TIMER_STOP | CPUIDLE_FLAG_RCU_IDLE, + .enter = imx7d_enter_low_power_idle, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + }, + }, + .state_count = 3, + .safe_state_index = 0, +}; + +int imx7d_enable_rcosc(void) +{ + void __iomem *anatop_base = + (void __iomem *)IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR); + u32 val; + + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + /* set RC-OSC freq and turn it on */ + writel_relaxed(0x1 << XTALOSC_CTRL_24M_RC_OSC_EN_SHIFT, + anatop_base + XTALOSC_CTRL_24M + REG_SET); + /* + * config RC-OSC freq + * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0; + * osc_prog = 0xa7; + */ + writel_relaxed( + 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT | + 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT | + 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set count_trg = 0x2dc */ + writel_relaxed( + 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT | + 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT, + anatop_base + XTALOSC24M_OSC_CONFIG1); + /* wait at least 4ms according to hardware design */ + mdelay(6); + /* + * now add some hysteresis, hyst_plus=3, hyst_minus=3 + * (the minimum hysteresis that looks good is 2) + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0); + val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK << + XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)); + val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) | + (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0); + /* set the count_1m_trg = 0x2d7 */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2); + val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK << + XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT); + val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT; + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2); + /* + * hardware design require to write XTALOSC24M_OSC_CONFIG0 or + * XTALOSC24M_OSC_CONFIG1 to + * make XTALOSC24M_OSC_CONFIG2 write work + */ + val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1); + writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG1); + + return 0; +} + +int __init imx7d_cpuidle_init(void) +{ + wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + + MX7_CPUIDLE_OCRAM_ADDR_OFFSET); + + /* Make sure wfi_iram_base is 8 byte aligned. */ + if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1)) + wfi_iram_base_phys += FNCPY_ALIGN - + ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN)); + + wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys); + + cpuidle_pm_info = wfi_iram_base; + cpuidle_pm_info->vbase = (phys_addr_t) wfi_iram_base; + cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys; + cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info); + cpuidle_pm_info->resume_addr = virt_to_phys(ca7_cpu_resume); + cpuidle_pm_info->num_online_cpus = num_online_cpus(); + + cpuidle_pm_info->ddrc_base.pbase = MX7D_DDRC_BASE_ADDR; + cpuidle_pm_info->ddrc_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_DDRC_BASE_ADDR); + + cpuidle_pm_info->ccm_base.pbase = MX7D_CCM_BASE_ADDR; + cpuidle_pm_info->ccm_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_CCM_BASE_ADDR); + + cpuidle_pm_info->anatop_base.pbase = MX7D_ANATOP_BASE_ADDR; + cpuidle_pm_info->anatop_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR); + + cpuidle_pm_info->src_base.pbase = MX7D_SRC_BASE_ADDR; + cpuidle_pm_info->src_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_SRC_BASE_ADDR); + + cpuidle_pm_info->iomuxc_gpr_base.pbase = MX7D_IOMUXC_GPR_BASE_ADDR; + cpuidle_pm_info->iomuxc_gpr_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR); + + cpuidle_pm_info->gpc_base.pbase = MX7D_GPC_BASE_ADDR; + cpuidle_pm_info->gpc_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_GPC_BASE_ADDR); + + cpuidle_pm_info->gic_dist_base.pbase = MX7D_GIC_BASE_ADDR; + cpuidle_pm_info->gic_dist_base.vbase = + (void __iomem *)IMX_IO_P2V(MX7D_GIC_BASE_ADDR); + + imx7d_cpuidle_gic_base = ioremap(MX7D_GIC_BASE_ADDR, MX7D_GIC_SIZE); + + imx7d_enable_rcosc(); + + /* code size should include cpuidle_pm_info size */ + if (!psci_ops.cpu_suspend) { + imx7d_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + + sizeof(*cpuidle_pm_info), + &imx7d_low_power_idle, + MX7_CPUIDLE_OCRAM_SIZE - sizeof(*cpuidle_pm_info)); + } + + return cpuidle_register(&imx7d_cpuidle_driver, NULL); +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/cpuidle-imx7ulp.c linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx7ulp.c --- linux-6.1.55/arch/arm/mach-imx/cpuidle-imx7ulp.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/cpuidle-imx7ulp.c 2024-06-19 12:33:58.128189625 +0200 @@ -15,10 +15,18 @@ static int imx7ulp_enter_wait(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - if (index == 1) + u32 mode; + + if (index == 1) { imx7ulp_set_lpm(ULP_PM_WAIT); - else - imx7ulp_set_lpm(ULP_PM_STOP); + } else { + mode = imx7ulp_get_mode(); + + if (mode == 3) + imx7ulp_set_lpm(ULP_PM_WAIT); + else + imx7ulp_set_lpm(ULP_PM_STOP); + } cpu_do_idle(); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/ddr3_freq_imx6.S linux-imx-phytec/arch/arm/mach-imx/ddr3_freq_imx6.S --- linux-6.1.55/arch/arm/mach-imx/ddr3_freq_imx6.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/ddr3_freq_imx6.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,1103 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "hardware.h" + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MDCF0 0x0c +#define MMDC0_MDCF1 0x10 +#define MMDC0_MDMISC 0x18 +#define MMDC0_MDSCR 0x1c +#define MMDC0_MAARCR 0x400 +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 +#define MMDC0_MPZQHWCTRL 0x800 +#define MMDC1_MPZQHWCTRL 0x4800 +#define MMDC0_MPODTCTRL 0x818 +#define MMDC1_MPODTCTRL 0x4818 +#define MMDC0_MPDGCTRL0 0x83c +#define MMDC1_MPDGCTRL0 0x483c +#define MMDC0_MPMUR0 0x8b8 +#define MMDC1_MPMUR0 0x48b8 + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 +#define PL310_AUX_CTRL 0x104 +#define PL310_DCACHE_LOCKDOWN_BASE 0x900 +#define PL310_AUX_16WAY_BIT 0x10000 +#define PL310_LOCKDOWN_NBREGS 8 +#define PL310_LOCKDOWN_SZREG 4 +#define PL310_8WAYS_MASK 0x00FF +#define PL310_16WAYS_UPPERMASK 0xFF00 + +#define IMX6QP_REVISION_ID 0x630100 +#define ANADIG_DIGPROG 0x260 + +.extern iram_tlb_phys_addr + +.globl mx6_ddr3_freq_change_start +.globl mx6_ddr3_freq_change_end + + .align 3 + + .macro is_mx6qp + + /* check if the SOC is i.MX6QP */ + ldr r0, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r1, [r0, #ANADIG_DIGPROG] + ldr r2, =IMX6QP_REVISION_ID + cmp r1, r2 + + .endm + + .macro switch_to_528MHz + + /* check if periph_clk_sel is already set */ + ldr r0, [r6, #CCM_CBCDR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq set_ahb_podf_before_switch + + /* change periph_clk to be sourced from pll3_clk. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(3 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 20) + str r0, [r6, #CCM_CBCDR] + + /* + * set the AHB dividers before the switch, + * don't change AXI clock divider, + * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #0xd00 + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update528: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update528 + + /* now switch periph_clk to pll3_main_clk. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch3: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch3 + + b switch_pre_periph_clk_528 + +set_ahb_podf_before_switch: + /* + * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #0xd00 + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update528_1: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update528_1 + +switch_pre_periph_clk_528: + + /* now switch pre_periph_clk to PLL2_528MHz. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0xc << 16) + str r0, [r6, #CCM_CBCMR] + + /* now switch periph_clk back. */ + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch4: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch4 + + .endm + + .macro switch_to_400MHz + + /* check if periph_clk_sel is already set. */ + ldr r0, [r6, #CCM_CBCDR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq set_ahb_podf_before_switch1 + + /* change periph_clk to be sourced from pll3_clk. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(3 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 24) + str r0, [r6, #CCM_CBCDR] + + /* now switch periph_clk to pll3_main_clk. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch5: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch5 + + b switch_pre_periph_clk_400 + +set_ahb_podf_before_switch1: + /* + * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(0x9 << 8) + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update400_1: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update400_1 + +switch_pre_periph_clk_400: + + /* now switch pre_periph_clk to PFD_400MHz. */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0xc << 16) + orr r0, r0, #(0x4 << 16) + str r0, [r6, #CCM_CBCMR] + + /* now switch periph_clk back. */ + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch6: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch6 + + /* + * change AHB divider so that we are at 400/3=133MHz. + * don't change AXI clock divider. + * set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(0x9 << 8) + orr r0, r0, #(1 << 16) + str r0, [r6, #CCM_CBCDR] + +wait_div_update400_2: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update400_2 + + .endm + + .macro switch_to_50MHz + + /* check if periph_clk_sel is already set. */ + ldr r0, [r6, #CCM_CBCDR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq switch_pre_periph_clk_50 + + /* + * set the periph_clk to be sourced from PLL2_PFD_200M + * change periph_clk to be sourced from pll3_clk. + * ensure PLL3 is the source and set the divider to 1. + */ + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0x3 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 24) + str r0, [r6, #CCM_CBCDR] + + /* now switch periph_clk to pll3_main_clk. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch_50: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch_50 + +switch_pre_periph_clk_50: + + /* now switch pre_periph_clk to PFD_200MHz. */ + ldr r0, [r6, #CCM_CBCMR] + orr r0, r0, #(0xc << 16) + str r0, [r6, #CCM_CBCMR] + + /* + * set the MMDC_DIV=4, AXI_DIV = 4, AHB_DIV=8, + */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(0x18 << 16) + orr r0, r0, #(0x3 << 16) + + /* + * if changing AHB divider remember to change + * the IPGPER divider too below. + */ + orr r0, r0, #0x1d00 + str r0, [r6, #CCM_CBCDR] + +wait_div_update_50: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update_50 + + /* now switch periph_clk back. */ + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch2: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch2 + + .endm + + .macro switch_to_24MHz + /* + * change the freq now try setting DDR to 24MHz. + * source it from the periph_clk2 ensure the + * periph_clk2 is sourced from 24MHz and the + * divider is 1. + */ + + ldr r0, [r6, #CCM_CBCMR] + bic r0, r0, #(0x3 << 12) + orr r0, r0, #(1 << 12) + str r0, [r6, #CCM_CBCMR] + + ldr r0, [r6, #CCM_CBCDR] + bic r0, r0, #(0x38 << 24) + str r0, [r6, #CCM_CBCDR] + + /* now switch periph_clk to 24MHz. */ + ldr r0, [r6, #CCM_CBCDR] + orr r0, r0, #(1 << 25) + str r0, [r6, #CCM_CBCDR] + +periph_clk_switch1: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne periph_clk_switch1 + + /* change all the dividers to 1. */ + ldr r0, [r6, #CCM_CBCDR] + ldr r2, =0x3f1f00 + bic r0, r0, r2 + orr r0, r0, #(1 << 8) + str r0, [r6, #CCM_CBCDR] + + /* Wait for the divider to change. */ +wait_div_update: + ldr r0, [r6, #CCM_CDHIPR] + cmp r0, #0 + bne wait_div_update + + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + /* disable d-cache */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + dsb + isb + + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + .endm + +/* + * mx6_ddr3_freq_change + * + * idle the processor (eg, wait for interrupt). + * make sure DDR is in self-refresh. + * IRQs are already disabled. + */ +ENTRY(mx6_ddr3_freq_change) + +mx6_ddr3_freq_change_start: + stmfd sp!, {r4-r12} + + /* + * r5 -> mmdc_base + * r6 -> ccm_base + * r7 -> iomux_base + * r12 -> l2_base + */ + mov r4, r0 + mov r8, r1 + mov r9, r2 + mov r11, r3 + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* + * Need to flush and disable L1 before + * disabling L2, we need data to + * coherent. Flushing L1 pushes + * everyhting to L2. We sync L2 later, but + * it can still have dirty lines. + * While exiting, we need to enable L2 first + * and then L1. + */ + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* + * Make sure the L2 buffers are drained. + * Sync operation on L2 drains the buffers. + */ + ldr r12, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r1, [r12, #L2_CACHE_SYNC] + cmp r1, #0x0 + bne wait_for_l2_to_idle + + mov r1, #0x0 + str r1, [r12, #L2_CACHE_SYNC] + + dsb + isb + + ldr r1, [r12, #PL310_AUX_CTRL] + tst r1, #PL310_AUX_16WAY_BIT + mov r1, #PL310_8WAYS_MASK + orrne r1, #PL310_16WAYS_UPPERMASK + mov r6, #PL310_LOCKDOWN_NBREGS + add r5, r12, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r1, [r5], #PL310_LOCKDOWN_SZREG + str r1, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + + /* Now switch the TTBR. */ + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + + ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + ldr r6, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r7, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR) + + /* Read the Original MU delay value */ + ldr r1, [r5, #MMDC0_MPMUR0] + mov r10, r1, lsr #16 + ldr r1, =0x3ff + and r10, r10, r1 + + /* disable automatic power saving. */ + ldr r0, [r5, #MMDC0_MAPSR] + orr r0, r0, #0x01 + str r0, [r5, #MMDC0_MAPSR] + + /* disable MMDC power down timer. */ + ldr r0, [r5, #MMDC0_MDPDC] + bic r0, r0, #(0xff << 8) + str r0, [r5, #MMDC0_MDPDC] + + /* delay for a while */ + ldr r1, =4 +delay1: + ldr r2, =0 +cont1: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont1 + sub r1, r1, #1 + cmp r1, #0 + bgt delay1 + + /* set CON_REG */ + ldr r0, =0x8000 + str r0, [r5, #MMDC0_MDSCR] +poll_conreq_set_1: + ldr r0, [r5, #MMDC0_MDSCR] + and r0, r0, #(0x4 << 12) + cmp r0, #(0x4 << 12) + bne poll_conreq_set_1 + + /* + * if requested frequency is great than + * 300MHz, skip setting bypass adopt mode. + */ + ldr r1, =300000000 + cmp r4, r1 + bge 1f + + is_mx6qp + bne 1f + /* Switch to adopt mode, set MMDC0_MAARCR bit25~26 to 2b'01 */ + ldr r0, [r5, #MMDC0_MAARCR] + bic r0, r0, #(0x3 << 25) + orr r0, #(0x01 << 25) + str r0 , [r5, #MMDC0_MAARCR] +1: + ldr r0, =0x00008050 + str r0, [r5, #MMDC0_MDSCR] + ldr r0, =0x00008058 + str r0, [r5, #MMDC0_MDSCR] + + /* + * if requested frequency is greater than + * 300MHz go to DLL on mode. + */ + ldr r1, =300000000 + cmp r4, r1 + bge dll_on_mode + +dll_off_mode: + + /* if DLL is currently on, turn it off. */ + cmp r9, #1 + beq continue_dll_off_1 + + ldr r0, =0x00018031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00018039 + str r0, [r5, #MMDC0_MDSCR] + + ldr r1, =10 +delay1a: + ldr r2, =0 +cont1a: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont1a + sub r1, r1, #1 + cmp r1, #0 + bgt delay1a + +continue_dll_off_1: + /* set DVFS - enter self refresh mode */ + ldr r0, [r5, #MMDC0_MAPSR] + orr r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + + /* de-assert con_req */ + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] + +poll_dvfs_set_1: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + bne poll_dvfs_set_1 + + ldr r1, =24000000 + cmp r4, r1 + beq switch_freq_24 + + switch_to_50MHz + b continue_dll_off_2 + +switch_freq_24: + switch_to_24MHz + +continue_dll_off_2: + + /* set SBS - block ddr accesses */ + ldr r0, [r5, #MMDC0_MADPCR0] + orr r0, r0, #(1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + /* clear DVFS - exit from self refresh mode */ + ldr r0, [r5, #MMDC0_MAPSR] + bic r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq poll_dvfs_clear_1 + + /* if DLL was previously on, continue DLL off routine. */ + cmp r9, #1 + beq continue_dll_off_3 + + ldr r0, =0x00018031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00018039 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x08208030 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x08208038 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00088032 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x0008803A + str r0, [r5, #MMDC0_MDSCR] + + /* delay for a while. */ + ldr r1, =4 +delay_1: + ldr r2, =0 +cont_1: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont_1 + sub r1, r1, #1 + cmp r1, #0 + bgt delay_1 + + ldr r0, [r5, #MMDC0_MDCF0] + bic r0, r0, #0xf + orr r0, r0, #0x3 + str r0, [r5, #MMDC0_MDCF0] + + ldr r0, [r5, #MMDC0_MDCF1] + bic r0, r0, #0x7 + orr r0, r0, #0x4 + str r0, [r5, #MMDC0_MDCF1] + + ldr r0, [r5, #MMDC0_MDMISC] + bic r0, r0, #(0x3 << 16) /* walat = 0x1 */ + orr r0, r0, #(0x1 << 16) + bic r0, r0, #(0x7 << 6) /* ralat = 0x2 */ + orr r0, r0, #(0x2 << 6) + str r0, [r5, #MMDC0_MDMISC] + + /* enable dqs pull down in the IOMUX. */ + ldr r1, [r11] + add r11, r11, #8 + ldr r2, =0x3028 +update_iomux: + ldr r0, [r11, #0x0] + ldr r3, [r7, r0] + bic r3, r3, r2 + orr r3, r3, #(0x3 << 12) + orr r3, r3, #0x28 + str r3, [r7, r0] + add r11, r11, #8 + sub r1, r1, #1 + cmp r1, #0 + bgt update_iomux + + /* ODT disabled. */ + ldr r0, =0x0 + ldr r2, =MMDC0_MPODTCTRL + str r0, [r5, r2] + ldr r2, =MMDC1_MPODTCTRL + str r0, [r5, r2] + + /* DQS gating disabled. */ + ldr r2, =MMDC0_MPDGCTRL0 + ldr r0, [r5, r2] + orr r0, r0, #(1 << 29) + str r0, [r5, r2] + + ldr r2, =MMDC1_MPDGCTRL0 + ldr r0, [r5, r2] + orr r0, r0, #(0x1 << 29) + str r0, [r5, r2] + + /* Add workaround for ERR005778.*/ + /* double the original MU_UNIT_DEL_NUM. */ + lsl r10, r10, #1 + + /* Bypass the automatic MU by setting the mu_byp_en */ + ldr r2, [r5, #MMDC0_MPMUR0] + orr r2, r2, #0x400 + orr r2, r2, r10 + str r2, [r5, #MMDC0_MPMUR0] + ldr r0, =MMDC1_MPMUR0 + str r2, [r5, r0] + + /* Now perform a force measure */ + ldr r0, [r5, #MMDC0_MPMUR0] + orr r0, r0, #0x800 + str r0, [r5, #MMDC0_MPMUR0] + ldr r2, =MMDC1_MPMUR0 + str r0, [r5, r2] + /* Wait for FRC_MSR to clear. */ +1: + ldr r0, [r5, #MMDC0_MPMUR0] + and r0, r0, #0x800 + ldr r1, [r5, r2] + and r1, r1, #0x800 + orr r0, r0, r1 + cmp r0, #0x0 + bne 1b + +continue_dll_off_3: + /* clear SBS - unblock accesses to DDR. */ + ldr r0, [r5, #MMDC0_MADPCR0] + bic r0, r0, #(0x1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] +poll_conreq_clear_1: + ldr r0, [r5, #MMDC0_MDSCR] + and r0, r0, #(0x4 << 12) + cmp r0, #(0x4 << 12) + beq poll_conreq_clear_1 + + b done + +dll_on_mode: + /* assert DVFS - enter self refresh mode. */ + ldr r0, [r5, #MMDC0_MAPSR] + orr r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + + /* de-assert CON_REQ. */ + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] + + /* poll DVFS ack. */ +poll_dvfs_set_2: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + bne poll_dvfs_set_2 + + ldr r1, =528000000 + cmp r4, r1 + beq switch_freq_528 + + switch_to_400MHz + + b continue_dll_on + +switch_freq_528: + switch_to_528MHz + +continue_dll_on: + + /* set SBS step-by-step mode. */ + ldr r0, [r5, #MMDC0_MADPCR0] + orr r0, r0, #( 1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + /* clear DVFS - exit self refresh mode. */ + ldr r0, [r5, #MMDC0_MAPSR] + bic r0, r0, #(1 << 21) + str r0, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_2: + ldr r0, [r5, #MMDC0_MAPSR] + and r0, r0, #(1 << 25) + cmp r0, #(1 << 25) + beq poll_dvfs_clear_2 + + /* if DLL is currently off, turn it back on. */ + cmp r9, #0 + beq update_calibration_only + + /* issue zq calibration command */ + ldr r0, [r5, #MMDC0_MPZQHWCTRL] + orr r0, r0, #0x3 + str r0, [r5, #MMDC0_MPZQHWCTRL] + ldr r2, =MMDC1_MPZQHWCTRL + str r0, [r5, r2] + + /* enable DQS gating. */ + ldr r2, =MMDC0_MPDGCTRL0 + ldr r0, [r5, r2] + bic r0, r0, #(1 << 29) + str r0, [r5, r2] + + ldr r2, =MMDC1_MPDGCTRL0 + ldr r0, [r5, r2] + bic r0, r0, #(1 << 29) + str r0, [r5, r2] + + /* force measure. */ + ldr r0, =0x00000800 + str r0, [r5, #MMDC0_MPMUR0] + ldr r2, =MMDC1_MPMUR0 + str r0, [r5, r2] + + /* Wait for FRC_MSR to clear. */ +1: + ldr r0, [r5, #MMDC0_MPMUR0] + and r0, r0, #0x800 + ldr r1, [r5, r2] + and r1, r1, #0x800 + orr r0, r0, r1 + cmp r0, #0x0 + bne 1b + + /* disable dqs pull down in the IOMUX. */ + ldr r1, [r11] + add r11, r11, #8 +update_iomux1: + ldr r0, [r11, #0x0] + ldr r3, [r11, #0x4] + str r3, [r7, r0] + add r11, r11, #8 + sub r1, r1, #1 + cmp r1, #0 + bgt update_iomux1 + + /* config MMDC timings to 528MHz. */ + ldr r9, [r8] + add r8, r8, #8 + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + /* configure ddr devices to dll on, odt. */ + ldr r0, =0x00048031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00048039 + str r0, [r5, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r1, =4 +delay7: + ldr r2, =0 +cont7: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont7 + sub r1, r1, #1 + cmp r1, #0 + bgt delay7 + + /* reset dll. */ + ldr r0, =0x09408030 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x09408038 + str r0, [r5, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r1, =100 +delay8: + ldr r2, =0 +cont8: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont8 + sub r1, r1, #1 + cmp r1, #0 + bgt delay8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, =0x00428031 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x00428039 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + /* issue a zq command. */ + ldr r0, =0x04008040 + str r0, [r5, #MMDC0_MDSCR] + + ldr r0, =0x04008048 + str r0, [r5, #MMDC0_MDSCR] + + /* MMDC ODT enable. */ + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + + ldr r2, =0x4818 + str r3, [r5, r2] + + /* delay for while. */ + ldr r1, =40 +delay15: + ldr r2, =0 +cont15: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont15 + sub r1, r1, #1 + cmp r1, #0 + bgt delay15 + + /* enable MMDC power down timer. */ + ldr r0, [r5, #MMDC0_MDPDC] + orr r0, r0, #(0x55 << 8) + str r0, [r5, #MMDC0_MDPDC] + + b update_calibration + +update_calibration_only: + ldr r1, [r8] + sub r1, r1, #7 + add r8, r8, #64 + b update_calib + +update_calibration: + /* write the new calibration values. */ + mov r1, r9 + sub r1, r1, #7 + +update_calib: + ldr r0, [r8, #0x0] + ldr r3, [r8, #0x4] + str r3, [r5, r0] + add r8, r8, #8 + sub r1, r1, #1 + cmp r1, #0 + bgt update_calib + + /* perform a force measurement. */ + ldr r0, =0x800 + str r0, [r5, #MMDC0_MPMUR0] + ldr r2, =MMDC1_MPMUR0 + str r0, [r5, r2] + + /* Wait for FRC_MSR to clear. */ +1: + ldr r0, [r5, #MMDC0_MPMUR0] + and r0, r0, #0x800 + ldr r1, [r5, r2] + and r1, r1, #0x800 + orr r0, r0, r1 + cmp r0, #0x0 + bne 1b + + /* clear SBS - unblock DDR accesses. */ + ldr r0, [r5, #MMDC0_MADPCR0] + bic r0, r0, #(1 << 8) + str r0, [r5, #MMDC0_MADPCR0] + + is_mx6qp + bne 3f + /* + * Switch back to adopt_bp mode, set MMDC0_MAARCR + * bit25~26 to 2b'10. + */ + ldr r0, [r5, #MMDC0_MAARCR] + bic r0, r0, #(0x3 << 25) + orr r0, r0, #(0x2 << 25) + str r0, [r5, #MMDC0_MAARCR] +3: + mov r0, #0x0 + str r0, [r5, #MMDC0_MDSCR] +poll_conreq_clear_2: + ldr r0, [r5, #MMDC0_MDSCR] + and r0, r0, #(0x4 << 12) + cmp r0, #(0x4 << 12) + beq poll_conreq_clear_2 + +done: + /* MMDC0_MAPSR adopt power down enable. */ + ldr r0, [r5, #MMDC0_MAPSR] + bic r0, r0, #0x01 + str r0, [r5, #MMDC0_MAPSR] + +#ifdef CONFIG_CACHE_L2X0 + ldr r1, [r12, #PL310_AUX_CTRL] + tst r1, #PL310_AUX_16WAY_BIT + mov r6, #PL310_LOCKDOWN_NBREGS + mov r1, #0x00 /* 8 ways mask */ + orrne r1, #0x0000 /* 16 ways mask */ + add r5, r12, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r1, [r5], #PL310_LOCKDOWN_SZREG + str r1, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b + + isb + dsb +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + isb + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + isb + dsb + + /* restore registers */ + ldmfd sp!, {r4-r12} + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +mx6_ddr3_freq_change_end: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/ddr3_freq_imx6sx.S linux-imx-phytec/arch/arm/mach-imx/ddr3_freq_imx6sx.S --- linux-6.1.55/arch/arm/mach-imx/ddr3_freq_imx6sx.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/ddr3_freq_imx6sx.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,764 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +.globl imx6_up_ddr3_freq_change_start +.globl imx6_up_ddr3_freq_change_end + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MDCF0 0xc +#define MMDC0_MDCF1 0x10 +#define MMDC0_MDMISC 0x18 +#define MMDC0_MDSCR 0x1c +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 +#define MMDC0_MPZQHWCTRL 0x800 +#define MMDC0_MPODTCTRL 0x818 +#define MMDC0_MPDGCTRL0 0x83c +#define MMDC0_MPMUR0 0x8b8 + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 +#define PL310_AUX_CTRL 0x104 +#define PL310_DCACHE_LOCKDOWN_BASE 0x900 +#define PL310_AUX_16WAY_BIT 0x10000 +#define PL310_LOCKDOWN_NBREGS 8 +#define PL310_LOCKDOWN_SZREG 4 +#define PL310_8WAYS_MASK 0x00FF +#define PL310_16WAYS_UPPERMASK 0xFF00 + +#define BUSFREQ_INFO_FREQ_OFFSET 0x0 +#define BUSFREQ_INFO_DDR_SETTINGS_OFFSET 0x4 +#define BUSFREQ_INFO_DLL_OFF_OFFSET 0x8 +#define BUSFREQ_INFO_IOMUX_OFFSETS_OFFSET 0xc +#define BUSFREQ_INFO_MU_DELAY_OFFSET 0x10 + +.extern iram_tlb_phys_addr + + .align 3 + + /* Check if the cpu is cortex-a7 */ + .macro is_ca7 + + /* Read the primary cpu number is MPIDR */ + mrc p15, 0, r7, c0, c0, 0 + ldr r8, =0xfff0 + and r7, r7, r8 + ldr r8, =0xc070 + cmp r7, r8 + + .endm + + .macro do_delay + +1: + ldr r9, =0 +2: + ldr r10, [r4, r9] + add r9, r9, #4 + cmp r9, #16 + bne 2b + sub r8, r8, #1 + cmp r8, #0 + bgt 1b + + .endm + + .macro wait_for_ccm_handshake + +3: + ldr r8, [r5, #CCM_CDHIPR] + cmp r8, #0 + bne 3b + + .endm + + .macro switch_to_400MHz + + /* check whether periph2_clk is already from top path */ + ldr r8, [r5, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_400m + + /* now switch periph2_clk back. */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_400m: + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_50MHz + + /* check whether periph2_clk is already from top path */ + ldr r8, [r5, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_50m + + /* now switch periph2_clk back. */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_50m: + + /* fabric_mmdc_podf to 7 so that mmdc is 400 / 8 = 50MHz */ + ldr r8, [r5, #CCM_CBCDR] + orr r8, r8, #(0x7 << 3) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_24MHz + + /* periph2_clk2 sel to OSC_CLK */ + ldr r8, [r5, #CCM_CBCMR] + orr r8, r8, #(1 << 20) + str r8, [r5, #CCM_CBCMR] + + /* periph2_clk2_podf to 0 */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #0x7 + str r8, [r5, #CCM_CBCDR] + + /* periph2_clk sel to periph2_clk2 */ + ldr r8, [r5, #CCM_CBCDR] + orr r8, r8, #(0x1 << 26) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r5, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r5, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + +/* + * imx6_up_ddr3_freq_change + * Below code can be used by i.MX6SX and i.MX6UL. + * + * idle the processor (eg, wait for interrupt). + * make sure DDR is in self-refresh. + * IRQs are already disabled. + */ +ENTRY(imx6_up_ddr3_freq_change) + +imx6_up_ddr3_freq_change_start: + stmfd sp!, {r4 - r11} + + ldr r1, [r0, #BUSFREQ_INFO_DDR_SETTINGS_OFFSET] + ldr r2, [r0, #BUSFREQ_INFO_DLL_OFF_OFFSET] + ldr r3, [r0, #BUSFREQ_INFO_IOMUX_OFFSETS_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + ldr r4, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r6, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR) + + is_ca7 + beq skip_disable_l2 + +#ifdef CONFIG_CACHE_L2X0 + /* + * make sure the L2 buffers are drained, + * sync operation on L2 drains the buffers. + */ + ldr r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r7, [r8, #0x730] + cmp r7, #0x0 + bne wait_for_l2_to_idle + + mov r7, #0x0 + str r7, [r8, #L2_CACHE_SYNC] + + /* Lock L2. */ + + ldr r9, [r8, #PL310_AUX_CTRL] + tst r9, #PL310_AUX_16WAY_BIT + mov r9, #PL310_8WAYS_MASK + orrne r9, #PL310_16WAYS_UPPERMASK + mov r10, #PL310_LOCKDOWN_NBREGS + add r11, r8, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r9, [r11], #PL310_LOCKDOWN_SZREG + str r9, [r11], #PL310_LOCKDOWN_SZREG + subs r10, r10, #1 + bne 1b + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb +#endif + +skip_disable_l2: + /* disable automatic power saving. */ + ldr r8, [r4, #MMDC0_MAPSR] + orr r8, r8, #0x1 + str r8, [r4, #MMDC0_MAPSR] + + /* disable MMDC power down timer. */ + ldr r8, [r4, #MMDC0_MDPDC] + bic r8, r8, #(0xff << 8) + str r8, [r4, #MMDC0_MDPDC] + + /* delay for a while */ + ldr r8, =4 + do_delay + + /* set CON_REG */ + ldr r8, =0x8000 + str r8, [r4, #MMDC0_MDSCR] +poll_conreq_set_1: + ldr r8, [r4, #MMDC0_MDSCR] + and r8, r8, #(0x4 << 12) + cmp r8, #(0x4 << 12) + bne poll_conreq_set_1 + + /* + * if requested frequency is greater than + * 300MHz go to DLL on mode. + */ + ldr r8, [r0, #BUSFREQ_INFO_FREQ_OFFSET] + ldr r9, =300000000 + cmp r8, r9 + bge dll_on_mode + +dll_off_mode: + /* if DLL is currently on, turn it off. */ + cmp r2, #1 + beq continue_dll_off_1 + + ldr r8, =0x00018031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00018039 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =10 + do_delay + +continue_dll_off_1: + /* set DVFS - enter self refresh mode */ + ldr r8, [r4, #MMDC0_MAPSR] + orr r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + + /* de-assert con_req */ + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] + +poll_dvfs_set_1: + ldr r8, [r4, #MMDC0_MAPSR] + and r8, r8, #(1 << 25) + cmp r8, #(1 << 25) + bne poll_dvfs_set_1 + + ldr r8, [r0, #BUSFREQ_INFO_FREQ_OFFSET] + ldr r9, =24000000 + cmp r8, r9 + beq switch_freq_24 + + switch_to_50MHz + b continue_dll_off_2 + +switch_freq_24: + switch_to_24MHz + +continue_dll_off_2: + /* set SBS - block ddr accesses */ + ldr r8, [r4, #MMDC0_MADPCR0] + orr r8, r8, #(1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + /* clear DVFS - exit from self refresh mode */ + ldr r8, [r4, #MMDC0_MAPSR] + bic r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r8, [r4, #MMDC0_MAPSR] + and r8, r8, #(1 << 25) + cmp r8, #(1 << 25) + beq poll_dvfs_clear_1 + + /* if DLL was previously on, continue DLL off routine. */ + cmp r2, #1 + beq continue_dll_off_3 + + ldr r8, =0x00018031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00018039 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x04208030 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x04208038 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00088032 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x0008803A + str r8, [r4, #MMDC0_MDSCR] + + /* delay for a while. */ + ldr r8, =4 + do_delay + + ldr r8, [r4, #MMDC0_MDCF0] + bic r8, r8, #0xf + orr r8, r8, #0x3 + str r8, [r4, #MMDC0_MDCF0] + + ldr r8, [r4, #MMDC0_MDCF1] + bic r8, r8, #0x7 + orr r8, r8, #0x4 + str r8, [r4, #MMDC0_MDCF1] + + ldr r8, [r4, #MMDC0_MDMISC] + bic r8, r8, #(0x3 << 16) /* walat = 0x1 */ + orr r8, r8, #(0x1 << 16) + bic r8, r8, #(0x7 << 6) /* ralat = 0x2 */ + orr r8, r8, #(0x2 << 6) + str r8, [r4, #MMDC0_MDMISC] + + /* enable dqs pull down in the IOMUX. */ + ldr r8, [r3] + add r3, r3, #8 + ldr r9, =0x3028 +update_iomux: + ldr r10, [r3] + ldr r11, [r6, r10] + bic r11, r11, r9 + orr r11, r11, #(0x3 << 12) + orr r11, r11, #0x28 + str r11, [r6, r10] + add r3, r3, #8 + sub r8, r8, #1 + cmp r8, #0 + bgt update_iomux + + /* ODT disabled. */ + ldr r8, =0x0 + str r8, [r4, #MMDC0_MPODTCTRL] + + /* DQS gating disabled. */ + ldr r8, [r4, #MMDC0_MPDGCTRL0] + orr r8, r8, #(1 << 29) + str r8, [r4, #MMDC0_MPDGCTRL0] + + /* Add workaround for ERR005778.*/ + /* double the original MU_UNIT_DEL_NUM. */ + ldr r8, [r0, #BUSFREQ_INFO_MU_DELAY_OFFSET] + lsl r8, r8, #1 + + /* Bypass the automatic MU by setting the mu_byp_en */ + ldr r10, [r4, #MMDC0_MPMUR0] + orr r10, r10, #0x400 + /* Set the MU_BYP_VAL */ + orr r10, r10, r8 + str r10, [r4, #MMDC0_MPMUR0] + + /* Now perform a force measure */ + ldr r8, [r4, #MMDC0_MPMUR0] + orr r8, r8, #0x800 + str r8, [r4, #MMDC0_MPMUR0] + /* Wait for FRC_MSR to clear. */ +1: + ldr r8, [r4, #MMDC0_MPMUR0] + and r8, r8, #0x800 + cmp r8, #0x0 + bne 1b + +continue_dll_off_3: + /* clear SBS - unblock accesses to DDR. */ + ldr r8, [r4, #MMDC0_MADPCR0] + bic r8, r8, #(0x1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] +poll_conreq_clear_1: + ldr r8, [r4, #MMDC0_MDSCR] + and r8, r8, #(0x4 << 12) + cmp r8, #(0x4 << 12) + beq poll_conreq_clear_1 + + b done + +dll_on_mode: + /* assert DVFS - enter self refresh mode. */ + ldr r8, [r4, #MMDC0_MAPSR] + orr r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + + /* de-assert CON_REQ. */ + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] + + /* poll DVFS ack. */ +poll_dvfs_set_2: + ldr r8, [r4, #MMDC0_MAPSR] + and r8, r8, #(1 << 25) + cmp r8, #(1 << 25) + bne poll_dvfs_set_2 + + switch_to_400MHz + + /* set SBS step-by-step mode. */ + ldr r8, [r4, #MMDC0_MADPCR0] + orr r8, r8, #(1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + /* clear DVFS - exit self refresh mode. */ + ldr r8, [r4, #MMDC0_MAPSR] + bic r8, r8, #(1 << 21) + str r8, [r4, #MMDC0_MAPSR] + +poll_dvfs_clear_2: + ldr r8, [r4, #MMDC0_MAPSR] + ands r8, r8, #(1 << 25) + bne poll_dvfs_clear_2 + + /* if DLL is currently off, turn it back on. */ + cmp r2, #0 + beq update_calibration_only + + /* issue zq calibration command */ + ldr r8, [r4, #MMDC0_MPZQHWCTRL] + orr r8, r8, #0x3 + str r8, [r4, #MMDC0_MPZQHWCTRL] + + /* enable DQS gating. */ + ldr r10, =MMDC0_MPDGCTRL0 + ldr r8, [r4, r10] + bic r8, r8, #(1 << 29) + str r8, [r4, r10] + + /* Now perform a force measure */ + ldr r8, =0x00000800 + str r8, [r4, #MMDC0_MPMUR0] + /* Wait for FRC_MSR to clear. */ +1: + ldr r8, [r4, #MMDC0_MPMUR0] + and r8, r8, #0x800 + cmp r8, #0x0 + bne 1b + + /* disable dqs pull down in the IOMUX. */ + ldr r8, [r3] + add r3, r3, #8 +update_iomux1: + ldr r10, [r3, #0x0] + ldr r11, [r3, #0x4] + str r11, [r6, r10] + add r3, r3, #8 + sub r8, r8, #1 + cmp r8, #0 + bgt update_iomux1 + + /* config MMDC timings to 400MHz. */ + ldr r1, [r0, #BUSFREQ_INFO_DDR_SETTINGS_OFFSET] + ldr r7, [r1] + add r1, r1, #8 + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + /* configure ddr devices to dll on, odt. */ + ldr r8, =0x00028031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00028039 + str r8, [r4, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r8, =4 + do_delay + + /* reset dll. */ + ldr r8, =0x09208030 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x09208038 + str r8, [r4, #MMDC0_MDSCR] + + /* delay for while. */ + ldr r8, =100 + do_delay + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r8, =0x00428031 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x00428039 + str r8, [r4, #MMDC0_MDSCR] + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + /* issue a zq command. */ + ldr r8, =0x04008040 + str r8, [r4, #MMDC0_MDSCR] + + ldr r8, =0x04008048 + str r8, [r4, #MMDC0_MDSCR] + + /* MMDC ODT enable. */ + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + + /* delay for while. */ + ldr r8, =40 + do_delay + + /* enable MMDC power down timer. */ + ldr r8, [r4, #MMDC0_MDPDC] + orr r8, r8, #(0x55 << 8) + str r8, [r4, #MMDC0_MDPDC] + + b update_calibration + +update_calibration_only: + ldr r8, [r1] + sub r8, r8, #7 + add r1, r1, #64 + b update_calib + +update_calibration: + /* write the new calibration values. */ + mov r8, r7 + sub r8, r8, #7 + +update_calib: + ldr r10, [r1, #0x0] + ldr r11, [r1, #0x4] + str r11, [r4, r10] + add r1, r1, #8 + sub r8, r8, #1 + cmp r8, #0 + bgt update_calib + + /* perform a force measurement. */ + ldr r8, =0x800 + str r8, [r4, #MMDC0_MPMUR0] + /* Wait for FRC_MSR to clear. */ +1: + ldr r8, [r4, #MMDC0_MPMUR0] + and r8, r8, #0x800 + cmp r8, #0x0 + bne 1b + + /* clear SBS - unblock DDR accesses. */ + ldr r8, [r4, #MMDC0_MADPCR0] + bic r8, r8, #(1 << 8) + str r8, [r4, #MMDC0_MADPCR0] + + mov r8, #0x0 + str r8, [r4, #MMDC0_MDSCR] +poll_conreq_clear_2: + ldr r8, [r4, #MMDC0_MDSCR] + and r8, r8, #(0x4 << 12) + cmp r8, #(0x4 << 12) + beq poll_conreq_clear_2 + +done: + + /* MMDC0_MAPSR adopt power down enable. */ + ldr r8, [r4, #MMDC0_MAPSR] + bic r8, r8, #0x01 + str r8, [r4, #MMDC0_MAPSR] + + is_ca7 + beq skip_enable_l2 + +#ifdef CONFIG_CACHE_L2X0 + /* Unlock L2. */ + ldr r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r9, [r8, #PL310_AUX_CTRL] + tst r9, #PL310_AUX_16WAY_BIT + mov r10, #PL310_LOCKDOWN_NBREGS + mov r9, #0x00 /* 8 ways mask */ + orrne r9, #0x0000 /* 16 ways mask */ + add r11, r8, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r9, [r11], #PL310_LOCKDOWN_SZREG + str r9, [r11], #PL310_LOCKDOWN_SZREG + subs r10, r10, #1 + bne 1b + +#endif + +skip_enable_l2: + /* Enable L1 data cache. */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #0x4 + mcr p15, 0, r7, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #0x800 + mcr p15, 0, r7, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r7, =0x0 + mcr p15, 0, r7, c7, c1, 6 + + /* restore registers */ + ldmfd sp!, {r4 - r11} + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +imx6_up_ddr3_freq_change_end: +ENDPROC(imx6_up_ddr3_freq_change) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/ddr3_freq_imx7d.S linux-imx-phytec/arch/arm/mach-imx/ddr3_freq_imx7d.S --- linux-6.1.55/arch/arm/mach-imx/ddr3_freq_imx7d.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/ddr3_freq_imx7d.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,594 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define DDRC_MSTR 0x0 +#define DDRC_STAT 0x4 +#define DDRC_MRCTRL0 0x10 +#define DDRC_MRCTRL1 0x14 +#define DDRC_MRSTAT 0x18 +#define DDRC_PWRCTL 0x30 +#define DDRC_RFSHCTL3 0x60 +#define DDRC_RFSHTMG 0x64 +#define DDRC_DBG1 0x304 +#define DDRC_SWCTL 0x320 +#define DDRC_SWSTAT 0x324 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 +#define DDRC_ZQCTL0 0x180 +#define DDRC_DFIMISC 0x1b0 +#define DDRC_DBGCAM 0x308 +#define DDRPHY_LP_CON0 0x18 +#define IOMUXC_GPR8 0x20 +#define DDRPHY_MDLL_CON0 0xb0 +#define DDRPHY_MDLL_CON1 0xb4 +#define DDRPHY_OFFSETD_CON0 0x50 +#define DDRPHY_OFFSETR_CON0 0x20 +#define DDRPHY_OFFSETR_CON1 0x24 +#define DDRPHY_OFFSETR_CON2 0x28 +#define DDRPHY_OFFSETW_CON0 0x30 +#define DDRPHY_OFFSETW_CON1 0x34 +#define DDRPHY_OFFSETW_CON2 0x38 +#define DDRPHY_CA_WLDSKEW_CON0 0x6c +#define DDRPHY_CA_DSKEW_CON0 0x7c +#define DDRPHY_CA_DSKEW_CON1 0x80 +#define DDRPHY_CA_DSKEW_CON2 0x84 + +#define ANADIG_DIGPROG 0x800 + + .align 3 + + .macro switch_to_below_100m + + ldr r7, =0x2 + str r7, [r4, #DDRC_DBG1] + + ldr r6, =0x36000000 +1: + ldr r7, [r4, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 1b + + ldr r6, =0x1 +2: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 2b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x0 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +3: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 3b + + ldr r7, =0x20f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x8 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800020f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +4: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 4b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x1 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x20 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x23 +5: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + bne 5b + + ldr r7, =0x0 + str r7, [r4, #DDRC_SWCTL] + + ldr r7, [r4, #DDRC_MSTR] + and r6, r7, #0x400 + ldr r7, =0x03048001 + /* Set 10th bit in new value to be same as old */ + orr r7, r7, r6 + str r7, [r4, #DDRC_MSTR] + + ldr r7, =0x1 + str r7, [r4, #DDRC_SWCTL] + + ldr r6, =0x1 +6: + ldr r7, [r4, #DDRC_SWSTAT] + and r7, r7, r6 + cmp r7, r6 + bne 6b + + ldr r7, =0x10010100 + str r7, [r5, #0x4] + + ldr r6, =24000000 + cmp r0, r6 + beq 25f + + ldr r7, =0x000B000D + str r7,[r4, #DDRC_RFSHTMG] + b 7f + +25: + ldr r7, =0x00030004 + str r7,[r4, #DDRC_RFSHTMG] + + /* dram alt sel set to OSC */ + ldr r7, =0x10000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 1 */ + ldr r7, =0x11000000 + ldr r8, =0x9880 + str r7, [r2, r8] + b 8f +7: + /* dram alt sel set to pfd0_392m */ + ldr r7, =0x15000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 4 */ + ldr r7, =0x11000003 + ldr r8, =0x9880 + str r7, [r2, r8] +8: + ldr r7, =0x202ffd0 + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x1000007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 20f + + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + ldr r7, =0x60606060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x00006060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + b 21f +20: + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +21: + ldr r7, =0x1100007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x1000007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x1 +9: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 9b + + ldr r7, =0xf0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x820 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800000f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +10: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 10b + + ldr r7, =0x800020 + str r7, [r4, #DDRC_ZQCTL0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_DBG1] + + /* enable auto self-refresh */ + ldr r7, [r4, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r4, #DDRC_PWRCTL] + + .endm + + .macro switch_to_533m + + ldr r7, =0x2 + str r7, [r4, #DDRC_DBG1] + + ldr r7, =0x78 + str r7, [r3, #IOMUXC_GPR8] + orr r7, r7, #0x100 + str r7, [r3, #IOMUXC_GPR8] + + ldr r6, =0x30000000 +11: + ldr r7, [r4, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 11b + + ldr r6, =0x1 +12: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 12b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x1 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x20 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x23 +13: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + bne 13b + + ldr r7, [r4, #DDRC_MSTR] + and r6, r7, #0x400 + ldr r7, =0x03040001 + /* Set 10th bit in new value to be same as old */ + orr r7, r7, r6 + str r7, [r4, #DDRC_MSTR] + + ldr r7, =0x40800020 + str r7, [r4, #DDRC_ZQCTL0] + + + ldr r7, =0x10210100 + str r7, [r5, #0x4] + + ldr r7, =0x00040046 + str r7, [r4, #DDRC_RFSHTMG] + + /* dram root set to from dram main, div by 2 */ + ldr r7, =0x10000001 + ldr r8, =0x9880 + str r7, [r2, r8] + + ldr r7, =0x1010007e + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 22f + + ldr r7, =0x40404040 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + ldr r7, =0x18181818 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x40401818 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + b 23f +22: + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +23: + ldr r7, =0x11000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r6, =0x4 +14: + ldr r7, [r5, #DDRPHY_MDLL_CON1] + and r7, r7, r6 + cmp r7, r6 + bne 14b + + ldr r7, =0x1 + str r7, [r4, #DDRC_RFSHCTL3] + ldr r7, =0x3 + str r7, [r4, #DDRC_RFSHCTL3] + + ldr r7, =0x0 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x1 +15: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 15b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x0 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +16: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 16b + + ldr r7, =0xf0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x930 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800000f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_RFSHCTL3] + ldr r7, =0x2 + str r7, [r4, #DDRC_RFSHCTL3] + + ldr r6, =0x1 +17: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 17b + + ldr r7, =0xf0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x930 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800000f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +18: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 18b + + ldr r7, =0x20f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x408 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800020f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r6, =0x1 +19: + ldr r7, [r4, #DDRC_MRSTAT] + and r7, r7, r6 + cmp r7, r6 + beq 19b + + ldr r7, =0x10f0 + str r7, [r4, #DDRC_MRCTRL0] + ldr r7, =0x4 + str r7, [r4, #DDRC_MRCTRL1] + ldr r7, =0x800010f0 + str r7, [r4, #DDRC_MRCTRL0] + + ldr r7, =0x0 + str r7, [r4, #DDRC_DBG1] + + /* enable auto self-refresh */ + ldr r7, [r4, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r4, #DDRC_PWRCTL] + + .endm + +ENTRY(imx7d_ddr3_freq_change) + push {r2 - r9} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + ldr r2, =IMX_IO_P2V(MX7D_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR) + ldr r4, =IMX_IO_P2V(MX7D_DDRC_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX7D_DDRC_PHY_BASE_ADDR) + ldr r9, =IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR) + + ldr r6, =100000000 + cmp r0, r6 + bgt set_to_533m + +set_to_below_100m: + switch_to_below_100m + b done + +set_to_533m: + switch_to_533m + b done + +done: + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r9} + mov pc, lr + .ltorg +ENDPROC(imx7d_ddr3_freq_change) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/ddrc.c linux-imx-phytec/arch/arm/mach-imx/ddrc.c --- linux-6.1.55/arch/arm/mach-imx/ddrc.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/ddrc.c 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,86 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +#include "hardware.h" + +#define DDRC_MSTR 0x0 +#define BM_DDRC_MSTR_DDR3 0x1 +#define BM_DDRC_MSTR_LPDDR2 0x4 +#define BM_DDRC_MSTR_LPDDR3 0x8 + +static int ddr_type; + +static int imx_ddrc_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + void __iomem *ddrc_base, *reg; + u32 val; + + ddrc_base = of_iomap(np, 0); + WARN_ON(!ddrc_base); + + reg = ddrc_base + DDRC_MSTR; + /* Get ddr type */ + val = readl_relaxed(reg); + val &= (BM_DDRC_MSTR_DDR3 | BM_DDRC_MSTR_LPDDR2 + | BM_DDRC_MSTR_LPDDR3); + + switch (val) { + case BM_DDRC_MSTR_DDR3: + pr_info("DDR type is DDR3!\n"); + ddr_type = IMX_DDR_TYPE_DDR3; + break; + case BM_DDRC_MSTR_LPDDR2: + pr_info("DDR type is LPDDR2!\n"); + ddr_type = IMX_DDR_TYPE_LPDDR2; + break; + case BM_DDRC_MSTR_LPDDR3: + pr_info("DDR type is LPDDR3!\n"); + ddr_type = IMX_DDR_TYPE_LPDDR3; + break; + default: + break; + } + + return 0; +} + +int imx_ddrc_get_ddr_type(void) +{ + return ddr_type; +} + +static struct of_device_id imx_ddrc_dt_ids[] = { + { .compatible = "fsl,imx7-ddrc", }, + { /* sentinel */ } +}; + +static struct platform_driver imx_ddrc_driver = { + .driver = { + .name = "imx-ddrc", + .owner = THIS_MODULE, + .of_match_table = imx_ddrc_dt_ids, + }, + .probe = imx_ddrc_probe, +}; + +static int __init imx_ddrc_init(void) +{ + return platform_driver_register(&imx_ddrc_driver); +} +postcore_initcall(imx_ddrc_init); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/gpc.c linux-imx-phytec/arch/arm/mach-imx/gpc.c --- linux-6.1.55/arch/arm/mach-imx/gpc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/gpc.c 2024-06-19 12:33:58.128189625 +0200 @@ -14,22 +14,153 @@ #include "common.h" #include "hardware.h" -#define GPC_CNTR 0x0 +#define GPC_CNTR 0x000 +#define GPC_CNTR_L2_PGE 22 + #define GPC_IMR1 0x008 +#define GPC_PGC_MF_PDN 0x220 #define GPC_PGC_CPU_PDN 0x2a0 #define GPC_PGC_CPU_PUPSCR 0x2a4 #define GPC_PGC_CPU_PDNSCR 0x2a8 #define GPC_PGC_SW2ISO_SHIFT 0x8 #define GPC_PGC_SW_SHIFT 0x0 - -#define GPC_CNTR_L2_PGE_SHIFT 22 +#define GPC_M4_LPSR 0x2c +#define GPC_M4_LPSR_M4_SLEEPING_SHIFT 4 +#define GPC_M4_LPSR_M4_SLEEPING_MASK 0x1 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK 0x1 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT 0 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK 0x1 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT 1 + +#define GPC_PGC_CPU_SW_SHIFT 0 +#define GPC_PGC_CPU_SW_MASK 0x3f +#define GPC_PGC_CPU_SW2ISO_SHIFT 8 +#define GPC_PGC_CPU_SW2ISO_MASK 0x3f #define IMR_NUM 4 #define GPC_MAX_IRQS (IMR_NUM * 32) +/* for irq #74 and #75 */ +#define GPC_USB_VBUS_WAKEUP_IRQ_MASK 0xc00 + +/* for irq #150 and #151 */ +#define GPC_ENET_WAKEUP_IRQ_MASK 0xC00000 + static void __iomem *gpc_base; static u32 gpc_wake_irqs[IMR_NUM]; static u32 gpc_saved_imrs[IMR_NUM]; +static u32 gpc_mf_irqs[IMR_NUM]; +static u32 gpc_mf_request_on[IMR_NUM]; +static DEFINE_SPINLOCK(gpc_lock); + +void imx_gpc_add_m4_wake_up_irq(u32 hwirq, bool enable) +{ + unsigned int idx = hwirq / 32; + unsigned long flags; + u32 mask; + + /* Sanity check for SPI irq */ + if (hwirq < 32) + return; + + mask = 1 << hwirq % 32; + spin_lock_irqsave(&gpc_lock, flags); + gpc_wake_irqs[idx] = enable ? gpc_wake_irqs[idx] | mask : + gpc_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpc_lock, flags); +} + +void imx_gpc_hold_m4_in_sleep(void) +{ + int val; + unsigned long timeout = jiffies + msecs_to_jiffies(500); + + /* wait M4 in wfi before asserting hold request */ + while (!imx_gpc_is_m4_sleeping()) + if (time_after(jiffies, timeout)) + pr_err("M4 is NOT in expected sleep!\n"); + + val = readl_relaxed(gpc_base + GPC_M4_LPSR); + val &= ~(GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK << + GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT); + writel_relaxed(val, gpc_base + GPC_M4_LPSR); + + timeout = jiffies + msecs_to_jiffies(500); + while (readl_relaxed(gpc_base + GPC_M4_LPSR) + & (GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK << + GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT)) + if (time_after(jiffies, timeout)) + pr_err("Wait M4 hold ack timeout!\n"); +} + +void imx_gpc_release_m4_in_sleep(void) +{ + int val; + + val = readl_relaxed(gpc_base + GPC_M4_LPSR); + val |= GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK << + GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT; + writel_relaxed(val, gpc_base + GPC_M4_LPSR); +} + +unsigned int imx_gpc_is_m4_sleeping(void) +{ + if (readl_relaxed(gpc_base + GPC_M4_LPSR) & + (GPC_M4_LPSR_M4_SLEEPING_MASK << + GPC_M4_LPSR_M4_SLEEPING_SHIFT)) + return 1; + + return 0; +} + +bool imx_gpc_usb_wakeup_enabled(void) +{ + if (!(cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll())) + return false; + + /* + * for SoC later than i.MX6SX, USB vbus wakeup + * only needs weak 2P5 on, stop_mode_config is + * NOT needed, so we check if is USB vbus wakeup + * is enabled(assume irq #74 and #75) to decide + * if to keep weak 2P5 on. + */ + if (gpc_wake_irqs[1] & GPC_USB_VBUS_WAKEUP_IRQ_MASK) + return true; + + return false; +} + +bool imx_gpc_enet_wakeup_enabled(void) +{ + if (!cpu_is_imx6q()) + return false; + + if (gpc_wake_irqs[3] & GPC_ENET_WAKEUP_IRQ_MASK) + return true; + + return false; +} + +unsigned int imx_gpc_is_mf_mix_off(void) +{ + return readl_relaxed(gpc_base + GPC_PGC_MF_PDN); +} + +static void imx_gpc_mf_mix_off(void) +{ + int i; + + for (i = 0; i < IMR_NUM; i++) + if (((gpc_wake_irqs[i] | gpc_mf_request_on[i]) & + gpc_mf_irqs[i]) != 0) + return; + + pr_info("Turn off M/F mix!\n"); + /* turn off mega/fast mix */ + writel_relaxed(0x1, gpc_base + GPC_PGC_MF_PDN); +} void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw) { @@ -53,9 +184,9 @@ u32 val; val = readl_relaxed(gpc_base + GPC_CNTR); - val &= ~(1 << GPC_CNTR_L2_PGE_SHIFT); + val &= ~(1 << GPC_CNTR_L2_PGE); if (power_off) - val |= 1 << GPC_CNTR_L2_PGE_SHIFT; + val |= 1 << GPC_CNTR_L2_PGE; writel_relaxed(val, gpc_base + GPC_CNTR); } @@ -64,6 +195,11 @@ void __iomem *reg_imr1 = gpc_base + GPC_IMR1; int i; + /* power down the mega-fast power domain */ + if ((cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) && arm_power_off) + imx_gpc_mf_mix_off(); + /* Tell GPC to power off ARM core when suspend */ if (arm_power_off) imx_gpc_set_arm_power_in_lpm(arm_power_off); @@ -81,6 +217,10 @@ /* Keep ARM core powered on for other low-power modes */ imx_gpc_set_arm_power_in_lpm(false); + /* Keep M/F mix powered on for other low-power modes */ + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + writel_relaxed(0x0, gpc_base + GPC_PGC_MF_PDN); for (i = 0; i < IMR_NUM; i++) writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); @@ -89,11 +229,14 @@ static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) { unsigned int idx = d->hwirq / 32; + unsigned long flags; u32 mask; mask = 1 << d->hwirq % 32; + spin_lock_irqsave(&gpc_lock, flags); gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : gpc_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpc_lock, flags); /* * Do *not* call into the parent, as the GIC doesn't have any @@ -224,11 +367,78 @@ .free = irq_domain_free_irqs_common, }; +int imx_gpc_mf_power_on(unsigned int irq, unsigned int on) +{ + struct irq_desc *d = irq_to_desc(irq); + unsigned int idx = d->irq_data.hwirq / 32; + unsigned long flags; + u32 mask; + + mask = 1 << (d->irq_data.hwirq % 32); + spin_lock_irqsave(&gpc_lock, flags); + gpc_mf_request_on[idx] = on ? gpc_mf_request_on[idx] | mask : + gpc_mf_request_on[idx] & ~mask; + spin_unlock_irqrestore(&gpc_lock, flags); + + return 0; +} + +int imx_gpc_mf_request_on(unsigned int irq, unsigned int on) +{ + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) + return imx_gpc_mf_power_on(irq, on); + else if (cpu_is_imx7d()) + return imx_gpcv2_mf_power_on(irq, on); + else + return 0; +} +EXPORT_SYMBOL_GPL(imx_gpc_mf_request_on); + +void imx_gpc_switch_pupscr_clk(bool flag) +{ + static u32 pupscr_sw2iso, pupscr_sw; + u32 ratio, pupscr = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR); + + if (flag) { + /* save the init clock setting IPG/2048 for IPG@66Mhz */ + pupscr_sw2iso = (pupscr >> GPC_PGC_CPU_SW2ISO_SHIFT) & + GPC_PGC_CPU_SW2ISO_MASK; + pupscr_sw = (pupscr >> GPC_PGC_CPU_SW_SHIFT) & + GPC_PGC_CPU_SW_MASK; + /* + * i.MX6UL TO1.0 ARM power up uses IPG/2048 as clock source, + * from TO1.1, PGC_CPU_PUPSCR bit [5] is re-defined to switch + * clock to IPG/32, enable this bit to speed up the ARM power + * up process in low power idle case(IPG@1.5Mhz). So the sw and + * sw2iso need to be adjusted as below: + * sw_new(sw2iso_new) = (2048 * 1.5 / 66 * 32) * sw(sw2iso) + */ + ratio = 3072 / (66 * 32); + pupscr &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT | + GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + pupscr |= (ratio * pupscr_sw + 1) << GPC_PGC_CPU_SW_SHIFT | + 1 << 5 | (ratio * pupscr_sw2iso + 1) << + GPC_PGC_CPU_SW2ISO_SHIFT; + writel_relaxed(pupscr, gpc_base + GPC_PGC_CPU_PUPSCR); + } else { + /* restore back after exit from low power idle */ + pupscr &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT | + GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + pupscr |= pupscr_sw << GPC_PGC_CPU_SW_SHIFT | + pupscr_sw2iso << GPC_PGC_CPU_SW2ISO_SHIFT; + writel_relaxed(pupscr, gpc_base + GPC_PGC_CPU_PUPSCR); + } +} + static int __init imx_gpc_init(struct device_node *node, struct device_node *parent) { struct irq_domain *parent_domain, *domain; int i; + u32 val; + u32 cpu_pupscr_sw2iso, cpu_pupscr_sw; + u32 cpu_pdnscr_iso2sw, cpu_pdnscr_iso; if (!parent) { pr_err("%pOF: no parent, giving up\n", node); @@ -257,12 +467,70 @@ for (i = 0; i < IMR_NUM; i++) writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); + /* Read supported wakeup source in M/F domain */ + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6ulz() || cpu_is_imx6sll()) { + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 0, + &gpc_mf_irqs[0]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 1, + &gpc_mf_irqs[1]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 2, + &gpc_mf_irqs[2]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 3, + &gpc_mf_irqs[3]); + if (!(gpc_mf_irqs[0] | gpc_mf_irqs[1] | + gpc_mf_irqs[2] | gpc_mf_irqs[3])) + pr_info("No wakeup source in Mega/Fast domain found!\n"); + } + + /* clear the L2_PGE bit on i.MX6SLL */ + if (cpu_is_imx6sll()) { + val = readl_relaxed(gpc_base + GPC_CNTR); + val &= ~(1 << GPC_CNTR_L2_PGE); + writel_relaxed(val, gpc_base + GPC_CNTR); + } + /* * Clear the OF_POPULATED flag set in of_irq_init so that * later the GPC power domain driver will not be skipped. */ of_node_clear_flag(node, OF_POPULATED); + /* + * If there are CPU isolation timing settings in dts, + * update them according to dts, otherwise, keep them + * with default value in registers. + */ + cpu_pupscr_sw2iso = cpu_pupscr_sw = + cpu_pdnscr_iso2sw = cpu_pdnscr_iso = 0; + + /* Read CPU isolation setting for GPC */ + of_property_read_u32(node, "fsl,cpu_pupscr_sw2iso", &cpu_pupscr_sw2iso); + of_property_read_u32(node, "fsl,cpu_pupscr_sw", &cpu_pupscr_sw); + of_property_read_u32(node, "fsl,cpu_pdnscr_iso2sw", &cpu_pdnscr_iso2sw); + of_property_read_u32(node, "fsl,cpu_pdnscr_iso", &cpu_pdnscr_iso); + + /* Return if no property found in dtb */ + if ((cpu_pupscr_sw2iso | cpu_pupscr_sw + | cpu_pdnscr_iso2sw | cpu_pdnscr_iso) == 0) + return 0; + + /* Update CPU PUPSCR timing if it is defined in dts */ + val = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR); + val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT); + val |= cpu_pupscr_sw2iso << GPC_PGC_CPU_SW2ISO_SHIFT; + val |= cpu_pupscr_sw << GPC_PGC_CPU_SW_SHIFT; + writel_relaxed(val, gpc_base + GPC_PGC_CPU_PUPSCR); + + /* Update CPU PDNSCR timing if it is defined in dts */ + val = readl_relaxed(gpc_base + GPC_PGC_CPU_PDNSCR); + val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT); + val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT); + val |= cpu_pdnscr_iso2sw << GPC_PGC_CPU_SW2ISO_SHIFT; + val |= cpu_pdnscr_iso << GPC_PGC_CPU_SW_SHIFT; + writel_relaxed(val, gpc_base + GPC_PGC_CPU_PDNSCR); + return 0; } IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/gpcv2.c linux-imx-phytec/arch/arm/mach-imx/gpcv2.c --- linux-6.1.55/arch/arm/mach-imx/gpcv2.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/gpcv2.c 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,856 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "hardware.h" + +#define IMR_NUM 4 +#define GPC_MAX_IRQS (IMR_NUM * 32) +#define GPC_LPCR_A7_BSC 0x0 +#define GPC_LPCR_A7_AD 0x4 +#define GPC_LPCR_M4 0x8 +#define GPC_SLPCR 0x14 +#define GPC_MLPCR 0x20 +#define GPC_PGC_ACK_SEL_A7 0x24 +#define GPC_MISC 0x2c +#define GPC_IMR1_CORE0 0x30 +#define GPC_IMR1_CORE1 0x40 +#define GPC_IMR1_M4 0x50 +#define GPC_SLOT0_CFG 0xb0 +#define GPC_PGC_CPU_MAPPING 0xec +#define GPC_CPU_PGC_SW_PUP_REQ 0xf0 +#define GPC_PU_PGC_SW_PUP_REQ 0xf8 +#define GPC_CPU_PGC_SW_PDN_REQ 0xfc +#define GPC_PU_PGC_SW_PDN_REQ 0x104 +#define GPC_GTOR 0x124 +#define GPC_PGC_C0 0x800 +#define GPC_PGC_C0_PUPSCR 0x804 +#define GPC_PGC_SCU_TIMING 0x890 +#define GPC_PGC_C1 0x840 +#define GPC_PGC_C1_PUPSCR 0x844 +#define GPC_PGC_SCU 0x880 +#define GPC_PGC_FM 0xa00 + +#define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000 +#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000 +#define BM_LPCR_A7_BSC_LPM1 0xc +#define BM_LPCR_A7_BSC_LPM0 0x3 +#define BP_LPCR_A7_BSC_LPM1 2 +#define BP_LPCR_A7_BSC_LPM0 0 +#define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000 +#define BM_SLPCR_EN_DSM 0x80000000 +#define BM_SLPCR_RBC_EN 0x40000000 +#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000 +#define BM_SLPCR_VSTBY 0x4 +#define BM_SLPCR_SBYOS 0x2 +#define BM_SLPCR_BYPASS_PMIC_READY 0x1 +#define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000 +#define BM_LPCR_A7_AD_L2PGE 0x10000 +#define BM_LPCR_A7_AD_EN_C1_PUP 0x800 +#define BM_LPCR_A7_AD_EN_C1_IRQ_PUP 0x400 +#define BM_LPCR_A7_AD_EN_C0_PUP 0x200 +#define BM_LPCR_A7_AD_EN_C0_IRQ_PUP 0x100 +#define BM_LPCR_A7_AD_EN_PLAT_PDN 0x10 +#define BM_LPCR_A7_AD_EN_C1_PDN 0x8 +#define BM_LPCR_A7_AD_EN_C1_WFI_PDN 0x4 +#define BM_LPCR_A7_AD_EN_C0_PDN 0x2 +#define BM_LPCR_A7_AD_EN_C0_WFI_PDN 0x1 + +#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2 +#define BM_GPC_PGC_PCG 0x1 +#define BM_GPC_PGC_CORE_PUPSCR 0x7fff80 + +#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000 +#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000 +#define BM_GPC_MLPCR_MEMLP_CTL_DIS 0x1 + +#define BP_LPCR_A7_BSC_IRQ_SRC 28 + +#define MAX_SLOT_NUMBER 10 +#define A7_LPM_WAIT 0x5 +#define A7_LPM_STOP 0xa + +enum imx_gpc_slot { + CORE0_A7, + CORE1_A7, + SCU_A7, + FAST_MEGA_MIX, + MIPI_PHY, + PCIE_PHY, + USB_OTG1_PHY, + USB_OTG2_PHY, + USB_HSIC_PHY, + CORE0_M4, +}; + +static void __iomem *gpc_base; +static u32 gpcv2_wake_irqs[IMR_NUM]; +static u32 gpcv2_saved_imrs[IMR_NUM]; +static u32 gpcv2_saved_imrs_m4[IMR_NUM]; +static u32 gpcv2_mf_irqs[IMR_NUM]; +static u32 gpcv2_mf_request_on[IMR_NUM]; +static DEFINE_SPINLOCK(gpcv2_lock); + +void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable) +{ + unsigned int idx = hwirq / 32; + unsigned long flags; + u32 mask; + + /* Sanity check for SPI irq */ + if (hwirq < 32) + return; + + mask = 1 << hwirq % 32; + spin_lock_irqsave(&gpcv2_lock, flags); + gpcv2_wake_irqs[idx] = enable ? gpcv2_wake_irqs[idx] | mask : + gpcv2_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) +{ + unsigned int idx = d->hwirq / 32; + unsigned long flags; + u32 mask; + + BUG_ON(idx >= IMR_NUM); + + mask = 1 << d->hwirq % 32; + spin_lock_irqsave(&gpcv2_lock, flags); + gpcv2_wake_irqs[idx] = on ? gpcv2_wake_irqs[idx] | mask : + gpcv2_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpcv2_lock, flags); + + return 0; +} + +void imx_gpcv2_mask_all(void) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i; + + for (i = 0; i < IMR_NUM; i++) { + gpcv2_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); + writel_relaxed(~0, reg_imr1 + i * 4); + } +} + +void imx_gpcv2_restore_all(void) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i; + + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(gpcv2_saved_imrs[i], reg_imr1 + i * 4); +} + +void imx_gpcv2_hwirq_unmask(unsigned int hwirq) +{ + void __iomem *reg; + u32 val; + + reg = gpc_base + GPC_IMR1_CORE0 + (hwirq / 32) * 4; + val = readl_relaxed(reg); + val &= ~(1 << hwirq % 32); + writel_relaxed(val, reg); +} + +void imx_gpcv2_hwirq_mask(unsigned int hwirq) +{ + void __iomem *reg; + u32 val; + + reg = gpc_base + GPC_IMR1_CORE0 + (hwirq / 32) * 4; + val = readl_relaxed(reg); + val |= 1 << (hwirq % 32); + writel_relaxed(val, reg); +} + +static void imx_gpcv2_irq_unmask(struct irq_data *d) +{ + imx_gpcv2_hwirq_unmask(d->hwirq); + irq_chip_unmask_parent(d); +} + +static void imx_gpcv2_irq_mask(struct irq_data *d) +{ + imx_gpcv2_hwirq_mask(d->hwirq); + irq_chip_mask_parent(d); +} + +void imx_gpcv2_set_slot_ack(u32 index, enum imx_gpc_slot m_core, + bool mode, bool ack) +{ + u32 val; + + if (index >= MAX_SLOT_NUMBER) + pr_err("Invalid slot index!\n"); + /* set slot */ + writel_relaxed(readl_relaxed(gpc_base + GPC_SLOT0_CFG + index * 4) | + ((mode + 1) << (m_core * 2)), + gpc_base + GPC_SLOT0_CFG + index * 4); + + if (ack) { + /* set ack */ + val = readl_relaxed(gpc_base + GPC_PGC_ACK_SEL_A7); + /* clear dummy ack */ + val &= ~(1 << (15 + (mode ? 16 : 0))); + val |= 1 << (m_core + (mode ? 16 : 0)); + writel_relaxed(val, gpc_base + GPC_PGC_ACK_SEL_A7); + } +} + +void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode) +{ + unsigned long flags; + u32 val1, val2; + + spin_lock_irqsave(&gpcv2_lock, flags); + + val1 = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC); + val2 = readl_relaxed(gpc_base + GPC_SLPCR); + + /* all cores' LPM settings must be same */ + val1 &= ~(BM_LPCR_A7_BSC_LPM0 | BM_LPCR_A7_BSC_LPM1); + + val1 |= BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + + val2 &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY); + /* + * GPC: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #32 (IOMUX) to be always pending + * by setting IOMUX_GPR1_IRQ. + * 2) Software should then unmask IRQ #32 in GPC before setting GPC + * Low-Power mode. + * 3) Software should mask IRQ #32 right after GPC Low-Power mode + * is set. + */ + switch (mode) { + case WAIT_CLOCKED: + imx_gpcv2_hwirq_unmask(0); + break; + case WAIT_UNCLOCKED: + val1 |= A7_LPM_WAIT << BP_LPCR_A7_BSC_LPM0; + val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + imx_gpcv2_hwirq_mask(0); + break; + case STOP_POWER_ON: + val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0; + val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + val2 |= BM_SLPCR_EN_DSM; + val2 |= BM_SLPCR_RBC_EN; + val2 |= BM_SLPCR_BYPASS_PMIC_READY; + imx_gpcv2_hwirq_mask(0); + break; + case STOP_POWER_OFF: + val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0; + val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM; + val2 |= BM_SLPCR_EN_DSM; + val2 |= BM_SLPCR_RBC_EN; + val2 |= BM_SLPCR_SBYOS; + val2 |= BM_SLPCR_VSTBY; + val2 |= BM_SLPCR_BYPASS_PMIC_READY; + imx_gpcv2_hwirq_mask(0); + break; + default: + return; + } + writel_relaxed(val1, gpc_base + GPC_LPCR_A7_BSC); + writel_relaxed(val2, gpc_base + GPC_SLPCR); + + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_plat_power_gate_by_lpm(bool pdn) +{ + u32 val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD); + + val &= ~(BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE); + if (pdn) + val |= BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE; + + writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD); +} + +void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) +{ + u32 val = readl_relaxed(gpc_base + offset) & (~BM_GPC_PGC_PCG); + + if (enable) + val |= BM_GPC_PGC_PCG; + + writel_relaxed(val, gpc_base + offset); +} + +void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) +{ + u32 val = readl_relaxed(gpc_base + (pdn ? + GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ)); + + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1); + val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7; + writel_relaxed(val, gpc_base + (pdn ? + GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ)); + + while ((readl_relaxed(gpc_base + (pdn ? + GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ)) & + BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0) + ; + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1); +} + +void imx_gpcv2_set_cpu_power_gate_by_wfi(u32 cpu, bool pdn) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&gpcv2_lock, flags); + val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD); + + if (cpu == 0) { + if (pdn) { + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0); + val |= BM_LPCR_A7_AD_EN_C0_WFI_PDN | + BM_LPCR_A7_AD_EN_C0_IRQ_PUP; + } else { + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0); + val &= ~(BM_LPCR_A7_AD_EN_C0_WFI_PDN | + BM_LPCR_A7_AD_EN_C0_IRQ_PUP); + } + } + if (cpu == 1) { + if (pdn) { + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1); + val |= BM_LPCR_A7_AD_EN_C1_WFI_PDN | + BM_LPCR_A7_AD_EN_C1_IRQ_PUP; + } else { + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1); + val &= ~(BM_LPCR_A7_AD_EN_C1_WFI_PDN | + BM_LPCR_A7_AD_EN_C1_IRQ_PUP); + } + } + writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD); + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_cpu_power_gate_by_lpm(u32 cpu, bool pdn) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&gpcv2_lock, flags); + + val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD); + if (cpu == 0) { + if (pdn) + val |= BM_LPCR_A7_AD_EN_C0_PDN | + BM_LPCR_A7_AD_EN_C0_PUP; + else + val &= ~(BM_LPCR_A7_AD_EN_C0_PDN | + BM_LPCR_A7_AD_EN_C0_PUP); + } + if (cpu == 1) { + if (pdn) + val |= BM_LPCR_A7_AD_EN_C1_PDN | + BM_LPCR_A7_AD_EN_C1_PUP; + else + val &= ~(BM_LPCR_A7_AD_EN_C1_PDN | + BM_LPCR_A7_AD_EN_C1_PUP); + } + + writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD); + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_cpu_power_gate_in_idle(bool pdn) +{ + unsigned long flags; + u32 cpu; + + for_each_possible_cpu(cpu) + imx_gpcv2_set_cpu_power_gate_by_lpm(cpu, pdn); + + spin_lock_irqsave(&gpcv2_lock, flags); + + imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_C0); + if (num_online_cpus() > 1) + imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_C1); + imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_SCU); + imx_gpcv2_set_plat_power_gate_by_lpm(pdn); + + if (pdn) { + imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false); + if (num_online_cpus() > 1) + imx_gpcv2_set_slot_ack(2, CORE1_A7, false, false); + imx_gpcv2_set_slot_ack(3, SCU_A7, false, true); + imx_gpcv2_set_slot_ack(6, SCU_A7, true, false); + if (num_online_cpus() > 1) + imx_gpcv2_set_slot_ack(6, CORE1_A7, true, false); + imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true); + } else { + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 0 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 2 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 3 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 6 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 7 * 0x4); + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 8 * 0x4); + writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK | + BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK, + gpc_base + GPC_PGC_ACK_SEL_A7); + imx_gpcv2_enable_rbc(false); + } + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + +void imx_gpcv2_set_mix_phy_gate_by_lpm(u32 pdn_index, u32 pup_index) +{ + /* set power down slot */ + writel_relaxed(1 << (FAST_MEGA_MIX * 2), + gpc_base + GPC_SLOT0_CFG + pdn_index * 4); + + /* set power up slot */ + writel_relaxed(1 << (FAST_MEGA_MIX * 2 + 1), + gpc_base + GPC_SLOT0_CFG + pup_index * 4); +} + +unsigned int imx_gpcv2_is_mf_mix_off(void) +{ + return readl_relaxed(gpc_base + GPC_PGC_FM); +} + +static void imx_gpcv2_mf_mix_off(void) +{ + int i; + + for (i = 0; i < IMR_NUM; i++) + if (((gpcv2_wake_irqs[i] | gpcv2_mf_request_on[i]) & + gpcv2_mf_irqs[i]) != 0) + return; + + pr_info("Turn off Mega/Fast mix in DSM\n"); + imx_gpcv2_set_slot_ack(1, FAST_MEGA_MIX, false, false); + imx_gpcv2_set_slot_ack(5, FAST_MEGA_MIX, true, false); + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_FM); +} + +int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on) +{ + struct irq_desc *desc = irq_to_desc(irq); + unsigned long hwirq = desc->irq_data.hwirq; + unsigned int idx = hwirq / 32; + unsigned long flags; + u32 mask = 1 << (hwirq % 32); + + BUG_ON(idx >= IMR_NUM); + + spin_lock_irqsave(&gpcv2_lock, flags); + gpcv2_mf_request_on[idx] = on ? gpcv2_mf_request_on[idx] | mask : + gpcv2_mf_request_on[idx] & ~mask; + spin_unlock_irqrestore(&gpcv2_lock, flags); + + return 0; +} + +void imx_gpcv2_enable_rbc(bool enable) +{ + u32 val; + + /* + * need to mask all interrupts in GPC before + * operating RBC configurations + */ + imx_gpcv2_mask_all(); + + /* configure RBC enable bit */ + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~BM_SLPCR_RBC_EN; + val |= enable ? BM_SLPCR_RBC_EN : 0; + writel_relaxed(val, gpc_base + GPC_SLPCR); + + /* configure RBC count */ + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~BM_SLPCR_REG_BYPASS_COUNT; + val |= enable ? BM_SLPCR_REG_BYPASS_COUNT : 0; + writel(val, gpc_base + GPC_SLPCR); + + /* + * need to delay at least 2 cycles of CKIL(32K) + * due to hardware design requirement, which is + * ~61us, here we use 65us for safe + */ + udelay(65); + + /* restore GPC interrupt mask settings */ + imx_gpcv2_restore_all(); +} + + +void imx_gpcv2_pre_suspend(bool arm_power_off) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i; + + if (arm_power_off) { + imx_gpcv2_set_lpm_mode(STOP_POWER_OFF); + /* enable core0 power down/up with low power mode */ + imx_gpcv2_set_cpu_power_gate_by_lpm(0, true); + /* enable plat power down with low power mode */ + imx_gpcv2_set_plat_power_gate_by_lpm(true); + + /* + * To avoid confuse, we use slot 0~4 for power down, + * slot 5~9 for power up. + * + * Power down slot sequence: + * Slot0 -> CORE0 + * Slot1 -> Mega/Fast MIX + * Slot2 -> SCU + * + * Power up slot sequence: + * Slot5 -> Mega/Fast MIX + * Slot6 -> SCU + * Slot7 -> CORE0 + */ + imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false); + imx_gpcv2_set_slot_ack(2, SCU_A7, false, true); + + if ((!imx_src_is_m4_enabled()) || + (imx_src_is_m4_enabled() && imx_mu_is_m4_in_stop())) + imx_gpcv2_mf_mix_off();; + + imx_gpcv2_set_slot_ack(6, SCU_A7, true, false); + imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true); + + /* enable core0, scu */ + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0); + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_SCU); + } else { + imx_gpcv2_set_lpm_mode(STOP_POWER_ON); + } + + for (i = 0; i < IMR_NUM; i++) { + gpcv2_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); + writel_relaxed(~gpcv2_wake_irqs[i], reg_imr1 + i * 4); + } +} + +void imx_gpcv2_enable_wakeup_for_m4(void) +{ + void __iomem *reg_imr2 = gpc_base + GPC_IMR1_M4; + u32 i; + + for (i = 0; i < IMR_NUM; i++) { + gpcv2_saved_imrs_m4[i] = readl_relaxed(reg_imr2 + i * 4); + writel_relaxed(~gpcv2_wake_irqs[i], reg_imr2 + i * 4); + } +} + +void imx_gpcv2_disable_wakeup_for_m4(void) +{ + void __iomem *reg_imr2 = gpc_base + GPC_IMR1_M4; + u32 i; + + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(gpcv2_saved_imrs_m4[i], reg_imr2 + i * 4); +} + +void imx_gpcv2_post_resume(void) +{ + void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0; + int i, val; + + /* only external IRQs to wake up LPM and core 0/1 */ + val = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC); + val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP; + writel_relaxed(val, gpc_base + GPC_LPCR_A7_BSC); + /* mask m4 dsm trigger if M4 NOT enabled */ + if (!imx_src_is_m4_enabled()) + writel_relaxed(readl_relaxed(gpc_base + GPC_LPCR_M4) | + BM_LPCR_M4_MASK_DSM_TRIGGER, gpc_base + GPC_LPCR_M4); + /* set mega/fast mix in A7 domain */ + val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); + val |= 0x1; + writel_relaxed(val, gpc_base + GPC_PGC_CPU_MAPPING); + /* set SCU timing */ + writel_relaxed((0x59 << 10) | 0x5B | (0x2 << 20), + gpc_base + GPC_PGC_SCU_TIMING); + + /* set C0/C1 power up timming per design requirement */ + val = readl_relaxed(gpc_base + GPC_PGC_C0_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C0_PUPSCR); + + val = readl_relaxed(gpc_base + GPC_PGC_C1_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C1_PUPSCR); + + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~(BM_SLPCR_EN_DSM); + if (!imx_src_is_m4_enabled()) + val &= ~(BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY); + val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE; + writel_relaxed(val, gpc_base + GPC_SLPCR); + + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { + /* disable memory low power mode */ + val = readl_relaxed(gpc_base + GPC_MLPCR); + val |= BM_GPC_MLPCR_MEMLP_CTL_DIS; + writel_relaxed(val, gpc_base + GPC_MLPCR); + } + + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(gpcv2_saved_imrs[i], reg_imr1 + i * 4); + + imx_gpcv2_set_lpm_mode(WAIT_CLOCKED); + imx_gpcv2_set_cpu_power_gate_by_lpm(0, false); + imx_gpcv2_set_plat_power_gate_by_lpm(false); + + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0); + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_SCU); + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_FM); + for (i = 0; i < MAX_SLOT_NUMBER; i++){ + if (i == 1 || i == 5) /* skip slts m4 uses */ + continue; + writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + i * 0x4); + } + writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK | + BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK, + gpc_base + GPC_PGC_ACK_SEL_A7); + + /* disable RBC */ + imx_gpcv2_enable_rbc(false); +} + +static struct irq_chip imx_gpcv2_chip = { + .name = "GPCV2", + .irq_eoi = irq_chip_eoi_parent, + .irq_mask = imx_gpcv2_irq_mask, + .irq_unmask = imx_gpcv2_irq_unmask, + .irq_retrigger = irq_chip_retrigger_hierarchy, + .irq_set_wake = imx_gpcv2_irq_set_wake, +#ifdef CONFIG_SMP + .irq_set_affinity = irq_chip_set_affinity_parent, +#endif +}; + +static int imx_gpcv2_domain_xlate(struct irq_domain *domain, + struct device_node *controller, + const u32 *intspec, + unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + if (irq_domain_get_of_node(domain) != controller) + return -EINVAL; /* Shouldn't happen, really... */ + if (intsize != 3) + return -EINVAL; /* Not GIC compliant */ + if (intspec[0] != 0) + return -EINVAL; /* No PPI should point to this domain */ + + *out_hwirq = intspec[1]; + *out_type = intspec[2]; + return 0; +} + +static int imx_gpcv2_domain_alloc(struct irq_domain *domain, + unsigned int irq, + unsigned int nr_irqs, void *data) +{ + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + irq_hw_number_t hwirq; + int i; + + if (fwspec->param_count != 3) + return -EINVAL; /* Not GIC compliant */ + if (fwspec->param[0] != 0) + return -EINVAL; /* No PPI should point to this domain */ + + hwirq = fwspec->param[1]; + if (hwirq >= GPC_MAX_IRQS) + return -EINVAL; /* Can't deal with this */ + + for (i = 0; i < nr_irqs; i++) + irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i, + &imx_gpcv2_chip, NULL); + + parent_fwspec.fwnode = domain->parent->fwnode; + parent_fwspec.param_count = 3; + parent_fwspec.param[0] = 0; + parent_fwspec.param[1] = hwirq; + parent_fwspec.param[2] = fwspec->param[2]; + + return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, + &parent_fwspec); +} + +static struct irq_domain_ops imx_gpcv2_domain_ops = { + .xlate = imx_gpcv2_domain_xlate, + .alloc = imx_gpcv2_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + +static int __init imx_gpcv2_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *parent_domain, *domain; + int i, val; + + if (!parent) { + pr_err("%s: no parent, giving up\n", node->full_name); + return -ENODEV; + } + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("%s: unable to obtain parent domain\n", node->full_name); + return -ENXIO; + } + + gpc_base = of_iomap(node, 0); + if (WARN_ON(!gpc_base)) + return -ENOMEM; + + domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS, + node, &imx_gpcv2_domain_ops, + NULL); + if (!domain) { + iounmap(gpc_base); + return -ENOMEM; + } + + /* Initially mask all interrupts */ + for (i = 0; i < IMR_NUM; i++) { + writel_relaxed(~0, gpc_base + GPC_IMR1_CORE0 + i * 4); + writel_relaxed(~0, gpc_base + GPC_IMR1_CORE1 + i * 4); + } + /* + * Due to hardware design requirement, need to make sure GPR + * interrupt(#32) is unmasked during RUN mode to avoid entering + * DSM by mistake. + */ + writel_relaxed(~0x1, gpc_base + GPC_IMR1_CORE0); + + /* Read supported wakeup source in M/F domain */ + if (cpu_is_imx7d()) { + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 0, + &gpcv2_mf_irqs[0]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 1, + &gpcv2_mf_irqs[1]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 2, + &gpcv2_mf_irqs[2]); + of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 3, + &gpcv2_mf_irqs[3]); + if (!(gpcv2_mf_irqs[0] | gpcv2_mf_irqs[1] | + gpcv2_mf_irqs[2] | gpcv2_mf_irqs[3])) + pr_info("No wakeup source in Mega/Fast domain found!\n"); + } + + /* only external IRQs to wake up LPM and core 0/1 */ + val = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC); + val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP; + writel_relaxed(val, gpc_base + GPC_LPCR_A7_BSC); + /* mask m4 dsm trigger if M4 NOT enabled */ + if (!imx_src_is_m4_enabled()) + writel_relaxed(readl_relaxed(gpc_base + GPC_LPCR_M4) | + BM_LPCR_M4_MASK_DSM_TRIGGER, gpc_base + GPC_LPCR_M4); + /* set mega/fast mix in A7 domain */ + val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); + val |= 0x1; + writel_relaxed(val, gpc_base + GPC_PGC_CPU_MAPPING); + + /* set SCU timing */ + writel_relaxed((0x59 << 10) | 0x5B | (0x2 << 20), + gpc_base + GPC_PGC_SCU_TIMING); + + /* set C0/C1 power up timming per design requirement */ + val = readl_relaxed(gpc_base + GPC_PGC_C0_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C0_PUPSCR); + + val = readl_relaxed(gpc_base + GPC_PGC_C1_PUPSCR); + val &= ~BM_GPC_PGC_CORE_PUPSCR; + val |= (0x1A << 7); + writel_relaxed(val, gpc_base + GPC_PGC_C1_PUPSCR); + + writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK | + BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK, + gpc_base + GPC_PGC_ACK_SEL_A7); + + val = readl_relaxed(gpc_base + GPC_SLPCR); + val &= ~(BM_SLPCR_EN_DSM); + if (!imx_src_is_m4_enabled()) + val &= ~(BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN | + BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY); + val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE; + writel_relaxed(val, gpc_base + GPC_SLPCR); + + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { + /* disable memory low power mode */ + val = readl_relaxed(gpc_base + GPC_MLPCR); + val |= BM_GPC_MLPCR_MEMLP_CTL_DIS; + writel_relaxed(val, gpc_base + GPC_MLPCR); + } + + /* disable RBC */ + imx_gpcv2_enable_rbc(false); + + /* + * Clear the OF_POPULATED flag set in of_irq_init so that + * later the GPC power domain driver will not be skipped. + */ + of_node_clear_flag(node, OF_POPULATED); + + return 0; +} + +/* + * We cannot use the IRQCHIP_DECLARE macro that lives in + * drivers/irqchip, so we're forced to roll our own. Not very nice. + */ +OF_DECLARE_2(irqchip, imx_gpcv2, "fsl,imx7d-gpc", imx_gpcv2_init); + +void __init imx_gpcv2_check_dt(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc"); + if (WARN_ON(!np)) + return; + + if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { + pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); + + /* map GPC, so that at least CPUidle and WARs keep working */ + gpc_base = of_iomap(np, 0); + } +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/hardware.h linux-imx-phytec/arch/arm/mach-imx/hardware.h --- linux-6.1.55/arch/arm/mach-imx/hardware.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/hardware.h 2024-06-19 12:33:58.128189625 +0200 @@ -81,13 +81,16 @@ * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000 * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000 + * mx7d: + * CCM 0x30380000+0x010000 -> 0xf5380000+0x010000 + * ANATOP 0x30360000+0x010000 -> 0xf5360000+0x010000 + * UART1 0x30860000+0x010000 -> 0xf5860000+0x010000 */ #define IMX_IO_P2V(x) ( \ - (((x) & 0x80000000) >> 7) | \ (0xf4000000 + \ - (((x) & 0x50000000) >> 6) + \ - (((x) & 0x0b000000) >> 4) + \ - (((x) & 0x000fffff)))) + (((x) & 0x50000000) >> 4) + \ + (((x) & 0x0a000000) >> 4) + \ + (((x) & 0x00ffffff)))) #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) @@ -98,6 +101,9 @@ #include "mx35.h" #include "mx2x.h" #include "mx27.h" +#include "mx6.h" +#include "mx7.h" +#include "mx7ulp.h" #define imx_map_entry(soc, name, _type) { \ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/headsmp.S linux-imx-phytec/arch/arm/mach-imx/headsmp.S --- linux-6.1.55/arch/arm/mach-imx/headsmp.S 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/headsmp.S 2024-06-19 12:33:58.128189625 +0200 @@ -22,11 +22,13 @@ ENTRY(v7_secondary_startup) ARM_BE8(setend be) @ go BE8 if entered LE mrc p15, 0, r0, c0, c0, 0 - lsl r0, r0, #16 - lsr r0, r0, #20 + ldr r1, =0xf00 + orr r1, r1, #0xff + mov r0, r0, lsr #4 + and r0, r0, r1 /* 0xc07 is cortex A7's ID */ - mov r1, #0xc00 - orr r1, #0x7 + ldr r1, =0xc00 + orr r1, r1, #0x7 cmp r0, r1 beq secondary_startup diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/hotplug.c linux-imx-phytec/arch/arm/mach-imx/hotplug.c --- linux-6.1.55/arch/arm/mach-imx/hotplug.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/hotplug.c 2024-06-19 12:33:58.128189625 +0200 @@ -11,7 +11,6 @@ #include #include "common.h" -#include "hardware.h" /* * platform-specific code to shutdown a CPU @@ -41,7 +40,5 @@ return 0; imx_enable_cpu(cpu, false); imx_set_cpu_arg(cpu, 0); - if (cpu_is_imx7d()) - imx_gpcv2_set_core1_pdn_pup_by_software(true); return 1; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/imx6sll_low_power_idle.S linux-imx-phytec/arch/arm/mach-imx/imx6sll_low_power_idle.S --- linux-6.1.55/arch/arm/mach-imx/imx6sll_low_power_idle.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/imx6sll_low_power_idle.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,780 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x30 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x34 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x3c +#define PM_INFO_MX6Q_L2_P_OFFSET 0x40 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x44 +#define PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET 0x48 + +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x4c +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x50 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6sll_lpm_wfi_start +.globl mx6sll_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + +10: + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] + + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* disconnect vdd_high_in and vdd_snvs_in */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6sx_low_power_idle */ + + .align 3 +ENTRY(imx6sll_low_power_idle) +mx6sll_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6sll_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* save disagnostic register */ + mrc p15, 0, r7, c15, c0, 1 + str r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* sync L2 */ + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r7, [r10, #0x730] + cmp r7, #0x0 + bne wait_for_l2_to_idle + + mov r7, #0x0 + str r7, [r10, #0x730] + /* disable L2 */ + str r7, [r10, #0x100] + + dsb + isb +#endif + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + ccm_enter_idle + anatop_enter_idle + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + +#ifdef CONFIG_CACHE_L2X0 + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + mov r7, #0x1 + /* enable L2 */ + str r7, [r10, #0x100] +#endif + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + /* restore disagnostic register */ + ldr r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + mcr p15, 0, r7, c15, c0, 1 + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6sll_lpm_wfi_end: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/imx6sl_low_power_idle.S linux-imx-phytec/arch/arm/mach-imx/imx6sl_low_power_idle.S --- linux-6.1.55/arch/arm/mach-imx/imx6sl_low_power_idle.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/imx6sl_low_power_idle.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,776 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the license, or + * (at your option) any later version. + * + * This program is distributed in teh hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x0 +#define PM_INFO_TTBR_OFFSET 0x4 +#define PM_INFO_MMDC_V_OFFSET 0x8 +#define PM_INFO_IOMUXC_V_OFFSET 0xc +#define PM_INFO_CCM_V_OFFSET 0x10 +#define PM_INFO_L2_V_OFFSET 0x14 +#define PM_INFO_ANATOP_V_OFFSET 0x18 +#define PM_INFO_IO_NUM_OFFSET 0x1c +#define PM_INFO_IO_VAL_OFFSET 0x20 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c + +.global mx6sl_lpm_wfi_start +.global mx6sl_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + /* + * if in audio_bus_freq_mode, skip to + * audio_mode low power setting. + */ + cmp r1, #0x1 + beq audio_mode + /* + * Now set DDR rate to 1MHz. + * DDR is from bypassed PLL2 on periph2_clk2 path. + * Set the periph2_clk2_podf to divide by 8. + */ + ldr r6, [r10, #0x14] + orr r6, r6, #0x07 + str r6, [r10, #0x14] + + /* Now set MMDC PODF to divide by 3. */ + ldr r6, [r10, #0x14] + bic r6, r6, #0x38 + orr r6, r6, #0x10 + str r6, [r10, #0x14] + + ccm_do_wait + + /* Set the AHB to 3MHz. AXI to 3MHz. */ + ldr r6, [r10, #0x14] + /*r12 stores the origin AHB podf value */ + mov r12, r6 + orr r6, r6, #0x1c00 + orr r6, r6, #0x70000 + str r6, [r10, #0x14] + + ccm_do_wait + + /* Now set ARM to 24MHz. + * Move ARM to be sourced from step_clk + * after setting step_clk to 24MHz. + */ + ldr r6, [r10, #0x0c] + bic r6, r6, #0x100 + str r6, [r10, #0xc] + /*Now pll1_sw_clk to step_clk */ + ldr r6, [r10, #0x0c] + orr r6, r6, #0x4 + str r6, [r10, #0x0c] + + /* Bypass PLL1 and power it down */ + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + ldr r6, =(1 << 16) + orr r6, r6, #0x1000 + str r6, [r10, #0x04] + + /* + * Set the ARM PODF to divide by 8. + * IPG is at 1.5MHz here, we need ARM to + * run at the 12:5 ratio (WAIT mode issue). + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r11, [r10, #0x10] + ldr r6, =0x07 + str r6, [r10, #0x10] + + ccm_do_wait + + b ccm_idle_done + +audio_mode: + /* + * MMDC is sourced from pll2_200M. + * Set the mmdc_podf to div by 8 + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r6, [r10, #0x14] + orr r6, r6, #0x38 + str r6, [r10, #0x14] + + ccm_do_wait + + /* + * ARM is sourced from pll2_pfd2_400M here. + * switch ARM to bypassed PLL1 + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r6, [r10, #0x0c] + bic r6, r6, #0x4 + str r6, [r10, #0xc] + + /* + * set the arm_podf to divide by 3 + * as IPG is at 4MHz, we cannot run + * arm clk above 9.6MHz when system + * enter WAIT mode + */ + ldr r11, [r10, #0x10] + ldr r6, =0x2 + str r6, [r10, #0x10] + + ccm_do_wait + +ccm_idle_done: + + .endm + + .macro ccm_exit_idle + + /* + * If in audio_bus_freq_mode, skip to + * audio_mode ccm restore. + */ + cmp r1, #0x1 + beq audio_ccm_restore + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + /* Power up PLL1 and un-bypass it. */ + ldr r6, =(1 << 12) + str r6, [r10, #0x08] + + /* Wait for PLL1 to relock */ + ldr r8, =0x0 + pll_do_wait_lock + + ldr r6, =(1 << 16) + str r6, [r10, #0x08] + + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + /* Set PLL1_sw_clk back to PLL1 */ + ldr r6, [r10, #0x0c] + bic r6, r6, #0x4 + str r6, [r10, #0x0c] + + /* Restore AHB/AXI back */ + str r12, [r10, #0x14] + + ccm_do_wait + + /* restore mmdc back to 24MHz*/ + ldr r6, [r10, #0x14] + bic r6, r6, #0x3f + str r6, [r10, #0x14] + + ccm_do_wait + b ccm_exit_done + +audio_ccm_restore: + /* move arm clk back to pll2_pfd2_400M */ + ldr r6, [r10, #0xc] + orr r6, r6, #0x4 + str r6, [r10, #0xc] + + /* restore mmdc podf */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + ldr r6, [r10, #0x14] + bic r6, r6, #0x38 + orr r6, #0x8 + str r6, [r10, #0x14] + + ccm_do_wait + +ccm_exit_done: + + .endm + + .macro check_pll_state + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + /* + * Check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2p5 can be off and + * only enable the weak one. PLL1 will be powered + * down late, so no need to check PLL1 state. + */ + + /* sys PLL2 */ + ldr r6, [r10, #0x30] + ands r6, r6, #(1 << 31) + bne 1f + + /* usb PLL3 */ + ldr r6, [r10, #0x10] + ands r6, r6, #(1 << 31) + bne 1f + + /* audio PLL4 */ + ldr r6, [r10, #0x70] + ands r6, r6, #(1 << 31) + bne 1f + + /* video PLL5 */ + ldr r6, [r10, #0xa0] + ands r6, r6, #(1 << 31) + bne 1f + + /* enet PLL6 */ + ldr r6, [r10, #0xe0] + ands r6, r6, #(1 << 31) + bne 1f + + /* usb host PLL7 */ + ldr r6, [r10, #0x20] + ands r6, r6, #(1 << 31) + bne 1f + + ldr r4, =0x1 + b check_done +1: + ldr r4, =0x0 + +check_done: + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + cmp r4, #0x0 + beq anatop_enter_done + + /* Disable 1p1 brown out. */ + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + ldr r6, [r10, #0x110] + bic r6, r6, #0x2 + str r6, [r10, #0x110] + /* + * Set the OSC bias current to -37.5% + * to drop the power on VDDHIGH. + */ + ldr r6, [r10, #0x150] + orr r6, r6, #0xc000 + str r6, [r10, #0x150] + + /* + * if the usb VBUS wakeup is enabled, skip + * disable main 2p5. + */ + cmp r2, #0x1 + beq anatop_enter_done + + /* Enable the week 2p5 */ + ldr r6, [r10, #0x130] + orr r6, r6, #0x40000 + str r6, [r10, #0x130] + + /* Disable main 2p5. */ + ldr r6, [r10, #0x130] + bic r6, r6, #0x1 + str r6, [r10, #0x130] + + /* + * Cannot diable regular bandgap + * in LDO-enable mode. The bandgap + * is required for ARM-LDO to regulate + * the voltage. + */ + ldr r6, [r10, #0x140] + and r6, r6, #0x1f + cmp r6, #0x1f + bne anatop_enter_done + + /* Enable low power bandgap */ + ldr r6, [r10, #0x260] + orr r6, r6, #0x20 + str r6, [r10, #0x260] + + /* + * Turn off the bias current + * from the regular bandgap. + */ + ldr r6, [r10, #0x260] + orr r6, r6, #0x80 + str r6, [r10, #0x260] + + /* + * Clear the REFTTOP+SELFBIASOFF, + * self_bais circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r6, [r10, #0x150] + bic r6, r6, #0x8 + str r6, [r10, #0x150] + + /* Power down the regular bandgap */ + ldr r6, [r10, #0x150] + orr r6, r6, #0x1 + str r6, [r10, #0x150] +anatop_enter_done: + + .endm + + .macro anatop_exit_idle + + ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET] + cmp r4, #0x0 + beq skip_anatop_restore + + cmp r2, #0x1 + beq ldo2p5_not_disabled + /* + * Regular bandgap will not be disabled + * in LDO-enabled mode as it is required + * for ARM-LDO to reguulate the voltage. + */ + ldr r6, [r10, #0x140] + and r6, r6, #0x1f + cmp r6, #0x1f + bne skip_bandgap_restore + + /* Power up the regular bandgap */ + ldr r6, [r10, #0x150] + bic r6, r6, #0x1 + str r6, [r10, #0x150] + + /* wait for bandgap stable */ +3: + ldr r6, [r10, #0x150] + and r6, r6, #0x80 + cmp r6, #0x80 + bne 3b + + /* now disable bandgap self-bias circuit */ + ldr r6, [r10, #0x150] + orr r6, r6, #0x8 + str r6, [r10, #0x150] + + /* Turn on the bias current + * from the regular bandgap. + */ + ldr r6, [r10, #0x260] + bic r6, r6, #0x80 + str r6, [r10, #0x260] + + /* Disable the low power bandgap */ + ldr r6, [r10, #0x260] + bic r6, r6, #0x20 + str r6, [r10, #0x260] + +skip_bandgap_restore: + /* Enable main 2p5. */ + ldr r6, [r10, #0x130] + orr r6, r6, #0x1 + str r6, [r10, #0x130] + + /* Ensure the 2p5 is up */ +5: + ldr r6, [r10, #0x130] + and r6, r6, #0x20000 + cmp r6, #0x20000 + bne 5b + + /* Disable the weak 2p5 */ + ldr r6, [r10, #0x130] + bic r6, r6, #0x40000 + str r6, [r10, #0x130] + +ldo2p5_not_disabled: + /* + * Set the OSC bias current to max + * value for normal operation. + */ + ldr r6, [r10, #0x150] + bic r6, r6, #0xc000 + str r6, [r10, #0x150] + + /* Enable 1p1 brown out, */ + ldr r6, [r10, #0x110] + orr r6, r6, #0x2 + str r6, [r10, #0x110] + +skip_anatop_restore: + + .endm + + .macro disable_l1_dcache + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + + dsb + isb + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power saving. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x04] + bic r7, r7, #0xff00 + str r7, [r10, #0x04] + + /* Make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] + +poll_dvfs_set: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq poll_dvfs_set + + /* set SBS step-by step mode */ + ldr r7, [r10, #0x410] + orr r7, r7, #0x100 + str r7, [r10, #0x410] + + .endm + + .macro resume_mmdc + /* restore MMDC IO */ + ldr r10, [r0, #PM_INFO_IOMUXC_V_OFFSET] + + ldr r6, [r0, #PM_INFO_IO_NUM_OFFSET] + ldr r7, =PM_INFO_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + /* + * Need to reset the FIFO to avoid MMDC lockup + * caused because of floating/changing the + * configuration of many DDR IO pads. + */ + ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET] + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 <<31) + bne 8b + + ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET] + /* Let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x04] + orr r7, r7, #0x5500 + str r7, [r10, #0x04] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* Clear SBS - unblock DDR accesses */ + ldr r7, [r10, #0x410] + bic r7, r7, #0x100 + str r7, [r10, #0x410] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * we need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to the IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is transslated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + + /* store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + /* Read TTBCR and set PD0=1, N=1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* Flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N=0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + /* Flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0 ,r6, c1, c0, 0 + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + /* Restore ttbr */ + ldr r7, [r0, #PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* + * imx6sl_low_power_wfi code + * r0: wfi code base address + * r1: audio_bus_freq mode stat + * r2: vbus_ldo status + * r4: used for store the PLLs state + * r11: used for saving the ARM_PODF origin value + * r12: used for saving AHB_PODF origin value + */ + .align 3 +ENTRY(imx6sl_low_power_idle) + +mx6sl_lpm_wfi_start: + push {r4-r12} + + tlb_set_to_ocram + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* sync L2 */ + ldr r10, [r0, #PM_INFO_L2_V_OFFSET] + /* Wait for background operations to complete. */ +wait_for_l2_idle: + ldr r6, [r10, #0x730] + cmp r6, #0x0 + bne wait_for_l2_idle + + mov r6, #0x0 + str r6, [r10, #0x730] + /* disable L2 */ + str r6, [r10, #0x100] + + dsb + isb +#endif + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + /* save DDR IO settings and set to LPM mode*/ + ldr r10, [r0, #PM_INFO_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_IO_NUM_OFFSET] + ldr r8, =PM_INFO_IO_VAL_OFFSET + add r8, r8, r0 + + /* imx6sl's last 3 IOs need special setting */ + sub r7, r7, #0x3 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + ldr r6, =0x1000 + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r5, [r8], #0x4 + str r6, [r10, r9] + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + ldr r6, =0x80000 + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + + + /* check the PLLs lock state */ + check_pll_state + + ccm_enter_idle + /* if in audio low power mode, no + * need to do anatop setting. + */ + cmp r1, #0x1 + beq do_wfi + anatop_enter_idle +do_wfi: + wfi + /* + * Add these nops so that the + * prefetcher will not try to get + * any instrutions from DDR. + * The prefetch depth is about 23 + * on A9, so adding 25 nops. + */ + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* + * restore the ARM PODF first to speed + * up the restore procedure + */ + ldr r10, [r0, #PM_INFO_CCM_V_OFFSET] + /* Restore arm_clk_podf */ + str r11, [r10, #0x10] + ccm_do_wait + + /* + * if in audio low power mode, skip + * restore the anatop setting. + */ + cmp r1, #0x1 + beq skip_analog_restore + anatop_exit_idle + +skip_analog_restore: + ccm_exit_idle + resume_mmdc + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + +#ifdef CONFIG_CACHE_L2X0 + ldr r10, [r0, #PM_INFO_L2_V_OFFSET] + mov r7, #0x1 + /* enable L2 */ + str r7, [r10, #0x100] +#endif + tlb_back_to_ddr + + /* Restore register */ + pop {r4 - r12} + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +mx6sl_lpm_wfi_end: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/imx6sx_low_power_idle.S linux-imx-phytec/arch/arm/mach-imx/imx6sx_low_power_idle.S --- linux-6.1.55/arch/arm/mach-imx/imx6sx_low_power_idle.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/imx6sx_low_power_idle.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,887 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_L2_P_OFFSET 0x30 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x34 +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x38 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x3c +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x40 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x44 +#define PM_INFO_MX6Q_SEMA4_P_OFFSET 0x48 +#define PM_INFO_MX6Q_SEMA4_V_OFFSET 0x4c +#define PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET 0x50 +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x54 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x58 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6sx_lpm_wfi_start +.globl mx6sx_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from osc */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* Disable PLL1 bypass output */ + ldr r7, [r10] + bic r7, r7, #0x12000 + str r7, [r10] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + /* enable PLL1 bypass output */ + ldr r7, [r10] + orr r7, r7, #0x12000 + str r7, [r10] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from pll2_pfd2 */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 10f + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + + /* only switch to RC-OSC clk after TO1.2 */ + ldr r7, [r10, #0x260] + and r7, r7, #0x3 + cmp r7, #0x2 + blt 10f + + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] +10: + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* only switch to RC-OSC after TO1.2 */ + ldr r7, [r10, #0x260] + and r7, r7, #0x3 + cmp r7, #0x2 + blt 15f + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 12f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x4] + bic r7, r7, #0xff00 + str r7, [r10, #0x4] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x4] + orr r7, r7, #0x5500 + str r7, [r10, #0x4] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro sema4_lock + + /* lock share memory sema4 */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_SEMA4_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_SEMA4_P_OFFSET] + ldrb r6, =0x1 +16: + ldrb r7, [r10, #0x6] + cmp r7, #0x0 + bne 16b + strb r6, [r10, #0x6] + + .endm + + .macro sema4_unlock + + /* unlock share memory sema4 */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_SEMA4_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_SEMA4_P_OFFSET] + ldrb r6, =0x0 + strb r6, [r10, #0x6] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6sx_low_power_idle */ + + .align 3 +ENTRY(imx6sx_low_power_idle) +mx6sx_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6sx_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* save disagnostic register */ + mrc p15, 0, r7, c15, c0, 1 + str r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + +#ifdef CONFIG_CACHE_L2X0 + /* sync L2 */ + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r7, [r10, #0x730] + cmp r7, #0x0 + bne wait_for_l2_to_idle + + mov r7, #0x0 + str r7, [r10, #0x730] + /* disable L2 */ + str r7, [r10, #0x100] + + dsb + isb +#endif + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + sema4_lock + ccm_enter_idle + anatop_enter_idle + sema4_unlock + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + sema4_lock + anatop_exit_idle + ccm_exit_idle + sema4_unlock + resume_mmdc + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + +#ifdef CONFIG_CACHE_L2X0 + ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + mov r7, #0x1 + /* enable L2 */ + str r7, [r10, #0x100] +#endif + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + /* restore disagnostic register */ + ldr r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET] + mcr p15, 0, r7, c15, c0, 1 + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + sema4_lock + anatop_exit_idle + ccm_exit_idle + sema4_unlock + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6sx_lpm_wfi_end: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/imx6ull_low_power_idle.S linux-imx-phytec/arch/arm/mach-imx/imx6ull_low_power_idle.S --- linux-6.1.55/arch/arm/mach-imx/imx6ull_low_power_idle.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/imx6ull_low_power_idle.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,764 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x30 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x34 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x3c +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6ull_lpm_wfi_start +.globl mx6ull_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 10f + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + +10: + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] + + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* disconnect vdd_high_in and vdd_snvs_in */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 12f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x4] + bic r7, r7, #0xff00 + str r7, [r10, #0x4] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x4] + orr r7, r7, #0x5500 + str r7, [r10, #0x4] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6ull_low_power_idle */ + + .align 3 +ENTRY(imx6ull_low_power_idle) +mx6ull_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6ull_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + ccm_enter_idle + anatop_enter_idle + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + anatop_exit_idle + ccm_exit_idle + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + resume_mmdc + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6ull_lpm_wfi_end: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/imx6ul_low_power_idle.S linux-imx-phytec/arch/arm/mach-imx/imx6ul_low_power_idle.S --- linux-6.1.55/arch/arm/mach-imx/imx6ul_low_power_idle.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/imx6ul_low_power_idle.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,821 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8 +#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x30 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x34 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x3c +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 + +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + +.globl mx6ul_lpm_wfi_start +.globl mx6ul_lpm_wfi_end + + .macro pll_do_wait_lock +1: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 1b + + .endm + + .macro ccm_do_wait +2: + ldr r7, [r10, #0x48] + cmp r7, #0x0 + bne 2b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set ahb to 3MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x1c00 + str r7, [r10, #0x14] + + /* set perclk to 6MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + orr r7, r7, #0x3 + str r7, [r10, #0x1c] + + /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */ + ldr r7, [r10, #0x14] + orr r7, r7, #0x2 + orr r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + ccm_do_wait + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* bypass PLL1 output to OSC */ + ldr r7, [r10] + orr r7, r7, #(0x1 << 16) + str r7, [r10] + + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from osc */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* Disable PLL1 bypass output */ + ldr r7, [r10] + bic r7, r7, #0x12000 + str r7, [r10] + + /* + * disable pll2, suppose when system enter low + * power idle mode, only 396MHz pfd needs pll2, + * now we switch arm clock to OSC, we can disable + * pll2 now, gate pll2_pfd2 first. + */ + ldr r7, [r10, #0x100] + orr r7, #0x800000 + str r7, [r10, #0x100] + + ldr r7, [r10, #0x30] + orr r7, r7, #0x1000 + bic r7, r7, #0x2000 + str r7, [r10, #0x30] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* enable pll2 and pll2_pfd2 */ + ldr r7, [r10, #0x30] + bic r7, r7, #0x1000 + orr r7, r7, #0x2000 + str r7, [r10, #0x30] + + ldr r8, =0x30 + pll_do_wait_lock + + ldr r7, [r10, #0x100] + bic r7, #0x800000 + str r7, [r10, #0x100] + + /* enable PLL1 bypass output */ + ldr r7, [r10] + orr r7, r7, #0x12000 + str r7, [r10] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET] + + /* set perclk back to 24MHz */ + ldr r7, [r10, #0x1c] + bic r7, r7, #0x3f + str r7, [r10, #0x1c] + + /* set mmdc back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x7 + bic r7, r7, #(0x7 << 3) + str r7, [r10, #0x14] + + /* set ahb div back to 24MHz */ + ldr r7, [r10, #0x14] + bic r7, r7, #0x1c00 + str r7, [r10, #0x14] + + ccm_do_wait + + /* set pll1_sw to from pll1 main */ + ldr r7, [r10, #0xc] + bic r7, r7, #0x4 + str r7, [r10, #0xc] + + /* set step from pll2_pfd2 */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x100 + str r7, [r10, #0xc] + + /* set pll1_sw to from step */ + ldr r7, [r10, #0xc] + orr r7, r7, #0x4 + str r7, [r10, #0xc] + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* Unbypass PLL1 */ + ldr r7, [r10] + bic r7, r7, #(0x1 << 16) + str r7, [r10] + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + + /* + * check whether any PLL is enabled, as only when + * there is no PLLs enabled, 2P5 and 1P1 can be + * off and only enable weak ones. + */ + + /* arm pll1 */ + ldr r7, [r10, #0] + ands r7, r7, #(1 << 31) + bne 10f + + /* sys pll2 */ + ldr r7, [r10, #0x30] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb pll3 */ + ldr r7, [r10, #0x10] + ands r7, r7, #(1 << 31) + bne 10f + + /* audio pll4 */ + ldr r7, [r10, #0x70] + ands r7, r7, #(1 << 31) + bne 10f + + /* vidio pll5 */ + ldr r7, [r10, #0xa0] + ands r7, r7, #(1 << 31) + bne 10f + + /* enet pll6 */ + ldr r7, [r10, #0xe0] + ands r7, r7, #(1 << 31) + bne 10f + + /* usb host pll7 */ + ldr r7, [r10, #0x20] + ands r7, r7, #(1 << 31) + bne 10f + + /* enable weak 2P5 and turn off regular 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x40000 + str r7, [r10, #0x130] + bic r7, r7, #0x1 + str r7, [r10, #0x130] + + /* enable weak 1p1 and turn off regular 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x40000 + str r7, [r10, #0x110] + bic r7, r7, #0x1 + str r7, [r10, #0x110] + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 10f + + /* low power band gap enable */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x20 + str r7, [r10, #0x270] + + /* turn off the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x80 + str r7, [r10, #0x270] + + /* + * clear the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + * Per RM, should be cleared when + * band gap is powered down. + */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn off regular bandgap */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1 + str r7, [r10, #0x150] + + /* switch to RC-OSC */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x40000000 + str r7, [r10, #0x150] +10: + /* lower OSC current by 37.5% */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* disconnect vdd_high_in and vdd_snvs_in */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x1000 + str r7, [r10, #0x150] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + + /* increase OSC current to normal */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x6000 + str r7, [r10, #0x150] + + /* turn on XTAL-OSC and detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x40000000 + orr r7, r7, #0x10000 + str r7, [r10, #0x150] + + /* wait for XTAL stable */ +14: + ldr r7, [r10, #0x150] + ands r7, r7, #0x8000 + beq 14b + + /* switch to XTAL-OSC */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x10 + str r7, [r10, #0x270] + + /* turn off XTAL-OSC detector */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x10000 + str r7, [r10, #0x150] +15: + /* check whether we need to enable 2P5/1P1 */ + ldr r7, [r10, #0x110] + ands r7, r7, #0x40000 + beq 11f + + /* check whether ARM LDO is bypassed */ + ldr r7, [r10, #0x140] + and r7, r7, #0x1f + cmp r7, #0x1f + bne 12f + + /* turn on regular bandgap and wait for stable */ + ldr r7, [r10, #0x150] + bic r7, r7, #0x1 + str r7, [r10, #0x150] +13: + ldr r7, [r10, #0x150] + ands r7, #0x80 + beq 13b + + /* + * set the REFTOP_SELFBIASOFF, + * self-bias circuit of the band gap. + */ + ldr r7, [r10, #0x150] + orr r7, r7, #0x8 + str r7, [r10, #0x150] + + /* turn on the bias current from the regular bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x80 + str r7, [r10, #0x270] + + /* low power band gap disable */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x20 + str r7, [r10, #0x270] +12: + /* enable regular 2P5 and turn off weak 2P5 */ + ldr r7, [r10, #0x130] + orr r7, r7, #0x1 + str r7, [r10, #0x130] + + /* Ensure the 2P5 is up. */ +3: + ldr r7, [r10, #0x130] + ands r7, r7, #0x20000 + beq 3b + ldr r7, [r10, #0x130] + bic r7, r7, #0x40000 + str r7, [r10, #0x130] + + /* enable regular 1p1 and turn off weak 1P1 */ + ldr r7, [r10, #0x110] + orr r7, r7, #0x1 + str r7, [r10, #0x110] +4: + ldr r7, [r10, #0x110] + ands r7, r7, #0x20000 + beq 4b + ldr r7, [r10, #0x110] + bic r7, r7, #0x40000 + str r7, [r10, #0x110] +11: + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro mmdc_enter_dvfs_mode + + /* disable automatic power savings. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + /* disable power down timer */ + ldr r7, [r10, #0x4] + bic r7, r7, #0xff00 + str r7, [r10, #0x4] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq 5b + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +6: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 6b + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +7: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 7b + + /* reset FIFO a second time */ + ldr r6, [r10, r7] + orr r6, r6, #(1 << 31) + str r6, [r10, r7] +8: + ldr r6, [r10, r7] + ands r6, r6, #(1 << 31) + bne 8b + + /* let DDR out of self-refresh */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r10, #MX6Q_MMDC_MAPSR] +9: + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 9b + + /* enable power down timer */ + ldr r7, [r10, #0x4] + orr r7, r7, #0x5500 + str r7, [r10, #0x4] + + /* enable DDR auto power saving */ + ldr r7, [r10, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r10, #MX6Q_MMDC_MAPSR] + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Restore the TTBCR */ + + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + +.extern iram_tlb_phys_addr + +/* imx6ul_low_power_idle */ + + .align 3 +ENTRY(imx6ul_low_power_idle) +mx6ul_lpm_wfi_start: + push {r4 - r10} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx6ul_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + str r3, [r10, #0x20] + str r1, [r10, #0x24] + + /* set ARM power to be gated */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x1 + str r7, [r10, #0x2a0] + + disable_l1_dcache + + tlb_set_to_ocram + + /* make sure MMDC in self-refresh */ + ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + mmdc_enter_dvfs_mode + + /* save DDR IO settings */ + ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 +save_and_set_mmdc_io_lpm: + ldr r9, [r8], #0x4 + ldr r5, [r10, r9] + str r6, [r10, r9] + str r5, [r8], #0x4 + subs r7, r7, #0x1 + bne save_and_set_mmdc_io_lpm + + mov r5, #0x0 + ccm_enter_idle + anatop_enter_idle + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r4, [r10, #MX6Q_GPC_IMR1] + ldr r5, [r10, #MX6Q_GPC_IMR2] + ldr r6, [r10, #MX6Q_GPC_IMR3] + ldr r7, [r10, #MX6Q_GPC_IMR4] + + ldr r3, =0xffffffff + str r3, [r10, #MX6Q_GPC_IMR1] + str r3, [r10, #MX6Q_GPC_IMR2] + str r3, [r10, #MX6Q_GPC_IMR3] + str r3, [r10, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 4 (120us). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~130uS. + */ + ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r3, [r10, #MX6Q_CCM_CCR] + bic r3, r3, #(0x3f << 21) + orr r3, r3, #(0x4 << 21) + str r3, [r10, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r3, [r10, #MX6Q_CCM_CCR] + orr r3, r3, #(0x1 << 27) + str r3, [r10, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r4, [r10, #MX6Q_GPC_IMR1] + str r5, [r10, #MX6Q_GPC_IMR2] + str r6, [r10, #MX6Q_GPC_IMR3] + str r7, [r10, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =50 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + mov r5, #0x0 + anatop_exit_idle + ccm_exit_idle + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + resume_mmdc + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + + tlb_back_to_ddr + + /* Restore registers */ + pop {r4 - r10} + mov pc, lr + +wakeup: + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r10, #MX6Q_SRC_GPR1] + str r7, [r10, #MX6Q_SRC_GPR2] + + /* clear ARM power gate setting */ + ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r7, =0x0 + str r7, [r10, #0x2a0] + + mov r5, #0x1 + anatop_exit_idle + ccm_exit_idle + resume_mmdc + + /* Restore registers */ + mov pc, lr + .ltorg +mx6ul_lpm_wfi_end: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/imx7d_low_power_idle.S linux-imx-phytec/arch/arm/mach-imx/imx7d_low_power_idle.S --- linux-6.1.55/arch/arm/mach-imx/imx7d_low_power_idle.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/imx7d_low_power_idle.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,773 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define PM_INFO_VBASE_OFFSET 0x0 +#define PM_INFO_PBASE_OFFSET 0x4 +#define PM_INFO_RESUME_ADDR_OFFSET 0x8 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0xc +#define PM_INFO_PM_INFO_TTBR_OFFSET 0x10 +#define PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET 0x14 +#define PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET 0x18 +#define PM_INFO_VAL_OFFSET 0x1c +#define PM_INFO_FLAG0_OFFSET 0x20 +#define PM_INFO_FLAG1_OFFSET 0x24 +#define PM_INFO_MX7D_DDRC_P_OFFSET 0x28 +#define PM_INFO_MX7D_DDRC_V_OFFSET 0x2c +#define PM_INFO_MX7D_CCM_P_OFFSET 0x30 +#define PM_INFO_MX7D_CCM_V_OFFSET 0x34 +#define PM_INFO_MX7D_ANATOP_P_OFFSET 0x38 +#define PM_INFO_MX7D_ANATOP_V_OFFSET 0x3c +#define PM_INFO_MX7D_SRC_P_OFFSET 0x40 +#define PM_INFO_MX7D_SRC_V_OFFSET 0x44 +#define PM_INFO_MX7D_IOMUXC_GPR_P_OFFSET 0x48 +#define PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET 0x4c +#define PM_INFO_MX7D_GPC_P_OFFSET 0x50 +#define PM_INFO_MX7D_GPC_V_OFFSET 0x54 +#define PM_INFO_MX7D_GIC_DIST_P_OFFSET 0x58 +#define PM_INFO_MX7D_GIC_DIST_V_OFFSET 0x5c + +#define MX7D_SRC_GPR1 0x74 +#define MX7D_SRC_GPR2 0x78 +#define MX7D_SRC_GPR3 0x7c +#define MX7D_SRC_GPR4 0x80 +#define MX7D_GPC_IMR1 0x30 +#define MX7D_GPC_IMR2 0x34 +#define MX7D_GPC_IMR3 0x38 +#define MX7D_GPC_IMR4 0x3c +#define DDRC_STAT 0x4 +#define DDRC_PWRCTL 0x30 +#define DDRC_DBG1 0x304 +#define DDRC_DBGCAM 0x308 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 + +/* + * imx_pen_lock + * + * The reference link of Peterson's algorithm: + * http://en.wikipedia.org/wiki/Peterson's_algorithm + * + * val1 = r1 = !turn (inverted from Peterson's algorithm) + * on cpu 0: + * r2 = flag[0] (in flag0) + * r3 = flag[1] (in flag1) + * on cpu1: + * r2 = flag[1] (in flag1) + * r3 = flag[0] (in flag0) + * + */ + .macro imx_pen_lock + + mov r8, r0 + mrc p15, 0, r5, c0, c0, 5 + and r5, r5, #3 + add r6, r8, #PM_INFO_VAL_OFFSET + cmp r5, #0 + addeq r7, r8, #PM_INFO_FLAG0_OFFSET + addeq r8, r8, #PM_INFO_FLAG1_OFFSET + addne r7, r8, #PM_INFO_FLAG1_OFFSET + addne r8, r8, #PM_INFO_FLAG0_OFFSET + + mov r9, #1 + str r9, [r7] + dsb + str r5, [r6] +1: + dsb + ldr r9, [r8] + cmp r9, #1 + ldreq r9, [r6] + cmpeq r9, r5 + beq 1b + + .endm + + .macro imx_pen_unlock + + dsb + mrc p15, 0, r6, c0, c0, 5 + and r6, r6, #3 + cmp r6, #0 + addeq r7, r0, #PM_INFO_FLAG0_OFFSET + addne r7, r0, #PM_INFO_FLAG1_OFFSET + mov r9, #0 + str r9, [r7] + + .endm + + .macro disable_l1_dcache + + push {r0 - r12, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r12, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r12, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r12, lr} + +#ifdef CONFIG_SMP + clrex + + /* Turn off SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + bic r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + dsb +#endif + + .endm + + .macro tlb_set_to_ocram + + /* save ttbr */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro tlb_back_to_ddr + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* restore ttbr */ + ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + /* r10 must be DDRC base address */ + .macro ddrc_enter_self_refresh + + ldr r10, [r0, #PM_INFO_MX7D_DDRC_V_OFFSET] + + /* disable port */ + ldr r7, =0x0 + str r7, [r10, #DDRC_PCTRL_0] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r10, #DDRC_PWRCTL] + + /* wait rw port_busy clear */ + ldr r6, =(0x1 << 16) + orr r6, r6, #0x1 +2: + ldr r7, [r10, #DDRC_PSTAT] + ands r7, r7, r6 + bne 2b + + ldr r7, =0x1 + str r7, [r10, #DDRC_DBG1] + + ldr r6, =0x36000000 +11: + ldr r7, [r10, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 11b + + /* enter self-refresh bit 5 */ + ldr r7, =(0x1 << 5) + str r7, [r10, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +3: + ldr r7, [r10, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 3b +4: + ldr r7, [r10, #DDRC_STAT] + ands r7, r7, #0x20 + beq 4b + + /* disable dram clk */ + ldr r7, [r10, #DDRC_PWRCTL] + orr r7, r7, #(1 << 3) + str r7, [r10, #DDRC_PWRCTL] + + /* + * TO1.1 adds feature of DDR pads power down, + * although TO1.0 has no such function, but it is + * NOT harmful to program GPR registers for TO1.0, + * it can avoid the logic of version check in idle + * thread. + */ + ldr r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET] + ldr r7, =0xf0000 + str r7, [r10] + + /* delay 20us, measured by gpio */ + ldr r7, =20 +12: + subs r7, r7, #0x1 + bne 12b + + .endm + + /* r10 must be DDRC base address */ + .macro ddrc_exit_self_refresh + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET] + + ldr r7, =0x0 + str r7, [r10] + + ldr r7, =20 +13: + subs r7, r7, #0x1 + bne 13b + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_DDRC_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_DDRC_V_OFFSET] + + ldr r7, =0x0 + str r7, [r10, #DDRC_DBG1] + + ldr r6, =0x30000000 +14: + ldr r7, [r10, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 14b + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r10, #DDRC_PWRCTL] + + /* wait until self-refresh mode exited */ +5: + ldr r7, [r10, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + beq 5b + + /* enable auto self-refresh */ + ldr r7, [r10, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r10, #DDRC_PWRCTL] + + ldr r7, =0x1 + str r7, [r10, #DDRC_PCTRL_0] + + .endm + + .macro pll_do_wait_lock +6: + ldr r7, [r10, r8] + ands r7, #0x80000000 + beq 6b + + .endm + + .macro ccm_enter_idle + + ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* ungate pfd1 332m for lower axi */ + ldr r7, =0x8000 + str r7, [r10, #0xc8] + + ldr r10, [r0, #PM_INFO_MX7D_CCM_V_OFFSET] + + /* switch ARM CLK to OSC */ + ldr r8, =0x8000 + ldr r7, [r10, r8] + bic r7, r7, #0x7000000 + str r7, [r10, r8] + + /* lower AXI clk from 24MHz to 3MHz */ + ldr r8, =0x8800 + ldr r7, [r10, r8] + orr r7, r7, #0x7 + str r7, [r10, r8] + + /* lower AHB clk from 24MHz to 3MHz */ + ldr r8, =0x9000 + ldr r7, [r10, r8] + orr r7, r7, #0x7 + str r7, [r10, r8] + + /* gate dram clk */ + ldr r8, =0x9880 + ldr r7, [r10, r8] + bic r7, r7, #0x10000000 + str r7, [r10, r8] + + ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* gate pfd1 332m */ + ldr r7, =0x8000 + str r7, [r10, #0xc4] + + /* gate system pll pfd div 1 */ + ldr r7, =0x10 + str r7, [r10, #0xb4] + /* power down ARM, 480 and DRAM PLL */ + ldr r7, =0x1000 + str r7, [r10, #0x64] + str r7, [r10, #0xb4] + ldr r7, =0x100000 + str r7, [r10, #0x74] + + .endm + + .macro ccm_exit_idle + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* power up ARM, 480 and DRAM PLL */ + ldr r7, =0x1000 + str r7, [r10, #0x68] + ldr r8, =0x60 + pll_do_wait_lock + + ldr r7, =0x1000 + str r7, [r10, #0xb8] + ldr r8, =0xb0 + pll_do_wait_lock + + ldr r7, =0x100000 + str r7, [r10, #0x78] + ldr r8, =0x70 + pll_do_wait_lock + + /* ungate pfd1 332m for lower axi */ + ldr r7, =0x8000 + str r7, [r10, #0xc8] + + /* ungate system pll pfd div 1 */ + ldr r7, =0x10 + str r7, [r10, #0xb8] + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_CCM_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_CCM_V_OFFSET] + + /* switch ARM CLK to PLL */ + ldr r8, =0x8000 + ldr r7, [r10, r8] + orr r7, r7, #0x1000000 + str r7, [r10, r8] + + /* restore AXI clk from 3MHz to 24MHz */ + ldr r8, =0x8800 + ldr r7, [r10, r8] + bic r7, r7, #0x7 + str r7, [r10, r8] + + /* restore AHB clk from 3MHz to 24MHz */ + ldr r8, =0x9000 + ldr r7, [r10, r8] + bic r7, r7, #0x7 + str r7, [r10, r8] + + /* ungate dram clk */ + ldr r8, =0x9880 + ldr r7, [r10, r8] + orr r7, r7, #0x10000000 + str r7, [r10, r8] + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* gate pfd1 332m for lower axi */ + ldr r7, =0x8000 + str r7, [r10, #0xc4] + + .endm + + .macro anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* XTAL to RC-OSC switch */ + ldr r7, [r10] + orr r7, r7, #0x1000 + str r7, [r10] + /* power down XTAL */ + ldr r7, [r10] + orr r7, r7, #0x1 + str r7, [r10] + + /* enable weak 1P0A */ + ldr r7, [r10, #0x200] + orr r7, r7, #0x40000 + str r7, [r10, #0x200] + + /* disable LDO 1P0A */ + ldr r7, [r10, #0x200] + bic r7, r7, #0x1 + str r7, [r10, #0x200] + + /* disable LDO 1P2 */ + ldr r7, [r10, #0x220] + bic r7, r7, #0x1 + str r7, [r10, #0x220] + + /* switch to low power bandgap */ + ldr r7, [r10, #0x270] + orr r7, r7, #0x400 + str r7, [r10, #0x270] + /* power down normal bandgap */ + orr r7, r7, #0x1 + str r7, [r10, #0x270] + + .endm + + .macro anatop_exit_idle + + cmp r5, #0x1 + ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET] + + /* power on normal bandgap */ + ldr r7, [r10, #0x270] + bic r7, r7, #0x1 + str r7, [r10, #0x270] + /* switch to normal bandgap */ + bic r7, r7, #0x400 + str r7, [r10, #0x270] + + /* enable LDO 1P2 */ + ldr r7, [r10, #0x220] + orr r7, r7, #0x1 + str r7, [r10, #0x220] +7: + ldr r7, [r10, #0x220] + ands r7, #0x20000 + beq 7b + + /* enable LDO 1P0A */ + ldr r7, [r10, #0x200] + orr r7, r7, #0x1 + str r7, [r10, #0x200] +9: + ldr r7, [r10, #0x200] + ands r7, #0x20000 + beq 9b + /* disable weak 1P0A */ + ldr r7, [r10, #0x200] + bic r7, r7, #0x40000 + str r7, [r10, #0x200] + + /* power up XTAL and wait */ + ldr r7, [r10] + bic r7, r7, #0x1 + str r7, [r10] +10: + ldr r7, [r10] + ands r7, r7, #0x4 + beq 10b + /* RC-OSC to XTAL switch */ + ldr r7, [r10] + bic r7, r7, #0x1000 + str r7, [r10] + + .endm + +.extern iram_tlb_phys_addr + + .align 3 +ENTRY(imx7d_low_power_idle) + push {r0 - r12} + + /* get necessary info from pm_info */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r5, =imx7d_low_power_idle + ldr r6, =wakeup + sub r6, r6, r5 + add r8, r1, r2 + add r3, r8, r6 + + /* r11 is cpu id */ + mrc p15, 0, r11, c0, c0, 5 + and r11, r11, #3 + cmp r11, #0x0 + ldreq r6, =MX7D_SRC_GPR1 + ldreq r7, =MX7D_SRC_GPR2 + ldrne r6, =MX7D_SRC_GPR3 + ldrne r7, =MX7D_SRC_GPR4 + /* store physical resume addr and pm_info address. */ + ldr r10, [r0, #PM_INFO_MX7D_SRC_V_OFFSET] + str r3, [r10, r6] + str r1, [r10, r7] + + disable_l1_dcache + + tlb_set_to_ocram + + /* check last to sleep */ + ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET] + ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET] + cmp r6, r7 + bne lpi_enter_done + + ddrc_enter_self_refresh + ccm_enter_idle + anatop_enter_idle + + ldr r10, [r0, #PM_INFO_MX7D_GIC_DIST_V_OFFSET] + ldr r7, =0x0 + ldr r8, =0x1000 + str r7, [r10, r8] + + ldr r10, [r0, #PM_INFO_MX7D_GPC_V_OFFSET] + ldr r4, [r10, #MX7D_GPC_IMR1] + ldr r5, [r10, #MX7D_GPC_IMR2] + ldr r6, [r10, #MX7D_GPC_IMR3] + ldr r7, [r10, #MX7D_GPC_IMR4] + + ldr r8, =0xffffffff + str r8, [r10, #MX7D_GPC_IMR1] + str r8, [r10, #MX7D_GPC_IMR2] + str r8, [r10, #MX7D_GPC_IMR3] + str r8, [r10, #MX7D_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 8 (2ms). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~2ms. + */ + ldr r8, [r10, #0x14] + orr r8, r8, #(0x3f << 24) + str r8, [r10, #0x14] + + /* enable the counter. */ + ldr r8, [r10, #0x14] + orr r8, r8, #(0x1 << 30) + str r8, [r10, #0x14] + + /* unmask all the GPC interrupts. */ + str r4, [r10, #MX7D_GPC_IMR1] + str r5, [r10, #MX7D_GPC_IMR2] + str r6, [r10, #MX7D_GPC_IMR3] + str r7, [r10, #MX7D_GPC_IMR4] + + /* + * now delay for a short while (30usec) + * ARM is at 24MHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r4, =5 +rbc_loop: + subs r4, r4, #0x1 + bne rbc_loop + +lpi_enter_done: + + imx_pen_unlock + + wfi + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + imx_pen_lock + + /* check first to wake */ + ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET] + ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET] + cmp r6, r7 + bne skip_lpi_flow + + ldr r5, =0x0 + anatop_exit_idle + ccm_exit_idle + ddrc_exit_self_refresh + + ldr r10, [r0, #PM_INFO_MX7D_GIC_DIST_V_OFFSET] + ldr r7, =0x1 + ldr r8, =0x1000 + str r7, [r10, r8] + +skip_lpi_flow: + tlb_back_to_ddr + +#ifdef CONFIG_SMP + /* Turn on SMP bit. */ + mrc p15, 0, r7, c1, c0, 1 + orr r7, r7, #0x40 + mcr p15, 0, r7, c1, c0, 1 + + isb +#endif + + /* enable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + orr r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + /* Restore registers */ + pop {r0 - r12} + mov pc, lr + +wakeup: + + /* invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 0 + mcr p15, 0, r1, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r1, #0x1800 + mcr p15, 0, r1, c1, c0, 0 + isb + + imx_pen_lock + + /* check first to wake */ + ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET] + ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET] + cmp r6, r7 + bne wakeup_skip_lpi_flow + + ldr r5, =0x1 + anatop_exit_idle + ccm_exit_idle + ddrc_exit_self_refresh + +wakeup_skip_lpi_flow: + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + + /* Restore registers */ + mov pc, lr + .ltorg +ENDPROC(imx7d_low_power_idle) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/Kconfig linux-imx-phytec/arch/arm/mach-imx/Kconfig --- linux-6.1.55/arch/arm/mach-imx/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/Kconfig 2024-06-19 12:33:58.124189556 +0200 @@ -28,9 +28,29 @@ bool select PM_GENERIC_DOMAINS if PM +config HAVE_IMX_GPCV2 + bool + select PM_GENERIC_DOMAINS if PM + config HAVE_IMX_MMDC bool +config HAVE_IMX_AMP + bool + +config HAVE_IMX_DDRC + bool + select HAVE_IMX_BUSFREQ + +config HAVE_IMX_BUSFREQ + bool + +config HAVE_IMX_MU + bool + +config HAVE_IMX_RPMSG + bool + config HAVE_IMX_SRC def_bool y if SMP select ARCH_HAS_RESET_CONTROLLER @@ -168,7 +188,13 @@ select ARM_ERRATA_754322 select ARM_ERRATA_775420 select PINCTRL_IMX6SX + select HAVE_IMX_AMP select SOC_IMX6 + select HAVE_IMX_MU + select IMX_MBOX + select HAVE_IMX_RPMSG + select IMX_SEMA4 + select KEYBOARD_SNVS_PWRKEY help This enables support for Freescale i.MX6 SoloX processor. @@ -204,6 +230,12 @@ select HAVE_IMX_MMDC select HAVE_IMX_SRC select IMX_GPCV2 + select HAVE_IMX_DDRC + select HAVE_IMX_MU + select IMX_MBOX + select HAVE_IMX_RPMSG + select HAVE_IMX_GPCV2 + select KEYBOARD_SNVS_PWRKEY config SOC_IMX7D_CM4 bool diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/lpddr2_freq_imx6q.S linux-imx-phytec/arch/arm/mach-imx/lpddr2_freq_imx6q.S --- linux-6.1.55/arch/arm/mach-imx/lpddr2_freq_imx6q.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/lpddr2_freq_imx6q.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,765 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "hardware.h" + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +.globl mx6q_lpddr2_freq_change_start +.globl mx6q_lpddr2_freq_change_end + + .macro wait_for_ccm_handshake + /* wait for div update */ +1: + ldr r9, [r2, #CCM_CDHIPR] + cmp r9, #0 + bne 1b + + .endm + + .macro set_mmdc_misc_ralat_2_cycles + + /* Set MMDCx_MISC[RALAT] = 2 cycles */ + ldr r6, [r8, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r8, #0x18] + + /* Check if lpddr2 channel 1 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq 1f + + ldr r6, [r4, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r4, #0x18] +1: + .endm + + .macro switch_to_400MHz + /* set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3 */ + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(0x9 << 8) + orr r9, r9, #(1 << 16) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* check periph_clk_sel */ + ldr r9, [r2, #CCM_CBCDR] + and r9, r9, #(1 << 25) + cmp r9, #(1 << 25) + bne skip_periph_clk_switch_400m + + /* now switch periph_clk back. */ + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + +skip_periph_clk_switch_400m: + + .endm + + .macro switch_to_100MHz + /* set the MMDC_DIV=4, AXI_DIV=8, AHB_DIV=8 */ + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(0x1F << 16) + orr r9, r9, #(0x1D << 8) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* check if periph_clk_sel is already set. */ + ldr r9, [r2, #CCM_CBCDR] + and r9, r9, #(1 << 25) + cmp r9, #(1 << 25) + bne skip_periph_clk_switch_100m + + /* now switch periph_clk back. */ + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + +skip_periph_clk_switch_100m: + + .endm + + .macro switch_to_24MHz + /* + * change the freq now try setting DDR to 24MHz. + * source it from the periph_clk2 ensure the + * periph_clk2 is sourced from 24MHz and the + * divider is 1. + */ + + ldr r9, [r2, #CCM_CBCMR] + bic r9, r9, #(0x3 << 12) + orr r9, r9, #(1 << 12) + str r9, [r2, #CCM_CBCMR] + + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(0x7 << 27) + str r9, [r2, #CCM_CBCDR] + + /* now switch periph_clk to 24MHz. */ + ldr r9, [r2, #CCM_CBCDR] + orr r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* change all the dividers to 1. */ + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(1 << 8) + str r9, [r2, #CCM_CBCDR] + + /* Wait for the divider to change. */ + wait_for_ccm_handshake + + .endm + + .macro switch_to_24MHZ_from_pll2 + /* Change DDR freq settings from pll2_pfd2 (div 2) */ + + ldr r9, [r2, #CCM_CBCMR] + bic r9, r9, #(0x3 << 18) + orr r9, r9, #(0x3 << 18) + str r9, [r2, #CCM_CBCMR] + + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(1 << 8) + orr r9, r9, #(0x7 << 19) + str r9, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro set_timings_below_100MHz_operation + set_mmdc_misc_ralat_2_cycles + + /* Adjust LPDDR2 timings for 24Mhz operation */ + ldr r5, =0x03162073 + str r5, [r8, #0xC] /* MMDC0_MDCFG0 */ + ldr r7, =0x00020482 + str r7, [r8, #0x10] /* MMDC0_MDCFG1 */ + ldr r9, =0x00000049 + str r9, [r8, #0x14] /* MMDC0_MDCFG2 */ + ldr r10, =0x00020333 + str r10, [r8, #0x38] /* MMDC0_MDCFG3LP */ + + /* Check if lpddr2 channel 1 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_below_100Mhz_ch1_timings + + str r5, [r4, #0xC] /* MMDC1_MDCFG0 */ + str r7, [r4, #0x10] /* MMDC1_MDCFG1 */ + str r9, [r4, #0x14] /* MMDC1_MDCFG2 */ + str r10, [r4, #0x38] /* MMDC1_MDCFG3LP */ + +skip_below_100Mhz_ch1_timings: + + .endm + + .macro restore_mmdc_settings_info + /* restore timing from mmdc_settings_info */ + ldr r6, [r1, #0x0] + ldr r7, [r1, #0x4] +1: + ldr r9, [r7], #0x4 + ldr r10, [r7], #0x4 + str r10, [r8, r9] + subs r6, r6, #0x1 + bne 1b + + /* Check if lpddr2 channel 1 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq 3f + + ldr r6, [r1, #0x0] + ldr r7, [r1, #0x4] +2: + ldr r9, [r7], #0x4 + ldr r10, [r7], #0x4 + str r10, [r4, r9] + subs r6, r6, #0x1 + bne 2b +3: + + .endm + + .macro mmdc_clk_lower_equal_100MHz + + ldr r10, =100000000 + cmp r0, r10 + beq set_timmings_100MHz + set_timings_below_100MHz_operation + b common_to_lower_equal_100MHz + +set_timmings_100MHz: + restore_mmdc_settings_info + set_mmdc_misc_ralat_2_cycles + +common_to_lower_equal_100MHz: + + /* if MMDC is not in 400MHz mode, skip double mu count */ + ldr r5, [r1, #0x8] + ldr r6, =400000000 + cmp r5, r6 + bne skip_lower_force_measure_ch1 + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r9, =0x3FF + and r6, r6, r9 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r8, r5] + orr r6, r6, #0x400 + str r6, [r8, r5] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r8, r5] + ldr r9, =0x3FF + bic r6, r6, r9 + orr r6, r6, r7 + str r6, [r8, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r8, r5] + orr r6, r6, #0x800 + str r6, [r8, r5] + /* Wait for FRC_MSR to clear. */ +force_measure: + ldr r6, [r8, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_lower_force_measure_ch1 + + ldr r5, =0x8B8 + ldr r6, [r4, r5] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r9, =0x3FF + and r6, r6, r9 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r4, r5] + orr r6, r6, #0x400 + str r6, [r4, r5] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r4, r5] + ldr r9, =0x3FF + bic r6, r6, r9 + orr r6, r6, r7 + str r6, [r4, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r4, r5] + orr r6, r6, #0x800 + str r6, [r4, r5] + /* Wait for FRC_MSR to clear. */ +force_measure_ch1: + ldr r6, [r4, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure_ch1 + +skip_lower_force_measure_ch1: + + .endm + + .macro mmdc_clk_above_100MHz + + restore_mmdc_settings_info + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + bic r6, r6, #0x400 + str r6, [r8, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r8, r5] + orr r6, r6, #0x800 + str r6, [r8, r5] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r8, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_above_force_measure_ch1 + + ldr r5, =0x8B8 + ldr r6, [r4, r5] + bic r6, r6, #0x400 + str r6, [r4, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r4, r5] + orr r6, r6, #0x800 + str r6, [r4, r5] + /* Wait for FRC_MSR to clear. */ +force_measure1_ch1: + ldr r6, [r4, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1_ch1 + +skip_above_force_measure_ch1: + + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + /* disable d-cache */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + dsb + isb + + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + .endm + +/* + * mx6_lpddr2_freq_change + * + * Make sure DDR is in self-refresh. + * IRQs are already disabled. + * r0 : DDR freq. + * r1 : mmdc_settings_info + */ + .align 3 +ENTRY(mx6q_lpddr2_freq_change) +mx6q_lpddr2_freq_change_start: + push {r2-r10} + + /* + * Need to flush and disable L1 before + * disabling L2, we need data to + * coherent. Flushing L1 pushes + * everyhting to L2. We sync L2 later, but + * it can still have dirty lines. + * While exiting, we need to enable L2 first + * and then L1. + */ + disable_l1_dcache + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r6, [r7, #0x730] + cmp r6, #0x0 + bne wait_for_l2_to_idle + + mov r6, #0x0 + str r6, [r7, #0x730] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + /* Disable L2. */ + str r6, [r7, #0x100] +#endif + + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + ldr r4, =IMX_IO_P2V(MX6Q_MMDC_P1_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x01 + str r6, [r8, #0x404] + + /* MMDC0_MDPDC disable power down timer */ + ldr r6, [r8, #0x4] + bic r6, r6, #0xff00 + str r6, [r8, #0x4] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_psd_ch1 + + ldr r6, [r4, #0x404] + orr r6, r6, #0x01 + str r6, [r4, #0x404] + + ldr r6, [r4, #0x4] + bic r6, r6, #0xff00 + str r6, [r4, #0x4] + +skip_psd_ch1: + /* Delay for a while */ + ldr r10, =10 +delay1: + ldr r7, =0 +cont1: + ldr r6, [r8, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont1 + sub r10, r10, #1 + cmp r10, #0 + bgt delay1 + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_set_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r8, #0x410] + orr r6, r6, #0x100 + str r6, [r8, #0x410] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_sbs_ch1 + + ldr r6, [r4, #0x404] + orr r6, r6, #0x200000 + str r6, [r4, #0x404] + +poll_dvfs_set_2: + ldr r6, [r4, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_2 + + ldr r6, [r4, #0x410] + orr r6, r6, #0x100 + str r6, [r4, #0x410] + +skip_sbs_ch1: + ldr r10, =100000000 + cmp r0, r10 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_equal_100MHz + +set_ddr_mu_above_100: + ldr r10, =24000000 + cmp r0, r10 + beq set_to_24MHz + + ldr r10, =100000000 + cmp r0, r10 + beq set_to_100MHz + + ldr r10, =400000000 + cmp r0, r10 + switch_to_400MHz + b done + +set_to_24MHz: +/* + switch_to_24MHZ_from_pll2 +*/ + switch_to_24MHz + b done + +set_to_100MHz: + switch_to_100MHz + +done: + + ldr r10,=100000000 + cmp r0, r10 + ble skip_mmdc_clk_check + mmdc_clk_above_100MHz + +skip_mmdc_clk_check: + + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_clear_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x01 + str r6, [r8, #0x404] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_enable_psd_ch1 + + ldr r6, [r4, #0x404] + bic r6, r6, #0x200000 + str r6, [r4, #0x404] + +poll_dvfs_clear_2: + ldr r6, [r4, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_2 + + ldr r6, [r4, #0x404] + bic r6, r6, #0x01 + str r6, [r4, #0x404] + +skip_enable_psd_ch1: + ldr r10, =24000000 + cmp r0, r10 + beq skip_power_down + + /* Enable MMDC power down timer. */ + ldr r6, [r8, #0x4] + orr r6, r6, #0x5500 + str r6, [r8, #0x4] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_power_down + + ldr r6, [r4, #0x4] + orr r6, r6, #0x5500 + str r6, [r4, #0x4] + +skip_power_down: + /* clear SBS - unblock DDR accesses */ + ldr r6, [r8, #0x410] + bic r6, r6, #0x100 + str r6, [r8, #0x410] + + /* Check if lpddr2 channel 2 is enabled */ + ldr r6, [r8, #0x18] + ands r6, r6, #(1 << 2) + beq skip_disable_sbs_ch1 + + ldr r6, [r4, #0x410] + bic r6, r6, #0x100 + str r6, [r4, #0x410] + +skip_disable_sbs_ch1: +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2. */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r6, =0x1 + str r6, [r7, #0x100] +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + pop {r2-r10} + + /* Restore registers */ + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +mx6q_lpddr2_freq_change_end: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/lpddr2_freq_imx6.S linux-imx-phytec/arch/arm/mach-imx/lpddr2_freq_imx6.S --- linux-6.1.55/arch/arm/mach-imx/lpddr2_freq_imx6.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/lpddr2_freq_imx6.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,618 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define PL310_AUX_CTRL 0x104 +#define PL310_DCACHE_LOCKDOWN_BASE 0x900 +#define PL310_AUX_16WAY_BIT 0x10000 +#define PL310_LOCKDOWN_NBREGS 8 +#define PL310_LOCKDOWN_SZREG 4 +#define PL310_8WAYS_MASK 0x00FF +#define PL310_16WAYS_UPPERMASK 0xFF00 + +.globl imx6_lpddr2_freq_change_start +.globl imx6_lpddr2_freq_change_end + + .macro mx6sl_switch_to_24MHz + + /* + * Set MMDC clock to be sourced from PLL3. + * Ensure first periph2_clk2 is sourced from PLL3. + * Set the PERIPH2_CLK2_PODF to divide by 2. + */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x7 + orr r6, r6, #0x1 + str r6, [r2, #0x14] + + /* Select PLL3 to source MMDC. */ + ldr r6, [r2, #0x18] + bic r6, r6, #0x100000 + str r6, [r2, #0x18] + + /* Swtich periph2_clk_sel to run from PLL3. */ + ldr r6, [r2, #0x14] + orr r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch1: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch1 + + /* + * Need to clock gate the 528 PFDs before + * powering down PLL2. + * Only the PLL2_PFD2_400M should be ON + * at this time, so only clock gate that one. + */ + ldr r6, [r3, #0x100] + orr r6, r6, #0x800000 + str r6, [r3, #0x100] + + /* + * Set PLL2 to bypass state. We should be here + * only if MMDC is not sourced from PLL2. + */ + ldr r6, [r3, #0x30] + orr r6, r6, #0x10000 + str r6, [r3, #0x30] + + ldr r6, [r3, #0x30] + orr r6, r6, #0x1000 + str r6, [r3, #0x30] + + /* Ensure pre_periph2_clk_mux is set to pll2 */ + ldr r6, [r2, #0x18] + bic r6, r6, #0x600000 + str r6, [r2, #0x18] + + /* Set MMDC clock to be sourced from the bypassed PLL2. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch2: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch2 + + /* + * Now move MMDC back to periph2_clk2 source. + * after selecting PLL2 as the option. + * Select PLL2 as the source. + */ + ldr r6, [r2, #0x18] + orr r6, r6, #0x100000 + str r6, [r2, #0x18] + + /* set periph2_clk2_podf to divide by 1. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x7 + str r6, [r2, #0x14] + + /* Now move periph2_clk to periph2_clk2 source */ + ldr r6, [r2, #0x14] + orr r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch3: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch3 + + /* Now set the MMDC PODF back to 1.*/ + ldr r6, [r2, #0x14] + bic r6, r6, #0x38 + str r6, [r2, #0x14] + +mmdc_podf0: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne mmdc_podf0 + + .endm + + .macro ddr_switch_400MHz + + /* Set MMDC divider first, in case PLL3 is at 480MHz. */ + ldr r6, [r3, #0x10] + and r6, r6, #0x10000 + cmp r6, #0x10000 + beq pll3_in_bypass + + /* Set MMDC divder to divide by 2. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x38 + orr r6, r6, #0x8 + str r6, [r2, #0x14] + +mmdc_podf: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne mmdc_podf + +pll3_in_bypass: + /* + * Check if we are switching between + * 400Mhz <-> 100MHz.If so, we should + * try to source MMDC from PLL2_200M. + */ + cmp r1, #0 + beq not_low_bus_freq + + /* Ensure that MMDC is sourced from PLL2 mux first. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch4: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch4 + +not_low_bus_freq: + /* Now ensure periph2_clk2_sel mux is set to PLL3 */ + ldr r6, [r2, #0x18] + bic r6, r6, #0x100000 + str r6, [r2, #0x18] + + /* Now switch MMDC to PLL3. */ + ldr r6, [r2, #0x14] + orr r6, r6, #0x4000000 + str r6, [r2, #0x14] + +periph2_clk_switch5: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne periph2_clk_switch5 + + /* + * Check if PLL2 is already unlocked. + * If so do nothing with PLL2. + */ + cmp r1, #0 + beq pll2_already_on + + /* Now power up PLL2 and unbypass it. */ + ldr r6, [r3, #0x30] + bic r6, r6, #0x1000 + str r6, [r3, #0x30] + + /* Make sure PLL2 has locked.*/ +wait_for_pll_lock: + ldr r6, [r3, #0x30] + and r6, r6, #0x80000000 + cmp r6, #0x80000000 + bne wait_for_pll_lock + + ldr r6, [r3, #0x30] + bic r6, r6, #0x10000 + str r6, [r3, #0x30] + + /* + * Need to enable the 528 PFDs after + * powering up PLL2. + * Only the PLL2_PFD2_400M should be ON + * as it feeds the MMDC. Rest should have + * been managed by clock code. + */ + ldr r6, [r3, #0x100] + bic r6, r6, #0x800000 + str r6, [r3, #0x100] + +pll2_already_on: + /* + * Now switch MMDC clk back to pll2_mux option. + * Ensure pre_periph2_clk2 is set to pll2_pfd_400M. + * If switching to audio DDR freq, set the + * pre_periph2_clk2 to PLL2_PFD_200M + */ + ldr r6, =400000000 + cmp r6, r0 + bne use_pll2_pfd_200M + + ldr r6, [r2, #0x18] + bic r6, r6, #0x600000 + orr r6, r6, #0x200000 + str r6, [r2, #0x18] + ldr r6, =400000000 + b cont2 + +use_pll2_pfd_200M: + ldr r6, [r2, #0x18] + orr r6, r6, #0x600000 + str r6, [r2, #0x18] + ldr r6, =200000000 + +cont2: + ldr r4, [r2, #0x14] + bic r4, r4, #0x4000000 + str r4, [r2, #0x14] + +periph2_clk_switch6: + ldr r4, [r2, #0x48] + cmp r4, #0 + bne periph2_clk_switch6 + +change_divider_only: + /* + * Calculate the MMDC divider + * based on the requested freq. + */ + ldr r4, =0 +Loop2: + sub r6, r6, r0 + cmp r6, r0 + blt Div_Found + add r4, r4, #1 + bgt Loop2 + + /* Shift divider into correct offset. */ + lsl r4, r4, #3 +Div_Found: + /* Set the MMDC PODF. */ + ldr r6, [r2, #0x14] + bic r6, r6, #0x38 + orr r6, r6, r4 + str r6, [r2, #0x14] + +mmdc_podf1: + ldr r6, [r2, #0x48] + cmp r6, #0 + bne mmdc_podf1 + + .endm + + .macro mmdc_clk_lower_100MHz + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r4, =0x3FF + and r6, r6, r4 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r8, r5] + orr r6, r6, #0x400 + str r6, [r8, r5] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r8, r5] + ldr r4, =0x3FF + bic r6, r6, r4 + orr r6, r6, r7 + str r6, [r8, r5] + + .endm + + .macro mmdc_clk_above_100MHz + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r5, =0x8B8 + ldr r6, [r8, r5] + bic r6, r6, #0x400 + str r6, [r8, r5] + /* Now perform a Force Measurement. */ + ldr r6, [r8, r5] + orr r6, r6, #0x800 + str r6, [r8, r5] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r8, r5] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + .endm + +/* + * mx6_lpddr2_freq_change + * + * Make sure DDR is in self-refresh. + * IRQs are already disabled. + * r0 : DDR freq. + * r1: low_bus_freq_mode flag + */ + .align 3 +ENTRY(mx6_lpddr2_freq_change) +imx6_lpddr2_freq_change_start: + push {r4-r10} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + + /* Wait for background operations to complete. */ +wait_for_l2_to_idle: + ldr r6, [r7, #0x730] + cmp r6, #0x0 + bne wait_for_l2_to_idle + + mov r6, #0x0 + str r6, [r7, #0x730] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r3, #PL310_8WAYS_MASK + orrne r3, #PL310_16WAYS_UPPERMASK + mov r6, #PL310_LOCKDOWN_NBREGS + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x01 + str r6, [r8, #0x404] + + /* MMDC0_MDPDC disable power down timer */ + ldr r6, [r8, #0x4] + bic r6, r6, #0xff00 + str r6, [r8, #0x4] + + /* Delay for a while */ + ldr r10, =10 +delay1: + ldr r7, =0 +cont1: + ldr r6, [r8, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont1 + sub r10, r10, #1 + cmp r10, #0 + bgt delay1 + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r8, #0x404] + orr r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_set_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r8, #0x410] + orr r6, r6, #0x100 + str r6, [r8, #0x410] + + ldr r10, =100000000 + cmp r0, r10 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_100MHz + +set_ddr_mu_above_100: + ldr r10, =24000000 + cmp r0, r10 + beq set_to_24MHz + + ddr_switch_400MHz + + ldr r10,=100000000 + cmp r0, r10 + blt done + mmdc_clk_above_100MHz + + b done + +set_to_24MHz: + mx6sl_switch_to_24MHz + +done: + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x200000 + str r6, [r8, #0x404] + +poll_dvfs_clear_1: + ldr r6, [r8, #0x404] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r8, #0x404] + bic r6, r6, #0x01 + str r6, [r8, #0x404] + + ldr r10, =24000000 + cmp r0, r10 + beq skip_power_down + + /* Enable MMDC power down timer. */ + ldr r6, [r8, #0x4] + orr r6, r6, #0x5500 + str r6, [r8, #0x4] + +skip_power_down: + /* clear SBS - unblock DDR accesses */ + ldr r6, [r8, #0x410] + bic r6, r6, #0x100 + str r6, [r8, #0x410] + +#ifdef CONFIG_CACHE_L2X0 + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r6, #PL310_LOCKDOWN_NBREGS + mov r3, #0x00 /* 8 ways mask */ + orrne r3, #0x0000 /* 16 ways mask */ + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + pop {r4-r10} + + /* Restore registers */ + mov pc, lr + + /* + * Add ltorg here to ensure that all + * literals are stored here and are + * within the text space. + */ + .ltorg +imx6_lpddr2_freq_change_end: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/lpddr2_freq_imx6sll.S linux-imx-phytec/arch/arm/mach-imx/lpddr2_freq_imx6sll.S --- linux-6.1.55/arch/arm/mach-imx/lpddr2_freq_imx6sll.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/lpddr2_freq_imx6sll.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,456 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 +#define PL310_AUX_CTRL 0x104 +#define PL310_DCACHE_LOCKDOWN_BASE 0x900 +#define PL310_AUX_16WAY_BIT 0x10000 +#define PL310_LOCKDOWN_NBREGS 8 +#define PL310_LOCKDOWN_SZREG 4 +#define PL310_8WAYS_MASK 0x00FF +#define PL310_16WAYS_UPPERMASK 0xFF00 + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 + +#define HIGH_BUS_MODE 0x0 + + .macro wait_for_ccm_handshake + +1: + ldr r8, [r2, #CCM_CDHIPR] + cmp r8, #0 + bne 1b + + .endm + + .macro switch_to_24MHz + + /* periph2_clk2 sel to OSC_CLK */ + ldr r8, [r2, #CCM_CBCMR] + orr r8, r8, #(1 << 20) + str r8, [r2, #CCM_CBCMR] + + /* periph2_clk2_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #0x7 + str r8, [r2, #CCM_CBCDR] + + /* periph2_clk sel to periph2_clk2 */ + ldr r8, [r2, #CCM_CBCDR] + orr r8, r8, #(0x1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_100MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_100m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SLL, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_100m: + + /* fabric_mmdc_podf to 3 so that mmdc is 400 / 4 = 100MHz */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + orr r8, r8, #(0x3 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_400MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_400m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SLL, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_400m: + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro mmdc_clk_lower_100MHz + /* if MMDC is not in 400MHz mode, skip double mu count */ + cmp r1, #HIGH_BUS_MODE + bne 1f + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r4, =0x3FF + and r6, r6, r4 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r5, r8] + orr r6, r6, #0x400 + str r6, [r5, r8] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r5, r8] + ldr r4, =0x3FF + bic r6, r6, r4 + orr r6, r6, r7 + str r6, [r5, r8] + + /* For freq lower than 100MHz, need to set RALAT to 2 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r5, #0x18] +1: + .endm + + .macro mmdc_clk_above_100MHz + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + bic r6, r6, #0x400 + str r6, [r5, r8] + /* Now perform a Force Measurement. */ + ldr r6, [r5, r8] + orr r6, r6, #0x800 + str r6, [r5, r8] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r5, r8] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + + /* For freq higher than 100MHz, need to set RALAT to 5 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x5 << 6) + str r6, [r5, #0x18] + + .endm + + .align 3 +/* + * Below code can be used by i.MX6SLL when changing the + * frequency of MMDC. the MMDC is the same on these two SOCs. + */ +ENTRY(imx6sll_lpddr2_freq_change) + push {r2 - r8} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + mov r6, #0x0 + str r6, [r7, #L2_CACHE_SYNC] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r3, #PL310_8WAYS_MASK + orrne r3, #PL310_16WAYS_UPPERMASK + mov r6, #PL310_LOCKDOWN_NBREGS + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + /* Delay for a while */ + ldr r8, =10 +delay: + ldr r7, =0 +cont: + ldr r6, [r5, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont + sub r8, r8, #1 + cmp r8, #0 + bgt delay + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_set_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r5, #MMDC0_MADPCR0] + orr r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + + ldr r6, =100000000 + cmp r0, r6 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_100MHz + +set_ddr_mu_above_100: + ldr r6, =24000000 + cmp r0, r6 + beq set_to_24MHz + + ldr r6, =100000000 + cmp r0, r6 + beq set_to_100MHz + + switch_to_400MHz + + mmdc_clk_above_100MHz + + b done + +set_to_24MHz: + switch_to_24MHz + b done +set_to_100MHz: + switch_to_100MHz +done: + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + /* clear SBS - unblock DDR accesses */ + ldr r6, [r5, #MMDC0_MADPCR0] + bic r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + +#ifdef CONFIG_CACHE_L2X0 + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r6, #PL310_LOCKDOWN_NBREGS + mov r3, #0x00 /* 8 ways mask */ + orrne r3, #0x0000 /* 16 ways mask */ + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r8} + mov pc, lr diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/lpddr2_freq_imx6sx.S linux-imx-phytec/arch/arm/mach-imx/lpddr2_freq_imx6sx.S --- linux-6.1.55/arch/arm/mach-imx/lpddr2_freq_imx6sx.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/lpddr2_freq_imx6sx.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,492 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1c +#define CCM_CDHIPR 0x48 + +#define L2_CACHE_SYNC 0x730 +#define PL310_AUX_CTRL 0x104 +#define PL310_DCACHE_LOCKDOWN_BASE 0x900 +#define PL310_AUX_16WAY_BIT 0x10000 +#define PL310_LOCKDOWN_NBREGS 8 +#define PL310_LOCKDOWN_SZREG 4 +#define PL310_8WAYS_MASK 0x00FF +#define PL310_16WAYS_UPPERMASK 0xFF00 + +#define MMDC0_MDPDC 0x4 +#define MMDC0_MAPSR 0x404 +#define MMDC0_MADPCR0 0x410 + +#define HIGH_BUS_MODE 0x0 + + /* Check if the cpu is cortex-a7 */ + .macro is_ca7 + + /* Read the primary cpu number is MPIDR */ + mrc p15, 0, r6, c0, c0, 0 + ldr r7, =0xfff0 + and r6, r6, r7 + ldr r7, =0xc070 + cmp r6, r7 + + .endm + + .macro wait_for_ccm_handshake + +1: + ldr r8, [r2, #CCM_CDHIPR] + cmp r8, #0 + bne 1b + + .endm + + .macro switch_to_24MHz + + /* periph2_clk2 sel to OSC_CLK */ + ldr r8, [r2, #CCM_CBCMR] + orr r8, r8, #(1 << 20) + str r8, [r2, #CCM_CBCMR] + + /* periph2_clk2_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #0x7 + str r8, [r2, #CCM_CBCDR] + + /* periph2_clk sel to periph2_clk2 */ + ldr r8, [r2, #CCM_CBCDR] + orr r8, r8, #(0x1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_100MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_100m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_100m: + + /* fabric_mmdc_podf to 3 so that mmdc is 400 / 4 = 100MHz */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + orr r8, r8, #(0x3 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro switch_to_400MHz + + /* check whether periph2_clk is from top path */ + ldr r8, [r2, #CCM_CBCDR] + ands r8, #(1 << 26) + beq skip_periph2_clk2_switch_400m + + /* now switch periph2_clk back. */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(1 << 26) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + /* + * on i.MX6SX, pre_periph2_clk will be always from + * pll2_pfd2, so no need to set pre_periph2_clk + * parent, just set the mmdc divider directly. + */ +skip_periph2_clk2_switch_400m: + + /* fabric_mmdc_podf to 0 */ + ldr r8, [r2, #CCM_CBCDR] + bic r8, r8, #(0x7 << 3) + str r8, [r2, #CCM_CBCDR] + + wait_for_ccm_handshake + + .endm + + .macro mmdc_clk_lower_100MHz + /* if MMDC is not in 400MHz mode, skip double mu count */ + cmp r1, #HIGH_BUS_MODE + bne 1f + + /* + * Prior to reducing the DDR frequency (at 528/400 MHz), + * read the Measure unit count bits (MU_UNIT_DEL_NUM) + */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + /* Original MU unit count */ + mov r6, r6, LSR #16 + ldr r4, =0x3FF + and r6, r6, r4 + /* Original MU unit count * 2 */ + mov r7, r6, LSL #1 + /* + * Bypass the automatic measure unit when below 100 MHz + * by setting the Measure unit bypass enable bit (MU_BYP_EN) + */ + ldr r6, [r5, r8] + orr r6, r6, #0x400 + str r6, [r5, r8] + /* + * Double the measure count value read in step 1 and program it in the + * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit + * Register for the reduced frequency operation below 100 MHz + */ + ldr r6, [r5, r8] + ldr r4, =0x3FF + bic r6, r6, r4 + orr r6, r6, r7 + str r6, [r5, r8] + + /* For freq lower than 100MHz, need to set RALAT to 2 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x2 << 6) + str r6, [r5, #0x18] +1: + .endm + + .macro mmdc_clk_above_100MHz + + /* Make sure that the PHY measurement unit is NOT in bypass mode */ + ldr r8, =0x8B8 + ldr r6, [r5, r8] + bic r6, r6, #0x400 + str r6, [r5, r8] + /* Now perform a Force Measurement. */ + ldr r6, [r5, r8] + orr r6, r6, #0x800 + str r6, [r5, r8] + /* Wait for FRC_MSR to clear. */ +force_measure1: + ldr r6, [r5, r8] + and r6, r6, #0x800 + cmp r6, #0x0 + bne force_measure1 + + /* For freq higher than 100MHz, need to set RALAT to 5 */ + ldr r6, [r5, #0x18] + bic r6, r6, #(0x7 << 6) + orr r6, r6, #(0x5 << 6) + str r6, [r5, #0x18] + + .endm + + .align 3 +/* + * Below code can be used by i.MX6SX and i.MX6UL when changing the + * frequency of MMDC. the MMDC is the same on these two SOCs. + */ +ENTRY(imx6_up_lpddr2_freq_change) + + push {r2 - r8} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + is_ca7 + beq skip_disable_l2 + +#ifdef CONFIG_CACHE_L2X0 + /* + * Need to make sure the buffers in L2 are drained. + * Performing a sync operation does this. + */ + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + mov r6, #0x0 + str r6, [r7, #L2_CACHE_SYNC] + + /* + * The second dsb might be needed to keep cache sync (device write) + * ordering with the memory accesses before it. + */ + dsb + isb + + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r3, #PL310_8WAYS_MASK + orrne r3, #PL310_16WAYS_UPPERMASK + mov r6, #PL310_LOCKDOWN_NBREGS + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + +skip_disable_l2: + ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) + + /* Disable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + /* MMDC0_MDPDC disable power down timer */ + ldr r6, [r5, #MMDC0_MDPDC] + bic r6, r6, #0xff00 + str r6, [r5, #MMDC0_MDPDC] + + /* Delay for a while */ + ldr r8, =10 +delay: + ldr r7, =0 +cont: + ldr r6, [r5, r7] + add r7, r7, #4 + cmp r7, #16 + bne cont + sub r8, r8, #1 + cmp r8, #0 + bgt delay + + /* Make the DDR explicitly enter self-refresh. */ + ldr r6, [r5, #MMDC0_MAPSR] + orr r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_set_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + bne poll_dvfs_set_1 + + /* set SBS step-by-step mode */ + ldr r6, [r5, #MMDC0_MADPCR0] + orr r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + + ldr r6, =100000000 + cmp r0, r6 + bgt set_ddr_mu_above_100 + mmdc_clk_lower_100MHz + +set_ddr_mu_above_100: + ldr r6, =24000000 + cmp r0, r6 + beq set_to_24MHz + + ldr r6, =100000000 + cmp r0, r6 + beq set_to_100MHz + + switch_to_400MHz + + mmdc_clk_above_100MHz + + b done + +set_to_24MHz: + switch_to_24MHz + b done +set_to_100MHz: + switch_to_100MHz +done: + /* clear DVFS - exit from self refresh mode */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x200000 + str r6, [r5, #MMDC0_MAPSR] + +poll_dvfs_clear_1: + ldr r6, [r5, #MMDC0_MAPSR] + and r6, r6, #0x2000000 + cmp r6, #0x2000000 + beq poll_dvfs_clear_1 + + /* Enable Automatic power savings. */ + ldr r6, [r5, #MMDC0_MAPSR] + bic r6, r6, #0x1 + str r6, [r5, #MMDC0_MAPSR] + + ldr r6, =24000000 + cmp r0, r6 + beq skip_power_down + + /* Enable MMDC power down timer. */ + ldr r6, [r5, #MMDC0_MDPDC] + orr r6, r6, #0x5500 + str r6, [r5, #MMDC0_MDPDC] + +skip_power_down: + /* clear SBS - unblock DDR accesses */ + ldr r6, [r5, #MMDC0_MADPCR0] + bic r6, r6, #0x100 + str r6, [r5, #MMDC0_MADPCR0] + + is_ca7 + beq skip_enable_l2 + +#ifdef CONFIG_CACHE_L2X0 + ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR) + ldr r3, [r7, #PL310_AUX_CTRL] + tst r3, #PL310_AUX_16WAY_BIT + mov r6, #PL310_LOCKDOWN_NBREGS + mov r3, #0x00 /* 8 ways mask */ + orrne r3, #0x0000 /* 16 ways mask */ + add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE +1: /* lock Dcache and Icache */ + str r3, [r5], #PL310_LOCKDOWN_SZREG + str r3, [r5], #PL310_LOCKDOWN_SZREG + subs r6, r6, #1 + bne 1b +#endif + +skip_enable_l2: + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r8} + mov pc, lr diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/lpddr3_freq_imx.S linux-imx-phytec/arch/arm/mach-imx/lpddr3_freq_imx.S --- linux-6.1.55/arch/arm/mach-imx/lpddr3_freq_imx.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/lpddr3_freq_imx.S 2024-06-19 12:33:58.128189625 +0200 @@ -0,0 +1,444 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "hardware.h" + +#define DDRC_MSTR 0x0 +#define DDRC_STAT 0x4 +#define DDRC_PWRCTL 0x30 +#define DDRC_RFSHTMG 0x64 +#define DDRC_DBG1 0x304 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 +#define DDRC_DFIMISC 0x1b0 +#define DDRC_DBGCAM 0x308 +#define DDRC_SWCTL 0x320 +#define DDRC_SWSTAT 0x324 +#define DDRPHY_LP_CON0 0x18 +#define IOMUXC_GPR8 0x20 +#define DDRPHY_PHY_CON1 0x4 +#define DDRPHY_MDLL_CON0 0xb0 +#define DDRPHY_MDLL_CON1 0xb4 +#define DDRPHY_OFFSETD_CON0 0x50 +#define DDRPHY_OFFSETR_CON0 0x20 +#define DDRPHY_OFFSETR_CON1 0x24 +#define DDRPHY_OFFSETR_CON2 0x28 +#define DDRPHY_OFFSETW_CON0 0x30 +#define DDRPHY_OFFSETW_CON1 0x34 +#define DDRPHY_OFFSETW_CON2 0x38 +#define DDRPHY_RFSHTMG 0x64 +#define DDRPHY_CA_WLDSKEW_CON0 0x6c +#define DDRPHY_CA_DSKEW_CON0 0x7c +#define DDRPHY_CA_DSKEW_CON1 0x80 +#define DDRPHY_CA_DSKEW_CON2 0x84 + +#define ANADIG_DIGPROG 0x800 + + .align 3 + + .macro ddrc_prepare + + /* disable port */ + ldr r7, =0x0 + str r7, [r4, #DDRC_PCTRL_0] + + /* wait port busy done */ + ldr r6, =0x10001 +1: + ldr r7, [r4, #DDRC_PSTAT] + and r7, r7, r6 + cmp r7, #0 + bne 1b + + ldr r7, =0x20 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x23 +2: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + bne 2b + + ldr r7, =0x1 + str r7, [r4, #DDRC_DBG1] + + ldr r6, =0x30000000 +3: + ldr r7, [r4, #DDRC_DBGCAM] + and r7, r7, r6 + cmp r7, r6 + bne 3b + + ldr r7, =0x0 + str r7, [r4, #DDRC_SWCTL] + + ldr r7, =0x0 + str r7, [r4, #DDRC_DFIMISC] + + ldr r7, =0x1 + str r7, [r4, #DDRC_SWCTL] + + ldr r6, =0x1 +4: + ldr r7, [r4, #DDRC_SWSTAT] + and r7, r7, r6 + cmp r7, r6 + bne 4b + + .endm + + .macro ddrc_done + + ldr r7, =0x0 + str r7, [r4, #DDRC_PWRCTL] + + ldr r6, =0x3 +5: + ldr r7, [r4, #DDRC_STAT] + and r7, r7, r6 + cmp r7, r6 + beq 5b + + ldr r7, =0x0 + str r7, [r4, #DDRC_DBG1] + + ldr r7, =0x1 + str r7, [r4, #DDRC_PCTRL_0] + + /* enable auto self-refresh */ + ldr r7, [r4, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r4, #DDRC_PWRCTL] + + .endm + + .macro switch_to_below_100m + + /* LPDDR2 and LPDDR3 has different setting */ + ldr r8, [r4, #DDRC_MSTR] + ands r8, r8, #0x4 + bne 9f + + /* LPDDR3 */ + ldr r7, =0x00000100 + str r7, [r5, #DDRPHY_PHY_CON1] + b 10f +9: + /* LPDDR2 */ + ldr r7, =0x10010100 + str r7, [r5, #DDRPHY_PHY_CON1] +10: + ldr r6, =24000000 + cmp r0, r6 + beq 16f + + ldr r7, =0x0005000B + str r7, [r4, #DDRC_RFSHTMG] + b 6f +16: + ldr r7, =0x00010003 + str r7, [r4, #DDRC_RFSHTMG] + + /* dram alt sel set to OSC */ + ldr r7, =0x10000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 1 */ + ldr r7, =0x11000000 + ldr r8, =0x9880 + str r7, [r2, r8] + b 7f + +6: + /* dram alt sel set to pfd0_392m */ + ldr r7, =0x15000000 + ldr r8, =0xa080 + str r7, [r2, r8] + /* dram root set to from dram alt, div by 4 */ + ldr r7, =0x11000003 + ldr r8, =0x9880 + str r7, [r2, r8] +7: + ldr r7, =0x202ffd0 + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x7f7f7f7f + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 11f + + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + ldr r7, =0x60606060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x00006060 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + b 12f +11: + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +12: + ldr r7, =0x100007f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x7f + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + .endm + + .macro switch_to_533m + + ldr r7, =0x10210100 + str r7, [r5, #DDRPHY_PHY_CON1] + + ldr r7, =0x00200038 + str r7, [r4, #DDRC_RFSHTMG] + + /* dram root set to from dram main, div by 2 */ + ldr r7, =0x10000001 + ldr r8, =0x9880 + str r7, [r2, r8] + + ldr r7, =0x1010007e + str r7, [r5, #DDRPHY_MDLL_CON0] + + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETR_CON0] + str r7, [r5, #DDRPHY_OFFSETR_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETR_CON2] + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_OFFSETW_CON0] + str r7, [r5, #DDRPHY_OFFSETW_CON1] + ldr r7, =0x8 + str r7, [r5, #DDRPHY_OFFSETW_CON2] + + /* LPDDR2 and LPDDR3 has different setting */ + ldr r8, [r4, #DDRC_MSTR] + ands r8, r8, #0x4 + beq 15f + + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 14f + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x0a0a0808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + ldr r7, =0x0a0a0a0a + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + b 14f +15: + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x11 + bne 13f + + ldr r7, =0x1c1c1c1c + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x30301c1c + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + ldr r7, =0x30303030 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + b 14f +13: + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x0808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +14: + ldr r7, =0x11000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + ldr r7, =0x10000008 + str r7, [r5, #DDRPHY_OFFSETD_CON0] + + ldr r6, =0x4 +8: + ldr r7, [r5, #DDRPHY_MDLL_CON1] + and r7, r7, r6 + cmp r7, r6 + bne 8b + + .endm + +ENTRY(imx_lpddr3_freq_change) + push {r2 - r9} + + /* + * To ensure no page table walks occur in DDR, we + * have a another page table stored in IRAM that only + * contains entries pointing to IRAM, AIPS1 and AIPS2. + * We need to set the TTBR1 to the new IRAM TLB. + * Do the following steps: + * 1. Flush the Branch Target Address Cache (BTAC) + * 2. Set TTBR1 to point to IRAM page table. + * 3. Disable page table walks in TTBR0 (PD0 = 1) + * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0 + * and 2-4G is translated by TTBR1. + */ + + ldr r6, =iram_tlb_phys_addr + ldr r7, [r6] + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r7, c2, c0, 1 + + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + ldr r2, =IMX_IO_P2V(MX7D_CCM_BASE_ADDR) + ldr r3, =IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR) + ldr r4, =IMX_IO_P2V(MX7D_DDRC_BASE_ADDR) + ldr r5, =IMX_IO_P2V(MX7D_DDRC_PHY_BASE_ADDR) + ldr r9, =IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR) + + ddrc_prepare + + ldr r6, =100000000 + cmp r0, r6 + bgt set_to_533m + +set_to_below_100m: + switch_to_below_100m + b done + +set_to_533m: + switch_to_533m + b done + +done: + ddrc_done + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + /* Restore the TTBCR */ + dsb + isb + + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + dsb + isb + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + /* Restore registers */ + pop {r2 - r9} + mov pc, lr +ENDPROC(imx_lpddr3_freq_change) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mach-imx6q.c linux-imx-phytec/arch/arm/mach-imx/mach-imx6q.c --- linux-6.1.55/arch/arm/mach-imx/mach-imx6q.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/mach-imx6q.c 2024-06-19 12:33:58.132189693 +0200 @@ -125,6 +125,37 @@ of_node_put(np); } +static void __init imx6q_csi_mux_init(void) +{ + /* + * MX6Q SabreSD board: + * IPU1 CSI0 connects to parallel interface. + * Set GPR1 bit 19 to 0x1. + * + * MX6DL SabreSD board: + * IPU1 CSI0 connects to parallel interface. + * Set GPR13 bit 0-2 to 0x4. + * IPU1 CSI1 connects to MIPI CSI2 virtual channel 1. + * Set GPR13 bit 3-5 to 0x1. + */ + struct regmap *gpr; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + if (of_machine_is_compatible("fsl,imx6q-sabresd") || + of_machine_is_compatible("fsl,imx6q-sabreauto") || + of_machine_is_compatible("fsl,imx6qp-sabresd") || + of_machine_is_compatible("fsl,imx6qp-sabreauto")) + regmap_update_bits(gpr, IOMUXC_GPR1, 1 << 19, 1 << 19); + else if (of_machine_is_compatible("fsl,imx6dl-sabresd") || + of_machine_is_compatible("fsl,imx6dl-sabreauto")) + regmap_update_bits(gpr, IOMUXC_GPR13, 0x3F, 0x0C); + } else { + pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n", + __func__); + } +} + static void __init imx6q_axi_init(void) { struct regmap *gpr; @@ -176,6 +207,7 @@ of_platform_default_populate(NULL, NULL, NULL); imx_anatop_init(); + imx6q_csi_mux_init(); cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); imx6q_1588_init(); imx6q_axi_init(); @@ -201,6 +233,8 @@ { debug_ll_io_init(); imx_scu_map_io(); + imx6_pm_map_io(); + imx_busfreq_map_io(); } static void __init imx6q_init_irq(void) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mach-imx6sl.c linux-imx-phytec/arch/arm/mach-imx/mach-imx6sl.c --- linux-6.1.55/arch/arm/mach-imx/mach-imx6sl.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/mach-imx6sl.c 2024-06-19 12:33:58.132189693 +0200 @@ -15,7 +15,7 @@ #include "cpuidle.h" #include "hardware.h" -static void __init imx6sl_fec_init(void) +static void __init imx6sl_fec_clk_init(void) { struct regmap *gpr; @@ -31,6 +31,12 @@ } } +static inline void imx6sl_fec_init(void) +{ + imx6sl_fec_clk_init(); + imx6_enet_mac_init("fsl,imx6sl-fec", "fsl,imx6sl-ocotp"); +} + static void __init imx6sl_init_late(void) { /* imx6sl reuses imx6q cpufreq driver */ @@ -40,7 +46,7 @@ if (IS_ENABLED(CONFIG_SOC_IMX6SL) && cpu_is_imx6sl()) imx6sl_cpuidle_init(); else if (IS_ENABLED(CONFIG_SOC_IMX6SLL)) - imx6sx_cpuidle_init(); + imx6sll_cpuidle_init(); } static void __init imx6sl_init_machine(void) @@ -66,6 +72,14 @@ imx6_pm_ccm_init("fsl,imx6sll-ccm"); } +static void __init imx6sl_map_io(void) +{ + imx6_pm_map_io(); +#ifdef CONFIG_CPU_FREQ + imx_busfreq_map_io(); +#endif +} + static const char * const imx6sl_dt_compat[] __initconst = { "fsl,imx6sl", "fsl,imx6sll", @@ -75,6 +89,7 @@ DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") .l2c_aux_val = 0, .l2c_aux_mask = ~0, + .map_io = imx6sl_map_io, .init_irq = imx6sl_init_irq, .init_machine = imx6sl_init_machine, .init_late = imx6sl_init_late, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mach-imx6sx.c linux-imx-phytec/arch/arm/mach-imx/mach-imx6sx.c --- linux-6.1.55/arch/arm/mach-imx/mach-imx6sx.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/mach-imx6sx.c 2024-06-19 12:33:58.132189693 +0200 @@ -32,6 +32,7 @@ static inline void imx6sx_enet_init(void) { + imx6_enet_mac_init("fsl,imx6sx-fec", "fsl,imx6sx-ocotp"); imx6sx_enet_clk_sel(); } @@ -54,6 +55,13 @@ imx6_pm_ccm_init("fsl,imx6sx-ccm"); } +static void __init imx6sx_map_io(void) +{ + debug_ll_io_init(); + imx6_pm_map_io(); + imx_busfreq_map_io(); +} + static void __init imx6sx_init_late(void) { imx6sx_cpuidle_init(); @@ -70,6 +78,7 @@ DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)") .l2c_aux_val = 0, .l2c_aux_mask = ~0, + .map_io = imx6sx_map_io, .init_irq = imx6sx_init_irq, .init_machine = imx6sx_init_machine, .dt_compat = imx6sx_dt_compat, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mach-imx6ul.c linux-imx-phytec/arch/arm/mach-imx/mach-imx6ul.c --- linux-6.1.55/arch/arm/mach-imx/mach-imx6ul.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/mach-imx6ul.c 2024-06-19 12:33:58.132189693 +0200 @@ -31,6 +31,7 @@ static inline void imx6ul_enet_init(void) { imx6ul_enet_clk_init(); + imx6_enet_mac_init("fsl,imx6ul-fec", "fsl,imx6ul-ocotp"); } static void __init imx6ul_init_machine(void) @@ -54,12 +55,18 @@ static void __init imx6ul_init_late(void) { - imx6sx_cpuidle_init(); + imx6ul_cpuidle_init(); if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); } +static void __init imx6ul_map_io(void) +{ + imx6_pm_map_io(); + imx_busfreq_map_io(); +} + static const char * const imx6ul_dt_compat[] __initconst = { "fsl,imx6ul", "fsl,imx6ull", @@ -67,6 +74,7 @@ }; DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)") + .map_io = imx6ul_map_io, .init_irq = imx6ul_init_irq, .init_machine = imx6ul_init_machine, .init_late = imx6ul_init_late, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mach-imx7d.c linux-imx-phytec/arch/arm/mach-imx/mach-imx7d.c --- linux-6.1.55/arch/arm/mach-imx/mach-imx7d.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/mach-imx7d.c 2024-06-19 12:33:58.132189693 +0200 @@ -13,6 +13,13 @@ #include #include "common.h" +#include "cpuidle.h" + +static struct property device_disabled = { + .name = "status", + .length = sizeof("disabled"), + .value = "disabled", +}; static int bcm54220_phy_fixup(struct phy_device *dev) { @@ -35,6 +42,23 @@ } } +static void __init imx7d_enet_mdio_fixup(void) +{ + struct regmap *gpr; + + /* The management data input/output (MDIO) bus where often high-speed, + * open-drain operation is required. i.MX7D TO1.0 ENET MDIO pin has no + * open drain as IC ticket number: TKT252980, i.MX7D TO1.1 fix the issue. + * GPR1[8:7] are reserved bits at TO1.0, there no need to add version check. + */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR0, IMX7D_GPR0_ENET_MDIO_OPEN_DRAIN_MASK, + IMX7D_GPR0_ENET_MDIO_OPEN_DRAIN_MASK); + else + pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); +} + static void __init imx7d_enet_clk_sel(void) { struct regmap *gpr; @@ -50,27 +74,54 @@ static inline void imx7d_enet_init(void) { + imx6_enet_mac_init("fsl,imx7d-fec", "fsl,imx7d-ocotp"); + imx7d_enet_mdio_fixup(); imx7d_enet_phy_init(); imx7d_enet_clk_sel(); } +static inline void imx7d_disable_arm_arch_timer(void) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "arm,armv7-timer"); + if (node) { + pr_info("disable arm arch timer for nosmp!\n"); + of_add_property(node, &device_disabled); + } +} + static void __init imx7d_init_machine(void) { imx_anatop_init(); + of_platform_default_populate(NULL, NULL, NULL); + imx7d_pm_init(); imx7d_enet_init(); } static void __init imx7d_init_late(void) { + imx7d_cpuidle_init(); if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); } static void __init imx7d_init_irq(void) { + imx_gpcv2_check_dt(); imx_init_revision_from_anatop(); - imx7_src_init(); + imx_src_init(); irqchip_init(); +#ifndef CONFIG_SMP + imx7d_disable_arm_arch_timer(); +#endif +} + +static void __init imx7d_map_io(void) +{ + debug_ll_io_init(); + imx7_pm_map_io(); + imx_busfreq_map_io(); } static const char *const imx7d_dt_compat[] __initconst = { @@ -80,7 +131,8 @@ }; DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)") - .smp = smp_ops(imx7_smp_ops), + .map_io = imx7d_map_io, + .smp = smp_ops(imx_smp_ops), .init_irq = imx7d_init_irq, .init_machine = imx7d_init_machine, .init_late = imx7d_init_late, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mach-imx7ulp.c linux-imx-phytec/arch/arm/mach-imx/mach-imx7ulp.c --- linux-6.1.55/arch/arm/mach-imx/mach-imx7ulp.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/mach-imx7ulp.c 2024-06-19 12:33:58.132189693 +0200 @@ -10,6 +10,7 @@ #include #include #include +#include #include "common.h" #include "cpuidle.h" @@ -17,6 +18,15 @@ #define SIM_JTAG_ID_REG 0x8c +/* static IO mapping, and ioremap() could always share the same mapping. */ +static struct map_desc mx7ulp_io_desc[] __initdata = { + mx7ulp_aips_map_entry(1, MT_DEVICE), + mx7ulp_aips_map_entry(2, MT_DEVICE), + mx7ulp_aips_map_entry(3, MT_DEVICE), + mx7ulp_aips_map_entry(4, MT_DEVICE), + mx7ulp_aips_map_entry(5, MT_DEVICE), +}; + static void __init imx7ulp_set_revision(void) { struct regmap *sim; @@ -69,15 +79,23 @@ NULL, }; +static void __init imx7ulp_map_io(void) +{ + iotable_init(mx7ulp_io_desc, ARRAY_SIZE(mx7ulp_io_desc)); + imx7ulp_pm_map_io(); +} + static void __init imx7ulp_init_late(void) { if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); imx7ulp_cpuidle_init(); + imx7ulp_enable_nmi(); } DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)") + .map_io = imx7ulp_map_io, .init_machine = imx7ulp_init_machine, .dt_compat = imx7ulp_dt_compat, .init_late = imx7ulp_init_late, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/Makefile linux-imx-phytec/arch/arm/mach-imx/Makefile --- linux-6.1.55/arch/arm/mach-imx/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/Makefile 2024-06-19 12:33:58.124189556 +0200 @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-y := cpu.o system.o irq-common.o +obj-y := cpu.o system.o irq-common.o common.o obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o @@ -17,11 +17,18 @@ ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o -obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o -obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sx.o -obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o -obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o -obj-$(CONFIG_SOC_IMX7ULP) += cpuidle-imx7ulp.o +AFLAGS_imx6sl_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o imx6sl_low_power_idle.o +AFLAGS_imx6sll_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sll.o imx6sll_low_power_idle.o +obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o imx6sx_low_power_idle.o +AFLAGS_imx6sx_low_power_idle.o :=-Wa,-march=armv7-a +AFLAGS_imx6ul_low_power_idle.o :=-Wa,-march=armv7-a +AFLAGS_imx6ull_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6ul.o imx6ul_low_power_idle.o imx6ull_low_power_idle.o +obj-$(CONFIG_SOC_IMX7ULP) += cpuidle-imx7ulp.o pm-rpmsg.o +AFLAGS_imx7d_low_power_idle.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX7D_CA7) += cpuidle-imx7d.o imx7d_low_power_idle.o endif ifdef CONFIG_SND_SOC_IMX_PCM_FIQ @@ -31,26 +38,46 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o +obj-$(CONFIG_HAVE_IMX_GPCV2) += gpcv2.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o -ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7D_CA7)$(CONFIG_SOC_LS1021A),) +obj-$(CONFIG_HAVE_IMX_DDRC) += ddrc.o +obj-$(CONFIG_HAVE_IMX_MU) += mu.o +ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),) AFLAGS_headsmp.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o endif -obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o -obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o -obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o -obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o +obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o ddr3_freq_imx6.o smp_wfe_imx6.o \ + lpddr2_freq_imx6q.o +obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o lpddr2_freq_imx6.o +obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o lpddr2_freq_imx6sll.o +obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o ddr3_freq_imx6sx.o smp_wfe_imx6.o lpddr2_freq_imx6sx.o obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o -obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o +obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o pm-imx7.o ddr3_freq_imx7d.o smp_wfe.o \ + lpddr3_freq_imx.o suspend-imx7.o obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o +obj-y += busfreq-imx.o busfreq_ddr3.o busfreq_lpddr2.o +AFLAGS_smp_wfe.o :=-Wa,-march=armv7-a +AFLAGS_smp_wfe_imx6.o :=-Wa,-march=armv7-a +AFLAGS_ddr3_freq_imx7d.o :=-Wa,-march=armv7-a +AFLAGS_lpddr3_freq_imx.o :=-Wa,-march=armv7-a +AFLAGS_ddr3_freq_imx6.o :=-Wa,-march=armv7-a +AFLAGS_lpddr2_freq_imx6.o :=-Wa,-march=armv7-a +AFLAGS_lpddr2_freq_imx6q.o :=-Wa,-march=armv7-a +AFLAGS_lpddr2_freq_imx6sx.o :=-Wa,-march=armv7-a +AFLAGS_lpddr2_freq_imx6sll.o :=-Wa,-march=armv7-a +AFLAGS_ddr3_freq_imx6sx.o :=-Wa,-march=armv7-a + ifeq ($(CONFIG_SUSPEND),y) AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a +AFLAGS_suspend-imx7.o :=-Wa,-march=armv7-a +AFLAGS_suspend-imx7ulp.o :=-Wa,-march=armv7-a obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o +obj-$(CONFIG_SOC_IMX7ULP) += suspend-imx7ulp.o endif ifeq ($(CONFIG_ARM_CPU_SUSPEND),y) AFLAGS_resume-imx6.o :=-Wa,-march=armv7-a @@ -68,3 +95,8 @@ obj-$(CONFIG_SOC_VF610) += mach-vf610.o obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o + +ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7),) +# Bus frequency by OPTEE OS +obj-$(CONFIG_OPTEE) += busfreq_optee.o +endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mmdc.c linux-imx-phytec/arch/arm/mach-imx/mmdc.c --- linux-6.1.55/arch/arm/mach-imx/mmdc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/mmdc.c 2024-06-19 12:33:58.132189693 +0200 @@ -59,6 +59,7 @@ #define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu) static int ddr_type; +static int lpddr2_2ch_mode; struct fsl_mmdc_devtype_data { unsigned int flags; @@ -103,7 +104,7 @@ struct device *dev; struct perf_event *mmdc_events[MMDC_NUM_COUNTERS]; struct hlist_node node; - struct fsl_mmdc_devtype_data *devtype_data; + const struct fsl_mmdc_devtype_data *devtype_data; struct clk *mmdc_ipg_clk; }; @@ -504,7 +505,9 @@ GFP_KERNEL, "mmdc%d", ret); pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk; - pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data; + pmu_mmdc->devtype_data = &imx6q_data; + if (of_id) + pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data; hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); @@ -586,6 +589,11 @@ return ddr_type; } +int imx_mmdc_get_lpddr2_2ch_mode(void) +{ + return lpddr2_2ch_mode; +} + static struct platform_driver imx_mmdc_driver = { .driver = { .name = "imx-mmdc", diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mu.c linux-imx-phytec/arch/arm/mach-imx/mu.c --- linux-6.1.55/arch/arm/mach-imx/mu.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/mu.c 2024-06-19 12:33:58.132189693 +0200 @@ -0,0 +1,434 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "hardware.h" + +#define MU_ATR0_OFFSET 0x0 +#define MU_ARR0_OFFSET 0x10 +#define MU_ARR1_OFFSET 0x14 +#define MU_ASR 0x20 +#define MU_ACR 0x24 +#define MX7ULP_MU_TR0 0x20 +#define MX7ULP_MU_RR0 0x40 +#define MX7ULP_MU_RR1 0x44 +#define MX7ULP_MU_SR 0x60 +#define MX7ULP_MU_CR 0x64 + +#define MU_LPM_HANDSHAKE_INDEX 0 +#define MU_RPMSG_HANDSHAKE_INDEX 1 +#define MU_LPM_BUS_HIGH_READY_FOR_M4 0xFFFF6666 +#define MU_LPM_M4_FREQ_CHANGE_READY 0xFFFF7777 +#define MU_LPM_M4_REQUEST_HIGH_BUS 0x2222CCCC +#define MU_LPM_M4_RELEASE_HIGH_BUS 0x2222BBBB +#define MU_LPM_M4_WAKEUP_SRC_VAL 0x55555000 +#define MU_LPM_M4_WAKEUP_SRC_MASK 0xFFFFF000 +#define MU_LPM_M4_WAKEUP_IRQ_MASK 0xFF0 +#define MU_LPM_M4_WAKEUP_IRQ_SHIFT 0x4 +#define MU_LPM_M4_WAKEUP_ENABLE_MASK 0xF +#define MU_LPM_M4_WAKEUP_ENABLE_SHIFT 0x0 + +#define MU_LPM_M4_RUN_MODE 0x5A5A0001 +#define MU_LPM_M4_WAIT_MODE 0x5A5A0002 +#define MU_LPM_M4_STOP_MODE 0x5A5A0003 + +#define MAX_NUM 10 /* enlarge it if overflow happen */ + +static void __iomem *mu_base; +static u32 m4_message[MAX_NUM]; +static u32 in_idx, out_idx; +static struct delayed_work mu_work; +static u32 m4_wake_irqs[4]; +static bool m4_freq_low; +struct irq_domain *domain; +static bool m4_in_stop; +static struct clk *clk; +static DEFINE_SPINLOCK(mu_lock); + +void imx_mu_set_m4_run_mode(void) +{ + m4_in_stop = false; +} + +bool imx_mu_is_m4_in_stop(void) +{ + return m4_in_stop; +} + +bool imx_mu_is_m4_in_low_freq(void) +{ + return m4_freq_low; +} + +void imx_mu_enable_m4_irqs_in_gic(bool enable) +{ + int i, j; + + for (i = 0; i < 4; i++) { + if (m4_wake_irqs[i] == 0) + continue; + for (j = 0; j < 32; j++) { + if (m4_wake_irqs[i] & (1 << j)) { + if (enable) + enable_irq(irq_find_mapping( + domain, i * 32 + j)); + else + disable_irq(irq_find_mapping( + domain, i * 32 + j)); + } + } + } +} + +static irqreturn_t mcc_m4_dummy_isr(int irq, void *param) +{ + return IRQ_HANDLED; +} + +static int imx_mu_send_message(unsigned int index, unsigned int data) +{ + u32 val, ep; + int i, te_flag = 0; + unsigned long timeout = jiffies + msecs_to_jiffies(500); + + /* wait for transfer buffer empty, and no event pending */ + do { + if (cpu_is_imx7ulp()) + val = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + val = readl_relaxed(mu_base + MU_ASR); + ep = val & BIT(4); + if (time_after(jiffies, timeout)) { + pr_err("Waiting MU transmit buffer empty timeout!\n"); + return -EIO; + } + } while (((val & (1 << (20 + 3 - index))) == 0) || (ep == BIT(4))); + + if (cpu_is_imx7ulp()) + writel_relaxed(data, mu_base + index * 0x4 + MX7ULP_MU_TR0); + else + writel_relaxed(data, mu_base + index * 0x4 + MU_ATR0_OFFSET); + + /* + * make a double check that TEn is not empty after write + */ + if (cpu_is_imx7ulp()) + val = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + val = readl_relaxed(mu_base + MU_ASR); + ep = val & BIT(4); + if (((val & (1 << (20 + (3 - index)))) == 0) || (ep == BIT(4))) + return 0; + else + te_flag = 1; + + /* + * Make sure that TEn flag is changed, after the ATRn is filled up. + */ + for (i = 0; i < 100; i++) { + if (cpu_is_imx7ulp()) + val = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + val = readl_relaxed(mu_base + MU_ASR); + ep = val & BIT(4); + if (((val & (1 << (20 + 3 - index))) == 0) || (ep == BIT(4))) { + /* + * BUG here. TEn flag is changes, after the + * ATRn is filled with MSG for a while. + */ + te_flag = 0; + break; + } else if (time_after(jiffies, timeout)) { + /* Can't see TEn 1->0, maybe already handled! */ + te_flag = 1; + break; + } + } + if (te_flag == 0) + pr_info("BUG: TEn is not changed immediately" + "when ATRn is filled up.\n"); + + return 0; +} + +static void mu_work_handler(struct work_struct *work) +{ + int ret; + u32 irq, enable, idx, mask, virq; + struct of_phandle_args args; + u32 message; + unsigned long flags; + + spin_lock_irqsave(&mu_lock, flags); + message = m4_message[out_idx % MAX_NUM]; + spin_unlock_irqrestore(&mu_lock, flags); + + pr_debug("receive M4 message 0x%x\n", message); + + switch (message) { + case MU_LPM_M4_RUN_MODE: + case MU_LPM_M4_WAIT_MODE: + m4_in_stop = false; + break; + case MU_LPM_M4_STOP_MODE: + m4_in_stop = true; + break; + case MU_LPM_M4_REQUEST_HIGH_BUS: + request_bus_freq(BUS_FREQ_HIGH); +#ifdef CONFIG_SOC_IMX6SX + if (cpu_is_imx6sx()) + imx6sx_set_m4_highfreq(true); +#endif + imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX, + MU_LPM_BUS_HIGH_READY_FOR_M4); + m4_freq_low = false; + break; + case MU_LPM_M4_RELEASE_HIGH_BUS: + release_bus_freq(BUS_FREQ_HIGH); +#ifdef CONFIG_SOC_IMX6SX + if (cpu_is_imx6sx()) { + imx6sx_set_m4_highfreq(false); + imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX, + MU_LPM_M4_FREQ_CHANGE_READY); + } +#endif + m4_freq_low = true; + break; + default: + if ((message & MU_LPM_M4_WAKEUP_SRC_MASK) == + MU_LPM_M4_WAKEUP_SRC_VAL) { + irq = (message & MU_LPM_M4_WAKEUP_IRQ_MASK) >> + MU_LPM_M4_WAKEUP_IRQ_SHIFT; + + enable = (message & MU_LPM_M4_WAKEUP_ENABLE_MASK) >> + MU_LPM_M4_WAKEUP_ENABLE_SHIFT; + + /* to hwirq start from 0 */ + irq -= 32; + + idx = irq / 32; + mask = 1 << irq % 32; + + args.np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpc"); + args.args_count = 3; + args.args[0] = 0; + args.args[1] = irq; + args.args[2] = IRQ_TYPE_LEVEL_HIGH; + + virq = irq_create_of_mapping(&args); + + if (enable && can_request_irq(virq, 0)) { + ret = request_irq(virq, mcc_m4_dummy_isr, + IRQF_NO_SUSPEND, "imx-m4-dummy", NULL); + if (ret) { + pr_err("%s: register interrupt %d failed, rc %d\n", + __func__, virq, ret); + break; + } + disable_irq(virq); + m4_wake_irqs[idx] = m4_wake_irqs[idx] | mask; + } + imx_gpc_add_m4_wake_up_irq(irq, enable); + } + break; + } + + spin_lock_irqsave(&mu_lock, flags); + m4_message[out_idx % MAX_NUM] = 0; + out_idx++; + spin_unlock_irqrestore(&mu_lock, flags); + + /* enable RIE3 interrupt */ + if (cpu_is_imx7ulp()) + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) | BIT(27), + mu_base + MX7ULP_MU_CR); + else + writel_relaxed(readl_relaxed(mu_base + MU_ACR) | BIT(27), + mu_base + MU_ACR); +} + +int imx_mu_lpm_ready(bool ready) +{ + u32 val; + + if (cpu_is_imx7ulp()) { + val = readl_relaxed(mu_base + MX7ULP_MU_CR); + if (ready) + writel_relaxed(val | BIT(0), mu_base + MX7ULP_MU_CR); + else + writel_relaxed(val & ~BIT(0), mu_base + MX7ULP_MU_CR); + } else { + val = readl_relaxed(mu_base + MU_ACR); + if (ready) + writel_relaxed(val | BIT(0), mu_base + MU_ACR); + else + writel_relaxed(val & ~BIT(0), mu_base + MU_ACR); + } + return 0; +} + +static irqreturn_t imx_mu_isr(int irq, void *param) +{ + u32 irqs; + unsigned long flags; + + if (cpu_is_imx7ulp()) + irqs = readl_relaxed(mu_base + MX7ULP_MU_SR); + else + irqs = readl_relaxed(mu_base + MU_ASR); + + if (irqs & (1 << 27)) { + spin_lock_irqsave(&mu_lock, flags); + /* get message from receive buffer */ + if (cpu_is_imx7ulp()) + m4_message[in_idx % MAX_NUM] = readl_relaxed(mu_base + + MX7ULP_MU_RR0); + else + m4_message[in_idx % MAX_NUM] = readl_relaxed(mu_base + + MU_ARR0_OFFSET); + /* disable RIE3 interrupt */ + if (cpu_is_imx7ulp()) + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) + & (~BIT(27)), mu_base + MX7ULP_MU_CR); + else + writel_relaxed(readl_relaxed(mu_base + MU_ACR) + & (~BIT(27)), mu_base + MU_ACR); + in_idx++; + if (in_idx == out_idx) { + spin_unlock_irqrestore(&mu_lock, flags); + pr_err("MU overflow!\n"); + return IRQ_HANDLED; + } + spin_unlock_irqrestore(&mu_lock, flags); + + schedule_delayed_work(&mu_work, 0); + } + + return IRQ_HANDLED; +} + +static int imx_mu_probe(struct platform_device *pdev) +{ + int ret; + u32 irq; + struct device_node *np; + struct device *dev = &pdev->dev; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-mu-lp"); + mu_base = of_iomap(np, 0); + WARN_ON(!mu_base); + + ret = of_device_is_compatible(np, "fsl,imx7ulp-mu-lp"); + if (ret) + irq = platform_get_irq(pdev, 1); + else + irq = platform_get_irq(pdev, 0); + ret = request_irq(irq, imx_mu_isr, + IRQF_NO_SUSPEND | IRQF_SHARED, "imx-mu-lp", dev); + if (ret) { + pr_err("%s: register interrupt %d failed, rc %d\n", + __func__, irq, ret); + return ret; + } + + ret = of_device_is_compatible(np, "fsl,imx7d-mu-lp"); + if (ret) { + clk = devm_clk_get(&pdev->dev, "mu"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, + "mu clock source missing or invalid\n"); + return PTR_ERR(clk); + } else { + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(&pdev->dev, + "unable to enable mu clock\n"); + return ret; + } + } + + /* MU always as a wakeup source for low power mode */ + imx_gpcv2_add_m4_wake_up_irq(irq_to_desc(irq)->irq_data.hwirq, + true); + } else { + /* MU always as a wakeup source for low power mode */ + imx_gpc_add_m4_wake_up_irq(irq_to_desc(irq)->irq_data.hwirq, true); + } + + INIT_DELAYED_WORK(&mu_work, mu_work_handler); + /* bit0 of MX7ULP_MU_CR used to let m4 to know MU is ready now */ + if (cpu_is_imx7ulp()) + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) | + BIT(0) | BIT(26) | BIT(27), mu_base + MX7ULP_MU_CR); + else + writel_relaxed(readl_relaxed(mu_base + MU_ACR) | + BIT(26) | BIT(27), mu_base + MU_ACR); + + pr_info("MU is ready for cross core communication!\n"); + + return 0; +} + +static const struct of_device_id imx_mu_ids[] = { + { .compatible = "fsl,imx6sx-mu-lp" }, + { .compatible = "fsl,imx7d-mu-lp" }, + { .compatible = "fsl,imx7ulp-mu-lp" }, + { } +}; + +#ifdef CONFIG_PM_SLEEP +static int mu_suspend(struct device *dev) +{ + return 0; +} + +static int mu_resume(struct device *dev) +{ + if (!cpu_is_imx7ulp()) + return 0; + + writel_relaxed(readl_relaxed(mu_base + MX7ULP_MU_CR) | + BIT(0) | BIT(26) | BIT(27), mu_base + MX7ULP_MU_CR); + + return 0; +} +#endif +static const struct dev_pm_ops mu_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(mu_suspend, mu_resume) +}; + +static struct platform_driver imx_mu_driver = { + .driver = { + .name = "imx-mu-lp", + .owner = THIS_MODULE, + .pm = &mu_pm_ops, + .of_match_table = imx_mu_ids, + }, + .probe = imx_mu_probe, +}; + +static int __init imx_mu_init(void) +{ + return platform_driver_register(&imx_mu_driver); +} +subsys_initcall(imx_mu_init); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mx6.h linux-imx-phytec/arch/arm/mach-imx/mx6.h --- linux-6.1.55/arch/arm/mach-imx/mx6.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/mx6.h 2024-06-19 12:33:58.132189693 +0200 @@ -0,0 +1,51 @@ +/* + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * * This program is free software; you can redistribute it and/or modify + * * it under the terms of the GNU General Public License version 2 as + * * published by the Free Software Foundation. + * */ + +#ifndef __ASM_ARCH_MXC_IOMAP_H__ +#define __ASM_ARCH_MXC_IOMAP_H__ + +#define MX6Q_IO_P2V(x) IMX_IO_P2V(x) +#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x)) + +#define MX6Q_L2_BASE_ADDR 0x00a02000 +#define MX6Q_L2_SIZE 0x1000 +#define MX6Q_IOMUXC_BASE_ADDR 0x020e0000 +#define MX6Q_IOMUXC_SIZE 0x4000 +#define MX6Q_SRC_BASE_ADDR 0x020d8000 +#define MX6Q_SRC_SIZE 0x4000 +#define MX6Q_CCM_BASE_ADDR 0x020c4000 +#define MX6Q_CCM_SIZE 0x4000 +#define MX6Q_ANATOP_BASE_ADDR 0x020c8000 +#define MX6Q_ANATOP_SIZE 0x1000 +#define MX6Q_GPC_BASE_ADDR 0x020dc000 +#define MX6Q_GPC_SIZE 0x4000 +#define MX6Q_SEMA4_BASE_ADDR 0x02290000 +#define MX6Q_SEMA4_SIZE 0x4000 +#define MX6Q_MMDC_P0_BASE_ADDR 0x021b0000 +#define MX6Q_MMDC_P0_SIZE 0x4000 +#define MX6Q_MMDC_P1_BASE_ADDR 0x021b4000 +#define MX6Q_MMDC_P1_SIZE 0x4000 +#define MX6Q_AIPS1_BASE_ADDR 0x02000000 +#define MX6Q_AIPS1_SIZE 0x100000 +#define MX6Q_AIPS2_BASE_ADDR 0x02100000 +#define MX6Q_AIPS2_SIZE 0x100000 +#define MX6Q_AIPS3_BASE_ADDR 0x02200000 +#define MX6Q_AIPS3_SIZE 0x100000 + +#define MX6SX_IRAM_TLB_BASE_ADDR 0x008f8000 +#define MX6Q_IRAM_TLB_BASE_ADDR 0x00900000 +#define MX6Q_IRAM_TLB_SIZE 0x4000 +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX6_SUSPEND_IRAM_DATA_SIZE 256 +#define MX6SL_WFI_IRAM_DATA_SIZE 100 + +#define MX6_SUSPEND_IRAM_ADDR_OFFSET 0 +#define MX6_CPUIDLE_IRAM_ADDR_OFFSET 0x1000 +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mx7.h linux-imx-phytec/arch/arm/mach-imx/mx7.h --- linux-6.1.55/arch/arm/mach-imx/mx7.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/mx7.h 2024-06-19 12:33:58.132189693 +0200 @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * * This program is free software; you can redistribute it and/or modify + * * it under the terms of the GNU General Public License version 2 as + * * published by the Free Software Foundation. + * */ + +#ifndef __ASM_ARCH_MX7_IOMAP_H__ +#define __ASM_ARCH_MX7_IOMAP_H__ + +#define MX7D_IO_P2V(x) IMX_IO_P2V(x) +#define MX7D_IO_ADDRESS(x) IOMEM(MX7D_IO_P2V(x)) + +#define MX7D_LPSR_BASE_ADDR 0x30270000 +#define MX7D_LPSR_SIZE 0x10000 +#define MX7D_CCM_BASE_ADDR 0x30380000 +#define MX7D_CCM_SIZE 0x10000 +#define MX7D_IOMUXC_BASE_ADDR 0x30330000 +#define MX7D_IOMUXC_SIZE 0x10000 +#define MX7D_IOMUXC_GPR_BASE_ADDR 0x30340000 +#define MX7D_IOMUXC_GPR_SIZE 0x10000 +#define MX7D_ANATOP_BASE_ADDR 0x30360000 +#define MX7D_ANATOP_SIZE 0x10000 +#define MX7D_SNVS_BASE_ADDR 0x30370000 +#define MX7D_SNVS_SIZE 0x10000 +#define MX7D_GPC_BASE_ADDR 0x303a0000 +#define MX7D_GPC_SIZE 0x10000 +#define MX7D_SRC_BASE_ADDR 0x30390000 +#define MX7D_SRC_SIZE 0x10000 +#define MX7D_DDRC_BASE_ADDR 0x307a0000 +#define MX7D_DDRC_SIZE 0x10000 +#define MX7D_DDRC_PHY_BASE_ADDR 0x30790000 +#define MX7D_DDRC_PHY_SIZE 0x10000 +#define MX7D_AIPS1_BASE_ADDR 0x30000000 +#define MX7D_AIPS1_SIZE 0x400000 +#define MX7D_AIPS2_BASE_ADDR 0x30400000 +#define MX7D_AIPS2_SIZE 0x400000 +#define MX7D_AIPS3_BASE_ADDR 0x30900000 +#define MX7D_AIPS3_SIZE 0x300000 +#define MX7D_GIC_BASE_ADDR 0x31000000 +#define MX7D_GIC_SIZE 0x100000 + +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX7_IRAM_TLB_SIZE 0x4000 +#define MX7_SUSPEND_OCRAM_SIZE 0x1000 +#define MX7_CPUIDLE_OCRAM_ADDR_OFFSET 0x1000 +#define MX7_CPUIDLE_OCRAM_SIZE 0x1000 +#define MX7_BUSFREQ_OCRAM_ADDR_OFFSET 0x2000 +#define MX7_BUSFREQ_OCRAM_SIZE 0x1000 + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mx7ulp.h linux-imx-phytec/arch/arm/mach-imx/mx7ulp.h --- linux-6.1.55/arch/arm/mach-imx/mx7ulp.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/mx7ulp.h 2024-06-19 12:33:58.132189693 +0200 @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright NXP 2017. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MX7ULP_IOMAP_H__ +#define __ASM_ARCH_MX7ULP_IOMAP_H__ + +#define MX7ULP_IO_P2V(x) IMX_IO_P2V(x) +#define MX7ULP_IO_ADDRESS(x) IOMEM(MX7ULP_IO_P2V(x)) + +#define MX7ULP_AIPS1_BASE_ADDR 0x40000000 +#define MX7ULP_AIPS1_SIZE 0x100000 +#define MX7ULP_AIPS2_BASE_ADDR 0x40300000 +#define MX7ULP_AIPS2_SIZE 0x100000 +#define MX7ULP_AIPS3_BASE_ADDR 0x40400000 +#define MX7ULP_AIPS3_SIZE 0x100000 +#define MX7ULP_AIPS4_BASE_ADDR 0x40a00000 +#define MX7ULP_AIPS4_SIZE 0x100000 +#define MX7ULP_AIPS5_BASE_ADDR 0x41000000 +#define MX7ULP_AIPS5_SIZE 0x100000 +#define MX7ULP_GPIOC_BASE_ADDR 0x400f0000 +#define MX7ULP_GPIOC_SIZE 0x1000 +#define MX7ULP_PCC3_BASE_ADDR 0x40b30000 +#define MX7ULP_PCC3_SIZE 0x1000 +#define MX7ULP_SCG1_BASE_ADDR 0x403e0000 +#define MX7ULP_SCG1_SIZE 0x1000 +#define MX7ULP_PCC2_BASE_ADDR 0x403f0000 +#define MX7ULP_PCC2_SIZE 0x1000 +#define MX7ULP_SIM_BASE_ADDR 0x410a3000 +#define MX7ULP_SIM_SIZE 0x1000 +#define MX7ULP_PMC1_BASE_ADDR 0x40400000 +#define MX7ULP_PMC1_SIZE 0x1000 +#define MX7ULP_SMC1_BASE_ADDR 0x40410000 +#define MX7ULP_SMC1_SIZE 0x1000 +#define MX7ULP_MMDC_BASE_ADDR 0x40ab0000 +#define MX7ULP_MMDC_SIZE 0x1000 +#define MX7ULP_IOMUXC1_BASE_ADDR 0x40ac0000 +#define MX7ULP_IOMUXC1_BASE__SIZE 0x1000 +#define MX7ULP_MMDC_IO_BASE_ADDR 0x40ad0000 +#define MX7ULP_MMDC_IO_SIZE 0x1000 + +/* below is just used for static mapping of the AIPSx's memory region */ +#define MX7ULP_AIPS_VIRT_BASE(x) (0xf4000000 + ((x) * SZ_1M)) + +#define mx7ulp_aips_map_entry(index, _type) { \ + .virtual = MX7ULP_AIPS_VIRT_BASE(index), \ + .pfn = __phys_to_pfn(MX7ULP_AIPS ## index ## _BASE_ADDR), \ + .length = SZ_1M, \ + .type = _type, \ +} + +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX7ULP_IRAM_TLB_SIZE 0x4000 +#define MX7ULP_SUSPEND_OCRAM_SIZE 0x1000 + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/mxc.h linux-imx-phytec/arch/arm/mach-imx/mxc.h --- linux-6.1.55/arch/arm/mach-imx/mxc.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/mxc.h 2024-06-19 12:33:58.132189693 +0200 @@ -14,7 +14,13 @@ #error "Do not include directly." #endif +#define IMX_DDR_TYPE_DDR3 0 #define IMX_DDR_TYPE_LPDDR2 1 +#define IMX_DDR_TYPE_LPDDR3 2 +#define IMX_MMDC_DDR_TYPE_LPDDR3 3 + +#define IMX_LPDDR2_1CH_MODE 0 +#define IMX_LPDDR2_2CH_MODE 1 #ifndef __ASSEMBLY__ @@ -65,11 +71,28 @@ return __mxc_cpu_type == MXC_CPU_IMX6Q; } +static inline bool cpu_is_imx6(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6Q || + __mxc_cpu_type == MXC_CPU_IMX6DL || + __mxc_cpu_type == MXC_CPU_IMX6SL || + __mxc_cpu_type == MXC_CPU_IMX6SX || + __mxc_cpu_type == MXC_CPU_IMX6UL || + __mxc_cpu_type == MXC_CPU_IMX6ULL || + __mxc_cpu_type == MXC_CPU_IMX6SLL || + __mxc_cpu_type == MXC_CPU_IMX6ULZ; +} + static inline bool cpu_is_imx7d(void) { return __mxc_cpu_type == MXC_CPU_IMX7D; } +static inline bool cpu_is_imx7ulp(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX7ULP; +} + struct cpu_op { u32 cpu_rate; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/platsmp.c linux-imx-phytec/arch/arm/mach-imx/platsmp.c --- linux-6.1.55/arch/arm/mach-imx/platsmp.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/platsmp.c 2024-06-19 12:33:58.132189693 +0200 @@ -18,7 +18,7 @@ #include "hardware.h" u32 g_diag_reg; -static void __iomem *scu_base; +void __iomem *scu_base; static struct map_desc scu_io_desc __initdata = { /* .virtual and .pfn are run-time assigned */ @@ -47,15 +47,39 @@ return 0; } +#define MXC_ARCH_CA7 0xc07 +static unsigned long __mxc_arch_type; + +static inline bool arm_is_ca7(void) +{ + return __mxc_arch_type == MXC_ARCH_CA7; +} /* * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. */ static void __init imx_smp_init_cpus(void) { + unsigned long arch_type; int i, ncores; - ncores = scu_get_core_count(scu_base); + asm volatile( + ".align 4\n" + "mrc p15, 0, %0, c0, c0, 0\n" + : "=r" (arch_type) + ); + /* MIDR[15:4] defines ARCH type */ + __mxc_arch_type = (arch_type >> 4) & 0xfff; + + if (arm_is_ca7()) { + unsigned long val; + + /* CA7 core number, [25:24] of CP15 L2CTLR */ + asm volatile("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + ncores = ((val >> 24) & 0x3) + 1; + } else { + ncores = scu_get_core_count(scu_base); + } for (i = ncores; i < NR_CPUS; i++) set_cpu_possible(i, false); @@ -63,11 +87,15 @@ void imx_smp_prepare(void) { + if (arm_is_ca7()) + return; scu_enable(scu_base); } static void __init imx_smp_prepare_cpus(unsigned int max_cpus) { + if (arm_is_ca7()) + return; imx_smp_prepare(); /* @@ -88,32 +116,6 @@ .smp_boot_secondary = imx_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = imx_cpu_die, - .cpu_kill = imx_cpu_kill, -#endif -}; - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -static void __init imx7_smp_init_cpus(void) -{ - struct device_node *np; - int i, ncores = 0; - - /* The iMX7D SCU does not report core count, get it from DT */ - for_each_of_cpu_node(np) - ncores++; - - for (i = ncores; i < NR_CPUS; i++) - set_cpu_possible(i, false); -} - -const struct smp_operations imx7_smp_ops __initconst = { - .smp_init_cpus = imx7_smp_init_cpus, - .smp_boot_secondary = imx_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_die = imx_cpu_die, .cpu_kill = imx_cpu_kill, #endif }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/pm-imx6.c linux-imx-phytec/arch/arm/mach-imx/pm-imx6.c --- linux-6.1.55/arch/arm/mach-imx/pm-imx6.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/pm-imx6.c 2024-06-19 12:33:58.132189693 +0200 @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2011-2014 Freescale Semiconductor, Inc. + * Copyright 2011-2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ @@ -15,15 +15,21 @@ #include #include #include +#include #include +#include #include +#include #include #include #include +#include #include #include #include +#include + #include "common.h" #include "hardware.h" @@ -56,13 +62,215 @@ #define CGPR 0x64 #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) +#define CCGR4 0x78 +#define CCGR6 0x80 #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 -#define MX6_MAX_MMDC_IO_NUM 33 +#define MX6_MAX_MMDC_IO_NUM 36 +#define MX6_MAX_MMDC_NUM 36 + +#define ROMC_ROMPATCH0D 0xf0 +#define ROMC_ROMPATCHCNTL 0xf4 +#define ROMC_ROMPATCHENL 0xfc +#define ROMC_ROMPATCH0A 0x100 +#define BM_ROMPATCHCNTL_0D (0x1 << 0) +#define BM_ROMPATCHCNTL_DIS (0x1 << 29) +#define BM_ROMPATCHENL_0D (0x1 << 0) +#define ROM_ADDR_FOR_INTERNAL_RAM_BASE 0x10d7c + +#define UART_UCR1 0x80 +#define UART_UCR2 0x84 +#define UART_UCR3 0x88 +#define UART_UCR4 0x8c +#define UART_UFCR 0x90 +#define UART_UESC 0x9c +#define UART_UTIM 0xa0 +#define UART_UBIR 0xa4 +#define UART_UBMR 0xa8 +#define UART_UBRC 0xac +#define UART_UTS 0xb4 + +#define IOMUXC_GPR5_CLOCK_AFCG_X_BYPASS_MASK 0xf800 + +extern unsigned long iram_tlb_base_addr; +extern unsigned long iram_tlb_phys_addr; + +/* QSPI register layout */ +#define QSPI_MCR 0x00 +#define QSPI_IPCR 0x08 +#define QSPI_BUF0CR 0x10 +#define QSPI_BUF1CR 0x14 +#define QSPI_BUF2CR 0x18 +#define QSPI_BUF3CR 0x1c +#define QSPI_BFGENCR 0x20 +#define QSPI_BUF0IND 0x30 +#define QSPI_BUF1IND 0x34 +#define QSPI_BUF2IND 0x38 +#define QSPI_SFAR 0x100 +#define QSPI_SMPR 0x108 +#define QSPI_RBSR 0x10c +#define QSPI_RBCT 0x110 +#define QSPI_TBSR 0x150 +#define QSPI_TBDR 0x154 +#define QSPI_SFA1AD 0x180 +#define QSPI_SFA2AD 0x184 +#define QSPI_SFB1AD 0x188 +#define QSPI_SFB2AD 0x18c +#define QSPI_RBDR_BASE 0x200 +#define QSPI_LUTKEY 0x300 +#define QSPI_LCKCR 0x304 +#define QSPI_LUT_BASE 0x310 + +#define QSPI_RBDR_(x) (QSPI_RBDR_BASE + (x) * 4) +#define QSPI_LUT(x) (QSPI_LUT_BASE + (x) * 4) + +#define QSPI_LUTKEY_VALUE 0x5AF05AF0 +#define QSPI_LCKER_LOCK 0x1 +#define QSPI_LCKER_UNLOCK 0x2 + +enum qspi_regs_valuetype { + QSPI_PREDEFINED, + QSPI_RETRIEVED, +}; + +struct qspi_regs { + int offset; + unsigned int value; + enum qspi_regs_valuetype valuetype; +}; + +struct qspi_regs qspi_regs_imx6sx[] = { + {QSPI_IPCR, 0, QSPI_RETRIEVED}, + {QSPI_BUF0CR, 0, QSPI_RETRIEVED}, + {QSPI_BUF1CR, 0, QSPI_RETRIEVED}, + {QSPI_BUF2CR, 0, QSPI_RETRIEVED}, + {QSPI_BUF3CR, 0, QSPI_RETRIEVED}, + {QSPI_BFGENCR, 0, QSPI_RETRIEVED}, + {QSPI_BUF0IND, 0, QSPI_RETRIEVED}, + {QSPI_BUF1IND, 0, QSPI_RETRIEVED}, + {QSPI_BUF2IND, 0, QSPI_RETRIEVED}, + {QSPI_SFAR, 0, QSPI_RETRIEVED}, + {QSPI_SMPR, 0, QSPI_RETRIEVED}, + {QSPI_RBSR, 0, QSPI_RETRIEVED}, + {QSPI_RBCT, 0, QSPI_RETRIEVED}, + {QSPI_TBSR, 0, QSPI_RETRIEVED}, + {QSPI_TBDR, 0, QSPI_RETRIEVED}, + {QSPI_SFA1AD, 0, QSPI_RETRIEVED}, + {QSPI_SFA2AD, 0, QSPI_RETRIEVED}, + {QSPI_SFB1AD, 0, QSPI_RETRIEVED}, + {QSPI_SFB2AD, 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(0), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(1), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(2), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(3), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(4), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(5), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(6), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(7), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(8), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(9), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(10), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(11), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(12), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(13), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(14), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(15), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(16), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(17), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(18), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(19), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(20), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(21), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(22), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(23), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(24), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(25), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(26), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(27), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(28), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(29), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(30), 0, QSPI_RETRIEVED}, + {QSPI_RBDR_(31), 0, QSPI_RETRIEVED}, + {QSPI_LUTKEY, QSPI_LUTKEY_VALUE, QSPI_PREDEFINED}, + {QSPI_LCKCR, QSPI_LCKER_UNLOCK, QSPI_PREDEFINED}, + {QSPI_LUT(0), 0, QSPI_RETRIEVED}, + {QSPI_LUT(1), 0, QSPI_RETRIEVED}, + {QSPI_LUT(2), 0, QSPI_RETRIEVED}, + {QSPI_LUT(3), 0, QSPI_RETRIEVED}, + {QSPI_LUT(4), 0, QSPI_RETRIEVED}, + {QSPI_LUT(5), 0, QSPI_RETRIEVED}, + {QSPI_LUT(6), 0, QSPI_RETRIEVED}, + {QSPI_LUT(7), 0, QSPI_RETRIEVED}, + {QSPI_LUT(8), 0, QSPI_RETRIEVED}, + {QSPI_LUT(9), 0, QSPI_RETRIEVED}, + {QSPI_LUT(10), 0, QSPI_RETRIEVED}, + {QSPI_LUT(11), 0, QSPI_RETRIEVED}, + {QSPI_LUT(12), 0, QSPI_RETRIEVED}, + {QSPI_LUT(13), 0, QSPI_RETRIEVED}, + {QSPI_LUT(14), 0, QSPI_RETRIEVED}, + {QSPI_LUT(15), 0, QSPI_RETRIEVED}, + {QSPI_LUT(16), 0, QSPI_RETRIEVED}, + {QSPI_LUT(17), 0, QSPI_RETRIEVED}, + {QSPI_LUT(18), 0, QSPI_RETRIEVED}, + {QSPI_LUT(19), 0, QSPI_RETRIEVED}, + {QSPI_LUT(20), 0, QSPI_RETRIEVED}, + {QSPI_LUT(21), 0, QSPI_RETRIEVED}, + {QSPI_LUT(22), 0, QSPI_RETRIEVED}, + {QSPI_LUT(23), 0, QSPI_RETRIEVED}, + {QSPI_LUT(24), 0, QSPI_RETRIEVED}, + {QSPI_LUT(25), 0, QSPI_RETRIEVED}, + {QSPI_LUT(26), 0, QSPI_RETRIEVED}, + {QSPI_LUT(27), 0, QSPI_RETRIEVED}, + {QSPI_LUT(28), 0, QSPI_RETRIEVED}, + {QSPI_LUT(29), 0, QSPI_RETRIEVED}, + {QSPI_LUT(30), 0, QSPI_RETRIEVED}, + {QSPI_LUT(31), 0, QSPI_RETRIEVED}, + {QSPI_LUT(32), 0, QSPI_RETRIEVED}, + {QSPI_LUT(33), 0, QSPI_RETRIEVED}, + {QSPI_LUT(34), 0, QSPI_RETRIEVED}, + {QSPI_LUT(35), 0, QSPI_RETRIEVED}, + {QSPI_LUT(36), 0, QSPI_RETRIEVED}, + {QSPI_LUT(37), 0, QSPI_RETRIEVED}, + {QSPI_LUT(38), 0, QSPI_RETRIEVED}, + {QSPI_LUT(39), 0, QSPI_RETRIEVED}, + {QSPI_LUT(40), 0, QSPI_RETRIEVED}, + {QSPI_LUT(41), 0, QSPI_RETRIEVED}, + {QSPI_LUT(42), 0, QSPI_RETRIEVED}, + {QSPI_LUT(43), 0, QSPI_RETRIEVED}, + {QSPI_LUT(44), 0, QSPI_RETRIEVED}, + {QSPI_LUT(45), 0, QSPI_RETRIEVED}, + {QSPI_LUT(46), 0, QSPI_RETRIEVED}, + {QSPI_LUT(47), 0, QSPI_RETRIEVED}, + {QSPI_LUT(48), 0, QSPI_RETRIEVED}, + {QSPI_LUT(49), 0, QSPI_RETRIEVED}, + {QSPI_LUT(50), 0, QSPI_RETRIEVED}, + {QSPI_LUT(51), 0, QSPI_RETRIEVED}, + {QSPI_LUT(52), 0, QSPI_RETRIEVED}, + {QSPI_LUT(53), 0, QSPI_RETRIEVED}, + {QSPI_LUT(54), 0, QSPI_RETRIEVED}, + {QSPI_LUT(55), 0, QSPI_RETRIEVED}, + {QSPI_LUT(56), 0, QSPI_RETRIEVED}, + {QSPI_LUT(57), 0, QSPI_RETRIEVED}, + {QSPI_LUT(58), 0, QSPI_RETRIEVED}, + {QSPI_LUT(59), 0, QSPI_RETRIEVED}, + {QSPI_LUT(60), 0, QSPI_RETRIEVED}, + {QSPI_LUT(61), 0, QSPI_RETRIEVED}, + {QSPI_LUT(62), 0, QSPI_RETRIEVED}, + {QSPI_LUT(63), 0, QSPI_RETRIEVED}, + {QSPI_LUTKEY, QSPI_LUTKEY_VALUE, QSPI_PREDEFINED}, + {QSPI_LCKCR, QSPI_LCKER_LOCK, QSPI_PREDEFINED}, + {QSPI_MCR, 0, QSPI_RETRIEVED}, +}; +static unsigned int *ocram_saved_in_ddr; +static void __iomem *ocram_base; +static void __iomem *console_base; +static void __iomem *qspi_base; +static unsigned int ocram_size; static void __iomem *ccm_base; static void __iomem *suspend_ocram_base; static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); +struct regmap *romcp; /* * suspend ocram space layout: @@ -92,6 +300,8 @@ const char *pl310_compat; const u32 mmdc_io_num; const u32 *mmdc_io_offset; + const u32 mmdc_num; + const u32 *mmdc_offset; }; static const u32 imx6q_mmdc_io_offset[] __initconst = { @@ -106,6 +316,18 @@ 0x74c, /* GPR_ADDS */ }; +static const u32 imx6q_mmdc_io_lpddr2_offset[] __initconst = { + 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ + 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ + 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ + 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ + 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ + 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ + 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ + 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x74c, 0x590, 0x598, 0x57c, /* GRP_ADDS, SDCKE0, SDCKE1, RESET */ +}; + static const u32 imx6dl_mmdc_io_offset[] __initconst = { 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ @@ -126,11 +348,25 @@ 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ }; -static const u32 imx6sll_mmdc_io_offset[] __initconst = { - 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */ - 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ - 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */ - 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/ +static const u32 imx6sx_mmdc_io_lpddr2_offset[] __initconst = { + 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ + 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ + 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ + 0x324, 0x328, 0x340, /* DRAM_SDCKE0 ~ 1, DRAM_RESET */ +}; + +static const u32 imx6sx_mmdc_lpddr2_offset[] __initconst = { + 0x01c, 0x85c, 0x800, 0x890, + 0x8b8, 0x81c, 0x820, 0x824, + 0x828, 0x82c, 0x830, 0x834, + 0x838, 0x848, 0x850, 0x8c0, + 0x83c, 0x840, 0x8b8, 0x00c, + 0x004, 0x010, 0x014, 0x018, + 0x02c, 0x030, 0x038, 0x008, + 0x040, 0x000, 0x020, 0x818, + 0x800, 0x004, 0x01c, }; static const u32 imx6sx_mmdc_io_offset[] __initconst = { @@ -141,6 +377,16 @@ 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ }; +static const u32 imx6sx_mmdc_offset[] __initconst = { + 0x800, 0x80c, 0x810, 0x83c, + 0x840, 0x848, 0x850, 0x81c, + 0x820, 0x824, 0x828, 0x8b8, + 0x004, 0x008, 0x00c, 0x010, + 0x014, 0x018, 0x01c, 0x02c, + 0x030, 0x040, 0x000, 0x01c, + 0x020, 0x818, 0x01c, +}; + static const u32 imx6ul_mmdc_io_offset[] __initconst = { 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ @@ -148,6 +394,53 @@ 0x494, 0x4b0, /* MODE_CTL, MODE, */ }; +static const u32 imx6ul_mmdc_offset[] __initconst = { + 0x01c, 0x800, 0x80c, 0x83c, + 0x848, 0x850, 0x81c, 0x820, + 0x82c, 0x830, 0x8c0, 0x8b8, + 0x004, 0x008, 0x00c, 0x010, + 0x014, 0x018, 0x01c, 0x02c, + 0x030, 0x040, 0x000, 0x01c, + 0x020, 0x818, 0x01c, +}; + +static const u32 imx6ul_mmdc_io_lpddr2_offset[] __initconst = { + 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ + 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ + 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */ + 0x494, 0x4b0, 0x274, 0x278, /* MODE_CTL, MODE, SDCKE0, SDCKE1 */ + 0x288, /* DRAM_RESET */ +}; + +static const u32 imx6ul_mmdc_lpddr2_offset[] __initconst = { + 0x01c, 0x85c, 0x800, 0x890, + 0x8b8, 0x81c, 0x820, 0x82c, + 0x830, 0x83c, 0x848, 0x850, + 0x8c0, 0x8b8, 0x004, 0x008, + 0x00c, 0x010, 0x038, 0x014, + 0x018, 0x01c, 0x02c, 0x030, + 0x040, 0x000, 0x020, 0x818, + 0x800, 0x004, 0x01c, +}; + +static const u32 imx6sll_mmdc_io_offset[] __initconst = { + 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */ + 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ + 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */ + 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/ +}; + +static const u32 imx6sll_mmdc_lpddr3_offset[] __initconst = { + 0x01c, 0x85c, 0x800, 0x890, + 0x8b8, 0x81c, 0x820, 0x82c, + 0x830, 0x83c, 0x848, 0x850, + 0x8c0, 0x8b8, 0x004, 0x008, + 0x00c, 0x010, 0x038, 0x014, + 0x018, 0x01c, 0x02c, 0x030, + 0x040, 0x000, 0x020, 0x818, + 0x800, 0x004, 0x01c, +}; + static const struct imx6_pm_socdata imx6q_pm_data __initconst = { .mmdc_compat = "fsl,imx6q-mmdc", .src_compat = "fsl,imx6q-src", @@ -156,6 +449,19 @@ .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), .mmdc_io_offset = imx6q_mmdc_io_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, +}; + +static const struct imx6_pm_socdata imx6q_lpddr2_pm_data __initconst = { + .mmdc_compat = "fsl,imx6q-mmdc", + .src_compat = "fsl,imx6q-src", + .iomuxc_compat = "fsl,imx6q-iomuxc", + .gpc_compat = "fsl,imx6q-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_lpddr2_offset), + .mmdc_io_offset = imx6q_mmdc_io_lpddr2_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, }; static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { @@ -166,6 +472,8 @@ .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), .mmdc_io_offset = imx6dl_mmdc_io_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, }; static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { @@ -176,16 +484,8 @@ .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), .mmdc_io_offset = imx6sl_mmdc_io_offset, -}; - -static const struct imx6_pm_socdata imx6sll_pm_data __initconst = { - .mmdc_compat = "fsl,imx6sll-mmdc", - .src_compat = "fsl,imx6sll-src", - .iomuxc_compat = "fsl,imx6sll-iomuxc", - .gpc_compat = "fsl,imx6sll-gpc", - .pl310_compat = "arm,pl310-cache", - .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset), - .mmdc_io_offset = imx6sll_mmdc_io_offset, + .mmdc_num = 0, + .mmdc_offset = NULL, }; static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { @@ -196,6 +496,19 @@ .pl310_compat = "arm,pl310-cache", .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset), .mmdc_io_offset = imx6sx_mmdc_io_offset, + .mmdc_num = ARRAY_SIZE(imx6sx_mmdc_offset), + .mmdc_offset = imx6sx_mmdc_offset, +}; + +static const struct imx6_pm_socdata imx6sx_lpddr2_pm_data __initconst = { + .mmdc_compat = "fsl,imx6sx-mmdc", + .src_compat = "fsl,imx6sx-src", + .iomuxc_compat = "fsl,imx6sx-iomuxc", + .gpc_compat = "fsl,imx6sx-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_lpddr2_offset), + .mmdc_io_offset = imx6sx_mmdc_io_lpddr2_offset, + .mmdc_num = ARRAY_SIZE(imx6sx_mmdc_lpddr2_offset), + .mmdc_offset = imx6sx_mmdc_lpddr2_offset, }; static const struct imx6_pm_socdata imx6ul_pm_data __initconst = { @@ -206,6 +519,56 @@ .pl310_compat = NULL, .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset), .mmdc_io_offset = imx6ul_mmdc_io_offset, + .mmdc_num = ARRAY_SIZE(imx6ul_mmdc_offset), + .mmdc_offset = imx6ul_mmdc_offset, +}; + +static const struct imx6_pm_socdata imx6ul_lpddr2_pm_data __initconst = { + .mmdc_compat = "fsl,imx6ul-mmdc", + .src_compat = "fsl,imx6ul-src", + .iomuxc_compat = "fsl,imx6ul-iomuxc", + .gpc_compat = "fsl,imx6ul-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_lpddr2_offset), + .mmdc_io_offset = imx6ul_mmdc_io_lpddr2_offset, + .mmdc_num = ARRAY_SIZE(imx6ul_mmdc_lpddr2_offset), + .mmdc_offset = imx6ul_mmdc_lpddr2_offset, +}; + +static const struct imx6_pm_socdata imx6sll_pm_data __initconst = { + .mmdc_compat = "fsl,imx6sll-mmdc", + .src_compat = "fsl,imx6sll-src", + .iomuxc_compat = "fsl,imx6sll-iomuxc", + .gpc_compat = "fsl,imx6sll-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset), + .mmdc_io_offset = imx6sll_mmdc_io_offset, + .mmdc_num = ARRAY_SIZE(imx6sll_mmdc_lpddr3_offset), + .mmdc_offset = imx6sll_mmdc_lpddr3_offset, +}; + +static struct map_desc iram_tlb_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +/* + * AIPS1 and AIPS2 is not used, because it will trigger a BUG_ON if + * lowlevel debug and earlyprintk are configured. + * + * it is because there is a vm conflict because UART1 is mapped early if + * AIPS1 is mapped using 1M size. + * + * Thus no use AIPS1 and AIPS2 to avoid kernel BUG_ON. + */ +static struct map_desc imx6_pm_io_desc[] __initdata = { + imx_map_entry(MX6Q, MMDC_P0, MT_DEVICE), + imx_map_entry(MX6Q, MMDC_P1, MT_DEVICE), + imx_map_entry(MX6Q, SRC, MT_DEVICE), + imx_map_entry(MX6Q, IOMUXC, MT_DEVICE), + imx_map_entry(MX6Q, CCM, MT_DEVICE), + imx_map_entry(MX6Q, ANATOP, MT_DEVICE), + imx_map_entry(MX6Q, GPC, MT_DEVICE), + imx_map_entry(MX6Q, L2, MT_DEVICE), }; /* @@ -220,14 +583,19 @@ phys_addr_t resume_addr; /* The physical resume address for asm code */ u32 ddr_type; u32 pm_info_size; /* Size of pm_info. */ - struct imx6_pm_base mmdc_base; + struct imx6_pm_base mmdc0_base; + struct imx6_pm_base mmdc1_base; struct imx6_pm_base src_base; struct imx6_pm_base iomuxc_base; struct imx6_pm_base ccm_base; struct imx6_pm_base gpc_base; struct imx6_pm_base l2_base; + struct imx6_pm_base anatop_base; + u32 ttbr1; /* Store TTBR1 */ u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ - u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ + u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][3]; /* To save offset, value, low power settings */ + u32 mmdc_num; /* Number of MMDC registers which need saved/restored. */ + u32 mmdc_val[MX6_MAX_MMDC_NUM][2]; } __aligned(8); void imx6_set_int_mem_clk_lpm(bool enable) @@ -306,11 +674,18 @@ val |= 0x2 << BP_CLPCR_LPM; val &= ~BM_CLPCR_VSTBY; val &= ~BM_CLPCR_SBYOS; - if (cpu_is_imx6sl()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6sll()) val |= BM_CLPCR_BYPASS_PMIC_READY; if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || - cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz()) + cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + else if (cpu_is_imx6q() && + imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 && + imx_mmdc_get_lpddr2_2ch_mode() == IMX_LPDDR2_2CH_MODE) { + /* keep handshake enabled for lpddr2 2ch-mode */ + val &= ~BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + val &= ~BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; break; @@ -324,11 +699,18 @@ val |= 0x3 << BP_CLPCR_STBY_COUNT; val |= BM_CLPCR_VSTBY; val |= BM_CLPCR_SBYOS; - if (cpu_is_imx6sl() || cpu_is_imx6sx()) + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6sll()) val |= BM_CLPCR_BYPASS_PMIC_READY; if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || - cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz()) + cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + else if (cpu_is_imx6q() && + imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 && + imx_mmdc_get_lpddr2_2ch_mode() == IMX_LPDDR2_2CH_MODE) { + /* keep handshake enabled for lpddr2 2ch-mode */ + val &= ~BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + val &= ~BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; break; @@ -359,8 +741,18 @@ return 0; } +#define MX6Q_SUSPEND_PARAM \ + ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + static int imx6q_suspend_finish(unsigned long val) { + if (psci_ops.cpu_suspend) { + return psci_ops.cpu_suspend(MX6Q_SUSPEND_PARAM, + __pa(cpu_resume)); + } + if (!imx6_suspend_in_ocram_fn) { cpu_do_idle(); } else { @@ -379,19 +771,104 @@ return 0; } +static void imx6_console_save(unsigned int *regs) +{ + if (!console_base) + return; + + regs[0] = readl_relaxed(console_base + UART_UCR1); + regs[1] = readl_relaxed(console_base + UART_UCR2); + regs[2] = readl_relaxed(console_base + UART_UCR3); + regs[3] = readl_relaxed(console_base + UART_UCR4); + regs[4] = readl_relaxed(console_base + UART_UFCR); + regs[5] = readl_relaxed(console_base + UART_UESC); + regs[6] = readl_relaxed(console_base + UART_UTIM); + regs[7] = readl_relaxed(console_base + UART_UBIR); + regs[8] = readl_relaxed(console_base + UART_UBMR); + regs[9] = readl_relaxed(console_base + UART_UTS); +} + +static void imx6_console_restore(unsigned int *regs) +{ + if (!console_base) + return; + + writel_relaxed(regs[4], console_base + UART_UFCR); + writel_relaxed(regs[5], console_base + UART_UESC); + writel_relaxed(regs[6], console_base + UART_UTIM); + writel_relaxed(regs[7], console_base + UART_UBIR); + writel_relaxed(regs[8], console_base + UART_UBMR); + writel_relaxed(regs[9], console_base + UART_UTS); + writel_relaxed(regs[0], console_base + UART_UCR1); + writel_relaxed(regs[1] | 0x1, console_base + UART_UCR2); + writel_relaxed(regs[2], console_base + UART_UCR3); + writel_relaxed(regs[3], console_base + UART_UCR4); +} + +static void imx6_qspi_save(struct qspi_regs *pregs, int reg_num) +{ + int i; + + if (!qspi_base) + return; + + for (i = 0; i < reg_num; i++) { + if (QSPI_RETRIEVED == pregs[i].valuetype) + pregs[i].value = readl_relaxed(qspi_base + + pregs[i].offset); + } +} + +static void imx6_qspi_restore(struct qspi_regs *pregs, int reg_num) +{ + int i; + + if (!qspi_base) + return; + + for (i = 0; i < reg_num; i++) + writel_relaxed(pregs[i].value, qspi_base + pregs[i].offset); +} + static int imx6q_pm_enter(suspend_state_t state) { + unsigned int console_saved_reg[10] = {0}; + static unsigned int ccm_ccgr4, ccm_ccgr6; + +#ifdef CONFIG_SOC_IMX6SX + if (imx_src_is_m4_enabled()) { + if (imx_gpc_is_m4_sleeping() && imx_mu_is_m4_in_low_freq()) { + imx_gpc_hold_m4_in_sleep(); + imx_mu_enable_m4_irqs_in_gic(true); + } else { + pr_info("M4 is busy, enter WAIT mode instead of STOP!\n"); + imx6_set_lpm(WAIT_UNCLOCKED); + imx6_set_int_mem_clk_lpm(true); + imx_gpc_pre_suspend(false); + /* Zzz ... */ + cpu_do_idle(); + imx_gpc_post_resume(); + imx6_set_lpm(WAIT_CLOCKED); + + return 0; + } + } +#endif switch (state) { case PM_SUSPEND_STANDBY: imx6_set_lpm(STOP_POWER_ON); imx6_set_int_mem_clk_lpm(true); imx_gpc_pre_suspend(false); +#ifdef CONFIG_SOC_IMX6SL if (cpu_is_imx6sl()) imx6sl_set_wait_clk(true); +#endif /* Zzz ... */ cpu_do_idle(); +#ifdef CONFIG_SOC_IMX6SL if (cpu_is_imx6sl()) imx6sl_set_wait_clk(false); +#endif imx_gpc_post_resume(); imx6_set_lpm(WAIT_CLOCKED); break; @@ -407,8 +884,50 @@ imx6_enable_rbc(true); imx_gpc_pre_suspend(true); imx_anatop_pre_suspend(); + if ((cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) && + imx_gpc_is_mf_mix_off()) + imx6_console_save(console_saved_reg); + if (cpu_is_imx6sx() && imx_gpc_is_mf_mix_off()) { + ccm_ccgr4 = readl_relaxed(ccm_base + CCGR4); + ccm_ccgr6 = readl_relaxed(ccm_base + CCGR6); + /* + * i.MX6SX RDC needs PCIe and eim clk to be enabled + * if Mega/Fast off, it is better to check cpu type + * and whether Mega/Fast is off in this suspend flow, + * but we need to add cpu type check for 3 places which + * will increase code size, so here we just do it + * for all cases, as when STOP mode is entered, CCM + * hardware will gate all clocks, so it will NOT impact + * any function or power. + */ + writel_relaxed(ccm_ccgr4 | (0x3 << 0), ccm_base + + CCGR4); + writel_relaxed(ccm_ccgr6 | (0x3 << 10), ccm_base + + CCGR6); + memcpy(ocram_saved_in_ddr, ocram_base, ocram_size); + imx6_console_save(console_saved_reg); + if (imx_src_is_m4_enabled()) + imx6_qspi_save(qspi_regs_imx6sx, + sizeof(qspi_regs_imx6sx) / + sizeof(struct qspi_regs)); + } + /* Zzz ... */ cpu_suspend(0, imx6q_suspend_finish); + + if (cpu_is_imx6sx() && imx_gpc_is_mf_mix_off()) { + writel_relaxed(ccm_ccgr4, ccm_base + CCGR4); + writel_relaxed(ccm_ccgr6, ccm_base + CCGR6); + memcpy(ocram_base, ocram_saved_in_ddr, ocram_size); + imx6_console_restore(console_saved_reg); + if (imx_src_is_m4_enabled()) + imx6_qspi_restore(qspi_regs_imx6sx, + sizeof(qspi_regs_imx6sx) / + sizeof(struct qspi_regs)); + } + if ((cpu_is_imx6ull() || cpu_is_imx6ulz() || cpu_is_imx6sll()) && + imx_gpc_is_mf_mix_off()) + imx6_console_restore(console_saved_reg); if (cpu_is_imx6q() || cpu_is_imx6dl()) imx_smp_prepare(); imx_anatop_post_resume(); @@ -422,6 +941,13 @@ return -EINVAL; } +#ifdef CONFIG_SOC_IMX6SX + if (imx_src_is_m4_enabled()) { + imx_mu_enable_m4_irqs_in_gic(false); + imx_gpc_release_m4_in_sleep(); + } +#endif + return 0; } @@ -435,41 +961,113 @@ .valid = imx6q_pm_valid, }; -static int __init imx6_pm_get_base(struct imx6_pm_base *base, - const char *compat) +static int __init imx6_dt_find_lpsram(unsigned long node, const char *uname, + int depth, void *data) { - struct device_node *node; - struct resource res; - int ret = 0; + unsigned long lpram_addr; + const __be32 *prop = of_get_flat_dt_prop(node, "reg", NULL); - node = of_find_compatible_node(NULL, NULL, compat); - if (!node) - return -ENODEV; - - ret = of_address_to_resource(node, 0, &res); - if (ret) - goto put_node; - - base->pbase = res.start; - base->vbase = ioremap(res.start, resource_size(&res)); - if (!base->vbase) - ret = -ENOMEM; + if (of_flat_dt_is_compatible(node, "fsl,lpm-sram")) { + if (!prop) + return -EINVAL; + + lpram_addr = be32_to_cpup(prop); + + /* We need to create a 1M page table entry. */ + iram_tlb_io_desc.virtual = IMX_IO_P2V(lpram_addr & 0xFFF00000); + iram_tlb_io_desc.pfn = __phys_to_pfn(lpram_addr & 0xFFF00000); + iram_tlb_phys_addr = lpram_addr; + iram_tlb_base_addr = IMX_IO_P2V(lpram_addr); -put_node: - of_node_put(node); - return ret; + iotable_init(&iram_tlb_io_desc, 1); + } + + return 0; +} + +void __init imx6_pm_map_io(void) +{ + unsigned long i; + + iotable_init(imx6_pm_io_desc, ARRAY_SIZE(imx6_pm_io_desc)); + + /* + * Get the address of IRAM or OCRAM to be used by the low + * power code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx6_dt_find_lpsram, NULL)); + + /* + * We moved suspend/resume and lowpower idle to TEE, + * But busfreq now still in Linux, this table is still needed + * If we later decide to move busfreq to TEE, we could drop this. + */ + /* Return if no IRAM space is allocated for suspend/resume code. */ + if (!iram_tlb_base_addr) { + pr_warn("No IRAM/OCRAM memory allocated for suspend/resume \ + code. Please ensure device tree has an entry for \ + fsl,lpm-sram.\n"); + return; + } + + /* Set all entries to 0. */ + memset((void *)iram_tlb_base_addr, 0, MX6Q_IRAM_TLB_SIZE); + + /* + * Make sure the IRAM virtual address has a mapping in the IRAM + * page table. + * + * Only use the top 11 bits [31-20] when storing the physical + * address in the page table as only these bits are required + * for 1M mapping. + */ + i = ((iram_tlb_base_addr >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (iram_tlb_phys_addr & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS1 virtual address has a mapping in the + * IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_AIPS1_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_AIPS1_BASE_ADDR & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS2 virtual address has a mapping in the + * IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_AIPS2_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_AIPS2_BASE_ADDR & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS3 virtual address has a mapping + * in the IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_AIPS3_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_AIPS3_BASE_ADDR & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the L2 controller virtual address has a mapping + * in the IRAM page table. + */ + i = ((IMX_IO_P2V(MX6Q_L2_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + i) = + (MX6Q_L2_BASE_ADDR & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; } static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) { - phys_addr_t ocram_pbase; - struct device_node *node; - struct platform_device *pdev; struct imx6_cpu_pm_info *pm_info; - struct gen_pool *ocram_pool; - unsigned long ocram_base; + unsigned long iram_paddr; int i, ret = 0; const u32 *mmdc_offset_array; + const u32 *mmdc_io_offset_array; suspend_set_ops(&imx6q_pm_ops); @@ -478,41 +1076,27 @@ return -EINVAL; } - node = of_find_compatible_node(NULL, NULL, "mmio-sram"); - if (!node) { - pr_warn("%s: failed to find ocram node!\n", __func__); - return -ENODEV; - } - - pdev = of_find_device_by_node(node); - if (!pdev) { - pr_warn("%s: failed to find ocram device!\n", __func__); - ret = -ENODEV; - goto put_node; - } + if (psci_ops.cpu_suspend) + return ret; - ocram_pool = gen_pool_get(&pdev->dev, NULL); - if (!ocram_pool) { - pr_warn("%s: ocram pool unavailable!\n", __func__); - ret = -ENODEV; - goto put_device; - } - - ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); - if (!ocram_base) { - pr_warn("%s: unable to alloc ocram!\n", __func__); - ret = -ENOMEM; - goto put_device; - } + /* + * 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB, + * The lower 8K is not used, so use the lower 8K for IRAM code and + * pm_info. + * + */ + iram_paddr = iram_tlb_phys_addr + MX6_SUSPEND_IRAM_ADDR_OFFSET; - ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); + /* Make sure iram_paddr is 8 byte aligned. */ + if ((uintptr_t)(iram_paddr) & (FNCPY_ALIGN - 1)) + iram_paddr += FNCPY_ALIGN - iram_paddr % (FNCPY_ALIGN); - suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, - MX6Q_SUSPEND_OCRAM_SIZE, false); + /* Get the virtual address of the suspend code. */ + suspend_ocram_base = (void *)IMX_IO_P2V(iram_paddr); memset(suspend_ocram_base, 0, sizeof(*pm_info)); pm_info = suspend_ocram_base; - pm_info->pbase = ocram_pbase; + pm_info->pbase = iram_paddr; pm_info->resume_addr = __pa_symbol(v7_cpu_resume); pm_info->pm_info_size = sizeof(*pm_info); @@ -520,51 +1104,118 @@ * ccm physical address is not used by asm code currently, * so get ccm virtual address directly. */ - pm_info->ccm_base.vbase = ccm_base; + pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR; + pm_info->ccm_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_CCM_BASE_ADDR); + + pm_info->mmdc0_base.pbase = MX6Q_MMDC_P0_BASE_ADDR; + pm_info->mmdc0_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR); + + pm_info->mmdc1_base.pbase = MX6Q_MMDC_P1_BASE_ADDR; + pm_info->mmdc1_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_MMDC_P1_BASE_ADDR); + + pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR; + pm_info->src_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_SRC_BASE_ADDR); + + pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR; + pm_info->iomuxc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR); + + pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR; + pm_info->gpc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_GPC_BASE_ADDR); + + pm_info->l2_base.pbase = MX6Q_L2_BASE_ADDR; + pm_info->l2_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_L2_BASE_ADDR); + + pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR; + pm_info->anatop_base.vbase = (void __iomem *) + IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR); - ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); - if (ret) { - pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); - goto put_device; + pm_info->ddr_type = imx_mmdc_get_ddr_type(); + pm_info->mmdc_io_num = socdata->mmdc_io_num; + mmdc_io_offset_array = socdata->mmdc_io_offset; + pm_info->mmdc_num = socdata->mmdc_num; + mmdc_offset_array = socdata->mmdc_offset; + + for (i = 0; i < pm_info->mmdc_io_num; i++) { + pm_info->mmdc_io_val[i][0] = + mmdc_io_offset_array[i]; + pm_info->mmdc_io_val[i][1] = + readl_relaxed(pm_info->iomuxc_base.vbase + + mmdc_io_offset_array[i]); + pm_info->mmdc_io_val[i][2] = 0; } - ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); - if (ret) { - pr_warn("%s: failed to get src base %d!\n", __func__, ret); - goto src_map_failed; + /* i.MX6SLL has no DRAM RESET pin */ + if (cpu_is_imx6sll()) { + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 2][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 1][2] = 0x1000; + } else { + if (pm_info->ddr_type == IMX_DDR_TYPE_LPDDR2) { + /* for LPDDR2, CKE0/1 and RESET pin need special setting */ + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 3][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 2][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 1][2] = 0x80000; + } } - ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); - if (ret) { - pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); - goto iomuxc_map_failed; + /* initialize MMDC settings */ + for (i = 0; i < pm_info->mmdc_num; i++) { + pm_info->mmdc_val[i][0] = + mmdc_offset_array[i]; + pm_info->mmdc_val[i][1] = + readl_relaxed(pm_info->mmdc0_base.vbase + + mmdc_offset_array[i]); } - ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); - if (ret) { - pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); - goto gpc_map_failed; + if (cpu_is_imx6sll() && pm_info->ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) { + pm_info->mmdc_val[0][1] = 0x8000; + pm_info->mmdc_val[2][1] = 0xa1390003; + pm_info->mmdc_val[3][1] = 0x400000; + pm_info->mmdc_val[4][1] = 0x800; + pm_info->mmdc_val[13][1] = 0x800; + pm_info->mmdc_val[14][1] = 0x20052; + pm_info->mmdc_val[20][1] = 0x201718; + pm_info->mmdc_val[21][1] = 0x8000; + pm_info->mmdc_val[28][1] = 0xa1310003; } - if (socdata->pl310_compat) { - ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat); - if (ret) { - pr_warn("%s: failed to get pl310-cache base %d!\n", - __func__, ret); - goto pl310_cache_map_failed; - } + /* need to overwrite the value for some mmdc registers */ + if ((cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz()) && + pm_info->ddr_type != IMX_DDR_TYPE_LPDDR2) { + pm_info->mmdc_val[20][1] = (pm_info->mmdc_val[20][1] + & 0xffff0000) | 0x0202; + pm_info->mmdc_val[23][1] = 0x8033; } - pm_info->ddr_type = imx_mmdc_get_ddr_type(); - pm_info->mmdc_io_num = socdata->mmdc_io_num; - mmdc_offset_array = socdata->mmdc_io_offset; + if (cpu_is_imx6sx() && + pm_info->ddr_type == IMX_DDR_TYPE_LPDDR2) { + pm_info->mmdc_val[0][1] = 0x8000; + pm_info->mmdc_val[2][1] = 0xa1390003; + pm_info->mmdc_val[3][1] = 0x380000; + pm_info->mmdc_val[4][1] = 0x800; + pm_info->mmdc_val[18][1] = 0x800; + pm_info->mmdc_val[20][1] = 0x20024; + pm_info->mmdc_val[23][1] = 0x1748; + pm_info->mmdc_val[32][1] = 0xa1310003; + } - for (i = 0; i < pm_info->mmdc_io_num; i++) { - pm_info->mmdc_io_val[i][0] = - mmdc_offset_array[i]; - pm_info->mmdc_io_val[i][1] = - readl_relaxed(pm_info->iomuxc_base.vbase + - mmdc_offset_array[i]); + if ((cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz()) && + pm_info->ddr_type == IMX_DDR_TYPE_LPDDR2) { + pm_info->mmdc_val[0][1] = 0x8000; + pm_info->mmdc_val[2][1] = 0xa1390003; + pm_info->mmdc_val[3][1] = 0x470000; + pm_info->mmdc_val[4][1] = 0x800; + pm_info->mmdc_val[13][1] = 0x800; + pm_info->mmdc_val[14][1] = 0x20012; + pm_info->mmdc_val[20][1] = 0x1748; + pm_info->mmdc_val[21][1] = 0x8000; + pm_info->mmdc_val[28][1] = 0xa1310003; } imx6_suspend_in_ocram_fn = fncpy( @@ -572,23 +1223,6 @@ &imx6_suspend, MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); - __arm_iomem_set_ro(suspend_ocram_base, MX6Q_SUSPEND_OCRAM_SIZE); - - goto put_device; - -pl310_cache_map_failed: - iounmap(pm_info->gpc_base.vbase); -gpc_map_failed: - iounmap(pm_info->iomuxc_base.vbase); -iomuxc_map_failed: - iounmap(pm_info->src_base.vbase); -src_map_failed: - iounmap(pm_info->mmdc_base.vbase); -put_device: - put_device(&pdev->dev); -put_node: - of_node_put(node); - return ret; } @@ -620,29 +1254,6 @@ IMX6Q_GPR1_GINT); } -static void imx6_pm_stby_poweroff(void) -{ - gic_cpu_if_down(0); - imx6_set_lpm(STOP_POWER_OFF); - imx6q_suspend_finish(0); - - mdelay(1000); - - pr_emerg("Unable to poweroff system\n"); -} - -static int imx6_pm_stby_poweroff_probe(void) -{ - if (pm_power_off) { - pr_warn("%s: pm_power_off already claimed %p %ps!\n", - __func__, pm_power_off, pm_power_off); - return -EBUSY; - } - - pm_power_off = imx6_pm_stby_poweroff; - return 0; -} - void __init imx6_pm_ccm_init(const char *ccm_compat) { struct device_node *np; @@ -660,15 +1271,15 @@ val &= ~BM_CLPCR_LPM; writel_relaxed(val, ccm_base + CLPCR); - if (of_property_read_bool(np, "fsl,pmic-stby-poweroff")) - imx6_pm_stby_poweroff_probe(); - of_node_put(np); } void __init imx6q_pm_init(void) { - imx6_pm_common_init(&imx6q_pm_data); + if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx6_pm_common_init(&imx6q_lpddr2_pm_data); + else + imx6_pm_common_init(&imx6q_pm_data); } void __init imx6dl_pm_init(void) @@ -678,25 +1289,96 @@ void __init imx6sl_pm_init(void) { + struct device_node *np; struct regmap *gpr; - if (cpu_is_imx6sl()) { - imx6_pm_common_init(&imx6sl_pm_data); - } else { + if (cpu_is_imx6sll()) { imx6_pm_common_init(&imx6sll_pm_data); + np = of_find_node_by_path( + "/soc/bus@2000000/spba-bus@2000000/serial@2020000"); + if (np) + console_base = of_iomap(np, 0); + /* i.MX6SLL has bus auto clock gating function */ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) regmap_update_bits(gpr, IOMUXC_GPR5, - IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0); + IOMUXC_GPR5_CLOCK_AFCG_X_BYPASS_MASK, 0); + return; } + + imx6_pm_common_init(&imx6sl_pm_data); } void __init imx6sx_pm_init(void) { - imx6_pm_common_init(&imx6sx_pm_data); + struct device_node *np; + struct resource res; + + if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx6_pm_common_init(&imx6sx_lpddr2_pm_data); + else + imx6_pm_common_init(&imx6sx_pm_data); + if (imx_get_soc_revision() < IMX_CHIP_REVISION_1_2) { + /* + * As there is a 16K OCRAM(start from 0x8f8000) + * dedicated for low power function on i.MX6SX, + * but ROM did NOT do the ocram address change + * accordingly, so we need to add a data patch + * to workaround this issue, otherwise, system + * will fail to resume from DSM mode. TO1.2 fixes + * this issue. + */ + romcp = syscon_regmap_lookup_by_compatible( + "fsl,imx6sx-romcp"); + if (IS_ERR(romcp)) { + pr_err("failed to find fsl,imx6sx-romcp regmap\n"); + return; + } + regmap_write(romcp, ROMC_ROMPATCH0D, iram_tlb_phys_addr); + regmap_update_bits(romcp, ROMC_ROMPATCHCNTL, + BM_ROMPATCHCNTL_0D, BM_ROMPATCHCNTL_0D); + regmap_update_bits(romcp, ROMC_ROMPATCHENL, + BM_ROMPATCHENL_0D, BM_ROMPATCHENL_0D); + regmap_write(romcp, ROMC_ROMPATCH0A, + ROM_ADDR_FOR_INTERNAL_RAM_BASE); + regmap_update_bits(romcp, ROMC_ROMPATCHCNTL, + BM_ROMPATCHCNTL_DIS, ~BM_ROMPATCHCNTL_DIS); + } + + np = of_find_compatible_node(NULL, NULL, "fsl,mega-fast-sram"); + ocram_base = of_iomap(np, 0); + WARN_ON(!ocram_base); + WARN_ON(of_address_to_resource(np, 0, &res)); + ocram_size = resource_size(&res); + ocram_saved_in_ddr = kzalloc(ocram_size, GFP_KERNEL); + WARN_ON(!ocram_saved_in_ddr); + + np = of_find_node_by_path( + "/soc/bus@2000000/spba-bus@2000000/serial@2020000"); + if (np) + console_base = of_iomap(np, 0); + if (imx_src_is_m4_enabled()) { + np = of_find_compatible_node(NULL, NULL, + "fsl,imx6sx-qspi-m4-restore"); + if (np) + qspi_base = of_iomap(np, 0); + WARN_ON(!qspi_base); + } } void __init imx6ul_pm_init(void) { - imx6_pm_common_init(&imx6ul_pm_data); + struct device_node *np; + + if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx6_pm_common_init(&imx6ul_lpddr2_pm_data); + else + imx6_pm_common_init(&imx6ul_pm_data); + + if (cpu_is_imx6ull() || cpu_is_imx6ulz()) { + np = of_find_node_by_path( + "/soc/bus@2000000/spba-bus@2000000/serial@2020000"); + if (np) + console_base = of_iomap(np, 0); + } } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/pm-imx7.c linux-imx-phytec/arch/arm/mach-imx/pm-imx7.c --- linux-6.1.55/arch/arm/mach-imx/pm-imx7.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/pm-imx7.c 2024-06-19 12:33:58.132189693 +0200 @@ -0,0 +1,1225 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "hardware.h" +#include "cpuidle.h" + +#define MX7_SUSPEND_OCRAM_SIZE 0x1000 +#define MX7_MAX_DDRC_NUM 32 +#define MX7_MAX_DDRC_PHY_NUM 16 + +#define MX7_SUSPEND_IRAM_ADDR_OFFSET 0 +#define READ_DATA_FROM_HARDWARE 0 + +#define UART_UCR1 0x80 +#define UART_UCR2 0x84 +#define UART_UCR3 0x88 +#define UART_UCR4 0x8c +#define UART_UFCR 0x90 +#define UART_UESC 0x9c +#define UART_UTIM 0xa0 +#define UART_UBIR 0xa4 +#define UART_UBMR 0xa8 +#define UART_UBRC 0xac +#define UART_UTS 0xb4 + +#define MAX_IOMUXC_GPR 23 +#define MAX_UART_IO 4 +#define MAX_CCM_LPCG 167 +#define MAX_GPT 3 +#define MAX_GPIO_ROW 7 +#define MAX_GPIO_COL 8 + +#define UART_RX_IO 0x128 +#define UART_RX_PAD 0x398 +#define UART_TX_IO 0x12c +#define UART_TX_PAD 0x39c + +#define GPT_CR 0x0 +#define GPT_PR 0x4 +#define GPT_IR 0xc + +#define CCM_LPCG_START 0x4040 +#define CCM_LPCG_STEP 0x10 +#define CCM_EIM_LPCG 0x4160 +#define CCM_PXP_LPCG 0x44c0 +#define CCM_PCIE_LPCG 0x4600 + +#define BM_CCM_ROOT_POST_PODF 0x3f +#define BM_CCM_ROOT_PRE_PODF 0x70000 +#define BM_CCM_ROOT_MUX 0x7000000 +#define BM_CCM_ROOT_ENABLE 0x10000000 + +#define SYS_COUNTER_CNTSR 0x4 +#define BM_SYS_COUNTER_CNTSR_FCR1 0x200 +#define BM_SYS_COUNTER_CNTSR_FCR0 0x100 +#define BM_SYS_COUNTER_CNTCR_FCR1 0x200 +#define BM_SYS_COUNTER_CNTCR_FCR0 0x100 + +#define PFD_A_OFFSET 0xc0 +#define PFD_B_OFFSET 0xd0 + +#define PLL_ARM_OFFSET 0x60 +#define PLL_DDR_OFFSET 0x70 +#define PLL_DDR_SS_OFFSET 0x80 +#define PLL_DDR_NUM_OFFSET 0x90 +#define PLL_DDR_DENOM_OFFSET 0xa0 +#define PLL_480_OFFSET 0xb0 +#define PLL_ENET_OFFSET 0xe0 +#define PLL_AUDIO_OFFSET 0xf0 +#define PLL_AUDIO_SS_OFFSET 0x100 +#define PLL_AUDIO_NUM_OFFSET 0x110 +#define PLL_AUDIO_DENOM_OFFSET 0x120 +#define PLL_VIDEO_OFFSET 0x130 +#define PLL_VIDEO_SS_OFFSET 0x140 +#define PLL_VIDEO_NUM_OFFSET 0x150 +#define PLL_VIDEO_DENOM_OFFSET 0x160 + +#define REG_SET 0x4 +#define REG_CLR 0x8 + +#define GPIO_DR 0x0 +#define GPIO_GDIR 0x4 +#define GPIO_ICR1 0xc +#define GPIO_ICR2 0x10 +#define GPIO_IMR 0x14 +#define GPIO_EDGE 0x1c + +#define M4RCR 0x0C +#define M4_SP_OFF 0x00 +#define M4_PC_OFF 0x04 +#define M4_RCR_HALT 0xAB +#define M4_RCR_GO 0xAA +#define M4_OCRAMS_RESERVED_SIZE 0xc + +extern unsigned long iram_tlb_base_addr; +extern unsigned long iram_tlb_phys_addr; + +static unsigned int *ocram_saved_in_ddr; +static void __iomem *ocram_base; +static unsigned int ocram_size; +static unsigned int *lpm_ocram_saved_in_ddr; +static void __iomem *lpm_ocram_base; + +static unsigned int *lpm_m4tcm_saved_in_ddr; +static void __iomem *lpm_m4tcm_base; +static void __iomem *m4_bootrom_base; + +static unsigned int lpm_ocram_size; +static void __iomem *ccm_base; +static void __iomem *lpsr_base; +static void __iomem *console_base; +static void __iomem *suspend_ocram_base; +static void __iomem *iomuxc_base; +static void __iomem *gpt1_base; +static void __iomem *system_counter_ctrl_base; +static void __iomem *system_counter_cmp_base; +static void __iomem *gpio1_base; +static void (*imx7_suspend_in_ocram_fn)(void __iomem *ocram_vbase); +struct imx7_cpu_pm_info *pm_info; +static bool lpsr_enabled; +static u32 iomuxc_gpr[MAX_IOMUXC_GPR]; +static u32 uart1_io[MAX_UART_IO]; +static u32 ccm_lpcg[MAX_CCM_LPCG]; +static u32 ccm_root[][2] = { + {0x8000, 0}, {0x8080, 0}, {0x8100, 0}, {0x8800, 0}, + {0x8880, 0}, {0x8900, 0}, {0x8980, 0}, {0x9000, 0}, + {0x9800, 0}, {0x9880, 0}, {0xa000, 0}, {0xa080, 0}, + {0xa100, 0}, {0xa180, 0}, {0xa200, 0}, {0xa280, 0}, + {0xa300, 0}, {0xa380, 0}, {0xa400, 0}, {0xa480, 0}, + {0xa500, 0}, {0xa580, 0}, {0xa600, 0}, {0xa680, 0}, + {0xa700, 0}, {0xa780, 0}, {0xa800, 0}, {0xa880, 0}, + {0xa900, 0}, {0xa980, 0}, {0xaa00, 0}, {0xaa80, 0}, + {0xab00, 0}, {0xab80, 0}, {0xac00, 0}, {0xac80, 0}, + {0xad00, 0}, {0xad80, 0}, {0xae00, 0}, {0xae80, 0}, + {0xaf00, 0}, {0xaf80, 0}, {0xb000, 0}, {0xb080, 0}, + {0xb100, 0}, {0xb180, 0}, {0xb200, 0}, {0xb280, 0}, + {0xb300, 0}, {0xb380, 0}, {0xb400, 0}, {0xb480, 0}, + {0xb500, 0}, {0xb580, 0}, {0xb600, 0}, {0xb680, 0}, + {0xb700, 0}, {0xb780, 0}, {0xb800, 0}, {0xb880, 0}, + {0xb900, 0}, {0xb980, 0}, {0xba00, 0}, {0xba80, 0}, + {0xbb00, 0}, {0xbb80, 0}, {0xbc00, 0}, {0xbc80, 0}, + {0xbd00, 0}, {0xbd80, 0}, {0xbe00, 0}, +}; +static u32 pfd_a, pfd_b; +static u32 pll[15]; +static u32 gpt1_regs[MAX_GPT]; +static u32 sys_ctrl_reg, sys_cmp_reg; +static u32 gpio_reg[MAX_GPIO_ROW][MAX_GPIO_COL]; +/* + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7_suspend code + * PM_INFO structure(imx7_cpu_pm_info) + * ======================== low address ======================= + */ + +struct imx7_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx7_pm_socdata { + u32 ddr_type; + const char *ddrc_compat; + const char *src_compat; + const char *iomuxc_compat; + const char *gpc_compat; + const u32 ddrc_num; + const u32 (*ddrc_offset)[2]; + const u32 ddrc_phy_num; + const u32 (*ddrc_phy_offset)[2]; +}; + +static const u32 imx7d_ddrc_lpddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x1a0, READ_DATA_FROM_HARDWARE }, + { 0x1a4, READ_DATA_FROM_HARDWARE }, + { 0x1a8, READ_DATA_FROM_HARDWARE }, + { 0x64, READ_DATA_FROM_HARDWARE }, + { 0xd0, READ_DATA_FROM_HARDWARE }, + { 0xdc, READ_DATA_FROM_HARDWARE }, + { 0xe0, READ_DATA_FROM_HARDWARE }, + { 0xe4, READ_DATA_FROM_HARDWARE }, + { 0xf4, READ_DATA_FROM_HARDWARE }, + { 0x100, READ_DATA_FROM_HARDWARE }, + { 0x104, READ_DATA_FROM_HARDWARE }, + { 0x108, READ_DATA_FROM_HARDWARE }, + { 0x10c, READ_DATA_FROM_HARDWARE }, + { 0x110, READ_DATA_FROM_HARDWARE }, + { 0x114, READ_DATA_FROM_HARDWARE }, + { 0x118, READ_DATA_FROM_HARDWARE }, + { 0x120, READ_DATA_FROM_HARDWARE }, + { 0x11c, READ_DATA_FROM_HARDWARE }, + { 0x180, READ_DATA_FROM_HARDWARE }, + { 0x184, READ_DATA_FROM_HARDWARE }, + { 0x190, READ_DATA_FROM_HARDWARE }, + { 0x194, READ_DATA_FROM_HARDWARE }, + { 0x200, READ_DATA_FROM_HARDWARE }, + { 0x204, READ_DATA_FROM_HARDWARE }, + { 0x210, READ_DATA_FROM_HARDWARE }, + { 0x214, READ_DATA_FROM_HARDWARE }, + { 0x218, READ_DATA_FROM_HARDWARE }, + { 0x240, READ_DATA_FROM_HARDWARE }, + { 0x244, READ_DATA_FROM_HARDWARE }, +}; + +static const u32 imx7d_ddrc_phy_lpddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x4, READ_DATA_FROM_HARDWARE }, + { 0x8, READ_DATA_FROM_HARDWARE }, + { 0x10, READ_DATA_FROM_HARDWARE }, + { 0xb0, READ_DATA_FROM_HARDWARE }, + { 0x1c, READ_DATA_FROM_HARDWARE }, + { 0x9c, READ_DATA_FROM_HARDWARE }, + { 0x7c, READ_DATA_FROM_HARDWARE }, + { 0x80, READ_DATA_FROM_HARDWARE }, + { 0x84, READ_DATA_FROM_HARDWARE }, + { 0x88, READ_DATA_FROM_HARDWARE }, + { 0x6c, READ_DATA_FROM_HARDWARE }, + { 0x20, READ_DATA_FROM_HARDWARE }, + { 0x30, READ_DATA_FROM_HARDWARE }, + { 0x50, 0x01000008 }, + { 0x50, 0x00000008 }, + { 0xc0, 0x0e487304 }, + { 0xc0, 0x0e4c7304 }, + { 0xc0, 0x0e4c7306 }, + { 0xc0, 0x0e487304 }, +}; + +static const u32 imx7d_ddrc_ddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x1a0, READ_DATA_FROM_HARDWARE }, + { 0x1a4, READ_DATA_FROM_HARDWARE }, + { 0x1a8, READ_DATA_FROM_HARDWARE }, + { 0x64, READ_DATA_FROM_HARDWARE }, + { 0x490, READ_DATA_FROM_HARDWARE }, + { 0xd0, READ_DATA_FROM_HARDWARE }, + { 0xd4, READ_DATA_FROM_HARDWARE }, + { 0xdc, READ_DATA_FROM_HARDWARE }, + { 0xe0, READ_DATA_FROM_HARDWARE }, + { 0xe4, READ_DATA_FROM_HARDWARE }, + { 0xf4, READ_DATA_FROM_HARDWARE }, + { 0x100, READ_DATA_FROM_HARDWARE }, + { 0x104, READ_DATA_FROM_HARDWARE }, + { 0x108, READ_DATA_FROM_HARDWARE }, + { 0x10c, READ_DATA_FROM_HARDWARE }, + { 0x110, READ_DATA_FROM_HARDWARE }, + { 0x114, READ_DATA_FROM_HARDWARE }, + { 0x120, READ_DATA_FROM_HARDWARE }, + { 0x180, READ_DATA_FROM_HARDWARE }, + { 0x190, READ_DATA_FROM_HARDWARE }, + { 0x194, READ_DATA_FROM_HARDWARE }, + { 0x200, READ_DATA_FROM_HARDWARE }, + { 0x204, READ_DATA_FROM_HARDWARE }, + { 0x210, READ_DATA_FROM_HARDWARE }, + { 0x214, READ_DATA_FROM_HARDWARE }, + { 0x218, READ_DATA_FROM_HARDWARE }, + { 0x240, READ_DATA_FROM_HARDWARE }, + { 0x244, READ_DATA_FROM_HARDWARE }, +}; + +static const u32 imx7d_ddrc_phy_ddr3_setting[][2] __initconst = { + { 0x0, READ_DATA_FROM_HARDWARE }, + { 0x4, READ_DATA_FROM_HARDWARE }, + { 0x10, READ_DATA_FROM_HARDWARE }, + { 0xb0, READ_DATA_FROM_HARDWARE }, + { 0x9c, READ_DATA_FROM_HARDWARE }, + { 0x7c, READ_DATA_FROM_HARDWARE }, + { 0x80, READ_DATA_FROM_HARDWARE }, + { 0x84, READ_DATA_FROM_HARDWARE }, + { 0x88, READ_DATA_FROM_HARDWARE }, + { 0x6c, READ_DATA_FROM_HARDWARE }, + { 0x20, READ_DATA_FROM_HARDWARE }, + { 0x30, READ_DATA_FROM_HARDWARE }, + { 0x50, 0x01000010 }, + { 0x50, 0x00000010 }, + { 0xc0, 0x0e407304 }, + { 0xc0, 0x0e447304 }, + { 0xc0, 0x0e447306 }, + { 0xc0, 0x0e407304 }, +}; + +static const struct imx7_pm_socdata imx7d_pm_data_lpddr3 __initconst = { + .ddrc_compat = "fsl,imx7d-ddrc", + .src_compat = "fsl,imx7d-src", + .iomuxc_compat = "fsl,imx7d-iomuxc", + .gpc_compat = "fsl,imx7d-gpc", + .ddrc_num = ARRAY_SIZE(imx7d_ddrc_lpddr3_setting), + .ddrc_offset = imx7d_ddrc_lpddr3_setting, + .ddrc_phy_num = ARRAY_SIZE(imx7d_ddrc_phy_lpddr3_setting), + .ddrc_phy_offset = imx7d_ddrc_phy_lpddr3_setting, +}; + +static const struct imx7_pm_socdata imx7d_pm_data_ddr3 __initconst = { + .ddrc_compat = "fsl,imx7d-ddrc", + .src_compat = "fsl,imx7d-src", + .iomuxc_compat = "fsl,imx7d-iomuxc", + .gpc_compat = "fsl,imx7d-gpc", + .ddrc_num = ARRAY_SIZE(imx7d_ddrc_ddr3_setting), + .ddrc_offset = imx7d_ddrc_ddr3_setting, + .ddrc_phy_num = ARRAY_SIZE(imx7d_ddrc_phy_ddr3_setting), + .ddrc_phy_offset = imx7d_ddrc_phy_ddr3_setting, +}; + +/* + * This structure is for passing necessary data for low level ocram + * suspend code(arch/arm/mach-imx/suspend-imx7.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/suspend-imx7.S must be also changed accordingly, + * otherwise, the suspend to ocram function will be broken! + */ +struct imx7_cpu_pm_info { + u32 m4_reserve0; + u32 m4_reserve1; + u32 m4_reserve2; + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 ddr_type; + u32 pm_info_size; /* Size of pm_info. */ + struct imx7_pm_base ddrc_base; + struct imx7_pm_base ddrc_phy_base; + struct imx7_pm_base src_base; + struct imx7_pm_base iomuxc_gpr_base; + struct imx7_pm_base ccm_base; + struct imx7_pm_base gpc_base; + struct imx7_pm_base snvs_base; + struct imx7_pm_base anatop_base; + struct imx7_pm_base lpsr_base; + struct imx7_pm_base gic_base; + u32 ttbr1; /* Store TTBR1 */ + u32 ddrc_num; /* Number of DDRC which need saved/restored. */ + u32 ddrc_val[MX7_MAX_DDRC_NUM][2]; /* To save offset and value */ + u32 ddrc_phy_num; /* Number of DDRC which need saved/restored. */ + u32 ddrc_phy_val[MX7_MAX_DDRC_NUM][2]; /* To save offset and value */ +} __aligned(8); + +static struct map_desc imx7_pm_io_desc[] __initdata = { + imx_map_entry(MX7D, AIPS1, MT_DEVICE), + imx_map_entry(MX7D, AIPS2, MT_DEVICE), + imx_map_entry(MX7D, AIPS3, MT_DEVICE), +}; + +static void imx7_gpio_save(void) +{ + u32 i; + + for (i = 0; i < 7; i++) { + gpio_reg[i][0] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_DR); + gpio_reg[i][1] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_GDIR); + gpio_reg[i][3] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_ICR1); + gpio_reg[i][4] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_ICR2); + gpio_reg[i][5] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_IMR); + gpio_reg[i][7] = readl_relaxed(gpio1_base + + (i << 16) + GPIO_EDGE); + } +} + +static void imx7_gpio_restore(void) +{ + u32 i, val; + + for (i = 0; i < 7; i++) { + writel_relaxed(gpio_reg[i][1], gpio1_base + + (i << 16) + GPIO_GDIR); + writel_relaxed(gpio_reg[i][3], gpio1_base + + (i << 16) + GPIO_ICR1); + writel_relaxed(gpio_reg[i][4], gpio1_base + + (i << 16) + GPIO_ICR2); + writel_relaxed(gpio_reg[i][5], gpio1_base + + (i << 16) + GPIO_IMR); + writel_relaxed(gpio_reg[i][7], gpio1_base + + (i << 16) + GPIO_EDGE); + /* only restore output gpio value */ + val = readl_relaxed(gpio1_base + (i << 16) + GPIO_DR) | + (gpio_reg[i][0] & gpio_reg[i][1]); + writel_relaxed(val, gpio1_base + (i << 16) + GPIO_DR); + } +} + +static void imx7_ccm_save(void) +{ + u32 i; + + for (i = 0; i < MAX_CCM_LPCG; i++) + ccm_lpcg[i] = readl_relaxed(pm_info->ccm_base.vbase + + i * CCM_LPCG_STEP + CCM_LPCG_START); + pfd_a = readl_relaxed(pm_info->anatop_base.vbase + PFD_A_OFFSET); + pfd_b = readl_relaxed(pm_info->anatop_base.vbase + PFD_B_OFFSET); + + pll[0] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_ARM_OFFSET); + pll[1] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_OFFSET); + pll[2] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_SS_OFFSET); + pll[3] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_NUM_OFFSET); + pll[4] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_DDR_DENOM_OFFSET); + pll[5] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_480_OFFSET); + pll[6] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_ENET_OFFSET); + pll[7] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + pll[8] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_SS_OFFSET); + pll[9] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_NUM_OFFSET); + pll[10] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_AUDIO_DENOM_OFFSET); + pll[11] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + pll[12] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_SS_OFFSET); + pll[13] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_NUM_OFFSET); + pll[14] = readl_relaxed(pm_info->anatop_base.vbase + + PLL_VIDEO_DENOM_OFFSET); + + /* enable all PLLs/PFDs for saving CCM root */ + writel_relaxed(0x1c000070, pm_info->anatop_base.vbase + + PLL_480_OFFSET + 0x8); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_A_OFFSET + 0x8); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_B_OFFSET + 0x8); + writel_relaxed(0x1fc0, pm_info->anatop_base.vbase + + PLL_ENET_OFFSET + 0x4); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + + for (i = 0; i < sizeof(ccm_root) / 8; i++) + ccm_root[i][1] = readl_relaxed( + pm_info->ccm_base.vbase + ccm_root[i][0]); +} + +static void imx7_ccm_restore(void) +{ + u32 i, val; + + /* enable all PLLs/PFDs for restoring CCM root */ + writel_relaxed(0x1c000070, pm_info->anatop_base.vbase + + PLL_480_OFFSET + REG_CLR); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_A_OFFSET + REG_CLR); + writel_relaxed(0x80808080, pm_info->anatop_base.vbase + + PFD_B_OFFSET + REG_CLR); + writel_relaxed(0x1fc0, pm_info->anatop_base.vbase + + PLL_ENET_OFFSET + REG_SET); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + writel_relaxed(0x12000, pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + + for (i = 0; i < sizeof(ccm_root) / 8; i++) { + val = readl_relaxed(pm_info->ccm_base.vbase + ccm_root[i][0]); + /* restore post podf */ + val &= ~BM_CCM_ROOT_POST_PODF; + val |= ccm_root[i][1] & BM_CCM_ROOT_POST_PODF; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + /* resotre pre podf */ + val &= ~BM_CCM_ROOT_PRE_PODF; + val |= ccm_root[i][1] & BM_CCM_ROOT_PRE_PODF; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + /* restore mux */ + val &= ~BM_CCM_ROOT_MUX; + val |= ccm_root[i][1] & BM_CCM_ROOT_MUX; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + /* restore enable */ + val &= ~BM_CCM_ROOT_ENABLE; + val |= ccm_root[i][1] & BM_CCM_ROOT_ENABLE; + writel_relaxed(val, pm_info->ccm_base.vbase + ccm_root[i][0]); + } + + /* restore PLLs */ + writel_relaxed(pll[0], pm_info->anatop_base.vbase + + PLL_ARM_OFFSET); + writel_relaxed(pll[1], pm_info->anatop_base.vbase + + PLL_DDR_OFFSET); + writel_relaxed(pll[2], pm_info->anatop_base.vbase + + PLL_DDR_SS_OFFSET); + writel_relaxed(pll[3], pm_info->anatop_base.vbase + + PLL_DDR_NUM_OFFSET); + writel_relaxed(pll[4], pm_info->anatop_base.vbase + + PLL_DDR_DENOM_OFFSET); + writel_relaxed(pll[5], pm_info->anatop_base.vbase + + PLL_480_OFFSET); + writel_relaxed(pll[6], pm_info->anatop_base.vbase + + PLL_ENET_OFFSET); + writel_relaxed(pll[7], pm_info->anatop_base.vbase + + PLL_AUDIO_OFFSET); + writel_relaxed(pll[8], pm_info->anatop_base.vbase + + PLL_AUDIO_SS_OFFSET); + writel_relaxed(pll[9], pm_info->anatop_base.vbase + + PLL_AUDIO_NUM_OFFSET); + writel_relaxed(pll[10], pm_info->anatop_base.vbase + + PLL_AUDIO_DENOM_OFFSET); + writel_relaxed(pll[11], pm_info->anatop_base.vbase + + PLL_VIDEO_OFFSET); + writel_relaxed(pll[12], pm_info->anatop_base.vbase + + PLL_VIDEO_SS_OFFSET); + writel_relaxed(pll[13], pm_info->anatop_base.vbase + + PLL_VIDEO_NUM_OFFSET); + writel_relaxed(pll[14], pm_info->anatop_base.vbase + + PLL_VIDEO_DENOM_OFFSET); + + for (i = 0; i < MAX_CCM_LPCG; i++) + writel_relaxed(ccm_lpcg[i], pm_info->ccm_base.vbase + + i * CCM_LPCG_STEP + CCM_LPCG_START); + /* restore PFDs */ + writel_relaxed(pfd_a & 0x80808080, + pm_info->anatop_base.vbase + PFD_A_OFFSET + REG_SET); + writel_relaxed(pfd_a, pm_info->anatop_base.vbase + PFD_A_OFFSET); + + writel_relaxed(pfd_b & 0x80808080, + pm_info->anatop_base.vbase + PFD_B_OFFSET + REG_SET); + writel_relaxed(pfd_b, pm_info->anatop_base.vbase + PFD_B_OFFSET); +} + +static void imx7_sys_counter_save(void) +{ + sys_ctrl_reg = readl_relaxed(system_counter_ctrl_base); + sys_cmp_reg = readl_relaxed(system_counter_cmp_base); +} + +static void imx7_sys_counter_restore(void) +{ + writel_relaxed(sys_ctrl_reg, system_counter_ctrl_base); + writel_relaxed(sys_cmp_reg, system_counter_cmp_base); +} + +static void imx7_gpt_save(void) +{ + gpt1_regs[0] = readl_relaxed(gpt1_base + GPT_CR); + gpt1_regs[1] = readl_relaxed(gpt1_base + GPT_PR); + gpt1_regs[2] = readl_relaxed(gpt1_base + GPT_IR); +} + +static void imx7_gpt_restore(void) +{ + writel_relaxed(gpt1_regs[0], gpt1_base + GPT_CR); + writel_relaxed(gpt1_regs[1], gpt1_base + GPT_PR); + writel_relaxed(gpt1_regs[2], gpt1_base + GPT_IR); +} + +static void imx7_iomuxc_gpr_save(void) +{ + u32 i; + + for (i = 0; i < MAX_IOMUXC_GPR; i++) + iomuxc_gpr[i] = readl_relaxed( + pm_info->iomuxc_gpr_base.vbase + i * 4); +} + +static void imx7_iomuxc_gpr_restore(void) +{ + u32 i; + + for (i = 0; i < MAX_IOMUXC_GPR; i++) + writel_relaxed(iomuxc_gpr[i], + pm_info->iomuxc_gpr_base.vbase + i * 4); +} + +static void imx7_console_save(unsigned int *regs) +{ + if (!console_base) + return; + + regs[0] = readl_relaxed(console_base + UART_UCR1); + regs[1] = readl_relaxed(console_base + UART_UCR2); + regs[2] = readl_relaxed(console_base + UART_UCR3); + regs[3] = readl_relaxed(console_base + UART_UCR4); + regs[4] = readl_relaxed(console_base + UART_UFCR); + regs[5] = readl_relaxed(console_base + UART_UESC); + regs[6] = readl_relaxed(console_base + UART_UTIM); + regs[7] = readl_relaxed(console_base + UART_UBIR); + regs[8] = readl_relaxed(console_base + UART_UBMR); + regs[9] = readl_relaxed(console_base + UART_UTS); +} + +static void imx7_console_io_save(void) +{ + /* save uart1 io, driver resume is too late */ + uart1_io[0] = readl_relaxed(iomuxc_base + UART_RX_IO); + uart1_io[1] = readl_relaxed(iomuxc_base + UART_RX_PAD); + uart1_io[2] = readl_relaxed(iomuxc_base + UART_TX_IO); + uart1_io[3] = readl_relaxed(iomuxc_base + UART_TX_PAD); +} + +static void imx7_console_restore(unsigned int *regs) +{ + if (!console_base) + return; + + writel_relaxed(regs[4], console_base + UART_UFCR); + writel_relaxed(regs[5], console_base + UART_UESC); + writel_relaxed(regs[6], console_base + UART_UTIM); + writel_relaxed(regs[7], console_base + UART_UBIR); + writel_relaxed(regs[8], console_base + UART_UBMR); + writel_relaxed(regs[9], console_base + UART_UTS); + writel_relaxed(regs[0], console_base + UART_UCR1); + writel_relaxed(regs[1] | 0x1, console_base + UART_UCR2); + writel_relaxed(regs[2], console_base + UART_UCR3); + writel_relaxed(regs[3], console_base + UART_UCR4); +} + +static void imx7_console_io_restore(void) +{ + /* restore uart1 io */ + writel_relaxed(uart1_io[0], iomuxc_base + UART_RX_IO); + writel_relaxed(uart1_io[1], iomuxc_base + UART_RX_PAD); + writel_relaxed(uart1_io[2], iomuxc_base + UART_TX_IO); + writel_relaxed(uart1_io[3], iomuxc_base + UART_TX_PAD); +} + +#define MX7D_SUSPEND_POWERDWN_PARAM \ + ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +#define MX7D_SUSPEND_STANDBY_PARAM \ + ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_STANDBY << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +static int imx7_suspend_finish(unsigned long val) +{ + u32 state; + + if (val == 0) + state = MX7D_SUSPEND_POWERDWN_PARAM; + else + state = MX7D_SUSPEND_STANDBY_PARAM; + + if (psci_ops.cpu_suspend) { + return psci_ops.cpu_suspend(state, __pa(cpu_resume)); + } + + if (!imx7_suspend_in_ocram_fn) { + cpu_do_idle(); + } else { + /* + * call low level suspend function in ocram, + * as we need to float DDR IO. + */ + local_flush_tlb_all(); + imx7_suspend_in_ocram_fn(suspend_ocram_base); + } + + return 0; +} + +static void imx7_pm_set_lpsr_resume_addr(unsigned long addr) +{ + writel_relaxed(addr, pm_info->lpsr_base.vbase); +} + +static int imx7_pm_is_resume_from_lpsr(void) +{ + return readl_relaxed(lpsr_base); +} + +static int imx7_pm_enter(suspend_state_t state) +{ + unsigned int console_saved_reg[10] = {0}; + u32 val; + + if (!iram_tlb_base_addr) { + pr_warn("No IRAM/OCRAM memory allocated for suspend/resume \ + code. Please ensure device tree has an entry for \ + fsl,lpm-sram.\n"); + return -EINVAL; + } + + /* + * arm_arch_timer driver requires system counter to be + * a clock source with CLOCK_SOURCE_SUSPEND_NONSTOP flag + * set, which means hardware system counter needs to keep + * running during suspend, as the base clock for system + * counter is 24MHz which will be disabled in STOP mode, + * so we need to switch system counter's clock to alternate + * (lower) clock, it is based on 32K, from block guide, there + * is no special flow needs to be followed, system counter + * hardware will handle the clock transition. + */ + val = readl_relaxed(system_counter_ctrl_base); + val &= ~BM_SYS_COUNTER_CNTCR_FCR0; + val |= BM_SYS_COUNTER_CNTCR_FCR1; + writel_relaxed(val, system_counter_ctrl_base); + while (!(readl_relaxed(system_counter_ctrl_base + SYS_COUNTER_CNTSR) + & BM_SYS_COUNTER_CNTSR_FCR1)) + ; + + switch (state) { + case PM_SUSPEND_STANDBY: + imx_anatop_pre_suspend(); + imx_gpcv2_pre_suspend(false); + + /* Zzz ... */ + if (psci_ops.cpu_suspend) + cpu_suspend(1, imx7_suspend_finish); + else + imx7_suspend_in_ocram_fn(suspend_ocram_base); + + imx_anatop_post_resume(); + imx_gpcv2_post_resume(); + break; + case PM_SUSPEND_MEM: + imx_anatop_pre_suspend(); + imx_gpcv2_pre_suspend(true); + if (imx_gpcv2_is_mf_mix_off()) { + /* + * per design requirement, EXSC for PCIe/EIM/PXP + * will need clock to recover RDC setting on + * resume, so enable PCIe/EIM LPCG for RDC + * recovery when M/F mix off + */ + writel_relaxed(0x3, pm_info->ccm_base.vbase + + CCM_EIM_LPCG); + writel_relaxed(0x3, pm_info->ccm_base.vbase + + CCM_PXP_LPCG); + writel_relaxed(0x3, pm_info->ccm_base.vbase + + CCM_PCIE_LPCG); + /* stop m4 if mix will also be shutdown */ + if (imx_src_is_m4_enabled() && imx_mu_is_m4_in_stop()) { + writel(M4_RCR_HALT, + pm_info->src_base.vbase + M4RCR); + imx_gpcv2_enable_wakeup_for_m4(); + } + imx7_console_save(console_saved_reg); + memcpy(ocram_saved_in_ddr, ocram_base, ocram_size); + if (lpsr_enabled) { + imx7_pm_set_lpsr_resume_addr(pm_info->resume_addr); + imx7_console_io_save(); + memcpy(lpm_ocram_saved_in_ddr, lpm_ocram_base, + lpm_ocram_size); + imx7_iomuxc_gpr_save(); + imx7_ccm_save(); + imx7_gpt_save(); + imx7_sys_counter_save(); + imx7_gpio_save(); + } + } + + /* Zzz ... */ + cpu_suspend(0, imx7_suspend_finish); + + if (imx7_pm_is_resume_from_lpsr()) { + imx7_console_io_restore(); + memcpy(lpm_ocram_base, lpm_ocram_saved_in_ddr, + lpm_ocram_size); + imx7_iomuxc_gpr_restore(); + imx7_ccm_restore(); + imx7_gpt_restore(); + imx7_sys_counter_restore(); + imx7_gpio_restore(); + imx7d_enable_rcosc(); + } + if (imx_gpcv2_is_mf_mix_off() || + imx7_pm_is_resume_from_lpsr()) { + writel_relaxed(0x0, pm_info->ccm_base.vbase + + CCM_EIM_LPCG); + writel_relaxed(0x0, pm_info->ccm_base.vbase + + CCM_PXP_LPCG); + writel_relaxed(0x0, pm_info->ccm_base.vbase + + CCM_PCIE_LPCG); + memcpy(ocram_base, ocram_saved_in_ddr, ocram_size); + imx7_console_restore(console_saved_reg); + if (imx_src_is_m4_enabled() && imx_mu_is_m4_in_stop()) { + imx_gpcv2_disable_wakeup_for_m4(); + /* restore M4 image */ + memcpy(lpm_m4tcm_base, + lpm_m4tcm_saved_in_ddr, SZ_32K); + /* kick m4 to enable */ + writel(M4_RCR_GO, + pm_info->src_base.vbase + M4RCR); + /* offset high bus count for m4 image */ + request_bus_freq(BUS_FREQ_HIGH); + /* restore M4 to run mode */ + imx_mu_set_m4_run_mode(); + /* gpc wakeup */ + } + } + /* clear LPSR resume address */ + imx7_pm_set_lpsr_resume_addr(0); + imx_anatop_post_resume(); + imx_gpcv2_post_resume(); + break; + default: + return -EINVAL; + } + + /* restore system counter's clock to base clock */ + val = readl_relaxed(system_counter_ctrl_base); + val &= ~BM_SYS_COUNTER_CNTCR_FCR1; + val |= BM_SYS_COUNTER_CNTCR_FCR0; + writel_relaxed(val, system_counter_ctrl_base); + while (!(readl_relaxed(system_counter_ctrl_base + SYS_COUNTER_CNTSR) + & BM_SYS_COUNTER_CNTSR_FCR0)) + ; + + return 0; +} + +static int imx7_pm_valid(suspend_state_t state) +{ + return state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM; +} + +static const struct platform_suspend_ops imx7_pm_ops = { + .enter = imx7_pm_enter, + .valid = imx7_pm_valid, +}; + +void __init imx7_pm_set_ccm_base(void __iomem *base) +{ + ccm_base = base; +} + +static struct map_desc iram_tlb_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +static int __init imx7_dt_find_lpsram(unsigned long node, const char *uname, + int depth, void *data) +{ + unsigned long lpram_addr; + const __be32 *prop = of_get_flat_dt_prop(node, "reg", NULL); + + if (of_flat_dt_is_compatible(node, "fsl,lpm-sram")) { + if (!prop) + return -EINVAL; + + lpram_addr = be32_to_cpup(prop); + + /* We need to create a 1M page table entry. */ + iram_tlb_io_desc.virtual = IMX_IO_P2V(lpram_addr & 0xFFF00000); + iram_tlb_io_desc.pfn = __phys_to_pfn(lpram_addr & 0xFFF00000); + iram_tlb_phys_addr = lpram_addr; + iram_tlb_base_addr = IMX_IO_P2V(lpram_addr); + iotable_init(&iram_tlb_io_desc, 1); + } + + return 0; +} + +void __init imx7_pm_map_io(void) +{ + unsigned long i, j; + + iotable_init(imx7_pm_io_desc, ARRAY_SIZE(imx7_pm_io_desc)); + /* + * Get the address of IRAM or OCRAM to be used by the low + * power code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx7_dt_find_lpsram, NULL)); + + /* Return if no IRAM space is allocated for suspend/resume code. */ + if (!iram_tlb_base_addr) { + pr_warn("No valid ocram available for suspend/resume!\n"); + return; + } + + /* TODO: Handle M4 in TEE? */ + /* Set all entries to 0 except first 3 words reserved for M4. */ + memset((void *)(iram_tlb_base_addr + M4_OCRAMS_RESERVED_SIZE), + 0, MX7_IRAM_TLB_SIZE - M4_OCRAMS_RESERVED_SIZE); + + /* + * Make sure the IRAM virtual address has a mapping in the IRAM + * page table. + * + * Only use the top 12 bits [31-20] when storing the physical + * address in the page table as only these bits are required + * for 1M mapping. + */ + j = ((iram_tlb_base_addr >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + (iram_tlb_phys_addr & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; + + /* + * Make sure the AIPS1 virtual address has a mapping in the + * IRAM page table. + */ + for (i = 0; i < 4; i++) { + j = ((IMX_IO_P2V(MX7D_AIPS1_BASE_ADDR + i * 0x100000) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7D_AIPS1_BASE_ADDR + i * 0x100000) & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + /* + * Make sure the AIPS2 virtual address has a mapping in the + * IRAM page table. + */ + for (i = 0; i < 4; i++) { + j = ((IMX_IO_P2V(MX7D_AIPS2_BASE_ADDR + i * 0x100000) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7D_AIPS2_BASE_ADDR + i * 0x100000) & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + /* + * Make sure the AIPS3 virtual address has a mapping + * in the IRAM page table. + */ + for (i = 0; i < 4; i++) { + j = ((IMX_IO_P2V(MX7D_AIPS3_BASE_ADDR + i * 0x100000) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7D_AIPS3_BASE_ADDR + i * 0x100000) & 0xFFF00000) | + TT_ATTRIB_NON_CACHEABLE_1M; + } + + /* + * Make sure the GIC virtual address has a mapping in the + * IRAM page table. + */ + j = ((IMX_IO_P2V(MX7D_GIC_BASE_ADDR) >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + (MX7D_GIC_BASE_ADDR & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M; +} + +static int __init imx7_suspend_init(const struct imx7_pm_socdata *socdata) +{ + const u32 (*ddrc_offset_array)[2]; + const u32 (*ddrc_phy_offset_array)[2]; + unsigned long iram_paddr; + int i; + + suspend_set_ops(&imx7_pm_ops); + + if (!socdata) { + pr_warn("%s: invalid argument!\n", __func__); + return -EINVAL; + } + + /* + * 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB, + * The lower 8K is not used, so use the lower 8K for IRAM code and + * pm_info. + * + */ + iram_paddr = iram_tlb_phys_addr + MX7_SUSPEND_IRAM_ADDR_OFFSET; + + /* Make sure iram_paddr is 8 byte aligned. */ + if ((uintptr_t)(iram_paddr) & (FNCPY_ALIGN - 1)) + iram_paddr += FNCPY_ALIGN - iram_paddr % (FNCPY_ALIGN); + + /* Get the virtual address of the suspend code. */ + suspend_ocram_base = (void *)IMX_IO_P2V(iram_paddr); + + if (psci_ops.cpu_suspend) { + pm_info = kmalloc(sizeof(*pm_info), GFP_KERNEL); + if (!pm_info) + return -ENOMEM; + } else { + pm_info = suspend_ocram_base; + } + /* pbase points to iram_paddr. */ + pm_info->pbase = iram_paddr; + pm_info->resume_addr = virt_to_phys(ca7_cpu_resume); + pm_info->pm_info_size = sizeof(*pm_info); + + /* + * ccm physical address is not used by asm code currently, + * so get ccm virtual address directly, as we already have + * it from ccm driver. + */ + pm_info->ccm_base.pbase = MX7D_CCM_BASE_ADDR; + pm_info->ccm_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_CCM_BASE_ADDR); + + pm_info->ddrc_base.pbase = MX7D_DDRC_BASE_ADDR; + pm_info->ddrc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_DDRC_BASE_ADDR); + + pm_info->ddrc_phy_base.pbase = MX7D_DDRC_PHY_BASE_ADDR; + pm_info->ddrc_phy_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_DDRC_PHY_BASE_ADDR); + + pm_info->src_base.pbase = MX7D_SRC_BASE_ADDR; + pm_info->src_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_SRC_BASE_ADDR); + + pm_info->iomuxc_gpr_base.pbase = MX7D_IOMUXC_GPR_BASE_ADDR; + pm_info->iomuxc_gpr_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR); + + pm_info->gpc_base.pbase = MX7D_GPC_BASE_ADDR; + pm_info->gpc_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_GPC_BASE_ADDR); + + pm_info->anatop_base.pbase = MX7D_ANATOP_BASE_ADDR; + pm_info->anatop_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR); + + pm_info->snvs_base.pbase = MX7D_SNVS_BASE_ADDR; + pm_info->snvs_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_SNVS_BASE_ADDR); + + pm_info->lpsr_base.pbase = MX7D_LPSR_BASE_ADDR; + lpsr_base = pm_info->lpsr_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_LPSR_BASE_ADDR); + + pm_info->gic_base.pbase = MX7D_GIC_BASE_ADDR; + pm_info->gic_base.vbase = (void __iomem *) + IMX_IO_P2V(MX7D_GIC_BASE_ADDR); + + pm_info->ddrc_num = socdata->ddrc_num; + ddrc_offset_array = socdata->ddrc_offset; + pm_info->ddrc_phy_num = socdata->ddrc_phy_num; + ddrc_phy_offset_array = socdata->ddrc_phy_offset; + + /* initialize DDRC settings */ + for (i = 0; i < pm_info->ddrc_num; i++) { + pm_info->ddrc_val[i][0] = ddrc_offset_array[i][0]; + if (ddrc_offset_array[i][1] == READ_DATA_FROM_HARDWARE) + pm_info->ddrc_val[i][1] = + readl_relaxed(pm_info->ddrc_base.vbase + + ddrc_offset_array[i][0]); + else + pm_info->ddrc_val[i][1] = ddrc_offset_array[i][1]; + + if (pm_info->ddrc_val[i][0] == 0xd0) + pm_info->ddrc_val[i][1] |= 0xc0000000; + } + + /* initialize DDRC PHY settings */ + for (i = 0; i < pm_info->ddrc_phy_num; i++) { + pm_info->ddrc_phy_val[i][0] = + ddrc_phy_offset_array[i][0]; + if (ddrc_phy_offset_array[i][1] == READ_DATA_FROM_HARDWARE) + pm_info->ddrc_phy_val[i][1] = + readl_relaxed(pm_info->ddrc_phy_base.vbase + + ddrc_phy_offset_array[i][0]); + else + pm_info->ddrc_phy_val[i][1] = + ddrc_phy_offset_array[i][1]; + } + + if (psci_ops.cpu_suspend) + return 0; + + imx7_suspend_in_ocram_fn = fncpy( + suspend_ocram_base + sizeof(*pm_info), + &imx7_suspend, + MX7_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); + + return 0; +} + +static void __init imx7_pm_common_init(const struct imx7_pm_socdata + *socdata) +{ + int ret; + struct regmap *gpr; + + if (IS_ENABLED(CONFIG_SUSPEND)) { + ret = imx7_suspend_init(socdata); + if (ret) + pr_warn("%s: No DDR LPM support with suspend %d!\n", + __func__, ret); + } + + /* + * Force IOMUXC irq pending, so that the interrupt to GPC can be + * used to deassert dsm_request signal when the signal gets + * asserted unexpectedly. + */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_IRQ_MASK, + IMX7D_GPR1_IRQ_MASK); +} + +void __init imx7d_pm_init(void) +{ + struct device_node *np; + struct resource res; + if (imx_src_is_m4_enabled()) { + /* map the 32K of M4 TCM */ + np = of_find_node_by_path( + "/tcml@7f8000"); + if (np) + lpm_m4tcm_base = of_iomap(np, 0); + WARN_ON(!lpm_m4tcm_base); + + /* map the m4 bootrom from dtb */ + np = of_find_node_by_path( + "/soc/sram@180000"); + if (np) + m4_bootrom_base = of_iomap(np, 0); + WARN_ON(!m4_bootrom_base); + + lpm_m4tcm_saved_in_ddr = kzalloc(SZ_32K, GFP_KERNEL); + WARN_ON(!lpm_m4tcm_saved_in_ddr); + + /* save M4 Image to DDR */ + memcpy(lpm_m4tcm_saved_in_ddr, lpm_m4tcm_base, SZ_32K); + } + np = of_find_compatible_node(NULL, NULL, "fsl,lpm-sram"); + if (of_get_property(np, "fsl,enable-lpsr", NULL)) + lpsr_enabled = true; + + if (psci_ops.cpu_suspend) + lpsr_enabled = false; + + if (lpsr_enabled) { + pr_info("LPSR mode enabled, DSM will go into LPSR mode!\n"); + lpm_ocram_base = of_iomap(np, 0); + WARN_ON(!lpm_ocram_base); + WARN_ON(of_address_to_resource(np, 0, &res)); + lpm_ocram_size = resource_size(&res); + lpm_ocram_saved_in_ddr = kzalloc(lpm_ocram_size, GFP_KERNEL); + WARN_ON(!lpm_ocram_saved_in_ddr); + + np = of_find_node_by_path( + "/soc/bus@30000000/pinctrl@30330000"); + if (np) + iomuxc_base = of_iomap(np, 0); + WARN_ON(!iomuxc_base); + + np = of_find_node_by_path( + "/soc/bus@30000000/timer@302d0000"); + if (np) + gpt1_base = of_iomap(np, 0); + WARN_ON(!gpt1_base); + + np = of_find_node_by_path( + "/soc/bus@30400000/system-counter-cmp@306b0000"); + if (np) + system_counter_cmp_base = of_iomap(np, 0); + WARN_ON(!system_counter_cmp_base); + + np = of_find_node_by_path( + "/soc/bus@30000000/gpio@30200000"); + if (np) + gpio1_base = of_iomap(np, 0); + WARN_ON(!gpio1_base); + } + + np = of_find_node_by_path( + "/soc/bus@30400000/system-counter-ctrl@306c0000"); + if (np) + system_counter_ctrl_base = of_iomap(np, 0); + WARN_ON(!system_counter_ctrl_base); + + if (imx_ddrc_get_ddr_type() == IMX_DDR_TYPE_LPDDR3 + || imx_ddrc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx7_pm_common_init(&imx7d_pm_data_lpddr3); + else if (imx_ddrc_get_ddr_type() == IMX_DDR_TYPE_DDR3) + imx7_pm_common_init(&imx7d_pm_data_ddr3); + + np = of_find_compatible_node(NULL, NULL, "fsl,mega-fast-sram"); + ocram_base = of_iomap(np, 0); + WARN_ON(!ocram_base); + WARN_ON(of_address_to_resource(np, 0, &res)); + ocram_size = resource_size(&res); + ocram_saved_in_ddr = kzalloc(ocram_size, GFP_KERNEL); + WARN_ON(!ocram_saved_in_ddr); + + np = of_find_node_by_path( + "/soc/bus@30800000/spba-bus@30800000/serial@30860000"); + if (np) + console_base = of_iomap(np, 0); + + /* clear LPSR resume address first */ + imx7_pm_set_lpsr_resume_addr(0); +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/pm-imx7ulp.c linux-imx-phytec/arch/arm/mach-imx/pm-imx7ulp.c --- linux-6.1.55/arch/arm/mach-imx/pm-imx7ulp.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/pm-imx7ulp.c 2024-06-19 12:33:58.132189693 +0200 @@ -5,65 +5,888 @@ * Author: Dong Aisheng */ +#include +#include +#include #include +#include +#include +#include +#include #include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include #include "common.h" +#include "hardware.h" + +#define MU_SR 0x60 + +#define PMPROT 0x8 +#define PMCTRL 0x10 +#define PMSTAT 0x18 +#define SRS 0x20 +#define RPC 0x24 +#define SSRS 0x28 +#define SRIE 0x2c +#define SRIF 0x30 +#define CSRE 0x34 +#define MR 0x40 + +#define PMC1_HSRUN 0x4 +#define PMC1_RUN 0x8 +#define PMC1_VLPR 0xc +#define PMC1_STOP 0x10 +#define PMC1_VLPS 0x14 +#define PMC1_LLS 0x18 +#define PMC1_VLLS 0x1c +#define PMC1_STATUS 0x20 +#define PMC1_CTRL 0x24 +#define PMC0_CTRL 0x28 + +#define BM_PMPROT_AHSRUN (1 << 7) +#define BM_PMPROT_AVLP (1 << 5) +#define BM_PMPROT_ALLS (1 << 3) +#define BM_PMPROT_AVLLS (1 << 1) + +#define BM_PMCTRL_STOPA (1 << 24) +#define BM_PMCTRL_PSTOPO (3 << 16) +#define BM_PMCTRL_RUNM (3 << 8) +#define BM_PMCTRL_STOPM (7 << 0) + +#define BM_VLPS_RBBEN (1 << 28) + +#define BM_CTRL_LDOEN (1 << 31) +#define BM_CTRL_LDOOKDIS (1 << 30) + +#define BM_VLLS_MON1P2HVDHP (1 << 5) +#define BM_VLLS_MON1P2LVDHP (1 << 4) -#define SMC_PMCTRL 0x10 -#define BP_PMCTRL_PSTOPO 16 -#define PSTOPO_PSTOP3 0x3 -#define PSTOPO_PSTOP2 0x2 -#define PSTOPO_PSTOP1 0x1 -#define BP_PMCTRL_RUNM 8 -#define RUNM_RUN 0 #define BP_PMCTRL_STOPM 0 -#define STOPM_STOP 0 +#define BP_PMCTRL_PSTOPO 16 -#define BM_PMCTRL_PSTOPO (3 << BP_PMCTRL_PSTOPO) -#define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM) -#define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM) +#define MX7ULP_MAX_MMDC_IO_NUM 64 +#define MX7ULP_MAX_MMDC_NUM 50 +#define MX7ULP_MAX_IOMUX_NUM 116 +#define MX7ULP_MAX_SELECT_INPUT_NUM 78 + +#define IOMUX_START 0x0 +#define SELECT_INPUT_START 0x200 + +#define TPM_SC 0x10 +#define TPM_MOD 0x18 +#define TPM_C0SC 0x20 +#define TPM_C0V 0x24 + +#define PCC2_ENABLE_PCS_FIRC ((1 << 30) | (3 << 24)) +#define PCC2_ENABLE (1 << 30) + +#define LPUART_BAUD 0x10 +#define LPUART_CTRL 0x18 +#define LPUART_FIFO 0x28 +#define LPUART_WATER 0x2c + +#define GPIO_PDOR 0x0 +#define GPIO_PDDR 0x14 + +#define PTC2_LPUART4_TX_OFFSET 0x8 +#define PTC3_LPUART4_RX_OFFSET 0xc +#define PTC2_LPUART4_TX_INPUT_OFFSET 0x248 +#define PTC3_LPUART4_RX_INPUT_OFFSET 0x24c +#define LPUART4_MUX_VALUE (4 << 8) +#define LPUART4_INPUT_VALUE (1) + +#define MU_B_SR_NMIC (1 << 3) + +#define DGO_GPR3 0x60 +#define DGO_GPR4 0x64 + +#define ADDR_1M_MASK 0xFFF00000 + +#define WDOG_CS 0x0 +#define WDOG_CS_CMD32EN BIT(13) +#define WDOG_CNT 0x4 +#define REFRESH_SEQ0 0xA602 +#define REFRESH_SEQ1 0xB480 +#define REFRESH ((REFRESH_SEQ1 << 16) | REFRESH_SEQ0) + +#define WDOG_CS_EN BIT(7) +#define WDOG_TOVAL 0x8 +#define WDOG_CS_ULK BIT(11) +#define WDOG_CS_RCS BIT(10) +#define WDOG_CS_UPDATE BIT(5) +#define WDOG_CS_WAIT BIT(1) +#define WDOG_CS_STOP BIT(0) static void __iomem *smc1_base; +static void __iomem *pmc0_base; +static void __iomem *pmc1_base; +static void __iomem *tpm5_base; +static void __iomem *lpuart4_base; +static void __iomem *iomuxc1_base; +static void __iomem *pcc2_base; +static void __iomem *pcc3_base; +static void __iomem *mu_base; +static void __iomem *scg1_base; +static void __iomem *wdog1_base; +static void __iomem *gpio_base[4]; +static void __iomem *port_pcr_base[4]; +static void __iomem *suspend_ocram_base; +static void (*imx7ulp_suspend_in_ocram_fn)(void __iomem *sram_base); + +static u32 port_pcr[4][20]; +static u32 port_num[4] = {20, 12, 16, 20}; +static u32 tpm5_regs[4]; +static u32 lpuart4_regs[4]; +static u32 pcc2_regs[24][2] = { + {0x20, 0}, {0x3c, 0}, {0x40, 0}, {0x6c, 0}, + {0x84, 0}, {0x90, 0}, {0x94, 0}, {0x98, 0}, + {0x9c, 0}, {0xa4, 0}, {0xa8, 0}, {0xac, 0}, + {0xb0, 0}, {0xb4, 0}, {0xb8, 0}, {0xc4, 0}, + {0xcc, 0}, {0xd0, 0}, {0xd4, 0}, {0xd8, 0}, + {0xdc, 0}, {0xe0, 0}, {0xf4, 0}, {0x10c, 0}, +}; + +static u32 pcc3_regs[16][2] = { + {0x84, 0}, {0x88, 0}, {0x90, 0}, {0x94, 0}, + {0x98, 0}, {0x9c, 0}, {0xa0, 0}, {0xa4, 0}, + {0xa8, 0}, {0xac, 0}, {0xb8, 0}, {0xbc, 0}, + {0xc0, 0}, {0xc4, 0}, {0x140, 0}, {0x144, 0}, +}; + +static u32 scg1_offset[17] = { + 0x14, 0x30, 0x40, 0x304, + 0x500, 0x504, 0x508, 0x50c, + 0x510, 0x514, 0x600, 0x604, + 0x608, 0x60c, 0x610, 0x614, + 0x104, +}; + +extern unsigned long iram_tlb_base_addr; +extern unsigned long iram_tlb_phys_addr; + +/* + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7ulp_suspend code + * PM_INFO structure(imx7ulp_cpu_pm_info) + * ======================== low address ======================= + */ +struct imx7ulp_pm_socdata { + u32 ddr_type; + const char *mmdc_compat; + const u32 mmdc_io_num; + const u32 *mmdc_io_offset; + const u32 mmdc_num; + const u32 *mmdc_offset; +}; + +static const u32 imx7ulp_mmdc_io_lpddr3_offset[] __initconst = { + 0x0, 0x4, 0x8, 0xc, + 0x10, 0x14, 0x18, 0x1c, + 0x20, 0x24, 0x28, 0x2c, + 0x30, 0x34, 0x38, 0x3c, + 0x40, 0x44, 0x48, 0x4c, + 0x50, 0x54, 0x58, 0x5c, + 0x60, 0x64, 0x68, 0x6c, + 0x70, 0x74, 0x78, 0x7c, + 0x80, 0x84, 0x88, 0x8c, + 0x90, 0x94, 0x98, 0x9c, + 0xa0, 0xa4, 0xa8, 0xac, + 0xb0, 0xb4, 0xb8, 0xbc, + 0xc0, 0xc4, 0xc8, 0xcc, + 0xd0, 0xd4, 0xd8, 0xdc, + 0xe8, 0xf8, 0xfc, 0x120, + 0x124, +}; + +static const u32 imx7ulp_mmdc_lpddr3_offset[] __initconst = { + 0x01c, 0x800, 0x85c, 0x890, + 0x848, 0x850, 0x81c, 0x820, + 0x824, 0x828, 0x82c, 0x830, + 0x834, 0x838, 0x8c0, 0x8b8, + 0x004, 0x00c, 0x010, 0x038, + 0x014, 0x018, 0x02c, 0x030, + 0x040, 0x000, 0x01c, 0x01c, + 0x01c, 0x01c, 0x01c, 0x01c, + 0x01c, 0x01c, 0x01c, 0x01c, + 0x01c, 0x01c, 0x83c, 0x020, + 0x800, 0x004, 0x404, 0x01c, +}; + +static const u32 imx7ulp_lpddr3_script[] __initconst = { + 0x00008000, 0xA1390003, 0x0D3900A0, 0x00400000, + 0x40404040, 0x40404040, 0x33333333, 0x33333333, + 0x33333333, 0x33333333, 0xf3333333, 0xf3333333, + 0xf3333333, 0xf3333333, 0x24922492, 0x00000800, + 0x00020052, 0x292C42F3, 0x00100A22, 0x00120556, + 0x00C700DB, 0x00211718, 0x0F9F26D2, 0x009F0E10, + 0x0000003F, 0xC3190000, 0x00008050, 0x00008058, + 0x003F8030, 0x003F8038, 0xFF0A8030, 0xFF0A8038, + 0x04028030, 0x04028038, 0x83018030, 0x83018038, + 0x01038030, 0x01038038, 0x20000000, 0x00001800, + 0xA1310000, 0x00020052, 0x00011006, 0x00000000, +}; + +static const struct imx7ulp_pm_socdata imx7ulp_lpddr3_pm_data __initconst = { + .mmdc_compat = "fsl,imx7ulp-mmdc", + .mmdc_io_num = ARRAY_SIZE(imx7ulp_mmdc_io_lpddr3_offset), + .mmdc_io_offset = imx7ulp_mmdc_io_lpddr3_offset, + .mmdc_num = ARRAY_SIZE(imx7ulp_mmdc_lpddr3_offset), + .mmdc_offset = imx7ulp_mmdc_lpddr3_offset, +}; + +/* + * This structure is for passing necessary data for low level ocram + * suspend code(arch/arm/mach-imx/suspend-imx7ulp.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/suspend-imx7ulp.S must be also changed accordingly, + * otherwise, the suspend to sram function will be broken! + */ +struct imx7ulp_cpu_pm_info { + u32 m4_reserve0; + u32 m4_reserve1; + u32 m4_reserve2; + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 pm_info_size; /* Size of pm_info. */ + void __iomem *sim_base; + void __iomem *scg1_base; + void __iomem *mmdc_base; + void __iomem *mmdc_io_base; + void __iomem *smc1_base; + u32 scg1[17]; + u32 ttbr1; /* Store TTBR1 */ + u32 gpio[4][2]; + u32 iomux_num; /* Number of IOs which need saved/restored. */ + u32 iomux_val[MX7ULP_MAX_IOMUX_NUM]; /* To save value */ + u32 select_input_num; /* Number of select input which need saved/restored. */ + u32 select_input_val[MX7ULP_MAX_SELECT_INPUT_NUM]; /* To save value */ + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MX7ULP_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ + u32 mmdc_num; /* Number of MMDC registers which need saved/restored. */ + u32 mmdc_val[MX7ULP_MAX_MMDC_NUM][2]; +} __aligned(8); + +static struct imx7ulp_cpu_pm_info *pm_info; +static void __iomem *aips1_base; +static void __iomem *aips2_base; +static void __iomem *aips3_base; +static void __iomem *aips4_base; +static void __iomem *aips5_base; -int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode) +static void imx7ulp_gpio_save(void) +{ + int i; + + for (i = 0; i < 4; i++) { + pm_info->gpio[i][0] = readl_relaxed(gpio_base[i] + GPIO_PDOR); + pm_info->gpio[i][1] = readl_relaxed(gpio_base[i] + GPIO_PDDR); + } +} + +static void imx7ulp_port_pcr_save(void) +{ + int i; + int j; + for (i = 0; i < 4; i++) + for (j=0; j < port_num[i]; j++) + port_pcr[i][j] = readl_relaxed(port_pcr_base[i] + j * 4); +} + +static void imx7ulp_port_pcr_restore(void) +{ + int i; + int j; + for (i = 0; i < 4; i++) + for (j=0; j < port_num[i]; j++) + writel_relaxed(port_pcr[i][j], port_pcr_base[i] + j * 4); +} + +static void imx7ulp_scg1_save(void) +{ + int i; + + for (i = 0; i < 17; i++) + pm_info->scg1[i] = readl_relaxed(scg1_base + scg1_offset[i]); +} + +static void imx7ulp_pcc3_save(void) +{ + int i; + + for (i = 0; i < 16; i++) + pcc3_regs[i][1] = readl_relaxed(pcc3_base + pcc3_regs[i][0]); +} + +static void imx7ulp_pcc3_restore(void) { - u32 val = readl_relaxed(smc1_base + SMC_PMCTRL); + int i; - /* clear all */ - val &= ~(BM_PMCTRL_RUNM | BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO); + for (i = 0; i < 16; i++) + writel_relaxed(pcc3_regs[i][1], pcc3_base + pcc3_regs[i][0]); +} + +static void imx7ulp_pcc2_save(void) +{ + int i; + + for (i = 0; i < 24; i++) + pcc2_regs[i][1] = readl_relaxed(pcc2_base + pcc2_regs[i][0]); +} + +static void imx7ulp_pcc2_restore(void) +{ + int i; + + for (i = 0; i < 24; i++) + writel_relaxed(pcc2_regs[i][1], pcc2_base + pcc2_regs[i][0]); +} + +static inline void imx7ulp_iomuxc_save(void) +{ + int i; + + pm_info->iomux_num = MX7ULP_MAX_IOMUX_NUM; + pm_info->select_input_num = MX7ULP_MAX_SELECT_INPUT_NUM; + + for (i = 0; i < pm_info->iomux_num; i++) + pm_info->iomux_val[i] = + readl_relaxed(iomuxc1_base + + IOMUX_START + i * 0x4); + for (i = 0; i < pm_info->select_input_num; i++) + pm_info->select_input_val[i] = + readl_relaxed(iomuxc1_base + + SELECT_INPUT_START + i * 0x4); +} + +static void imx7ulp_lpuart_save(void) +{ + lpuart4_regs[0] = readl_relaxed(lpuart4_base + LPUART_BAUD); + lpuart4_regs[1] = readl_relaxed(lpuart4_base + LPUART_FIFO); + lpuart4_regs[2] = readl_relaxed(lpuart4_base + LPUART_WATER); + lpuart4_regs[3] = readl_relaxed(lpuart4_base + LPUART_CTRL); +} + +static void imx7ulp_lpuart_restore(void) +{ + writel_relaxed(LPUART4_MUX_VALUE, + iomuxc1_base + PTC2_LPUART4_TX_OFFSET); + writel_relaxed(LPUART4_MUX_VALUE, + iomuxc1_base + PTC3_LPUART4_RX_OFFSET); + writel_relaxed(LPUART4_INPUT_VALUE, + iomuxc1_base + PTC2_LPUART4_TX_INPUT_OFFSET); + writel_relaxed(LPUART4_INPUT_VALUE, + iomuxc1_base + PTC3_LPUART4_RX_INPUT_OFFSET); + + writel_relaxed(lpuart4_regs[0], lpuart4_base + LPUART_BAUD); + writel_relaxed(lpuart4_regs[1], lpuart4_base + LPUART_FIFO); + writel_relaxed(lpuart4_regs[2], lpuart4_base + LPUART_WATER); + writel_relaxed(lpuart4_regs[3], lpuart4_base + LPUART_CTRL); +} + +static void imx7ulp_tpm_save(void) +{ + tpm5_regs[0] = readl_relaxed(tpm5_base + TPM_SC); + tpm5_regs[1] = readl_relaxed(tpm5_base + TPM_MOD); + tpm5_regs[2] = readl_relaxed(tpm5_base + TPM_C0SC); + tpm5_regs[3] = readl_relaxed(tpm5_base + TPM_C0V); +} + +static void imx7ulp_tpm_restore(void) +{ + writel_relaxed(tpm5_regs[0], tpm5_base + TPM_SC); + writel_relaxed(tpm5_regs[1], tpm5_base + TPM_MOD); + writel_relaxed(tpm5_regs[2], tpm5_base + TPM_C0SC); + writel_relaxed(tpm5_regs[3], tpm5_base + TPM_C0V); +} + +static void imx7ulp_set_dgo(u32 val) +{ + writel_relaxed(val, pm_info->sim_base + DGO_GPR3); + writel_relaxed(val, pm_info->sim_base + DGO_GPR4); +} + +int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode) +{ + u32 val1 = BM_PMPROT_AHSRUN | BM_PMPROT_AVLP | BM_PMPROT_AVLLS; + u32 val2 = readl_relaxed(smc1_base + PMCTRL); + u32 val3 = readl_relaxed(pmc0_base + PMC0_CTRL); + + val2 &= ~(BM_PMCTRL_RUNM | + BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO); + val3 |= BM_CTRL_LDOOKDIS; switch (mode) { case ULP_PM_RUN: /* system/bus clock enabled */ - val |= PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO; + val2 |= 0x3 << BP_PMCTRL_PSTOPO; break; case ULP_PM_WAIT: /* system clock disabled, bus clock enabled */ - val |= PSTOPO_PSTOP2 << BP_PMCTRL_PSTOPO; + val2 |= 0x2 << BP_PMCTRL_PSTOPO; break; case ULP_PM_STOP: /* system/bus clock disabled */ - val |= PSTOPO_PSTOP1 << BP_PMCTRL_PSTOPO; + val2 |= 0x1 << BP_PMCTRL_PSTOPO; + break; + case ULP_PM_VLPS: + val2 |= 0x2 << BP_PMCTRL_STOPM; + break; + case ULP_PM_VLLS: + val2 |= 0x4 << BP_PMCTRL_STOPM; break; default: return -EINVAL; } - writel_relaxed(val, smc1_base + SMC_PMCTRL); + writel_relaxed(val1, smc1_base + PMPROT); + writel_relaxed(val2, smc1_base + PMCTRL); + writel_relaxed(val3, pmc0_base + PMC0_CTRL); return 0; } -void __init imx7ulp_pm_init(void) +#define MX7ULP_SUSPEND_POWERDWN_PARAM \ + ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +#define MX7ULP_SUSPEND_STANDBY_PARAM \ + ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_STANDBY << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) + +static int imx7ulp_suspend_finish(unsigned long val) +{ + u32 state; + + if (val == 0) + state = MX7ULP_SUSPEND_POWERDWN_PARAM; + else + state = MX7ULP_SUSPEND_STANDBY_PARAM; + + if (psci_ops.cpu_suspend) + return psci_ops.cpu_suspend(state, __pa(cpu_resume)); + + imx7ulp_suspend_in_ocram_fn(suspend_ocram_base); + + return 0; +} + +static void imx7ulp_wdog_disable(void) +{ + /* + * On revision 2.2, wdog2 is by default disabled when out of + * reset, so here, we ONLY disable wdog1. WDOG was in unlock + * state when power on reset or resume from low power mode. + */ + + u32 value = readl_relaxed(wdog1_base + WDOG_CS); + + if (!(value & WDOG_CS_ULK)) + return; + + value &= ~WDOG_CS_EN; + value |= WDOG_CS_CMD32EN | WDOG_CS_UPDATE | WDOG_CS_WAIT | WDOG_CS_STOP; + writel_relaxed(value, wdog1_base + WDOG_CS); + writel_relaxed(0xffff, wdog1_base + WDOG_TOVAL); + + while (readl_relaxed(wdog1_base + WDOG_CS) & WDOG_CS_ULK); + while (!(readl_relaxed(wdog1_base + WDOG_CS) & WDOG_CS_RCS)); +} + +static int imx7ulp_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + if (psci_ops.cpu_suspend) + /* Zzz ... */ + cpu_suspend(1, imx7ulp_suspend_finish); + else { + imx7ulp_set_lpm(ULP_PM_VLPS); + writel_relaxed( + readl_relaxed(pmc1_base + PMC1_VLPS) | BM_VLPS_RBBEN, + pmc1_base + PMC1_VLPS); + + /* Zzz ... */ + cpu_suspend(0, imx7ulp_suspend_finish); + + writel_relaxed( + readl_relaxed(pmc1_base + PMC1_VLPS) & ~BM_VLPS_RBBEN, + pmc1_base + PMC1_VLPS); + imx7ulp_set_lpm(ULP_PM_RUN); + } + break; + case PM_SUSPEND_MEM: + if (psci_ops.cpu_suspend) { + /* Zzz ... */ + cpu_suspend(0, imx7ulp_suspend_finish); + } else { + imx7ulp_gpio_save(); + imx7ulp_port_pcr_save(); + imx7ulp_scg1_save(); + imx7ulp_pcc2_save(); + imx7ulp_pcc3_save(); + imx7ulp_tpm_save(); + if (!console_suspend_enabled) + imx7ulp_lpuart_save(); + imx7ulp_iomuxc_save(); + imx7ulp_set_lpm(ULP_PM_VLLS); + + /* Zzz ... */ + cpu_suspend(0, imx7ulp_suspend_finish); + + imx7ulp_pcc2_restore(); + imx7ulp_pcc3_restore(); + imx7ulp_port_pcr_restore(); + if (!console_suspend_enabled) + imx7ulp_lpuart_restore(); + imx7ulp_set_dgo(0); + imx7ulp_tpm_restore(); + imx7ulp_set_lpm(ULP_PM_RUN); + } + imx7ulp_wdog_disable(); + break; + default: + return -EINVAL; + } + + return 0; +} + +/* Put CA7 into VLLS mode before M4 power off CA7 */ +void imx7ulp_poweroff(void) +{ + imx7ulp_set_lpm(ULP_PM_VLLS); + cpu_suspend(0, imx7ulp_suspend_finish); +} + +static int imx7ulp_pm_valid(suspend_state_t state) +{ + return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM); +} + +static const struct platform_suspend_ops imx7ulp_pm_ops = { + .enter = imx7ulp_pm_enter, + .valid = imx7ulp_pm_valid, +}; + +static int __init imx7ulp_suspend_init(void) +{ + int ret = 0; + + suspend_set_ops(&imx7ulp_pm_ops); + + return ret; +} + +static struct map_desc iram_tlb_io_desc __initdata = { + /* .virtual and .pfn are run-time assigned */ + .length = SZ_1M, + .type = MT_MEMORY_RWX_NONCACHED, +}; + +static int __init imx7ulp_dt_find_lpsram(unsigned long node, const char *uname, + int depth, void *data) +{ + unsigned long lpram_addr; + const __be32 *prop = of_get_flat_dt_prop(node, "reg", NULL); + + if (of_flat_dt_is_compatible(node, "fsl,lpm-sram")) { + if (!prop) + return -EINVAL; + + lpram_addr = be32_to_cpup(prop); + + /* We need to create a 1M page table entry. */ + iram_tlb_io_desc.virtual = + IMX_IO_P2V(lpram_addr & ADDR_1M_MASK); + iram_tlb_io_desc.pfn = __phys_to_pfn(lpram_addr & ADDR_1M_MASK); + iram_tlb_phys_addr = lpram_addr; + iram_tlb_base_addr = IMX_IO_P2V(lpram_addr); + iotable_init(&iram_tlb_io_desc, 1); + } + + return 0; +} + +void __init imx7ulp_pm_map_io(void) +{ + /* + * Get the address of IRAM or OCRAM to be used by the low + * power code from the device tree. + */ + WARN_ON(of_scan_flat_dt(imx7ulp_dt_find_lpsram, NULL)); + + /* Return if no IRAM space is allocated for suspend/resume code. */ + if (!iram_tlb_base_addr) { + pr_warn("No valid ocram available for suspend/resume!\n"); + return; + } +} + +void __init imx7ulp_pm_common_init(const struct imx7ulp_pm_socdata + *socdata) { struct device_node *np; + unsigned long sram_paddr = 0; + const u32 *mmdc_offset_array; + const u32 *mmdc_io_offset_array; + unsigned long i, j; + int ret; + + if (psci_ops.cpu_suspend) { + aips1_base = ioremap(MX7ULP_AIPS1_BASE_ADDR, SZ_1M); + aips2_base = ioremap(MX7ULP_AIPS2_BASE_ADDR, SZ_1M); + aips3_base = ioremap(MX7ULP_AIPS3_BASE_ADDR, SZ_1M); + aips4_base = ioremap(MX7ULP_AIPS4_BASE_ADDR, SZ_1M); + aips5_base = ioremap(MX7ULP_AIPS5_BASE_ADDR, SZ_1M); + } else { + /* Set all entries to 0 except first 3 words reserved for M4. */ + memset((void *)iram_tlb_base_addr, 0, MX7ULP_IRAM_TLB_SIZE); + + /* + * Make sure the IRAM virtual address has a mapping in the IRAM + * page table. + * + * Only use the top 12 bits [31-20] when storing the physical + * address in the page table as only these bits are required + * for 1M mapping. + */ + j = ((iram_tlb_base_addr >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + (iram_tlb_phys_addr & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS1 virtual address has a mapping in the + * IRAM page table. + */ + aips1_base = ioremap(MX7ULP_AIPS1_BASE_ADDR, SZ_1M); + j = (((u32)aips1_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS1_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS2 virtual address has a mapping in the + * IRAM page table. + */ + aips2_base = ioremap(MX7ULP_AIPS2_BASE_ADDR, SZ_1M); + j = (((u32)aips2_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS2_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS3 virtual address has a mapping in the + * IRAM page table. + */ + aips3_base = ioremap(MX7ULP_AIPS3_BASE_ADDR, SZ_1M); + j = (((u32)aips3_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS3_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS4 virtual address has a mapping in the + * IRAM page table. + */ + aips4_base = ioremap(MX7ULP_AIPS4_BASE_ADDR, SZ_1M); + j = (((u32)aips4_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS4_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + /* + * Make sure the AIPS5 virtual address has a mapping in the + * IRAM page table. + */ + aips5_base = ioremap(MX7ULP_AIPS5_BASE_ADDR, SZ_1M); + j = (((u32)aips5_base >> 20) << 2) / 4; + *((unsigned long *)iram_tlb_base_addr + j) = + ((MX7ULP_AIPS5_BASE_ADDR) & ADDR_1M_MASK) | + TT_ATTRIB_NON_CACHEABLE_1M; + } np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1"); smc1_base = of_iomap(np, 0); of_node_put(np); WARN_ON(!smc1_base); + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc0"); + pmc0_base = of_iomap(np, 0); + WARN_ON(!pmc0_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc1"); + pmc1_base = of_iomap(np, 0); + WARN_ON(!pmc1_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-tpm"); + tpm5_base = of_iomap(np, 0); + WARN_ON(!tpm5_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-lpuart"); + lpuart4_base = of_iomap(np, 0); + WARN_ON(!lpuart4_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc2"); + pcc2_base = of_iomap(np, 0); + WARN_ON(!pcc2_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc3"); + pcc3_base = of_iomap(np, 0); + WARN_ON(!pcc3_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-iomuxc1"); + iomuxc1_base = of_iomap(np, 0); + WARN_ON(!iomuxc1_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-scg1"); + scg1_base = of_iomap(np, 0); + WARN_ON(!scg1_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-wdt"); + wdog1_base = of_iomap(np, 0); + WARN_ON(!wdog1_base); + + np = NULL; + for (i = 0; i < 4; i++) { + np = of_find_compatible_node(np, NULL, "fsl,vf610-gpio"); + port_pcr_base[i] = of_iomap(np, 0); + gpio_base[i] = of_iomap(np, 1); + WARN_ON(!port_pcr_base[i]); + WARN_ON(!gpio_base[i]); + } + + if (psci_ops.cpu_suspend) { + pm_info = kzalloc(SZ_16K, GFP_KERNEL); + if (!pm_info) + panic("pm info allocation failed\n"); + } else { + /* + * 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB, + * The lower 8K is not used, so use the lower 8K for IRAM code and + * pm_info. + * + */ + sram_paddr = iram_tlb_phys_addr; + + /* Make sure sram_paddr is 8 byte aligned. */ + if ((uintptr_t)(sram_paddr) & (FNCPY_ALIGN - 1)) + sram_paddr += FNCPY_ALIGN - sram_paddr % (FNCPY_ALIGN); + + /* Get the virtual address of the suspend code. */ + suspend_ocram_base = (void *)IMX_IO_P2V(sram_paddr); + + pm_info = suspend_ocram_base; + } + pm_info->pbase = sram_paddr; + pm_info->resume_addr = virt_to_phys(imx7ulp_cpu_resume); + pm_info->pm_info_size = sizeof(*pm_info); + + pm_info->scg1_base = aips2_base + + (MX7ULP_SCG1_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->smc1_base = aips3_base + + (MX7ULP_SMC1_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->mmdc_base = aips4_base + + (MX7ULP_MMDC_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->mmdc_io_base = aips4_base + + (MX7ULP_MMDC_IO_BASE_ADDR & ~ADDR_1M_MASK); + pm_info->sim_base = aips5_base + + (MX7ULP_SIM_BASE_ADDR & ~ADDR_1M_MASK); + + pm_info->mmdc_io_num = socdata->mmdc_io_num; + mmdc_io_offset_array = socdata->mmdc_io_offset; + pm_info->mmdc_num = socdata->mmdc_num; + mmdc_offset_array = socdata->mmdc_offset; + + for (i = 0; i < pm_info->mmdc_io_num; i++) { + pm_info->mmdc_io_val[i][0] = + mmdc_io_offset_array[i]; + pm_info->mmdc_io_val[i][1] = + readl_relaxed(pm_info->mmdc_io_base + + mmdc_io_offset_array[i]); + } + + /* initialize MMDC settings */ + for (i = 0; i < pm_info->mmdc_num; i++) + pm_info->mmdc_val[i][0] = + mmdc_offset_array[i]; + + for (i = 0; i < pm_info->mmdc_num; i++) + pm_info->mmdc_val[i][1] = imx7ulp_lpddr3_script[i]; + + if (!psci_ops.cpu_suspend) { + imx7ulp_suspend_in_ocram_fn = fncpy( + suspend_ocram_base + sizeof(*pm_info), + &imx7ulp_suspend, + MX7ULP_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); + } + + if (IS_ENABLED(CONFIG_SUSPEND)) { + ret = imx7ulp_suspend_init(); + if (ret) + pr_warn("%s: No DDR LPM support with suspend %d!\n", + __func__, ret); + } +} + +u32 imx7ulp_get_mode(void) +{ + u32 mode; + + mode = readl_relaxed(smc1_base + PMCTRL) & BM_PMCTRL_RUNM; + mode >>= 8; + + return mode; +} + +void __init imx7ulp_pm_init(void) +{ + imx7ulp_pm_common_init(&imx7ulp_lpddr3_pm_data); imx7ulp_set_lpm(ULP_PM_RUN); } + +static irqreturn_t imx7ulp_nmi_isr(int irq, void *param) +{ + writel_relaxed(readl_relaxed(mu_base + MU_SR) | MU_B_SR_NMIC, + mu_base + MU_SR); + pm_system_wakeup(); + + return IRQ_HANDLED; +} + +void imx7ulp_enable_nmi(void) +{ + struct device_node *np; + int irq, ret; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-nmi"); + mu_base = of_iomap(np, 0); + WARN_ON(!mu_base); + irq = of_irq_get(np, 0); + ret = request_irq(irq, imx7ulp_nmi_isr, + IRQF_NO_SUSPEND, "imx7ulp-nmi", NULL); + if (ret) { + pr_err("%s: register interrupt %d failed, rc %d\n", + __func__, irq, ret); + return; + } +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/pm-rpmsg.c linux-imx-phytec/arch/arm/mach-imx/pm-rpmsg.c --- linux-6.1.55/arch/arm/mach-imx/pm-rpmsg.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/pm-rpmsg.c 2024-06-19 12:33:58.132189693 +0200 @@ -0,0 +1,363 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +#define RPMSG_TIMEOUT 1000 + +#define PM_RPMSG_TYPE 0 +#define HEATBEAT_RPMSG_TYPE 2 + +enum pm_rpmsg_cmd { + PM_RPMSG_MODE, + PM_RPMSG_HEART_BEAT, + PM_RPMSG_HEART_BEAT_OFF, +}; + +enum pm_rpmsg_power_mode { + PM_RPMSG_HSRUN, + PM_RPMSG_RUN, + PM_RPMSG_VLPR, + PM_RPMSG_WAIT, + PM_RPMSG_VLPS, + PM_RPMSG_VLLS, + PM_RPMSG_REBOOT, + PM_RPMSG_SHUTDOWN, +}; + +struct pm_rpmsg_info { + struct rpmsg_device *rpdev; + struct device *dev; + struct pm_rpmsg_data *msg; + struct pm_qos_request pm_qos_req; + struct notifier_block restart_handler; + struct completion cmd_complete; + bool first_flag; + struct mutex lock; +}; + +static struct pm_rpmsg_info pm_rpmsg; + +static struct delayed_work heart_beat_work; + +static bool heartbeat_off; + +struct pm_rpmsg_data { + struct imx_rpmsg_head header; + u8 data; +} __attribute__ ((packed)); + +static int pm_send_message(struct pm_rpmsg_data *msg, + struct pm_rpmsg_info *info, bool ack) +{ + int err; + + if (!info->rpdev) { + dev_dbg(info->dev, + "rpmsg channel not ready, m4 image ready?\n"); + return -EINVAL; + } + + mutex_lock(&info->lock); + cpu_latency_qos_add_request(&info->pm_qos_req, + 0); + + reinit_completion(&info->cmd_complete); + + err = rpmsg_send(info->rpdev->ept, (void *)msg, + sizeof(struct pm_rpmsg_data)); + + if (err) { + dev_err(&info->rpdev->dev, "rpmsg_send failed: %d\n", err); + goto err_out; + } + + if (ack) { + err = wait_for_completion_timeout(&info->cmd_complete, + msecs_to_jiffies(RPMSG_TIMEOUT)); + if (!err) { + dev_err(&info->rpdev->dev, "rpmsg_send timeout!\n"); + err = -ETIMEDOUT; + goto err_out; + } + + if (info->msg->data != 0) { + dev_err(&info->rpdev->dev, "rpmsg not ack %d!\n", + info->msg->data); + err = -EINVAL; + goto err_out; + } + + err = 0; + } + +err_out: + cpu_latency_qos_remove_request(&info->pm_qos_req); + mutex_unlock(&info->lock); + + return err; +} + +static int pm_vlls_notify_m4(bool enter) +{ + struct pm_rpmsg_data msg; + + memset(&msg, 0, sizeof(msg)); + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_MODE; + msg.data = enter ? PM_RPMSG_VLLS : PM_RPMSG_RUN; + + return pm_send_message(&msg, &pm_rpmsg, true); +} + +void pm_shutdown_notify_m4(void) +{ + struct pm_rpmsg_data msg; + + memset(&msg, 0, sizeof(msg)); + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_MODE; + msg.data = PM_RPMSG_SHUTDOWN; + /* No ACK from M4 */ + local_irq_enable(); + pm_send_message(&msg, &pm_rpmsg, false); + imx7ulp_poweroff(); +} + +void pm_reboot_notify_m4(void) +{ + struct pm_rpmsg_data msg; + + memset(&msg, 0, sizeof(msg)); + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_MODE; + msg.data = PM_RPMSG_REBOOT; + + pm_send_message(&msg, &pm_rpmsg, false); + /* Give a grace period for failure to restart of 1s */ + mdelay(1000); +} + +void pm_heartbeat_off_notify_m4(bool enter) +{ + struct pm_rpmsg_data msg; + + memset(&msg, 0, sizeof(msg)); + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = PM_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_HEART_BEAT_OFF; + msg.data = enter ? 0 : 1; + + pm_send_message(&msg, &pm_rpmsg, true); +} + +static void pm_heart_beat_work_handler(struct work_struct *work) +{ + struct pm_rpmsg_data msg; + + memset(&msg, 0, sizeof(msg)); + /* Notify M4 side A7 in RUN mode at boot time */ + if (pm_rpmsg.first_flag) { + pm_vlls_notify_m4(false); + + pm_heartbeat_off_notify_m4(heartbeat_off); + + pm_rpmsg.first_flag = false; + } + + if (!heartbeat_off) { + msg.header.cate = IMX_RMPSG_LIFECYCLE; + msg.header.major = IMX_RMPSG_MAJOR; + msg.header.minor = IMX_RMPSG_MINOR; + msg.header.type = HEATBEAT_RPMSG_TYPE; + msg.header.cmd = PM_RPMSG_HEART_BEAT; + msg.data = 0; + pm_send_message(&msg, &pm_rpmsg, false); + + schedule_delayed_work(&heart_beat_work, + msecs_to_jiffies(30000)); + } +} + +static void pm_poweroff_rpmsg(void) +{ + pm_shutdown_notify_m4(); + /* Wait 5s to let M4 power off A7 */ + mdelay(5000); + pr_emerg("Unable to poweroff system\n"); +} + +static int pm_restart_handler(struct notifier_block *this, unsigned long mode, + void *cmd) +{ + pm_reboot_notify_m4(); + + return NOTIFY_DONE; +} + +static int pm_rpmsg_probe(struct rpmsg_device *rpdev) +{ + int ret; + + pm_rpmsg.rpdev = rpdev; + + dev_info(&rpdev->dev, "new channel: 0x%x -> 0x%x!\n", + rpdev->src, rpdev->dst); + + init_completion(&pm_rpmsg.cmd_complete); + mutex_init(&pm_rpmsg.lock); + + INIT_DELAYED_WORK(&heart_beat_work, + pm_heart_beat_work_handler); + + pm_rpmsg.first_flag = true; + schedule_delayed_work(&heart_beat_work, 0); + + pm_rpmsg.restart_handler.notifier_call = pm_restart_handler; + pm_rpmsg.restart_handler.priority = 128; + ret = register_restart_handler(&pm_rpmsg.restart_handler); + if (ret) + dev_err(&rpdev->dev, "cannot register restart handler\n"); + + pm_power_off = pm_poweroff_rpmsg; + + return 0; +} + +static int pm_rpmsg_cb(struct rpmsg_device *rpdev, void *data, int len, + void *priv, u32 src) +{ + struct pm_rpmsg_data *msg = (struct pm_rpmsg_data *)data; + + pm_rpmsg.msg = msg; + + complete(&pm_rpmsg.cmd_complete); + + return 0; +} + +static void pm_rpmsg_remove(struct rpmsg_device *rpdev) +{ + dev_info(&rpdev->dev, "pm rpmsg driver is removed\n"); +} + +static struct rpmsg_device_id pm_rpmsg_id_table[] = { + { .name = "rpmsg-life-cycle-channel" }, + { }, +}; + +static struct rpmsg_driver pm_rpmsg_driver = { + .drv.name = "pm_rpmsg", + .drv.owner = THIS_MODULE, + .id_table = pm_rpmsg_id_table, + .probe = pm_rpmsg_probe, + .callback = pm_rpmsg_cb, + .remove = pm_rpmsg_remove, +}; + +#ifdef CONFIG_PM_SLEEP +static int pm_heartbeat_suspend(struct device *dev) +{ + int err; + + err = pm_vlls_notify_m4(true); + if (err) + return err; + + cancel_delayed_work_sync(&heart_beat_work); + + return 0; +} + +static int pm_heartbeat_resume(struct device *dev) +{ + int err; + + err = pm_vlls_notify_m4(false); + if (err) + return err; + + schedule_delayed_work(&heart_beat_work, + msecs_to_jiffies(10000)); + + return 0; +} +#endif + +static int pm_heartbeat_probe(struct platform_device *pdev) +{ + platform_set_drvdata(pdev, &pm_rpmsg); + + return register_rpmsg_driver(&pm_rpmsg_driver); +} + +static const struct of_device_id pm_heartbeat_id[] = { + {"fsl,heartbeat-rpmsg",}, + {}, +}; +MODULE_DEVICE_TABLE(of, pm_heartbeat_id); + +static const struct dev_pm_ops pm_heartbeat_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_heartbeat_suspend, + pm_heartbeat_resume) +}; + +static struct platform_driver pm_heartbeat_driver = { + .driver = { + .name = "heartbeat-rpmsg", + .owner = THIS_MODULE, + .of_match_table = pm_heartbeat_id, + .pm = &pm_heartbeat_ops, + }, + .probe = pm_heartbeat_probe, +}; + +static int __init setup_heartbeat(char *str) +{ + heartbeat_off = true; + + return 1; +}; +__setup("heartbeat_off", setup_heartbeat); + +module_platform_driver(pm_heartbeat_driver); + +MODULE_DESCRIPTION("Freescale PM rpmsg driver"); +MODULE_AUTHOR("Anson Huang "); +MODULE_LICENSE("GPL"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/resume-imx6.S linux-imx-phytec/arch/arm/mach-imx/resume-imx6.S --- linux-6.1.55/arch/arm/mach-imx/resume-imx6.S 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/resume-imx6.S 2024-06-19 12:33:58.132189693 +0200 @@ -14,11 +14,24 @@ * where absolute virtual addresses to the data section have to be * turned into relative ones. */ + .macro is_cortex_a7 + + /* Read the primary cpu number is MPIDR */ + mrc p15, 0, r5, c0, c0, 0 + ldr r6, =0xfff0 + and r5, r5, r6 + ldr r6, =0xc070 + cmp r5, r6 + + .endm ENTRY(v7_cpu_resume) bl v7_invalidate_l1 + is_cortex_a7 + beq done #ifdef CONFIG_CACHE_L2X0 bl l2c310_early_resume #endif +done: b cpu_resume ENDPROC(v7_cpu_resume) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/smc_sip.h linux-imx-phytec/arch/arm/mach-imx/smc_sip.h --- linux-6.1.55/arch/arm/mach-imx/smc_sip.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/smc_sip.h 2024-06-19 12:33:58.132189693 +0200 @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2018 NXP + */ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __SMC_SIP_H__ +#define __SMC_SIP_H__ + +#include + +/* + * Macro definition building the OPTEE SMC Code function + * for a Fast Call, SIP operation + */ +#define OPTEE_SMC_FAST_CALL_SIP_VAL(func_num) \ + ARM_SMCCC_CALL_VAL( \ + ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_SIP, \ + (func_num)) + + +/* + * Definition of the i.MX SMC SIP Operations + * Operation value must be aligned with i.MX OPTEE + * SIP definitions + */ +/* Busfreq operation */ +#define IMX_SIP_BUSFREQ_CHANGE 6 + +#endif /* __SMC_SIP_H__ */ + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/smp_wfe_imx6.S linux-imx-phytec/arch/arm/mach-imx/smp_wfe_imx6.S --- linux-6.1.55/arch/arm/mach-imx/smp_wfe_imx6.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/smp_wfe_imx6.S 2024-06-19 12:33:58.132189693 +0200 @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include "hardware.h" + +#ifdef CONFIG_SMP +.extern scu_base +#endif + +.globl wfe_smp_freq_change_start +.globl wfe_smp_freq_change_end + +#ifdef CONFIG_SMP + + .align 3 + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + /* disable d-cache */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + dsb + isb + + push {r0 - r11, lr} + + ldr r7, =v7_flush_kern_cache_all + mov lr, pc + mov pc, r7 + pop {r0 - r11, lr} + + .endm + +ENTRY(wfe_smp_freq_change) +wfe_smp_freq_change_start: + push {r4 - r11, lr} + + mov r6, r0 + mov r7, r1 + + dsb + isb + + disable_l1_dcache + + isb + + /* Turn off SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + bic r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + + /* Inform the SCU we are going to enter WFE. */ + push {r0 - r11, lr} + + ldr r0,=scu_base + ldr r0, [r0] + mov r1, #SCU_PM_DORMANT + ldr r3, =scu_power_mode + mov lr, pc + mov pc, r3 + + pop {r0 - r11, lr} + +go_back_wfe: + wfe + + ldr r3, [r7] + cmp r3, #1 + beq go_back_wfe + + /* Turn ON SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + orr r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + /* Enable L1 data cache. */ + mrc p15, 0, r8, c1, c0, 0 + orr r8, r8, #0x4 + mcr p15, 0, r8, c1, c0, 0 + isb + + /* Inform the SCU we have exited WFE. */ + push {r0 - r11, lr} + + ldr r0,=scu_base + ldr r0, [r0] + mov r1, #SCU_PM_NORMAL + ldr r3, =scu_power_mode + mov lr, pc + mov pc, r3 + + pop {r0 - r11, lr} + + /* Pop all saved registers. */ + pop {r4 - r11, lr} + mov pc, lr + .ltorg +wfe_smp_freq_change_end: +ENDPROC(wfe_smp_freq_change) + +#ifdef CONFIG_OPTEE +/** + * @brief Switch CPU in WFE mode while bus frequency change + * on-going + * + * @param[in] r0 CPU in WFE Status + * @param[in] r1 Bus frequency change status + */ + +.globl imx_smp_wfe_optee_end + +ENTRY(imx_smp_wfe_optee) + push {r4-r11, lr} + + dsb + isb + + disable_l1_dcache + isb + + /* Set flag CPU entering WFE. */ + mov r4, #1 + str r4, [r0] + + dsb + isb + +1: + wfe + + /* Check if busfreq is done, else loop */ + ldr r4, [r1] + cmp r4, #1 + beq 1b + + /* Enable L1 data cache. */ + mrc p15, 0, r4, c1, c0, 0 + orr r4, r4, #0x4 + mcr p15, 0, r4, c1, c0, 0 + isb + + /* Set flag CPU exiting WFE. */ + mov r4, #0 + str r4, [r0] + + /* Pop all saved registers. */ + pop {r4-r11, lr} + mov pc, lr + .ltorg +imx_smp_wfe_optee_end: +ENDPROC(imx_smp_wfe_optee) +#endif +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/smp_wfe.S linux-imx-phytec/arch/arm/mach-imx/smp_wfe.S --- linux-6.1.55/arch/arm/mach-imx/smp_wfe.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/smp_wfe.S 2024-06-19 12:33:58.132189693 +0200 @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "hardware.h" + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + +#ifdef CONFIG_SMP + .align 3 + +ENTRY(imx7_smp_wfe) + push {r4 - r11, lr} + + dsb + isb + + disable_l1_dcache + + isb + + /* Turn off SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + bic r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + /* Set flag of entering WFE. */ + mov r7, #0xff + lsl r7, r7, r0 + mov r6, #SCU_PM_DORMANT + lsl r6, r6, r0 + ldr r8, [r1, #0x4] + bic r8, r8, r7 + orr r6, r6, r8 + str r6, [r1, #0x4] + +go_back_wfe: + wfe + + /* Offset 0x0 stores busfeq done flag */ + ldr r6, [r1] + cmp r6, #1 + beq go_back_wfe + + /* Turn ON SMP bit. */ + mrc p15, 0, r8, c1, c0, 1 + orr r8, r8, #0x40 + mcr p15, 0, r8, c1, c0, 1 + + isb + /* Enable L1 data cache. */ + mrc p15, 0, r8, c1, c0, 0 + orr r8, r8, #0x4 + mcr p15, 0, r8, c1, c0, 0 + isb + + /* Set flag of exiting WFE. */ + mov r7, #0xff + lsl r7, r7, r0 + mov r6, #SCU_PM_NORMAL + lsl r6, r6, r0 + ldr r8, [r1, #0x4] + bic r8, r8, r7 + orr r6, r6, r8 + str r6, [r1, #0x4] + + /* Pop all saved registers. */ + pop {r4 - r11, lr} + mov pc, lr + .ltorg +ENDPROC(imx7_smp_wfe) +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/src.c linux-imx-phytec/arch/arm/mach-imx/src.c --- linux-6.1.55/arch/arm/mach-imx/src.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/src.c 2024-06-19 12:33:58.132189693 +0200 @@ -6,7 +6,6 @@ #include #include -#include #include #include #include @@ -17,9 +16,7 @@ #include "hardware.h" #define SRC_SCR 0x000 -#define SRC_GPR1_V1 0x020 -#define SRC_GPR1_V2 0x074 -#define SRC_GPR1(gpr_v2) ((gpr_v2) ? SRC_GPR1_V2 : SRC_GPR1_V1) +#define SRC_GPR1 0x020 #define BP_SRC_SCR_WARM_RESET_ENABLE 0 #define BP_SRC_SCR_SW_GPU_RST 1 #define BP_SRC_SCR_SW_VPU_RST 2 @@ -29,17 +26,17 @@ #define BP_SRC_SCR_CORE1_RST 14 #define BP_SRC_SCR_CORE1_ENABLE 22 /* below is for i.MX7D */ +#define SRC_GPR1_V2 0x074 +#define SRC_A7RCR0 0x004 #define SRC_A7RCR1 0x008 -#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1 -#define GPC_CPU_PGC_SW_PUP_REQ 0xf0 -#define GPC_CPU_PGC_SW_PDN_REQ 0xfc -#define GPC_PGC_C1 0x840 -#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2 +#define SRC_M4RCR 0x00C + +#define BP_SRC_A7RCR0_A7_CORE_RESET0 0 +#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1 static void __iomem *src_base; -static DEFINE_SPINLOCK(scr_lock); -static bool gpr_v2; -static void __iomem *gpc_base; +static DEFINE_SPINLOCK(src_lock); +static bool m4_is_enabled; static const int sw_reset_bits[5] = { BP_SRC_SCR_SW_GPU_RST, @@ -49,6 +46,11 @@ BP_SRC_SCR_SW_IPU2_RST }; +bool imx_src_is_m4_enabled(void) +{ + return m4_is_enabled; +} + static int imx_src_reset_module(struct reset_controller_dev *rcdev, unsigned long sw_reset_idx) { @@ -62,11 +64,11 @@ bit = 1 << sw_reset_bits[sw_reset_idx]; - spin_lock_irqsave(&scr_lock, flags); + spin_lock_irqsave(&src_lock, flags); val = readl_relaxed(src_base + SRC_SCR); val |= bit; writel_relaxed(val, src_base + SRC_SCR); - spin_unlock_irqrestore(&scr_lock, flags); + spin_unlock_irqrestore(&src_lock, flags); timeout = jiffies + msecs_to_jiffies(1000); while (readl(src_base + SRC_SCR) & bit) { @@ -82,50 +84,14 @@ .reset = imx_src_reset_module, }; -static void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) -{ - writel_relaxed(enable, gpc_base + offset); -} - -/* - * The motivation for bringing up the second i.MX7D core inside the kernel - * is that legacy vendor bootloaders usually do not implement PSCI support. - * This is a significant blocker for systems in the field that are running old - * bootloader versions to upgrade to a modern mainline kernel version, as only - * one CPU of the i.MX7D would be brought up. - * Bring up the second i.MX7D core inside the kernel to make the migration - * path to mainline kernel easier for the existing iMX7D users. - */ -void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) -{ - u32 reg = pdn ? GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ; - u32 val, pup; - int ret; - - imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1); - val = readl_relaxed(gpc_base + reg); - val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7; - writel_relaxed(val, gpc_base + reg); - - ret = readl_relaxed_poll_timeout_atomic(gpc_base + reg, pup, - !(pup & BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7), - 5, 1000000); - if (ret < 0) { - pr_err("i.MX7D: CORE1_A7 power up timeout\n"); - val &= ~BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7; - writel_relaxed(val, gpc_base + reg); - } - - imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1); -} - void imx_enable_cpu(int cpu, bool enable) { u32 mask, val; cpu = cpu_logical_map(cpu); - spin_lock(&scr_lock); - if (gpr_v2) { + spin_lock(&src_lock); + if (cpu_is_imx7d()) { + /* enable core */ if (enable) imx_gpcv2_set_core1_pdn_pup_by_software(false); @@ -140,26 +106,42 @@ val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); writel_relaxed(val, src_base + SRC_SCR); } - spin_unlock(&scr_lock); + spin_unlock(&src_lock); } void imx_set_cpu_jump(int cpu, void *jump_addr) { + spin_lock(&src_lock); cpu = cpu_logical_map(cpu); - writel_relaxed(__pa_symbol(jump_addr), - src_base + SRC_GPR1(gpr_v2) + cpu * 8); + if (cpu_is_imx7d()) + writel_relaxed(__pa_symbol(jump_addr), + src_base + SRC_GPR1_V2 + cpu * 8); + else + writel_relaxed(__pa_symbol(jump_addr), + src_base + SRC_GPR1 + cpu * 8); + spin_unlock(&src_lock); } u32 imx_get_cpu_arg(int cpu) { cpu = cpu_logical_map(cpu); - return readl_relaxed(src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4); + if (cpu_is_imx7d()) + return readl_relaxed(src_base + SRC_GPR1_V2 + + cpu * 8 + 4); + else + return readl_relaxed(src_base + SRC_GPR1 + + cpu * 8 + 4); } void imx_set_cpu_arg(int cpu, u32 arg) { cpu = cpu_logical_map(cpu); - writel_relaxed(arg, src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4); + if (cpu_is_imx7d()) + writel_relaxed(arg, src_base + SRC_GPR1_V2 + + cpu * 8 + 4); + else + writel_relaxed(arg, src_base + SRC_GPR1 + + cpu * 8 + 4); } void __init imx_src_init(void) @@ -168,43 +150,41 @@ u32 val; np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src"); - if (!np) - return; + if (!np) { + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-src"); + if (!np) + return; + } + src_base = of_iomap(np, 0); WARN_ON(!src_base); + if (cpu_is_imx7d()) { + val = readl_relaxed(src_base + SRC_M4RCR); + if (((val & BIT(3)) == BIT(3)) && !(val & BIT(0))) + m4_is_enabled = true; + else + m4_is_enabled = false; + return; + } + /* * force warm reset sources to generate cold reset * for a more reliable restart */ - spin_lock(&scr_lock); + spin_lock(&src_lock); val = readl_relaxed(src_base + SRC_SCR); - val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); - writel_relaxed(val, src_base + SRC_SCR); - spin_unlock(&scr_lock); -} -void __init imx7_src_init(void) -{ - struct device_node *np; - - gpr_v2 = true; - - np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-src"); - if (!np) - return; + /* bit 4 is m4c_non_sclr_rst on i.MX6SX */ + if (cpu_is_imx6sx() && ((val & + (1 << BP_SRC_SCR_SW_OPEN_VG_RST)) == 0)) + m4_is_enabled = true; + else + m4_is_enabled = false; - src_base = of_iomap(np, 0); - if (!src_base) - return; - - np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc"); - if (!np) - return; - - gpc_base = of_iomap(np, 0); - if (!gpc_base) - return; + val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); + writel_relaxed(val, src_base + SRC_SCR); + spin_unlock(&src_lock); } static const struct of_device_id imx_src_dt_ids[] = { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/suspend-imx6.S linux-imx-phytec/arch/arm/mach-imx/suspend-imx6.S --- linux-6.1.55/arch/arm/mach-imx/suspend-imx6.S 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mach-imx/suspend-imx6.S 2024-06-19 12:33:58.132189693 +0200 @@ -41,23 +41,32 @@ #define PM_INFO_RESUME_ADDR_OFFSET 0x4 #define PM_INFO_DDR_TYPE_OFFSET 0x8 #define PM_INFO_PM_INFO_SIZE_OFFSET 0xC -#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 -#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 -#define PM_INFO_MX6Q_SRC_P_OFFSET 0x18 -#define PM_INFO_MX6Q_SRC_V_OFFSET 0x1C -#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x20 -#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x24 -#define PM_INFO_MX6Q_CCM_P_OFFSET 0x28 -#define PM_INFO_MX6Q_CCM_V_OFFSET 0x2C -#define PM_INFO_MX6Q_GPC_P_OFFSET 0x30 -#define PM_INFO_MX6Q_GPC_V_OFFSET 0x34 -#define PM_INFO_MX6Q_L2_P_OFFSET 0x38 -#define PM_INFO_MX6Q_L2_V_OFFSET 0x3C -#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 -#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 +#define PM_INFO_MX6Q_MMDC0_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC0_V_OFFSET 0x14 +#define PM_INFO_MX6Q_MMDC1_P_OFFSET 0x18 +#define PM_INFO_MX6Q_MMDC1_V_OFFSET 0x1C +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x20 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x24 +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x28 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x2C +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x30 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x34 +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x38 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x3C +#define PM_INFO_MX6Q_L2_P_OFFSET 0x40 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x44 +#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x48 +#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x4C +#define PM_INFO_MX6Q_TTBR1_V_OFFSET 0x50 +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x54 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x58 +/* below offsets depends on MX6_MAX_MMDC_IO_NUM(36) definition */ +#define PM_INFO_MMDC_NUM_OFFSET 0x208 +#define PM_INFO_MMDC_VAL_OFFSET 0x20C #define MX6Q_SRC_GPR1 0x20 #define MX6Q_SRC_GPR2 0x24 +#define MX6Q_MMDC_MISC 0x18 #define MX6Q_MMDC_MAPSR 0x404 #define MX6Q_MMDC_MPDGCTRL0 0x83c #define MX6Q_GPC_IMR1 0x08 @@ -65,10 +74,50 @@ #define MX6Q_GPC_IMR3 0x10 #define MX6Q_GPC_IMR4 0x14 #define MX6Q_CCM_CCR 0x0 +#define MX6Q_ANATOP_CORE 0x140 .align 3 .arm + /* Check if the cpu is cortex-a7 */ + .macro is_cortex_a7 + + /* Read the primary cpu number is MPIDR */ + mrc p15, 0, r5, c0, c0, 0 + ldr r6, =0xfff0 + and r5, r5, r6 + ldr r6, =0xc070 + cmp r5, r6 + + .endm + + .macro disable_l1_cache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 -r10, lr} + ldr r7, = v7_flush_dcache_all + mov lr, pc + mov pc , r7 + pop {r0 -r10, lr} + + .endm + .macro sync_l2_cache /* sync L2 cache to drain L2's buffers to DRAM. */ @@ -87,29 +136,8 @@ .endm - .macro resume_mmdc - - /* restore MMDC IO */ - cmp r5, #0x0 - ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] - ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] - - ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] - ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET - add r7, r7, r0 -1: - ldr r8, [r7], #0x4 - ldr r9, [r7], #0x4 - str r9, [r11, r8] - subs r6, r6, #0x1 - bne 1b - - cmp r5, #0x0 - ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] - ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] - - cmp r3, #IMX_DDR_TYPE_LPDDR2 - bne 4f + /* r11 must be MMDC base address */ + .macro reset_read_fifo /* reset read FIFO, RST_RD_FIFO */ ldr r7, =MX6Q_MMDC_MPDGCTRL0 @@ -129,23 +157,294 @@ ldr r6, [r11, r7] ands r6, r6, #(1 << 31) bne 3b + + /* check if lppdr2 2 channel mode is enabled */ + ldr r7, =MX6Q_MMDC_MISC + ldr r6, [r11, r7] + ands r6, r6, #(1 << 2) + beq 6f + + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r12, r7] + orr r6, r6, #(1 << 31) + str r6, [r12, r7] 4: + ldr r6, [r12, r7] + ands r6, r6, #(1 << 31) + bne 4b + + ldr r6, [r12, r7] + orr r6, r6, #(1 << 31) + str r6, [r12, r7] +5: + ldr r6, [r12, r7] + ands r6, r6, #(1 << 31) + bne 5b + +6: + .endm + + /* r11 must be MMDC base address */ + .macro mmdc_out_and_auto_self_refresh + /* let DDR out of self-refresh */ ldr r7, [r11, #MX6Q_MMDC_MAPSR] bic r7, r7, #(1 << 21) str r7, [r11, #MX6Q_MMDC_MAPSR] -5: +7: ldr r7, [r11, #MX6Q_MMDC_MAPSR] ands r7, r7, #(1 << 25) - bne 5b + bne 7b /* enable DDR auto power saving */ ldr r7, [r11, #MX6Q_MMDC_MAPSR] bic r7, r7, #0x1 str r7, [r11, #MX6Q_MMDC_MAPSR] + /* check if lppdr2 2 channel mode is enabled */ + ldr r7, =MX6Q_MMDC_MISC + ldr r6, [r11, r7] + ands r6, r6, #(1 << 2) + beq 9f + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r12, #MX6Q_MMDC_MAPSR] +8: + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 8b + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r12, #MX6Q_MMDC_MAPSR] +9: + .endm + + /* r10 must be iomuxc base address */ + .macro resume_iomuxc_gpr + + add r10, r10, #0x4000 + /* IOMUXC GPR DRAM_RESET_BYPASS */ + ldr r4, [r10, #0x8] + bic r4, r4, #(0x1 << 27) + str r4, [r10, #0x8] + /* IOMUXC GPR DRAM_CKE_BYPASS */ + ldr r4, [r10, #0x8] + bic r4, r4, #(0x1 << 31) + str r4, [r10, #0x8] + .endm + .macro resume_io + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +10: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x8 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 10b + + cmp r5, #0x0 + /* Here only MMDC0 is set */ + ldreq r11, [r0, #PM_INFO_MX6Q_MMDC0_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_MMDC0_P_OFFSET] + ldreq r12, [r0, #PM_INFO_MX6Q_MMDC1_V_OFFSET] + ldrne r12, [r0, #PM_INFO_MX6Q_MMDC1_P_OFFSET] + + reset_read_fifo + mmdc_out_and_auto_self_refresh + + .endm + + .macro resume_mmdc_io + + cmp r5, #0x0 + ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + ldreq r11, [r0, #PM_INFO_MX6Q_MMDC0_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_MMDC0_P_OFFSET] + + /* resume mmdc iomuxc settings */ + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +11: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x8 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 11b + + /* check whether we need to restore MMDC */ + cmp r5, #0x0 + beq 12f + + /* check whether last suspend is with M/F mix off */ + ldr r9, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET] + ldr r6, [r9, #0x220] + cmp r6, #0x0 + bne 13f +12: + resume_iomuxc_gpr + reset_read_fifo + + b 17f +13: + /* restore MMDC settings */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_VAL_OFFSET + add r7, r7, r0 +14: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r11, r8] + subs r6, r6, #0x1 + bne 14b + + /* let DDR enter self-refresh */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 20) + str r7, [r11, #MX6Q_MMDC_MAPSR] +15: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + beq 15b + + resume_iomuxc_gpr + reset_read_fifo + + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX6Q_MMDC_MAPSR] +16: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne 16b + + /* kick off MMDC */ + ldr r4, =0x0 + str r4, [r11, #0x1c] + +17: + mmdc_out_and_auto_self_refresh + + .endm + + .macro store_ttbr1 + + /* Store TTBR1 to pm_info->ttbr1 */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_MX6Q_TTBR1_V_OFFSET] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r6, [r6] + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r6, c2, c0, 1 + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Disable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + is_cortex_a7 + beq 17f + +#ifdef CONFIG_CACHE_L2X0 + ldr r8, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + mov r6, #0x0 + str r6, [r8, #0x100] + + dsb + isb +#endif +17: + .endm + + .macro restore_ttbr1 + + is_cortex_a7 + beq 18f + +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2. */ + ldr r8, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + ldr r7, =0x1 + str r7, [r8, #0x100] +#endif + +18: + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Restore TTBCR */ + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Restore TTBR1, get the origin ttbr1 from pm info */ + ldr r7, [r0, #PM_INFO_MX6Q_TTBR1_V_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + ENTRY(imx6_suspend) ldr r1, [r0, #PM_INFO_PBASE_OFFSET] ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] @@ -180,10 +479,25 @@ str r9, [r11, #MX6Q_SRC_GPR1] str r1, [r11, #MX6Q_SRC_GPR2] + /* + * Check if the cpu is Cortex-A7, for Cortex-A7 + * the cache implementation is not the same as + * Cortex-A9, so the cache maintenance operation + * is different. + */ + is_cortex_a7 + beq a7_dache_flush + /* need to sync L2 cache before DSM. */ sync_l2_cache + b ttbr_store +a7_dache_flush: + disable_l1_cache +ttbr_store: + store_ttbr1 - ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldr r11, [r0, #PM_INFO_MX6Q_MMDC0_V_OFFSET] + ldr r12, [r0, #PM_INFO_MX6Q_MMDC1_V_OFFSET] /* * put DDR explicitly into self-refresh and * disable automatic power savings. @@ -202,31 +516,59 @@ ands r7, r7, #(1 << 25) beq poll_dvfs_set + /* check if lppdr2 2 channel mode is enabled */ + ldr r7, =MX6Q_MMDC_MISC + ldr r6, [r11, r7] + ands r6, r6, #(1 << 2) + beq skip_self_refresh_ch1 + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r12, #MX6Q_MMDC_MAPSR] + + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r12, #MX6Q_MMDC_MAPSR] + +poll_dvfs_set_ch1: + ldr r7, [r12, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq poll_dvfs_set_ch1 + +skip_self_refresh_ch1: + /* use r11 to store the IO address */ ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] - ldr r6, =0x0 - ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET add r8, r8, r0 - /* LPDDR2's last 3 IOs need special setting */ - cmp r3, #IMX_DDR_TYPE_LPDDR2 - subeq r7, r7, #0x3 set_mmdc_io_lpm: - ldr r9, [r8], #0x8 - str r6, [r11, r9] - subs r7, r7, #0x1 + ldr r7, [r8], #0x8 + ldr r9, [r8], #0x4 + str r9, [r11, r7] + subs r6, r6, #0x1 bne set_mmdc_io_lpm - cmp r3, #IMX_DDR_TYPE_LPDDR2 - bne set_mmdc_io_lpm_done - ldr r6, =0x1000 - ldr r9, [r8], #0x8 - str r6, [r11, r9] - ldr r9, [r8], #0x8 - str r6, [r11, r9] - ldr r6, =0x80000 - ldr r9, [r8] - str r6, [r11, r9] -set_mmdc_io_lpm_done: + /* check whether it supports Mega/Fast off */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + cmp r6, #0x0 + beq set_mmdc_lpm_done + + /* IOMUXC GPR DRAM_RESET */ + add r11, r11, #0x4000 + ldr r6, [r11, #0x8] + orr r6, r6, #(0x1 << 28) + str r6, [r11, #0x8] + + /* IOMUXC GPR DRAM_RESET_BYPASS */ + ldr r6, [r11, #0x8] + orr r6, r6, #(0x1 << 27) + str r6, [r11, #0x8] + + /* IOMUXC GPR DRAM_CKE_BYPASS */ + ldr r6, [r11, #0x8] + orr r6, r6, #(0x1 << 31) + str r6, [r11, #0x8] +set_mmdc_lpm_done: /* * mask all GPC interrupts before @@ -286,6 +628,27 @@ subs r6, r6, #0x1 bne rbc_loop + /* + * ERR005852 Analog: Transition from Deep Sleep Mode to + * LDO Bypass Mode may cause the slow response of the + * VDDARM_CAP output. + * + * Software workaround: + * if internal ldo(VDDARM) bypassed, switch to analog bypass + * mode (0x1E), prio to entering DSM, and then, revert to the + * normal bypass mode, when exiting from DSM. + */ + ldr r11, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET] + ldr r10, [r11, #MX6Q_ANATOP_CORE] + and r10, r10, #0x1f + cmp r10, #0x1f + bne ldo_check_done1 +ldo_analog_bypass: + ldr r10, [r11, #MX6Q_ANATOP_CORE] + bic r10, r10, #0x1f + orr r10, r10, #0x1e + str r10, [r11, #MX6Q_ANATOP_CORE] +ldo_check_done1: /* Zzz, enter stop mode */ wfi nop @@ -298,8 +661,28 @@ * wakeup source, system should auto * resume, we need to restore MMDC IO first */ + /* restore it with 0x1f if use ldo bypass mode.*/ + ldr r10, [r11, #MX6Q_ANATOP_CORE] + and r10, r10, #0x1f + cmp r10, #0x1e + bne ldo_check_done2 +ldo_bypass_restore: + ldr r10, [r11, #MX6Q_ANATOP_CORE] + orr r10, r10, #0x1f + str r10, [r11, #MX6Q_ANATOP_CORE] +ldo_check_done2: mov r5, #0x0 - resume_mmdc + /* check whether it supports Mega/Fast off */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + cmp r6, #0x0 + beq only_resume_io + resume_mmdc_io + b resume_mmdc_done +only_resume_io: + resume_io +resume_mmdc_done: + + restore_ttbr1 /* return to suspend finish */ ret lr @@ -314,6 +697,16 @@ mcr p15, 0, r6, c1, c0, 0 isb + /* restore it with 0x1f if use ldo bypass mode.*/ + ldr r11, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET] + ldr r7, [r11, #MX6Q_ANATOP_CORE] + and r7, r7, #0x1f + cmp r7, #0x1e + bne ldo_check_done3 + ldr r7, [r11, #MX6Q_ANATOP_CORE] + orr r7, r7, #0x1f + str r7, [r11, #MX6Q_ANATOP_CORE] +ldo_check_done3: /* get physical resume address from pm_info. */ ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] /* clear core0's entry and parameter */ @@ -324,7 +717,16 @@ ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET] mov r5, #0x1 - resume_mmdc + /* check whether it supports Mega/Fast off */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + cmp r6, #0x0 + beq dsm_only_resume_io + resume_mmdc_io + b dsm_resume_mmdc_done +dsm_only_resume_io: + ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET] + resume_io +dsm_resume_mmdc_done: ret lr ENDPROC(imx6_suspend) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/suspend-imx7.S linux-imx-phytec/arch/arm/mach-imx/suspend-imx7.S --- linux-6.1.55/arch/arm/mach-imx/suspend-imx7.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/suspend-imx7.S 2024-06-19 12:33:58.132189693 +0200 @@ -0,0 +1,713 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include "hardware.h" + +/* + * ==================== low level suspend ==================== + * + * Better to follow below rules to use ARM registers: + * r0: pm_info structure address; + * r1 ~ r4: for saving pm_info members; + * r5 ~ r10: free registers; + * r11: io base address. + * + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7_suspend code + * PM_INFO structure(imx7_cpu_pm_info) + * ======================== low address ======================= + */ + +/* + * Below offsets are based on struct imx7_cpu_pm_info + * which defined in arch/arm/mach-imx/pm-imx7.c, this + * structure contains necessary pm info for low level + * suspend related code. + */ +#define PM_INFO_M4_RESERVE0_OFFSET 0x0 +#define PM_INFO_M4_RESERVE1_OFFSET 0x4 +#define PM_INFO_M4_RESERVE2_OFFSET 0x8 +#define PM_INFO_PBASE_OFFSET 0xc +#define PM_INFO_RESUME_ADDR_OFFSET 0x10 +#define PM_INFO_DDR_TYPE_OFFSET 0x14 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x18 +#define PM_INFO_MX7_DDRC_P_OFFSET 0x1c +#define PM_INFO_MX7_DDRC_V_OFFSET 0x20 +#define PM_INFO_MX7_DDRC_PHY_P_OFFSET 0x24 +#define PM_INFO_MX7_DDRC_PHY_V_OFFSET 0x28 +#define PM_INFO_MX7_SRC_P_OFFSET 0x2c +#define PM_INFO_MX7_SRC_V_OFFSET 0x30 +#define PM_INFO_MX7_IOMUXC_GPR_P_OFFSET 0x34 +#define PM_INFO_MX7_IOMUXC_GPR_V_OFFSET 0x38 +#define PM_INFO_MX7_CCM_P_OFFSET 0x3c +#define PM_INFO_MX7_CCM_V_OFFSET 0x40 +#define PM_INFO_MX7_GPC_P_OFFSET 0x44 +#define PM_INFO_MX7_GPC_V_OFFSET 0x48 +#define PM_INFO_MX7_SNVS_P_OFFSET 0x4c +#define PM_INFO_MX7_SNVS_V_OFFSET 0x50 +#define PM_INFO_MX7_ANATOP_P_OFFSET 0x54 +#define PM_INFO_MX7_ANATOP_V_OFFSET 0x58 +#define PM_INFO_MX7_LPSR_P_OFFSET 0x5c +#define PM_INFO_MX7_LPSR_V_OFFSET 0x60 +#define PM_INFO_MX7_GIC_DIST_P_OFFSET 0x64 +#define PM_INFO_MX7_GIC_DIST_V_OFFSET 0x68 +#define PM_INFO_MX7_TTBR1_V_OFFSET 0x6c +#define PM_INFO_DDRC_REG_NUM_OFFSET 0x70 +#define PM_INFO_DDRC_REG_OFFSET 0x74 +#define PM_INFO_DDRC_VALUE_OFFSET 0x78 +#define PM_INFO_DDRC_PHY_REG_NUM_OFFSET 0x174 +#define PM_INFO_DDRC_PHY_REG_OFFSET 0x178 +#define PM_INFO_DDRC_PHY_VALUE_OFFSET 0x17c + +#define MX7_SRC_GPR1 0x74 +#define MX7_SRC_GPR2 0x78 +#define GPC_PGC_C0 0x800 +#define GPC_PGC_FM 0xa00 +#define ANADIG_SNVS_MISC_CTRL 0x380 +#define ANADIG_SNVS_MISC_CTRL_SET 0x384 +#define ANADIG_SNVS_MISC_CTRL_CLR 0x388 +#define ANADIG_DIGPROG 0x800 +#define DDRC_STAT 0x4 +#define DDRC_PWRCTL 0x30 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCTRL_0 0x490 +#define DDRC_DFIMISC 0x1b0 +#define DDRC_SWCTL 0x320 +#define DDRC_SWSTAT 0x324 +#define DDRPHY_LP_CON0 0x18 + +#define CCM_SNVS_LPCG 0x250 +#define MX7D_GPC_IMR1 0x30 +#define MX7D_GPC_IMR2 0x34 +#define MX7D_GPC_IMR3 0x38 +#define MX7D_GPC_IMR4 0x3c + + .align 3 + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro store_ttbr1 + + /* Store TTBR1 to pm_info->ttbr1 */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_MX7_TTBR1_V_OFFSET] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r6, [r6] + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r6, c2, c0, 1 + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro restore_ttbr1 + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Restore TTBCR */ + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Restore TTBR1, get the origin ttbr1 from pm info */ + ldr r7, [r0, #PM_INFO_MX7_TTBR1_V_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + .macro ddrc_enter_self_refresh + + ldr r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r11, #DDRC_PWRCTL] + + /* wait rw port_busy clear */ + ldr r6, =(0x1 << 16) + orr r6, r6, #0x1 +1: + ldr r7, [r11, #DDRC_PSTAT] + ands r7, r7, r6 + bne 1b + + /* enter self-refresh bit 5 */ + ldr r7, =(0x1 << 5) + str r7, [r11, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +2: + ldr r7, [r11, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 2b +3: + ldr r7, [r11, #DDRC_STAT] + ands r7, r7, #0x20 + beq 3b + + /* disable dram clk */ + ldr r7, [r11, #DDRC_PWRCTL] + orr r7, r7, #(1 << 3) + str r7, [r11, #DDRC_PWRCTL] + + .endm + + .macro ddrc_exit_self_refresh + + cmp r5, #0x0 + ldreq r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX7_DDRC_P_OFFSET] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r11, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +4: + ldr r7, [r11, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + beq 4b + + /* enable auto self-refresh */ + ldr r7, [r11, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r11, #DDRC_PWRCTL] + + .endm + + .macro wait_delay +5: + subs r6, r6, #0x1 + bne 5b + + .endm + + .macro ddr_enter_retention + + ldr r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r11, #DDRC_PCTRL_0] + + /* wait rw port_busy clear */ + ldr r6, =(0x1 << 16) + orr r6, r6, #0x1 +6: + ldr r7, [r11, #DDRC_PSTAT] + ands r7, r7, r6 + bne 6b + + ldr r11, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + /* enter self-refresh bit 5 */ + ldr r7, =(0x1 << 5) + str r7, [r11, #DDRC_PWRCTL] + + /* wait until self-refresh mode entered */ +7: + ldr r7, [r11, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 7b +8: + ldr r7, [r11, #DDRC_STAT] + ands r7, r7, #0x20 + beq 8b + + /* disable dram clk */ + ldr r7, =(0x1 << 5) + orr r7, r7, #(1 << 3) + str r7, [r11, #DDRC_PWRCTL] + + ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldr r7, [r11, #ANADIG_DIGPROG] + and r7, r7, #0xff + cmp r7, #0x11 + bne 10f + + /* TO 1.1 */ + ldr r11, [r0, #PM_INFO_MX7_IOMUXC_GPR_V_OFFSET] + ldr r7, =0x38000000 + str r7, [r11] + + /* LPSR mode need to use TO1.0 flow as IOMUX lost power */ + ldr r10, [r0, #PM_INFO_MX7_LPSR_V_OFFSET] + ldr r7, [r10] + cmp r7, #0x0 + beq 11f +10: + /* reset ddr_phy */ + ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldr r7, =0x0 + str r7, [r11, #ANADIG_SNVS_MISC_CTRL] + + /* delay 7 us */ + ldr r6, =6000 + wait_delay + + ldr r11, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + ldr r6, =0x1000 + ldr r7, [r11, r6] + orr r7, r7, #0x1 + str r7, [r11, r6] +11: + /* turn off ddr power */ + ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldr r7, =(0x1 << 29) + str r7, [r11, #ANADIG_SNVS_MISC_CTRL_SET] + + ldr r11, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + ldr r6, =0x1000 + ldr r7, [r11, r6] + orr r7, r7, #0x1 + str r7, [r11, r6] + + .endm + + .macro ddr_exit_retention + + cmp r5, #0x0 + ldreq r1, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] + ldrne r1, [r0, #PM_INFO_MX7_ANATOP_P_OFFSET] + ldreq r2, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + ldrne r2, [r0, #PM_INFO_MX7_SRC_P_OFFSET] + ldreq r3, [r0, #PM_INFO_MX7_DDRC_V_OFFSET] + ldrne r3, [r0, #PM_INFO_MX7_DDRC_P_OFFSET] + ldreq r4, [r0, #PM_INFO_MX7_DDRC_PHY_V_OFFSET] + ldrne r4, [r0, #PM_INFO_MX7_DDRC_PHY_P_OFFSET] + ldreq r10, [r0, #PM_INFO_MX7_CCM_V_OFFSET] + ldrne r10, [r0, #PM_INFO_MX7_CCM_P_OFFSET] + ldreq r11, [r0, #PM_INFO_MX7_IOMUXC_GPR_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX7_IOMUXC_GPR_P_OFFSET] + + /* turn on ddr power */ + ldr r7, =(0x1 << 29) + str r7, [r1, #ANADIG_SNVS_MISC_CTRL_CLR] + + ldr r6, =50 + wait_delay + + /* clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + orr r7, r7, #0x3 + str r7, [r2, r6] + ldr r7, [r2, r6] + bic r7, r7, #0x1 + str r7, [r2, r6] +13: + ldr r6, [r0, #PM_INFO_DDRC_REG_NUM_OFFSET] + ldr r7, =PM_INFO_DDRC_REG_OFFSET + add r7, r7, r0 +14: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r3, r8] + subs r6, r6, #0x1 + bne 14b + ldr r7, =0x20 + str r7, [r3, #DDRC_PWRCTL] + ldr r7, =0x0 + str r7, [r3, #DDRC_DFIMISC] + + /* do PHY, clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + bic r7, r7, #0x2 + str r7, [r2, r6] + + ldr r7, [r1, #ANADIG_DIGPROG] + and r7, r7, #0xff + cmp r7, #0x11 + bne 12f + + /* + * TKT262940: + * System hang when press RST for DDR PAD is + * in retention mode, fixed on TO1.1 + */ + ldr r7, [r11] + bic r7, r7, #(1 << 27) + str r7, [r11] + ldr r7, [r11] + bic r7, r7, #(1 << 29) + str r7, [r11] +12: + ldr r7, =(0x1 << 30) + str r7, [r1, #ANADIG_SNVS_MISC_CTRL_SET] + + /* need to delay ~5mS */ + ldr r6, =0x100000 + wait_delay + + ldr r6, [r0, #PM_INFO_DDRC_PHY_REG_NUM_OFFSET] + ldr r7, =PM_INFO_DDRC_PHY_REG_OFFSET + add r7, r7, r0 + +15: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r4, r8] + subs r6, r6, #0x1 + bne 15b + + ldr r7, =0x0 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0x170 + orr r7, r7, #0x8 + str r7, [r11, #0x20] + + ldr r7, =0x2 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0xf + str r7, [r4, #DDRPHY_LP_CON0] + + /* wait until self-refresh mode entered */ +16: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 16b + ldr r7, =0x0 + str r7, [r3, #DDRC_SWCTL] + ldr r7, =0x1 + str r7, [r3, #DDRC_DFIMISC] + ldr r7, =0x1 + str r7, [r3, #DDRC_SWCTL] +17: + ldr r7, [r3, #DDRC_SWSTAT] + and r7, r7, #0x1 + cmp r7, #0x1 + bne 17b +18: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x20 + cmp r7, #0x20 + bne 18b + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r3, #DDRC_PWRCTL] +19: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x30 + cmp r7, #0x0 + bne 19b + +20: + ldr r7, [r3, #DDRC_STAT] + and r7, r7, #0x3 + cmp r7, #0x1 + bne 20b + + /* enable port */ + ldr r7, =0x1 + str r7, [r3, #DDRC_PCTRL_0] + + /* enable auto self-refresh */ + ldr r7, [r3, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r3, #DDRC_PWRCTL] + + .endm + +ENTRY(imx7_suspend) + push {r4-r12} + + /* make sure SNVS clk is enabled */ + ldr r11, [r0, #PM_INFO_MX7_CCM_V_OFFSET] + add r11, r11, #0x4000 + ldr r7, =0x3 + str r7, [r11, #CCM_SNVS_LPCG] + + /* check whether it is a standby mode */ + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_C0] + cmp r7, #0 + beq ddr_only_self_refresh + + /* + * The value of r0 is mapped the same in origin table and IRAM table, + * thus no need to care r0 here. + */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET] + ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r6, =imx7_suspend + ldr r7, =resume + sub r7, r7, r6 + add r8, r1, r4 + add r9, r8, r7 + + ldr r11, [r0, #PM_INFO_MX7_SRC_V_OFFSET] + /* store physical resume addr and pm_info address. */ + str r9, [r11, #MX7_SRC_GPR1] + str r1, [r11, #MX7_SRC_GPR2] + + disable_l1_dcache + + store_ttbr1 + + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_FM] + cmp r7, #0 + beq ddr_only_self_refresh + + ddr_enter_retention + /* enter LPSR mode if resume addr is valid */ + ldr r11, [r0, #PM_INFO_MX7_LPSR_V_OFFSET] + ldr r7, [r11] + cmp r7, #0x0 + beq ddr_retention_enter_out + + /* disable STOP mode before entering LPSR */ + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11] + bic r7, #0xf + str r7, [r11] + + /* shut down vddsoc to enter lpsr mode */ + ldr r11, [r0, #PM_INFO_MX7_SNVS_V_OFFSET] + ldr r7, [r11, #0x38] + orr r7, r7, #0x60 + str r7, [r11, #0x38] +wait_shutdown: + wfi + nop + nop + nop + nop + b wait_shutdown + +ddr_only_self_refresh: + ddrc_enter_self_refresh + b wfi +ddr_retention_enter_out: + + ldr r11, [r0, #PM_INFO_MX7_GIC_DIST_V_OFFSET] + ldr r7, =0x0 + ldr r8, =0x1000 + str r7, [r11, r8] + + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r4, [r11, #MX7D_GPC_IMR1] + ldr r5, [r11, #MX7D_GPC_IMR2] + ldr r6, [r11, #MX7D_GPC_IMR3] + ldr r7, [r11, #MX7D_GPC_IMR4] + + ldr r8, =0xffffffff + str r8, [r11, #MX7D_GPC_IMR1] + str r8, [r11, #MX7D_GPC_IMR2] + str r8, [r11, #MX7D_GPC_IMR3] + str r8, [r11, #MX7D_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 0x3f (2ms). With this setting, the latency + * from wakeup interrupt to ARM power up + * is ~2ms. + */ + ldr r8, [r11, #0x14] + orr r8, r8, #(0x3f << 24) + str r8, [r11, #0x14] + + /* enable the counter. */ + ldr r8, [r11, #0x14] + orr r8, r8, #(0x1 << 30) + str r8, [r11, #0x14] + + /* unmask all the GPC interrupts. */ + str r4, [r11, #MX7D_GPC_IMR1] + str r5, [r11, #MX7D_GPC_IMR2] + str r6, [r11, #MX7D_GPC_IMR3] + str r7, [r11, #MX7D_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 1GHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r7, =2000 +rbc_loop: + subs r7, r7, #0x1 + bne rbc_loop +wfi: + /* Zzz, enter stop mode */ + wfi + nop + nop + nop + nop + + mov r5, #0x0 + + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_FM] + cmp r7, #0 + beq wfi_ddr_self_refresh_out + + ddr_exit_retention + b wfi_ddr_retention_out +wfi_ddr_self_refresh_out: + ddrc_exit_self_refresh +wfi_ddr_retention_out: + + /* check whether it is a standby mode */ + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11, #GPC_PGC_C0] + cmp r7, #0 + beq standby_out + + ldr r11, [r0, #PM_INFO_MX7_GIC_DIST_V_OFFSET] + ldr r7, =0x1 + ldr r8, =0x1000 + str r7, [r11, r8] + + restore_ttbr1 +standby_out: + pop {r4-r12} + /* return to suspend finish */ + mov pc, lr + +resume: + /* invalidate L1 I-cache first */ + mov r6, #0x0 + mcr p15, 0, r6, c7, c5, 0 + mcr p15, 0, r6, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r6, #0x1800 + mcr p15, 0, r6, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r11, [r0, #PM_INFO_MX7_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r11, #MX7_SRC_GPR1] + str r7, [r11, #MX7_SRC_GPR2] + + mov r5, #0x1 + + ldr r11, [r0, #PM_INFO_MX7_GPC_P_OFFSET] + ldr r7, [r11, #GPC_PGC_FM] + cmp r7, #0 + beq dsm_ddr_self_refresh_out + + ddr_exit_retention + b dsm_ddr_retention_out +dsm_ddr_self_refresh_out: + ddrc_exit_self_refresh +dsm_ddr_retention_out: + + mov pc, lr +ENDPROC(imx7_suspend) + +ENTRY(ca7_cpu_resume) + bl v7_invalidate_l1 + b cpu_resume +ENDPROC(ca7_cpu_resume) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mach-imx/suspend-imx7ulp.S linux-imx-phytec/arch/arm/mach-imx/suspend-imx7ulp.S --- linux-6.1.55/arch/arm/mach-imx/suspend-imx7ulp.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm/mach-imx/suspend-imx7ulp.S 2024-06-19 12:33:58.136189762 +0200 @@ -0,0 +1,625 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include "hardware.h" + +/* + * ==================== low level suspend ==================== + * + * Better to follow below rules to use ARM registers: + * r0: pm_info structure address; + * + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx7ulp_suspend code + * PM_INFO structure(imx7ulp_cpu_pm_info) + * ======================== low address ======================= + */ + +/* + * Below offsets are based on struct imx7ulp_cpu_pm_info + * which defined in arch/arm/mach-imx/pm-imx7ulp.c, this + * structure contains necessary pm info for low level + * suspend related code. + */ +#define PM_INFO_M4_RESERVE0_OFFSET 0x0 +#define PM_INFO_M4_RESERVE1_OFFSET 0x4 +#define PM_INFO_M4_RESERVE2_OFFSET 0x8 +#define PM_INFO_PBASE_OFFSET 0xc +#define PM_INFO_RESUME_ADDR_OFFSET 0x10 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0x14 +#define PM_INFO_PM_INFO_SIM_VBASE_OFFSET 0x18 +#define PM_INFO_PM_INFO_SCG1_VBASE_OFFSET 0x1c +#define PM_INFO_PM_INFO_MMDC_VBASE_OFFSET 0x20 +#define PM_INFO_PM_INFO_MMDC_IO_VBASE_OFFSET 0x24 +#define PM_INFO_PM_INFO_SMC1_VBASE_OFFSET 0x28 +#define PM_INFO_PM_INFO_SCG1_VAL_OFFSET 0x2c +#define PM_INFO_MX7ULP_TTBR1_V_OFFSET 0x70 +#define PM_INFO_MX7ULP_GPIO_REG_OFFSET 0x74 +#define PM_INFO_IOMUX_NUM_OFFSET 0x94 +#define PM_INFO_IOMUX_VAL_OFFSET 0x98 +#define PM_INFO_SELECT_INPUT_NUM_OFFSET 0x268 +#define PM_INFO_SELECT_INPUT_VAL_OFFSET 0x26c +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x3a4 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x3a8 +/* below offsets depends on MX7ULP_MAX_MMDC_IO_NUM(36) definition */ +#define PM_INFO_MMDC_NUM_OFFSET 0x5a8 +#define PM_INFO_MMDC_VAL_OFFSET 0x5ac + +#define DGO_CTRL0 0x50 +#define DGO_GPR3 0x60 +#define DGO_GPR4 0x64 + +#define MX7ULP_MMDC_MISC 0x18 +#define MX7ULP_MMDC_MAPSR 0x404 +#define MX7ULP_MMDC_MPDGCTRL0 0x83c + +#define SCG_RCCR 0x14 +#define SCG_DDRCCR 0x30 +#define SCG_NICCCR 0x40 +#define SCG_FIRCDIV 0x304 +#define SCG_APLLCSR 0x500 +#define SCG_APLLDIV 0x504 +#define SCG_APLLCFG 0x508 +#define SCG_APLLPFD 0x50c +#define SCG_APLLNUM 0x510 +#define SCG_APLLDENOM 0x514 +#define SCG_SPLLCSR 0x600 +#define SCG_SPLLDIV 0x604 +#define SCG_SPLLCFG 0x608 +#define SCG_SPLLPFD 0x60c +#define SCG_SPLLNUM 0x610 +#define SCG_SPLLDENOM 0x614 +#define SCG_SOSCDIV 0x104 + +#define PMC1_CTRL 0x24 + +#define GPIO_PDOR 0x0 +#define GPIO_PDDR 0x14 +#define GPIO_PORT_NUM 0x4 +#define GPIO_PORT_OFFSET 0x40 + +#define PMCTRL 0x10 + +#define IOMUX_OFFSET 0x0 +#define SELECT_INPUT_OFFSET 0x200 + + .align 3 + + .macro store_ttbr1 + + /* Store TTBR1 to pm_info->ttbr1 */ + mrc p15, 0, r7, c2, c0, 1 + str r7, [r0, #PM_INFO_MX7ULP_TTBR1_V_OFFSET] + + /* Disable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + bic r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the BTAC. */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + ldr r6, =iram_tlb_phys_addr + ldr r6, [r6] + dsb + isb + + /* Store the IRAM table in TTBR1 */ + mcr p15, 0, r6, c2, c0, 1 + /* Read TTBCR and set PD0=1, N = 1 */ + mrc p15, 0, r6, c2, c0, 2 + orr r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + .endm + + .macro restore_ttbr1 + + /* Enable L1 data cache. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x4 + mcr p15, 0, r6, c1, c0, 0 + + dsb + isb + + /* Restore TTBCR */ + /* Read TTBCR and set PD0=0, N = 0 */ + mrc p15, 0, r6, c2, c0, 2 + bic r6, r6, #0x11 + mcr p15, 0, r6, c2, c0, 2 + dsb + isb + + /* flush the TLB */ + ldr r6, =0x0 + mcr p15, 0, r6, c8, c3, 0 + + /* Enable Branch Prediction, Z bit in SCTLR. */ + mrc p15, 0, r6, c1, c0, 0 + orr r6, r6, #0x800 + mcr p15, 0, r6, c1, c0, 0 + + /* Flush the Branch Target Address Cache (BTAC) */ + ldr r6, =0x0 + mcr p15, 0, r6, c7, c1, 6 + + /* Restore TTBR1, get the origin ttbr1 from pm info */ + ldr r7, [r0, #PM_INFO_MX7ULP_TTBR1_V_OFFSET] + mcr p15, 0, r7, c2, c0, 1 + + .endm + + .macro disable_l1_dcache + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + /* disable d-cache */ + mrc p15, 0, r7, c1, c0, 0 + bic r7, r7, #(1 << 2) + mcr p15, 0, r7, c1, c0, 0 + dsb + isb + + push {r0 - r10, lr} + ldr r7, =v7_flush_dcache_all + mov lr, pc + mov pc, r7 + pop {r0 - r10, lr} + + .endm + + .macro restore_mmdc_settings + + ldr r10, =MX7ULP_MMDC_IO_BASE_ADDR + ldr r11, =MX7ULP_MMDC_BASE_ADDR + + /* resume mmdc iomuxc settings */ + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +11: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r10, r8] + subs r6, r6, #0x1 + bne 11b + + /* restore MMDC settings */ + ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_VAL_OFFSET + add r7, r7, r0 +1: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r11, r8] + subs r6, r6, #0x1 + bne 1b + + /* let DDR enter self-refresh */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + orr r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +2: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + beq 2b + + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +3: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne 3b + + /* kick off MMDC */ + ldr r4, =0x0 + str r4, [r11, #0x1c] + + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +4: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne 4b + + /* enable DDR auto power saving */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r11, #MX7ULP_MMDC_MAPSR] + + .endm + +ENTRY(imx7ulp_suspend) + push {r4-r12} + + /* + * The value of r0 is mapped the same in origin table and IRAM table, + * thus no need to care r0 here. + */ + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + ldr r3, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r6, =imx7ulp_suspend + ldr r7, =resume + sub r7, r7, r6 + add r8, r1, r3 + add r9, r8, r7 + + ldr r11, [r0, #PM_INFO_PM_INFO_SIM_VBASE_OFFSET] + /* store physical resume addr and pm_info address. */ + str r9, [r11, #DGO_GPR3] + str r1, [r11, #DGO_GPR4] + ldr r7, [r11, #DGO_CTRL0] + orr r7, r7, #0xc + str r7, [r11, #DGO_CTRL0] +wait_dgo: + ldr r7, [r11, #DGO_CTRL0] + and r7, r7, #0x18000 + cmp r7, #0x18000 + bne wait_dgo + + ldr r7, [r11, #DGO_CTRL0] + orr r7, r7, #0x18000 + bic r7, r7, #0xc + str r7, [r11, #DGO_CTRL0] + + disable_l1_dcache + + store_ttbr1 + + ldr r11, [r0, #PM_INFO_PM_INFO_MMDC_VBASE_OFFSET] + + /* + * put DDR explicitly into self-refresh and + * disable automatic power savings. + */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r11, #MX7ULP_MMDC_MAPSR] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + orr r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] + +poll_dvfs_set: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + beq poll_dvfs_set + + /* put mmdc io into lpm */ + ldr r11, [r0, #PM_INFO_PM_INFO_MMDC_IO_VBASE_OFFSET] + ldr r10, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +mmdc_io_lpm: + ldr r8, [r7], #0x8 + mov r9, #0x0 + str r9, [r11, r8] + subs r10, r10, #0x1 + bne mmdc_io_lpm + + /* switch NIC clock to FIRC */ + ldr r10, [r0, #PM_INFO_PM_INFO_SCG1_VBASE_OFFSET] + ldr r7, [r10, #SCG_NICCCR] + bic r7, #(1 << 28) + str r7, [r10, #SCG_NICCCR] + + /* switch RUN clock to FIRC */ + ldr r7, [r10, #SCG_RCCR] + bic r7, #(0xf << 24) + orr r7, #(0x3 << 24) + str r7, [r10, #SCG_RCCR] + + /* turn off SPLL and SPFD */ + ldr r7, [r10, #SCG_SPLLPFD] + mov r8, r7 + orr r7, r7, #(0x1 << 31) + orr r7, r7, #(0x1 << 23) + orr r7, r7, #(0x1 << 15) + orr r7, r7, #(0x1 << 7) + str r7, [r10, #SCG_SPLLPFD] + + ldr r7, [r10, #SCG_SPLLCSR] + bic r7, r7, #0x1 + str r7, [r10, #SCG_SPLLCSR] + + /* turn off APLL and APFD */ + ldr r7, [r10, #SCG_APLLPFD] + mov r9, r7 + orr r7, r7, #(0x1 << 31) + orr r7, r7, #(0x1 << 23) + orr r7, r7, #(0x1 << 15) + orr r7, r7, #(0x1 << 7) + str r7, [r10, #SCG_APLLPFD] + + ldr r7, [r10, #SCG_APLLCSR] + bic r7, r7, #0x1 + str r7, [r10, #SCG_APLLCSR] + + /* Zzz, enter stop mode */ + wfi + nop + nop + nop + nop + + /* clear core0's entry and parameter */ + ldr r10, [r0, #PM_INFO_PM_INFO_SIM_VBASE_OFFSET] + mov r7, #0x0 + str r7, [r10, #DGO_GPR3] + str r7, [r10, #DGO_GPR4] + + /* enable SPLL and SPFD */ + ldr r10, [r0, #PM_INFO_PM_INFO_SCG1_VBASE_OFFSET] + ldr r7, [r10, #SCG_SPLLCSR] + orr r7, r7, #1 + str r7, [r10, #SCG_SPLLCSR] +wait_spll: + ldr r7, [r10, #SCG_SPLLCSR] + ands r7, r7, #(1 << 24) + beq wait_spll + + str r8, [r10, #SCG_SPLLPFD] + /* switch RUN clock to SPLL */ + ldr r7, [r10, #SCG_RCCR] + bic r7, #(0xf << 24) + orr r7, #(0x6 << 24) + str r7, [r10, #SCG_RCCR] + + /* enable APLL and APFD */ + ldr r7, [r10, #SCG_APLLCSR] + orr r7, r7, #1 + str r7, [r10, #SCG_APLLCSR] +wait_apll: + ldr r7, [r10, #SCG_APLLCSR] + ands r7, r7, #(1 << 24) + beq wait_apll + + str r9, [r10, #SCG_APLLPFD] + + /* switch NIC clock to DDR */ + ldr r7, [r10, #SCG_NICCCR] + orr r7, #(1 << 28) + str r7, [r10, #SCG_NICCCR] + + /* let mmdc io out of lpm */ + ldr r11, [r0, #PM_INFO_PM_INFO_MMDC_IO_VBASE_OFFSET] + ldr r10, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +mmdc_io_exit_lpm: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r11, r8] + subs r10, r10, #0x1 + bne mmdc_io_exit_lpm + + /* let DDR out of self-refresh */ + ldr r11, [r0, #PM_INFO_PM_INFO_MMDC_VBASE_OFFSET] + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #(1 << 20) + str r7, [r11, #MX7ULP_MMDC_MAPSR] +poll_dvfs_clear: + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + ands r7, r7, #(1 << 24) + bne poll_dvfs_clear + + /* enable DDR auto power saving */ + ldr r7, [r11, #MX7ULP_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r11, #MX7ULP_MMDC_MAPSR] + + restore_ttbr1 + pop {r4-r12} + /* return to suspend finish */ + mov pc, lr + +resume: + /* invalidate L1 I-cache first */ + mov r6, #0x0 + mcr p15, 0, r6, c7, c5, 0 + mcr p15, 0, r6, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r6, #0x1800 + mcr p15, 0, r6, c1, c0, 0 + isb + + ldr r6, =MX7ULP_SIM_BASE_ADDR + ldr r0, [r6, #DGO_GPR4] + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + + ldr r11, =MX7ULP_SCG1_BASE_ADDR + /* enable spll and pfd0 */ + ldr r5, =PM_INFO_PM_INFO_SCG1_VAL_OFFSET + add r6, r5, #48 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLCFG] + + add r6, r5, #56 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLNUM] + + add r6, r5, #60 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLDENOM] + + add r6, r5, #40 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLCSR] +5: + ldr r7, [r11, #SCG_SPLLCSR] + ands r7, r7, #0x1000000 + beq 5b + + add r6, r5, #44 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLDIV] + + add r6, r5, #52 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SPLLPFD] + + add r6, r5, #0 + ldr r7, [r0, r6] + str r7, [r11, #SCG_RCCR] + + /* enable apll and pfd0 */ + add r6, r5, #24 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLCFG] + + add r6, r5, #32 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLNUM] + + add r6, r5, #36 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLDENOM] + + add r6, r5, #16 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLCSR] +6: + ldr r7, [r11, #SCG_APLLCSR] + ands r7, r7, #0x1000000 + beq 6b + + add r6, r5, #20 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLDIV] + + add r6, r5, #28 + ldr r7, [r0, r6] + str r7, [r11, #SCG_APLLPFD] + + /* set ddr ccr */ + add r6, r5, #4 + ldr r7, [r0, r6] + str r7, [r11, #SCG_DDRCCR] + + /* set nic sel */ + add r6, r5, #8 + ldr r7, [r0, r6] + str r7, [r11, #SCG_NICCCR] + + /* set firc div2 to get 48MHz */ + add r6, r5, #12 + ldr r7, [r0, r6] + str r7, [r11, #SCG_FIRCDIV] + + /* restore system OSC div */ + add r6, r5, #64 + ldr r7, [r0, r6] + str r7, [r11, #SCG_SOSCDIV] + + /* enable mmdc clock in pcc3 */ + ldr r11, =MX7ULP_PCC3_BASE_ADDR + ldr r7, [r11, #0xac] + orr r7, r7, #(1 << 30) + str r7, [r11, #0xac] + + /* enable GPIO clock in pcc2 */ + ldr r11, =MX7ULP_PCC2_BASE_ADDR + ldr r7, [r11, #0x3c] + orr r7, r7, #(1 << 30) + str r7, [r11, #0x3c] + + /* restore gpio settings */ + ldr r10, =MX7ULP_GPIOC_BASE_ADDR + ldr r7, =PM_INFO_MX7ULP_GPIO_REG_OFFSET + add r7, r7, r0 + ldr r6, =GPIO_PORT_NUM +12: + ldr r9, [r7], #0x4 + str r9, [r10, #GPIO_PDOR] + ldr r9, [r7], #0x4 + str r9, [r10, #GPIO_PDDR] + add r10, r10, #GPIO_PORT_OFFSET + subs r6, r6, #0x1 + bne 12b + + /* restore iomuxc settings */ + ldr r10, =MX7ULP_IOMUXC1_BASE_ADDR + add r10, r10, #IOMUX_OFFSET + ldr r6, [r0, #PM_INFO_IOMUX_NUM_OFFSET] + ldr r7, =PM_INFO_IOMUX_VAL_OFFSET + add r7, r7, r0 +13: + ldr r9, [r7], #0x4 + str r9, [r10], #0x4 + subs r6, r6, #0x1 + bne 13b + + /* restore select input settings */ + ldr r10, =MX7ULP_IOMUXC1_BASE_ADDR + add r10, r10, #SELECT_INPUT_OFFSET + ldr r6, [r0, #PM_INFO_SELECT_INPUT_NUM_OFFSET] + ldr r7, =PM_INFO_SELECT_INPUT_VAL_OFFSET + add r7, r7, r0 +14: + ldr r9, [r7], #0x4 + str r9, [r10], #0x4 + subs r6, r6, #0x1 + bne 14b + + /* isoack */ + ldr r6, =MX7ULP_PMC1_BASE_ADDR + ldr r7, [r6, #PMC1_CTRL] + orr r7, r7, #(1 << 14) + str r7, [r6, #PMC1_CTRL] + + restore_mmdc_settings + + mov pc, lr +ENDPROC(imx7ulp_suspend) + +ENTRY(imx7ulp_cpu_resume) + bl v7_invalidate_l1 + b cpu_resume +ENDPROC(imx7ulp_cpu_resume) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mm/cache-l2x0.c linux-imx-phytec/arch/arm/mm/cache-l2x0.c --- linux-6.1.55/arch/arm/mm/cache-l2x0.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mm/cache-l2x0.c 2024-06-19 12:33:58.224191266 +0200 @@ -867,6 +867,11 @@ l2x0_saved_regs.aux_ctrl = aux; data->enable(l2x0_base, data->num_lock); + } else { + pr_info("%s cache controller enabled try to unlock\n", + data->type); + + data->unlock(l2x0_base, data->num_lock); } outer_cache = fns; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mm/dma-mapping.c linux-imx-phytec/arch/arm/mm/dma-mapping.c --- linux-6.1.55/arch/arm/mm/dma-mapping.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mm/dma-mapping.c 2024-06-19 12:33:58.228191335 +0200 @@ -1792,6 +1792,7 @@ xen_setup_dma_ops(dev); dev->archdata.dma_ops_setup = true; } +EXPORT_SYMBOL(arch_setup_dma_ops); void arch_teardown_dma_ops(struct device *dev) { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mm/ioremap.c linux-imx-phytec/arch/arm/mm/ioremap.c --- linux-6.1.55/arch/arm/mm/ioremap.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mm/ioremap.c 2024-06-19 12:33:58.228191335 +0200 @@ -385,6 +385,13 @@ } EXPORT_SYMBOL(ioremap_wc); +void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size) +{ + return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(ioremap_cache_ns); + /* * Remap an arbitrary physical address space into the kernel virtual * address space as memory. Needed when the kernel wants to execute diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm/mm/mmu.c linux-imx-phytec/arch/arm/mm/mmu.c --- linux-6.1.55/arch/arm/mm/mmu.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm/mm/mmu.c 2024-06-19 12:33:58.228191335 +0200 @@ -307,6 +307,13 @@ #endif .domain = DOMAIN_KERNEL, }, + [MT_MEMORY_RW_NS] = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_XN, + .prot_l1 = PMD_TYPE_TABLE, + .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN, + .domain = DOMAIN_KERNEL, + }, [MT_ROM] = { .prot_sect = PMD_TYPE_SECT, .domain = DOMAIN_KERNEL, @@ -657,6 +664,7 @@ } kern_pgprot |= PTE_EXT_AF; vecs_pgprot |= PTE_EXT_AF; + mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte; /* * Set PXN for user mappings @@ -682,6 +690,7 @@ mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; + mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd; mem_types[MT_MEMORY_RO].prot_sect |= ecc_mask | cp->pmd; mem_types[MT_MEMORY_RO].prot_pte |= kern_pgprot; mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts 2024-06-19 12:33:58.268192018 +0200 @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NXP LS1012A 2G5RDB Board. + * + * Copyright 2017 NXP + * + * Bhaskar Upadhaya + */ +/dts-v1/; + +#include "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A 2G5RDB Board"; + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; + + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + mmc0 = &esdhc0; + mmc1 = &esdhc1; + }; +}; + +&duart0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi { + num-cs = <2>; + bus-num = <0>; + status = "okay"; + + qflash0: s25fs512s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + m25p,fast-read; + reg = <0>; + }; +}; + +&sata { + status = "okay"; +}; + +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + sgmii_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi 2024-06-19 12:33:58.272192087 +0200 @@ -290,7 +290,7 @@ dcfg: dcfg@1ee0000 { compatible = "fsl,ls1012a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; @@ -351,24 +351,26 @@ }; i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; + scl-gpios = <&gpio0 2 0>; status = "disabled"; }; i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; + scl-gpios = <&gpio0 13 0>; status = "disabled"; }; @@ -492,13 +494,15 @@ }; usb0: usb@2f00000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1012a-dwc3", "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = <0 60 0x4>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; }; sata: sata@3200000 { @@ -550,6 +554,7 @@ <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + big-endian; status = "disabled"; }; @@ -568,6 +573,35 @@ }; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pfe_reserved: packetbuffer@83400000 { + reg = <0 0x83400000 0 0xc00000>; + }; + }; + + pfe: pfe@4000000 { + compatible = "fsl,pfe"; + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ + reg-names = "pfe", "pfe-ddr"; + fsl,pfe-num-interfaces = <0x2>; + interrupts = <0 172 0x4>, /* HIF interrupt */ + <0 173 0x4>, /*HIF_NOCPY interrupt */ + <0 174 0x4>; /* WoL interrupt */ + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; + memory-region = <&pfe_reserved>; + fsl,pfe-scfg = <&scfg 0>; + fsl,rcpm-wakeup = <&rcpm 0xf0000020>; + clocks = <&clockgen 4 0>; + clock-names = "pfe"; + + status = "okay"; + }; + firmware { optee { compatible = "linaro,optee-tz"; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts 2024-06-19 12:33:58.272192087 +0200 @@ -14,6 +14,11 @@ model = "LS1012A Freedom Board"; compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + }; + sys_mclk: clock-mclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -110,6 +115,45 @@ }; }; +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; + &sai2 { status = "okay"; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts 2024-06-19 12:33:58.272192087 +0200 @@ -14,6 +14,60 @@ / { model = "LS1012A FRWY Board"; compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; + + aliases { + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; + mmc0 = &esdhc0; + mmc1 = &esdhc1; + }; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + frame-master; + bitclock-master; + system-clock-frequency = <25000000>; + }; + }; +}; + +&pcie1 { + status = "okay"; }; &duart0 { @@ -22,6 +76,74 @@ &i2c0 { status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0xa>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_1p8v>; + clocks = <&sys_mclk>; + }; +}; + +&qspi { + num-cs = <1>; + bus-num = <0>; + status = "okay"; + + qflash0: w25q16dw@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,gemac-bus-id = <0x0>; /* BUS_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; + +&sai2 { + status = "okay"; }; &pcie1 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts 2024-06-19 12:33:58.272192087 +0200 @@ -16,6 +16,8 @@ aliases { mmc0 = &esdhc0; mmc1 = &esdhc1; + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; }; sys_mclk: clock-mclk { @@ -148,6 +150,47 @@ }; }; +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x2>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy1>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x3>; + phy-mode = "sgmii-2500"; + phy-handle = <&sgmii_phy2>; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + sgmii_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + }; +}; + &sai2 { status = "okay"; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts 2024-06-19 12:33:58.272192087 +0200 @@ -18,6 +18,8 @@ serial0 = &duart0; mmc0 = &esdhc0; mmc1 = &esdhc1; + ethernet0 = &pfe_mac0; + ethernet1 = &pfe_mac1; }; }; @@ -96,11 +98,49 @@ spi-max-frequency = <50000000>; m25p,fast-read; reg = <0>; - spi-rx-bus-width = <2>; - spi-tx-bus-width = <2>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; }; }; &sata { status = "okay"; }; + +&pfe { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pfe_mac0: ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy>; + }; + + pfe_mac1: ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + }; + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy: ethernet-phy@2 { + reg = <0x2>; + }; + + rgmii_phy: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 2024-06-19 12:33:58.272192087 +0200 @@ -605,6 +605,7 @@ snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + dma-coherent; status = "disabled"; }; @@ -615,6 +616,7 @@ snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + dma-coherent; status = "disabled"; }; @@ -712,6 +714,7 @@ reg = <0 0x5000000 0 0x800000>; #global-interrupts = <8>; #iommu-cells = <1>; + dma-coherent; stream-match-mask = <0x7c00>; /* global secure fault */ interrupts = , @@ -854,12 +857,13 @@ port { dpi0_out: endpoint { - + remote-endpoint = <&dp1_out>; }; }; }; - gpu: gpu@f0c0000 { + /* Remove the upstream node to add node from SDK driver */ +/* gpu: gpu@f0c0000 { compatible = "vivante,gc"; reg = <0x0 0xf0c0000 0x0 0x10000>; interrupts = ; @@ -869,6 +873,17 @@ clock-names = "core", "shader", "bus"; #cooling-cells = <2>; }; +*/ + + gpu@f0c0000 { + compatible = "fsl,ls1028a-gpu"; + reg = <0x0 0x0f0c0000 0x0 0x10000>, + <0x0 0x80000000 0x0 0x80000000>, + <0x0 0x0 0x0 0x3000000>; + reg-names = "base", "phys_baseaddr", + "contiguous_mem"; + interrupts = ; + }; sai1: audio-controller@f100000 { #sound-dai-cells = <0>; @@ -1003,6 +1018,22 @@ clocks = <&osc_27m>; }; + hdptx0: display@f200000 { + compatible = "cdn,ls1028a-dp"; + reg = <0x0 0xf200000 0x0 0xfffff>; + interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen 2 2>, <&clockgen 2 2>, <&clockgen 2 2>, + <&clockgen 2 2>, <&clockgen 2 2>, <&dpclk>; + clock-names = "clk_core", "pclk", "sclk", + "cclk", "clk_vif", "clk_pxl"; + + port { + dp1_out: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + }; + tmu: tmu@1f80000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; @@ -1318,5 +1349,4 @@ status = "disabled"; }; }; - }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts 2024-06-19 12:33:58.272192087 +0200 @@ -60,28 +60,28 @@ port@0 { status = "okay"; phy-handle = <&slot2_qxgmii0>; - phy-mode = "usxgmii"; + phy-mode = "10g-qxgmii"; managed = "in-band-status"; }; port@1 { status = "okay"; phy-handle = <&slot2_qxgmii1>; - phy-mode = "usxgmii"; + phy-mode = "10g-qxgmii"; managed = "in-band-status"; }; port@2 { status = "okay"; phy-handle = <&slot2_qxgmii2>; - phy-mode = "usxgmii"; + phy-mode = "10g-qxgmii"; managed = "in-band-status"; }; port@3 { status = "okay"; phy-handle = <&slot2_qxgmii3>; - phy-mode = "usxgmii"; + phy-mode = "10g-qxgmii"; managed = "in-band-status"; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 2024-06-19 12:33:58.272192087 +0200 @@ -272,6 +272,11 @@ status = "okay"; }; +&hdptx0 { + lane-mapping = <0x4e>; + status = "okay"; +}; + &i2c0 { status = "okay"; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb-dpdk.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * NXP LS1028A RDB Board device tree file for DPDK + * + * Copyright 2018-2022 NXP + */ + +/dts-v1/; +#include "fsl-ls1028a-rdb.dts" + +&enetc_port0 { + /* Leave the port with SGMII in-band autoneg enabled */ + /delete-property/ phy-handle; +}; + +&enetc_port2 { + fixed-link { + /delete-property/ pause; + }; +}; + +/delete-node/ &enetc_mdio_pf3; + +/* l2switch ports */ +&mscc_felix_port0 { + /delete-property/ phy-handle; +}; + +&mscc_felix_port1 { + /delete-property/ phy-handle; +}; + +&mscc_felix_port2 { + /delete-property/ phy-handle; +}; + +&mscc_felix_port3 { + /delete-property/ phy-handle; +}; + +&mscc_felix_port4 { + fixed-link { + /delete-property/ pause; + }; +}; + +&mscc_felix_port5 { + /delete-property/ ethernet; + fixed-link { + /delete-property/ pause; + }; +}; + +&enetc_port3 { + fixed-link { + /delete-property/ pause; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 2024-06-19 12:33:58.272192087 +0200 @@ -192,6 +192,11 @@ status = "okay"; }; +&hdptx0 { + lane-mapping = <0x4e>; + status = "okay"; +}; + &i2c0 { status = "okay"; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 2024-06-19 12:33:58.272192087 +0200 @@ -311,6 +311,48 @@ clocks = <&sysclk>; }; + smmu: iommu@9000000 { + compatible = "arm,mmu-500"; + reg = <0 0x9000000 0 0x400000>; + stream-match-mask = <0x7f00>; + #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + scfg: scfg@1570000 { compatible = "fsl,ls1043a-scfg", "syscon"; reg = <0x0 0x1570000 0x0 0x10000>; @@ -824,7 +866,7 @@ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; usb0: usb@2f00000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; @@ -832,11 +874,13 @@ snps,dis_rxdet_inp3_quirk; usb3-lpm-capable; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; usb1: usb@3000000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; reg = <0x0 0x3000000 0x0 0x10000>; interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; @@ -844,11 +888,13 @@ snps,dis_rxdet_inp3_quirk; usb3-lpm-capable; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; usb2: usb@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1043a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; @@ -856,6 +902,8 @@ snps,dis_rxdet_inp3_quirk; usb3-lpm-capable; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; @@ -903,6 +951,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -930,6 +979,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -957,6 +1007,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,263 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1043a-qds.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3500000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3600000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +/delete-node/ iommu@9000000; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + dma-coherent; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi0 { + dma-coherent; +}; + +&dspi1 { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&gpio4 { + dma-coherent; +}; + +&uqe { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,262 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1043a-rdb.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3500000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +pcie@3600000 { + /delete-property/ iommu-map; + dma-coherent; +}; + +/delete-node/ iommu@9000000; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi0 { + dma-coherent; +}; + +&dspi1 { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&gpio4 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&fman0 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,140 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2014-2015, Freescale Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "fsl-ls1043a-rdb-sdk.dts" + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,p4080-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,p4080-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,p4080-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@0 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>; + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>; + }; + + ethernet@1 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>; + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>; + }; + + ethernet@2 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; + }; + + ethernet@3 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; + }; + + ethernet@4 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; + }; + + ethernet@5 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>; + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>; + }; + + ethernet@8 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; + + }; + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* */ + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi 2024-06-19 12:33:58.272192087 +0200 @@ -317,6 +317,48 @@ bus-width = <4>; }; + smmu: iommu@9000000 { + compatible = "arm,mmu-500"; + reg = <0 0x9000000 0 0x400000>; + stream-match-mask = <0x7f00>; + #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + scfg: scfg@1570000 { compatible = "fsl,ls1046a-scfg", "syscon"; reg = <0x0 0x1570000 0x0 0x10000>; @@ -712,6 +754,7 @@ QORIQ_CLK_PLL_DIV(2)>, <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>; + dma-noncoherent; }; aux_bus: aux_bus { @@ -722,7 +765,7 @@ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; usb0: usb@2f00000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = ; dr_mode = "host"; @@ -730,10 +773,12 @@ snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; usb3-lpm-capable; + snps,host-vbus-glitches; + dma-coherent; }; usb1: usb@3000000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; reg = <0x0 0x3000000 0x0 0x10000>; interrupts = ; dr_mode = "host"; @@ -741,10 +786,12 @@ snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; usb3-lpm-capable; + snps,host-vbus-glitches; + dma-coherent; }; usb2: usb@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1046a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; dr_mode = "host"; @@ -752,6 +799,8 @@ snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; usb3-lpm-capable; + snps,host-vbus-glitches; + dma-coherent; }; sata: sata@3200000 { @@ -806,6 +855,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -845,6 +895,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -884,6 +935,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + iommu-map = <0 &smmu 0 1>; /* update by bootloader */ num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2019 NXP. + * + */ + +#include "fsl-ls1046a-frwy.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; + +&fsldpaa { + ethernet@1 { + status = "disabled"; + }; + ethernet@2 { + status = "disabled"; + }; + ethernet@3 { + status = "disabled"; + }; + ethernet@6 { + status = "disabled"; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + dma-coherent; + }; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio0 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&sata { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&fman0 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2019 NXP. + * + */ + +#include "fsl-ls1046a-frwy-sdk.dts" + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@0 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>; + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>; + }; + + ethernet@4 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>; + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>; + }; + + ethernet@5 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; + }; + + ethernet@9 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; + }; + + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* */ + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,264 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1046a-qds.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; +}; + +pcie@3500000 { + /delete-property/ iommu-map; +}; + +pcie@3600000 { + /delete-property/ iommu-map; +}; + +/delete-node/ iommu@9000000; +}; + +&fsldpaa { + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + dma-coherent; + }; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + dma-coherent; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio0 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&sata { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts 2024-06-19 12:33:58.272192087 +0200 @@ -104,7 +104,7 @@ #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; + spi-rx-bus-width = <1>; spi-tx-bus-width = <1>; reg = <0>; }; @@ -114,7 +114,7 @@ #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; + spi-rx-bus-width = <1>; spi-tx-bus-width = <1>; reg = <1>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,273 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "fsl-ls1046a-rdb.dts" +#include "qoriq-qman-portals-sdk.dtsi" +#include "qoriq-bman-portals-sdk.dtsi" + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&soc { +/delete-property/ dma-coherent; + +#include "qoriq-dpaa-eth.dtsi" +#include "qoriq-fman3-0-6oh.dtsi" + +pcie@3400000 { + /delete-property/ iommu-map; +}; + +pcie@3500000 { + /delete-property/ iommu-map; +}; + +pcie@3600000 { + /delete-property/ iommu-map; +}; + +/delete-node/ iommu@9000000; +}; + +&fsldpaa { + ethernet@0 { + status = "disabled"; + }; + ethernet@1 { + status = "disabled"; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + dma-coherent; + }; +}; + +&fman0 { + compatible = "fsl,fman", "simple-bus"; +}; + +&clockgen { + dma-coherent; +}; + +&scfg { + dma-coherent; +}; + +&crypto { + dma-coherent; +}; + +&dcfg { + dma-coherent; +}; + +&ifc { + dma-coherent; +}; + +&qspi { + dma-coherent; +}; + +&esdhc { + dma-coherent; +}; + +&ddr { + dma-coherent; +}; + +&tmu { + dma-coherent; +}; + +&qman { + dma-coherent; +}; + +&bman { + dma-coherent; +}; + +&bportals { + dma-coherent; +}; + +&qportals { + dma-coherent; +}; + +&dspi { + dma-coherent; +}; + +&i2c0 { + dma-coherent; +}; + +&i2c1 { + dma-coherent; +}; + +&i2c2 { + dma-coherent; +}; + +&i2c3 { + dma-coherent; +}; + +&duart0 { + dma-coherent; +}; + +&duart1 { + dma-coherent; +}; + +&duart2 { + dma-coherent; +}; + +&duart3 { + dma-coherent; +}; + +&gpio0 { + dma-coherent; +}; + +&gpio1 { + dma-coherent; +}; + +&gpio2 { + dma-coherent; +}; + +&gpio3 { + dma-coherent; +}; + +&lpuart0 { + dma-coherent; +}; + +&lpuart1 { + dma-coherent; +}; + +&lpuart2 { + dma-coherent; +}; + +&lpuart3 { + dma-coherent; +}; + +&lpuart4 { + dma-coherent; +}; + +&lpuart5 { + dma-coherent; +}; + +&ftm_alarm0 { + dma-coherent; +}; + +&wdog0 { + dma-coherent; +}; + +&edma0 { + dma-coherent; +}; + +&sata { + dma-coherent; +}; + +&qdma { + dma-coherent; +}; + +&msi1 { + dma-coherent; +}; + +&msi2 { + dma-coherent; +}; + +&msi3 { + dma-coherent; +}; + +&fman0 { + dma-coherent; +}; + +&ptp_timer0 { + dma-coherent; +}; + +&fsldpaa { + dma-coherent; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-shared-mac9-only.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-shared-mac9-only.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-shared-mac9-only.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-shared-mac9-only.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2019-2021 NXP + * Device Tree file to support Shared Mac interface for 1046A family SoC. + * This file is for MAC9 as shared and rest of the interfaces are assigned to Linux Kernel only + */ + +#include "fsl-ls1046a-rdb-sdk.dts" + +&bportals { + bman-bpids@0 { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <16 48>; + }; +}; + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@8 { + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1 0x8a 1>; + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1 0x84 1>; + }; + + + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* */ + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; +}; + +/ { + chosen { + name = "chosen"; + dpaa-extended-args { + fman0-extd-args { + + cell-index = <0>; + compatible = "fsl,fman-extended-args"; + dma-aid-mode = "port"; + + fman0_rxt0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-rx-extended-args"; + /* Define Virtual storage profile */ + /* */ + vsp-window = <2 0>; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,133 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright (C) 2016, Freescale Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "fsl-ls1046a-rdb-sdk.dts" + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@2 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; + }; + + ethernet@3 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; + }; + + ethernet@4 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; + }; + + ethernet@5 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>; + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>; + }; + + ethernet@8 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; + }; + + ethernet@9 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>; + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>; + }; + + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* */ + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; + + pcie@3400000 { + /delete-property/ iommu-map; + }; + + pcie@3500000 { + /delete-property/ iommu-map; + }; + + pcie@3600000 { + /delete-property/ iommu-map; + }; + + /delete-node/ iommu@9000000; +}; +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,189 @@ +/* + * Device Tree file to support Shared Mac interface for 1046A family SoC. + * + * Copyright 2019-2021 NXP + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "fsl-ls1046a-rdb-sdk.dts" + +&bportals { + bman-bpids@0 { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <16 48>; + }; +}; + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@2 { + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x54 1 0x55 1 0x86 1>; + fsl,qman-frame-queues-tx = <0x74 1 0x75 1 0x80 1>; + }; + + ethernet@3 { + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x56 1 0x57 1 0x87 1>; + fsl,qman-frame-queues-tx = <0x76 1 0x77 1 0x81 1>; + }; + + ethernet@4 { + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x58 1 0x59 1 0x88 1>; + fsl,qman-frame-queues-tx = <0x78 1 0x79 1 0x82 1>; + }; + + ethernet@5 { + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1 0x89 1>; + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1 0x83 1>; + }; + + ethernet@8 { + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1 0x8a 1>; + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1 0x84 1>; + }; + + ethernet@9 { + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1 0x8b 1>; + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1 0x85 1>; + }; + + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* */ + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; +}; +/ { + chosen { + name = "chosen"; + dpaa-extended-args { + fman0-extd-args { + + cell-index = <0>; + compatible = "fsl,fman-extended-args"; + dma-aid-mode = "port"; + + fman0_rx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + /* Define Virtual storage profile */ + /* */ + vsp-window = <2 0>; + }; + fman0_rx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + /* Define Virtual storage profile */ + /* */ + vsp-window = <2 0>; + }; + fman0_rx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + /* Define Virtual storage profile */ + /* */ + vsp-window = <2 0>; + }; + fman0_rx5-extd-args { + cell-index = <5>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + /* Define Virtual storage profile */ + /* */ + vsp-window = <2 0>; + }; + fman0_rx6-extd-args { + cell-index = <6>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + /* Define Virtual storage profile */ + /* */ + vsp-window = <2 0>; + }; + fman0_rx7-extd-args { + cell-index = <7>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + /* Define Virtual storage profile */ + /* */ + vsp-window = <2 0>; + }; + fman0_rxt0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-rx-extended-args"; + /* Define Virtual storage profile */ + /* */ + vsp-window = <2 0>; + }; + fman0_rxt1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-10g-rx-extended-args"; + /* Define Virtual storage profile */ + /* */ + vsp-window = <2 0>; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared-mac10.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared-mac10.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared-mac10.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa-shared-mac10.dts 2024-06-19 12:33:58.272192087 +0200 @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2019-2021 NXP + * Device Tree file to support Shared Mac interface for 1046A family SoC. + * This file is for MAC10 as shared and rest of the interfaces are for Userspace-DPDK + */ + +#include "fsl-ls1046a-rdb-sdk.dts" + +&bportals { + bman-bpids@0 { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <16 48>; + }; +}; + +&soc { + bp7: buffer-pool@7 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <7>; + fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xdeadbeef>; + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; + dma-coherent; + }; + + bp8: buffer-pool@8 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <8>; + fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xabbaf00d>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + bp9: buffer-pool@9 { + compatible = "fsl,ls1046a-bpool", "fsl,bpool"; + fsl,bpid = <9>; + fsl,bpool-ethernet-cfg = <0 16 0 1728 0 0xfeedabba>; + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; + dma-coherent; + }; + + fsl,dpaa { + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; + dma-coherent; + + ethernet@2 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; + }; + + ethernet@3 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; + }; + + ethernet@4 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; + }; + + ethernet@5 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>; + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>; + }; + + ethernet@8 { + compatible = "fsl,dpa-ethernet-init"; + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; + }; + + ethernet@9 { + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1 0x8b 1>; + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1 0x85 1>; + }; + + dpa-fman0-oh@2 { + compatible = "fsl,dpa-oh"; + /* Define frame queues for the OH port*/ + /* */ + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; + fsl,fman-oh-port = <&fman0_oh2>; + }; + }; +}; + +/ { + chosen { + name = "chosen"; + dpaa-extended-args { + fman0-extd-args { + + cell-index = <0>; + compatible = "fsl,fman-extended-args"; + dma-aid-mode = "port"; + + fman0_rxt1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-10g-rx-extended-args"; + /* Define Virtual storage profile */ + /* */ + vsp-window = <2 0>; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* For legacy usdpaa based use-cases, update the size and + alignment parameters. e.g. to allocate 256 MB memory: + size = <0 0x10000000>; + alignment = <0 0x10000000>; + */ + usdpaa_mem: usdpaa_mem { + compatible = "fsl,usdpaa-mem"; + alloc-ranges = <0 0 0x10000 0>; + size = <0 0x1000>; + alignment = <0 0x1000>; + }; + }; +}; + +&fman0 { + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 2024-06-19 12:33:58.272192087 +0200 @@ -415,7 +415,7 @@ }; i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1088a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; @@ -426,35 +426,38 @@ }; i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1088a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(8)>; + scl-gpios = <&gpio2 12 0>; status = "disabled"; }; i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1088a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(8)>; + scl-gpios = <&gpio3 28 0>; status = "disabled"; }; i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1088a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(8)>; + scl-gpios = <&gpio3 30 0>; status = "disabled"; }; @@ -488,24 +491,28 @@ }; usb0: usb@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1088a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; usb1: usb@3110000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1088a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; @@ -591,6 +598,8 @@ reg = <0x00 0x03400000 0x0 0x00100000>, <0x20 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "pme"; num-ib-windows = <24>; num-ob-windows = <256>; max-functions = /bits/ 8 <2>; @@ -628,6 +637,8 @@ reg = <0x00 0x03500000 0x0 0x00100000>, <0x28 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "pme"; num-ib-windows = <6>; num-ob-windows = <6>; status = "disabled"; @@ -664,6 +675,8 @@ reg = <0x00 0x03600000 0x0 0x00100000>, <0x30 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "pme"; num-ib-windows = <6>; num-ob-windows = <6>; status = "disabled"; @@ -674,6 +687,7 @@ reg = <0 0x5000000 0 0x800000>; #iommu-cells = <1>; stream-match-mask = <0x7C00>; + dma-coherent; #global-interrupts = <12>; // global secure fault interrupts = , diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts 2024-06-19 12:33:58.272192087 +0200 @@ -223,7 +223,7 @@ #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; + spi-rx-bus-width = <1>; spi-tx-bus-width = <1>; reg = <0>; }; @@ -233,7 +233,7 @@ #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; + spi-rx-bus-width = <1>; spi-tx-bus-width = <1>; reg = <1>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -12,6 +12,7 @@ #include #include #include +#include / { compatible = "fsl,ls2080a"; @@ -397,9 +398,9 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>, + QORIQ_CLK_PLL_DIV(32)>, <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>; + QORIQ_CLK_PLL_DIV(32)>; clock-names = "wdog_clk", "apb_pclk"; }; @@ -407,9 +408,9 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>, + QORIQ_CLK_PLL_DIV(32)>, <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>; + QORIQ_CLK_PLL_DIV(32)>; clock-names = "wdog_clk", "apb_pclk"; }; @@ -417,9 +418,9 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>, + QORIQ_CLK_PLL_DIV(32)>, <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>; + QORIQ_CLK_PLL_DIV(32)>; clock-names = "wdog_clk", "apb_pclk"; }; @@ -427,9 +428,9 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>, + QORIQ_CLK_PLL_DIV(32)>, <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>; + QORIQ_CLK_PLL_DIV(32)>; clock-names = "wdog_clk", "apb_pclk"; }; @@ -437,9 +438,9 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc200000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>, + QORIQ_CLK_PLL_DIV(32)>, <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>; + QORIQ_CLK_PLL_DIV(32)>; clock-names = "wdog_clk", "apb_pclk"; }; @@ -447,9 +448,9 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc210000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>, + QORIQ_CLK_PLL_DIV(32)>, <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>; + QORIQ_CLK_PLL_DIV(32)>; clock-names = "wdog_clk", "apb_pclk"; }; @@ -457,9 +458,9 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc300000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>, + QORIQ_CLK_PLL_DIV(32)>, <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>; + QORIQ_CLK_PLL_DIV(32)>; clock-names = "wdog_clk", "apb_pclk"; }; @@ -467,9 +468,9 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc310000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>, + QORIQ_CLK_PLL_DIV(32)>, <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(4)>; + QORIQ_CLK_PLL_DIV(32)>; clock-names = "wdog_clk", "apb_pclk"; }; @@ -1003,7 +1004,7 @@ i2c0: i2c@2000000 { status = "disabled"; - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls208xa-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; @@ -1015,7 +1016,7 @@ i2c1: i2c@2010000 { status = "disabled"; - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls208xa-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; @@ -1023,11 +1024,12 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; + scl-gpios = <&gpio2 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; i2c2: i2c@2020000 { status = "disabled"; - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls208xa-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; @@ -1035,11 +1037,12 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; + scl-gpios = <&gpio3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; i2c3: i2c@2030000 { status = "disabled"; - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls208xa-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; @@ -1047,6 +1050,7 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; + scl-gpios = <&gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; ifc: memory-controller@2240000 { @@ -1081,8 +1085,8 @@ pcie1: pcie@3400000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 108 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -1103,8 +1107,8 @@ pcie2: pcie@3500000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 113 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -1125,8 +1129,8 @@ pcie3: pcie@3600000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 118 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -1147,8 +1151,8 @@ pcie4: pcie@3700000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 123 0x4>; /* Level high type */ - interrupt-names = "intr"; + interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -1188,24 +1192,26 @@ usb0: usb@3100000 { status = "disabled"; - compatible = "snps,dwc3"; + compatible = "fsl,ls2088a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 80 0x4>; /* Level high type */ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; usb1: usb@3110000 { status = "disabled"; - compatible = "snps,dwc3"; + compatible = "fsl,ls2088a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = <0 81 0x4>; /* Level high type */ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; ccn@4000000 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -1032,7 +1032,7 @@ }; usb0: usb@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; dr_mode = "host"; @@ -1040,11 +1040,13 @@ usb3-lpm-capable; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; usb1: usb@3110000 { - compatible = "snps,dwc3"; + compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = ; dr_mode = "host"; @@ -1052,6 +1054,8 @@ usb3-lpm-capable; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; @@ -1413,6 +1417,7 @@ status = "disabled"; pcs1: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1426,6 +1431,7 @@ status = "disabled"; pcs2: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1439,6 +1445,7 @@ status = "disabled"; pcs3: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1452,6 +1459,7 @@ status = "disabled"; pcs4: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1465,6 +1473,7 @@ status = "disabled"; pcs5: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1478,6 +1487,7 @@ status = "disabled"; pcs6: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1491,6 +1501,7 @@ status = "disabled"; pcs7: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1504,6 +1515,7 @@ status = "disabled"; pcs8: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1517,6 +1529,7 @@ status = "disabled"; pcs9: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1530,6 +1543,7 @@ status = "disabled"; pcs10: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1543,6 +1557,7 @@ status = "disabled"; pcs11: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1556,6 +1571,7 @@ status = "disabled"; pcs12: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1569,6 +1585,7 @@ status = "disabled"; pcs13: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1582,6 +1599,7 @@ status = "disabled"; pcs14: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1595,6 +1613,7 @@ status = "disabled"; pcs15: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1608,6 +1627,7 @@ status = "disabled"; pcs16: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1621,6 +1641,7 @@ status = "disabled"; pcs17: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; @@ -1634,6 +1655,7 @@ status = "disabled"; pcs18: ethernet-phy@0 { + compatible = "fsl,lx2160a-lynx-pcs"; reg = <0>; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts 2024-06-19 12:33:58.276192156 +0200 @@ -31,6 +31,28 @@ regulator-boot-on; regulator-always-on; }; + + sfp2: sfp-2 { + compatible = "sff,sfp"; + i2c-bus = <&sfp2_i2c>; + maximum-power-milliwatt = <2000>; + /* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */ + /* tx-disable-gpios = <&sfp2_csr 0 GPIO_ACTIVE_HIGH>; */ + los-gpios = <&sfp2_csr 4 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&sfp2_csr 5 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sfp2_csr 7 GPIO_ACTIVE_LOW>; + }; + + sfp3: sfp-3 { + compatible = "sff,sfp"; + i2c-bus = <&sfp3_i2c>; + maximum-power-milliwatt = <2000>; + /* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */ + /* tx-disable-gpios = <&sfp3_csr 0 GPIO_ACTIVE_HIGH>; */ + los-gpios = <&sfp3_csr 4 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&sfp3_csr 5 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sfp3_csr 7 GPIO_ACTIVE_LOW>; + }; }; &crypto { @@ -50,11 +72,17 @@ }; &dpmac5 { - phy-handle = <&inphi_phy>; + sfp = <&sfp2>; + managed = "in-band-status"; + phys = <&serdes_1 5>, <&inphi_retimer 0>; + phy-names = "serdes", "retimer"; }; &dpmac6 { - phy-handle = <&inphi_phy>; + sfp = <&sfp3>; + managed = "in-band-status"; + phys = <&serdes_1 4>, <&inphi_retimer 1>; + phy-names = "serdes", "retimer"; }; &dpmac17 { @@ -120,9 +148,10 @@ &emdio2 { status = "okay"; - inphi_phy: ethernet-phy@0 { - compatible = "ethernet-phy-id0210.7440"; + inphi_retimer: retimer@0 { + compatible = "inphi,in112525"; reg = <0x0>; + #phy-cells = <1>; }; }; @@ -170,6 +199,37 @@ &i2c0 { status = "okay"; + cpld@66 { + compatible = "fsl,lx2160a-rdb-qixis-cpld"; + reg = <0x66>; + #address-cells = <1>; + #size-cells = <0>; + + sfp2_csr: gpio@19 { + compatible = "fsl,lx2160a-rdb-qixis-cpld-gpio"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SFP2_TX_EN", "", + "", "", + "SFP2_RX_LOS", "SFP2_TX_FAULT", + "", "SFP2_MOD_ABS"; + }; + + sfp3_csr: gpio@1a { + compatible = "fsl,lx2160a-rdb-qixis-cpld-gpio"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SFP3_TX_EN", "", + "", "", + "SFP3_RX_LOS", "SFP3_TX_FAULT", + "", "SFP3_MOD_ABS"; + }; + }; + i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>; @@ -205,15 +265,40 @@ vcc-supply = <&sb_3v3>; }; }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + + i2c-mux@75 { + compatible = "nxp,pca9547"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + + sfp2_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + sfp3_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + }; + }; }; }; &i2c4 { status = "okay"; - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; + rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; /* IRQ_RTC_B -> IRQ08, active low */ interrupts-extended = <&extirq 8 IRQ_TYPE_LEVEL_LOW>; }; @@ -231,6 +316,14 @@ status = "okay"; }; +&pcs_mdio5 { + status = "okay"; +}; + +&pcs_mdio6 { + status = "okay"; +}; + &sata0 { status = "okay"; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dm.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dm.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dm.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dm.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8DM"; + compatible = "fsl, imx8dm", "fsl,imx8qm"; + +}; + +&thermal_zones { + /delete-node/ cpu-thermal0; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@0; + /delete-node/ cpu@1; + /delete-node/ cpu@2; + /delete-node/ cpu@3; + /delete-node/ l2-cache0; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dm-lpddr4-val.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dm.dtsi" +#include "imx8q-val.dtsi" + +/ { + model = "Freescale i.MX8DM Validation Board"; + compatible = "fsl,imx8dm-val", "fsl,imx8dm", "fsl,imx8qm"; +}; + +&gpu_3d1 { + status = "disabled"; +}; + +&dc1_prg1 { + status = "disabled"; +}; + +&dc1_prg2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-17x17-val.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dx.dtsi" +#include "imx8x-17x17-val.dtsi" + +/ { + model = "Freescale i.MX8DX 17x17 Validation Board"; + compatible = "fsl,imx8dx-17x17-val", "fsl,imx8dx", "fsl,imx8qxp"; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + */ + +/dts-v1/; + +#include "imx8dxp.dtsi" + +&gpu_3d0 { + assigned-clock-rates = <372000000>, <372000000>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ddr3l-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ddr3l-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ddr3l-evk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ddr3l-evk.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,936 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl.dtsi" + +/ { + model = "Freescale i.MX8DXL DDR3L EVK"; + compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl"; + + chosen { + stdout-path = &lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x20000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg = <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x8000000>; + alloc-ranges = <0 0x98000000 0 0x8000000>; + linux,cma-default; + }; + }; + + reg_can0_stby: regulator-can0-stby { + compatible = "regulator-fixed"; + regulator-name = "can0-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3480>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8960_1>; + audio-asrc = <&asrc0>; + hp-det-gpio = <&pca6416_2 11 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; + + sound-wm8960-2 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-2"; + audio-cpu = <&sai2>; + audio-codec = <&wm8960_2>; + capture-only; + hp-det-gpio = <&pca6416_2 12 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; + + sound-wm8960-3 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-3"; + audio-cpu = <&sai3>; + audio-codec = <&wm8960_3>; + capture-only; + hp-det-gpio = <&pca6416_2 13 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; + + sound-wm8960-4 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-4"; + audio-cpu = <&sai0>; + audio-codec = <&wm8960_4>; + hp-det-gpio = <&pca6416_2 10 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&edma2 { + status = "okay"; +}; + +&edma3 { + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <10 20 200000>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + qca,disable-smarteee; + qca,disable-hibernation-mode; + vddio-supply = <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + fsl,magic-packet; + rx-internal-delay-ps = <2000>; + phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + qca,disable-smarteee; + vddio-supply = <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can0_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + nxp,fspi-individual-mode; + + mt25qu512abb0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; + + mt25qu512abb1: flash@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; + fsl,max-nand-cs = <1>; + fsl,use-minimum-ecc; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca6416_1: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <5 IRQ_TYPE_EDGE_BOTH>; + }; + + pca9548_1: pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + wm8960_1: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + wm8960_2: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + wm8960_3: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + + wm8960_4: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416_3: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9548_2: pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + fsl,spi-only-use-cs1-sel; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-1 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&lsio_gpio4 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + status = "disabled"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&sai0 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai2 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai2_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai3_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; + max-frequency = <100000000>; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c + >; + }; + + pinctrl_adc: adcgrp{ + fsl,pins = < + IMX8DXL_ADC_IN0_ADMA_ADC_IN0 0x06000021 + IMX8DXL_ADC_IN1_ADMA_ADC_IN1 0x06000021 + IMX8DXL_ADC_IN4_ADMA_ADC_IN4 0x06000021 + IMX8DXL_ADC_IN5_ADMA_ADC_IN5 0x06000021 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 + IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 + IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c + + IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c + IMX8DXL_USDHC1_WP_CONN_NAND_ALE 0x0e00004c + IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x0600004c + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x0600004c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x0600004c + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x0600004c + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x0600004c + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x0600004c + >; + }; + + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 + IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD 0x06000060 + IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000060 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 + IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 + IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 + IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ + IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ + IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usbotg1: otg1 { + fsl,pins = < + IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usbotg2: otg2 { + fsl,pins = < + IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 + >; + }; +}; + +&imx8dxl_cm4 { + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, + <&vdev1vring0>, <&vdev1vring1>; + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ddr3l-evk-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ddr3l-evk-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ddr3l-evk-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ddr3l-evk-rpmsg.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl-ddr3l-evk.dts" + +&imx8dxl_cm4 { + /* Assume you have partitioned M4, so M4 is not controled by Linux */ + /delete-property/ power-domains; + status = "okay"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexcan3 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&cm40_lpuart { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl.dtsi 2024-06-19 12:33:58.280192223 +0200 @@ -17,6 +17,9 @@ #size-cells = <2>; aliases { + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; ethernet0 = &fec1; ethernet1 = &eqos; gpio0 = &lsio_gpio0; @@ -27,7 +30,16 @@ gpio5 = &lsio_gpio5; gpio6 = &lsio_gpio6; gpio7 = &lsio_gpio7; + i2c2 = &i2c2; + i2c3 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; mu1 = &lsio_mu1; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &cm40_lpuart; }; cpus: cpus { @@ -80,6 +92,26 @@ }; }; + cm4 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + imx8dxl_cm4: imx8dxl_cm4@0 { + compatible = "fsl,imx8qxp-cm4"; + rsc-da = <0x90000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + fsl,resource-id = ; + fsl,entry-address = <0x34fe0000>; + status = "disabled"; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, + <&pd IMX_SC_R_M4_0_MU_1A>; + }; + }; + gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ @@ -129,8 +161,6 @@ clk: clock-controller { compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; #clock-cells = <2>; - clocks = <&xtal32k &xtal24m>; - clock-names = "xtal_32KHz", "xtal_24Mhz"; }; iomuxc: pinctrl { @@ -138,7 +168,7 @@ }; ocotp: ocotp { - compatible = "fsl,imx8qxp-scu-ocotp"; + compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp"; #address-cells = <1>; #size-cells = <1>; @@ -225,14 +255,37 @@ clock-output-names = "xtal_24MHz"; }; + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + /* sorted in register address */ + #include "imx8-ss-v2x.dtsi" + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm40.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-lcdif.dtsi" }; #include "imx8dxl-ss-adma.dtsi" #include "imx8dxl-ss-conn.dtsi" #include "imx8dxl-ss-lsio.dtsi" +#include "imx8dxl-ss-hsio.dtsi" #include "imx8dxl-ss-ddr.dtsi" +#include "imx8dxl-ss-security.dtsi" + +&cm40_intmux { + interrupts = , + , + , + , + , + , + , + ; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts 2024-06-19 12:33:58.276192156 +0200 @@ -49,6 +49,82 @@ alloc-ranges = <0 0x98000000 0 0x14000000>; linux,cma-default; }; + + vdev0vring0: vdev0vring0@90000000 { + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@900ff000 { + reg = <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + }; + + enet0_reset: enet0-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + #reset-cells = <0>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca6416_2 0 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reg_pcieb: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "reg_pcieb"; + gpio = <&pca6416_1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + m2_uart1_sel: fixedregulator@101 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "m2_uart1_sel"; + gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + m2_spi0_sel: fixedregulator@102 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "m2_spi0_sel"; + gpio = <&pca6416_1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; }; mux3_en: regulator-0 { @@ -60,12 +136,22 @@ regulator-always-on; }; + pcie_clk_sel_ext: fixedregulator@103 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "clk_ext_sel"; + gpio = <&pca6416_1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + reg_fec1_sel: regulator-1 { compatible = "regulator-fixed"; regulator-name = "fec1_supply"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; regulator-always-on; status = "disabled"; }; @@ -81,6 +167,24 @@ status = "disabled"; }; + reg_can0_stby: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "can0-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_stby: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-3 { compatible = "regulator-fixed"; regulator-name = "SD1_SPWR"; @@ -90,6 +194,126 @@ enable-active-high; off-on-delay-us = <3480>; }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai0>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8960_1>; + audio-asrc = <&asrc0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; + + sound-wm8960-2 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-2"; + audio-cpu = <&sai2>; + audio-codec = <&wm8960_2>; + capture-only; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; + + sound-wm8960-3 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio-3"; + audio-cpu = <&sai3>; + audio-codec = <&wm8960_3>; + capture-only; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; + + scu_gpio0: scu-gpio0 { + compatible = "fsl,imx8qxp-sc-gpio"; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + mii_select: mii_select { + compatible = "regulator-fixed"; + regulator-name = "mii-select"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&scu_gpio0 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&adc0 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&edma2 { + status = "okay"; +}; + +&edma3 { + status = "okay"; }; &eqos { @@ -148,8 +372,6 @@ ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; qca,disable-smarteee; vddio-supply = <&vddio1>; @@ -161,6 +383,48 @@ }; }; +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + nxp,fspi-dll-slvdly = <4>; + status = "okay"; + + mt35xu512aba0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + +&imx8dxl_cm4 { + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&lsio_mu5 { + status = "okay"; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + fsl,spi-only-use-cs1-sel; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + &i2c2 { #address-cells = <1>; #size-cells = <0>; @@ -199,10 +463,77 @@ reg = <0x68>; gpio-controller; #gpio-cells = <2>; + resets = <&enet0_reset>; status = "disabled"; }; }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + wm8960_1: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout1_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + wm8960_2: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout1_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + wm8960_3: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + pinctrl-assert-gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + clocks = <&mclkout1_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + i2c@4 { #address-cells = <1>; #size-cells = <0>; @@ -223,12 +554,102 @@ }; }; +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416_3: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + }; + + pca9548_2: i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; +}; + +&cm40_intmux { + status = "disabled"; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; status = "okay"; }; +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&cm40_lpuart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm40_lpuart>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can0_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + &lsio_gpio4 { status = "okay"; }; @@ -237,6 +658,73 @@ status = "okay"; }; +&phyx1 { + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&pcieb{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcieb>; + status = "okay"; +}; + +&pcieb_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + status = "disabled"; +}; + +&sai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai2 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai2_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai3_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + fsl,sai-asynchronous; + status = "okay"; +}; + &thermal_zones { pmic-thermal0 { polling-delay-passive = <250>; @@ -268,9 +756,43 @@ }; }; -&usdhc1 { +&usbphy1 { + status = "okay"; + fsl,tx-d-cal = <114>; +}; + +&usbotg1 { pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy2 { + status = "okay"; + fsl,tx-d-cal = <111>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; no-sd; no-sdio; @@ -279,12 +801,15 @@ }; &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; vmmc-supply = <®_usdhc2_vmmc>; cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; + max-frequency = <100000000>; status = "okay"; }; @@ -332,6 +857,39 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 + IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 + IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 @@ -362,6 +920,15 @@ >; }; + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 @@ -390,6 +957,58 @@ >; }; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000060 + IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC 0x06000040 + IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC 0x06000060 + IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD 0x06000060 + IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 + IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 + IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 + IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 @@ -406,6 +1025,38 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ @@ -418,6 +1069,30 @@ fsl,pins = < IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl-evk.dts" + +®_fec1_sel { + status = "okay"; +}; + +®_fec1_io { + status = "okay"; +}; + +&mii_select { + /delete-property/ enable-active-high; +}; + +&eqos { + status = "disabled"; +}; + +&fec1 { + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <12000000>; + phy-supply = <®_fec1_io>; + status = "okay"; +}; + +&max7322 { + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-enet0-tja1100.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dxl-evk-enet0.dts" + +ðphy1 { + status = "disabled"; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_fec1_rmii>; + clocks = <&enet0_lpcg 4>, + <&enet0_lpcg 2>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>, + <&enet0_lpcg 0>, + <&enet0_lpcg 1>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + phy-supply = <&mii_select>; + phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <20>; + phy-reset-post-delay = <100>; + /delete-property/ rx-internal-delay-ps; + /delete-property/ tx-internal-delay-ps; + + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + }; + }; +}; + +&iomuxc { + pinctrl_fec1_rmii: fec1rmiigrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN 0x06000060 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000060 + >; + }; +}; + +&enet0_reset { + status = "disabled"; +}; + +&max7322 { + status = "disabled"; +}; + +®_fec1_io { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8dxl-evk.dts" + +/ { + panel { + compatible = "wks,101wx001"; + blctr-gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&pca6416_1 3 GPIO_ACTIVE_LOW>, + <&pca6416_1 4 GPIO_ACTIVE_LOW>, + <&pca6416_1 6 GPIO_ACTIVE_LOW>, + <&pca6416_1 7 GPIO_ACTIVE_LOW>, + <&pca6416_1 8 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; +}; + +/delete-node/ &m2_spi0_sel; + +&sai0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&m2_uart1_sel { + status = "disabled"; +}; + +&cm40_lpuart { + status = "disabled"; +}; + +&lpuart1 { + status = "disabled"; +}; + +&eqos { + status = "disabled"; +}; + +&lpspi3 { + status = "disabled"; +}; + +&wm8960_1 { + status = "disabled"; +}; + +&wm8960_2 { + status = "disabled"; +}; + +&wm8960_3 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00 0xe8000023 + IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01 0xe8000023 + IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02 0xe8000023 + IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 0xd0000023 + IMX8DXL_UART1_TX_ADMA_LCDIF_D04 0xe8000023 + IMX8DXL_UART1_RX_ADMA_LCDIF_D05 0xe8000023 + IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06 0xe8000023 + IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07 0xe8000023 + IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08 0xe8000023 + IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09 0xe8000023 + IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10 0xe8000023 + IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11 0xe8000023 + IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12 0xe8000023 + IMX8DXL_ADC_IN1_ADMA_LCDIF_D13 0xe8200003 + IMX8DXL_ADC_IN0_ADMA_LCDIF_D14 0xe8200003 + IMX8DXL_ADC_IN3_ADMA_LCDIF_D15 0xe8200003 + IMX8DXL_ADC_IN2_ADMA_LCDIF_D16 0xe8200003 + IMX8DXL_ADC_IN5_ADMA_LCDIF_D17 0xe8200003 + IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC 0xd0000023 + IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET 0xd0000023 + IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN 0xd0000023 + IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC 0xd0000023 + IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK 0xd0000023 + >; + }; +}; + +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>; + assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + assigned-clock-rates = <0>, <24000000>, <711000000>; + interrupts = ; + + port@0 { + lcdif_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-lpspi-slave.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dxl-evk.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi3 { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040 + >; +}; + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + /delete-property/ cs-gpios; + spi-slave; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl-evk-rpmsg.dts" + +&pcieb { + status = "disabled"; +}; + +&pcieb_ep { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-evk-rpmsg.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dxl-evk.dts" + +&imx8dxl_cm4 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; + status = "okay"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexcan3 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&cm40_lpuart { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-orangebox.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-orangebox.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-orangebox.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-orangebox.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,1137 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022-2023 NXP + */ + +/dts-v1/; + +#include "imx8dxl.dtsi" + +/ { + model = "Freescale i.MX8DXL OrangeBox"; + compatible = "fsl,imx8dxl-orangebox", "fsl,imx8dxl"; + + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + }; + + chosen { + stdout-path = &lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg = <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x98000000 0 0x14000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@90000000 { + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@900ff000 { + reg = <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pcal6524_i2c0_x23 19 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_can1_en: regulator-can1-en{ + compatible = "regulator-fixed"; + regulator-name = "can1-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524_i2c0_x23 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524_i2c0_x23 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can1_en>; + }; + + reg_usdhc2_vqmmc: regulator-1 { + compatible = "regulator-gpio"; + regulator-name = "usdhc2_1v8_3v3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + enable-gpios = <&pcal6524_i2c0_x23 22 GPIO_ACTIVE_HIGH>; + gpios = <&pcal6524_i2c0_x23 17 GPIO_ACTIVE_HIGH>; + states = <1800000 1>, <3300000 0>; + enable-active-high; + }; + + epdev_on: regulator-2 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pcal6524_i2c0_x22 11 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100000>; + off-on-delay-us = <100000>; + enable-active-high; + }; + + wl_reset: regulator-3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "wl_reg_on"; + gpio = <&pcal6524_i2c0_x23 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; + off-on-delay-us = <100000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&epdev_on>; + }; + + bt_sco_codec: audio-codec-1 { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai0>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + codec_sys_mclk: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <12288000>; + clock-output-names = "codec_sys_mclk"; + #clock-cells = <0>; + }; + + mercury_i2s_codec: audio-codec-2 { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + num-channels = <2>; + }; + + sound-mercury { + compatible = "simple-audio-card"; + simple-audio-card,name = "mercury-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec>; + simple-audio-card,bitclock-master = <&codec>; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + + codec: simple-audio-card,codec { + sound-dai = <&mercury_i2s_codec>; + }; + }; +}; + +&edma2 { + status = "okay"; +}; + +&edma3 { + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + nxp,fspi-dll-slvdly = <4>; + status = "okay"; + + mt35xu512aba0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + +&imx8dxl_cm4 { + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&cm40_intmux { + status = "disabled"; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&cm40_lpuart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm40_lpuart>; + status = "disabled"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usbphy1 { + status = "okay"; + fsl,tx-d-cal = <114>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy2 { + status = "okay"; + fsl,tx-d-cal = <111>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + pca6416_i2c0_x20: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca6408_i2c0_x21: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "V2X_CARD_PRSNT_B", + "MDM_CARD_PRSNT_B", + "MDM_CARD_TYPE0", + "MDM_CARD_TYPE1", + "MDM_CARD_TYPE2", + "MDM_CARD_REV0", + "MDM_CARD_REV1", + "MERCURY_CARD_PRSNT_B"; + }; + + pcal6524_i2c0_x22: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524_i2c0_x22>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <9 IRQ_TYPE_EDGE_BOTH>; + gpio-line-names = + "INTB_MERCURY", + "SXF1800_GPIO0", + "SXF1800_GPIO1", + "M2_WIFI_WAKE_B", + "MDM_PWRKEY", + "", + "V2X_PMIC_STANBY", + "SDHC1_CD_B", + "RST_SXF1800_B", + "M2_WIFI_EN", + "M2_DEV_WLAN_WAKE", + "M2_DEV_BT_WAKE", + "MDM_GPIO131", + "MDM_GPIO132", + "MDM_GPIO133", + "MDM_GPIO27", + "GPIO_MDM_RST_B", + "GPIO_ESW_RST_CORE_B", + "GPIO_GNSS_RST_B", + "GPIO_ENET0_PHY_RST_B", + "GPIO_S32K_RST_B", + "MDM_GPIO134", + "MDM_GPIO135"; + + epon_hog: epon-select-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "epdev selelct"; + }; + }; + + pcal6524_i2c0_x23: gpio@23 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524_i2c0_x23>; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <8 IRQ_TYPE_EDGE_BOTH>; + gpio-line-names = + "BATT_CHGOK_B", + "IMX_CAN1_EN", + "M2_BT_UART_WAKE_B", + "ESW_INT_B", + "IMX_GNSS_GEOFENCE_STAT", + "IMX_GNSS_RTK_STAT", + "ENET0_PHY_INT_B", + "BRD_THERM_FLT_B", + "IMX_CAN0_STB_B", + "IMX_CAN1_STB_B", + "IMX_CAN0_EN", + "IMX_CAN1_EN", + "CFG_MUX_MERCURY_I2S_SEL", + "CFG_MUX_RGMII0_SDHC_SEL", + "CFG_MUX_USB1_SEL0", + "CFG_MUX_USB1_SEL1", + "IMX_GNSS_EXT_INT", + "SDHC1_VSELECT", + "M2_WIFI_DIS_B", + "M2_BT_DIS_B", + "CFG_MUX_IMX_MDM_M2_SEL", + "PWR_EN_SXF1800", + "SDHC1_RST_B", + "CFG_MUX_GNSS_1PPS_SEL"; + + cfg_mux_mercury_i2s_sel { + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "cfg_mux_mercury_i2s_sel"; + }; + + fec1_select_hog: fec1-select-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_LOW>; + output-high; + line-name = "fec1_select"; + }; + + wl_disable: m2-wifi-dis-hog { + gpio-hog; + gpios = <18 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "m.2_wifi_dis_b"; + }; + + pwr_en_sxf1800 { + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SXF1800 Power enable"; + }; + }; + + pca9548_1: pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + fxls8967@19 { + compatible = "nxp,fxls8967af"; + reg = <0x19>; + status = "okay"; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + gnss@42 { + reg = <0x42>; + status = "disabled"; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + pagesize = <16>; + reg = <0x50>; + status = "disabled"; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + clk_gen@6b { + reg = <0x6b>; + status = "disabled"; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + + mercury_card@27 { + reg = <0x27>; + status = "disabled"; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + + temp_sensor@49 { + compatible = "nxp,pct2075"; + reg = <0x49>; + }; + }; + }; +}; + +&lsio_gpio0 { + gpio-line-names = + "", "", "", "", /* 0-3 */ + "", "", "", "", /* 4-7 */ + "", "", "", "", /* 8-11 */ + "", + "IMX_SPI3_SCK", /* 13 */ + "IMX_SPI3_MOSI", + "IMX_SPI3_MISO", + "IMX_SPI3_CS0_B", + "", "", + "TP67", /* 16 */ + "TP68", + "IMX_UART1_TXD", + "IMX_UART1_RXD", + "IMX_UART1_RTS", + "IMX_UART1_CTS"; + + status = "okay"; +}; + +&lsio_gpio1 { + gpio-line-names = + "", "", "", "", /* 0 -3 */ + "IMX_SAI0_TXC", /* 4 */ + "IMX_SAI0_TXD", + "IMX_SAI0_TXFS", + "IMX_V2X_RST_B", + "IMX_SAI0_RXD", /* 8 */ + "IMX_I2C0_1V8_SDA", + "IMX_I2C0_1V8_SCL", + "IMX_M40_UART0_1V8_TX", + "IMX_M40_UART0_1V8_RX", /* 12 */ + "IMX_PAD_AG35", + "", + "IMX_CAN0_3V3_RX", + "IMX_CAN0_3V3_TX", /* 16 */ + "IMX_CAN1_3V3_RX", + "IMX_CAN1_3V3_TX", + "IMX_UART3_3V3_RX", + "IMX_UART3_3V3_TX", /* 20 */ + "IMX_UART0_3V3_RX", + "IMX_UART0_3V3_TX", + "IMX_UART2_3V3_TX", + "IMX_UART2_3V3_RX"; /* 24 */ + status = "okay"; +}; + +&lsio_gpio2 { + status = "okay"; +}; + +&lsio_gpio4 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <&fixed0>; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + status = "okay"; + + fixed0:fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + phy-reset-gpios = <&pcal6524_i2c0_x22 20 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <12000000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Realtek RTL8211F (0x001cc916) */ + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&pcal6524_i2c0_x23>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + max-speed = <1000>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + cd-gpios = <&pcal6524_i2c0_x22 7 GPIO_ACTIVE_LOW>; + vqmmc-supply = <®_usdhc2_vqmmc>; + max-frequency = <100000000>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <4>; + no-sd; + non-removable; + max-frequency = <100000000>; + status = "disabled"; +}; + +&phyx1 { + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&pcieb{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <&epdev_on>; + status = "okay"; +}; + +&lpspi1 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>; + cs-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <3000000>; + reg = <0>; + }; +}; + +&lpspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + spi-slave; + status = "okay"; +}; + +&lpspi3 { + num-cs = <2>; + cs-gpios = <&lsio_gpio0 16 GPIO_ACTIVE_LOW>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + status = "okay"; + + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <3000000>; + reg = <0>; + }; + + spidev@1 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <3000000>; + reg = <1>; + }; +}; + +&sai0 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&sai3 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai3_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 + IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 0x000014a0 + >; + }; + + pinctrl_usbotg1: otg1 { + fsl,pins = < + IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usbotg2: otg2 { + fsl,pins = < + IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 + >; + }; + + pinctrl_pps: pps { + fsl,pins = < + IMX8DXL_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x04000021 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x00000021 + IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x00000021 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x00000021 + IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8DXL_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021 /* GNSS_WHEELTICK_1V8 */ + IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8DXL_QSPI0B_DQS_LSIO_GPIO3_IO22 0x06000021 /* GNSS_DIR_1V8 */ + IMX8DXL_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x06000021 /* MERCURY_GPIO2_1V8 */ + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8DXL_UART2_RX_ADMA_UART2_RX 0x06000020 + IMX8DXL_UART2_TX_ADMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8DXL_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 + IMX8DXL_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8DXL_ADC_IN0_ADMA_I2C0_SCL 0x06000021 + IMX8DXL_ADC_IN1_ADMA_I2C0_SDA 0x06000021 + >; + }; + + pinctrl_cm40_lpuart: cm40_lpuartgrp { + fsl,pins = < + IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020 + IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_eqos_mdio: eqosmdiogrp { + fsl,pins = < + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 0x00000021 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 0x00000021 + >; + }; + + pinctrl_pcal6524_i2c0_x22: pcal6524i2c0x22grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN 0x24000021 + >; + }; + + pinctrl_pcal6524_i2c0_x23: pcal6524i2c0x23grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN 0x24000021 + >; + }; + + pinctrl_lpspi1: lpspi1grp { + fsl,pins = < + IMX8DXL_SPI1_SCK_ADMA_SPI1_SCK 0x6000040 + IMX8DXL_SPI1_SDO_ADMA_SPI1_SDO 0x6000040 + IMX8DXL_SPI1_SDI_ADMA_SPI1_SDI 0x6000040 + >; + }; + + pinctrl_lpspi1_cs: lpspi1cs { + fsl,pins = < + IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 0x21 + >; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO 0x6000040 + IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI 0x6000040 + IMX8DXL_USDHC1_CD_B_ADMA_SPI2_CS0 0x6000040 + IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK 0x6000040 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 + IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 0x6000040 + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 + IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 + IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 + IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-orangebox-sd.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-orangebox-sd.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-orangebox-sd.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-orangebox-sd.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022-2023 NXP + */ + +#include "imx8dxl-orangebox.dts" + +&fec1_select_hog { + gpios = <13 GPIO_ACTIVE_HIGH>; +}; + +&pcal6524_i2c0_x22 { + V2X_PMIC_STANBY { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "v2x active"; + }; +}; + +&usdhc2 { + status = "okay"; +}; + +&usdhc3 { + /delete-property/ no-sd; + /delete-property/ non-removable; + cd-gpios = <&pca6408_i2c0_x21 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-lpddr4-val.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dx.dtsi" +#include "imx8x-val.dtsi" + +/ { + model = "Freescale i.MX8DX VALIDATION"; + compatible = "fsl,imx8dx-val", "fsl,imx8dx", "fsl,imx8qxp"; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dxl-phantom-mek.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,671 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8DXL Phantom MEK"; + compatible = "fsl,imx8dxl-phantom-mek", "fsl,imx8dxl-phantom", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_modem_reset>; + pinctrl-1 = <&pinctrl_modem_reset_sleep>; + reset-gpios = <&lsio_gpio3 1 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can0_en: regulator-can0-gen { + compatible = "regulator-fixed"; + regulator-name = "can0-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_en: regulator-can1-gen { + compatible = "regulator-fixed"; + regulator-name = "can1-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can0_stby: regulator-can0-stby { + compatible = "regulator-fixed"; + regulator-name = "can0-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can0_en>; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can1_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /*gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; removing as i2c bus is changing in new board */ + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <3480>; + enable-active-high; + }; + + reg_pcieb: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "reg_pcieb"; + gpio = <&lsio_gpio3 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_vbus>; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&lsio_gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound: sound { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8960>; + audio-asrc = <&asrc0>; + hp-det-gpio = <&lsio_gpio0 13 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "AMIC", + "RINPUT2", "AMIC", + "Mic Jack", "MICB", + "AMIC", "MICB"; + }; +}; + +&lvds_subsys { + status = "disabled"; +}; + +&acm { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8dxl-phantom-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 + IMX8QXP_ENET0_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + >; + }; + + pinctrl_cm40_i2c: cm40i2cgrp { + fsl,pins = < + IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c + IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_ioexp_rst_sleep: ioexp_rst_sleep_grp { + fsl,pins = < + IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x07800021 + >; + }; + + pinctrl_modem_reset: modemresetgrp { + fsl,pins = < + IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x06000021 + >; + }; + + pinctrl_modem_reset_sleep: modemreset_sleepgrp { + fsl,pins = < + IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x07800021 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000040 + IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC 0x06000040 + IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS 0x06000040 + IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 + IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 0x06000040 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + pinctrl_reg_usb_vbus: regusbvbusgrp { + fsl,pins = < + IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x06000021 + IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x06000021 + >; + }; + + pinctrl_gpio3: gpio3grp{ + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x07800000 + >; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + phy-reset-gpio=<&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + qca,disable-smarteee; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can0_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <8>; + }; +}; + +&cm40_intmux { + status = "okay"; +}; + +&cm40_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm40_i2c>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + fsl,sai-synchronous-rx; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <114>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&lsio_gpio3 { + pinctrl-name = "default"; + pinctrl-0 = <&pinctrl_gpio3>; +}; + +&tsens { + tsens-num = <3>; +}; + +&thermal_zones { + cpu0-thermal { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&a35_opp_table { + /delete-node/ opp-900000000; +}; + +&cpus { + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; + +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcieb>; + ext_osc = <1>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek-rpmsg.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dxl-phantom-mek.dtsi" + +/delete-node/ &cm40_i2c; + +&i2c_rpbus_5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&cm40_i2c_lpcg { + status = "disabled"; +}; + +&can0_lpcg { + status = "disabled"; +}; + +®_can0_en { + status = "disabled"; +}; + +®_can0_stby { + status = "disabled"; +}; + +®_can1_en { + status = "disabled"; +}; + +®_can1_stby { + status = "disabled"; +}; + +&cm40_intmux { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi 2024-06-19 12:33:58.280192223 +0200 @@ -3,6 +3,47 @@ * Copyright 2019~2020, 2022 NXP */ +/delete-node/ &asrc1; +/delete-node/ &asrc1_lpcg; +/delete-node/ &adc1; +/delete-node/ &adc1_lpcg; +/delete-node/ &amix; +/delete-node/ &amix_lpcg; +/delete-node/ &dsp_lpcg; +/delete-node/ &dsp_ram_lpcg; +/delete-node/ &edma1; +/delete-node/ &emvsim0; +/delete-node/ &emvsim0_lpcg; +/delete-node/ &esai0; +/delete-node/ &esai0_lpcg; +/delete-node/ &sai4; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5; +/delete-node/ &sai5_lpcg; +/delete-node/ &spdif1; +/delete-node/ &spdif1_lpcg; + +&acm { + compatible = "nxp,imx8dxl-acm"; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; +}; + +&adc0 { + interrupts = ; +}; + &audio_ipg_clk { clock-frequency = <160000000>; }; @@ -11,42 +52,214 @@ clock-frequency = <160000000>; }; +&edma0 { + reg = <0x591f0000 0x10000>, + <0x59200000 0x10000>, /* asrc0 */ + <0x59210000 0x10000>, + <0x59220000 0x10000>, + <0x59230000 0x10000>, + <0x59240000 0x10000>, + <0x59250000 0x10000>, + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59300000 0x10000>, /* sai2 rx */ + <0x59310000 0x10000>, /* sai3 rx */ + <0x59350000 0x10000>, /* gpt0 */ + <0x59360000 0x10000>, /* gpt1 */ + <0x59370000 0x10000>, /* gpt2 */ + <0x59380000 0x10000>; /* gpt3 */ + interrupts = , /* asrc 0 */ + , + , + , + , + , + , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , /* sai2 */ + , /* sai3 */ + , /* gpt0 */ + , /* gpt1 */ + , /* gpt2 */ + ; /* gpt3 */ + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-tx", "edma0-chan5-tx", + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan16-rx", "edma0-chan17-rx", /* sai2, sai3 */ + "edma0-chan21-tx", /* gpt0 */ + "edma0-chan22-tx", /* gpt1 */ + "edma0-chan23-tx", /* gpt2 */ + "edma0-chan24-rx"; /* gpt3 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH22>, + <&pd IMX_SC_R_DMA_0_CH23>, + <&pd IMX_SC_R_DMA_0_CH24>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan2", "edma0-chan3", + "edma0-chan4", "edma0-chan5", + "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan16", "edma0-chan17", + "edma0-chan21", "edma0-chan22", + "edma0-chan23", "edma0-chan24"; +}; + +&edma2 { + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&edma3 { + interrupts = , + , + , + , + , + , + , + ; +}; + +&flexcan1 { + compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + interrupts = ; +}; + +&flexcan2 { + compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + interrupts = ; +}; + +&flexcan3 { + compatible = "fsl,imx8dxl-flexcan", "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + interrupts = ; +}; + &i2c0 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = ; + dma-names = "tx","rx"; + dmas = <&edma3 1 0 0>, <&edma3 0 0 1>; }; &i2c1 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = ; + dma-names = "tx","rx"; + dmas = <&edma3 3 0 0>, <&edma3 2 0 1>; }; &i2c2 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = ; + dma-names = "tx","rx"; + dmas = <&edma3 5 0 0>, <&edma3 4 0 1>; }; &i2c3 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = ; + dma-names = "tx","rx"; + dmas = <&edma3 7 0 0>, <&edma3 6 0 1>; +}; + +&lpspi0 { + compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi"; + interrupts = ; +}; + +&lpspi1 { + compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi"; + interrupts = ; +}; + +&lpspi2 { + compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi"; + interrupts = ; +}; + +&lpspi3 { + compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi"; + interrupts = ; }; &lpuart0 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; interrupts = ; }; &lpuart1 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; interrupts = ; }; &lpuart2 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; interrupts = ; }; &lpuart3 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; interrupts = ; }; + +&sai0 { + interrupts = ; +}; + +&sai1 { + interrupts = ; +}; + +&sai2 { + interrupts = ; +}; + +&sai3 { + interrupts = ; +}; + +&spdif0 { + interrupts = , /* rx */ + ; /* tx */ +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi 2024-06-19 12:33:58.280192223 +0200 @@ -5,6 +5,9 @@ /delete-node/ &enet1_lpcg; /delete-node/ &fec2; +/delete-node/ &usbotg3; +/delete-node/ &usb3_lpcg; +/delete-node/ &usb3_phy; &conn_subsys { conn_enet0_root_clk: clock-conn-enet0-root { @@ -21,15 +24,16 @@ interrupts = , ; interrupt-names = "eth_wake_irq", "macirq"; - clocks = <&eqos_lpcg IMX_LPCG_CLK_4>, - <&eqos_lpcg IMX_LPCG_CLK_6>, - <&eqos_lpcg IMX_LPCG_CLK_0>, - <&eqos_lpcg IMX_LPCG_CLK_5>, - <&eqos_lpcg IMX_LPCG_CLK_2>; + clocks = <&eqos_lpcg 2>, + <&eqos_lpcg 4>, + <&eqos_lpcg 0>, + <&eqos_lpcg 3>, + <&eqos_lpcg 1>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <125000000>; power-domains = <&pd IMX_SC_R_ENET_1>; + clk_csr = <0>; status = "disabled"; }; @@ -63,14 +67,14 @@ usbmisc2: usbmisc@5b0e0200 { #index-cells = <1>; - compatible = "fsl,imx7ulp-usbmisc"; + compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc"; reg = <0x5b0e0200 0x200>; }; - usbphy2: usbphy@0x5b110000 { + usbphy2: usbphy@5b110000 { compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy"; reg = <0x5b110000 0x1000>; - clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>; + clocks = <&usb2_2_lpcg 0>; power-domains = <&pd IMX_SC_R_USB_1_PHY>; status = "disabled"; }; @@ -84,9 +88,7 @@ <&conn_axi_clk>, <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>; - clock-indices = , , - , , - ; + bit-offset = <0 8 16 20 24>; clock-output-names = "eqos_ptp", "eqos_mem_clk", "eqos_aclk", @@ -99,7 +101,7 @@ compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b280000 0x10000>; #clock-cells = <1>; - clock-indices = ; + bit-offset = <28>; clocks = <&conn_ipg_clk>; clock-output-names = "usboh3_2_phy_ipg_clk"; power-domains = <&pd IMX_SC_R_USB_1_PHY>; @@ -107,6 +109,14 @@ }; +&dma_apbh { + compatible = "fsl,imx8dxl-dma-apbh", "fsl,imx28-dma-apbh"; + interrupts = , + , + , + ; +}; + &enet0_lpcg { clocks = <&conn_enet0_root_clk>, <&conn_enet0_root_clk>, @@ -117,7 +127,7 @@ }; &fec1 { - compatible = "fsl,imx8qm-fec"; + compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec"; interrupts = , , , @@ -126,6 +136,11 @@ assigned-clock-rates = <125000000>; }; +&gpmi { + compatible = "fsl,imx8dxl-gpmi-nand", "fsl,imx8qxp-gpmi-nand"; + interrupts = ; +}; + &usdhc1 { compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; interrupts = ; @@ -140,3 +155,14 @@ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; interrupts = ; }; + +&usbotg1 { + interrupts = ; + /* + * usbotg1 and usbotg2 share one clcok + * scfw disable clock access and keep it always on + * in case other core (M4) use one of these. + */ + clocks = <&clk_dummy>; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi 2024-06-19 12:33:58.280192223 +0200 @@ -4,6 +4,36 @@ */ &ddr_pmu0 { - compatible = "fsl,imx8-ddr-pmu"; + compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu"; interrupts = ; }; + +&ddr_subsys { + db_ipg_clk: clock-db-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <456000000>; + clock-output-names = "db_ipg_clk"; + }; + + db_pmu0: db-pmu@5ca40000 { + compatible = "fsl,imx8dxl-db-pmu"; + reg = <0x5ca40000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>; + clock-names = "ipg", "cnt"; + power-domains = <&pd IMX_SC_R_PERF>; + }; + + db_pmu0_lpcg: clock-controller@5cae0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5cae0000 0x10000>; + #clock-cells = <1>; + clocks = <&db_ipg_clk>, <&db_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "perf_lpcg_cnt_clk", + "perf_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_PERF>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +&hsio_subsys { + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refb_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + bit-offset = <0 4 8 16>; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; +}; + +&pcieb { + compatible = "fsl,imx8dxl-pcie", "fsl,imx8qxp-pcie", "snps,dw-pcie"; + interrupts = , + ; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 47 4>, + <0 0 0 2 &gic 0 48 4>, + <0 0 0 3 &gic 0 49 4>, + <0 0 0 4 &gic 0 50 4>; +}; + +&pcieb_ep { + compatible = "fsl,imx8qxp-pcie-ep"; + interrupts = ; + interrupt-names = "dma"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi 2024-06-19 12:33:58.280192223 +0200 @@ -2,49 +2,94 @@ /* * Copyright 2019~2020, 2022 NXP */ +&flexspi0 { + compatible = "nxp,imx8dxl-fspi"; + interrupts = ; +}; &lsio_gpio0 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 47 13>, + <&iomuxc 13 61 4>, + <&iomuxc 19 67 4>, + <&iomuxc 24 72 1>; }; &lsio_gpio1 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 4 74 5>, + <&iomuxc 9 80 16>; }; &lsio_gpio2 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 1 98 2>, + <&iomuxc 3 101 1>, + <&iomuxc 5 107 8>; }; &lsio_gpio3 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 115 4>, + <&iomuxc 9 121 1>, + <&iomuxc 10 120 1>, + <&iomuxc 11 123 1>, + <&iomuxc 12 122 1>, + <&iomuxc 13 125 1>, + <&iomuxc 14 124 1>, + <&iomuxc 16 126 1>, + <&iomuxc 17 128 1>, + <&iomuxc 18 131 1>, + <&iomuxc 19 130 1>, + <&iomuxc 20 133 1>, + <&iomuxc 21 132 1>, + <&iomuxc 22 129 1>, + <&iomuxc 23 134 1>; }; &lsio_gpio4 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 7 9 12>, + <&iomuxc 19 22 2>, + <&iomuxc 21 25 2>, + <&iomuxc 29 29 3>; }; &lsio_gpio5 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 32 3>, + <&iomuxc 3 36 6>, + <&iomuxc 9 43 3>; }; &lsio_gpio6 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 53 7>, + <&iomuxc 8 86 10>, + <&iomuxc 19 107 8>; }; &lsio_gpio7 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 8 22 2>, + <&iomuxc 10 25 2>, + <&iomuxc 16 44 2>; }; &lsio_mu0 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; interrupts = ; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxl-ss-security.dtsi 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +&sec_mu2 { + interrupts = ; +}; + +&sec_mu3 { + interrupts = ; +}; + +&sec_mu4 { + interrupts = ; +}; + +&sec_jr2 { + interrupts = ; +}; + +&sec_jr3 { + interrupts = ; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8dx-mek.dts" + +/delete-node/ &adv_bridge0; +/delete-node/ &adv_bridge1; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&lvds_bridge0 { + status = "disabled"; +}; + +&lvds_bridge1 { + status = "disabled"; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&mipi0_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi0_panel_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel1_in: endpoint { + remote-endpoint = <&mipi1_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi1_panel_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-dsi-rm67191-rpmsg.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-dsi-rm67191.dts" +#include "imx8x-mek-rpmsg.dtsi" + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; +#include "imx8dx.dtsi" +#include "imx8x-mek.dtsi" + +/ { + model = "Freescale i.MX8DX MEK"; + compatible = "fsl,imx8dx-mek", "fsl,imx8dx", "fsl,imx8qxp"; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x96000000 0 0x14000000>; + linux,cma-default; + }; + }; +}; + +&thermal_zones { + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&imx8_gpu_ss { + reg = <0x80000000 0x40000000>, <0x0 0x08000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; +}; \ No newline at end of file diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-enet2-tja1100.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8qxp-enet2-tja1100.dtsi" + +&esai0 { + status = "disabled"; +}; + +&fec2 { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 + +#include "imx8dx-mek.dts" + +&isi_1 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_2 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_3 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; + +&i2c_mipi_csi0 { + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 8 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-ov5640-rpmsg.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 +#include "imx8dx-mek-ov5640.dts" +#include "imx8x-mek-rpmsg.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-rpmsg.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxp.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxp.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxp.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxp.dtsi 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp.dtsi" + +&thermal_zones { + cpu0-thermal { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8dxp-lpddr4-val.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8dxp.dtsi" +#include "imx8x-val.dtsi" + +/ { + model = "Freescale i.MX8DXP VALIDATION"; + compatible = "fsl,imx8dxp-val", "fsl,imx8dxp", "fsl,imx8qxp"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" +#include "imx8mm-ab2.dtsi" + +/ { + model = "FSL i.MX8MM Audio board 2.0"; + compatible = "fsl,imx8mm-ab2", "fsl,imx8mm"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ab2.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ab2.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ab2.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ab2.dtsi 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/ { + /delete-node/ ir-receiver; + /delete-node/ audio-codec; + /delete-node/ regulator-audio-board; + /delete-node/ regulator-pcie; + /delete-node/ sound-wm8524; + /delete-node/ sound-ak5558; + /delete-node/ sound-ak4497; + /delete-node/ sound-micfil; + + ak4458_reset: gpio-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + #reset-cells = <0>; + initially-in-reset; + }; + + leds { + panel { + label = "green:panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + reg_adc_dvdd_3v3: reg-adc-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "ADC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_adc_avdd_5v0: reg-adc-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ADC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_dvdd_3v3: reg-dac-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "DAC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_avdd_5v0: reg-dac-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "DAC_AVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_cph_3v3: reg-cph-3v3 { + compatible = "regulator-fixed"; + regulator-name = "CPH_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_vdd_pwr_5v0>; + }; + + reg_cph_1v8: reg-cph-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CPH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_cph_3v3>; + }; + + reg_pcie0: regulator-pcie { + status = "disabled"; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-card"; + model = "ak4458-audio"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai1>; + }; + codec { + sound-codec = <&ak4458_1>, <&ak4458_2>; + }; + }; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-card"; + model = "ak5552-audio"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai5>; + }; + codec { + sound-dai = <&ak5552>; + }; + }; + }; +}; + +&csi1_bridge { + status = "disabled"; + /delete-node/ port; +}; + +&fec1 { + mdio { + ethphy0: ethernet-phy@0 { + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + reset-deassert-us = <150000>; + reset-assert-us = <15000>; + max-speed = <100>; + }; + }; +}; + +&i2c2 { + /delete-node/ adv7535@3d; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; + }; + + ptn5110: tcpc@50 { + status = "disabled"; + /delete-node/ port; + }; + + ptn5150: tcpc@1d { + compatible = "nxp,ptn5150"; + reg = <0x1d>; + status = "okay"; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&i2c3 { + /delete-node/ ak5558@13; + /delete-node/ ak4497@11; + /delete-node/ ov5640_mipi@3c; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5_reg>; + }; + + ak4458_1: ak4458@10 { + #sound-dai-cells = <0>; + sound-name-prefix = "0"; + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + resets = <&ak4458_reset>; + AVDD-supply = <®_dac_avdd_5v0>; + DVDD-supply = <®_dac_dvdd_3v3>; + status = "okay"; + }; + + ak4458_2: ak4458@12 { + #sound-dai-cells = <0>; + sound-name-prefix = "1"; + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + resets = <&ak4458_reset>; + AVDD-supply = <®_dac_avdd_5v0>; + DVDD-supply = <®_dac_dvdd_3v3>; + status = "okay"; + }; + + ak4458_3: ak4458@11 { + #sound-dai-cells = <0>; + sound-name-prefix = "2"; + compatible = "asahi-kasei,ak4458"; + reg = <0x11>; + resets = <&ak4458_reset>; + AVDD-supply = <®_dac_avdd_5v0>; + DVDD-supply = <®_dac_dvdd_3v3>; + status = "disabled"; + }; + + ak5552: ak5552@13 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>; + AVDD-supply = <®_adc_avdd_5v0>; + DVDD-supply = <®_adc_dvdd_3v3>; + status = "okay"; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "disabled"; +}; + +&iomuxc { + /delete-node/ csi_pwn_grp; + /delete-node/ csi_rst_grp; + /delete-node/ pcie0reggrp; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ENET_PHY_RST_B */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* ENET_PHY_INT_B */ + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&mipi_csi_1 { + status = "disabled"; + /delete-node/ port; +}; + +&mipi_dsi { + status = "disabled"; + /delete-node/ port@1; +}; + +&pcie_phy { + status = "disabled"; +}; + +&pcie0 { + status = "disabled"; + /delete-property/ pinctrl-0; +}; + +&pcie0_ep { + status = "disabled"; + /delete-property/ pinctrl-0; +}; + +&sai1 { + fsl,dataline = <0 0xff 0xff>; +}; + +&sai3 { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + /delete-property/ usb-role-switch; + /delete-node/ port; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ab2.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@80000000 { + reg = <0 0x80000000 0 0x0101E400>; + no-map; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc-table { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + leds { + panel { + status = "disabled"; + }; + }; + + bt_sco_codec: bt_sco_codec { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + syscon = <&src>; + }; +}; + +&clk { + init-on-array = < + IMX8MM_CLK_UART4_ROOT + IMX8MM_CLK_AHB IMX8MM_CLK_DRAM_CORE + IMX8MM_CLK_NOC IMX8MM_CLK_NOC_APB + IMX8MM_CLK_MAIN_AXI IMX8MM_CLK_AUDIO_AHB + IMX8MM_CLK_DRAM_APB IMX8MM_CLK_A53_DIV + IMX8MM_ARM_PLL_OUT + >; +}; + +&i2c2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-evk.dts" +#include "imx8mm-ab2.dtsi" + +/ { + model = "FSL i.MX8MM DDR4 Audio Board 2.0"; + compatible = "fsl,imx8mm-ddr4-ab2", "fsl,imx8mm"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-ab2.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@80000000 { + reg = <0 0x80000000 0 0x0101E400>; + no-map; + }; + + vdev0vring0: vdev0vring0@b8000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc-table { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + leds { + panel { + status = "disabled"; + }; + }; + + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>; + syscon = <&src>; + }; +}; + +&clk { + init-on-array = < + IMX8MM_CLK_UART4_ROOT + IMX8MM_CLK_AHB IMX8MM_CLK_DRAM_CORE + IMX8MM_CLK_NOC IMX8MM_CLK_NOC_APB + IMX8MM_CLK_MAIN_AXI IMX8MM_CLK_AUDIO_AHB + IMX8MM_CLK_DRAM_APB IMX8MM_CLK_A53_DIV + IMX8MM_ARM_PLL_OUT + >; +}; + +&i2c2 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-ab2-m4.dts" + +/ { + model = "FSL i.MX8MM DDR4 RevB Audio Board 2.0"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0 { + ext_osc = <0>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-ab2.dts" + +/ { + model = "FSL i.MX8MM DDR4 RevB Audio Board 2.0"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0 { + ext_osc = <0>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts 2024-06-19 12:33:58.280192223 +0200 @@ -18,6 +18,133 @@ gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; }; }; + + reg_usdhc1_vmmc: regulator-usdhc1 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc1_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/delete-node/&pmic_nxp; + +&i2c1 { + pmic_rohm: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &gpmi { @@ -25,9 +152,40 @@ pinctrl-0 = <&pinctrl_gpmi_nand>; nand-on-flash-bbt; status = "okay"; + fsl,use-minimum-ecc; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + cap-power-off-card; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + vmmc-supply = <®_usdhc1_vmmc>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; }; &iomuxc { + pinctrl_reg_usdhc1_vmmc: regusdhc1vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x141 + >; + }; + pinctrl_gpmi_nand: gpmi-nand { fsl,pins = < MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 @@ -54,4 +212,11 @@ MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 >; }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-inmate.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-inmate.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-inmate.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-inmate.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm.dtsi" + +/ { + model = "Freescale i.MX8MM EVK"; + compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + interrupt-parent = <&gic>; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + clk_100m: clock@11 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "100m"; + }; + + display-subsystem { + /delete-property/ compatible; + }; + + pci@bb800000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbb800000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; +}; + +/delete-node/ &{/reserved-memory}; +/delete-node/ &{/busfreq}; +/delete-node/ &{/soc@0/ddr-pmu@3d800000}; + +&gpc { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; +&gpio2 { + status = "disabled"; +}; +&gpio3 { + status = "disabled"; +}; +&gpio4 { + status = "disabled"; +}; +&gpio5 { + status = "disabled"; +}; + +/delete-node/ &tmu; +/delete-node/ &{/thermal-zones}; +&iomuxc { + status = "disabled"; +}; + +&gpr { + /delete-property/ compatible; +}; + +/delete-node/ &anatop; +/delete-node/ &snvs; + +&clk { + /delete-property/ compatible; +}; + +&src { + /delete-property/ compatible; +}; + +/delete-node/ &system_counter; + +&ocotp { + /delete-property/ compatible; + status = "disabled"; +}; + +&sdma1 { + status = "disabled"; +}; + +&sdma2 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +/*/delete-node/ &{/imx_ion};*/ +/delete-node/ &pcie0; +/delete-node/ &crypto; +/delete-node/ &caam_sm; +/delete-node/ &caam_snvs; +/delete-node/ &irq_sec_vio; + +/delete-node/ &{/cpus/cpu@0}; +/delete-node/ &{/cpus/cpu@1}; +/delete-node/ &{/pmu}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&dma_apbh { + clocks = <&clk_266m>; + status = "okay"; +}; + +&gpmi { + clocks = <&clk_100m>, + <&clk_266m>; + status = "okay"; + nand-on-flash-bbt; + fsl,use-minimum-ecc; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-pcie-ep.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie0_ep{ + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm-ddr4-evk.dts" + +/ { + model = "FSL i.MX8MM DDR4 EVK RevB board"; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0{ + ext_osc = <0>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191-cmd-ram.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191-cmd-ram.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191-cmd-ram.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191-cmd-ram.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mm-ddr4-evk-revb-rm67191.dts" + +&mipi_dsi { + panel@0 { + video-mode = <3>; /* command mode */ + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67191.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019,2021 NXP + */ + +#include "imx8mm-ddr4-evk-revb.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + * 3: command mode + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts: synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67199-cmd-ram.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67199-cmd-ram.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67199-cmd-ram.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67199-cmd-ram.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mm-ddr4-evk-revb-rm67199.dts" + +&mipi_dsi { + panel@0 { + video-mode = <3>; /* command mode */ + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-revb-rm67199.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mm-ddr4-evk-revb-rm67191.dts" + +/delete-node/ &synaptics_dsx_ts; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&i2c2 { + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + edge-failling-trigger; + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191-cmd-ram.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191-cmd-ram.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191-cmd-ram.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191-cmd-ram.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mm-ddr4-evk-rm67191.dts" + +&mipi_dsi { + panel@0 { + video-mode = <3>; /* command mode */ + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67191.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019,2021 NXP + */ + +#include "imx8mm-ddr4-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + * 3: command mode + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts: synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67199-cmd-ram.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67199-cmd-ram.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67199-cmd-ram.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67199-cmd-ram.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mm-ddr4-evk-rm67199.dts" + +&mipi_dsi { + panel@0 { + video-mode = <3>; /* command mode */ + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-rm67199.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mm-ddr4-evk-rm67191.dts" + +/delete-node/ &synaptics_dsx_ts; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&i2c2 { + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + edge-failling-trigger; + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-root.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-root.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-root.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk-root.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-ddr4-evk.dts" + +/ { + interrupt-parent = <&gic>; +}; + +&cpu_pd_wait { + /delete-property/ compatible; + /*arm,psci-suspend-param = <0x0>;*/ +}; + +&clk { + init-on-array = ; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&{/reserved-memory} { + + ivshmem_reserved: ivshmem@bbb00000 { + no-map; + reg = <0 0xbbb00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@bba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00100000>; + }; + + pci_reserved: pci@bb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@bb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@b7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x24000000>; + }; +}; + +&uart2 { + /* uart2 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>, <&pinctrl_gpmi_nand>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; + +&dma_apbh { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm.dtsi 2024-06-19 12:33:58.288192361 +0200 @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,11 @@ mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; + sai1 = &sai1; + sai2 = &sai2; + sai3 = &sai3; + sai5 = &sai5; + sai6 = &sai6; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -174,6 +180,21 @@ }; }; + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x80000000 0 0x40000000>; + linux,cma-default; + }; + }; + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -277,6 +298,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; power-domains = <&pgc_otg1>; + wakeup-source; }; usbphynop2: usbphynop2 { @@ -287,10 +309,30 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; power-domains = <&pgc_otg2>; + wakeup-source; + }; + + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MM_DRAM_PLL_OUT>, <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>, <&clk IMX8MM_CLK_DRAM_APB>, + <&clk IMX8MM_CLK_DRAM_CORE>, <&clk IMX8MM_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>, + <&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC>, + <&clk IMX8MM_CLK_AHB>, <&clk IMX8MM_CLK_MAIN_AXI>, + <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + interrupts = , , + , ; + interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; }; soc: soc@0 { - compatible = "fsl,imx8mm-soc", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; @@ -298,6 +340,11 @@ nvmem-cells = <&imx8mm_uid>; nvmem-cell-names = "soc_unique_id"; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -317,12 +364,13 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30010000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI1_IPG>, + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; dma-names = "rx", "tx"; + fsl,dataline = <0 0xff 0xff>; status = "disabled"; }; @@ -331,10 +379,10 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI2_IPG>, + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI2_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -345,10 +393,10 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI3_IPG>, + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -359,12 +407,13 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI5_IPG>, + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; dma-names = "rx", "tx"; + fsl,dataline = <0 0xf 0xf>; status = "disabled"; }; @@ -373,10 +422,10 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI6_IPG>, + clocks = <&clk IMX8MM_CLK_SAI6_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI6_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -555,7 +604,7 @@ }; ocotp: efuse@30350000 { - compatible = "fsl,imx8mm-ocotp", "syscon"; + compatible = "fsl,imx8mm-ocotp", "syscon", "simple-mfd"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; /* For nvmem subnodes */ @@ -573,6 +622,12 @@ fec_mac_address: mac-address@90 { reg = <0x90 6>; }; + + imx8mm_soc: imx8mm-soc { + compatible = "fsl,imx8mm-soc"; + nvmem-cells = <&imx8mm_uid>; + nvmem-cell-names = "soc_unique_id"; + }; }; anatop: anatop@30360000 { @@ -580,6 +635,22 @@ reg = <0x30360000 0x10000>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -626,7 +697,8 @@ <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, <&clk IMX8MM_VIDEO_PLL1>, - <&clk IMX8MM_AUDIO_PLL1>; + <&clk IMX8MM_AUDIO_PLL1>, + <&clk IMX8MM_AUDIO_PLL2>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, <&clk IMX8MM_ARM_PLL_OUT>, <&clk IMX8MM_SYS_PLL3_OUT>, @@ -635,8 +707,9 @@ <400000000>, <400000000>, <750000000>, - <594000000>, - <393216000>; + <1039500000>, + <393216000>, + <361267200>; }; src: reset-controller@30390000 { @@ -1098,20 +1171,85 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; - csi: csi@32e20000 { - compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; + lcdif: lcdif@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rate = <594000000>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: mipi_dsi@32e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "cfg", "pll-ref", "apb-root"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <266000000>, <12000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + csi1_bridge: csi1_bridge@32e20000 { + compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi"; reg = <0x32e20000 0x1000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; - clock-names = "mclk"; + clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>; status = "disabled"; + }; - port { - csi_in: endpoint { - remote-endpoint = <&imx8mm_mipi_csi_out>; - }; - }; + mipi_csi_1: mipi_csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi"; + reg = <0x32e30000 0x1000>; + interrupts = ; + clock-frequency = <333000000>; + clocks = <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; + bus-width = <4>; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; }; disp_blk_ctrl: blk-ctrl@32e28000 { @@ -1141,38 +1279,9 @@ #power-domain-cells = <1>; }; - mipi_csi: mipi-csi@32e30000 { - compatible = "fsl,imx8mm-mipi-csi2"; - reg = <0x32e30000 0x1000>; - interrupts = ; - assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>; - - clock-frequency = <333000000>; - clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, - <&clk IMX8MM_CLK_CSI1_ROOT>, - <&clk IMX8MM_CLK_CSI1_PHY_REF>, - <&clk IMX8MM_CLK_DISP_AXI_ROOT>; - clock-names = "pclk", "wrap", "phy", "axi"; - power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - - imx8mm_mipi_csi_out: endpoint { - remote-endpoint = <&csi_in>; - }; - }; - }; + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp0>; }; usbotg1: usb@32e40000 { @@ -1290,51 +1399,24 @@ status = "disabled"; }; - gpu_3d: gpu@38000000 { - compatible = "vivante,gc"; - reg = <0x38000000 0x8000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_GPU_AHB>, - <&clk IMX8MM_CLK_GPU_BUS_ROOT>, - <&clk IMX8MM_CLK_GPU3D_ROOT>, - <&clk IMX8MM_CLK_GPU3D_ROOT>; - clock-names = "reg", "bus", "core", "shader"; - assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, - <&clk IMX8MM_GPU_PLL_OUT>; - assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; - assigned-clock-rates = <0>, <1000000000>; - power-domains = <&pgc_gpu>; - }; - - gpu_2d: gpu@38008000 { - compatible = "vivante,gc"; - reg = <0x38008000 0x8000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_GPU_AHB>, - <&clk IMX8MM_CLK_GPU_BUS_ROOT>, - <&clk IMX8MM_CLK_GPU2D_ROOT>; - clock-names = "reg", "bus", "core"; - assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, - <&clk IMX8MM_GPU_PLL_OUT>; - assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; - assigned-clock-rates = <0>, <1000000000>; - power-domains = <&pgc_gpu>; - }; - - vpu_g1: video-codec@38300000 { - compatible = "nxp,imx8mm-vpu-g1"; - reg = <0x38300000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; - power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; - }; - - vpu_g2: video-codec@38310000 { - compatible = "nxp,imx8mq-vpu-g2"; - reg = <0x38310000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; - power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; + pcie0_ep: pcie_ep@33800000 { + compatible = "fsl,imx8mm-pcie-ep"; + reg = <0x33800000 0x000400000>, + <0x18000000 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; }; vpu_blk_ctrl: blk-ctrl@38330000 { @@ -1365,20 +1447,96 @@ interrupts = ; }; - ddrc: memory-controller@3d400000 { - compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; - reg = <0x3d400000 0x400000>; - clock-names = "core", "pll", "alt", "apb"; - clocks = <&clk IMX8MM_CLK_DRAM_CORE>, - <&clk IMX8MM_DRAM_PLL>, - <&clk IMX8MM_CLK_DRAM_ALT>, - <&clk IMX8MM_CLK_DRAM_APB>; - }; - ddr-pmu@3d800000 { compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; interrupts = ; }; }; + + vpu_h1: vpu_h1@38320000 { + compatible = "nxp,imx8mm-hantro-h1"; + reg = <0x0 0x38320000 0x0 0x10000>; + reg-names = "regs_hantro_h1"; + interrupts = ; + interrupt-names = "irq_hantro_h1"; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro_h1", "clk_hantro_h1_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_H1>,<&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_H1>; + status = "disabled"; + }; + + vpu_g1: vpu_g1@38300000 { + compatible = "nxp,imx8mm-hantro"; + reg = <0x0 0x38300000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, <&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; + status = "disabled"; + }; + + vpu_g2: vpu_g2@38310000 { + compatible = "nxp,imx8mm-hantro"; + reg = <0x0 0x38310000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G2>, <&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; + status = "disabled"; + }; + + vpu_v4l2: vpu_v4l2 { + compatible = "nxp,imx8m-vsiv4l2"; + status = "disabled"; + }; + + gpu: gpu@38000000 { + compatible ="fsl,imx8mm-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0x0 0x8000>, <0x0 0x38008000 0x0 0x8000>, + <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = , + ; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", + "gpu3d_axi_clk", "gpu3d_ahb_clk", + "gpu2d_clk", "gpu2d_axi_clk", + "gpu2d_ahb_clk"; + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, + <&clk IMX8MM_CLK_GPU2D_SRC>, + <&clk IMX8MM_CLK_GPU_AXI>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>, + <&clk IMX8MM_GPU_PLL_OUT>, + <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <0>,<400000000>,<1000000000>; + + power-domains = <&pgc_gpu>; + + status = "disabled"; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-revE.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk.dts" + +/ { + mic_leds { + compatible = "gpio-leds"; + mic0 { + label = "mic0"; + gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic1 { + label = "mic1"; + gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic2 { + label = "mic2"; + gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic3 { + label = "mic3"; + gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic4 { + label = "mic4"; + gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic5 { + label = "mic5"; + gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic6 { + label = "mic6"; + gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic7 { + label = "mic7"; + gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sw_keys { + compatible = "gpio-keys"; + + sw4: volume_down { + label = "Volume Down"; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; + + sw3: volume_up { + label = "Volume Up"; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + }; + + sw2: volume_mute { + label = "Volume Mute"; + gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; + + sw1: key_act { + label = "Key Act"; + gpios = <&pca9555 12 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + reg_vddext_3v3: regulator-vddext { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&iomuxc { + pinctrl_swpdm_mute_irq: swpdm_mute_grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x19 + >; + }; + + pinctrl_pushbutton_irq: pushbutton_grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; +}; + +&i2c3 { + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pushbutton_irq>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_vddext_3v3>; + status = "okay"; + }; + + pca995btw: pca9955btw@7 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9955btw"; + reg = <0x07>; + led0 { + label = "green0"; + linux,default-trigger = "none"; + reg = <0>; + }; + + led1 { + label = "blue0"; + linux,default-trigger = "none"; + reg = <1>; + }; + + led2 { + label = "red0"; + linux,default-trigger = "none"; + reg = <2>; + }; + + led3 { + label = "green1"; + linux,default-trigger = "none"; + reg = <3>; + }; + + led4 { + label = "blue1"; + linux,default-trigger = "none"; + reg = <4>; + }; + + led5 { + label = "red1"; + linux,default-trigger = "none"; + reg = <5>; + }; + + led6 { + label = "green2"; + linux,default-trigger = "none"; + reg = <6>; + }; + + led7 { + label = "blue2"; + linux,default-trigger = "none"; + reg = <7>; + }; + + led8 { + label = "red2"; + linux,default-trigger = "none"; + reg = <8>; + }; + + led9 { + label = "green3"; + linux,default-trigger = "none"; + reg = <9>; + }; + + led10 { + label = "blue3"; + linux,default-trigger = "none"; + reg = <10>; + }; + + led11 { + label = "red3"; + linux,default-trigger = "none"; + reg = <11>; + }; + }; +}; + +&uart3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-8mic-swpdm.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk-8mic-revE.dts" + +/ { + sound-micfil { + status = "disabled"; + }; + + dmic: dmic { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + wakeup-delay-ms = <250>; + }; + + sound-swpdm { + compatible = "fsl,imx-audio-card"; + model = "imx-swpdm-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swpdm_mute_irq>; + pri-dai-link { + link-name = "PDM PCM"; + format = "pdm"; + cpu { + sound-dai = <&sai5>; + }; + codec { + sound-dai = <&dmic>; + }; + }; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + /delete-property/ fsl,sai-multi-lane; + dmas = <&sdma2 8 24 0>, <&sdma2 9 24 0>; + assigned-clock-rates = <24576000>; + fsl,dataline = <2 0xf 0xf>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-ak4497.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-evk.dts" + +/ { + sound-ak4458 { + status = "disabled"; + }; + + sound-ak4497 { + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <22579200>; + fsl,sai-multi-lane; + fsl,dataline = <2 0xff 0x11>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-ak5558.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + + +#include "imx8mm-evk.dts" + +/ { + sound-ak5558 { + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-audio-tdm.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,33 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mm-evk-ak5558.dts" + +/ { + sound-ak4458 { + pri-dai-link { + format = "dsp_b"; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + }; + }; + + sound-ak5558 { + pri-dai-link { + format = "dsp_b"; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-dpdk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-dpdk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-dpdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-dpdk.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mm-evk.dts" + +ðphy0 { + /delete-property/ reset-assert-us; + /delete-property/ reset-deassert-us; +}; + +&fec1 { + compatible = "fsl,imx8mm-fec-uio"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk.dts 2024-06-19 12:33:58.284192293 +0200 @@ -15,25 +15,16 @@ aliases { spi0 = &flexspi; }; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; + reg_usdhc1_vmmc: regulator-usdhc1 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc1_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; @@ -53,6 +44,27 @@ }; }; +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + vmmc-supply = <®_usdhc1_vmmc>; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + &usdhc3 { assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; assigned-clock-rates = <400000000>; @@ -66,6 +78,12 @@ }; &iomuxc { + pinctrl_reg_usdhc1_vmmc: regusdhc1vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x141 + >; + }; + pinctrl_flexspi: flexspigrp { fsl,pins = < MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 @@ -125,4 +143,11 @@ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 >; }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x159 + >; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi 2024-06-19 12:33:58.284192293 +0200 @@ -19,6 +19,14 @@ reg = <0x0 0x40000000 0 0x80000000>; }; + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + linux,autosuspend-period = <125>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -37,6 +45,17 @@ clock-frequency = <100000000>; }; + reg_audio_board: regulator-audio-board { + compatible = "regulator-fixed"; + regulator-name = "EXT_PWREN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <300000>; + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + reg_pcie0: regulator-pcie { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -56,6 +75,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -131,6 +151,76 @@ clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; }; }; + + sound-ak4458 { + compatible = "fsl,imx-audio-card"; + model = "ak4458-audio"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai1>; + }; + codec { + sound-dai = <&ak4458_1>, <&ak4458_2>; + }; + }; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-card"; + model = "ak5558-audio"; + status = "disabled"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai5>; + }; + codec { + sound-dai = <&ak5558>; + }; + }; + }; + + sound-ak4497 { + compatible = "fsl,imx-audio-card"; + model = "ak4497-audio"; + status = "disabled"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai1>; + }; + codec { + sound-dai = <&ak4497>; + }; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; }; &A53_0 { @@ -149,6 +239,32 @@ cpu-supply = <&buck2_reg>; }; +&csi1_bridge { + fsl,mipi-mode; + status = "okay"; + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -166,6 +282,9 @@ reg = <0>; reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,aldps-enable; + realtek,clkout-disable; qca,disable-smarteee; vddio-supply = <&vddio>; @@ -183,78 +302,69 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; + pmic_nxp: pca9450@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; interrupt-parent = <&gpio1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k>; - clock-output-names = "clk-32k-out"; regulators { buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <850000>; + nxp,dvs-standby-voltage = <800000>; }; buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; + regulator-ramp-delay = <3125>; }; buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; + regulator-name = "BUCK3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; }; buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; ldo1_reg: LDO1 { - regulator-name = "ldo1"; + regulator-name = "LDO1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -262,35 +372,33 @@ }; ldo2_reg: LDO2 { - regulator-name = "ldo2"; + regulator-name = "LDO2"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; + regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; }; }; }; @@ -302,6 +410,25 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + adv_bridge: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + ptn5110: tcpc@50 { compatible = "nxp,ptn5110"; pinctrl-names = "default"; @@ -333,7 +460,7 @@ }; &i2c3 { - clock-frequency = <400000>; + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; @@ -343,7 +470,111 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; }; + + ak4458_1: ak4458@10 { + #sound-dai-cells = <0>; + sound-name-prefix = "0"; + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4458_2: ak4458@12 { + #sound-dai-cells = <0>; + sound-name-prefix = "1"; + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak5558: ak5558@13 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4497: ak4497@11 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + reset-gpios = <&pca6416 5 GPIO_ACTIVE_LOW>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + dsd-path = <1>; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MM_CLK_CLKO1>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi1_sensor_ep: endpoint@1 { + remote-endpoint = <&ov5640_mipi1_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + + csi1_mipi_ep: endpoint@2 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MM_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; }; &pcie_phy { @@ -370,6 +601,18 @@ status = "okay"; }; +&pcie0_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + ext_osc = <1>; + status = "disabled"; +}; + &sai2 { #sound-dai-cells = <0>; pinctrl-names = "default"; @@ -377,6 +620,26 @@ assigned-clocks = <&clk IMX8MM_CLK_SAI2>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default", "dsd"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,sai-mclk-direction-output; + fsl,dataline = <0 0xff 0xff 2 0xff 0x11>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; status = "okay"; }; @@ -386,6 +649,31 @@ assigned-clocks = <&clk IMX8MM_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + fsl,sai-multi-lane; + fsl,sai-mclk-direction-output; + dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; + status = "disabled"; +}; + +&sai6 { + fsl,sai-monitor-spdif; + fsl,sai-asynchronous; status = "okay"; }; @@ -393,12 +681,51 @@ status = "okay"; }; +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -430,6 +757,22 @@ status = "okay"; }; +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_h1 { + status = "okay"; +}; + +&vpu_v4l2 { + status = "okay"; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -440,10 +783,46 @@ &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; +}; + +&gpu { status = "okay"; }; &iomuxc { + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -496,6 +875,12 @@ >; }; + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* Touch int */ + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -503,6 +888,12 @@ >; }; + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 @@ -516,6 +907,18 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 @@ -528,6 +931,40 @@ >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + pinctrl_sai2: sai2grp { fsl,pins = < MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 @@ -546,12 +983,40 @@ >; }; + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + pinctrl_typec1: typec1grp { fsl,pins = < MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 @@ -559,6 +1024,48 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-ecspi-slave.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-ecspi-slave.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-ecspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-ecspi-slave.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2020 NXP + +#include "imx8mm-evk.dts" + +/delete-node/&spidev0; + +&ecspi2 { + #address-cells = <0>; + /delete-property/cs-gpios; + spi-slave; +}; + +&pinctrl_ecspi2_cs { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x82 + >; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dac2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dac2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dac2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dac2.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP. + */ + +#include "imx8mm-evk-hifiberry-dacplus.dts" + +/ { + sound-pcm512x { + audio-widgets = + "Headphone", "Headphone Jack", + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + aux-devs= <&headphone_amp>; + }; +}; + +&i2c3 { + headphone_amp: amp@60 { + compatible = "ti,tpa6130a2"; + Vdd-supply = <®_3v3_vext>; + reg = <0x60>; + status = "okay"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplusadc.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplusadc.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplusadc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplusadc.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP. + */ + +#include "imx8mm-evk-hifiberry-dacplus.dts" + +/ { + sound-pcm512x { + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack", + "Line", "ADC1", + "Line", "ADC2"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR", + "VINL1", "ADC1", + "VINR1", "ADC2"; + adc,pluspro; + + pri-dai-link { + sndcodec: codec { + sound-dai = <&pcm512x>, <&pcm186x>; + }; + }; + }; +}; + +&i2c3 { + pcm186x: pcm186x@4a { + compatible = "ti,pcm1863"; + reg = <0x4a>; + iovdd-supply = <®_3v3_vext>; + avdd-supply = <®_3v3_vext>; + dvdd-supply = <®_3v3_vext>; + #sound-dai-cells = <0>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplus.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplus.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplus.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-hifiberry-dacplus.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mm-evk.dts" + +/ { + ext_osc_22m: ext-osc-22m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + clock-output-names = "sclk0"; + }; + + ext_osc_24m: ext-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-output-names = "sclk1"; + }; + + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-ak4458 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + dac,24db_digital_gain; + dac,led_status; + dac,sclk; + + pri-dai-link { + link-name = "pcm512x-hifi"; + format = "i2s"; + bitclock-master = <&sndcodec>; + frame-master = <&sndcodec>; + cpu { + sound-dai = <&sai5>; + }; + sndcodec: codec { + sound-dai = <&pcm512x>; + }; + }; + }; +}; + +&i2c3 { + ak4458_1: ak4458@10 { + status = "disabled"; + }; + + ak4458_2: ak4458@12 { + status = "disabled"; + }; + + ak5558: ak5558@13 { + status = "disabled"; + }; + + ak4497: ak4497@11 { + status = "disabled"; + }; + + pcm512x: pcm512x@4d { + compatible = "ti,pcm5122"; + reg = <0x4d>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + clocks = <&ext_osc_22m>, <&ext_osc_24m>; + clock-names = "sclk0", "sclk1"; + #sound-dai-cells = <0>; + }; +}; + +&iomuxc { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + #sound-dai-cells = <0>; + /delete-property/ fsl,sai-asynchronous; + /delete-property/ fsl,sai-multi-lane; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-inmate.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include + +/ { + model = "Freescale i.MX8MM EVK"; + compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&A53_2>, <&A53_3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_200m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + pci@bb800000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbb800000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + aips3: bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x8000000 0x8000000 0x10000000>; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_200m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacplus.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacplus.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacplus.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacplus.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mm-evk.dts" + +/ { + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-ak4458 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + dac,24db_digital_gain; + + pri-dai-link { + link-name = "pcm512x-hifi"; + format = "i2s"; + cpu { + sound-dai = <&sai5>; + }; + + codec { + sound-dai = <&pcm512x>; + }; + }; + }; +}; + +&i2c3 { + ak4458_1: ak4458@10 { + status = "disabled"; + }; + + ak4458_2: ak4458@12 { + status = "disabled"; + }; + + ak4497: ak4497@11 { + status = "disabled"; + }; + + pcm512x: pcm512x@4c { + compatible = "ti,pcm5122"; + reg = <0x4c>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + #sound-dai-cells = <0>; + }; +}; + +&iomuxc { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + #sound-dai-cells = <0>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacpro.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacpro.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacpro.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-iqaudio-dacpro.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mm-evk-iqaudio-dacplus.dts" + +&i2c3 { + pcm512x: pcm512x@4c { + compatible = "ti,pcm5142"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-lk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-lk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-lk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-lk.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019-2021 NXP + */ + +#include "imx8mm-evk.dts" + +/ { + interrupt-parent = <&gic>; + + ivshm_rpmsg { + compatible = "fsl,ivshm-rpmsg"; + + rpmsg_console { + compatible = "fsl,rpmsg-console"; + id = <2>; + size = <16384>; + }; + }; +}; + +&cpu_pd_wait { + /delete-property/ compatible; + /*arm,psci-suspend-param = <0x0>;*/ +}; + +&clk { + init-on-array = ; +}; + +&gpio5 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&{/reserved-memory} { + ivshmem_reserved: ivshmem@bba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00400000>; + }; + + pci_reserved: pci@bb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@bb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@b7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x20000000>; + }; +}; + +&sai3 { + status = "disabled"; +}; + +&sai5 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +&spdif1 { + status = "disabled"; +}; + +&{/reserved-memory/linux,cma} { + alloc-ranges = <0 0x40000000 0 0x60000000>; +}; + +&uart2 { + /* uart2 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + /* sdhc3 is used by 2nd linux, configure the pin */ + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-pcie-ep.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie0_ep{ + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-qca-wifi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-qca-wifi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-qca-wifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-qca-wifi.dts 2024-06-19 12:33:58.280192223 +0200 @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +/ { + model = "FSL i.MX8MM LPDDR4 EVK with QCA WIFI revC board "; +}; + +/delete-node/&pmic_nxp; + +&i2c1 { + pmic_rohm: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-revb-qca-wifi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-revb-qca-wifi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-revb-qca-wifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-revb-qca-wifi.dts 2024-06-19 12:33:58.284192293 +0200 @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk-qca-wifi.dts" + +/ { + model = "FSL i.MX8MM LPDDR4 EVK with QCA WIFI revB board "; +}; + +/* + * External OSC is used as PCIe REFCLK on RevC board. + * Use the -revb.dts file to distiguish the different + * HW design. + */ +&pcie0{ + ext_osc = <0>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191-cmd-ram.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191-cmd-ram.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191-cmd-ram.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191-cmd-ram.dts 2024-06-19 12:33:58.284192293 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mm-evk-rm67191.dts" + +&mipi_dsi { + panel@0 { + video-mode = <3>; /* command mode */ + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67191.dts 2024-06-19 12:33:58.284192293 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019,2021 NXP + */ + +#include "imx8mm-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + * 3: command mode + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts: synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67199-cmd-ram.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67199-cmd-ram.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67199-cmd-ram.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67199-cmd-ram.dts 2024-06-19 12:33:58.284192293 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mm-evk-rm67199.dts" + +&mipi_dsi { + panel@0 { + video-mode = <3>; /* command mode */ + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rm67199.dts 2024-06-19 12:33:58.284192293 +0200 @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mm-evk-rm67191.dts" + +/delete-node/ &synaptics_dsx_ts; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&i2c2 { + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + edge-failling-trigger; + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-root.dts 2024-06-19 12:33:58.284192293 +0200 @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-evk.dts" + +/ { + interrupt-parent = <&gic>; +}; + +&cpu_pd_wait { + /delete-property/ compatible; + /*arm,psci-suspend-param = <0x0>;*/ +}; + +&clk { + init-on-array = ; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&{/reserved-memory} { + + ivshmem_reserved: ivshmem@bbb00000 { + no-map; + reg = <0 0xbbb00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@bba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00100000>; + }; + + pci_reserved: pci@bb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@bb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@b7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x24000000>; + }; +}; + +&{/reserved-memory/linux,cma} { + alloc-ranges = <0 0x40000000 0 0x60000000>; +}; + +&uart2 { + /* uart2 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + /* sdhc3 is used by 2nd linux, configure the pin */ + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg.dts 2024-06-19 12:33:58.284192293 +0200 @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@b80ff000 { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + bt_sco_codec: bt_sco_codec { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: audio-codec { + status = "disabled"; + }; + + rpmsg_audio: rpmsg_audio { + compatible = "fsl,imx8mm-rpmsg-audio"; + model = "ak4497-audio"; + fsl,platform = "rpmsg-audio-channel"; + fsl,enable-lpa; + fsl,rpmsg-out; + assigned-clocks = <&clk IMX8MM_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, + <&clk IMX8MM_CLK_SAI1_ROOT>, + <&clk IMX8MM_CLK_SDMA3_ROOT>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; + status = "okay"; + }; + + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; + syscon = <&src>; + fsl,startup-delay-ms = <500>; + }; +}; + +&clk { + init-on-array = ; +}; + +/* + * ATTENTION: M4 may use IPs like below + * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1 + */ + +&i2c3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; + +&sai6 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg-wm8524.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg-wm8524.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg-wm8524.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg-wm8524.dts 2024-06-19 12:33:58.284192293 +0200 @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@b80ff000 { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + + }; + + bt_sco_codec: bt_sco_codec { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sound-wm8524 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + wm8524: audio-codec { + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + }; + + rpmsg_audio: rpmsg_audio { + compatible = "fsl,imx8mm-rpmsg-audio"; + model = "wm8524-audio"; + fsl,platform = "rpmsg-audio-channel"; + fsl,enable-lpa; + fsl,rpmsg-out; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, + <&clk IMX8MM_CLK_SAI3_ROOT>, + <&clk IMX8MM_CLK_SDMA3_ROOT>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; + audio-codec = <&wm8524>; + status = "okay"; + }; + + rpmsg_micfil: rpmsg_micfil { + compatible = "fsl,imx8mm-rpmsg-audio"; + model = "micfil-audio"; + fsl,platform = "rpmsg-micfil-channel"; + fsl,enable-lpa; + fsl,rpmsg-in; + assigned-clocks = <&clk IMX8MM_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + clocks = <&clk IMX8MM_CLK_PDM_IPG>, + <&clk IMX8MM_CLK_PDM_ROOT>, + <&clk IMX8MM_CLK_SDMA3_ROOT>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; + status = "okay"; + }; + + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; + syscon = <&src>; + }; +}; + +&clk { + init-on-array = ; +}; + +/* + * ATTENTION: M4 may use IPs like below + * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1 + */ + +&i2c3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +&micfil { + status = "disabled"; +}; + +&sai6 { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&uart3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg-wm8524-lpv.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg-wm8524-lpv.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg-wm8524-lpv.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-rpmsg-wm8524-lpv.dts 2024-06-19 12:33:58.284192293 +0200 @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx8mm-evk-rpmsg-wm8524.dts" + +&rpmsg_audio { + /delete-property/ fsl,enable-lpa; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mm-evk-usd-wifi.dts 2024-06-19 12:33:58.284192293 +0200 @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dts" + +&pinctrl_usdhc2 { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x1d0 + >; +}; + +&pinctrl_usdhc2_100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x1d0 + >; +}; + +&pinctrl_usdhc2_200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x1d0 + >; +}; + +&usdhc2 { + pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + /delete-property/ cd-gpios; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; +}; + +&usdhc1 { + status = "disabled"; + /delete-node/ wifi_wake_host; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ab2.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8mn-evk.dts" +#include "imx8mn-ab2.dtsi" + +/ { + model = "NXP i.MX8MNano Audio board 2.0"; + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; +}; + +&i2c2 { + pca6408_2: gpio@20 { + vcc-supply = <&buck4>; + }; +}; + +&i2c3 { + pca6416: gpio@20 { + vcc-supply = <&buck5>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ab2.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ab2.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ab2.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ab2.dtsi 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/ { + /delete-node/ audio-codec; + /delete-node/ ir-receiver; + /delete-node/ regulator-audio-board; + /delete-node/ sound-wm8524; + /delete-node/ sound-micfil; + /delete-node/ sound-ak5558; + + ak4458_reset: gpio-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + #reset-cells = <0>; + initially-in-reset; + }; + + gpio-leds { + panel { + label = "green:panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + reg_adc_dvdd_3v3: reg-adc-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "ADC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_adc_avdd_5v0: reg-adc-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ADC_DVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_dvdd_3v3: reg-dac-dvdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "DAC_DVDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_dac_avdd_5v0: reg-dac-avdd-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ADC_DVDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_ab2_ana_pwr>; + }; + + reg_cph_3v3: reg-cph-3v3 { + compatible = "regulator-fixed"; + regulator-name = "CPH_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ab2_vdd_pwr_5v0>; + }; + + reg_cph_1v8: reg-cph-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CPH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_ab2_vdd_pwr_5v0>; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-card"; + model = "ak4458-audio"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai3>; + }; + codec { + sound-dai = <&ak4458_1>; + }; + }; + }; +}; + +&cameradev { + status = "disabled"; +}; + +&fec1 { + mdio { + ethphy0: ethernet-phy@0 { + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + reset-deassert-us = <150000>; + reset-assert-us = <15000>; + max-speed = <100>; + }; + }; +}; + +&i2c2 { + /delete-node/ adv7535@3d; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ptn5110: tcpc@50 { + status = "disabled"; + /delete-node/ port; + }; + + ptn5150: tcpc@1d { + compatible = "nxp,ptn5150"; + reg = <0x1d>; + status = "okay"; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&i2c3 { + /delete-node/ ak5558@13; + /delete-node/ ak4497@11; + /delete-node/ ov5640_mipi@3c; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ak4458_1: ak4458@10 { + #sound-dai-cells = <0>; + sound-name-prefix = "0"; + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + resets = <&ak4458_reset>; + AVDD-supply = <®_dac_avdd_5v0>; + DVDD-supply = <®_dac_dvdd_3v3>; + status = "okay"; + }; + + ak4458_2: ak4458@12 { + #sound-dai-cells = <0>; + sound-name-prefix = "1"; + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + resets = <&ak4458_reset>; + AVDD-supply = <®_dac_avdd_5v0>; + DVDD-supply = <®_dac_dvdd_3v3>; + status = "disabled"; + }; + + ak4458_3: ak4458@11 { + #sound-dai-cells = <0>; + sound-name-prefix = "2"; + compatible = "asahi-kasei,ak4458"; + reg = <0x11>; + resets = <&ak4458_reset>; + AVDD-supply = <®_dac_avdd_5v0>; + DVDD-supply = <®_dac_dvdd_3v3>; + status = "disabled"; + }; + + ak5552: ak5552@13 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>; + AVDD-supply = <®_adc_avdd_5v0>; + DVDD-supply = <®_adc_dvdd_3v3>; + status = "disabled"; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "disabled"; +}; + +&iomuxc { + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0xd6 + >; + }; +}; + +&isi_0 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&mipi_csi_1 { + status = "disabled"; + /delete-node/ port@0; +}; + +&mipi_dsi { + status = "disabled"; + /delete-node/ port@1; +}; + + +&usbotg1 { + dr_mode = "peripheral"; + /delete-property/ usb-role-switch; + /delete-node/ port; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,dataline = <2 0x3 0x3>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-ab2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-ab2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-ab2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-ab2.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* + * Copyright 2021 NXP + */ + +#include "imx8mn-ab2.dts" + +/ { + model = "NXP i.MX8MNano DDR3L Audio board 2.0"; +}; + +&A53_0 { + cpu-supply = <&buck1>; +}; + +&aips4 { + /delete-node/ display-subsystem; +}; + +/delete-node/ &gpu; +/delete-node/ &lcdif; +/delete-node/ &mipi_dsi; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-ak5558.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-ak5558.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-ak5558.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-ak5558.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,39 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mn-ddr3l-evk.dts" + +/ { + sound-wm8524 { + audio-asrc = <0>; + }; + sound-ak5558 { + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; + +&ak5558 { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts 2024-06-19 12:33:58.288192361 +0200 @@ -112,3 +112,12 @@ }; }; }; + +&aips4 { + /delete-node/ display-subsystem; +}; + +/delete-node/ &adv_bridge; +/delete-node/ &gpu; +/delete-node/ &lcdif; +/delete-node/ &mipi_dsi; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk-rpmsg.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ddr3l-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x40000000 0 0x40000000>; + linux,cma-default; + }; + + m_core_reserved: m_core@77000000 { + no-map; + reg = <0 0x77000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@78000000 { + reg = <0 0x78000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@78008000 { + reg = <0 0x78008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@780ff000 { + reg = <0 0x780ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@78400000 { + compatible = "shared-dma-pool"; + reg = <0 0x78400000 0 0x100000>; + no-map; + }; + }; + + bt_sco_codec: bt_sco_codec { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: audio-codec { + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + }; + + rpmsg_audio: rpmsg_audio { + compatible = "fsl,imx8mn-rpmsg-audio"; + model = "wm8524-audio"; + fsl,enable-lpa; + fsl,rpmsg-out; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, + <&clk IMX8MN_CLK_SAI3_ROOT>, + <&clk IMX8MN_CLK_SDMA3_ROOT>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; + audio-codec = <&wm8524>; + status = "okay"; + }; + + imx8mn-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MN_CLK_DUMMY>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, <&rsc_table>; + status = "okay"; + fsl,startup-delay-ms = <500>; + }; +}; + +&clk { + init-on-array = < + IMX8MN_CLK_UART4_ROOT + >; +}; + +/* + * ATTENTION: M core may use IPs like below + * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, PWM3, SDMA1/3 and PDM + */ + +&ecspi2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&pwm3 { + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-ab2.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8mn-ddr4-evk.dts" +#include "imx8mn-ab2.dtsi" + +/ { + model = "NXP i.MX8MNano DDR4 Audio board 2.0"; + compatible = "fsl,imx8mn-ddr4-ab2", "fsl,imx8mn"; +}; + +&i2c2 { + pca6408_2: gpio@20 { + vcc-supply = <&buck4_reg>; + }; +}; + +&i2c3 { + pca6416: gpio@20 { + vcc-supply = <&buck5_reg>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-ak5558.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +/ { + sound-wm8524 { + audio-asrc = <0>; + }; + sound-ak5558 { + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; + +&ak5558 { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts 2024-06-19 12:33:58.288192361 +0200 @@ -29,26 +29,6 @@ cpu-supply = <&buck2_reg>; }; -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-600M { - opp-hz = /bits/ 64 <600000000>; - }; - }; -}; - &i2c1 { pmic@4b { compatible = "rohm,bd71847"; @@ -71,6 +51,8 @@ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <850000>; + rohm,dvs-suspend-voltage = <750000>; }; buck2_reg: BUCK2 { @@ -80,13 +62,9 @@ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <1250>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + rohm,dvs-suspend-voltage = <0>; }; buck4_reg: BUCK4 { @@ -140,14 +118,6 @@ regulator-always-on; }; - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - ldo6_reg: LDO6 { regulator-name = "ldo6"; regulator-min-microvolt = <900000>; @@ -158,3 +128,20 @@ }; }; }; + +&gpu { + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <400000000>, <400000000>; + status= "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-inmate.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include + +/ { + model = "Freescale i.MX8MN EVK"; + compatible = "fsl,imx8mn-evk", "fsl,imx8mm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_200m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + pci@bb800000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbb800000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + + aips3: bus@30800000 { + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x08000000 0x08000000 0x10000000>; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_200m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-lk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-lk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-lk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-lk.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019-2021 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +&{/} { + ivshm_rpmsg { + compatible = "fsl,ivshm-rpmsg"; + + rpmsg_console { + compatible = "fsl,rpmsg-console"; + id = <2>; + size = <16384>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x40000000>; + linux,cma-default; + }; + + ivshmem_reserved: ivshmem@bba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00400000>; + }; + + pci_reserved: pci@bb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@bb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@b7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x20000000>; + }; + }; +}; + +&clk { + init-on-array = ; +}; + +&gpio5 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&sai5 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +&usdhc3 { + status = "disabled"; +}; + +&spdif1 { + status = "disabled"; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MN_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191-cmd-ram.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191-cmd-ram.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191-cmd-ram.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191-cmd-ram.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mn-ddr4-evk-rm67191.dts" + +&mipi_dsi { + panel@0 { + video-mode = <3>; /* command mode */ + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67191.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018-2019,2021 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&i2c2 { + synaptics_dsx_ts: synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + * 3: command mode + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67199-cmd-ram.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67199-cmd-ram.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67199-cmd-ram.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67199-cmd-ram.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mn-ddr4-evk-rm67199.dts" + +&mipi_dsi { + panel@0 { + video-mode = <3>; /* command mode */ + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rm67199.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mn-ddr4-evk-rm67191.dts" + +/delete-node/ &synaptics_dsx_ts; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&i2c2 { + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + edge-failling-trigger; + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-root.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +/* +TODO: need uncomment when linux ready +&cpu_pd_wait { + /delete-property/ compatible; +}; +*/ + +&{/} { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x40000000>; + linux,cma-default; + }; + + ivshmem_reserved: ivshmem@bbb00000 { + no-map; + reg = <0 0xbbb00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@bba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00100000>; + }; + + pci_reserved: pci@bb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@bb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@b7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x24000000>; + }; + }; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; +}; + +&clk { + init-on-array = ; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MN_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-rpmsg.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m_core_reserved: m_core@80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@b80ff000 { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + bt_sco_codec: bt_sco_codec { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: audio-codec { + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + }; + + rpmsg_audio: rpmsg_audio { + compatible = "fsl,imx8mn-rpmsg-audio"; + model = "wm8524-audio"; + fsl,enable-lpa; + fsl,rpmsg-out; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, + <&clk IMX8MN_CLK_SAI3_ROOT>, + <&clk IMX8MN_CLK_SDMA3_ROOT>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; + audio-codec = <&wm8524>; + status = "okay"; + }; + + imx8mn-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MN_CLK_DUMMY>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; + status = "okay"; + }; +}; + +&clk { + init-on-array = < + IMX8MN_CLK_UART4_ROOT + >; +}; + +/* + * ATTENTION: M core may use IPs like below + * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, PWM3, SDMA1/3 and PDM + */ + +&ecspi2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&pwm3 { + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk-usd-wifi.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ddr4-evk.dts" + +&usdhc2 { + /delete-property/ cd-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn.dtsi 2024-06-19 12:33:58.292192429 +0200 @@ -39,6 +39,8 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; + isi0 = &isi_0; + csi0 = &mipi_csi_1; }; cpus { @@ -174,6 +176,21 @@ }; }; + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x40000000>; + linux,cma-default; + }; + }; + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -216,6 +233,22 @@ clock-output-names = "clk_ext4"; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MN_DRAM_PLL_OUT>, <&clk IMX8MN_CLK_DRAM_ALT>, + <&clk IMX8MN_CLK_DRAM_APB>, <&clk IMX8MN_CLK_DRAM_APB>, + <&clk IMX8MN_CLK_DRAM_CORE>, <&clk IMX8MN_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MN_SYS_PLL1_40M>, <&clk IMX8MN_SYS_PLL1_100M>, + <&clk IMX8MN_SYS_PLL2_333M>, <&clk IMX8MN_CLK_NOC>, + <&clk IMX8MN_CLK_AHB>, <&clk IMX8MN_CLK_MAIN_AXI>, + <&clk IMX8MN_CLK_24M>, <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + isi_0: isi@32e20000 { + compatible = "fsl,imx8mn-isi"; + reg = <0x0 0x32e20000 0x0 0x2000>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; + interrupts = ; + interface = <2 0 2>; + clocks = <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi_1: csi@32e30000 { + compatible = "fsl,imx8mn-mipi-csi"; + reg = <0x0 0x32e30000 0x0 0x10000>; + interrupts = ; + clock-frequency = <333000000>; + clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "mipi_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>; + bus-width = <4>; + csi-gpr = <&mipi2csi_gasket>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; + }; + }; + soc: soc@0 { - compatible = "fsl,imx8mn-soc", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; @@ -278,6 +365,11 @@ nvmem-cells = <&imx8mn_uid>; nvmem-cell-names = "soc_unique_id"; + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -530,7 +622,7 @@ }; sdma3: dma-controller@302b0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x302b0000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, @@ -541,7 +633,7 @@ }; sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x302c0000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, @@ -562,7 +654,7 @@ }; ocotp: efuse@30350000 { - compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; + compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon", "simple-mfd"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; #address-cells = <1>; @@ -579,6 +671,12 @@ fec_mac_address: mac-address@90 { reg = <0x90 6>; }; + + imx8mn_soc: imx8mn-soc { + compatible = "fsl,imx8mn-soc"; + nvmem-cells = <&imx8mn_uid>; + nvmem-cell-names = "soc_unique_id"; + }; }; anatop: anatop@30360000 { @@ -587,6 +685,22 @@ reg = <0x30360000 0x10000>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -627,6 +741,7 @@ <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MN_SYS_PLL3>, + <&clk IMX8MN_VIDEO_PLL1>, <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, @@ -637,6 +752,7 @@ <400000000>, <400000000>, <600000000>, + <1039500000>, <393216000>, <361267200>; }; @@ -992,7 +1108,7 @@ }; sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x30bd0000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, @@ -1042,6 +1158,63 @@ #size-cells = <1>; ranges; + lcdif: lcd-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mn-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>, + <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>, + <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rate = <594000000>, + <500000000>, + <200000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi_controller@32e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mn-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "cfg", "pll-ref", "apb-root"; + assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, + <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <266000000>, + <12000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; @@ -1070,6 +1243,11 @@ #power-domain-cells = <1>; }; + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp0>; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; @@ -1120,32 +1298,6 @@ status = "disabled"; }; - gpu: gpu@38000000 { - compatible = "vivante,gc"; - reg = <0x38000000 0x8000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_GPU_AHB>, - <&clk IMX8MN_CLK_GPU_BUS_ROOT>, - <&clk IMX8MN_CLK_GPU_CORE_ROOT>, - <&clk IMX8MN_CLK_GPU_SHADER>; - clock-names = "reg", "bus", "core", "shader"; - assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, - <&clk IMX8MN_CLK_GPU_SHADER>, - <&clk IMX8MN_CLK_GPU_AXI>, - <&clk IMX8MN_CLK_GPU_AHB>, - <&clk IMX8MN_GPU_PLL>; - assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, - <&clk IMX8MN_GPU_PLL_OUT>, - <&clk IMX8MN_SYS_PLL1_800M>, - <&clk IMX8MN_SYS_PLL1_800M>; - assigned-clock-rates = <400000000>, - <400000000>, - <800000000>, - <400000000>, - <1200000000>; - power-domains = <&pgc_gpumix>; - }; - gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, @@ -1155,16 +1307,6 @@ interrupts = ; }; - ddrc: memory-controller@3d400000 { - compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; - reg = <0x3d400000 0x400000>; - clock-names = "core", "pll", "alt", "apb"; - clocks = <&clk IMX8MN_CLK_DRAM_CORE>, - <&clk IMX8MN_DRAM_PLL>, - <&clk IMX8MN_CLK_DRAM_ALT>, - <&clk IMX8MN_CLK_DRAM_APB>; - }; - ddr-pmu@3d800000 { compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; @@ -1172,6 +1314,38 @@ }; }; + gpu: gpu@38000000 { + compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x38000000 0x0 0x40000>, + <0x0 0x40000000 0x0 0x80000000>, + <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = ; + interrupt-names = "irq_3d"; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <600000000>, <600000000>; + power-domains = <&pgc_gpumix>; + status = "disabled"; + }; + usbphynop1: usbphynop1 { #phy-cells = <0>; compatible = "usb-nop-xceiv"; @@ -1180,5 +1354,6 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk"; power-domains = <&pgc_otg1>; + wakeup-source; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-revE.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-revE.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-revE.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-revE.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" + +/ { + mic_leds { + compatible = "gpio-leds"; + mic0 { + label = "mic0"; + gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic1 { + label = "mic1"; + gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic2 { + label = "mic2"; + gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic3 { + label = "mic3"; + gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic4 { + label = "mic4"; + gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic5 { + label = "mic5"; + gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic6 { + label = "mic6"; + gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic7 { + label = "mic7"; + gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sw_keys { + compatible = "gpio-keys"; + + sw4: volume_down { + label = "Volume Down"; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; + + sw3: volume_up { + label = "Volume Up"; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + }; + + sw2: volume_mute { + label = "Volume Mute"; + gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; + + sw1: key_act { + label = "Key Act"; + gpios = <&pca9555 12 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + reg_vddext_3v3: regulator-vddext { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&iomuxc { + pinctrl_swpdm_mute_irq: swpdm_mute_grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x19 + >; + }; + + pinctrl_pushbutton_irq: pushbutton_grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; +}; + +&i2c3 { + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pushbutton_irq>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_vddext_3v3>; + status = "okay"; + }; + + pca995btw: pca9955btw@7 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9955btw"; + reg = <0x07>; + led0 { + label = "green0"; + linux,default-trigger = "none"; + reg = <0>; + }; + + led1 { + label = "blue0"; + linux,default-trigger = "none"; + reg = <1>; + }; + + led2 { + label = "red0"; + linux,default-trigger = "none"; + reg = <2>; + }; + + led3 { + label = "green1"; + linux,default-trigger = "none"; + reg = <3>; + }; + + led4 { + label = "blue1"; + linux,default-trigger = "none"; + reg = <4>; + }; + + led5 { + label = "red1"; + linux,default-trigger = "none"; + reg = <5>; + }; + + led6 { + label = "green2"; + linux,default-trigger = "none"; + reg = <6>; + }; + + led7 { + label = "blue2"; + linux,default-trigger = "none"; + reg = <7>; + }; + + led8 { + label = "red2"; + linux,default-trigger = "none"; + reg = <8>; + }; + + led9 { + label = "green3"; + linux,default-trigger = "none"; + reg = <9>; + }; + + led10 { + label = "blue3"; + linux,default-trigger = "none"; + reg = <10>; + }; + + led11 { + label = "red3"; + linux,default-trigger = "none"; + reg = <11>; + }; + }; +}; + +&uart3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-swpdm.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-swpdm.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-swpdm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-8mic-swpdm.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk-8mic-revE.dts" + +/ { + sound-micfil { + status = "disabled"; + }; + + dmic: dmic { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + wakeup-delay-ms = <250>; + }; + + sound-swpdm { + compatible = "fsl,imx-audio-card"; + model = "imx-swpdm-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swpdm_mute_irq>; + pri-dai-link { + link-name = "PDM PCM"; + format = "pdm"; + cpu { + sound-dai = <&sai5>; + }; + codec { + sound-dai = <&dmic>; + }; + }; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + /delete-property/ fsl,sai-multi-lane; + dmas = <&sdma2 8 24 0>, <&sdma2 9 24 0>; + assigned-clock-rates = <24576000>; + fsl,dataline = <2 0xf 0xf>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-ak5558.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,41 @@ +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mn-evk.dts" + +/ { + sound-wm8524 { + audio-asrc = <0>; + }; + + sound-ak5558 { + status = "okay"; + }; + + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; + +&ak5558 { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk.dts 2024-06-19 12:33:58.288192361 +0200 @@ -47,6 +47,8 @@ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <750000>; }; buck2: BUCK2 { @@ -56,8 +58,6 @@ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; }; buck4: BUCK4{ @@ -126,3 +126,7 @@ }; }; }; + +&gpu { + status= "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi 2024-06-19 12:33:58.288192361 +0200 @@ -28,6 +28,25 @@ reg = <0x0 0x40000000 0 0x80000000>; }; + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + linux,autosuspend-period = <125>; + }; + + reg_usdhc1_vmmc: regulator-usdhc1 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc1_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -36,6 +55,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; enable-active-high; }; @@ -47,6 +67,17 @@ linux,autosuspend-period = <125>; }; + reg_audio_board: regulator-audio-board { + compatible = "regulator-fixed"; + regulator-name = "EXT_PWREN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <300000>; + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + audio_codec_bt_sco: audio-codec-bt-sco { compatible = "linux,bt-sco"; #sound-dai-cells = <1>; @@ -92,6 +123,18 @@ "Line Out Jack", "LINEVOUTR"; }; + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + sound-spdif { compatible = "fsl,imx-audio-spdif"; model = "imx-spdif"; @@ -99,9 +142,50 @@ spdif-out; spdif-in; }; + + sound-ak5558 { + compatible = "fsl,imx-audio-card"; + model = "ak5558-audio"; + status = "disabled"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai5>; + }; + codec { + sound-dai = <&ak5558>; + }; + }; + fe-dai-link { + link-name = "HiFi-ASRC-FE"; + format = "i2s"; + cpu { + sound-dai = <&easrc>; + }; + }; + be-dai-link { + link-name = "HiFi-ASRC-BE"; + format = "dsp_b"; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + cpu { + sound-dai = <&sai5>; + }; + codec { + sound-dai = <&ak5558>; + }; + }; + }; +}; + +&cameradev { + status = "okay"; }; &easrc { + #sound-dai-cells = <0>; fsl,asrc-rate = <48000>; status = "okay"; }; @@ -123,6 +207,9 @@ reg = <0>; reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,aldps-enable; + realtek,clkout-disable; qca,disable-smarteee; vddio-supply = <&vddio>; @@ -145,7 +232,7 @@ #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <166000000>; - spi-tx-bus-width = <4>; + spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; }; }; @@ -159,10 +246,27 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; status = "okay"; + adv_bridge: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + ptn5110: tcpc@50 { compatible = "nxp,ptn5110"; pinctrl-names = "default"; @@ -194,9 +298,12 @@ }; &i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; status = "okay"; pca6416: gpio@20 { @@ -205,6 +312,119 @@ gpio-controller; #gpio-cells = <2>; }; + + ak4458_1: ak4458@10 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak4458_2: ak4458@12 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak5558: ak5558@13 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ak4497: ak4497@11 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + reset-gpios = <&pca6416 5 GPIO_ACTIVE_LOW>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + status = "disabled"; + }; + + ov5640_mipi_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MN_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MN_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + mipi1_sensor_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; }; &sai2 { @@ -214,6 +434,7 @@ assigned-clocks = <&clk IMX8MN_CLK_SAI2>; assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; status = "okay"; }; @@ -227,6 +448,25 @@ status = "okay"; }; +&sai5 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MN_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI5_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + fsl,sai-multi-lane; + fsl,sai-mclk-direction-output; + dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; + status = "disabled"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -237,9 +477,30 @@ assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -255,6 +516,29 @@ status = "okay"; }; +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + vmmc-supply = <®_usdhc1_vmmc>; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -306,6 +590,25 @@ }; &iomuxc { + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -343,6 +646,19 @@ >; }; + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + pinctrl_gpio_wlf: gpiowlfgrp { fsl,pins = < MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 @@ -376,12 +692,49 @@ >; }; + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -419,6 +772,15 @@ >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 @@ -435,6 +797,45 @@ >; }; + pinctrl_reg_usdhc1_vmmc: regusdhc1vmmcgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x141 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 @@ -530,4 +931,11 @@ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x159 + >; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dac2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dac2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dac2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dac2.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP. + */ + +#include "imx8mn-evk-hifiberry-dacplus.dts" + +/ { + sound-pcm512x { + audio-widgets = + "Headphone", "Headphone Jack", + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + aux-devs= <&headphone_amp>; + }; +}; + +&i2c3 { + headphone_amp: amp@60 { + compatible = "ti,tpa6130a2"; + Vdd-supply = <®_3v3_vext>; + reg = <0x60>; + status = "okay"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dacplus.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dacplus.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dacplus.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-hifiberry-dacplus.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mn-evk.dts" + +/ { + ext_osc_22m: ext-osc-22m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + clock-output-names = "sclk0"; + }; + + ext_osc_24m: ext-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-output-names = "sclk1"; + }; + + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + dac,24db_digital_gain; + dac,led_status; + dac,sclk; + + pri-dai-link { + link-name = "pcm512x-hifi"; + format = "i2s"; + bitclock-master = <&sndcodec>; + frame-master = <&sndcodec>; + cpu { + sound-dai = <&sai5>; + }; + sndcodec: codec { + sound-dai = <&pcm512x>; + }; + }; + }; +}; + +&i2c3 { + pcm512x: pcm512x@4d { + compatible = "ti,pcm5122"; + reg = <0x4d>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + clocks = <&ext_osc_22m>, <&ext_osc_24m>; + clock-names = "sclk0", "sclk1"; + #sound-dai-cells = <0>; + }; +}; + +&iomuxc { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + /delete-property/ fsl,sai-asynchronous; + /delete-property/ fsl,sai-multi-lane; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-inmate.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include + +/ { + model = "NXP i.MX8MNano EVK board"; + compatible = "fsl,imx8mn-evk", "fsl,imx8mm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-affinity = <&A53_2>, <&A53_3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_200m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + pci@bb800000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbb800000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + + aips3: bus@30800000 { + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x08000000 0x08000000 0x10000000>; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_200m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacplus.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacplus.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacplus.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacplus.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mn-evk.dts" + +/ { + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + dac,24db_digital_gain; + + pri-dai-link { + link-name = "pcm512x-hifi"; + format = "i2s"; + cpu { + sound-dai = <&sai5>; + }; + + codec { + sound-dai = <&pcm512x>; + }; + }; + }; +}; + +&i2c3 { + pcm512x: pcm512x@4c { + compatible = "ti,pcm5122"; + reg = <0x4c>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + #sound-dai-cells = <0>; + }; +}; + +&iomuxc { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + #sound-dai-cells = <0>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacpro.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacpro.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacpro.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-iqaudio-dacpro.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mn-evk-iqaudio-dacplus.dts" + +&i2c3 { + pcm512x: pcm512x@4c { + compatible = "ti,pcm5142"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-lk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-lk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-lk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-lk.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include "imx8mn-evk.dts" + +&{/} { + ivshm_rpmsg { + compatible = "fsl,ivshm-rpmsg"; + + rpmsg_console { + compatible = "fsl,rpmsg-console"; + id = <2>; + size = <16384>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x40000000>; + linux,cma-default; + }; + + ivshmem_reserved: ivshmem@bba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00400000>; + }; + + pci_reserved: pci@bb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@bb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@b7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x20000000>; + }; + }; +}; + +&clk { + init-on-array = ; +}; + +&gpio5 { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&sai5 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +&usdhc3 { + status = "disabled"; +}; + +&spdif1 { + status = "disabled"; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MN_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191-cmd-ram.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191-cmd-ram.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191-cmd-ram.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191-cmd-ram.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mn-evk-rm67191.dts" + +&mipi_dsi { + panel@0 { + video-mode = <3>; /* command mode */ + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67191.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019,2021 NXP + */ + +#include "imx8mn-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + * 3: command mode + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts: synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67199-cmd-ram.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67199-cmd-ram.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67199-cmd-ram.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67199-cmd-ram.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mn-evk-rm67199.dts" + +&mipi_dsi { + panel@0 { + video-mode = <3>; /* command mode */ + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-rm67199.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mn-evk-rm67191.dts" + +/delete-node/ &synaptics_dsx_ts; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&i2c2 { + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + edge-failling-trigger; + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-root.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" + +&{/} { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x93c00000>; + linux,cma-default; + }; + + ivshmem_reserved: ivshmem@bbb00000 { + no-map; + reg = <0 0xbbb00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@bba00000 { + no-map; + reg = <0 0xbba00000 0x0 0x00100000>; + }; + + pci_reserved: pci@bb800000 { + no-map; + reg = <0 0xbb800000 0x0 0x00200000>; + }; + + loader_reserved: loader@bb700000 { + no-map; + reg = <0 0xbb700000 0x0 0x00100000>; + }; + + jh_reserved: jh@b7c00000 { + no-map; + reg = <0 0xb7c00000 0x0 0x00400000>; + }; + + /* 512MB */ + inmate_reserved: inmate@93c00000 { + no-map; + reg = <0 0x93c00000 0x0 0x24000000>; + }; + }; +}; + +&cpu_pd_wait { + /delete-property/ compatible; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; +}; + +&clk { + init-on-array = ; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MN_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-rpmsg.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m_core_reserved: m_core@80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@b80ff000 { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + bt_sco_codec: bt_sco_codec { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: audio-codec { + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + }; + + rpmsg_audio: rpmsg_audio { + compatible = "fsl,imx8mn-rpmsg-audio"; + model = "wm8524-audio"; + fsl,enable-lpa; + fsl,rpmsg-out; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, + <&clk IMX8MN_CLK_SAI3_ROOT>, + <&clk IMX8MN_CLK_SDMA3_ROOT>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; + audio-codec = <&wm8524>; + status = "okay"; + }; + + imx8mn-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MN_CLK_DUMMY>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; + status = "okay"; + fsl,startup-delay-ms = <500>; + }; +}; + +&clk { + init-on-array = < + IMX8MN_CLK_UART4_ROOT + >; +}; + +/* + * ATTENTION: M core may use IPs like below + * ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, PWM3, SDMA1/3 and PDM + */ + +&ecspi2 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +&i2c3 { + status = "disabled"; +}; + +&pwm3 { + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-usd-wifi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-usd-wifi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-evk-usd-wifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-evk-usd-wifi.dts 2024-06-19 12:33:58.288192361 +0200 @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include "imx8mn-evk.dts" + +/* + * IW612 wifi chip needs more delay than other wifi chips to complete the host + * interface initialization after power up, otherwise the internal state of + * IW612 may be unstable, resulting in the failure of the SDIO3.0 switch + * voltage. + */ +®_usdhc2_vmmc { + startup-delay-us = <20000>; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + /delete-property/ cd-gpios; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; +}; + +&usdhc1 { + status = "disabled"; + /delete-node/ wifi_wake_host; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h 2024-06-19 12:33:58.292192429 +0200 @@ -474,7 +474,7 @@ #define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 #define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 #define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x1D4 0x43C 0x538 0x6 0x10 +#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x1D4 0x43C 0x538 0x6 0xA #define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 #define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x5EC 0x1 0x0 #define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x1 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,911 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MP SOM on AB2"; + compatible = "fsl,imx8mp-ab2", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "yellow:status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + }; + + ak4458_reset: gpio-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + #reset-cells = <0>; + initially-in-reset; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ab2_ana_pwr"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ab2_vdd_pwr_5v0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + pri-dai-link { + link-name = "XCVR PCM"; + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-card"; + model = "ak4458-audio"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai1>; + }; + codec { + sound-dai = <&ak4458_1>, <&ak4458_2>; + }; + }; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-card"; + model = "ak5552-audio"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai3>; + }; + codec { + sound-dai = <&ak5552>; + }; + }; + }; +}; + +&{/busfreq} { + status = "disabled"; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev1: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ak4458_1: ak4458@10 { + #sound-dai-cells = <0>; + sound-name-prefix = "0"; + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + resets = <&ak4458_reset>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; + + ak4458_2: ak4458@11 { + #sound-dai-cells = <0>; + sound-name-prefix = "1"; + compatible = "asahi-kasei,ak4458"; + reg = <0x11>; + resets = <&ak4458_reset>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; + + ak4458_3: ak4458@12 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + resets = <&ak4458_reset>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; + + ak5552: ak5552@13 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + reset-gpios = <&pca6416 2 GPIO_ACTIVE_LOW>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + }; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi_blk_ctrl { + status = "okay"; +}; + +&hdmi_pavi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + +&easrc { + #sound-dai-cells = <0>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,dataline = <2 0xff 0xff>; + fsl,sai-mclk-direction-output; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&xcvr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xcvr>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sdma2 { + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x10 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0xd6 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xd6 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6 + MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0xd6 + MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0xd6 + MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0xd6 + MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0xd6 + MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0xd6 + MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0xd6 + MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + >; + }; + + pinctrl_xcvr: xcvrgrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0xd6 + MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0xd6 + MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_vc8000e { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&gpu_2d { + status = "okay"; +}; + +&ml_vipsi { + status = "okay"; +}; + +&mix_gpu_ml { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + model = "NXP i.MX8MPlus DDR4 EVK board"; + + /delete-node/ gpio-leds; +}; + +&flexspi { + status = "disabled"; +}; + +&clk { + assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, + <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-rates = <400000000>, + <600000000>, + <393216000>, + <361267200>, + <1039500000>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; + nand-on-flash-bbt; + fsl,use-minimum-ecc; +}; + +&gpu_2d { + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>, + <&clk IMX8MP_GPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_GPU_PLL_OUT>, + <&clk IMX8MP_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <600000000>, + <300000000>, <600000000>; +}; + +&gpu_3d { + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>, + <&clk IMX8MP_GPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_GPU_PLL_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <800000000>, + <600000000>, <300000000>, + <600000000>; +}; + +&ml_vipsi { + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <800000000>, <300000000>; +}; + +&pcie{ + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <400000000>, <10000000>; +}; + +&pcie_ep{ + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <400000000>, <10000000>; +}; + +&usb_dwc3_0 { + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&usb_dwc3_1 { + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&vpu_g1 { + + assigned-clocks = <&clk IMX8MP_VPU_PLL>, <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <0>, <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, <600000000>, <600000000>; +}; + +&vpu_g2 { + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <500000000>, <600000000>; +}; + +&vpu_vc8000e { + assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <400000000>, <600000000>; +}; + +&lcdif1 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <400000000>, <200000000>; +}; + +&lcdif2 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <400000000>, <200000000>; +}; + +&lcdif3 { + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <400000000>, <133000000>; + thres-low = <2 3>; /* (FIFO * 2 / 3) */ + thres-high = <3 3>; /* (FIFO * 3 / 3) */ + status = "okay"; +}; + +&isi_0 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <400000000>, <200000000>; +}; + +&isi_1 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <400000000>, <200000000>; +}; + +&mipi_csi_0 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&isp_0 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&isp_1 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__NAND_ALE 0x00000096 + MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x00000096 + MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x00000096 + MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 0x00000096 + MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 0x00000096 + MX8MP_IOMUXC_NAND_CLE__NAND_CLE 0x00000096 + MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 0x00000096 + MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 0x00000096 + MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 0x00000096 + MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 0x00000096 + MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 0x00000096 + MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 0x00000096 + MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 0x00000096 + MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 0x00000096 + MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 0x00000096 + MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B 0x00000056 + MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 0x00000096 + MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x00000096 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp.dtsi 2024-06-19 12:33:58.296192498 +0200 @@ -6,9 +6,9 @@ #include #include #include +#include #include #include -#include #include #include @@ -41,12 +41,32 @@ serial2 = &uart3; serial3 = &uart4; spi0 = &flexspi; + isi0 = &isi_0; + isi1 = &isi_1; + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + isp0 = &isp_0; + isp1 = &isp_1; }; cpus { #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; @@ -65,6 +85,7 @@ nvmem-cell-names = "speed_grade"; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_1: cpu@1 { @@ -83,6 +104,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_2: cpu@2 { @@ -101,6 +123,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_3: cpu@3 { @@ -119,6 +142,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_L2: l2-cache0 { @@ -130,6 +154,13 @@ }; }; + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif1_disp>, + <&lcdif2_disp>, + <&lcdif3_disp>; + }; + a53_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -159,6 +190,66 @@ }; }; + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ocram: ocram@900000 { + no-map; + reg = <0 0x900000 0 0x70000>; + }; + +/* + * Memory reserved for optee usage. Please do not use. + * This will be automaticky added to dtb if OP-TEE is installed. + * optee@56000000 { + * reg = <0 0x56000000 0 0x2000000>; + * no-map; + * }; + */ + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x40000000 0 0xC0000000>; + linux,cma-default; + }; + + gpu_reserved: gpu_reserved@100000000 { + no-map; + reg = <0x1 0x00000000 0 0x10000000>; + }; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x1000000>; + no-map; + }; + dsp_reserved_heap: dsp_reserved_heap { + reg = <0 0x93400000 0 0xef0000>; + no-map; + }; + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + }; + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -201,14 +292,74 @@ clock-output-names = "clk_ext4"; }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; + sai1_mclk: sai-mclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai1_mclk"; + }; - dsp_reserved: dsp@92400000 { - reg = <0 0x92400000 0 0x2000000>; - no-map; + sai2_mclk: sai-mclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai2_mclk"; + }; + + sai3_mclk: sai-mclk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai3_mclk"; + }; + + sai5_mclk: sai-mclk5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai5_mclk"; + }; + + sai6_mclk: sai-mclk6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai6_mclk"; + }; + + sai7_mclk: sai-mclk7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai7_mclk"; + }; + + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MP_DRAM_PLL_OUT>, <&clk IMX8MP_CLK_DRAM_ALT>, + <&clk IMX8MP_CLK_DRAM_APB>, <&clk IMX8MP_CLK_DRAM_APB>, + <&clk IMX8MP_CLK_DRAM_CORE>, <&clk IMX8MP_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MP_SYS_PLL1_40M>, <&clk IMX8MP_SYS_PLL1_100M>, + <&clk IMX8MP_SYS_PLL2_333M>, <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_AHB>, <&clk IMX8MP_CLK_MAIN_AXI>, + <&clk IMX8MP_CLK_24M>, <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + }; + + power-domains { + compatible = "simple-bus"; + + audiomix_pd: audiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <5>; + domain-name = "audiomix"; + clocks = <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; }; }; @@ -293,16 +444,28 @@ ; clock-frequency = <8000000>; arm,no-tick-in-suspend; + interrupt-parent = <&gic>; }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; soc: soc@0 { - compatible = "fsl,imx8mp-soc", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; nvmem-cells = <&imx8mp_uid>; nvmem-cell-names = "soc_unique_id"; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -417,7 +580,7 @@ }; ocotp: efuse@30350000 { - compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; + compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon", "simple-mfd"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; /* For nvmem subnodes */ @@ -439,6 +602,12 @@ eth_mac2: mac-address@96 { reg = <0x96 6>; }; + + imx8mp_soc: imx8mp-soc { + compatible = "fsl,imx8mp-soc"; + nvmem-cells = <&imx8mp_uid>; + nvmem-cell-names = "soc_unique_id"; + }; }; anatop: anatop@30360000 { @@ -447,6 +616,22 @@ reg = <0x30360000 0x10000>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -494,7 +679,8 @@ <&clk IMX8MP_CLK_AUDIO_AHB>, <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, <&clk IMX8MP_AUDIO_PLL1>, - <&clk IMX8MP_AUDIO_PLL2>; + <&clk IMX8MP_AUDIO_PLL2>, + <&clk IMX8MP_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_ARM_PLL_OUT>, <&clk IMX8MP_SYS_PLL2_1000M>, @@ -509,7 +695,8 @@ <400000000>, <800000000>, <393216000>, - <361267200>; + <361267200>, + <1039500000>; }; src: reset-controller@30390000 { @@ -551,17 +738,11 @@ reg = ; }; - pgc_gpu2d: power-domain@6 { - #power-domain-cells = <0>; - reg = ; - clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; - power-domains = <&pgc_gpumix>; - }; - pgc_gpumix: power-domain@7 { #power-domain-cells = <0>; reg = ; clocks = <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AXI>, <&clk IMX8MP_CLK_GPU_AHB>; assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, <&clk IMX8MP_CLK_GPU_AHB>; @@ -570,6 +751,17 @@ assigned-clock-rates = <800000000>, <400000000>; }; + /* + * gpu driver not handle defer probe, but gpu2d pd will defer probe is + * put above gpumix, so move below gpumix + */ + pgc_gpu2d: power-domain@6 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; + power-domains = <&pgc_gpumix>; + }; + pgc_gpu3d: power-domain@9 { #power-domain-cells = <0>; reg = ; @@ -585,6 +777,23 @@ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; }; + pgc_hdmimix: power-domains@14 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <500000000>, <133000000>; + }; + + pgc_hdmi_phy: power-domains@15 { + #power-domain-cells = <0>; + reg = ; + }; + pgc_mipi_phy2: power-domain@16 { #power-domain-cells = <0>; reg = ; @@ -632,6 +841,14 @@ reg = ; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; }; + + pgc_mlmix: power-domain@24 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + }; }; }; }; @@ -706,12 +923,15 @@ ecspi1: spi@30820000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30820000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, <&clk IMX8MP_CLK_ECSPI1_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; dma-names = "rx", "tx"; status = "disabled"; @@ -720,12 +940,15 @@ ecspi2: spi@30830000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30830000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, <&clk IMX8MP_CLK_ECSPI2_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; dma-names = "rx", "tx"; status = "disabled"; @@ -734,12 +957,15 @@ ecspi3: spi@30840000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30840000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, <&clk IMX8MP_CLK_ECSPI3_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; dma-names = "rx", "tx"; status = "disabled"; @@ -903,11 +1129,13 @@ }; mu2: mailbox@30e60000 { - compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; + compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu"; reg = <0x30e60000 0x10000>; interrupts = ; + fsl,dsp_ap_mu_id = <2>; #mbox-cells = <2>; - status = "disabled"; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_MU2_ROOT>; + status = "okay"; }; i2c5: i2c@30ad0000 { @@ -988,7 +1216,7 @@ }; sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, @@ -1055,23 +1283,8 @@ }; noc: interconnect@32700000 { - compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; + compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc", "syscon"; reg = <0x32700000 0x100000>; - clocks = <&clk IMX8MP_CLK_NOC>; - #interconnect-cells = <1>; - operating-points-v2 = <&noc_opp_table>; - - noc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200M { - opp-hz = /bits/ 64 <200000000>; - }; - - opp-1000M { - opp-hz = /bits/ 64 <1000000000>; - }; - }; }; aips4: bus@32c00000 { @@ -1081,6 +1294,96 @@ #size-cells = <1>; ranges; + mipi_dsi: mipi_dsi@32e60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-mipi-dsim"; + reg = <0x32e60000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "cfg", "pll-ref", "apb-root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <12000000>; + interrupts = ; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + lcdif1: lcd-controller@32e80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif1"; + reg = <0x32e80000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <500000000>, <200000000>; + interrupts = ; + blk-ctl = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; + status = "disabled"; + + lcdif1_disp: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + lcdif2: lcd-controller@32e90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif2"; + reg = <0x32e90000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; + status = "disabled"; + + lcdif2_disp: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + lcdif2_disp_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ldb_ch0>; + }; + + lcdif2_disp_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ldb_ch1>; + }; + }; + }; + media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl", "syscon"; @@ -1099,18 +1402,6 @@ "lcdif1", "isi", "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2"; - interconnects = - <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, - <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, - <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, - <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, - <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, - <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, - <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, - <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; - interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", - "isi1", "isi2", "isp0", "isp1", - "dwe"; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, @@ -1153,13 +1444,632 @@ <&pgc_hsiomix>, <&pgc_pcie_phy>; power-domain-names = "bus", "usb", "usb-phy1", "usb-phy2", "pcie", "pcie-phy"; - interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, - <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, - <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, - <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; - interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>; }; + + hdmi_blk_ctrl: blk-ctrl@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; + reg = <0x32fc0000 0x23c>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>; + clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; + power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmi_phy>, + <&pgc_hdmimix>, <&pgc_hdmimix>; + power-domain-names = "bus", "irqsteer", "lcdif", + "pai", "pvi", "trng", + "hdmi-tx", "hdmi-tx-phy", + "hrv", "hdcp"; + #power-domain-cells = <1>; + }; + + ldb: ldb@32ec005c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ldb"; + clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + gpr = <&media_blk_ctrl>; + power-domains = <&pgc_mediamix>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch0: endpoint { + remote-endpoint = <&lcdif2_disp_ldb_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch1: endpoint { + remote-endpoint = <&lcdif2_disp_ldb_ch1>; + }; + }; + }; + }; + + ldb_phy: phy@32ec0128 { + compatible = "fsl,imx8mp-lvds-phy"; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&media_blk_ctrl>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "apb"; + power-domains = <&pgc_mediamix>; + status = "disabled"; + + ldb_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + mediamix_gpr: media_gpr@32ec0008 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0008 0x4>; + }; + + mediamix_gasket0: gasket@32ec0060 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0060 0x28>; + }; + + mediamix_gasket1: gasket@32ec0090 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32ec0090 0x28>; + }; + + isi_chain_buf: isi_chain@32e02000{ + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x32e02000 0x4>; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + isi_0: isi@32e00000 { + compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; + reg = <0x32e00000 0x2000>; + interrupts = ; + interface = <2 0 2>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "disp_axi", + "disp_apb", + "disp_axi_root", + "disp_apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; + isi_chain = <&isi_chain_buf>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + + m2m_device{ + compatible = "imx-isi-m2m"; + status = "disabled"; + }; + }; + + isi_1: isi@32e02000 { + compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; + reg = <0x32e02000 0x2000>; + interrupts = ; + interface = <3 0 2>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "disp_axi", + "disp_apb", + "disp_axi_root", + "disp_apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + dewarp: dwe@32e30000 { + compatible = "fsl,imx8mp-dwe"; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "core", "axi", "ahb"; + reg = <0x32e30000 0x10000>; + interrupts = ; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; + status = "disabled"; + }; + + isp_0: isp@32e10000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e10000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>; + clock-names = "core", "axi", "ahb", "sensor"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>, + <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + id = <0>; + gpr = <&media_blk_ctrl>; + status = "disabled"; + }; + + isp_1: isp@32e20000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e20000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>; + clock-names = "core", "axi", "ahb", "sensor"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>, + <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + id = <1>; + gpr = <&media_blk_ctrl>; + status = "disabled"; + }; + + mipi_csi_0: csi@32e40000 { + compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; + reg = <0x32e40000 0x10000>; + interrupts = ; + clock-frequency = <500000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "mipi_clk", + "disp_axi", + "disp_apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + bus-width = <4>; + csi-gpr = <&mediamix_gasket0>; + gpr = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; + status = "disabled"; + }; + + mipi_csi_1: csi@32e50000 { + compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; + reg = <0x32e50000 0x10000>; + interrupts = ; + clock-frequency = <266000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "mipi_clk", + "disp_axi", + "disp_apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; + bus-width = <4>; + csi-gpr = <&mediamix_gasket1>; + gpr = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; + status = "disabled"; + }; + }; + }; + + aips5: bus@30c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spba-bus@30c00000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sai1: sai@30c10000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; + reg = <0x30c10000 0x10000>; + interrupts = ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xff 0xff>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai2: sai@30c20000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; + reg = <0x30c20000 0x10000>; + interrupts = ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai3: sai@30c30000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; + reg = <0x30c30000 0x10000>; + interrupts = ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0x3 0x3>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai5: sai@30c50000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; + reg = <0x30c50000 0x10000>; + interrupts = ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai6: sai@30c60000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; + reg = <0x30c60000 0x10000>; + interrupts = ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sai7: sai@30c80000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai"; + reg = <0x30c80000 0x10000>; + interrupts = ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + easrc: easrc@30c90000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x30c90000 0x10000>; + interrupts = ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_ASRC_IPG>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + firmware-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-format = <2>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + micfil: micfil@30ca0000 { + compatible = "fsl,imx8mp-micfil"; + reg = <0x30ca0000 0x10000>; + interrupts = , + , + , + ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>, + <&clk IMX8MP_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + aud2htx: aud2htx@30cb0000 { + compatible = "fsl,imx8mp-aud2htx"; + reg = <0x30cb0000 0x10000>; + interrupts = ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_AUD2HTX_IPG>; + clock-names = "bus"; + dmas = <&sdma2 26 2 0>; + dma-names = "tx"; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + xcvr: xcvr@30cc0000 { + compatible = "fsl,imx8mp-xcvr"; + reg = <0x30cc0000 0x800>, + <0x30cc0800 0x400>, + <0x30cc0c00 0x080>, + <0x30cc0e00 0x080>; + reg-names = "ram", "regs", "rxfifo", + "txfifo"; + interrupts = /* XCVR IRQ 0 */ + , + /* XCVR IRQ 1 */ + , + /* XCVR PHY - SPDIF wakeup IRQ */ + ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_PHY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SPBA2_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; + dma-names = "rx", "tx"; + resets = <&audio_blk_ctrl 0>; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + }; + + sdma3: dma-controller@30e00000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; + reg = <0x30e00000 0x10000>; + interrupts = ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + sdma2: dma-controller@30e10000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma"; + reg = <0x30e10000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + power-domains = <&audiomix_pd>; + status = "disabled"; + }; + + audio_blk_ctrl: audio-blk-ctrl@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctrl-legacy", "syscon"; + reg = <0x30e20000 0x50C>; + power-domains = <&audiomix_pd>; + + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_BYPASS>; + assigned-clock-parents = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL>; + }; + + audiomix_dsp: audiomix_dsp { + compatible = "fsl,audiomix-dsp"; + power-domains = <&audiomix_pd>; + }; + + irqsteer_hdmi: irqsteer@32fc2000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "ipg"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <133000000>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; + status = "disabled"; + }; + + hdmi_pavi: hdmi-pai-pvi@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pavi"; + reg = <0x32fc4000 0x1000>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + status = "disabled"; + }; + + lcdif3: lcd-controller@32fc6000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif1"; + reg = <0x32fc6000 0x10000>; + clocks = <&hdmiphy 0>, + <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "pix", "disp-axi", "disp-apb"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <500000000>, <133000000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + status = "disabled"; + + lcdif3_disp: port@0 { + reg = <0>; + + lcdif3_to_hdmi: endpoint { + remote-endpoint = <&hdmi_from_lcdif3>; + }; + }; + }; + + hdmi: hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi"; + reg = <0x32fd8000 0x7eff>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&hdmiphy 0>; + clock-names = "iahb", "isfr", "pix"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_133M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <133000000>, <500000000>, <24000000>; + status = "disabled"; + + port@0 { + hdmi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_hdmi>; + }; + }; + }; + + hdmiphy: hdmiphy@32fdff00 { + compatible = "fsl,samsung-hdmi-phy"; + reg = <0x32fdff00 0x100>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "ref"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #clock-cells = <1>; + clock-output-names = "hdmi_phy"; + #phy-cells = <0>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + status = "disabled"; + }; + }; + + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8MP_CLK_NAND_ROOT>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; }; pcie: pcie@33800000 { @@ -1193,52 +2103,23 @@ status = "disabled"; }; - gpu3d: gpu@38000000 { - compatible = "vivante,gc"; - reg = <0x38000000 0x8000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, - <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, - <&clk IMX8MP_CLK_GPU_ROOT>, - <&clk IMX8MP_CLK_GPU_AHB>; - clock-names = "core", "shader", "bus", "reg"; - assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, - <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>, <800000000>; - power-domains = <&pgc_gpu3d>; - }; - - gpu2d: gpu@38008000 { - compatible = "vivante,gc"; - reg = <0x38008000 0x8000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, - <&clk IMX8MP_CLK_GPU_ROOT>, - <&clk IMX8MP_CLK_GPU_AHB>; - clock-names = "core", "bus", "reg"; - assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>; - power-domains = <&pgc_gpu2d>; - }; - - vpumix_blk_ctrl: blk-ctrl@38330000 { - compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; - reg = <0x38330000 0x100>; - #power-domain-cells = <1>; - power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, - <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; - power-domain-names = "bus", "g1", "g2", "vc8000e"; - clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, - <&clk IMX8MP_CLK_VPU_G2_ROOT>, - <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; - clock-names = "g1", "g2", "vc8000e"; - interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, - <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, - <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; - interconnect-names = "g1", "g2", "vc8000e"; + pcie_ep: pcie_ep@33800000 { + compatible = "fsl,imx8mp-pcie-ep"; + reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <3>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; }; gic: interrupt-controller@38800000 { @@ -1251,6 +2132,16 @@ interrupt-parent = <&gic>; }; + vpumix_blk_ctl: blk-ctl@38330000 { + compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; + #power-domain-cells = <1>; + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; + power-domain-names = "bus", "g1", "g2", "h1"; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + clock-names = "g1", "g2", "h1"; + }; + edacmc: memory-controller@3d400000 { compatible = "snps,ddrc-3.80a"; reg = <0x3d400000 0x400000>; @@ -1301,6 +2192,7 @@ phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; }; }; @@ -1343,18 +2235,359 @@ phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; }; }; + }; - dsp: dsp@3b6e8000 { - compatible = "fsl,imx8mp-dsp"; - reg = <0x3b6e8000 0x88000>; - mbox-names = "txdb0", "txdb1", - "rxdb0", "rxdb1"; - mboxes = <&mu2 2 0>, <&mu2 2 1>, - <&mu2 3 0>, <&mu2 3 1>; - memory-region = <&dsp_reserved>; - status = "disabled"; + vpu_g1: vpu_g1@38300000 { + compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; + reg = <0x0 0x38300000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <800000000>; + power-domains = <&vpumix_blk_ctl IMX8MP_VPUBLK_PD_G1>; + status = "disabled"; + }; + + vpu_g2: vpu_g2@38310000 { + compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro"; + reg = <0x0 0x38310000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <700000000>, <800000000>, <700000000>; + power-domains = <&vpumix_blk_ctl IMX8MP_VPUBLK_PD_G2>; + status = "disabled"; + }; + + vpu_vc8000e: vpu_vc8000e@38320000 { + compatible = "nxp,imx8mp-hantro-vc8000e"; + reg = <0x0 0x38320000 0x0 0x10000>; + reg-names = "regs_hantro_vc8000e"; + interrupts = ; + interrupt-names = "irq_hantro_vc8000e"; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro_vc8000e", "clk_hantro_vc8000e_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <800000000>; + power-domains = <&vpumix_blk_ctl IMX8MP_VPUBLK_PD_VC8000E>; + status = "disabled"; + }; + + vpu_v4l2: vpu_v4l2 { + compatible = "nxp,imx8m-vsiv4l2"; + status = "disabled"; + }; + + gpu_3d: gpu3d@38000000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x38000000 0x0 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "shader", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <1000000000>, + <800000000>, <400000000>; + power-domains = <&pgc_gpu3d>; + status = "disabled"; + }; + + gpu_2d: gpu2d@38008000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x38008000 0x0 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <800000000>, <400000000>; + power-domains = <&pgc_gpu2d>; + status = "disabled"; + }; + + ml_vipsi: vipsi@38500000 { + compatible = "fsl,imx8-gpu", "fsl,imx8-vipsi"; + reg = <0x0 0x38500000 0x0 0x20000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + clock-names = "core", "shader", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <800000000>, <400000000>; + power-domains = <&pgc_mlmix>; + status = "disabled"; + }; + + mix_gpu_ml: mix_gpu_ml { + compatible = "fsl,imx8mp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d>, <&ml_vipsi>, <&gpu_2d>; + reg = <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + memory-region=<&gpu_reserved>; + status = "disabled"; + }; + + dsp: dsp@3b6e8000 { + compatible = "fsl,imx8mp-hifi4"; + reg = <0x0 0x3B6E8000 0x0 0x88000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT>; + clock-names = "ocram", "core", "debug"; + firmware-name = "imx/dsp/hifi4.bin"; + power-domains = <&audiomix_pd>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu2 0 0>, + <&mu2 1 0>, + <&mu2 3 0>; + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + fsl,dsp-ctrl = <&audio_blk_ctrl>; + status = "disabled"; + }; + + i2c_rpbus_3: i2c-rpbus-3 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + etm0: etm@28440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28440000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_0>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + etm1: etm@28540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28540000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_1>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; + + etm2: etm@28640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28640000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_2>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port2>; + }; + }; + }; + }; + + etm3: etm@28740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x28740000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_3>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port3>; + }; + }; + }; + }; + + funnel0: funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + ca_funnel_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + ca_funnel_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + + }; + + funnel1: funnel@28c03000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x28c03000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + /* M7 input */ + }; + }; + + port@2 { + reg = <2>; + hugo_funnel_in_port2: endpoint { + /* DSP input */ + }; + }; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf@28c04000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x28c04000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + }; + + etr@28c06000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x28c06000 0x0 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; }; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-8mic-swpdm.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-8mic-swpdm.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-8mic-swpdm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-8mic-swpdm.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + sound-micfil { + status = "disabled"; + }; + + dmic: dmic { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + wakeup-delay-ms = <250>; + }; + + sound-swpdm { + compatible = "fsl,imx-audio-card"; + model = "imx-swpdm-audio"; + pri-dai-link { + link-name = "PDM PCM"; + format = "pdm"; + cpu { + sound-dai = <&sai5>; + }; + codec { + sound-dai = <&dmic>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_sai5:sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0xd6 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + dmas = <&sdma2 8 24 0>, <&sdma2 9 24 0>; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + fsl,sai-mclk-direction-output; + fsl,dataline = <2 0xf 0xf>; + status = "okay"; +}; + +&uart3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-basler.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Basler AG + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + basler_camera_vvcam@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x00>; + status = "okay"; + + port { + basler_ep_0: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <500000000>; + max-data-rate = /bits/ 64 <0>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + mipi_csi0_ep: endpoint { + remote-endpoint = <&basler_ep_0>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + /delete-node/port@1; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&i2c3 { + /delete-node/ov5640_mipi@3c; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov2775.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2021 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&iomuxc { + pinctrl_csi1_pwn: csi1_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10 + >; + }; + + pinctrl_csi1_rst: csi1_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x10 + >; + }; +}; + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + basler_camera@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x00>; + status = "okay"; + + port { + basler_ep_0: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <266000000>; + max-data-rate = /bits/ 64 <0>; + + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; +}; + +&i2c3 { + /delete-node/ov5640_mipi@3c; + + ov2775_1: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_1_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; + +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + mipi_csi0_ep: endpoint { + remote-endpoint = <&basler_ep_0>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; + + port@1 { + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov2775_mipi_1_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&isp_1 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-basler-ov5640.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + basler_camera@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x00>; + status = "okay"; + + port { + basler_ep_0: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <266000000>; + max-data-rate = /bits/ 64 <0>; + + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + mipi_csi0_ep: endpoint { + remote-endpoint = <&basler_ep_0>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; +}; + +&ov5640_1 { + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + csi_id = <1>; + + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "okay"; +}; + +&isp_0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-dpdk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-dpdk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-dpdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-dpdk.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021-2023 NXP + */ + +#include "imx8mp-evk.dts" + +ðphy1 { + /delete-property/ reset-gpios; + /delete-property/ reset-assert-us; + /delete-property/ reset-deassert-us; +}; + +&fec { + compatible = "fsl,imx8mm-fec-uio"; +}; + +&eqos { + compatible = "fsl,imx-enet-qos", "snps,dwmac-5.10a"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-dsp.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2021 + +#include "imx8mp-evk.dts" + +/ { + sound-wm8960 { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000026 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000026 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 + >; + }; + +}; + +&dsp { + compatible = "fsl,imx8mp-hifi4"; + reg = <0x0 0x3B6E8000 0x0 0x88000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>, <&pinctrl_i2c3>, <&pinctrl_uart4>, <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>, + <&clk IMX8MP_CLK_I2C3_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_ASRC_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, + <&clk IMX8MP_CLK_UART4_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT>; + clock-names = "ocram", "core", "debug", + "per_clk1", "per_clk2", "per_clk3", "per_clk4", "per_clk5", "per_clk6", + "per_clk7", "per_clk8", "per_clk9"; + firmware-name = "imx/dsp/hifi4.bin"; + power-domains = <&audiomix_pd>; + mbox-names = "tx0", "rx0", "rxdb0"; + mboxes = <&mu2 0 0>, + <&mu2 1 0>, + <&mu2 3 0>; + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + syscon = <&audio_blk_ctrl>; + status = "okay"; +}; + +&i2c3 { + status = "disabled"; +}; + +&easrc { + status = "disabled"; +}; + +&codec { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&uart3 { + status = "disabled"; +}; + +&micfil { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk.dts 2024-06-19 12:33:58.292192429 +0200 @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "imx8mp.dtsi" / { @@ -71,6 +72,19 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; enable-active-high; + regulator-always-on; + }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-name = "USB_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; }; reg_usdhc2_vmmc: regulator-usdhc2 { @@ -83,22 +97,204 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + audio-asrc = <&easrc>; + hp-det-gpio = <&gpio4 28 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "Mic Jack", "MICB"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + pri-dai-link { + link-name = "XCVR PCM"; + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + + lvds_backlight: lvds_backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 100000 0>; + status = "okay"; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; }; &A53_0 { - cpu-supply = <®_arm>; + cpu-supply = <&buck2>; }; &A53_1 { - cpu-supply = <®_arm>; + cpu-supply = <&buck2>; }; &A53_2 { - cpu-supply = <®_arm>; + cpu-supply = <&buck2>; }; &A53_3 { - cpu-supply = <®_arm>; + cpu-supply = <&buck2>; +}; + +&dsp { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&aud2htx { + status = "okay"; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev1: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; }; &eqos { @@ -212,6 +408,7 @@ reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; + realtek,aldps-enable; realtek,clkout-disable; }; }; @@ -228,6 +425,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; xceiver-supply = <®_can2_stby>; + pinctrl-assert-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; status = "disabled";/* can2 pin conflict with pdm */ }; @@ -246,19 +444,19 @@ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; regulators { - BUCK1 { + buck1: BUCK1 { regulator-name = "BUCK1"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; }; - reg_arm: BUCK2 { + buck2: BUCK2 { regulator-name = "BUCK2"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1025000>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; @@ -266,47 +464,63 @@ nxp,dvs-standby-voltage = <850000>; }; - BUCK4 { + buck4: BUCK4{ regulator-name = "BUCK4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - BUCK5 { + buck5: BUCK5{ regulator-name = "BUCK5"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - BUCK6 { + buck6: BUCK6 { regulator-name = "BUCK6"; - regulator-min-microvolt = <1045000>; - regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - LDO1 { + ldo1: LDO1 { regulator-name = "LDO1"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - LDO3 { + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { regulator-name = "LDO3"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - LDO5 { + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { regulator-name = "LDO5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; @@ -317,6 +531,106 @@ }; }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + lvds_bridge: lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + + port { + it6263_in: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; + + ov5640_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + + port { + ov5640_mipi_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + }; + }; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio4>; + interrupts = <19 8>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + &i2c3 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -351,6 +665,44 @@ "EXP_P1_6", "EXP_P1_7"; }; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <3 2 3>; + wlf,gpio-cfg = <1 3>; + SPKVDD1-supply = <®_audio_pwr>; + }; + + ov5640_1: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "disabled"; + + port { + ov5640_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + }; + }; + }; }; /* I2C on expansion connector J22. */ @@ -368,6 +720,72 @@ */ }; +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi_blk_ctrl { + status = "okay"; +}; + +&hdmi_pavi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&lcdif1 { + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; + + thres-low = <1 2>; /* (FIFO * 1 / 2) */ + thres-high = <3 4>; /* (FIFO * 3 / 4) */ +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@1 { + reg = <1>; + + lvds_out: endpoint { + remote-endpoint = <&it6263_in>; + }; + }; + }; +}; + +&ldb_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; + &pcie_phy { fsl,refclk-pad-mode = ; clocks = <&pcie0_refclk>; @@ -388,12 +806,96 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; vpcie-supply = <®_pcie0>; status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio5>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&pcie_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <500000000>, <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL2_50M>; + status = "disabled"; +}; + +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MP_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; }; &snvs_pwrkey { status = "okay"; }; +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&xcvr { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sdma2 { + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8997-bt"; + }; +}; + &uart2 { /* console */ pinctrl-names = "default"; @@ -401,7 +903,41 @@ status = "okay"; }; +&usb3_phy0 { + fsl,phy-tx-vref-tune = <0xe>; + fsl,phy-tx-preemp-amp-tune = <3>; + fsl,phy-tx-vboost-level = <5>; + fsl,phy-comp-dis-tune = <7>; + fsl,pcs-tx-deemph-3p5db = <0x21>; + fsl,phy-pcs-tx-swing-full = <0x7f>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "none"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + &usb3_phy1 { + fsl,phy-tx-preemp-amp-tune = <3>; + fsl,phy-tx-vref-tune = <0xb>; status = "okay"; }; @@ -410,12 +946,20 @@ }; &usb_dwc3_1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus>; + vbus-supply = <®_usb_vbus>; dr_mode = "host"; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; assigned-clock-rates = <400000000>; @@ -449,6 +993,55 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010 + /* + * M.2 pin20 & pin21 need to be set to 11 for 88W9098 to select the + * default Reference Clock Frequency + */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 @@ -515,6 +1108,17 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 @@ -528,6 +1132,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 @@ -542,10 +1153,17 @@ >; }; + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 + >; + }; + pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c4 >; }; @@ -573,6 +1191,64 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x16 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_typec: typec1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + >; + }; + + pinctrl_typec_mux: typec1muxgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 @@ -582,7 +1258,16 @@ pinctrl_usb1_vbus: usb1grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 >; }; @@ -681,4 +1366,112 @@ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 >; }; + + pinctrl_csi0_pwn: csi0_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x10 + >; + }; + + pinctrl_csi0_rst: csi0_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10 + >; + }; + + pinctrl_csi_mclk: csi_mclk_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x50 + >; + }; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_vc8000e { + status = "okay"; +}; + +&vpu_v4l2 { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&gpu_2d { + status = "okay"; +}; + +&ml_vipsi { + status = "okay"; +}; + +&mix_gpu_ml { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_0_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov5640_mipi_1_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "disabled"; + + cap_device { + status = "okay"; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2021 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + basler_0: basler_camera_vvcam@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x00>; + status = "okay"; + + port { + basler_ep_0: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <266000000>; + max-data-rate = /bits/ 64 <0>; + + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /delete-node/ov5640_mipi@3c; + + basler_1: basler_camera_vvcam@36 { + compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; + reg = <0x36>; + csi_id = <0x01>; + status = "okay"; + + port { + basler_ep_1: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <750000000>; + + max-lane-frequency = /bits/ 64 <750000000>; + max-pixel-frequency = /bits/ 64 <266000000>; + max-data-rate = /bits/ 64 <0>; + + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&isp_1 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + clock-frequency = <266000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&basler_ep_0>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&basler_ep_1>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-os08a20.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-os08a20.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-os08a20.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-os08a20.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + os08a20_0: os08a20_mipi@36 { + compatible = "ovti,os08a20"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_mclk>; + clocks = <&clk_dummy>; + clock-names = "csi_mclk"; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + os08a20_mipi_0_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /delete-node/ov5640_mipi@3c; + + os08a20_1: os08a20_mipi@36 { + compatible = "ovti,os08a20"; + reg = <0x36>; + clocks = <&clk_dummy>; + clock-names = "csi_mclk"; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + os08a20_mipi_1_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&isp_1 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + clock-frequency = <266000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; + + port@0 { + endpoint { + remote-endpoint = <&os08a20_mipi_0_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&os08a20_mipi_1_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + ov2775_0: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_0_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /delete-node/ov5640_mipi@3c; + + ov2775_1: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_1_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&isp_1 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + clock-frequency = <266000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + assigned-clock-rates = <266000000>; + + port@0 { + endpoint { + remote-endpoint = <&ov2775_mipi_0_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov2775_mipi_1_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-ecspi-slave.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-ecspi-slave.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-ecspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-ecspi-slave.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2020 NXP + +#include "imx8mp-evk.dts" + +/delete-node/&spidev1; + +&ecspi2 { + #address-cells = <0>; + /delete-property/cs-gpios; + spi-slave; +}; + +&pinctrl_ecspi2_cs { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x82 + >; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mp-evk.dts" + +&flexcan2 { + status = "okay";/* can2 pin conflict with pdm */ +}; + +&micfil { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dac2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dac2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dac2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dac2.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP. + */ + +#include "imx8mp-evk-hifiberry-dacplus.dts" + +/ { + sound-pcm512x { + audio-widgets = + "Headphone", "Headphone Jack", + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + aux-devs= <&headphone_amp>; + }; +}; + +&i2c3 { + headphone_amp: amp@60 { + compatible = "ti,tpa6130a2"; + Vdd-supply = <®_3v3_vext>; + reg = <0x60>; + status = "okay"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dacplusadc.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dacplusadc.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dacplusadc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dacplusadc.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP. + */ + +#include "imx8mp-evk-hifiberry-dacplus.dts" + +/ { + sound-pcm512x { + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack", + "Line", "ADC1", + "Line", "ADC2"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR", + "VINL1", "ADC1", + "VINR1", "ADC2"; + adc,pluspro; + + pri-dai-link { + sndcodec: codec { + sound-dai = <&pcm512x>, <&pcm186x>; + }; + }; + }; +}; + +&i2c3 { + pcm186x: pcm186x@4a { + compatible = "ti,pcm1863"; + reg = <0x4a>; + iovdd-supply = <®_3v3_vext>; + avdd-supply = <®_3v3_vext>; + dvdd-supply = <®_3v3_vext>; + #sound-dai-cells = <0>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dacplus.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dacplus.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dacplus.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-hifiberry-dacplus.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mp-evk.dts" + +/ { + ext_osc_22m: ext-osc-22m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + clock-output-names = "sclk0"; + }; + + ext_osc_24m: ext-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-output-names = "sclk1"; + }; + + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + dac,24db_digital_gain; + dac,led_status; + dac,sclk; + + pri-dai-link { + link-name = "pcm512x-hifi"; + format = "i2s"; + bitclock-master = <&sndcodec>; + frame-master = <&sndcodec>; + cpu { + sound-dai = <&sai5>; + }; + sndcodec: codec { + sound-dai = <&pcm512x>; + }; + }; + }; +}; + +&i2c3 { + pcm512x: pcm512x@4d { + compatible = "ti,pcm5122"; + reg = <0x4d>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + clocks = <&ext_osc_22m>, <&ext_osc_24m>; + clock-names = "sclk0", "sclk1"; + #sound-dai-cells = <0>; + }; +}; + +&iomuxc { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0xd6 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include + +/ { + model = "Freescale i.MX8MP EVK"; + compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-affinity = <&A53_2>, <&A53_3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_400m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + + osc_24m: clock@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 155 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 156 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + aips3: bus@30800000 { + compatible = "simple-bus"; + reg = <0x30800000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_400m>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacplus.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacplus.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacplus.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacplus.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mp-evk.dts" + +/ { + reg_3v3_vext: regulator-3v3-vext { + compatible = "regulator-fixed"; + regulator-name = "3V3_VEXT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-pcm512x { + compatible = "fsl,imx-audio-pcm512x"; + model = "pcm512x-audio"; + audio-widgets = + "Line", "Left Line Out Jack", + "Line", "Right Line Out Jack"; + audio-routing = + "Left Line Out Jack", "OUTL", + "Right Line Out Jack", "OUTR"; + dac,24db_digital_gain; + + pri-dai-link { + link-name = "pcm512x-hifi"; + format = "i2s"; + cpu { + sound-dai = <&sai5>; + }; + + codec { + sound-dai = <&pcm512x>; + }; + }; + }; +}; + +&i2c3 { + pcm512x: pcm512x@4c { + compatible = "ti,pcm5122"; + reg = <0x4c>; + AVDD-supply = <®_3v3_vext>; + DVDD-supply = <®_3v3_vext>; + CPVDD-supply = <®_3v3_vext>; + #sound-dai-cells = <0>; + }; +}; + +&iomuxc { + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0xd6 + >; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacpro.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacpro.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacpro.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacpro.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP. + */ + +#include "imx8mp-evk-iqaudio-dacplus.dts" + +&i2c3 { + pcm512x: pcm512x@4c { + compatible = "ti,pcm5142"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-it6263-lvds-dual-channel.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mp-evk.dts" + +&lvds_bridge { + split-mode; +}; + +&ldb { + fsl,dual-channel; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + lvds0_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight>; + + port { + panel_lvds_in: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; +}; + +/delete-node/ &lvds_bridge; + +&ldb { + status = "okay"; + fsl,dual-channel; + + lvds-channel@0 { + /delete-node/ port@1; + + port@1 { + reg = <1>; + + lvds_out: endpoint { + remote-endpoint = <&panel_lvds_in>; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-ndm.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-ndm.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-ndm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-ndm.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + model = "NXP i.MX8MPlus EVK board in Nominal Drive Mode"; +}; + +&clk { + assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, + <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-rates = <400000000>, + <600000000>, + <393216000>, + <361267200>, + <1039500000>; +}; + +&gpu_2d { + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>, + <&clk IMX8MP_GPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_GPU_PLL_OUT>, + <&clk IMX8MP_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <600000000>, + <300000000>, <600000000>; +}; + +&gpu_3d { + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>, + <&clk IMX8MP_GPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_GPU_PLL_OUT>, + <&clk IMX8MP_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <800000000>, + <600000000>, <300000000>, + <600000000>; +}; + +&ml_vipsi { + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <800000000>, <300000000>; +}; + +&pcie{ + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <400000000>, <10000000>; +}; + +&pcie_ep{ + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <400000000>, <10000000>; +}; + +&usb_dwc3_0 { + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&usb_dwc3_1 { + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&vpu_g1 { + + assigned-clocks = <&clk IMX8MP_VPU_PLL>, <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <0>, <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, <600000000>, <600000000>; +}; + +&vpu_g2 { + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <500000000>, <600000000>; +}; + +&vpu_vc8000e { + assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <400000000>, <600000000>; +}; + +&lcdif1 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <400000000>, <200000000>; +}; + +&lcdif2 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <400000000>, <200000000>; +}; + +&lcdif3 { + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <400000000>, <133000000>; + thres-low = <2 3>; /* (FIFO * 2 / 3) */ + thres-high = <3 3>; /* (FIFO * 3 / 3) */ + status = "okay"; +}; + +&isi_0 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <400000000>, <200000000>; +}; + +&isi_1 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <400000000>, <200000000>; +}; + +&mipi_csi_0 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&isp_0 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&isp_1 { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-os08a20.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-os08a20.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-os08a20.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-os08a20.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + os08a20_0: os08a20_mipi@36 { + compatible = "ovti,os08a20"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_mclk>; + clocks = <&clk_dummy>; + clock-names = "csi_mclk"; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + os08a20_mipi_0_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <500000000>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + + }; +}; + +&i2c3 { + /delete-node/ov5640_mipi@3c; + +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + endpoint { + remote-endpoint = <&os08a20_mipi_0_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + /delete-node/port@1; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-os08a20-ov5640.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-os08a20-ov5640.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-os08a20-ov5640.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-os08a20-ov5640.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&iomuxc { + pinctrl_csi1_pwn: csi1_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10 + >; + }; + + pinctrl_csi1_rst: csi1_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x10 + >; + }; +}; + +&ov5640_0 { + status = "disabled"; +}; + +&ov5640_1 { + pinctrl-0 = <&pinctrl_csi_mclk>; + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + csi_id = <1>; + + status = "okay"; +}; + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + os08a20_0: os08a20_mipi@36 { + compatible = "ovti,os08a20"; + reg = <0x36>; + pinctrl-names = "default"; + clocks = <&clk_dummy>; + clock-names = "csi_mclk"; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + os08a20_mipi_0_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "okay"; +}; + +&isp_0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + endpoint { + remote-endpoint = <&os08a20_mipi_0_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "imx8mp-evk.dts" + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + ov2775_0: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_0_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <500000000>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + ov5640_1: ov5640_mipi@3c { + status = "disabled"; + }; + + ov2775_1: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <1>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isp_0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + endpoint { + remote-endpoint = <&ov2775_mipi_0_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mp-evk.dts" + +&iomuxc { + pinctrl_csi1_pwn: csi1_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19 + >; + }; + + pinctrl_csi1_rst: csi1_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 + >; + }; +}; + +&i2c2 { + /delete-node/ov5640_mipi@3c; + + ov2775_0: ov2775_mipi@36 { + compatible = "ovti,ov2775"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + + port { + ov2775_mipi_0_ep: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + max-pixel-frequency = /bits/ 64 <266000000>; + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + + }; +}; + +&i2c3 { + /delete-node/ov2775_mipi@36; +}; + +&ov5640_1 { + pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>, <&pinctrl_csi_mclk>; + csi_id = <1>; + + status = "okay"; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + status = "okay"; +}; + +&isp_0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + endpoint { + remote-endpoint = <&ov2775_mipi_0_ep>; + data-lanes = <4>; + csis-hs-settle = <16>; + }; + }; +}; + +&mipi_csi_1 { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mp-evk.dts" + +&pcie{ + status = "disabled"; +}; + +&pcie_ep{ + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-revA3-8mic-revE.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-revA3-8mic-revE.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-revA3-8mic-revE.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-revA3-8mic-revE.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + mic_leds { + compatible = "gpio-leds"; + mic0 { + label = "mic0"; + gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic1 { + label = "mic1"; + gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic2 { + label = "mic2"; + gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic3 { + label = "mic3"; + gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic4 { + label = "mic4"; + gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic5 { + label = "mic5"; + gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic6 { + label = "mic6"; + gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic7 { + label = "mic7"; + gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sw_keys { + compatible = "gpio-keys"; + + sw4: volume_down { + label = "Volume Down"; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; + + sw3: volume_up { + label = "Volume Up"; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + }; + + sw2: volume_mute { + label = "Volume Mute"; + gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; + + sw1: key_act { + label = "Key Act"; + gpios = <&pca9555 12 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + reg_vddext_3v3: regulator-vddext { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&iomuxc { + pinctrl_swpdm_mute_irq: swpdm_mute_grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x19 + >; + }; + + pinctrl_pushbutton_irq: pushbutton_grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0xb0 + >; + }; +}; + +&i2c3 { + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pushbutton_irq>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_vddext_3v3>; + status = "okay"; + }; +}; + +&uart3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 NXP + */ + +#include + +/dts-v1/; +/plugin/; + +&{/} { + + sound-wm8960 { + status = "disabled"; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8962>; + audio-asrc = <&easrc>; + hp-det-gpio = <&gpio4 28 0>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN1R", "AMIC", + "IN1L", "AMIC"; + }; +}; + +&codec { + status = "disabled"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-rpmsg.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +/dts-v1/; + +#include "imx8mp-evk-rpmsg.dts" + +&rpmsg_audio { + model = "wm8962-audio"; + audio-routing = + "IN1R", "MICBIAS", + "IN1L", "MICBIAS"; + fsl,lpa-widgets = + "HPOUTL", "HPOUTR", "Playback", + "Capture", "IN1L", "IN1R"; +}; + +&i2c_rpbus_3 { + /delete-node/ wm8960@1a; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-rpmsg-lpv.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-rpmsg-lpv.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-rpmsg-lpv.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-rpmsg-lpv.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +/dts-v1/; + +#include "imx8mp-evk-revb4-rpmsg.dts" + +&rpmsg_audio { + /delete-property/ fsl,enable-lpa; + /delete-property/ fsl,rpmsg-in; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-sof-wm8962.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-sof-wm8962.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-sof-wm8962.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-revb4-sof-wm8962.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 NXP + */ + +#include "imx8mp-evk.dts" + +/delete-node/ &codec; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; + +/ { + /delete-node/ sound-wm8960; + + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_reserved_heap; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + sof-sound-wm8962 { + compatible = "simple-audio-card"; + label = "wm8962-audio"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + simple-audio-card,hp-det-gpio = <&gpio4 28 0>; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Microphone", "Headset Mic", + "Microphone", "Digital Mic", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Headphones", "HPOUTL", + "Headphones", "HPOUTR", + "Speaker", "SPKOUTL", + "Speaker", "SPKOUTR", + "Headset Mic", "MICBIAS", + "IN1R", "Headset Mic", + "IN1L", "Headset Mic", + "DMICDAT", "Digital Mic"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 1>; + }; + sndcodec: codec { + sound-dai = <&wm8962>; + }; + }; + }; +}; + +&dsp { + #sound-dai-cells = <1>; + compatible = "fsl,imx8mp-dsp"; + reg = <0x0 0x3B6E8000 0x0 0x88000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + + power-domains = <&audiomix_pd>; + + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>; + + clock-names = "ipg", "ocram", "core", + "sai3_bus", "sai3_mclk0", "sai3_mclk1", "sai3_mclk2", "sai3_mclk3", + "sdma3_root"; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&mu2 2 0>, <&mu2 2 1>, + <&mu2 3 0>, <&mu2 3 1>; + memory-region = <&dsp_reserved>; + /delete-property/ firmware-name; + + tplg-name = "sof-imx8mp-wm8962.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&wm8962 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sai3 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019,2021 NXP + */ + +#include "imx8mp-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts: synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-rm67199.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8mp-evk-rm67191.dts" + +/delete-node/ &synaptics_dsx_ts; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&i2c2 { + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + edge-failling-trigger; + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + interrupt-parent = <&gic>; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; +}; + +&cpu_pd_wait { + /delete-property/ compatible; +}; + +&clk { + init-on-array = ; +}; + +&{/busfreq} { + status = "disabled"; +}; + +&{/reserved-memory} { + jh_reserved: jh@fdc00000 { + no-map; + reg = <0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@fdb00000 { + no-map; + reg = <0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@fda00000 { + no-map; + reg = <0 0xfda00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@fd900000 { + no-map; + reg = <0 0xfd900000 0x0 0x00100000>; + }; + + pci_reserved: pci@fd700000 { + no-map; + reg = <0 0xfd700000 0x0 0x00200000>; + }; + + inmate_reserved: inmate@c0000000 { + no-map; + reg = <0 0xc0000000 0x0 0x3d700000>; + }; +}; + +&{/reserved-memory/linux,cma} { + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x60000000>; +}; + +&iomuxc { + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; +}; + +&usdhc3 { + status = "disabled"; +}; + +&uart4 { + /delete-property/ dmas; + /delete-property/ dma-names; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&uart2 { + /* uart4 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mp-evk.dts" + +/ { + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c_rpbus_3; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@55000000 { + reg = <0 0x55000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@55008000 { + reg = <0 0x55008000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@55400000 { + compatible = "shared-dma-pool"; + reg = <0 0x55400000 0 0x100000>; + no-map; + }; + + rsc_table: rsc-table@550ff000 { + reg = <0 0x550ff000 0 0x1000>; + no-map; + }; + + audio_reserved: audio@81000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x81000000 0 0x10000000>; + }; + + micfil_reserved: mic_rpmsg@91000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x91000000 0 0x100000>; + }; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + rpmsg_audio: rpmsg_audio { + compatible = "fsl,imx8mp-rpmsg-audio"; + model = "wm8960-audio"; + fsl,platform = "rpmsg-audio-channel"; + fsl,enable-lpa; + fsl,rpmsg-out; + fsl,rpmsg-in; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; + audio-codec = <&codec>; + memory-region = <&audio_reserved>; + power-domains = <&audiomix_pd>; + audio-routing = + "LINPUT1", "MICB", + "LINPUT3", "MICB"; + status = "okay"; + }; + + rpmsg_micfil: rpmsg_micfil { + compatible = "fsl,imx8mp-rpmsg-audio"; + model = "micfil-audio"; + fsl,platform = "rpmsg-micfil-channel"; + fsl,enable-lpa; + fsl,rpmsg-in; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k"; + memory-region = <&micfil_reserved>; + power-domains = <&audiomix_pd>; + status = "okay"; + }; + + imx8mp-cm7 { + compatible = "fsl,imx8mn-cm7"; + rsc-da = <0x55000000>; + clocks = <&clk IMX8MP_CLK_M7_DIV>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT>; + clock-names = "core", "audio"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; + status = "okay"; + fsl,startup-delay-ms = <500>; + }; +}; + +/* + * ATTENTION: M7 may use IPs like below + * ECSPI0/ECSPI2, FLEXCAN, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4, + * PWM4, SDMA1/SDMA2 + */ +&ecspi2 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexspi { + status = "disabled"; +}; + +/delete-node/ &i2c3; + +&i2c_rpbus_3 { + compatible = "fsl,i2c-rpbus"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ov5640_1: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "disabled"; + + port { + ov5640_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + }; + }; + }; + + codec: wm8960@1a { + compatible = "wlf,wm8960,lpa"; + reg = <0x1a>; + wlf,shared-lrclk; + SPKVDD1-supply = <®_audio_pwr>; + }; +}; + +&pwm4{ + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&micfil { + status = "disabled"; +}; + +&sdma3{ + status = "disabled"; +}; + +&uart3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg-lpv.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg-lpv.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg-lpv.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg-lpv.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx8mp-evk-rpmsg.dts" + +&rpmsg_audio { + /delete-property/ fsl,enable-lpa; + /delete-property/ fsl,rpmsg-in; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-pdm.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-pdm.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-pdm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-pdm.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2023 + +#include "imx8mp-evk.dts" + +/ { + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_reserved_heap; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + dmic: dmic { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + wakeup-delay-ms = <250>; + }; + + sof-sound-micfil { + compatible = "simple-audio-card"; + label = "micfil-audio"; + + simple-audio-card,dai-link { + format = "i2s"; + capture-only; + cpu { + sound-dai = <&dsp 2>; + }; + codec { + sound-dai = <&dmic>; + }; + }; + }; +}; + +&dsp { + #sound-dai-cells = <1>; + compatible = "fsl,imx8mp-dsp"; + reg = <0x0 0x3B6E8000 0x0 0x88000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + + power-domains = <&audiomix_pd>; + + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>; + clock-names = "ipg", "ocram", "core", "pdm_ipg_clk", "pdm_ipg_clk_app", "sdma3_root"; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&mu2 2 0>, <&mu2 2 1>, + <&mu2 3 0>, <&mu2 3 1>; + memory-region = <&dsp_reserved>; + /delete-property/ firmware-name; + + tplg-name = "sof-imx8mp-wm8960.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&micfil { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-sof-wm8960.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 + +#include "imx8mp-evk.dts" + +/ { + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_reserved_heap; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + sof-sound-wm8960 { + compatible = "simple-audio-card"; + label = "wm8960-audio"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + simple-audio-card,hp-det-gpio = <&gpio4 28 0>; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Headphones", "HP_L", + "Headphones", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "Mic Jack", "MICB"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 1>; + }; + sndcodec: codec { + sound-dai = <&codec>; + }; + }; + }; +}; + +&dsp { + #sound-dai-cells = <1>; + compatible = "fsl,imx8mp-dsp"; + reg = <0x0 0x3B6E8000 0x0 0x88000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + + power-domains = <&audiomix_pd>; + + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>; + + clock-names = "ipg", "ocram", "core", + "sai3_bus", "sai3_mclk0", "sai3_mclk1", "sai3_mclk2", "sai3_mclk3", + "sdma3_root"; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&mu2 2 0>, <&mu2 2 1>, + <&mu2 3 0>, <&mu2 3 1>; + memory-region = <&dsp_reserved>; + /delete-property/ firmware-name; + + tplg-name = "sof-imx8mp-wm8960.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&codec { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sai3 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-spdif-lb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-spdif-lb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-spdif-lb.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-spdif-lb.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + * + * This DTB showcase SPDIF loop back setup on i.MX8MP EVK. + * The signal path used to route SPDIF signal in loopback mode is: + * + * SPDIF_TX -> I2C5_SCL -> I2C5_SCL_3V3 -> J22 pin 3 -> + * J22 pin 5 -> I2C5_SDA_3V3 -> I2C5_SDA -> SPDIF_RX + */ + +#include "imx8mp-evk.dts" + +/ { + /delete-node/ regulator-can1-stby; +}; + +/delete-node/ &flexcan1; + +&xcvr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xcvr>; + pinctrl-assert-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; +}; + +&iomuxc { + + /delete-node/ flexcan1grp; + /delete-node/ flexcan1reggrp; + + pinctrl_xcvr: xcvrgrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0xd6 + MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0xd6 + >; + }; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-usdhc1-m2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-usdhc1-m2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-evk-usdhc1-m2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-evk-usdhc1-m2.dts 2024-06-19 12:33:58.292192429 +0200 @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + reg_usdhc1_vmmc: regulator-usdhc1 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc1_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_pwrseq>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_reg_usdhc1_vmmc: regusdhc1vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140 + >; + }; + + pinctrl_usdhc1_pwrseq: usdhc1pwrseq { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; +}; + +®_pcie0 { + status = "disabled"; +}; + +&pcie { + status = "disabled"; + /delete-node/ wifi_wake_host; +}; + +&pcie_phy { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + keep-power-in-suspend; + non-removable; + wakeup-source; + mmc-pwrseq = <&usdhc1_pwrseq>; + vmmc-supply = <®_usdhc1_vmmc>; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h 2024-06-19 12:33:58.292192429 +0200 @@ -13,10 +13,12 @@ #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x014 0x274 0x000 0x5 0x0 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M 0x018 0x278 0x000 0x5 0x0 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 @@ -58,26 +60,26 @@ #define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0 #define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 #define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__USB1_ID 0x03C 0x29C 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0 #define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__USB2_ID 0x040 0x2A0 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0 #define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0 #define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 #define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__USB1_PWR 0x044 0x2A4 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 #define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x048 0x2A8 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0 #define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x04C 0x2AC 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0 #define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0 #define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 #define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OC 0x050 0x2B0 0x000 0x1 0x0 #define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0 #define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0 #define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x050 0x2B0 0x000 0x6 0x0 @@ -258,10 +260,8 @@ #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF1_IN 0x0D4 0x334 0x544 0x3 0x1 #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 #define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 #define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0 #define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0 #define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0 #define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0 @@ -722,7 +722,7 @@ #define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 #define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 #define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x12 0x0 #define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 #define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 #define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-ddr3l-val.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8mq.dtsi" + +/ { + model = "NXP i.MX8MQ DDR3L ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + stdout-path = &uart1; + }; + + reg_usdhc2_vmmc: regulator-vsd-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2>; + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 + + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + >; + }; + + pinctrl_reg_usdhc2: regusdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_50M>; + assigned-clock-rates = <0>, <0>, <50000000>, <100000000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8mq.dtsi" + +/ { + model = "NXP i.MX8MQ DDR4 ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + stdout-path = &uart1; + }; + + + + reg_usdhc2_vmmc: regulator-vsd-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2>; + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + >; + }; + + pinctrl_reg_usdhc2: regusdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-ddr4-val-gpmi-nand.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2019 NXP + */ + +#include "imx8mq-ddr4-val.dts" + +&iomuxc { + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; + fsl,use-minimum-ecc; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq.dtsi 2024-06-19 12:33:58.300192566 +0200 @@ -11,7 +11,6 @@ #include "dt-bindings/input/input.h" #include #include -#include #include "imx8mq-pinfunc.h" / { @@ -21,6 +20,8 @@ #size-cells = <2>; aliases { + csi0 = &mipi_csi_1; + csi1 = &mipi_csi_2; ethernet0 = &fec1; gpio0 = &gpio1; gpio1 = &gpio2; @@ -120,6 +121,7 @@ #cooling-cells = <2>; nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; + cpu-idle-states = <&CPU_SLEEP>; }; A53_1: cpu@1 { @@ -138,6 +140,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_2: cpu@2 { @@ -156,6 +159,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_3: cpu@3 { @@ -174,6 +178,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_L2: l2-cache0 { @@ -183,6 +188,21 @@ cache-line-size = <64>; cache-sets = <1024>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + }; a53_opp_table: opp-table { @@ -266,48 +286,6 @@ }; }; }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 1>; - - trips { - gpu_alert: gpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - gpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - vpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 2>; - - trips { - vpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; }; timer { @@ -320,8 +298,27 @@ arm,no-tick-in-suspend; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT>, + <&clk IMX8MQ_CLK_DRAM_APB>, <&clk IMX8MQ_CLK_DRAM_APB>, + <&clk IMX8MQ_CLK_DRAM_CORE>, <&clk IMX8MQ_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MQ_SYS1_PLL_40M>, <&clk IMX8MQ_SYS1_PLL_400M>, + <&clk IMX8MQ_SYS1_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_NOC>, <&clk IMX8MQ_CLK_MAIN_AXI>, + <&clk IMX8MQ_CLK_AHB>, <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_SYS2_PLL_333M>, <&clk IMX8MQ_SYS1_PLL_133M>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys1_pll_40m", "sys1_pll_400m", + "sys1_pll_100m", "sys1_pll_800m", "noc_div", "main_axi_src", + "ahb_div", "osc_25m", "sys2_pll_333m", "sys1_pll_133m"; + interrupts = , , + , ; + interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + }; + soc: soc@0 { - compatible = "fsl,imx8mq-soc", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; @@ -329,6 +326,11 @@ nvmem-cells = <&imx8mq_uid>; nvmem-cell-names = "soc_unique_id"; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -338,57 +340,70 @@ sai1: sai@30010000 { #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; reg = <0x30010000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, - <&clk IMX8MQ_CLK_SAI1_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI1_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 1 0>, <&sdma2 9 1 0>; dma-names = "rx", "tx"; + fsl,dataline = <0 0xff 0xff>; status = "disabled"; }; sai6: sai@30030000 { #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; reg = <0x30030000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, - <&clk IMX8MQ_CLK_SAI6_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI6_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; dma-names = "rx", "tx"; + fsl,shared-interrupt; status = "disabled"; }; sai5: sai@30040000 { #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; reg = <0x30040000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, - <&clk IMX8MQ_CLK_SAI5_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI5_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; status = "disabled"; }; sai4: sai@30050000 { #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; reg = <0x30050000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, - <&clk IMX8MQ_CLK_SAI4_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI4_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; dma-names = "rx", "tx"; + fsl,dataline = <0 0x0 0xf>; status = "disabled"; }; @@ -586,7 +601,7 @@ }; ocotp: efuse@30350000 { - compatible = "fsl,imx8mq-ocotp", "syscon"; + compatible = "fsl,imx8mq-ocotp", "syscon", "simple-mfd"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; #address-cells = <1>; @@ -603,6 +618,12 @@ fec_mac_address: mac-address@90 { reg = <0x90 6>; }; + + imx8mq_soc: imx8mq-soc { + compatible = "fsl,imx8mq-soc"; + nvmem-cells = <&imx8mq_uid>; + nvmem-cell-names = "soc_unique_id"; + }; }; anatop: syscon@30360000 { @@ -611,6 +632,22 @@ interrupts = ; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -656,20 +693,25 @@ <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, <&clk IMX8MQ_AUDIO_PLL1>, - <&clk IMX8MQ_AUDIO_PLL2>; + <&clk IMX8MQ_AUDIO_PLL2>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>; assigned-clock-rates = <0>, <0>, <800000000>, <0>, <0>, <0>, <786432000>, - <722534400>; + <722534400>, + <0>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_ARM_PLL_OUT>, - <0>, + <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS2_PLL_500M>, <&clk IMX8MQ_AUDIO_PLL1>, - <&clk IMX8MQ_AUDIO_PLL2>; + <&clk IMX8MQ_AUDIO_PLL2>, + <0>, + <0>, + <&clk IMX8MQ_SYS1_PLL_266M>; }; src: reset-controller@30390000 { @@ -685,6 +727,7 @@ interrupts = ; interrupt-parent = <&gic>; interrupt-controller; + broken-wake-request-signals; #interrupt-cells = <3>; pgc { @@ -853,7 +896,7 @@ <0x08000000 0x08000000 0x10000000>; spdif1: spdif@30810000 { - compatible = "fsl,imx35-spdif"; + compatible = "fsl,imx8mm-spdif", "fsl,imx35-spdif"; reg = <0x30810000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ @@ -937,6 +980,8 @@ clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, <&clk IMX8MQ_CLK_UART3_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -948,11 +993,13 @@ clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, <&clk IMX8MQ_CLK_UART2_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; spdif2: spdif@308a0000 { - compatible = "fsl,imx35-spdif"; + compatible = "fsl,imx8mm-spdif", "fsl,imx35-spdif"; reg = <0x308a0000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ @@ -981,9 +1028,10 @@ reg = <0x308b0000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_SAI2_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -991,13 +1039,15 @@ sai3: sai@308c0000 { #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; reg = <0x308c0000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, - <&clk IMX8MQ_CLK_SAI3_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI3_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -1041,14 +1091,20 @@ <&clk IMX8MQ_CLK_DSI_AHB>, <&clk IMX8MQ_CLK_DSI_IPG_DIV>, <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_VIDEO_PLL1>, <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, + clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "video_pll", "lcdif"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>, <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_AHB>, <&clk IMX8MQ_CLK_DSI_IPG_DIV>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, - <&clk IMX8MQ_SYS1_PLL_266M>; - assigned-clock-rates = <80000000>, <266000000>, <20000000>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <27000000>, + <266000000>, + <80000000>, + <20000000>; interrupts = ; mux-controls = <&mux 0>; power-domains = <&pgc_mipi>; @@ -1143,111 +1199,38 @@ clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, <&clk IMX8MQ_CLK_UART4_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; - mipi_csi1: csi@30a70000 { - compatible = "fsl,imx8mq-mipi-csi2"; + mipi_csi_1: mipi_csi1@30a70000 { + compatible = "fsl,mxc-mipi-csi2_yav"; reg = <0x30a70000 0x1000>; + interrupts = ; clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, - <&clk IMX8MQ_CLK_CSI1_ESC>, - <&clk IMX8MQ_CLK_CSI1_PHY_REF>; - clock-names = "core", "esc", "ui"; + <&clk IMX8MQ_CLK_CSI1_ESC>, + <&clk IMX8MQ_CLK_CSI1_PHY_REF>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, - <&clk IMX8MQ_CLK_CSI1_PHY_REF>, - <&clk IMX8MQ_CLK_CSI1_ESC>; - assigned-clock-rates = <266000000>, <333000000>, <66000000>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, - <&clk IMX8MQ_SYS2_PLL_1000M>, - <&clk IMX8MQ_SYS1_PLL_800M>; + <&clk IMX8MQ_CLK_CSI1_PHY_REF>, + <&clk IMX8MQ_CLK_CSI1_ESC>; + assigned-clock-rates = <133000000>, <100000000>, <66000000>; power-domains = <&pgc_mipi_csi1>; - resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; - fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; - interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; - interconnect-names = "dram"; + csis-phy-reset = <&src 0x4c 7>; + phy-gpr = <&iomuxc_gpr 0x88>; status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - csi1_mipi_ep: endpoint { - remote-endpoint = <&csi1_ep>; - }; - }; - }; }; - csi1: csi@30a90000 { - compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; + csi1_bridge: csi1_bridge@30a90000 { + compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; reg = <0x30a90000 0x10000>; interrupts = ; - clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; - clock-names = "mclk"; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_CSI1_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; status = "disabled"; - - port { - csi1_ep: endpoint { - remote-endpoint = <&csi1_mipi_ep>; - }; - }; - }; - - mipi_csi2: csi@30b60000 { - compatible = "fsl,imx8mq-mipi-csi2"; - reg = <0x30b60000 0x1000>; - clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, - <&clk IMX8MQ_CLK_CSI2_ESC>, - <&clk IMX8MQ_CLK_CSI2_PHY_REF>; - clock-names = "core", "esc", "ui"; - assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, - <&clk IMX8MQ_CLK_CSI2_PHY_REF>, - <&clk IMX8MQ_CLK_CSI2_ESC>; - assigned-clock-rates = <266000000>, <333000000>, <66000000>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, - <&clk IMX8MQ_SYS2_PLL_1000M>, - <&clk IMX8MQ_SYS1_PLL_800M>; - power-domains = <&pgc_mipi_csi2>; - resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; - fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; - interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; - interconnect-names = "dram"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - csi2_mipi_ep: endpoint { - remote-endpoint = <&csi2_ep>; - }; - }; - }; - }; - - csi2: csi@30b80000 { - compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; - reg = <0x30b80000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; - clock-names = "mclk"; - status = "disabled"; - - port { - csi2_ep: endpoint { - remote-endpoint = <&csi2_mipi_ep>; - }; - }; }; mu: mailbox@30aa0000 { @@ -1288,6 +1271,35 @@ status = "disabled"; }; + mipi_csi_2: mipi_csi2@30b60000 { + compatible = "fsl,mxc-mipi-csi2_yav"; + reg = <0x30b60000 0x1000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, + <&clk IMX8MQ_CLK_CSI2_ESC>, + <&clk IMX8MQ_CLK_CSI2_PHY_REF>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, + <&clk IMX8MQ_CLK_CSI2_PHY_REF>, + <&clk IMX8MQ_CLK_CSI2_ESC>; + assigned-clock-rates = <133000000>, <100000000>, <66000000>; + power-domains = <&pgc_mipi_csi2>; + csis-phy-reset = <&src 0x50 7>; + phy-gpr = <&iomuxc_gpr 0xa4>; + status = "disabled"; + }; + + csi2_bridge: csi2_bridge@30b80000 { + compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; + reg = <0x30b80000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_CSI2_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + qspi0: spi@30bb0000 { #address-cells = <1>; #size-cells = <0>; @@ -1345,31 +1357,6 @@ }; }; - noc: interconnect@32700000 { - compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; - reg = <0x32700000 0x100000>; - clocks = <&clk IMX8MQ_CLK_NOC>; - fsl,ddrc = <&ddrc>; - #interconnect-cells = <1>; - operating-points-v2 = <&noc_opp_table>; - - noc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-133M { - opp-hz = /bits/ 64 <133333333>; - }; - - opp-400M { - opp-hz = /bits/ 64 <400000000>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; - }; - aips4: bus@32c00000 { /* AIPS4 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; @@ -1377,6 +1364,14 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + hdmi: hdmi@32c00000 { + reg = <0x32c00000 0x100000>, + <0x32e40000 0x40000>; + interrupts = , + ; + interrupt-names = "plug_in", "plug_out"; + }; + irqsteer: interrupt-controller@32e2d000 { compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; reg = <0x32e2d000 0x1000>; @@ -1388,31 +1383,35 @@ interrupt-controller; #interrupt-cells = <1>; }; - }; - gpu: gpu@38000000 { - compatible = "vivante,gc"; - reg = <0x38000000 0x40000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, - <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>; - clock-names = "core", "shader", "bus", "reg"; - #cooling-cells = <2>; - assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, - <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>, - <&clk IMX8MQ_GPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL>; - assigned-clock-rates = <800000000>, <800000000>, - <800000000>, <800000000>, <0>; - power-domains = <&pgc_gpu>; + dcss: display-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>, <16>, <17>; + interrupt-names = "ctxld", "ctxld_kick", "vblank", + "dtrc_ch1", "dtrc_ch2"; + interrupt-parent = <&irqsteer>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_CLK_DISP_DTRC>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, + <&hdmi_phy_27m>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src", + "pll_phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rates = <800000000>, + <400000000>; + status = "disabled"; + }; }; usb_dwc3_0: usb@38100000 { @@ -1431,7 +1430,8 @@ phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg1>; - usb3-resume-missing-cas; + snps,parkmode-disable-ss-quirk; + snps,dis_rxdet_inp3_quirk; status = "disabled"; }; @@ -1463,7 +1463,8 @@ phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg2>; - usb3-resume-missing-cas; + snps,parkmode-disable-ss-quirk; + snps,dis_rxdet_inp3_quirk; status = "disabled"; }; @@ -1479,31 +1480,33 @@ status = "disabled"; }; - vpu_g1: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu-g1"; - reg = <0x38300000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; - power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; - }; - - vpu_g2: video-codec@38310000 { - compatible = "nxp,imx8mq-vpu-g2"; - reg = <0x38310000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; - power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; - }; - - vpu_blk_ctrl: blk-ctrl@38320000 { - compatible = "fsl,imx8mq-vpu-blk-ctrl"; - reg = <0x38320000 0x100>; - power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; - power-domain-names = "bus", "g1", "g2"; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>; - clock-names = "g1", "g2"; - #power-domain-cells = <1>; + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8MQ_CLK_RAWNAND_ROOT>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; }; pcie0: pcie@33800000 { @@ -1581,6 +1584,25 @@ status = "disabled"; }; + pcie1_ep: pcie_ep@33c00000 { + compatible = "fsl,imx8mq-pcie-ep"; + reg = <0x33c00000 0x000400000>, + <0x20000000 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ @@ -1594,22 +1616,55 @@ interrupt-parent = <&gic>; }; - ddrc: memory-controller@3d400000 { - compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; - reg = <0x3d400000 0x400000>; - clock-names = "core", "pll", "alt", "apb"; - clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, - <&clk IMX8MQ_DRAM_PLL_OUT>, - <&clk IMX8MQ_CLK_DRAM_ALT>, - <&clk IMX8MQ_CLK_DRAM_APB>; - status = "disabled"; - }; - ddr-pmu@3d800000 { compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; interrupt-parent = <&gic>; interrupts = ; }; + + vpu: vpu@38300000 { + compatible = "nxp,imx8mq-hantro"; + reg = <0x38300000 0x200000>; + reg-names = "regs_hantro"; + interrupts = , ; + interrupt-names = "irq_hantro_g1", "irq_hantro_g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro_g1", "clk_hantro_g2", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, <&clk IMX8MQ_CLK_VPU_G2>, <&clk IMX8MQ_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <600000000>, <800000000>; + power-domains = <&pgc_vpu>; + status = "disabled"; + }; + + vpu_v4l2: vpu_v4l2 { + compatible = "nxp,imx8m-vsiv4l2"; + status = "disabled"; + }; + }; + + gpu3d: gpu3d@38000000 { + compatible = "fsl,imx8mq-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0x0 0x40000>, <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = ; + interrupt-names = "irq_3d"; + clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, + <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, + <&clk IMX8MQ_CLK_GPU_AXI>, + <&clk IMX8MQ_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, + <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, + <&clk IMX8MQ_CLK_GPU_AXI>, + <&clk IMX8MQ_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <800000000>, <800000000>, <400000000>; + power-domains = <&pgc_gpu>; + status = "disabled"; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-ak4497.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,93 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-ak4458 { + status = "disabled"; + }; + + sound-ak4497 { + status = "okay"; + }; +}; + +&iomuxc { + + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd512: sai1grp_dsd512 { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd", "dsd512"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + pinctrl-2 = <&pinctrl_sai1_dsd512>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL2_OUT>; + assigned-clock-rates = <45158400>; + fsl,sai-multi-lane; + fsl,dataline = <2 0xff 0x11>; + dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-audio-tdm.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,33 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-ak4458 { + pri-dai-link { + format = "dsp_b"; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + }; + }; + + sound-ak5558 { + pri-dai-link { + format = "dsp_b"; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-adv7535.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-hdmi { + status = "disabled"; + }; +}; + +&irqsteer { + status = "okay"; +}; + +/delete-node/ &hdmi; + +&lcdif { + status = "disabled"; +}; + +&dcss { + status = "okay"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <0>, <0>, + <800000000>, + <400000000>; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&adv_bridge { + status = "okay"; + + port@0 { + adv7535_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + /delete-node/ panel@0; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mipi_dsi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&dcss_out>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67191.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +/delete-node/&hdmi; + +&irqsteer { + status = "okay"; +}; + +&lcdif { + status = "disabled"; +}; + +&dcss { + status = "okay"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_APB>, + <&clk IMX8MQ_CLK_DISP_RTRM>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <0>, <0>, + <800000000>, + <25000000>, + <400000000>; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + fsl,clock-drop-level = <2>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mipi_dsi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&dcss_out>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; + +&synaptics_dsx_ts { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-dcss-rm67199.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8mq-evk-dcss-rm67191.dts" + +/delete-node/ &synaptics_dsx_ts; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&i2c3 { + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_dsi_ts_int>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; + edge-failling-trigger; + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-dp.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +&irqsteer { + status = "okay"; +}; + +&dcss { + status = "okay"; + disp-dev = "hdmi_disp"; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; +}; + +&hdmi { + compatible = "cdn,imx8mq-dp"; + lane-mapping = <0xc6>; + hdcp-config = <0x3>; + status = "okay"; + + port@1 { + hdmi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk.dts 2024-06-19 12:33:58.296192498 +0200 @@ -6,6 +6,7 @@ /dts-v1/; +#include #include "imx8mq.dtsi" / { @@ -21,12 +22,56 @@ reg = <0x00000000 0x40000000 0 0xc0000000>; }; + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x38000000>; + alloc-ranges = <0 0x80000000 0 0x38000000>; + linux,cma-default; + }; + }; + pcie0_refclk: pcie0-refclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; + ptn36043 { + compatible = "nxp,ptn36043"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ss_sel>; + switch-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + reg_pcie1: regulator-pcie { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -36,6 +81,7 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; enable-active-high; + regulator-always-on; }; reg_usdhc2_vmmc: regulator-vsd-3v3 { @@ -46,6 +92,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -116,6 +163,8 @@ cpudai: simple-audio-card,cpu { sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; }; link_codec: simple-audio-card,codec { @@ -124,6 +173,20 @@ }; }; + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + audio-cpu = <&sai4>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + }; + sound-spdif { compatible = "fsl,imx-audio-spdif"; model = "imx-spdif"; @@ -138,6 +201,52 @@ spdif-controller = <&spdif2>; spdif-in; }; + + sound-ak4458 { + compatible = "fsl,imx-audio-card"; + model = "ak4458-audio"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + cpu { + sound-dai = <&sai1>; + }; + codec { + sound-dai = <&ak4458_1>, <&ak4458_2>; + }; + }; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-card"; + model = "ak5558-audio"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + cpu { + sound-dai = <&sai5>; + }; + codec { + sound-dai = <&ak5558>; + }; + }; + }; + + sound-ak4497 { + compatible = "fsl,imx-audio-card"; + model = "ak4497-audio"; + status = "disabled"; + pri-dai-link { + link-name = "akcodec"; + format = "i2s"; + cpu { + sound-dai = <&sai1>; + }; + codec { + sound-dai = <&ak4497>; + }; + }; + }; }; &A53_0 { @@ -156,36 +265,28 @@ cpu-supply = <&buck2_reg>; }; -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; +&csi1_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; status = "okay"; - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - /* - * On imx8mq B0 PLL can't be bypassed so low bus is 166M - */ - opp-166M { - opp-hz = /bits/ 64 <166935483>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; }; }; }; -&dphy { +&csi2_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; status = "okay"; + + port { + csi2_ep: endpoint { + remote-endpoint = <&csi2_mipi_ep>; + }; + }; }; &fec1 { @@ -205,6 +306,9 @@ reg = <0>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,aldps-enable; + realtek,clkout-disable; qca,disable-smarteee; vddio-supply = <&vddh>; @@ -214,6 +318,40 @@ }; }; +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi1_sensor_ep: endpoint@0 { + remote-endpoint = <&ov5640_mipi1_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + + csi1_mipi_ep: endpoint@1 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&mipi_csi_2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi2_sensor_ep: endpoint@0 { + remote-endpoint = <&ov5640_mipi2_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + + csi2_mipi_ep: endpoint@1 { + remote-endpoint = <&csi2_ep>; + }; + }; +}; + &gpio5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wifi_reset>; @@ -231,8 +369,31 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + ov5640_mipi2: ov5640_mipi2@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + csi_id = <1>; + pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi2_ep: endpoint { + remote-endpoint = <&mipi2_sensor_ep>; + }; + }; + }; + pmic@8 { compatible = "fsl,pfuze100"; + fsl,pfuze-support-disable-sw; reg = <0x8>; regulators { @@ -314,37 +475,131 @@ }; }; }; -}; -&lcdif { - status = "okay"; + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <3 8>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; }; -&mipi_dsi { - #address-cells = <1>; - #size-cells = <0>; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - panel@0 { - pinctrl-0 = <&pinctrl_mipi_dsi>; + synaptics_dsx_ts: synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; pinctrl-names = "default"; - compatible = "raydium,rm67191"; - reg = <0>; - reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; - dsi-lanes = <4>; + pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "disabled"; + }; - port { - panel_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; + ak4458_1: ak4458@10 { + #sound-dai-cells = <0>; + sound-name-prefix = "0"; + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + }; + + ak4458_2: ak4458@12 { + #sound-dai-cells = <0>; + sound-name-prefix = "1"; + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; }; - ports { - port@1 { - reg = <1>; - mipi_dsi_out: endpoint { - remote-endpoint = <&panel_in>; + ak5558: ak5558@13 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + reset-gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; + }; + + ak4497: ak4497@11 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; + dsd-path = <1>; + }; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + status = "disabled"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; }; }; }; @@ -375,6 +630,31 @@ vpcie-supply = <®_pcie1>; vph-supply = <&vgen5_reg>; status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&pcie1_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; + status = "disabled"; }; &pgc_gpu { @@ -398,15 +678,35 @@ spi-max-frequency = <29000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + spi-nor,ddr-quad-read-dummy = <6>; }; }; +&sai1 { + pinctrl-names = "default", "pcm_b2m", "dsd"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_pcm_b2m>; + pinctrl-2 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI1_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + fsl,dataline = <0 0xff 0xff 2 0xff 0x11>; + dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; + status = "okay"; +}; + &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <0>, <24576000>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; status = "okay"; }; @@ -420,6 +720,37 @@ status = "okay"; }; +&sai4 { + assigned-clocks = <&clk IMX8MQ_CLK_SAI4>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-multi-lane; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI5_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + fsl,sai-multi-lane; + dmas = <&sdma2 2 25 0>, <&sdma2 3 25 0>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -430,6 +761,14 @@ assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_CLK_SPDIF1>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_AUDIO_PLL1_OUT>, <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", + "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; status = "okay"; }; @@ -443,9 +782,47 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; status = "okay"; }; +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8997-bt"; + }; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "none"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + &usb3_phy1 { status = "okay"; }; @@ -490,12 +867,49 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x16 + >; + }; + pinctrl_buck2: vddarmgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 >; }; + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f + >; + }; + + pinctrl_csi1_pwn: csi1_pwn_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + >; + }; + pinctrl_csi2_pwn: csi2_pwn_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -529,9 +943,29 @@ >; }; - pinctrl_mipi_dsi: mipidsigrp { + pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_dsi_ts_int: dsi_ts_int { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x19 + >; + }; + + pinctrl_i2c3_dsi_ts_int: dsi_ts_int { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x59 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 >; }; @@ -546,6 +980,7 @@ fsl,pins = < MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 >; }; @@ -578,7 +1013,69 @@ MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 >; }; @@ -598,6 +1095,18 @@ >; }; + pinctrl_ss_sel: usb3ssgrp{ + fsl,pins = < + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 @@ -605,6 +1114,16 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 @@ -710,3 +1229,42 @@ >; }; }; + +&vpu { + vpu-supply = <&sw1c_reg>; + status = "okay"; +}; + +&vpu_v4l2 { + status = "okay"; +}; + +&gpu3d { + status = "okay"; +}; + +&irqsteer { + status = "okay"; +}; + +&dcss { + status = "okay"; + + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; +}; + +&hdmi { + compatible = "cdn,imx8mq-hdmi"; + lane-mapping = <0xe4>; + hdcp-config = <0x3>; + status = "okay"; + port@1 { + hdmi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-dual-display.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8mq-evk-lcdif-adv7535.dts" + +/ { + sound-hdmi { + status = "okay"; + }; +}; + +&irqsteer { + status = "okay"; +}; + +&dcss { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include + +/ { + model = "Freescale i.MX8MQ EVK"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial1 = &uart2; + mmc2 = &usdhc1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + interrupt-parent = <&gic>; + interrupt-affinity = <&A53_2>, <&A53_3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc_25m: clock-osc-25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc_25m"; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_400m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "400m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + + pci@bfb00000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 54 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbfb00000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + + aips3: bus@30800000 { + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x08000000 0x08000000 0x10000000>; + + uart2: serial@30890000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx8mq-usdhc", + "fsl,imx7d-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = ; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + }; + }; +}; + +&uart2 { + clocks = <&osc_25m>, + <&osc_25m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc1 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_400m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-adv7535.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + */ + +#include "imx8mq-evk.dts" + +/ { + sound-hdmi { + status = "disabled"; + }; +}; + +&irqsteer { + status = "okay"; +}; + +&hdmi { + status = "disabled"; +}; + +&dcss { + status = "disabled"; +}; + +&lcdif { + status = "okay"; + max-memory-bandwidth = <221184000>; /* 1280x720-32@60 */ + + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; + + port { + lcdif_out: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&adv_bridge { + status = "okay"; + + port@0 { + adv7535_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + /delete-node/ panel@0; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mipi_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcdif_out>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67191.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,97 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +&lcdif { + status = "okay"; + max-memory-bandwidth = <497829888>; /* 1920x1080-32@60.02 */ + + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rate = <126000000>, <0>, <0>, <1134000000>; + + port { + lcdif_mipi_dsi: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + fsl,clock-drop-level = <2>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mipi_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&iomuxc { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; +}; + +&synaptics_dsx_ts { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-lcdif-rm67199.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8mq-evk-lcdif-rm67191.dts" + +/delete-node/ &synaptics_dsx_ts; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&i2c3 { + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_dsi_ts_int>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; + edge-failling-trigger; + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie1-m2.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,29 @@ +/* + * Copyright 2017-2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + modem_reset: modem-reset { + reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&pcie0{ + status = "disabled"; +}; + +&gpio5 { + /delete-node/ wl-reg-on-hog; /* disable the on-board wifi */ +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-pcie-ep.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mq-evk.dts" + +&pcie0{ + status = "disabled"; +}; + +&pcie1{ + status = "disabled"; +}; + +&pcie1_ep{ + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-pdm.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8mq-evk.dts" + +/ { + dmic: dmic { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + wakeup-delay-ms = <250>; + }; + + sound-swpdm { + compatible = "fsl,imx-audio-card"; + model = "imx-swpdm-audio"; + pri-dai-link { + link-name = "PDM PCM"; + format = "pdm"; + cpu { + sound-dai = <&sai3>; + }; + codec { + sound-dai = <&dmic>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mq-evk.dts" + +/ { + interrupt-parent = <&gic>; +}; + +&CPU_SLEEP { + /* We are not using GPC for now, need set 0 to avoid hang */ + arm,psci-suspend-param = <0x0>; +}; + +&clk { + init-on-array = ; +}; + +&iomuxc { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&resmem { + jh_reserved: jh@fdc00000 { + no-map; + reg = <0 0xfdc00000 0x0 0x400000>; + }; + + inmate_reserved: inmate@c0000000 { + no-map; + reg = <0 0xc0000000 0x0 0x3dc00000>; + }; + + loader_reserved: loader@bff00000 { + no-map; + reg = <0 0xbff00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@bfe00000 { + no-map; + reg = <0 0xbfe00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@bfd00000 { + no-map; + reg = <0 0xbfd00000 0x0 0x00100000>; + }; + + pci_reserved: pci@bfc00000 { + no-map; + reg = <0 0xbfb00000 0x0 0x00200000>; + }; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x30000000>; + alloc-ranges = <0 0x80000000 0 0x30000000>; + linux,cma-default; + }; +}; + +&uart1 { + /* uart2 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>, + <&clk IMX8MQ_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_CLK_25M>; +}; + +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + /* sdhc1 is used by 2nd linux, configure the pin */ + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_200mhz>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-rpmsg.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mq-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@b8000000 { + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@b80ff000 { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + + linux,cma { + alloc-ranges = <0 0x40000000 0 0x80000000>; + }; + }; + + imx8mq-cm4 { + compatible = "fsl,imx8mq-cm4"; + rsc-da = <0xb8000000>; + clocks = <&clk IMX8MQ_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; + syscon = <&src>; + fsl,startup-delay-ms = <500>; + }; +}; + +/* + * Regarding to the HW conflications, the following module should be disabled + * when M4 is running on evk board. + * gpt1, i2c2, pwm4, tmu, uart2 + */ + +&i2c2 { + status = "disabled"; +}; + +&pwm4 { + status = "disabled"; +}; + +&tmu { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-usdhc2-m2.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mq-evk.dts" + +/ { + modem_reset: modem-reset { + reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwrseq>; + reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_usdhc2_pwrseq: usdhc2pwrseq { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x46 + >; + }; +}; + +&pinctrl_reg_usdhc2 { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x46 + >; +}; + +&pinctrl_usdhc2 { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41 + >; +}; + +&pinctrl_usdhc2_100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41 + >; +}; + +&pinctrl_usdhc2_200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41 + >; +}; + +®_pcie1{ + status = "disabled"; +}; + +&pcie0{ + status = "disabled"; +}; + +&pcie1{ + status = "disabled"; + /delete-node/ wifi_wake_host; +}; + +®_usdhc2_vmmc { + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; + /delete-property/ off-on-delay-us; +}; + +&usdhc2 { + pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + /delete-property/ cd-gpios; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + mmc-pwrseq = <&usdhc2_pwrseq>; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio2>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&gpio5 { + /delete-node/ wl-reg-on-hog; /* disable the on-board wifi */ +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-evk-usd-wifi.dts 2024-06-19 12:33:58.296192498 +0200 @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mq-evk.dts" + +&pinctrl_usdhc2 { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&pinctrl_usdhc2_100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&pinctrl_usdhc2_200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49 + >; +}; + +&usdhc2 { + pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + /delete-property/ cd-gpios; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; +}; + +®_usdhc2_vmmc { + /* this property is used for sd card SD3.0 mode, no need for SDIO wifi */ + /delete-property/ off-on-delay-us; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; +}; + +&gpio5 { + /delete-node/ wl-reg-on-hog; /* disable the on-board wifi */ +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-wevk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-wevk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8mq-wevk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8mq-wevk.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 NXP + */ + +/dts-v1/; + +#include "imx8mq-evk.dts" + +/ { + modem_reset: modem-reset { + reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; + }; + + reg_pcie0: regulator-pcie0 { + compatible = "regulator-fixed"; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&iomuxc { + pinctrl_pca6416_rst: pca6416grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 + >; + }; +}; + +&pinctrl_pcie0 { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x41 + >; +}; + +&i2c3 { + pca6416: gpio@20 { + compatible = "nxp,pca6416"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca6416_rst>; + reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&gpio5 { + /delete-node/ wl-reg-on-hog; /* This pin is not used on wevk board */ +}; + +&uart3 { /* BT */ + pinctrl-assert-gpios = <&pca6416 5 GPIO_ACTIVE_LOW>; +}; + +&pcie0 { + vpcie-supply = <®_pcie0>; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio3>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&pcie1 { + /delete-node/ wifi_wake_host; +}; + +ðphy0 { + /delete-property/ qca,disable-smarteee; + /delete-property/ vddio-supply; + reset-deassert-us = <80000>; + realtek,aldps-enable; + realtek,clkout-disable; + + /delete-node/ vddh-regulator; +}; + +&qspi0 { + assigned-clocks = <&clk IMX8MQ_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>; + assigned-clock-rates = <266000000>; + pinctrl-assert-gpios = <&pca6416 4 GPIO_ACTIVE_HIGH>; /* QSPIA_RESET */ + + w25q256jv: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <33250000>; /* driver will x4 = 133MHz */ + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca53.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca53.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca53.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca53.dtsi 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &lpuart0; + serial3 = &lpuart3; + mu1 = &lsio_mu1; + mu8 = &lsio_mu8; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + dpu0 = &dpu1; + ldb0 = &ldb1; + i2c0 = &i2c_rpbus_0; + i2c1 = &i2c_rpbus_1; + dphy0 = &mipi0_dphy; + mipi_dsi0 = &mipi0_dsi_host; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + }; + + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + a53_opp_table: a53-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x52000000 0 0x2000>, /* GICC */ + <0x0 0x52010000 0 0x1000>, /* GICH */ + <0x0 0x52020000 0 0x20000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; + status = "disabled"; + }; + + system-controller { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", + "rx0", + "gip3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 1 0 + &lsio_mu1 3 3>; + + pd: power-controller { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + wakeup-irq = <235 236 237 258 262 267 271 + 345 346 347 348>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; + #clock-cells = <2>; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + + ocotp: ocotp { + compatible = "fsl,imx8qm-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + read-only; + + fec_mac0: mac@1c4 { + reg = <0x1c4 6>; + }; + + fec_mac1: mac@1c6 { + reg = <0x1c6 6>; + }; + }; + + rtc: rtc { + compatible = "fsl,imx8qm-sc-rtc"; + }; + + scu_key: keys { + compatible = "fsl,imx8qm-sc-key", "fsl,imx-sc-key"; + linux,keycodes = ; + wakeup-source; + }; + + watchdog { + compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qm-sc-thermal"; + tsens-num = <4>; + #thermal-sensor-cells = <1>; + }; + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_A53>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; + trips { + gpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_DRC_0>; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + rpmsg0: rpmsg0{ + compatible = "fsl,imx8qm-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <5>; + status = "disabled"; + }; + + rpmsg1: rpmsg1{ + compatible = "fsl,imx8qm-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu6 0 1 + &lsio_mu6 1 1 + &lsio_mu6 3 1>; + mub-partition = <6>; + status = "disabled"; + }; + + imx_shmem_net: imx_shmem_net { + compatible = "fsl,imx-shmem-net"; + mub-partition = <3>; + mbox-names = "tx", "rx"; + mboxes = <&lsio_mu8 0 1 + &lsio_mu8 1 1>; + status = "disabled"; + }; + + vpu_subsys_dsp: bus@55000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x55000000 0x0 0x55000000 0x1000000>; + + dsp: dsp@556e8000 { + compatible = "fsl,imx8qm-dsp"; + reg = <0x556e8000 0x88000>; + clocks = <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "ipg", "ocram", "core"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>; + memory-region = <&dsp_reserved>; + fixup-offset = <0x4000000>; + status = "disabled"; + }; + }; + + /* sorted in register address */ + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm41.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-img.dtsi" + #include "imx8-ss-dc0.dtsi" + #include "imx8-ss-dc1.dtsi" + #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-gpu1.dtsi" + #include "imx8-ss-vpu.dtsi" +}; + +#include "imx8qm-ss-audio.dtsi" +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-conn.dtsi" +#include "imx8qm-ss-ddr.dtsi" +#include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-dc.dtsi" +#include "imx8qm-ss-lvds.dtsi" +#include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hdmi.dtsi" +#include "imx8qm-ss-img.dtsi" +#include "imx8qm-ss-gpu.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca72.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca72.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca72.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-cockpit-ca72.dtsi 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet1 = &fec2; + mmc0 = &usdhc1; + serial2 = &lpuart2; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + mu2 = &lsio_mu2; + dpu1 = &dpu2; + ldb1 = &ldb2; + dphy1 = &mipi1_dphy; + mipi_dsi1 = &mipi1_dsi_host; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&A72_0>; + }; + core1 { + cpu = <&A72_1>; + }; + }; + }; + + A72_0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x100>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; + #cooling-cells = <2>; + }; + + A72_1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x101>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; + #cooling-cells = <2>; + }; + + A72_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + a72_opp_table: a72-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1596000000 { + opp-hz = /bits/ 64 <1596000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x52000000 0 0x2000>, /* GICC */ + <0x0 0x52010000 0 0x1000>, /* GICH */ + <0x0 0x52020000 0 0x20000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; + status = "disabled"; + }; + + system-controller { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", + "rx0", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 1 0 + &lsio_mu2 3 3>; + + pd: power-controller { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + wakeup-irq = <235 236 237 258 262 267 271 + 345 346 347 348>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; + #clock-cells = <2>; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + + ocotp: ocotp { + compatible = "fsl,imx8qm-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + read-only; + + fec_mac0: mac@1c4 { + reg = <0x1c4 6>; + }; + + fec_mac1: mac@1c6 { + reg = <0x1c6 6>; + }; + }; + + rtc: rtc { + compatible = "fsl,imx8qm-sc-rtc"; + }; + + scu_key: keys { + compatible = "fsl,imx8qm-sc-key", "fsl,imx-sc-key"; + linux,keycodes = ; + wakeup-source; + }; + + watchdog { + compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qm-sc-thermal"; + tsens-num = <4>; + #thermal-sensor-cells = <1>; + }; + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_A72>; + trips { + cpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; + trips { + gpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_DRC_0>; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + rpmsg0: rpmsg0{ + compatible = "fsl,imx8qm-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + status = "disabled"; + }; + + rpmsg1: rpmsg1{ + compatible = "fsl,imx8qm-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu6 0 1 + &lsio_mu6 1 1 + &lsio_mu6 3 1>; + mub-partition = <4>; + status = "disabled"; + }; + + imx_shmem_net: imx_shmem_net { + compatible = "fsl,imx-shmem-net"; + mub-partition = <1>; + mbox-names = "tx", "rx"; + mboxes = <&lsio_mu8b 0 1 + &lsio_mu8b 1 1>; + status = "disabled"; + }; + + vpu_subsys_dsp: bus@55000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x55000000 0x0 0x55000000 0x1000000>; + + dsp: dsp@556e8000 { + compatible = "fsl,imx8qm-dsp"; + reg = <0x556e8000 0x88000>; + clocks = <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "ipg", "ocram", "core"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>; + memory-region = <&dsp_reserved>; + fixup-offset = <0x4000000>; + status = "disabled"; + }; + }; + + /* sorted in register address */ + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm41.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-img.dtsi" + #include "imx8-ss-dc0.dtsi" + #include "imx8-ss-dc1.dtsi" + #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-gpu1.dtsi" + #include "imx8-ss-vpu.dtsi" +}; + +#include "imx8qm-ss-audio.dtsi" +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-conn.dtsi" +#include "imx8qm-ss-ddr.dtsi" +#include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-dc.dtsi" +#include "imx8qm-ss-lvds.dtsi" +#include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hdmi.dtsi" +#include "imx8qm-ss-img.dtsi" +#include "imx8qm-ss-gpu.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ddr4-val.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,849 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM DDR4 VALIDATION"; + compatible = "fsl,imx8qm-val", "fsl,imx8qm"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1FD_BCM89359/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1FD_BCM89359/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&lsio_gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x1000000>; + no-map; + }; + dsp_reserved_heap: dsp_reserved_heap { + reg = <0 0x93400000 0 0xef0000>; + no-map; + }; + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0xc0000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_b 3 0>; + enable-active-high; + }; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&iomuxc { + imx8qm-val { + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + IMX8QM_USDHC2_RESET_B_CONN_USDHC2_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + /* WP */ + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + /* CD */ + IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds1_pwm0: lvds1pwm0grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&lsio_gpio2 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>,<&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>,<&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; + +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + rx-internal-delay-ps = <2000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + qca,disable-smarteee; + vddio-supply = <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + qca,disable-smarteee; + vddio-supply = <&vddio1>; + status = "disabled"; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + rx-internal-delay-ps = <2000>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <8>; + }; +}; + +&i2c0_hdmi { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + fxas2100x@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + }; + + fxos8700@1d { + compatible = "nxp,fxos8700"; + reg = <0x1d>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "isil,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <20 2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "disabled"; +}; + +&lpuart3 { /* GPS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&cm41_intmux { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -5,10 +5,13 @@ */ #include +#include #include #include +#include #include #include +#include / { interrupt-parent = <&gic>; @@ -16,6 +19,8 @@ #size-cells = <2>; aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; @@ -23,9 +28,41 @@ serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; + serial4 = &lpuart4; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + mu0 = &lsio_mu0; + mu1 = &lsio_mu1; + mu2 = &lsio_mu2; + mu3 = &lsio_mu3; + mu4 = &lsio_mu4; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + dpu0 = &dpu1; + dpu1 = &dpu2; + ldb0 = &ldb1; + ldb1 = &ldb2; + i2c0 = &i2c_rpbus_0; + i2c1 = &i2c_rpbus_1; + dphy0 = &mipi0_dphy; + dphy1 = &mipi1_dphy; + mipi_dsi0 = &mipi0_dsi_host; + mipi_dsi1 = &mipi1_dsi_host; + vpu_core0 = &vpu_core0; + vpu_core1 = &vpu_core1; + vpu_core2 = &vpu_core2; }; - cpus { + cpus: cpus { #address-cells = <2>; #size-cells = <0>; @@ -59,6 +96,7 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x0>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -67,12 +105,15 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; }; A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x1>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -81,12 +122,15 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; }; A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -95,12 +139,15 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; }; A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -109,12 +156,15 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; }; A72_0: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0 0x100>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; i-cache-size = <0xC000>; i-cache-line-size = <64>; @@ -123,14 +173,19 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; + #cooling-cells = <2>; }; A72_1: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0 0x101>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -150,6 +205,66 @@ }; }; + a53_opp_table: a53-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + }; + + opp-896000000 { + opp-hz = /bits/ 64 <896000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + a72_opp_table: a72-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1596000000 { + opp-hz = /bits/ 64 <1596000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ @@ -181,6 +296,44 @@ ; /* Hypervisor */ }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; + }; + system-controller { compatible = "fsl,imx-scu"; mbox-names = "tx0", @@ -193,6 +346,8 @@ pd: power-controller { compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; + wakeup-irq = <235 236 237 258 262 267 271 + 345 346 347 348>; }; clk: clock-controller { @@ -207,16 +362,207 @@ rtc: rtc { compatible = "fsl,imx8qxp-sc-rtc"; }; + + ocotp: ocotp { + compatible = "fsl,imx8qm-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + read-only; + + fec_mac0: mac@1c4 { + reg = <0x1c4 6>; + }; + + fec_mac1: mac@1c6 { + reg = <0x1c6 6>; + }; + }; + + scu_key: keys { + compatible = "fsl,imx8qm-sc-key", "fsl,imx-sc-key"; + linux,keycodes = ; + wakeup-source; + }; + + watchdog { + compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + tsens: thermal-sensor { + compatible = "fsl,imx-sc-thermal"; + tsens-num = <6>; + #thermal-sensor-cells = <1>; + }; + + secvio: secvio { + compatible = "fsl,imx-sc-secvio"; + nvmem = <&ocotp>; + }; + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_A53>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_A72>; + trips { + cpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; + trips { + gpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; + trips { + gpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_DRC_0>; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + vpu_subsys_dsp: bus@55000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x55000000 0x0 0x55000000 0x1000000>; + + dsp: dsp@556e8000 { + compatible = "fsl,imx8qm-hifi4"; + reg = <0x556e8000 0x88000>; + clocks = <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "core", "ipg", "ocram"; + firmware-name = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu13 0 0>, + <&lsio_mu13 1 0>, + <&lsio_mu13 3 0>; + status = "disabled"; + }; }; /* sorted in register address */ + #include "imx8-ss-audio.dtsi" #include "imx8-ss-img.dtsi" #include "imx8-ss-dma.dtsi" + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm41.dtsi" #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-dc0.dtsi" + #include "imx8-ss-dc1.dtsi" + #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-gpu1.dtsi" + #include "imx8-ss-vpu.dtsi" }; #include "imx8qm-ss-img.dtsi" +#include "imx8qm-ss-audio.dtsi" #include "imx8qm-ss-dma.dtsi" #include "imx8qm-ss-conn.dtsi" +#include "imx8qm-ss-ddr.dtsi" #include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-dc.dtsi" +#include "imx8qm-ss-lvds.dtsi" +#include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hdmi.dtsi" +#include "imx8qm-ss-hdmi-rx.dtsi" +#include "imx8qm-ss-gpu.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-enet2-tja1100.dtsi 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,77 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* fec1 cannot attach to ethphy0 since the PHY address + * conflict with ethphy2. So eth0 should not work. + * There still enable fec1 to share the MDIO bus for fec2 due + * to board limitation. + */ +&fec1 { + /* PHY address should rework to 3 */ + phy-handle = <ðphy3>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + nxp,rmii-refclk-in; + /delete-property/ qca,disable-smarteee; + /delete-property/ vddio-supply; + }; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + qca,disable-smarteee; + vddio-supply = <&vddio3>; + + vddio3: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_fec2_rmii>; + clocks = <&enet1_lpcg 4>, + <&enet1_lpcg 2>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_DISABLE_50>, + <&enet1_lpcg 0>, + <&enet1_lpcg 1>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + /delete-property/ phy-supply; + /delete-property/ rx-internal-delay-ps; + /delete-property/ tx-internal-delay-ps; +}; + +&iomuxc { + pinctrl_fec2_rmii: fec2rmiigrp { + fsl,pins = < + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT 0x06000020 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER 0x06000020 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-lpddr4-val.dts" + +&thermal_zones { + /delete-node/ cpu-thermal1; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-lpddr4-val.dts" + +&thermal_zones { + /delete-node/ cpu-thermal0; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@0; + /delete-node/ cpu@1; + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-dp.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ +/* + * DisplayPort, LVDS1, and MIPI DSI1, disable LVDS0 and MIPI DSI0. + */ +#include "imx8qm-lpddr4-val.dts" + +/ { + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-dp"; + audio-cpu = <&sai5>; + hdmi-out; + }; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&mipi0_dsi_host { + status = "disabled"; +}; + +&mipi0_dphy { + status = "disabled"; +}; + +&i2c0_mipi0 { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_lpcg_lis_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_i2s { + status = "okay"; +}; + +&hdmi_lpcg_gpio_ipg { + status = "okay"; +}; + +&hdmi_lpcg_msi_hclk { + status = "okay"; +}; + +&hdmi_lpcg_pxl { + status = "okay"; +}; + +&hdmi_lpcg_phy { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_csr { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_ctrl { + status = "okay"; +}; + +&hdmi_lpcg_apb { + status = "okay"; +}; + +&hdmi { + compatible = "cdn,imx8qm-dp"; + firmware-name = "dpfw.bin"; + lane-mapping = <0x1b>; + hdcp-config = <0x2>; + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,940 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM LPDDR4 Validation Board"; + compatible = "fsl,imx8qm-lpddr4-val", "fsl,imx8qm"; + + chosen { + stdout-path = &lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds1 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpu_reserved: gpu_reserved@8800000000 { + no-map; + reg = <0x8 0x80000000 0 0x10000000>; + }; + + decoder_boot: decoder_boot@84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + + encoder1_boot: encoder1_boot@86000000 { + no-map; + reg = <0 0x86000000 0 0x200000>; + }; + + encoder2_boot: encoder2_boot@86200000 { + no-map; + reg = <0 0x86200000 0 0x200000>; + }; + + decoder_rpc: decoder_rpc@92000000 { + no-map; + reg = <0 0x92000000 0 0x100000>; + }; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x1000000>; + no-map; + }; + dsp_reserved_heap: dsp_reserved_heap { + reg = <0 0x93400000 0 0xef0000>; + no-map; + }; + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + encoder1_rpc: encoder1_rpc@94400000 { + no-map; + reg = <0 0x94400000 0 0x700000>; + }; + encoder2_rpc: encoder1_rpc@94b00000 { + no-map; + reg = <0 0x94b00000 0 0x700000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0xc0000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai0>; + audio-codec = <&cs42888>; + audio-asrc = <&asrc0>; + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + }; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; + +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&pwm_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds0>; + status = "okay"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&i2c0_mipi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&dc1_pc { + status = "okay"; +}; + +&dc1_prg1 { + status = "okay"; +}; + +&dc1_prg2 { + status = "okay"; + +}; + +&dc1_prg3 { + status = "okay"; +}; + +&dc1_prg4 { + status = "okay"; +}; + +&dc1_prg5 { + status = "okay"; +}; + +&dc1_prg6 { + status = "okay"; +}; + +&dc1_prg7 { + status = "okay"; +}; + +&dc1_prg8 { + status = "okay"; +}; + +&dc1_prg9 { + status = "okay"; +}; + +&dc1_dpr1_channel1 { + status = "okay"; +}; + +&dc1_dpr1_channel2 { + status = "okay"; +}; + +&dc1_dpr1_channel3 { + status = "okay"; +}; + +&dc1_dpr2_channel1 { + status = "okay"; +}; + +&dc1_dpr2_channel2 { + status = "okay"; +}; + +&dc1_dpr2_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&pwm_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds1>; + status = "okay"; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>; + status = "okay"; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + qca,disable-smarteee; + vddio-supply = <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + qca,disable-smarteee; + vddio-supply = <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_pwm_lvds0: pwmlvds0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_pwm_lvds1: pwmlvds1grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 + >; + }; +}; + +&gpu_3d0{ + status = "okay"; +}; + +&gpu_3d1{ + status = "okay"; +}; + +&imx8_gpu_ss { + memory-region=<&gpu_reserved>; + status = "okay"; +}; + + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qm-lpddr4-val.dts" + +&iomuxc { + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x6000040 + IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x6000040 + IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x6000040 + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x21 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x6000040 + IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x6000040 + IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x6000040 + IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x6000040 + >; + }; +}; + +&lpspi0 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <5000000>; + reg = <0>; + }; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-lpspi-slave.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018~2019 NXP + */ + +#include "imx8qm-lpddr4-val-lpspi.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi3 { + fsl,pins = < + IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x6000040 + IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x6000040 + IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x6000040 + IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x6000040 + >; +}; + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + /delete-property/ cs-gpios; + spi-slave; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-mqs.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,79 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qm-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx8qm-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-cpu = <&sai1>; + audio-codec = <&mqs>; + audio-asrc = <&asrc1>; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_MQS_L 0xc6000061 + IMX8QM_SPDIF0_RX_AUD_MQS_R 0xc6000061 + >; + }; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "okay"; +}; + +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + status = "disabled"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-spdif.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,86 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qm-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; + + sound-mqs { + compatible = "fsl,imx8qm-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-cpu = <&sai1>; + audio-codec = <&mqs>; + status = "disabled"; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_AUD_MQS_L 0xc6000061 + IMX8QM_SPDIF0_RX_AUD_MQS_R 0xc6000061 + >; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "disabled"; +}; + +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-ca53.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek.dts" + +&thermal_zones { + /delete-node/ cpu-thermal1; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-ca72.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek.dts" + +&thermal_zones { + /delete-node/ cpu-thermal0; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@0; + /delete-node/ cpu@1; + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a53.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a53.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a53.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a53.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,1859 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +/dts-v1/; + +#include +#include "imx8qm-cockpit-ca53.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + stdout-path = &lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + brcmfmac: brcmfmac { + compatible = "cypress,brcmfmac"; + pinctrl-names = "init", "idle", "default"; + pinctrl-0 = <&pinctrl_wifi_init>; + pinctrl-1 = <&pinctrl_wifi_init>; + pinctrl-2 = <&pinctrl_wifi>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + status = "disabled"; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds1 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_modem_reset>; + pinctrl-1 = <&pinctrl_modem_reset_sleep>; + reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder_boot@84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder1_boot: encoder1_boot@86000000 { + no-map; + reg = <0 0x86000000 0 0x200000>; + }; + encoder2_boot: encoder2_boot@86200000 { + no-map; + reg = <0 0x86200000 0 0x200000>; + }; + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + rpmsg_reserved: rpmsg@90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + shmem_dma_reserved:shmem_dma@92000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x92000000 0 0x400000>; + }; + decoder_rpc: decoder_rpc@92000000 { + no-map; + reg = <0 0x92000000 0 0x0>; + }; + dsp_reserved: dsp@92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder1_rpc: encoder1_rpc@94400000 { + no-map; + reg = <0 0x94400000 0 0x700000>; + }; + encoder2_rpc: encoder1_rpc@94b00000 { + no-map; + reg = <0 0x94b00000 0 0x700000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x1e000000>; + alloc-ranges = <0 0xa2000000 0 0x1e000000>; + linux,cma-default; + }; + + a72_reserved { + no-map; + reg = <0 0xc0000000 0 0x40000000>; + }; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&lsio_gpio1 13 0>; + enable-active-high; + status = "disabled"; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_pciea: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea_reg>; + regulator-name = "mpcie_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio4 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <4800>; + enable-active-high; + }; + + reg_can01_en: regulator-can01-gen { + compatible = "regulator-fixed"; + regulator-name = "can01-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_can2_en: regulator-can2-gen { + compatible = "regulator-fixed"; + regulator-name = "can2-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_can01_stby: regulator-can01-stby { + compatible = "regulator-fixed"; + regulator-name = "can01-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can01_en>; + status = "disabled"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can2_en>; + status = "disabled"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960>; + codec-master; + /* + * hp-det = ; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + status = "disabled"; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cm41_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm41_i2c>; + status = "disabled"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + power-domains = <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + power-domain-names = "pd_mclk_out_0", + "pd_audio_clk_0", + "pd_audio_clk_1", + "pd_audio_clk_0", + "pd_audio_clk_1"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "disabled"; + }; +}; + +&cm41_intmux { + status = "disabled"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; + +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp-v1"; + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "disabled"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "disabled"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "disabled"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&pwm_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds0>; + status = "okay"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&i2c0_mipi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "disabled"; +}; + +&mipi1_dsi_host { + status = "disabled"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&dc1_pc { + status = "disabled"; +}; + +&dc1_prg1 { + status = "disabled"; +}; + +&dc1_prg2 { + status = "disabled"; + +}; + +&dc1_prg3 { + status = "disabled"; +}; + +&dc1_prg4 { + status = "disabled"; +}; + +&dc1_prg5 { + status = "disabled"; +}; + +&dc1_prg6 { + status = "disabled"; +}; + +&dc1_prg7 { + status = "disabled"; +}; + +&dc1_prg8 { + status = "disabled"; +}; + +&dc1_prg9 { + status = "disabled"; +}; + +&dc1_dpr1_channel1 { + status = "disabled"; +}; + +&dc1_dpr1_channel2 { + status = "disabled"; +}; + +&dc1_dpr1_channel3 { + status = "disabled"; +}; + +&dc1_dpr2_channel1 { + status = "disabled"; +}; + +&dc1_dpr2_channel2 { + status = "disabled"; +}; + +&dc1_dpr2_channel3 { + status = "disabled"; +}; + +&dpu2 { + status = "disabled"; +}; + +&pwm_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds1>; + status = "disabled"; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "disabled"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "disabled"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; + cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + +&emvsim0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim0>; + status = "okay"; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "disabled"; +}; + +&lpuart2 { /* Dbg console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "disabled"; +}; + +&lpuart3 { /* MKbus */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can01_stby>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can01_stby>; + status = "disabled"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can2_stby>; + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; + /delete-property/ iommus; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + qca,disable-smarteee; + vddio-supply = <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + qca,disable-smarteee; + vddio-supply = <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; + status = "disabled"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&pciea{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + epdev_on-supply = <&epdev_on>; + vpcie-supply = <®_pciea>; + reserved-region = <&rpmsg_reserved>; + status = "disabled"; +}; + +&rpmsg0{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + status = "okay"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90100000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + status = "okay"; +}; + +&imx_shmem_net { + memory-region = <&shmem_dma_reserved>; + status = "okay"; +}; + +&sata { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 30 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + /delete-property/ iommus; + status = "disabled"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "disabled"; +}; + +&usb3_phy { + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + /delete-property/ iommus; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + /delete-property/ iommus; + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "isil,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <11 2>; + }; + + fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas21002c@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + interrupt-open-drain; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + ptn5110: tcpc@51 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; +}; + +&isi_0 { + status = "disabled"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "disabled"; + + cap_device { + status = "okay"; + }; +}; + +&isi_2 { + status = "disabled"; + + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + status = "disabled"; + + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + status = "disabled"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "disabled"; + + cap_device { + status = "okay"; + }; +}; + +&isi_6 { + status = "disabled"; + + cap_device { + status = "okay"; + }; +}; + +&isi_7 { + status = "disabled"; + + cap_device { + status = "okay"; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&irqsteer_csi1 { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 1 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "disabled"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "disabled"; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c + >; + }; + + pinctrl_cm41_i2c: cm41i2cgrp { + fsl,pins = < + IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c + IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c + IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c + >; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c + IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c + IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c + IMX8QM_SPI2_CS0_DMA_SPI2_CS0 0x0600004c + >; + }; + + pinctrl_lpspi2_cs: lpspi2cs { + fsl,pins = < + IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 + >; + }; + + pinctrl_sim0: sim0grp { + fsl,pins = < + IMX8QM_SIM0_CLK_DMA_SIM0_CLK 0xc0000021 + IMX8QM_SIM0_IO_DMA_SIM0_IO 0xc2000021 + IMX8QM_SIM0_PD_DMA_SIM0_PD 0xc0000021 + IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN 0xc0000021 + IMX8QM_SIM0_RST_DMA_SIM0_RST 0xc0000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 + IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_pwm_lvds0: pwmlvds0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_pwm_lvds1: pwmlvds1grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_modem_reset: modemresetgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 + >; + }; + + pinctrl_modem_reset_sleep: modemreset_sleepgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_pciea_reg: pcieareggrp { + fsl,pins = < + IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 + IMX8QM_SAI1_RXC_AUD_SAI1_RXC 0x06000040 + IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS 0x06000040 + IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 + IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_mipi_csi0: mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_mipi_csi1: mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_wifi: wifigrp{ + fsl,pins = < + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_wifi_init: wifi_initgrp{ + fsl,pins = < + /* reserve pin init/idle_state to support multiple wlan cards */ + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 + >; + }; + +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&gpu_3d0{ + status = "okay"; +}; + +&gpu_3d1{ + status = "disabled"; +}; + +&imx8_gpu_ss { + cores = <&gpu_3d0>; + status = "okay"; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>; + }; +}; + +&mu_m0{ + interrupts = ; +}; + +&mu1_m0{ + interrupts = ; +}; + +&mu2_m0{ + interrupts = ; + status = "okay"; +}; + +&vpu { + compatible = "nxp,imx8qm-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d080000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d090000 0x10000>; + memory-region = <&encoder1_boot>, <&encoder1_rpc>; + status = "okay"; +}; + +&vpu_core2 { + reg = <0x2d0a0000 0x10000>; + memory-region = <&encoder2_boot>, <&encoder2_rpc>; + status = "okay"; +}; + +&lsio_gpio0 { + status = "disabled"; +}; + +&lsio_gpio1 { + status = "okay"; +}; + +&lsio_gpio2 { + status = "okay"; +}; + +&lsio_gpio3 { + status = "disabled"; +}; + +&lsio_gpio4 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&lsio_gpio6 { + status = "disabled"; +}; + +&lsio_gpio7 { + status = "disabled"; +}; + +&lsio_mu8 { + status = "okay"; +}; + +&rtc { + read-only; +}; + +&crypto { + /delete-property/ interrupts; + power-domains = <&pd IMX_SC_R_CAAM_JR2>; + /delete-node/ sec_jr3; +}; + +/delete-node/ &asrc1; +/delete-node/ &ddr_pmu0; +/delete-node/ &ddr_pmu1; +/delete-node/ &dpu2; +/delete-node/ &dsp; +/delete-node/ &esai1; +/delete-node/ &fec2; +/delete-node/ &gpio0_mipi_csi0; +/delete-node/ &gpio0_mipi_csi1; +/delete-node/ &i2c_mipi_csi0; +/delete-node/ &i2c_mipi_csi1; +/delete-node/ &i2c1_lvds1; +/delete-node/ &irqsteer_csi0; +/delete-node/ &irqsteer_csi1; +/delete-node/ &isi_0; +/delete-node/ &isi_1; +/delete-node/ &isi_2; +/delete-node/ &isi_3; +/delete-node/ &isi_4; +/delete-node/ &isi_5; +/delete-node/ &isi_6; +/delete-node/ &isi_7; +/delete-node/ &jpegdec; +/delete-node/ &jpegenc; +/delete-node/ &ldb2; +/delete-node/ &ldb2_phy; +/delete-node/ &lpuart1; +/delete-node/ &lpuart2; +/delete-node/ &lvds1_region; +/delete-node/ &mipi_csi_0; +/delete-node/ &mipi_csi_1; +/delete-node/ &mqs; +/delete-node/ &sai0; +/delete-node/ &sai2; +/delete-node/ &sai3; +/delete-node/ &spdif0; +/delete-node/ &usbotg1; +/delete-node/ &usbphy1; +/delete-node/ &usdhc1; +/delete-node/ &usbmisc1; +/delete-node/ &mipi1_dsi_host; +/delete-node/ &i2c0_mipi1; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a72.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a72.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a72.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-cockpit-a72.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,1893 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +/dts-v1/; + +#include +#include "imx8qm-cockpit-ca72.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + stdout-path = &lpuart2; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + brcmfmac: brcmfmac { + compatible = "cypress,brcmfmac"; + pinctrl-names = "init", "idle", "default"; + pinctrl-0 = <&pinctrl_wifi_init>; + pinctrl-1 = <&pinctrl_wifi_init>; + pinctrl-2 = <&pinctrl_wifi>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + status = "disabled"; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds1 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_modem_reset>; + pinctrl-1 = <&pinctrl_modem_reset_sleep>; + reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder_boot@c4000000 { + no-map; + reg = <0 0xc4000000 0 0x2000000>; + }; + encoder1_boot: encoder1_boot@c6000000 { + no-map; + reg = <0 0xc6000000 0 0x200000>; + }; + encoder2_boot: encoder2_boot@c6200000 { + no-map; + reg = <0 0xc6200000 0 0x200000>; + }; + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + rpmsg_reserved: rpmsg@90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x100000>; + }; + shmem_dma_reserved:shmem_dma@92000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x92000000 0 0x400000>; + }; + decoder_rpc: decoder_rpc@d2000000 { + no-map; + reg = <0 0xd2000000 0 0x100000>; + }; + dsp_reserved: dsp@92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder1_rpc: encoder1_rpc@d4400000 { + no-map; + reg = <0 0xd4400000 0 0x700000>; + }; + encoder2_rpc: encoder2_rpc@d4b00000 { + no-map; + reg = <0 0xd4b00000 0 0x700000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x1e000000>; + alloc-ranges = <0 0xe2000000 0 0x1e000000>; + linux,cma-default; + }; + + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&lsio_gpio1 13 0>; + enable-active-high; + status = "disabled"; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pciea: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea_reg>; + regulator-name = "mpcie_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio4 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <4800>; + enable-active-high; + status = "disabled"; + }; + + reg_can01_en: regulator-can01-gen { + compatible = "regulator-fixed"; + regulator-name = "can01-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_can2_en: regulator-can2-gen { + compatible = "regulator-fixed"; + regulator-name = "can2-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_can01_stby: regulator-can01-stby { + compatible = "regulator-fixed"; + regulator-name = "can01-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can01_en>; + status = "disabled"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can2_en>; + status = "disabled"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8960>; + hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cm41_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm41_i2c>; + status = "disabled"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + power-domains = <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + power-domain-names = "pd_mclk_out_0", + "pd_audio_clk_0", + "pd_audio_clk_1", + "pd_audio_clk_0", + "pd_audio_clk_1"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "disabled"; + }; +}; + +&cm41_intmux { + status = "disabled"; +}; + +&dc0_pc { + status = "disabled"; +}; + +&dc0_prg1 { + status = "disabled"; +}; + +&dc0_prg2 { + status = "disabled"; + +}; + +&dc0_prg3 { + status = "disabled"; +}; + +&dc0_prg4 { + status = "disabled"; +}; + +&dc0_prg5 { + status = "disabled"; +}; + +&dc0_prg6 { + status = "disabled"; +}; + +&dc0_prg7 { + status = "disabled"; +}; + +&dc0_prg8 { + status = "disabled"; +}; + +&dc0_prg9 { + status = "disabled"; +}; + +&dc0_dpr1_channel1 { + status = "disabled"; +}; + +&dc0_dpr1_channel2 { + status = "disabled"; +}; + +&dc0_dpr1_channel3 { + status = "disabled"; +}; + +&dc0_dpr2_channel1 { + status = "disabled"; +}; + +&dc0_dpr2_channel2 { + status = "disabled"; +}; + +&dc0_dpr2_channel3 { + status = "disabled"; +}; + +&dpu1 { + status = "disabled"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp-v1"; + status = "disabled"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; + /delete-property/ dmas; +}; + +&asrc1 { + /delete-property/ dmas; +}; + +&amix { + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "okay"; + /delete-property/ dmas; +}; + +&esai1 { + /delete-property/ dmas; +}; + +&sai0 { + /delete-property/ dmas; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai2 { + /delete-property/ dmas; +}; + +&sai3 { + /delete-property/ dmas; +}; + +&sai4 { + /delete-property/ dmas; +}; + +&sai5 { + /delete-property/ dmas; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; + /delete-property/ dmas; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; + /delete-property/ dmas; +}; + +&spdif0 { + /delete-property/ dmas; +}; + +&spdif1 { + /delete-property/ dmas; +}; + + + +&pwm_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds0>; + status = "disabled"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "disabled"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "disabled"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "disabled"; +}; + +&mipi0_dsi_host { + status = "disabled"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&i2c0_mipi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; +// interrupt-parent = <&lsio_gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&dc1_pc { + status = "okay"; +}; + +&dc1_prg1 { + status = "okay"; +}; + +&dc1_prg2 { + status = "okay"; + +}; + +&dc1_prg3 { + status = "okay"; +}; + +&dc1_prg4 { + status = "okay"; +}; + +&dc1_prg5 { + status = "okay"; +}; + +&dc1_prg6 { + status = "okay"; +}; + +&dc1_prg7 { + status = "okay"; +}; + +&dc1_prg8 { + status = "okay"; +}; + +&dc1_prg9 { + status = "okay"; +}; + +&dc1_dpr1_channel1 { + status = "okay"; +}; + +&dc1_dpr1_channel2 { + status = "okay"; +}; + +&dc1_dpr1_channel3 { + status = "okay"; +}; + +&dc1_dpr2_channel1 { + status = "okay"; +}; + +&dc1_dpr2_channel2 { + status = "okay"; +}; + +&dc1_dpr2_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&pwm_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds1>; + status = "okay"; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; + cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; + status = "disabled"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + +&emvsim0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim0>; + status = "disabled"; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "disabled"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "disabled"; +}; + +&lpuart2 { /* Dbg console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + /delete-property/ dmas; + status = "okay"; +}; + +&lpuart3 { /* MKbus */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can01_stby>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can01_stby>; + status = "disabled"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can2_stby>; + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + fsl,rgmii_rxc_dly; + /delete-property/ iommus; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + qca,disable-smarteee; + vddio-supply = <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + qca,disable-smarteee; + vddio-supply = <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; + /delete-property/ iommus; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "disabled"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&pciea{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + epdev_on-supply = <&epdev_on>; + vpcie-supply = <®_pciea>; + reserved-region = <&rpmsg_reserved>; + status = "disabled"; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&lsio_mu5 { + status = "disabled"; +}; + +&lsio_mu6 { + status = "disabled"; +}; + +&lsio_mu8b { + status = "okay"; +}; + +&rpmsg0{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + status = "disabled"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90100000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + status = "disabled"; +}; + +&imx_shmem_net { + memory-region = <&shmem_dma_reserved>; + rxfirst; + status = "okay"; +}; + +&sata { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 30 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + /delete-property/ iommus; + status = "disabled"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usb3_phy { + status = "disabled"; +}; + +&usbotg3 { + status = "disabled"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + /delete-property/ iommus; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + /delete-property/ iommus; + status = "disabled"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "disabled"; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "isil,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <11 2>; + }; + + fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas21002c@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + interrupt-open-drain; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + ptn5110: tcpc@51 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_2 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_6 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_7 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&irqsteer_csi0 { + status = "disabled"; +}; + +&irqsteer_csi1 { + status = "disabled"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "disabled"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "disabled"; + + /* Camera 1 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "disabled"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "disabled"; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c + IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c + >; + }; + + pinctrl_cm41_i2c: cm41i2cgrp { + fsl,pins = < + IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c + IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c + IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c + >; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c + IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c + IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c + IMX8QM_SPI2_CS0_DMA_SPI2_CS0 0x0600004c + >; + }; + + pinctrl_lpspi2_cs: lpspi2cs { + fsl,pins = < + IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 + >; + }; + + pinctrl_sim0: sim0grp { + fsl,pins = < + IMX8QM_SIM0_CLK_DMA_SIM0_CLK 0xc0000021 + IMX8QM_SIM0_IO_DMA_SIM0_IO 0xc2000021 + IMX8QM_SIM0_PD_DMA_SIM0_PD 0xc0000021 + IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN 0xc0000021 + IMX8QM_SIM0_RST_DMA_SIM0_RST 0xc0000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 + IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_pwm_lvds0: pwmlvds0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_pwm_lvds1: pwmlvds1grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_modem_reset: modemresetgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 + >; + }; + + pinctrl_modem_reset_sleep: modemreset_sleepgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_pciea_reg: pcieareggrp { + fsl,pins = < + IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 + IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 + IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 + IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_mipi_csi0: mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_mipi_csi1: mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_wifi: wifigrp{ + fsl,pins = < + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_wifi_init: wifi_initgrp{ + fsl,pins = < + /* reserve pin init/idle_state to support multiple wlan cards */ + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 + >; + }; + +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&gpu_3d0{ + status = "disabled"; +}; + +&gpu_3d1{ + status = "okay"; +}; + +&imx8_gpu_ss { + cores = <&gpu_3d1>; + status = "okay"; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu2_disp0>, <&dpu2_disp1>; + }; +}; + +&mu_m0{ + interrupts = ; +}; + +&mu1_m0{ + interrupts = ; +}; + +&mu2_m0{ + interrupts = ; + status = "okay"; +}; + +&vpu { + compatible = "nxp,imx8qm-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d080000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d090000 0x10000>; + memory-region = <&encoder1_boot>, <&encoder1_rpc>; + status = "okay"; +}; + +&vpu_core2 { + reg = <0x2d0a0000 0x10000>; + memory-region = <&encoder2_boot>, <&encoder2_rpc>; + status = "okay"; +}; + +&lsio_gpio0 { + status = "okay"; +}; + +&lsio_gpio1 { + status = "disabled"; +}; + +&lsio_gpio2 { + status = "disabled"; +}; + +&lsio_gpio3 { + status = "okay"; +}; + +&lsio_gpio4 { + status = "disabled"; +}; + +&lsio_gpio5 { + status = "disabled"; +}; + +&lsio_gpio6 { + status = "okay"; +}; + +&lsio_gpio7 { + status = "okay"; +}; + +&crypto { + power-domains = <&pd IMX_SC_R_CAAM_JR3>; +}; + +&sec_jr2 { + status = "disabled"; +}; + +&edma0 { + reg = <0x591f0000 0x10000>, /* mp */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>; /* sai1 tx */ + dma-channels = <2>; + interrupts = , /* sai1 */ + ; + interrupt-names = "edma2-chan14-rx", "edma2-chan15-tx"; /* sai1 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>; + power-domain-names = "edma2-chan14", "edma2-chan15"; + status = "okay"; +}; + +&edma2 { + reg = <0x5a1f0000 0x10000>, /* mp */ + <0x5a300000 0x10000>, /* channel16 UART2 rx */ + <0x5a310000 0x10000>; /* channel17 UART2 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan16-rx", "edma0-chan17-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>; + power-domain-names = "edma0-chan16", "edma0-chan17"; + status = "okay"; +}; + +&crypto { + /delete-property/ interrupts; + power-domains = <&pd IMX_SC_R_CAAM_JR3>; + /delete-node/ sec_jr2; +}; + +/delete-node/ &edma1; + +/delete-node/ &gpu_3d0; + +/delete-node/ &ddr_pmu0; +/delete-node/ &ddr_pmu1; +/delete-node/ &dpu1; +/delete-node/ &hdmi; +/delete-node/ &dsp; +/delete-node/ &i2c1_lvds0; +/delete-node/ &ldb1; +/delete-node/ &ldb1_phy; +/delete-node/ &lpuart0; +/delete-node/ &lpuart1; +/delete-node/ &lpuart3; +/delete-node/ &lvds0_region; +/delete-node/ &mipi0_dsi_host; +/delete-node/ &i2c0_mipi0; +/delete-node/ &mqs; +/delete-node/ &usdhc2; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,792 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm-mek.dts" +#include "imx8qm-xen.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + + stdout-path = &lpuart0; + + /* Could be updated by U-Boot */ + module@0 { + bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + }; + + domu { + /* + * There are 5 MUs, 0A is used by Dom0, 1A is used + * by ATF, so for DomU, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + compatible = "xen,domu"; + /* + * The name entry in VM configuration file + * needs to be same as here. + */ + domain_name = "DomU"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + IMX_SC_R_MU_2A + >; + rsrcs = < + IMX_SC_R_MU_2A + IMX_SC_R_GPU_0_PID0 + IMX_SC_R_GPU_0_PID1 + IMX_SC_R_GPU_0_PID2 + IMX_SC_R_GPU_0_PID3 + IMX_SC_R_LVDS_0 + IMX_SC_R_LVDS_0_I2C_0 + IMX_SC_R_LVDS_0_PWM_0 + IMX_SC_R_DC_0 + IMX_SC_R_DC_0_BLIT0 + IMX_SC_R_DC_0_BLIT1 + IMX_SC_R_DC_0_BLIT2 + IMX_SC_R_DC_0_BLIT_OUT + IMX_SC_R_DC_0_WARP + IMX_SC_R_DC_0_VIDEO0 + IMX_SC_R_DC_0_VIDEO1 + IMX_SC_R_DC_0_FRAC0 + IMX_SC_R_DC_0_PLL_0 + IMX_SC_R_DC_0_PLL_1 + IMX_SC_R_SDHC_0 + /*vpu*/ + IMX_SC_R_VPU_PID0 + IMX_SC_R_VPU_PID1 + IMX_SC_R_VPU_PID2 + IMX_SC_R_VPU_PID3 + IMX_SC_R_VPU_PID4 + IMX_SC_R_VPU_PID5 + IMX_SC_R_VPU_PID6 + IMX_SC_R_VPU_PID7 + IMX_SC_R_VPU + IMX_SC_R_VPU_DEC_0 + IMX_SC_R_VPU_ENC_0 + IMX_SC_R_VPU_ENC_1 + IMX_SC_R_VPU_TS_0 + IMX_SC_R_VPU_MU_0 + IMX_SC_R_VPU_MU_1 + IMX_SC_R_VPU_MU_2 + IMX_SC_R_VPU_MU_3 + IMX_SC_R_MU_13A + IMX_SC_R_MU_13B + IMX_SC_R_DSP + IMX_SC_R_DSP_RAM + /* usbotg1 */ + IMX_SC_R_USB_0 + IMX_SC_R_USB_0_PHY + /* usbotg3 */ + IMX_SC_R_USB_2 + IMX_SC_R_USB_2_PHY + + /* ASRC0 */ + IMX_SC_R_DMA_2_CH0 + IMX_SC_R_DMA_2_CH1 + IMX_SC_R_DMA_2_CH2 + IMX_SC_R_DMA_2_CH3 + IMX_SC_R_DMA_2_CH4 + IMX_SC_R_DMA_2_CH5 + IMX_SC_R_DMA_2_CH6 + IMX_SC_R_DMA_2_CH7 + IMX_SC_R_DMA_2_CH8 + IMX_SC_R_DMA_2_CH9 + IMX_SC_R_DMA_2_CH10 + IMX_SC_R_DMA_2_CH11 + IMX_SC_R_DMA_2_CH12 + IMX_SC_R_DMA_2_CH13 + IMX_SC_R_DMA_2_CH14 + IMX_SC_R_DMA_2_CH15 + IMX_SC_R_DMA_2_CH16 + IMX_SC_R_DMA_2_CH17 + IMX_SC_R_DMA_2_CH18 + IMX_SC_R_DMA_2_CH19 + IMX_SC_R_DMA_2_CH20 + IMX_SC_R_AUDIO_CLK_0 + IMX_SC_R_AUDIO_CLK_1 + IMX_SC_R_MCLK_OUT_0 + IMX_SC_R_MCLK_OUT_1 + IMX_SC_R_AUDIO_PLL_0 + IMX_SC_R_AUDIO_PLL_1 + IMX_SC_R_ASRC_0 + IMX_SC_R_ASRC_1 + IMX_SC_R_ESAI_0 + IMX_SC_R_ESAI_1 + IMX_SC_R_SAI_0 + IMX_SC_R_SAI_1 + IMX_SC_R_SAI_2 + IMX_SC_R_SAI_3 + IMX_SC_R_SAI_4 + IMX_SC_R_SAI_5 + IMX_SC_R_SAI_6 + IMX_SC_R_SAI_7 + IMX_SC_R_SPDIF_0 + IMX_SC_R_SPDIF_1 + IMX_SC_R_MQS_0 + IMX_SC_R_DMA_3_CH0 + IMX_SC_R_DMA_3_CH1 + IMX_SC_R_DMA_3_CH2 + IMX_SC_R_DMA_3_CH3 + IMX_SC_R_DMA_3_CH4 + IMX_SC_R_DMA_3_CH5 + IMX_SC_R_DMA_3_CH6 + IMX_SC_R_DMA_3_CH7 + IMX_SC_R_DMA_3_CH8 + IMX_SC_R_DMA_3_CH9 + IMX_SC_R_DMA_3_CH10 + + IMX_SC_R_SATA_0 + IMX_SC_R_PCIE_A + IMX_SC_R_PCIE_B + IMX_SC_R_SERDES_0 + IMX_SC_R_SERDES_1 + IMX_SC_R_HSIO_GPIO + + IMX_SC_R_DMA_0_CH14 + IMX_SC_R_DMA_0_CH15 + IMX_SC_R_UART_1 + + IMX_SC_R_MIPI_0 + IMX_SC_R_MIPI_0_I2C_0 + IMX_SC_R_MIPI_0_I2C_1 + IMX_SC_R_MIPI_1 + IMX_SC_R_MIPI_1_I2C_0 + IMX_SC_R_MIPI_1_I2C_1 + + IMX_SC_R_HDMI_PLL_0 + IMX_SC_R_HDMI_PLL_1 + IMX_SC_R_HDMI + IMX_SC_R_HDMI_I2C_0 + IMX_SC_R_HDMI_I2S + + IMX_SC_R_CSI_0 + IMX_SC_R_CSI_0_I2C_0 + IMX_SC_R_CSI_1 + IMX_SC_R_CSI_1_I2C_0 + IMX_SC_R_ISI_CH0 + IMX_SC_R_ISI_CH1 + IMX_SC_R_ISI_CH2 + IMX_SC_R_ISI_CH3 + IMX_SC_R_ISI_CH4 + IMX_SC_R_ISI_CH5 + IMX_SC_R_ISI_CH6 + IMX_SC_R_ISI_CH7 + IMX_SC_R_MJPEG_DEC_MP + IMX_SC_R_MJPEG_DEC_S0 + IMX_SC_R_MJPEG_DEC_S1 + IMX_SC_R_MJPEG_DEC_S2 + IMX_SC_R_MJPEG_DEC_S3 + IMX_SC_R_MJPEG_ENC_MP + IMX_SC_R_MJPEG_ENC_S0 + IMX_SC_R_MJPEG_ENC_S1 + IMX_SC_R_MJPEG_ENC_S2 + IMX_SC_R_MJPEG_ENC_S3 + >; + pads = < + /* i2c1_lvds1 */ + IMX8QM_LVDS0_I2C1_SCL + IMX8QM_LVDS0_I2C1_SDA + /* emmc */ + IMX8QM_EMMC0_CLK + IMX8QM_EMMC0_CMD + IMX8QM_EMMC0_DATA0 + IMX8QM_EMMC0_DATA1 + IMX8QM_EMMC0_DATA2 + IMX8QM_EMMC0_DATA3 + IMX8QM_EMMC0_DATA4 + IMX8QM_EMMC0_DATA5 + IMX8QM_EMMC0_DATA6 + IMX8QM_EMMC0_DATA7 + IMX8QM_EMMC0_STROBE + IMX8QM_EMMC0_RESET_B + + /* lvds pwm */ + IMX8QM_LVDS0_GPIO00 + + /* usbotg1/3 */ + IMX8QM_USB_SS3_TC0 + IMX8QM_QSPI1A_SS0_B + IMX8QM_USB_SS3_TC3 + IMX8QM_QSPI1A_DATA0 + + /* ESAI0 */ + IMX8QM_ESAI0_FSR + IMX8QM_ESAI0_FST + IMX8QM_ESAI0_SCKR + IMX8QM_ESAI0_SCKT + IMX8QM_ESAI0_TX0 + IMX8QM_ESAI0_TX1 + IMX8QM_ESAI0_TX2_RX3 + IMX8QM_ESAI0_TX3_RX2 + IMX8QM_ESAI0_TX4_RX1 + IMX8QM_ESAI0_TX5_RX0 + /* SAI1 */ + IMX8QM_SAI1_RXD + IMX8QM_SAI1_RXC + IMX8QM_SAI1_RXFS + IMX8QM_SAI1_TXD + IMX8QM_SAI1_TXC + + IMX8QM_PCIE_CTRL0_CLKREQ_B + IMX8QM_PCIE_CTRL0_WAKE_B + IMX8QM_PCIE_CTRL0_PERST_B + IMX8QM_LVDS1_I2C0_SDA + IMX8QM_USDHC2_RESET_B + + IMX8QM_QSPI1A_DQS + IMX8QM_UART1_RX + IMX8QM_UART1_TX + IMX8QM_UART1_CTS_B + IMX8QM_UART1_RTS_B + + IMX8QM_MIPI_CSI0_I2C0_SCL + IMX8QM_MIPI_CSI0_I2C0_SDA + IMX8QM_MIPI_CSI1_I2C0_SCL + IMX8QM_MIPI_CSI1_I2C0_SDA + IMX8QM_MIPI_CSI1_GPIO0_00 + + IMX8QM_MIPI_CSI0_GPIO0_00 + IMX8QM_MIPI_CSI0_GPIO0_01 + IMX8QM_MIPI_CSI0_MCLK_OUT + + IMX8QM_USDHC2_WP + + IMX8QM_MIPI_DSI0_I2C0_SCL + IMX8QM_MIPI_DSI0_I2C0_SDA + IMX8QM_MIPI_DSI0_GPIO0_01 + + IMX8QM_MIPI_DSI1_I2C0_SCL + IMX8QM_MIPI_DSI1_I2C0_SDA + IMX8QM_MIPI_DSI1_GPIO0_01 + + IMX8QM_SCU_GPIO0_07 + + IMX8QM_SPI0_CS1 + IMX8QM_SPI2_CS1 + IMX8QM_SAI1_RXFS + IMX8QM_SAI1_RXC + >; + + gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 19 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 27 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 28 GPIO_ACTIVE_LOW>, + <&lsio_gpio1 30 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 1 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 3 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 6 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 9 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 22 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 25 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 26 GPIO_ACTIVE_HIGH>, + <&lsio_gpio4 27 GPIO_ACTIVE_LOW>, + <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + }; + }; + + /* Interrupt 33 is not used, use it virtual PL031 */ + rtc0: rtc@23000000 { + interrupts = ; + xen,passthrough; + }; + + gpio4_dummy: gpio4_dummy@0{ + /* Passthrough gpio4 interrupt to DomU */ + interrupts = ; + xen,passthrough; + }; + + gpio1_dummy: gpio1_dummy@0{ + /* Passthrough gpio1 interrupt to DomU */ + interrupts = ; + xen,passthrough; + }; + + reserved-device-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot@84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + xen,passthrough; + }; + encoder1_boot@86000000 { + no-map; + reg = <0 0x86000000 0 0x200000>; + xen,passthrough; + }; + encoder2_boot@86200000 { + no-map; + reg = <0 0x86200000 0 0x200000>; + xen,passthrough; + }; + m4@88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + xen,passthrough; + }; + decoder_rpc@92000000 { + no-map; + reg = <0 0x92000000 0 0x100000>; + xen,passthrough; + }; + dsp@92200000 { + no-map; + reg = <0 0x92200000 0 0x2000000>; + xen,passthrough; + }; + encoder1_rpc@94200000 { + no-map; + reg = <0 0x94200000 0 0x700000>; + xen,passthrough; + }; + encoder2_rpc@94900000 { + no-map; + reg = <0 0x94900000 0 0x700000>; + xen,passthrough; + }; + ts_boot@95000000 { + no-map; + reg = <0 0x95000000 0 0x400000>; + xen,passthrough; + }; + }; +}; + +&{/reserved-memory} { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0xc0000000 0 0x58000000>; + linux,cma-default; + }; +}; + +&smmu { + mmu-masters = <&dpu1 0x13>, <&gpu_3d0 0x15>, <&usdhc1 0x12>, <&edma0 0x14>, + <&vpu_core0 0x7>, <&usbotg1 0x11>, <&usbotg3 0x4>, + <&pciea 0x8>, <&edma214 0x10>, <&isi_0 0x5>; +}; + +&edma0 { + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; +}; + +&gpu_3d0{ + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; +}; + +&gpu_3d1{ + status = "okay"; +}; + +&imx8_gpu_ss { + cores = <&gpu_3d1>; + reg = <0xa8000000 0x58000000>, <0x0 0x10000000>; + status = "okay"; +}; + +&lsio_mu1 { + /* not map for dom0, dom0 will mmio trap to xen */ + xen,no-map; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu2_disp0>, <&dpu2_disp1>; + }; +}; + +&dc0_irqsteer { + reg = <0x56000000 0x20000>; + xen,passthrough; +}; + +&dc0_pc { + xen,passthrough; +}; + +&dc0_prg1 { + xen,passthrough; +}; + +&dc0_prg2 { + xen,passthrough; +}; + +&dc0_prg3 { + xen,passthrough; +}; + +&dc0_prg4 { + xen,passthrough; +}; + +&dc0_prg5 { + xen,passthrough; +}; + +&dc0_prg6 { + xen,passthrough; +}; + +&dc0_prg7 { + xen,passthrough; +}; + +&dc0_prg8 { + xen,passthrough; +}; + +&dc0_prg9 { + xen,passthrough; +}; + +&dc0_dpr1_channel1 { + xen,passthrough; +}; + +&dc0_dpr1_channel2 { + xen,passthrough; +}; + +&dc0_dpr1_channel3 { + xen,passthrough; +}; + +&dc0_dpr2_channel1 { + xen,passthrough; +}; + +&dc0_dpr2_channel2 { + xen,passthrough; +}; + +&dc0_dpr2_channel3 { + xen,passthrough; +}; + +&dpu1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&irqsteer_lvds0 { + reg = <0x56240000 0x10000>; + xen,passthrough; +}; + +&lvds0_region { + xen,passthrough; +}; + +&i2c1_lvds0 { + xen,passthrough; +}; + +&ldb1_phy { + xen,passthrough; +}; + +&ldb1 { + xen,passthrough; +}; + +&usdhc1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&sdhc0_lpcg { + xen,passthrough; +}; + +&lsio_mu2 { + xen,passthrough; +}; + +&lsio_gpio1 { + /* + * Use GPT1 interrupt for hack + * This could be removed when interrupt sharing be supported. + */ + interrupts = ; + xen,domu-irq; + xen,shared; +}; + +/* +&gpt0 { + /delete-property/ interrupts; + status = "disabled"; +}; +*/ + +&lsio_gpio4 { + /* + * Use GPT0 interrupt for hack + * This could be removed when interrupt sharing be supported. + */ + interrupts = ; + xen,domu-irq; + xen,shared; +}; + +&gpio0_mipi_csi0 { + xen,passthrough; +}; + +&gpio0_mipi_csi1 { + xen,passthrough; +}; + +/* vpu_subsys */ +&vpu_lpcg { + xen,passthrough; +}; + +&vpu { + xen,passthrough; +}; + +&vpu_core0 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + , + ; +}; + +&vpu_core1 { + xen,passthrough; +}; + +&vpu_core2 { + xen,passthrough; +}; + +/* +&vpu_ts { + xen,passthrough; +}; +*/ + +&dsp { + xen,passthrough; +}; + +&lsio_mu13 { + xen,passthrough; +}; + +&mu_m0 { + xen,passthrough; +}; + +&mu1_m0 { + xen,passthrough; +}; + +&mu2_m0 { + xen,passthrough; +}; + +/* +&mu3_m0 { + xen,passthrough; +}; +*/ + +&usbotg1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbmisc1 { + xen,passthrough; +}; + +&usbphy1 { + xen,passthrough; +}; + +&usb2_lpcg { + xen,passthrough; +}; + +&usbotg3 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +/* +&usb3phynop1 { + status = "disabled"; +}; +*/ + +&usb3_lpcg { + xen,passthrough; +}; + +&ptn5110 { + status = "disabled"; +}; + +&{/cbtl04gp} { + status = "disabled"; +}; + +&audio_subsys { + reg = <0 0x59000000 0 0x1000000>; + xen,passthrough; +}; + +/* Passthrough baseboard audio to DomU */ +&cs42888 { + xen,passthrough; +}; + +®_audio { + xen,passthrough; +}; + +&{/sound-cs42888} { + xen,passthrough; +}; + +&esai0 { + xen,passthrough; +}; + +&wm8960 { + xen,passthrough; +}; + +&hsio_subsys { + xen,passthrough; +}; + +&pciea { + #stream-id-cells = <1>; + iommus = <&smmu>; + xen,passthrough; + fsl,sc_rsrc_id = ; +}; + +&pcieb { + xen,passthrough; +}; + +&lpuart1 { + xen,passthrough; +}; + +&modem_reset { + status = "disabled"; +}; + +&edma214 { + xen,passthrough; + #stream-id-cells = <1>; +}; + +&hdmi_subsys { + xen,passthrough; + reg = <0 0x56260000 0 0x10000>; +}; + +&img_subsys { + xen,passthrough; + reg = <0 0x58000000 0 0x1000000>; +}; + +&mipi0_subsys { + xen,passthrough; + reg = <0 0x56220000 0 0x10000>; +}; + +&mipi1_subsys { + xen,passthrough; + reg = <0 0x57220000 0 0x10000>; +}; + +&isi_0 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&scu_key { + status = "disabled"; +}; + +&pwm_lvds0 { + status = "disabled"; +}; + +&uart0_lpcg { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,1463 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * At current stage, M41 is not ready to communicate with XEN, so we + * we need a way to tell XEN uboot is running or linux is running. + * XEN will check the contents of this area. + * So reserve a page at the beginning of GUEST_RAM0_BASE to avoid Linux + * touch this area. + */ +/memreserve/ 0x80000000 0x1000; + +/ { + model = "Freescale i.MX8QM DOMU"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm", "xen,xenvm-4.10", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + dpu0 = &dpu1; + ldb0 = &ldb1; + serial1 = &lpuart1; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + mu1 = &lsio_mu1; + mu2 = &lsio_mu2; + dphy0 = &mipi0_dphy; + dphy1 = &mipi1_dphy; + mipi_dsi0 = &mipi0_dsi_host; + mipi_dsi1 = &mipi1_dsi_host; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "hvc"; + }; + + memory@80000000 { + device_type = "memory"; + /* Will be updated by U-Boot or XEN TOOL */ + reg = <0x00000000 0x80000000 0 0x80000000>; + }; + + /* + * The reserved memory will be used when using U-Boot loading android + * image. For booting kernel using xl tool, pass args: + * cma=960M@2400M-3584M + */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + passthrough; + + decoder_boot: decoder_boot@84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x1000000>; + no-map; + }; + dsp_reserved_heap: dsp_reserved_heap { + reg = <0 0x93400000 0 0xef0000>; + no-map; + }; + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + encoder1_boot: encoder1_boot@86000000 { + no-map; + reg = <0 0x86000000 0 0x200000>; + }; + encoder2_boot: encoder2_boot@86200000 { + no-map; + reg = <0 0x86200000 0 0x200000>; + }; + decoder_rpc: decoder_rpc@92000000 { + no-map; + reg = <0 0x92000000 0 0x100000>; + }; + encoder1_rpc: encoder1_rpc@94200000 { + no-map; + reg = <0 0x94200000 0 0x700000>; + }; + encoder2_rpc: encoder2_rpc@94900000 { + no-map; + reg = <0 0x94900000 0 0x700000>; + }; + ts_boot: ts_boot@95000000 { + no-map; + reg = <0 0x95000000 0 0x400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0xc0000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + + gic: interrupt-controller@3001000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0x0>; + interrupt-controller; + redistributor-stride = <0x20000>; + #redistributor-regions = <0x1>; + reg = <0x0 0x3001000 0 0x10000>, /* GIC Dist */ + <0x0 0x3020000 0 0x1000000>; /* GICR */ + interrupts = ; + interrupt-parent = <&gic>; + linux,phandle = <0xfde8>; + phandle = <0xfde8>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + ; + interrupt-parent = <&gic>; + clock-frequency = <8000000>; + }; + + hypervisor { + compatible = "xen,xen-4.11", "xen,xen"; + reg = <0x0 0x38000000 0x0 0x1000000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + clk0: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + rtc0: rtc@23000000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0x23000000 0x0 0x1000>; + interrupts = ; + clocks = <&clk0>; + clock-names = "apb_pclk"; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_modem_reset>; + pinctrl-1 = <&pinctrl_modem_reset_sleep>; + reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + xen,passthrough; + }; + + passthrough { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + system-controller { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: power-controller { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; + #clock-cells = <2>; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + + }; + + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-gpu1.dtsi" + #include "imx8-ss-vpu.dtsi" + + brcmfmac: brcmfmac { + compatible = "cypress,brcmfmac"; + pinctrl-names = "init", "idle", "default"; + pinctrl-0 = <&pinctrl_wifi_init>; + pinctrl-1 = <&pinctrl_wifi_init>; + pinctrl-2 = <&pinctrl_wifi>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + }; + + #include "imx8-ss-dc0.dtsi" + #include "imx8-ss-dc1.dtsi" + #include "imx8-ss-audio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-dma.dtsi" + #include "imx8-ss-img.dtsi" + + scu_key: keys { + compatible = "fsl,imx8qm-sc-key", "fsl,imx-sc-key"; + linux,keycode = ; + xen,passthrough; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + xen,passthrough; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&lsio_gpio1 13 0>; + enable-active-high; + xen,passthrough; + }; + + reg_pciea: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea_reg>; + regulator-name = "mpcie_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio4 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + audio-asrc = <&asrc0>; + status = "okay"; + xen,passthrough; + }; + + xen_i2c0: xen_i2c@0 { + compatible = "xen,i2c"; + be-adapter = "5a800000.i2c"; + status = "okay"; + xen,passthrough; + }; + + xen_i2c1: xen_i2c@1 { + compatible = "xen,i2c"; + be-adapter = "3b230000.i2c"; + xen,passthrough; + status = "okay"; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + orientation-switch; + xen,passthrough; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + vpu_subsys_dsp: bus@55000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x55000000 0x0 0x55000000 0x1000000>; + xen,passthrough; + + dsp: dsp@556e8000 { + compatible = "fsl,imx8qm-hifi4"; + reg = <0x556e8000 0x88000>; + clocks = <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "core", "ipg", "ocram"; + firmware-name = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>; + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + status = "disabled"; + }; + }; + +}; + +#include "imx8qm-ss-conn.dtsi" +#include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-dc.dtsi" +#include "imx8qm-ss-gpu.dtsi" +#include "imx8qm-ss-lvds.dtsi" +#include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hdmi.dtsi" +#include "imx8qm-ss-audio.dtsi" +#include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hdmi.dtsi" +#include "imx8qm-ss-img.dtsi" + +/ { + display-subsystem { + xen,passthrough; + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>; + }; +}; + +&lsio_mu13 { + xen,passthrough; +}; + +&dc0_subsys { + xen,passthrough; +}; + +&dma_subsys { + xen,passthrough; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; + + + edma214: dma-controller@5a2e0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a1f0000 0x10000>, + <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ + <0x5a2f0000 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>; + power-domain-names = "edma0-chan14", "edma0-chan15"; + status = "okay"; + }; +}; + +&audio_subsys { + xen,passthrough; +}; + +&hsio_subsys { + xen,passthrough; +}; + +&lvds1_subsys { + xen,passthrough; +}; + +&hdmi_subsys { + xen,passthrough; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&pwm_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds0>; + status = "okay"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1_phy { + status="okay"; +}; + +&ldb1 { + status="okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&dc0_pc { + status="okay"; +}; + +&dc0_prg1 { + status="okay"; +}; + +&dc0_prg2 { + status="okay"; +}; + +&dc0_prg3 { + status="okay"; +}; + +&dc0_prg4 { + status="okay"; +}; + +&dc0_prg5 { + status="okay"; +}; + +&dc0_prg6 { + status="okay"; +}; + +&dc0_prg7 { + status="okay"; +}; + +&dc0_prg8 { + status="okay"; +}; + +&dc0_prg9 { + status="okay"; +}; + +&dc0_dpr1_channel1 { + status="okay"; +}; + +&dc0_dpr1_channel2 { + status="okay"; +}; + +&dc0_dpr1_channel3 { + status="okay"; +}; + +&dc0_dpr2_channel1 { + status="okay"; +}; + +&dc0_dpr2_channel2 { + status="okay"; +}; + +&dc0_dpr2_channel3 { + status="okay"; +}; + +&dpu1 { + status="okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "disabled"; +}; + +&imx8_gpu_ss { + /* xen guests have 2GB of low RAM @ 2GB */ + reg = <0x80000000 0x80000000>, <0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + cores = <&gpu_3d0>; + status = "okay"; +}; + +&iomuxc { + + pinctrl_wifi: wifigrp{ + fsl,pins = < + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_wifi_init: wifi_initgrp{ + fsl,pins = < + /* reserve pin init/idle_state to support multiple wlan cards */ + >; + }; + + pinctrl_pwm_lvds0: pwmlvds0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_pciea_reg: pcieareggrp { + fsl,pins = < + IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_modem_reset: modemresetgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 + >; + }; + + pinctrl_modem_reset_sleep: modemreset_sleepgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 + >; + }; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_mipi_csi0: mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_mipi_csi1: mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 + >; + }; +}; + +&usdhc1 { + /delete-property/ iommus; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + /delete-property/ iommus; + status = "disabled"; +}; + +&usdhc3 { + /delete-property/ iommus; + status = "disabled"; +}; + +&fec1 { + /delete-property/ iommus; + status = "disabled"; +}; + +&fec2 { + /delete-property/ iommus; + status = "disabled"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +/* +&usb3phynop1 { + status = "okay"; +}; +*/ + +&usbotg3 { + dr_mode = "otg"; + extcon = <&ptn5110>; + status = "okay"; + /delete-property/ iommus; +}; + +&xen_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "isil,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <11 2>; + }; + + fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + interrupt-open-drain; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + ptn5110: tcpc@51 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&mu_m0{ + interrupts = ; +}; + +&mu1_m0{ + interrupts = ; +}; + +&mu2_m0{ + interrupts = ; + status = "okay"; +}; + +/* +&mu3_m0{ + interrupts = ; + status = "okay"; +}; +*/ + +&vpu { + compatible = "nxp,imx8qm-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d080000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d090000 0x10000>; + memory-region = <&encoder1_boot>, <&encoder1_rpc>; + status = "okay"; +}; + +&vpu_core2 { + reg = <0x2d0a0000 0x10000>; + memory-region = <&encoder2_boot>, <&encoder2_rpc>; + status = "okay"; +}; + +/* +&vpu_ts { + compatible = "nxp,imx8qm-b0-vpu-ts"; + boot-region = <&ts_boot>; + reg-csr = <0x2d0b0000>; + status = "okay"; +}; +*/ + +&lsio_gpio4 { + /delete-property/ power-domains; +}; + +&lsio_gpio1 { + /delete-property/ power-domains; +}; + +/* Audio */ +&dsp { + compatible = "fsl,imx8qm-hifi4"; + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + /*pinctrl-0 = <&pinctrl_sai1>;*/ + status = "disabled"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&usbotg3_cdns3 { + /delete-property/ iommus; + status = "disabled"; +}; +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&xen_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "disabled"; +}; + +&sata { + /delete-property/ iommus; +}; + +&pciea{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + epdev_on-supply = <&epdev_on>; + vpcie-supply = <®_pciea>; + status = "okay"; +}; + +&pcieb{ + status = "disabled"; +}; + +&edma2 { + status = "disabled"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; + dmas = <&edma214 15 0 0>, <&edma214 14 0 1>; +}; + +&img_subsys { + xen,passthrough; +}; + +&hdmi_subsys { + xen,passthrough; +}; + +&mipi0_subsys { + xen,passthrough; +}; + +&mipi1_subsys { + xen,passthrough; +}; + +&dsi_ipg_clk { + xen,passthrough; +}; + +&mipi_pll_div2_clk { + xen,passthrough; +}; + +&i2c0_mipi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&i2c0_mipi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_2 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_6 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_7 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&irqsteer_csi1 { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 1 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67191.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek.dts" + +/delete-node/ &adv_bridge0; +/delete-node/ &adv_bridge1; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + pinctrl-names = "default"; + reset-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&mipi0_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi0_panel_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel1_in: endpoint { + remote-endpoint = <&mipi1_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi1_panel_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-dsi-rm67199.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek-dsi-rm67191.dts" + + +&mipi0_dsi_host { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&mipi1_dsi_host { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek.dts 2024-06-19 12:33:58.304192634 +0200 @@ -6,6 +6,7 @@ /dts-v1/; +#include #include "imx8qm.dtsi" / { @@ -16,25 +17,921 @@ stdout-path = &lpuart0; }; - cpus { - /delete-node/ cpu-map; - /delete-node/ cpu@100; - /delete-node/ cpu@101; - }; - memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x40000000>; }; + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm_lvds1 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_modem_reset>; + pinctrl-1 = <&pinctrl_modem_reset_sleep>; + reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpu_reserved: gpu_reserved@8800000000 { + no-map; + reg = <0x8 0x80000000 0 0x10000000>; + }; + + decoder_boot: decoder_boot@84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder1_boot: encoder1_boot@86000000 { + no-map; + reg = <0 0x86000000 0 0x200000>; + }; + encoder2_boot: encoder2_boot@86200000 { + no-map; + reg = <0 0x86200000 0 0x200000>; + }; + decoder_rpc: decoder_rpc@92000000 { + no-map; + reg = <0 0x92000000 0 0x100000>; + }; + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x1000000>; + no-map; + }; + dsp_reserved_heap: dsp_reserved_heap { + reg = <0 0x93400000 0 0xef0000>; + no-map; + }; + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + encoder1_rpc: encoder1_rpc@94400000 { + no-map; + reg = <0 0x94400000 0 0x700000>; + }; + encoder2_rpc: encoder1_rpc@94b00000 { + no-map; + reg = <0 0x94b00000 0 0x700000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0xc0000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pciea: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea_reg>; + regulator-name = "mpcie_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usbotg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&lsio_gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "SD1_SPWR"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <4800>; enable-active-high; }; + + reg_can01_en: regulator-can01-gen { + compatible = "regulator-fixed"; + regulator-name = "can01-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_en: regulator-can2-gen { + compatible = "regulator-fixed"; + regulator-name = "can2-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can01_stby: regulator-can01-stby { + compatible = "regulator-fixed"; + regulator-name = "can01-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can01_en>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can2_en>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai0>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-mek-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai0>; + audio-codec = <&cs42888>; + audio-asrc = <&asrc0>; + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx8qm-mek-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8960>; + hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; + + cm4 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + imx8qm_cm40: imx8qm_cm4@0 { + compatible = "fsl,imx8qm-cm4"; + rsc-da = <0x90000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table0>; + fsl,resource-id = ; + fsl,entry-address = <0x34fe0000>; + status = "okay"; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, + <&pd IMX_SC_R_M4_0_MU_1A>; + }; + + imx8qm_cm41: imx8x_cm4@1 { + compatible = "fsl,imx8qm-cm4"; + rsc-da = <0x90100000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu6 0 1 + &lsio_mu6 1 1 + &lsio_mu6 3 1>; + memory-region = <&vdevbuffer>, <&vdev2vring0>, <&vdev2vring1>, + <&vdev3vring0>, <&vdev3vring1>, <&rsc_table1>; + fsl,resource-id = ; + fsl,entry-address = <0x38fe0000>; + status = "okay"; + power-domains = <&pd IMX_SC_R_M4_1_PID0>, + <&pd IMX_SC_R_M4_1_MU_1A>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@90000000 { + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc_table0: rsc-table@900ff000 { + reg = <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + + vdev2vring0: vdev0vring0@90100000 { + reg = <0 0x90100000 0 0x8000>; + no-map; + }; + + vdev2vring1: vdev0vring1@90108000 { + reg = <0 0x90108000 0 0x8000>; + no-map; + }; + + vdev3vring0: vdev1vring0@90110000 { + reg = <0 0x90110000 0 0x8000>; + no-map; + }; + + vdev3vring1: vdev1vring1@90118000 { + reg = <0 0x90118000 0 0x8000>; + no-map; + }; + + rsc_table1: rsc-table@901ff000 { + reg = <0 0x901ff000 0 0x1000>; + no-map; + }; + }; + + /* + * this dummy i2c mux. + * gpio actually will not impact selection. + * at actual boards, only 1 devices connectted. + * I2C client driver will check ID when probe. + * Only matched ID's driver probe successfully. + */ + i2cvmux: i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_HIGH>; /* use an unused gpio */ + i2c-parent = <&i2c0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + }; + + i2c@0 { /* Rev D */ + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + lsm303arg@1e { + compatible = "st,lsm303agr-magn"; + reg = <0x1e>; + st,drdy-int-pin = <1>; + interrupt-parent = <&lsio_gpio4>; + interrupt-open-drain; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + +}; + +&lsio_mu5 { + status = "okay"; +}; + +&lsio_mu6 { + status = "okay"; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cm41_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm41_i2c>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; +}; + +&cm41_intmux { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; + +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-hifi4"; + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "okay"; +}; + +&sai0 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&pwm_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds0>; + status = "okay"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&i2c0_mipi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&dc1_pc { + status = "okay"; +}; + +&dc1_prg1 { + status = "okay"; +}; + +&dc1_prg2 { + status = "okay"; + +}; + +&dc1_prg3 { + status = "okay"; +}; + +&dc1_prg4 { + status = "okay"; +}; + +&dc1_prg5 { + status = "okay"; +}; + +&dc1_prg6 { + status = "okay"; +}; + +&dc1_prg7 { + status = "okay"; +}; + +&dc1_prg8 { + status = "okay"; +}; + +&dc1_prg9 { + status = "okay"; +}; + +&dc1_dpr1_channel1 { + status = "okay"; +}; + +&dc1_dpr1_channel2 { + status = "okay"; +}; + +&dc1_dpr1_channel3 { + status = "okay"; +}; + +&dc1_dpr2_channel1 { + status = "okay"; +}; + +&dc1_dpr2_channel2 { + status = "okay"; +}; + +&dc1_dpr2_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&pwm_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_lvds1>; + status = "okay"; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; + cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + +&emvsim0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim0>; + status = "okay"; }; &lpuart0 { @@ -43,12 +940,59 @@ status = "okay"; }; +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&lpuart2 { /* Dbg console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "disabled"; +}; + +&lpuart3 { /* MKbus */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii-txid"; phy-handle = <ðphy0>; fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; status = "okay"; mdio { @@ -58,18 +1002,142 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + qca,disable-smarteee; + vddio-supply = <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + qca,disable-smarteee; + vddio-supply = <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; }; }; -&usdhc1 { +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + nxp,fspi-dll-slvdly = <4>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + +&phyx2_0{ + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&phyx2_1{ + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&phyx1{ + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&pciea{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pciea>; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&lsio_gpio4>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&pcieb{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; no-sd; no-sdio; @@ -78,8 +1146,10 @@ }; &usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; vmmc-supply = <®_usdhc2_vmmc>; cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; @@ -87,9 +1157,343 @@ status = "okay"; }; +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + isl29023@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <11 2>; + }; + + fxas21002c@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + interrupt-open-drain; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + /* RevD */ + lsm303arg@19 { + compatible = "st,lsm303agr-accel"; + reg = <0x19>; + }; + + /* RevD */ + l3g4250@69 { + compatible = "st,l3g4200d-gyro"; + reg = <0x69>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + ptn5110: tcpc@51 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_2 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_6 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_7 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&irqsteer_csi1 { + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 1 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi1>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; + &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c + IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c + IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c + /* + * M.2 pin20 & pin21 need to be set to 11 for 88W9098 to select the + * default Reference Clock Frequency + */ + IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + IMX8QM_USB_SS3_TC2_LSIO_GPIO4_IO05 0x00000021 + /* sensor irq */ + IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + pinctrl_cm41_i2c: cm41i2cgrp { + fsl,pins = < + IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c + IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 @@ -107,6 +1511,111 @@ >; }; + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c + IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c + >; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040 + IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040 + IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040 + >; + }; + + pinctrl_lpspi2_cs: lpspi2cs { + fsl,pins = < + IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 + >; + }; + + pinctrl_sim0: sim0grp { + fsl,pins = < + IMX8QM_SIM0_CLK_DMA_SIM0_CLK 0xc0000021 + IMX8QM_SIM0_IO_DMA_SIM0_IO 0xc2000021 + IMX8QM_SIM0_PD_DMA_SIM0_PD 0xc0000021 + IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN 0xc0000021 + IMX8QM_SIM0_RST_DMA_SIM0_RST 0xc0000021 + >; + }; + pinctrl_lpuart0: lpuart0grp { fsl,pins = < IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 @@ -114,6 +1623,112 @@ >; }; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 + IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_pwm_lvds0: pwmlvds0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_pwm_lvds1: pwmlvds1grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_modem_reset: modemresetgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x06000021 + >; + }; + + pinctrl_modem_reset_sleep: modemreset_sleepgrp { + fsl,pins = < + IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x07800021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_pciea_reg: pcieareggrp { + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B 0x06000021 + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c + IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c + IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c + IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 + IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 + IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 + IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 @@ -130,6 +1745,14 @@ >; }; + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 @@ -141,4 +1764,146 @@ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 >; }; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_mipi_csi0: mipi_csi0 { + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_mipi_csi1: mipi_csi1 { + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 + >; + }; + +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&gpu_3d0{ + status = "okay"; +}; + +&gpu_3d1{ + status = "okay"; +}; + +&imx8_gpu_ss { + memory-region=<&gpu_reserved>; + status = "okay"; +}; + +&mu_m0{ + interrupts = ; +}; + +&mu1_m0{ + interrupts = ; +}; + +&mu2_m0{ + interrupts = ; + status = "okay"; +}; + +&vpu { + compatible = "nxp,imx8qm-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d080000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d090000 0x10000>; + memory-region = <&encoder1_boot>, <&encoder1_rpc>; + status = "okay"; +}; + +&vpu_core2 { + reg = <0x2d0a0000 0x10000>; + memory-region = <&encoder2_boot>, <&encoder2_rpc>; + status = "okay"; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-enet2-tja1100.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,16 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qm-mek.dts" +#include "imx8qm-enet2-tja1100.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-esai.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-esai.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-esai.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-esai.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qm-mek-rpmsg.dts" + +/ { + esai_client0: esai_client@0 { + compatible = "fsl,esai-client"; + fsl,client-id = <0>; + }; + + esai_client1: esai_client@1 { + compatible = "fsl,esai-client"; + fsl,client-id = <1>; + }; +}; + +&esai0 { + client-dais = <&esai_client0>, <&esai_client1>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Sandor Yu + */ + /* HDMI, LVDS1 and MIPI DSI1. LVDS0 and MIPI0 are disabled */ + +/dts-v1/; + +#include "imx8qm-mek-rpmsg.dts" + +/ { + sound-hdmi-tx { + compatible = "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai5>; + protocol = <1>; + hdmi-out; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&mipi0_dsi_host { + status = "disabled"; +}; + +&mipi0_dphy { + status = "disabled"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_lpcg_lis_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_i2s { + status = "okay"; +}; + +&hdmi_lpcg_gpio_ipg { + status = "okay"; +}; + +&hdmi_lpcg_msi_hclk { + status = "okay"; +}; + +&hdmi_lpcg_pxl { + status = "okay"; +}; + +&hdmi_lpcg_phy { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_csr { + status = "okay"; +}; + +&hdmi_lpcg_apb_mux_ctrl { + status = "okay"; +}; + +&hdmi_lpcg_apb { + status = "okay"; +}; + +&hdmi { + compatible = "cdn,imx8qm-hdmi"; + firmware-name = "hdmitxfw.bin"; + lane-mapping = <0x93>; + hdcp-config = <0x3>; + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi-rx.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi-rx.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi-rx.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi-rx.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 - 2022 NXP + * Sandor Yu + */ +/* + * HDMI RX only dts. + */ + +#include "imx8qm-mek-hdmi.dts" + +/ { + sound-hdmi-rx { + compatible = "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi-rx"; + audio-cpu = <&sai4>; + protocol = <1>; + hdmi-in; + }; +}; + +&sai4 { + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai4_lpcg { + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +/* HDMI RX */ +&isi_2 { + interface = <4 0 2>; /* + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + status = "okay"; + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + /* For HDMI RX 4K chain buf */ + interface = <4 0 2>; + status = "okay"; + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_5 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_6 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_7 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + /delete-property/virtual-channel; + status = "disabled"; +}; + +&i2c_mipi_csi0 { + status = "disabled"; +}; + +&mipi_csi_1 { + /delete-property/virtual-channel; + status = "disabled"; +}; + +&i2c_mipi_csi1 { + status = "disabled"; +}; + +&hdmi_rx_lpcg_gpio_ipg_s { + status = "okay"; +}; + +&hdmi_rx_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg_s { + status = "okay"; +}; + +&hdmi_rx_lpcg_pwm { + status = "okay"; +}; + +&hdmi_rx_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_rx_lpcg_i2c0_div { + status = "okay"; +}; + +&hdmi_rx_lpcg_i2c0_ipg { + status = "okay"; +}; + +&hdmi_rx_lpcg_i2c0_ipg_s { + status = "okay"; +}; + +&hdmi_rx_lpcg_sink_p { + status = "okay"; +}; + +&hdmi_rx_lpcg_sink_s { + status = "okay"; +}; + +&hdmi_rx_lpcg_hd_core { + status = "okay"; +}; + +&hdmi_rx_lpcg_pxl { + status = "okay"; +}; + +&hdmi_rx_lpcg_enc { + status = "okay"; +}; + +&irqsteer_hdmi_rx { + status = "okay"; +}; + +&hdmi_rx { + fsl,cec; + firmware-name = "hdmirxfw.bin"; + assigned-clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC1>, + <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC3>; + assigned-clock-parents = <&hdmi_rx_dig_pll>, + <&clk IMX_SC_R_HDMI_RX_BYPASS IMX_SC_PM_CLK_MISC2>; + assigned-clock-rates = <400000000>, <0>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi-rx-ov5640.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi-rx-ov5640.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi-rx-ov5640.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi-rx-ov5640.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 - 2022 NXP + * Oliver F. Brown + */ +/* + * HDMI RX and OV5640 on MIPI CSI 1 + */ + +#include "imx8qm-mek-hdmi.dts" + +/ { + sound-hdmi-rx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-rx"; + audio-cpu = <&sai4>; + protocol = <1>; + hdmi-in; + }; +}; + +&sai4 { + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai4_lpcg { + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "disabled"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + + +&isi_2 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; +&isi_3 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + + +&isi_4 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +/* HDMI RX */ +&isi_6 { + interface = <4 0 2>; /* + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + status = "okay"; + cap_device { + status = "okay"; + }; +}; + +&isi_7 { + /* For HDMI RX 4K chain buf */ + interface = <4 0 2>; + status = "okay"; + cap_device { + status = "okay"; + }; +}; + +&mipi_csi_0 { + /delete-property/virtual-channel; + status = "disabled"; +}; + +&i2c_mipi_csi0 { + status = "disabled"; +}; + +&mipi_csi_1 { + /delete-property/virtual-channel; + + /* Camera 1 MIPI CSI-2 (CSIS0) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov5640_mipi_1_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + }; +}; + +&i2c_mipi_csi1 { + ov5640_mipi_1: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; + +&hdmi_rx_lpcg_gpio_ipg_s { + status = "okay"; +}; + +&hdmi_rx_lpcg_pwm_ipg { + status = "okay"; +}; + +&hdmi_lpcg_pwm_ipg_s { + status = "okay"; +}; + +&hdmi_rx_lpcg_pwm { + status = "okay"; +}; + +&hdmi_rx_lpcg_i2c0 { + status = "okay"; +}; + +&hdmi_rx_lpcg_i2c0_div { + status = "okay"; +}; + +&hdmi_rx_lpcg_i2c0_ipg { + status = "okay"; +}; + +&hdmi_rx_lpcg_i2c0_ipg_s { + status = "okay"; +}; + +&hdmi_rx_lpcg_sink_p { + status = "okay"; +}; + +&hdmi_rx_lpcg_sink_s { + status = "okay"; +}; + +&hdmi_rx_lpcg_hd_core { + status = "okay"; +}; + +&hdmi_rx_lpcg_pxl { + status = "okay"; +}; + +&hdmi_rx_lpcg_enc { + status = "okay"; +}; + +&irqsteer_hdmi_rx { + status = "okay"; +}; + +&hdmi_rx { + fsl,cec; + firmware-name = "hdmirxfw.bin"; + assigned-clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC1>, + <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC3>; + assigned-clock-parents = <&hdmi_rx_dig_pll>, + <&clk IMX_SC_R_HDMI_RX_BYPASS IMX_SC_PM_CLK_MISC2>; + assigned-clock-rates = <400000000>, <0>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-inmate.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Freescale i.MX8QM MEK inmate"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + system-controller { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: power-controller { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; + #clock-cells = <2>; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 127 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + /* For early console */ + serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" +}; + +#include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-conn.dtsi" + +&edma0 { + status = "disabled"; +}; + +&edma1 { + status = "disabled"; +}; + +&edma2 { + status = "disabled"; +}; + +&acm { + status = "disabled"; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&lsio_gpio0 { + status = "disabled"; +}; + +&lsio_gpio1 { + status = "disabled"; +}; + +&lsio_gpio2 { + status = "disabled"; +}; + +&lsio_gpio3 { + status = "disabled"; +}; + +&lsio_gpio4 { + status = "disabled"; +}; + +&lsio_gpio5 { + status = "disabled"; +}; + +&lsio_gpio6 { + status = "disabled"; +}; + +&lsio_gpio7 { + status = "disabled"; +}; + +&fec1 { + /delete-property/ iommus; +}; + +&fec2 { + /delete-property/ iommus; +}; + +&usdhc1 { + /delete-property/ iommus; +}; + +&usdhc2 { + /delete-property/ iommus; +}; + +&usdhc3 { + /delete-property/ iommus; +}; + +&usbotg3 { + /delete-property/ iommus; +}; + +&usbotg3_cdns3 { + /delete-property/ iommus; +}; + +&iomuxc { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 + IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; + /delete-property/ dma-names; + /delete-property/ dmas; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qm-mek.dts" +#include "imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + lvds-to-hdmi-bridge@4c { + status = "disabled"; + }; +}; + +/delete-node/ &it6263_1_in; + +&ldb2 { + status = "okay"; + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qm-mek-rpmsg.dts" +#include "imx8qm-mek-jdi-wuxga-lvds1-panel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qm-mek.dts" + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_2 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_3 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_4 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_5 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_6 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_7 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + /delete-property/virtual-channel; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_0_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + }; +}; + +&mipi_csi_1 { + /delete-property/virtual-channel; + + /* Camera 1 MIPI CSI-2 (CSIS0) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov5640_mipi_1_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + }; +}; + +&i2c_mipi_csi0 { + ov5640_mipi_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; + +&i2c_mipi_csi1 { + ov5640_mipi_1: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-pcie-ep.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8qm-mek-rpmsg.dts" + +&pciea{ + status = "disabled"; +}; + +&pcieb{ + status = "disabled"; +}; + +&pciea_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + ext_osc = <1>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-revd.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-revd.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-revd.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-revd.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 NXP + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + + sound-wm8960 { + status = "disabled"; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8962>; + hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN1R", "AMIC", + "IN3R", "AMIC"; + }; +}; + +&wm8960 { + status = "disabled"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-revd-sof-wm8962.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-revd-sof-wm8962.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-revd-sof-wm8962.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-revd-sof-wm8962.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 NXP + */ + +#include "imx8qm-mek-rpmsg.dts" + +/delete-node/ &wm8960; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; + +/ { + /delete-node/ sound-wm8960; + + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_reserved_heap; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sof-sound-wm8962 { + compatible = "simple-audio-card"; + label = "wm8962-audio"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Microphone", "Headset Mic", + "Microphone", "Digital Mic", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Headphones", "HPOUTL", + "Headphones", "HPOUTR", + "Speaker", "SPKOUTL", + "Speaker", "SPKOUTR", + "Headset Mic", "MICBIAS", + "IN1R", "Headset Mic", + "IN3R", "Headset Mic", + "DMICDAT", "Digital Mic"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 1>; + }; + sndcodec: codec { + sound-dai = <&wm8962>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x591f0000 0x10000>, + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <6>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan21-tx", /* gpt5 */ + "edma2-chan23-rx"; /* gpt7 */ + + power-domains = <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH21>, + <&pd IMX_SC_R_DMA_2_CH23>; + power-domain-names = "edma2-chan8", "edma2-chan9", + "edma2-chan12", "edma2-chan13", + "edma2-chan21", "edma2-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + + clock-names = "ipg", "ocram", "core", + "sai1_bus", "sai1_mclk0", "sai1_mclk1", "sai1_mclk2", "sai1_mclk3"; + clocks = <&clk_dummy>, <&clk_dummy>, <&clk_dummy>, + <&sai1_lpcg 1>, <&clk_dummy>, <&sai1_lpcg 0>, + <&clk_dummy>, <&clk_dummy>; + assigned-clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; + memory-region = <&dsp_reserved>; + /delete-property/ firmware-name; + + tplg-name = "sof-imx8-wm8962.tplg"; + machine-drv-name = "asoc-simple-card"; + + status = "okay"; +}; + +&wm8962 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&cs42888 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-root.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm-mek.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + IMX_SC_R_MU_2A + >; + rsrcs = < + IMX_SC_R_SDHC_0 + IMX_SC_R_UART_2 + IMX_SC_R_MU_2A + >; + pads = < + /* emmc */ + IMX8QM_EMMC0_CLK + IMX8QM_EMMC0_CMD + IMX8QM_EMMC0_DATA0 + IMX8QM_EMMC0_DATA1 + IMX8QM_EMMC0_DATA2 + IMX8QM_EMMC0_DATA3 + IMX8QM_EMMC0_DATA4 + IMX8QM_EMMC0_DATA5 + IMX8QM_EMMC0_DATA6 + IMX8QM_EMMC0_DATA7 + IMX8QM_EMMC0_STROBE + IMX8QM_EMMC0_RESET_B + /* lpuart2 */ + IMX8QM_UART0_RTS_B + IMX8QM_UART0_CTS_B + >; + }; + }; + +}; + +&{/reserved-memory} { + + jh_reserved: jh@fdc00000 { + no-map; + reg = <0x0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@fdb00000 { + no-map; + reg = <0x0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@fd900000 { + no-map; + reg = <0x0 0xfd900000 0x0 0x00200000>; + }; + + pci_reserved: pci@fd700000 { + no-map; + reg = <0x0 0xfd700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@df7000000 { + no-map; + reg = <0x0 0xdf700000 0x0 0x1e000000>; + }; +}; + +&smmu { + /* Jailhouse hypervisor will initialize SMMU and use it. */ + status = "disabled"; +}; + +&usdhc1 { + /* Let U-Boot program SID */ + iommus = <&smmu 0x10 0x7f80>; + /delete-property/ compatible; +}; + +&lpuart2 { + /* Let inmate linux use this for console */ + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qm-mek.dts" + +/delete-node/ &cm41_i2c; + +&i2c_rpbus_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + status = "okay"; + }; +}; + +&cm41_i2c_lpcg { + status = "disabled"; +}; + +®_can01_en { + status = "disabled"; +}; + +®_can2_en { + status = "disabled"; +}; + +®_can01_stby { + status = "disabled"; +}; + +®_can2_stby { + status = "disabled"; +}; + +&cm41_intmux { + status = "disabled"; +}; + +&can0_lpcg { + status = "disabled"; +}; + +&can1_lpcg { + status = "disabled"; +}; + +&can2_lpcg { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&flexcan3 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&lpuart2 { + status = "disabled"; +}; + +&uart2_lpcg { + status = "disabled"; +}; + +&imx8qm_cm40 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; +}; + +&imx8qm_cm41 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-cs42888.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 + +#include "imx8qm-mek-rpmsg.dts" + +/ { + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_reserved_heap; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sof-audio-cs42888 { + compatible = "simple-audio-card"; + label = "imx-cs42888"; + simple-audio-card,widgets = + "Line", "Line Out Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + status = "okay"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 0>; + }; + codec { + sound-dai = <&cs42888>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x591f0000 0x10000>, + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ + "edma2-chan21-tx", /* gpt5 */ + "edma2-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_DMA_2_CH21>, + <&pd IMX_SC_R_DMA_2_CH23>; + power-domain-names = "edma2-chan8", "edma2-chan9", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15", + "edma2-chan21", "edma2-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + + clocks = <&clk_dummy>, <&clk_dummy>, <&clk_dummy>, + <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&clk_dummy>; + clock-names = "ipg", "ocram", "core", + "esai0_core", "esai0_extal", "esai0_fsys", "esai0_spba"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; + memory-region = <&dsp_reserved>; + /delete-property/ firmware-name; + + tplg-name = "sof-imx8-cs42888.tplg"; + machine-drv-name = "asoc-simple-card"; + + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-sof.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-sof.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-sof.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-sof.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2022 + +#include "imx8qm-mek-rpmsg.dts" + +/ { + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_reserved_heap; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sof-audio { + compatible = "simple-audio-card"; + label = "wm8960-audio"; + simple-audio-card,widgets = + "Line", "Line Out Jack", + "Line", "Line In Jack", + "Headphone", "Headphones", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack", + "Headphones", "HP_L", + "Headphones", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + status = "okay"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&dsp 0>; + }; + codec { + sound-dai = <&cs42888>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + bitclock-master=<&sndcodec>; + frame-master=<&sndcodec>; + hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + cpu { + sound-dai = <&dsp 1>; + }; + sndcodec: codec { + sound-dai = <&wm8960>; + }; + }; + + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x591f0000 0x10000>, + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <6>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan21-tx", /* gpt5 */ + "edma2-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH21>, + <&pd IMX_SC_R_DMA_2_CH23>; + power-domain-names = "edma2-chan8", "edma2-chan9", + "edma2-chan12", "edma2-chan13", + "edma2-chan21", "edma2-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>, <&pinctrl_sai1>; + + + clocks = <&clk_dummy>, <&clk_dummy>, <&clk_dummy>, + <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&clk_dummy>, + <&sai1_lpcg 1>, <&clk_dummy>, <&sai1_lpcg 0>, + <&clk_dummy>, <&clk_dummy>; + clock-names = "ipg", "ocram", "core", + "esai0_core", "esai0_extal", "esai0_fsys", "esai0_spba", + "sai1_bus", "sai1_mclk0", "sai1_mclk1", "sai1_mclk2", "sai1_mclk3"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>, <&sai1_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <0>, <786432000>, <49152000>, <12288000>, <49152000>, + <49152000>; + + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; + memory-region = <&dsp_reserved>; + /delete-property/ firmware-name; + + tplg-name = "sof-imx8-wm8960-cs42888.tplg"; + machine-drv-name = "asoc-simple-card"; + + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&cs42888 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-sof-wm8960.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qm-mek-rpmsg.dts" + +/ { + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_reserved_heap; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sof-sound-wm8960 { + compatible = "simple-audio-card"; + label = "wm8960-audio"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Headphones", "HP_L", + "Headphones", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 1>; + }; + sndcodec: codec { + sound-dai = <&wm8960>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x591f0000 0x10000>, + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <6>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan21-tx", /* gpt5 */ + "edma2-chan23-rx"; /* gpt7 */ + + power-domains = <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH21>, + <&pd IMX_SC_R_DMA_2_CH23>; + power-domain-names = "edma2-chan8", "edma2-chan9", + "edma2-chan12", "edma2-chan13", + "edma2-chan21", "edma2-chan23"; + status = "okay"; +}; + +&dsp { + compatible = "fsl,imx8qm-dsp"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + + clock-names = "ipg", "ocram", "core", + "sai1_bus", "sai1_mclk0", "sai1_mclk1", "sai1_mclk2", "sai1_mclk3"; + clocks = <&clk_dummy>, <&clk_dummy>, <&clk_dummy>, + <&sai1_lpcg 1>, <&clk_dummy>, <&sai1_lpcg 0>, + <&clk_dummy>, <&clk_dummy>; + assigned-clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; + memory-region = <&dsp_reserved>; + /delete-property/ firmware-name; + + tplg-name = "sof-imx8-wm8960.tplg"; + machine-drv-name = "asoc-simple-card"; + + status = "okay"; +}; + +&wm8960 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&cs42888 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ +#include "imx8qm-mek-rpmsg.dts" + +/ { + reg_usdhc3_vmmc: usdhc3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + power-domains = <&pd IMX_SC_R_BOARD_R3>; + }; +}; + +&iomuxc { + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + >; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + bus-width = <4>; + pinctrl-assert-gpios = <&lsio_gpio4 10 GPIO_ACTIVE_HIGH>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + vmmc-supply = <®_usdhc3_vmmc>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ +#include "imx8qm-mek-rpmsg.dts" + +&pinctrl_usdhc2 { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000021 + >; +}; + +&usdhc2 { + pinctrl-assert-gpios = <&lsio_gpio4 8 GPIO_ACTIVE_HIGH>; + /delete-property/ cd-gpios; + /delete-property/ wp-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-pcieax2pciebx1.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include +#include "imx8qm-mek.dts" + +/* + * Add the PCIeA x2 lanes and PCIeB x1 lane usecase + * hsio-cfg = + * NOTE: In this case, the HSIO nodes contained + * hsio-cfg = would be re-configured. + */ +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + num-lanes = <2>; + clocks = <&pciea_lpcg 0>, + <&pciea_lpcg 1>, + <&pciea_lpcg 2>, + <&phyx2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per","pcie_per", "misc_per"; + hsio-cfg = ; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx1_lpcg 0>, + <&phyx2_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&pciea_crr2_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "pcie_phy_pclk", "phy_per", + "pcie_per", "pciex2_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_PCIE_A>, + <&pd IMX_SC_R_SERDES_0>, + <&pd IMX_SC_R_SERDES_1>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_per", "pcie_phy", + "pcie_serdes", "hsio_gpio"; + hsio-cfg = ; + status = "okay"; +}; + +&sata { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +/delete-node/ &acm; +/delete-node/ &sai4; +/delete-node/ &sai5; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5_lpcg; + +/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ +&edma0{ + reg = <0x591f0000 0x10000>, + <0x59200000 0x10000>, /* asrc0 */ + <0x59210000 0x10000>, + <0x59220000 0x10000>, + <0x59230000 0x10000>, + <0x59240000 0x10000>, + <0x59250000 0x10000>, + <0x59260000 0x10000>, /* esai0 rx */ + <0x59270000 0x10000>, /* esai0 tx */ + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592A0000 0x10000>, /* spdif1 rx */ + <0x592B0000 0x10000>, /* spdif1 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59300000 0x10000>, /* sai2 rx */ + <0x59310000 0x10000>, /* sai3 rx */ + <0x59320000 0x10000>, /* sai4 rx */ + <0x59330000 0x10000>; /* sai5 tx */ + dma-channels = <20>; + interrupts = , /* asrc0 */ + , + , + , + , + , + , /* esai0 */ + , + , /* spdif0 */ + , + , /* spdif1 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , /* sai2 */ + , /* sai3 */ + , /* sai4 */ + ; /* sai5 */ + interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */ + "edma2-chan2-rx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx", + "edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */ + "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan10-rx", "edma2-chan11-tx", /* spdif1 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ + "edma2-chan16-rx", "edma2-chan17-tx", /* sai2, dai3 */ + "edma2-chan18-rx", "edma2-chan19-tx"; /* sai4, sai5 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_DMA_2_CH16>, + <&pd IMX_SC_R_DMA_2_CH17>, + <&pd IMX_SC_R_DMA_2_CH18>, + <&pd IMX_SC_R_DMA_2_CH19>; + power-domain-names = "edma2-chan0", "edma2-chan1", + "edma2-chan2", "edma2-chan3", + "edma2-chan4", "edma2-chan5", + "edma2-chan6", "edma2-chan7", + "edma2-chan8", "edma2-chan9", + "edma2-chan10", "edma2-chan11", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15", + "edma2-chan16", "edma2-chan17", + "edma2-chan18", "edma2-chan19"; +}; + +/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */ +&edma1{ + reg = <0x599F0000 0x10000>, + <0x59A00000 0x10000>, /* asrc1 */ + <0x59A10000 0x10000>, + <0x59A20000 0x10000>, + <0x59A30000 0x10000>, + <0x59A40000 0x10000>, + <0x59A50000 0x10000>, + <0x59A80000 0x10000>, /* sai6 rx */ + <0x59A90000 0x10000>, /* sai6 tx */ + <0x59AA0000 0x10000>; /* sai7 tx */ + dma-channels = <9>; + interrupts = , /* asrc1 */ + , + , + , + , + , + , /* sai6 */ + , + ; /* sai7 */ + interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */ + "edma3-chan2-rx", "edma3-chan3-tx", + "edma3-chan4-tx", "edma3-chan5-tx", + "edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */ + "edma3-chan10-tx"; /* sai7 */ + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, + <&pd IMX_SC_R_DMA_3_CH1>, + <&pd IMX_SC_R_DMA_3_CH2>, + <&pd IMX_SC_R_DMA_3_CH3>, + <&pd IMX_SC_R_DMA_3_CH4>, + <&pd IMX_SC_R_DMA_3_CH5>, + <&pd IMX_SC_R_DMA_3_CH8>, + <&pd IMX_SC_R_DMA_3_CH9>, + <&pd IMX_SC_R_DMA_3_CH10>; + power-domain-names = "edma3-chan0", "edma3-chan1", + "edma3-chan2", "edma3-chan3", + "edma3-chan4", "edma3-chan5", + "edma3-chan8", "edma3-chan9", + "edma3-chan10"; +}; + +&asrc0 { + clocks = <&asrc0_lpcg 0>, + <&asrc0_lpcg 1>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_0>; +}; + +&esai0 { + power-domains = <&pd IMX_SC_R_ESAI_0>; +}; + +&spdif0 { + power-domains = <&pd IMX_SC_R_SPDIF_0>; +}; + +&spdif1 { + power-domains = <&pd IMX_SC_R_SPDIF_1>; +}; + +&sai0 { + power-domains = <&pd IMX_SC_R_SAI_0>; +}; + +&sai1 { + power-domains = <&pd IMX_SC_R_SAI_1>; +}; + +&sai2 { + power-domains = <&pd IMX_SC_R_SAI_2>; +}; + +&sai3 { + power-domains = <&pd IMX_SC_R_SAI_3>; +}; + +&asrc1 { + clocks = <&asrc1_lpcg 0>, + <&asrc1_lpcg 1>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_1>; +}; + +&amix { + dais = <&sai6>, <&sai7>; +}; + +&asrc0_lpcg { + clocks = <&audio_ipg_clk>, + <&audio_ipg_clk>; + bit-offset = <0 8>; + clock-output-names = "asrc0_lpcg_ipg_clk", + "asrc0_lpcg_mem_clk"; +}; + +&esai0_lpcg { + bit-offset = <16 0>; + clock-output-names = "esai0_lpcg_extal_clk", + "esai0_lpcg_ipg_clk"; +}; + +&spdif0_lpcg { + bit-offset = <20 16>; + clock-output-names = "spdif0_lpcg_tx_clk", + "spdif0_lpcg_gclkw"; +}; + +&spdif1_lpcg { + bit-offset = <20 16>; + clock-output-names = "spdif1_lpcg_tx_clk", + "spdif1_lpcg_gclkw"; +}; + +&sai0_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai0_lpcg_mclk", + "sai0_lpcg_ipg_clk"; +}; + +&sai1_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai1_lpcg_mclk", + "sai1_lpcg_ipg_clk"; +}; + +&sai2_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai2_lpcg_mclk", + "sai2_lpcg_ipg_clk"; +}; + +&sai3_lpcg { + bit-offset = <16 0>; + clock-output-names = "sai3_lpcg_mclk", + "sai3_lpcg_ipg_clk"; +}; + +&asrc1_lpcg { + clocks = <&audio_ipg_clk>, + <&audio_ipg_clk>; + bit-offset = <0 8>; + clock-output-names = "asrc1_lpcg_ipg_clk", + "asrc1_lpcg_mem_clk"; +}; + +&mqs0_lpcg { + bit-offset = <16 0>; + clock-output-names = "mqs0_lpcg_mclk", + "mqs0_lpcg_ipg_clk"; +}; + +&dsp_lpcg { + status = "disabled"; +}; + +&dsp_ram_lpcg { + status = "disabled"; +}; + +&audio_subsys { + acm: acm@59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x59e00000 0x1D0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_ESAI_1>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SAI_6>, + <&pd IMX_SC_R_SAI_7>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_SPDIF_1>, + <&pd IMX_SC_R_MQS_0>; + }; + + sai4: sai@59080000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59080000 0x10000>; + interrupts = ; + clocks = <&sai4_lpcg 1>, + <&clk_dummy>, + <&sai4_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 18 0 1>; + fsl,dataline = <0 0xf 0x0>; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59090000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59090000 0x10000>; + interrupts = ; + clocks = <&sai5_lpcg 1>, + <&clk_dummy>, + <&sai5_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma0 19 0 0>; + fsl,dataline = <0 0x0 0xf>; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + esai1: esai@59810000 { + compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; + reg = <0x59810000 0x10000>; + interrupts = ; + clocks = <&esai1_lpcg 1>, + <&esai1_lpcg 0>, + <&esai1_lpcg 1>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma1 6 0 1>, <&edma1 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + status = "disabled"; + }; + + sai6: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = ; + clocks = <&sai6_lpcg 1>, + <&clk_dummy>, + <&sai6_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; + power-domains = <&pd IMX_SC_R_SAI_6>; + status = "disabled"; + }; + + sai7: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = ; + clocks = <&sai7_lpcg 1>, + <&clk_dummy>, + <&sai7_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma1 10 0 0>; + power-domains = <&pd IMX_SC_R_SAI_7>; + status = "disabled"; + }; + + sai4_lpcg: clock-controller@59480000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59480000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai4_lpcg_mclk", + "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5_lpcg: clock-controller@59490000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59490000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai5_lpcg_mclk", + "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + esai1_lpcg: clock-controller@59c10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c10000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "esai1_lpcg_extal_clk", + "esai1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + }; + + sai6_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai6_lpcg_mclk", + "sai6_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_6>; + }; + + sai7_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <16 0>; + clock-output-names = "sai7_lpcg_mclk", + "sai7_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_7>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -4,22 +4,70 @@ * Dong Aisheng */ +&conn_subsys { + usbh1: usb@5b0e0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb", + "fsl,imx27-usb"; + reg = <0x5b0e0000 0x200>; + interrupt-parent = <&gic>; + interrupts = ; + phy_type = "hsic"; + dr_mode = "host"; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + clocks = <&usb2_lpcg 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd IMX_SC_R_USB_1>; + status = "disabled"; + }; + + usbmisc2: usbmisc@5b0e0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x5b0e0200 0x200>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&usb2_lpcg 1>; + clock-names = "main_clk"; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + status = "disabled"; + }; +}; + &fec1 { compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; + iommus = <&smmu 0x12 0x7f80>; }; &fec2 { compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; + iommus = <&smmu 0x12 0x7f80>; }; &usdhc1 { compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + iommus = <&smmu 0x11 0x7f80>; }; &usdhc2 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; + iommus = <&smmu 0x11 0x7f80>; }; &usdhc3 { compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + iommus = <&smmu 0x11 0x7f80>; +}; + +&usbotg3 { + iommus = <&smmu 0x4 0x7f80>; +}; + +&usbotg3_cdns3 { + iommus = <&smmu 0x4 0x7f80>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +&dpu1 { + compatible = "fsl,imx8qm-dpu"; + + dpu1_disp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dpu1_disp0_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_disp>; + }; + + dpu1_disp0_mipi0: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi0_dsi_in>; + }; + }; + + dpu1_disp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dpu1_disp1_ldb1_ch0: endpoint@0 { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu1_disp1_ldb1_ch1: endpoint@1 { + remote-endpoint = <&ldb1_ch1>; + }; + }; +}; + +&dpu2 { + compatible = "fsl,imx8qm-dpu"; + + dpu2_disp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dpu2_disp0_mipi1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_dsi_in>; + }; + + }; + + dpu2_disp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dpu2_disp1_ldb2_ch0: endpoint@0 { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu2_disp1_ldb2_ch1: endpoint@1 { + remote-endpoint = <&ldb2_ch1>; + }; + }; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>, + <&dpu2_disp0>, <&dpu2_disp1>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +&ddr_subsys { + ddr_pmu1: ddr-pmu@5c120000 { + compatible = "fsl,imx8qm-ddr-pmu", "fsl,imx8-ddr-pmu"; + reg = <0x5c120000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; +}; + +&ddr_pmu0 { + interrupts = ; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -5,17 +5,188 @@ */ &dma_subsys { + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + reg = <0x5a0a0000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&uart4_lpcg 1>, <&uart4_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_4>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 21 0 0>, + <&edma2 20 0 1>; + status = "disabled"; + }; + uart4_lpcg: clock-controller@5a4a0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a4a0000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; - clock-indices = , ; + bit-offset = <0 16>; clock-output-names = "uart4_lpcg_baud_clk", "uart4_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_UART_4>; }; + + i2c4: i2c@5a840000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a840000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c4_lpcg 0>, + <&i2c4_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_4>; + status = "disabled"; + }; + + i2c4_lpcg: clock-controller@5ac40000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac40000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c4_lpcg_clk", + "i2c4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_4>; + }; + + can1_lpcg: clock-controller@5ace0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ace0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + bit-offset = <0 16 20>; + clock-output-names = "can1_lpcg_pe_clk", + "can1_lpcg_ipg_clk", + "can1_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_1>; + }; + + can2_lpcg: clock-controller@5acf0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acf0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + bit-offset = <0 16 20>; + clock-output-names = "can2_lpcg_pe_clk", + "can2_lpcg_ipg_clk", + "can2_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_2>; + }; +}; + +&flexcan1 { + fsl,clk-source = /bits/ 8 <1>; +}; + +&flexcan2 { + clocks = <&can1_lpcg 1>, + <&can1_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; + fsl,clk-source = /bits/ 8 <1>; +}; + +&flexcan3 { + clocks = <&can2_lpcg 1>, + <&can2_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; + fsl,clk-source = /bits/ 8 <1>; +}; + +&lpspi2 { + compatible = "fsl,imx8qm-lpspi", "fsl,imx7ulp-spi"; +}; + +/* edma0 called in imx8qm RM with the same address in edma2 of imx8qxp */ +&edma2 { + reg = <0x5a1f0000 0x10000>, + <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ + <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ + <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */ + <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */ + <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */ + <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */ + <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ + <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ + <0x5a2c0000 0x10000>, /* channel12 UART0 rx */ + <0x5a2d0000 0x10000>, /* channel13 UART0 tx */ + <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ + <0x5a2f0000 0x10000>, /* channel15 UART1 tx */ + <0x5a300000 0x10000>, /* channel16 UART2 rx */ + <0x5a310000 0x10000>, /* channel17 UART2 tx */ + <0x5a320000 0x10000>, /* channel18 UART3 rx */ + <0x5a330000 0x10000>, /* channel19 UART3 tx */ + <0x5a340000 0x10000>, /* channel20 UART4 rx */ + <0x5a350000 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <18>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-rx", "edma0-chan5-tx", + "edma0-chan6-rx", "edma0-chan7-tx", + "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan14-rx", "edma0-chan15-tx", + "edma0-chan16-rx", "edma0-chan17-tx", + "edma0-chan18-rx", "edma0-chan19-tx", + "edma0-chan20-rx", "edma0-chan21-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan2", "edma0-chan3", + "edma0-chan4", "edma0-chan5", + "edma0-chan6", "edma0-chan7", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan16", "edma0-chan17", + "edma0-chan18", "edma0-chan19", + "edma0-chan20", "edma0-chan21"; + status = "okay"; }; &lpuart0 { @@ -24,14 +195,20 @@ &lpuart1 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 15 0 0>, + <&edma2 14 0 1>; }; &lpuart2 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 17 0 0>, + <&edma2 16 0 1>; }; &lpuart3 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 19 0 0>, + <&edma2 18 0 1>; }; &i2c0 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +&gpu_3d0 { + assigned-clock-rates = <800000000>, <1000000000>; + fsl,sc_gpu_pid = ; +}; + +&gpu1_subsys { + imx8_gpu_ss: imx8_gpu1_ss { + compatible = "fsl,imx8qm-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>, <&gpu_3d1>; + reg = <0x80000000 0x80000000>, <0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + depth-compression = <0>; + /**/ + operating-points = < + /*overdrive*/ 800000 0 /*The first tuple is for core clock frequency*/ + 1000000 0 /*The second tuple is for shader clock frequency*/ + /*nominal*/ 650000 0 + 700000 0 + /*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ + >; + status = "disabled"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Sandor Yu + */ + +#include + +/ { + hdmi_subsys: bus@56260000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56260000 0x0 0x56260000 0x10000>; + + irqsteer_hdmi: irqsteer@56260000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56260000 0x1000>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupts = ; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&hdmi_lpcg_lis_ipg 0>; + clock-names = "ipg"; + assigned-clocks = <&clk IMX_SC_R_HDMI_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + assigned-clock-rates = <800000000>, <84375000>; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_i2c0: clock-controller@56263000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI_I2C_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <0 16>; + clock-output-names = "hdmi_lpcg_i2c0_clk", + "hdmi_lpcg_i2c0_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI_I2C_0>; + status = "disabled"; + }; + + hdmi_lpcg_lis_ipg: clock-controller@56263004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263004 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_lis_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_pwm_ipg: clock-controller@56263008 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263008 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_pwm_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_i2s: clock-controller@5626300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5626300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI_I2S IMX_SC_PM_CLK_MISC0>; + bit-offset = <0>; + clock-output-names = "hdmi_lpcg_i2s_clk"; + power-domains = <&pd IMX_SC_R_HDMI_I2S>; + status = "disabled"; + }; + + hdmi_lpcg_gpio_ipg: clock-controller@56263010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_gpio_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_msi_hclk: clock-controller@56263014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <0>; + clock-output-names = "hdmi_lpcg_msi_hclk_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_pxl: clock-controller@56263018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>; + bit-offset = <0>; + clock-output-names = "hdmi_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_phy: clock-controller@5626301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5626301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <0 16>; + clock-output-names = "hdmi_lpcg_phy_vif_clk", + "hdmi_lpcg_phy_pclk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_apb_mux_csr: clock-controller@56263020 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263020 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_lpcg_apb 0>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_apb_mux_csr_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_apb_mux_ctrl: clock-controller@56263024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263024 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_lpcg_apb 0>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_apb_mux_ctrl_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + hdmi_lpcg_apb: clock-controller@56263028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56263028 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>; + bit-offset = <16>; + clock-output-names = "hdmi_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_HDMI>; + status = "disabled"; + }; + + i2c0_hdmi: i2c@56266000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x56266000 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + clocks = <&hdmi_lpcg_i2c0 0>, + <&hdmi_lpcg_i2c0 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_HDMI_I2C_0 IMX_SC_PM_CLK_MISC2>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_HDMI_I2C_0>; + status = "disabled"; + }; + + hdmi:hdmi@56268000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x56268000 0x1000>, + <0x56261000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <10>, <13>; + interrupt-names = "plug_in", "plug_out"; + firmware-name = "hdmitxfw.bin"; + status = "disabled"; + + clocks = <&clk IMX_SC_R_HDMI_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC4>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>, + <&hdmi_lpcg_phy 1>, + <&hdmi_lpcg_msi_hclk 0>, + <&hdmi_lpcg_pxl 0>, + <&hdmi_lpcg_phy 0>, + <&hdmi_lpcg_lis_ipg 0>, + <&hdmi_lpcg_apb 0>, + <&hdmi_lpcg_apb_mux_csr 0>, + <&hdmi_lpcg_apb_mux_ctrl 0>, + <&clk IMX_SC_R_HDMI_I2S IMX_SC_PM_CLK_BYPASS>, + <&hdmi_lpcg_i2s 0>; + clock-names = "dig_pll", "av_pll", "clk_ipg", + "clk_core", "clk_pxl", "clk_pxl_mux", + "clk_pxl_link", "lpcg_hdp", "lpcg_msi", + "lpcg_pxl", "lpcg_vif", "lpcg_lis", + "lpcg_apb", "lpcg_apb_csr", "lpcg_apb_ctrl", + "clk_i2s_bypass", "lpcg_i2s"; + assigned-clocks = <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC3>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_HDMI IMX_SC_PM_CLK_MISC1>; + assigned-clock-parents = <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_HDMI_PLL_1 IMX_SC_PM_CLK_PLL>; + power-domains = <&pd IMX_SC_R_HDMI>, + <&pd IMX_SC_R_HDMI_PLL_0>, + <&pd IMX_SC_R_HDMI_PLL_1>; + power-domain-names = "hdmi", "pll0", "pll1"; + + port@0 { + reg = <0>; + hdmi_disp: endpoint { + remote-endpoint = <&dpu1_disp0_hdmi>; + }; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi-rx.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi-rx.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi-rx.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-hdmi-rx.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * Sandor Yu + */ + +#include + +&img_subsys { + irqsteer_hdmi_rx: irqsteer@58260000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58260000 0x1000>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupts = ; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&hdmi_rx_ipg>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_HDMI_RX>; + status = "disabled"; + }; + + hdmi_rx_ipg: clock-hdmi-rx-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "hdmi_rx_ipg_clk"; + }; + + hdmi_rx_dig_pll: clock-hdmi-rx-dig-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "hdmi_rx_dig_pll_clk"; + }; + + hdmi_rx_lpcg_gpio_ipg_s: clock-controller@58263000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263000 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_rx_ipg>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_gpio_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX>; + status = "disabled"; + }; + + hdmi_rx_lpcg_pwm_ipg: clock-controller@58263004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263004 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_lpcg_pwm_ipg_s 0>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_pwm_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX_PWM_0>; + status = "disabled"; + }; + + hdmi_lpcg_pwm_ipg_s: clock-controller@58263008 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263008 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_rx_ipg>; + bit-offset = <0>; + clock-output-names = "hdmi_lpcg_pwm_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX_PWM_0>; + status = "disabled"; + }; + + hdmi_rx_lpcg_pwm: clock-controller@5826300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5826300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI_RX_PWM_0 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_pwm_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX_PWM_0>; + status = "disabled"; + }; + + hdmi_rx_lpcg_i2c0: clock-controller@58263010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263010 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_rx_lpcg_i2c0_div 0>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_i2c0_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>; + status = "disabled"; + }; + + hdmi_rx_lpcg_i2c0_div: clock-controller@58263014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI_RX_I2C_0 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_i2c0_div_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>; + status = "disabled"; + }; + + hdmi_rx_lpcg_i2c0_ipg: clock-controller@58263018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263018 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_rx_lpcg_i2c0_ipg_s 0>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_i2c0_ipg_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>; + status = "disabled"; + }; + + hdmi_rx_lpcg_i2c0_ipg_s: clock-controller@5826301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5826301c 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_rx_ipg>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_i2c0_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>; + status = "disabled"; + }; + + hdmi_rx_lpcg_sink_p: clock-controller@58263020 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263020 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_rx_ipg>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_sink_p_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX>; + status = "disabled"; + }; + + hdmi_rx_lpcg_sink_s: clock-controller@58263024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263024 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_rx_ipg>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_sink_s_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX>; + status = "disabled"; + }; + + hdmi_rx_lpcg_hd_core: clock-controller@58263028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263028 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_hd_core_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX>; + status = "disabled"; + }; + + hdmi_rx_lpcg_pxl: clock-controller@5826302c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5826302c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC3>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX>; + status = "disabled"; + }; + + hdmi_rx_lpcg_enc: clock-controller@58263030 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263030 0x4>; + #clock-cells = <1>; + clocks = <&hdmi_rx_lpcg_pxl 0>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_enc_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX>; + status = "disabled"; + }; + + i2c0_hdmi_rx: i2c@58266000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x58266000 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi_rx>; + clocks = <&hdmi_rx_lpcg_i2c0>, + <&hdmi_rx_lpcg_i2c0_ipg>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_HDMI_RX_I2C_0 IMX_SC_PM_CLK_MISC2>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_HDMI_RX_I2C_0>; + status = "disabled"; + }; +}; + +&cameradev { + hdmi_rx: hdmi_rx@58268000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cdn,imx8qm-hdmirx"; + reg = <0x58268000 0x10000>, /* HDP Controller */ + <0x58261000 0x1000>; /* HDP SubSystem CSR */ + interrupts = <10>, <13>; + interrupt-names = "plug_in", "plug_out"; + interrupt-parent = <&irqsteer_hdmi_rx>; + clocks = <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC1>, + <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC3>, + <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC4>, + <&clk IMX_SC_R_HDMI_RX IMX_SC_PM_CLK_MISC0>, + <&hdmi_rx_lpcg_sink_p 0>, + <&hdmi_rx_lpcg_sink_s 0>, + <&hdmi_rx_lpcg_enc 0>, + <&hdmi_rx_pxl_link_lpcg 0>; + clock-names = "ref_clk", + "pxl_clk", "i2s_clk", "spdif_clk", + "lpcg_pclk", "lpcg_sclk", "lpcg_enc_clk", + "lpcg_pxl_link_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX>; + power-domain-names = "hdmi_rx"; + status = "disabled"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Richard Zhu + */ + +&hsio_subsys { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + pciea_lpcg: clock-controller@5f050000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f050000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; + bit-offset = <16 20 24>; + clock-output-names = "hsio_pciea_mstr_axi_clk", + "hsio_pciea_slv_axi_clk", + "hsio_pciea_dbi_axi_clk"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + }; + + sata_lpcg: clock-controller@5f070000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f070000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_axi_clk>; + bit-offset = <16>; + clock-output-names = "hsio_sata_clk"; + power-domains = <&pd IMX_SC_R_SATA_0>; + }; + + phyx2_lpcg: clock-controller@5f080000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f080000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refa_clk>, <&hsio_per_clk>, + <&hsio_refa_clk>, <&hsio_per_clk>; + bit-offset = <0 4 16 20>; + clock-output-names = "hsio_phyx2_pclk_0", + "hsio_phyx2_pclk_1", + "hsio_phyx2_apbclk_0", + "hsio_phyx2_apbclk_1"; + power-domains = <&pd IMX_SC_R_SERDES_0>; + }; + + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refa_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + bit-offset = <0 4 8 16>; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; + + phyx2_crr0_lpcg: clock-controller@5f0a0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0a0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_phyx2_per_clk"; + power-domains = <&pd IMX_SC_R_SERDES_0>; + }; + + pciea_crr2_lpcg: clock-controller@5f0c0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0c0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_pciea_per_clk"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + }; + + sata_crr4_lpcg: clock-controller@5f0e0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0e0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_sata_per_clk"; + power-domains = <&pd IMX_SC_R_SATA_0>; + }; + + phyx2_csr: csr@5f110000 { + compatible = "syscon"; + reg = <0x5f110000 0x8>; + }; + + pciea_csr: csr@5f130000 { + compatible = "syscon"; + reg = <0x5f130000 0x18>; + }; + + sata_csr: csr@5f150000 { + compatible = "syscon"; + reg = <0x5f150000 0x8>; + }; + + phyx2_0: pcie-phy@5f180000 { + compatible = "fsl,imx8qm-pcie-phy"; + reg = <0x5f180000 0x10000>; + ctrl-csr = <&pciea_csr>; + phy-csr = <&phyx2_csr>; + misc-csr = <&misc_csr>; + clocks = <&phyx2_lpcg 2>, <&phyx2_lpcg 0>, <&pciea_crr2_lpcg 0>, + <&phyx2_crr0_lpcg 0>, <&misc_crr5_lpcg 0>; + clock-names = "apb_pclk", "pipe_pclk", "ctrl_ips_clk", + "phy_ips_clk", "misc_ips_clk"; + power-domains = <&pd IMX_SC_R_SERDES_0>; + #phy-cells = <0>; + hsio-cfg = ; + status = "disabled"; + }; + + phyx2_1: pcie-phy@5f190000 { + compatible = "fsl,imx8qm-pcie-phy"; + reg = <0x5f190000 0x10000>; + ctrl-csr = <&pcieb_csr>; + phy-csr = <&phyx2_csr>; + misc-csr = <&misc_csr>; + clocks = <&phyx2_lpcg 3>, <&phyx2_lpcg 1>, <&pcieb_crr3_lpcg 0>, + <&phyx2_crr0_lpcg 0>, <&misc_crr5_lpcg 0>; + clock-names = "apb_pclk", "pipe_pclk", "ctrl_ips_clk", + "phy_ips_clk", "misc_ips_clk"; + power-domains = <&pd IMX_SC_R_SERDES_0>; + #phy-cells = <0>; + hsio-cfg = ; + status = "disabled"; + }; + + phyx1: pcie-phy@5f1a0000 { + compatible = "fsl,imx8qm-pcie-phy"; + reg = <0x5f1a0000 0x10000>; + ctrl-csr = <&sata_csr>; + phy-csr = <&phyx1_csr>; + misc-csr = <&misc_csr>; + clocks = <&phyx1_lpcg 0>, <&sata_crr4_lpcg 0>, + <&phyx1_crr1_lpcg 0>, <&misc_crr5_lpcg 0>; + clock-names = "pipe_pclk", "ctrl_ips_clk", + "phy_ips_clk", "misc_ips_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + #phy-cells = <0>; + hsio-cfg = ; + status = "disabled"; + }; + + pciea: pcie@5f000000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x5f000000 0x10000>, /* Controller reg */ + <0x6ff00000 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x6ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60000000 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 73 4>, + <0 0 0 2 &gic 0 74 4>, + <0 0 0 3 &gic 0 75 4>, + <0 0 0 4 &gic 0 76 4>; + clocks = <&pciea_lpcg 0>, + <&pciea_lpcg 1>, + <&pciea_lpcg 2>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + local-addr = <0x40000000>; + ctrl-csr = <&pciea_csr>; + phys = <&phyx2_0>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pciea_ep: pcie_ep@5f000000 { + compatible = "fsl,imx8qm-pcie-ep"; + reg = <0x5f000000 0x00010000>, + <0x60000000 0x10000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&pciea_lpcg 0>, + <&pciea_lpcg 1>, + <&pciea_lpcg 2>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + local-addr = <0x40000000>; + ctrl-csr = <&pciea_csr>; + phys = <&phyx2_0>; + phy-names = "pcie-phy"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + + pcieb: pcie@5f010000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x5f010000 0x10000>, /* Controller reg */ + <0x7ff00000 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + local-addr = <0x80000000>; + ctrl-csr = <&pcieb_csr>; + /* + * FIXME + * Since "REXT" pin is only present for "lane 0" of + * "PHY Instance 0", and its calibration result will be + * stored, and shared with "lane 1" of "PHY Instance 0" + * and "lane0" of "PHY Instance 1". + * + * Add the "lane 0" of "PHY Instance 0" here, although + * only "lane 1" of "PHY Instance 0" is used by PCIeb. + */ + phys = <&phyx2_1>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + sata: sata@5f020000 { + compatible = "fsl,imx8qm-ahci"; + reg = <0x5f020000 0x10000>, /* Controller reg */ + <0x5f1a0000 0x10000>; /* PHY reg */ + reg-names = "ctl", "phy"; + interrupts = ; + clocks = <&sata_lpcg 0>, + <&phyx1_lpcg 1>, + <&phyx1_lpcg 2>, + <&sata_crr4_lpcg 0>; + clock-names = "sata", "epcs_tx", "epcs_rx", "sata_ref"; + power-domains = <&pd IMX_SC_R_SATA_0>; + fsl,sc_rsrc_id = ; + iommus = <&smmu 0x13 0x7f80>; + ctrl-csr = <&sata_csr>; + /* + * Since "REXT" pin is only present for "lane 0" of + * "PHY Instance 0", and its calibration result will be + * stored, and shared with "lane 1" of "PHY Instance 0" + * and "lane0" of "PHY Instance 1". + * + * Add the "lane 0" of "PHY Instance 0" here, although + * only "lane 0" of "PHY Instance 1" is used by SATA. + */ + phys = <&phyx1>, <&phyx2_0>, <&phyx2_1>; + phy-names = "sata-phy", "cali-phy0", "cali-phy1"; + status = "disabled"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -10,3 +10,15 @@ &jpegenc { compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc"; }; + +&pi0_pxl_lpcg { + status = "disabled"; +}; + +&pi0_ipg_lpcg { + status = "disabled"; +}; + +&pi0_misc_lpcg { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -3,33 +3,100 @@ * Copyright 2019-2020 NXP * Dong Aisheng */ +&lsio_subsys { + lsio_mu6: mailbox@5d210000 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; + reg = <0x5d210000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_6A>; + }; + + lsio_mu8: mailbox@5d230000 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; + reg = <0x5d230000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_8A>; + status = "disabled"; + }; + + lsio_mu8b: mailbox@5d2c0000 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; + reg = <0x5d2c0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + fsl,mu-side-b; + power-domains = <&pd IMX_SC_R_MU_8B>; + status = "disabled"; + }; + +}; &lsio_gpio0 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 0 6>, + <&iomuxc 6 7 22>, + <&iomuxc 28 36 4>; }; &lsio_gpio1 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 40 4>, + <&iomuxc 4 50 12>, + <&iomuxc 16 63 8>, + <&iomuxc 24 72 8>; }; &lsio_gpio2 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 80 4>, + <&iomuxc 4 85 18>, + <&iomuxc 22 104 10>; }; &lsio_gpio3 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 114 2>, + <&iomuxc 2 117 16>, + <&iomuxc 18 141 1>, + <&iomuxc 19 140 1>, + <&iomuxc 20 139 1>, + <&iomuxc 21 138 1>, + <&iomuxc 22 137 1>, + <&iomuxc 23 136 1>, + <&iomuxc 24 135 1>, + <&iomuxc 25 134 1>, + <&iomuxc 26 142 3>, + <&iomuxc 29 146 3>; }; &lsio_gpio4 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 149 3>, + <&iomuxc 3 153 4>, + <&iomuxc 7 158 6>, + <&iomuxc 13 165 6>, + <&iomuxc 19 172 8>, + <&iomuxc 27 198 5>; }; &lsio_gpio5 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 203 1>, + <&iomuxc 1 205 2>, + <&iomuxc 3 210 11>, + <&iomuxc 14 223 3>, + <&iomuxc 17 227 2>, + <&iomuxc 19 230 5>, + <&iomuxc 24 236 6>, + <&iomuxc 30 243 2>; }; &lsio_gpio6 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 245 10>, + <&iomuxc 10 256 12>; }; &lsio_gpio7 { @@ -63,7 +130,3 @@ &lsio_mu6 { compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; }; - -&lsio_mu13 { - compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; -}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +/ { + lvds1_subsys: bus@56240000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56240000 0x0 0x56240000 0x10000>; + + lvds0_ipg_clk: clock-lvds-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "lvds0_ipg_clk"; + }; + + lvds0_lis_lpcg: clock-controller@56243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243000 0x4>; + #clock-cells = <1>; + clocks = <&lvds0_ipg_clk>; + bit-offset = <16>; + clock-output-names = "lvds0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; + + lvds0_pwm_lpcg: clock-controller@5624300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5624300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&lvds0_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds0_pwm_lpcg_clk", + "lvds0_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>; + }; + + lvds0_i2c0_lpcg: clock-controller@56243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds0_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds0_i2c0_lpcg_clk", + "lvds0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + }; + + lvds0_i2c1_lpcg: clock-controller@56243014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds0_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds0_i2c1_lpcg_clk", + "lvds0_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + }; + + irqsteer_lvds0: irqsteer@56240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&lvds0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; + + lvds0_region: lvds_region@56241000 { + compatible = "syscon"; + reg = <0x56241000 0xf0>; + }; + + ldb1_phy: ldb_phy@56241000 { + compatible = "mixel,lvds-phy"; + reg = <0x56241000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_0>; + status = "disabled"; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb1: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_0>; + gpr = <&lvds0_region>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu1_disp1_ldb1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu1_disp1_ldb1_ch1>; + }; + }; + }; + }; + + pwm_lvds0: pwm@56244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x56244000 0x1000>; + clocks = <&lvds0_pwm_lpcg 0>, + <&lvds0_pwm_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>; + status = "disabled"; + }; + + i2c0_lvds0: i2c@56246000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_lvds0>; + clocks = <&lvds0_i2c0_lpcg 0>, + <&lvds0_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + status = "disabled"; + }; + + i2c1_lvds0: i2c@56247000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56247000 0x1000>; + interrupts = <9>; + interrupt-parent = <&irqsteer_lvds0>; + clocks = <&lvds0_i2c0_lpcg 0>, + <&lvds0_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + status = "disabled"; + }; + }; + + lvds2_subsys: bus@57240000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x57240000 0x0 0x57240000 0x10000>; + + lvds1_ipg_clk: clock-lvds-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "lvds1_ipg_clk"; + }; + + lvds1_lis_lpcg: clock-controller@57243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243000 0x4>; + #clock-cells = <1>; + clocks = <&lvds1_ipg_clk>; + bit-offset = <16>; + clock-output-names = "lvds1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + }; + + lvds1_pwm_lpcg: clock-controller@5724300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5724300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>, + <&lvds1_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds1_pwm_lpcg_clk", + "lvds1_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>; + }; + + lvds1_i2c0_lpcg: clock-controller@57243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds1_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds1_i2c0_lpcg_clk", + "lvds1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + }; + + lvds1_i2c1_lpcg: clock-controller@57243014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds1_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds1_i2c1_lpcg_clk", + "lvds1_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + }; + + irqsteer_lvds1: irqsteer@57240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x57240000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&lvds1_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + }; + + lvds1_region: lvds_region@57241000 { + compatible = "syscon"; + reg = <0x57241000 0xf0>; + }; + + ldb2_phy: ldb_phy@57241000 { + compatible = "mixel,lvds-phy"; + reg = <0x57241000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_PHY>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_1>; + status = "disabled"; + + ldb2_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb2_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb2: ldb@572410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_1>; + gpr = <&lvds1_region>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu2_disp1_ldb2_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu2_disp1_ldb2_ch1>; + }; + }; + }; + }; + + pwm_lvds1: pwm@57244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x57244000 0x1000>; + clocks = <&lvds1_pwm_lpcg 0>, + <&lvds1_pwm_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>; + status = "disabled"; + }; + + i2c0_lvds1: i2c@57246000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x57246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&lvds1_i2c0_lpcg 0>, + <&lvds1_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + status = "disabled"; + }; + + i2c1_lvds1: i2c@57247000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x57247000 0x1000>; + interrupts = <9>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&lvds1_i2c0_lpcg 0>, + <&lvds1_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + status = "disabled"; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +/ { + dsi_ipg_clk: clock-dsi-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "dsi_ipg_clk"; + }; + + mipi_pll_div2_clk: clock-mipi-div2-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <432000000>; + clock-output-names = "mipi_pll_div2_clk"; + }; + + mipi0_subsys: bus@56220000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56220000 0x0 0x56220000 0x10000>; + + mipi0_lis_lpcg: clock-controller@56223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223000 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi0_i2c0_lpcg_clk: clock-controller@5622301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223018 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223014 0x4>; + #clock-cells = <1>; + clocks = <&mipi0_i2c0_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi0_i2c1_lpcg_clk: clock-controller@5622302c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622302c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + }; + + mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223028 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + }; + + mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223024 0x4>; + #clock-cells = <1>; + clocks = <&mipi0_i2c1_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi0_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + }; + + irqsteer_mipi0: irqsteer@56220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56220000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + i2c0_mipi0: i2c@56226000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi0>; + clocks = <&mipi0_i2c0_lpcg_clk 0>, + <&mipi0_i2c0_lpcg_ipg_clk 0>; + clock-names = "per", "ipg"; + assigned-clocks = <&mipi0_i2c0_lpcg_clk 0>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + status = "disabled"; + }; + + mipi0_csr: csr@56221000 { + compatible = "syscon"; + reg = <0x56221000 0x240>; + }; + + mipi0_dphy: dphy@56228300 { + compatible = "fsl,imx8qm-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + }; + + mipi0_dsi_host: dsi_host@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-nwl-dsi"; + reg = <0x56228000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + phys = <&mipi0_dphy>; + phy-names = "dphy"; + csr = <&mipi0_csr>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi0_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu1_disp0_mipi0>; + }; + }; + }; + }; + }; + + mipi1_subsys: bus@57220000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x57220000 0x0 0x57220000 0x10000>; + + mipi1_lis_lpcg: clock-controller@57223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223000 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi1_i2c0_lpcg_clk: clock-controller@5722301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5722301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223018 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223014 0x4>; + #clock-cells = <1>; + clocks = <&mipi1_i2c0_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi1_i2c1_lpcg_clk: clock-controller@5722302c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5722302c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + }; + + mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223028 0x4>; + #clock-cells = <1>; + clocks = <&dsi_ipg_clk>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + }; + + mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57223024 0x4>; + #clock-cells = <1>; + clocks = <&mipi1_i2c1_lpcg_ipg_s_clk 0>; + bit-offset = <0>; + clock-output-names = "mipi1_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + }; + + irqsteer_mipi1: irqsteer@57220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x57220000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi1_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + i2c0_mipi1: i2c@57226000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x57226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi1>; + clocks = <&mipi1_i2c0_lpcg_clk 0>, + <&mipi1_i2c0_lpcg_ipg_clk 0>; + clock-names = "per", "ipg"; + assigned-clocks = <&mipi1_i2c0_lpcg_clk 0>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + status = "disabled"; + }; + + mipi1_csr: csr@57221000 { + compatible = "syscon"; + reg = <0x57221000 0x240>; + }; + + mipi1_dphy: dphy@57228300 { + compatible = "fsl,imx8qm-mipi-dphy"; + reg = <0x57228300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + }; + + mipi1_dsi_host: dsi_host@57228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-nwl-dsi"; + reg = <0x57228000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi1>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + phys = <&mipi1_dphy>; + phy-names = "dphy"; + csr = <&mipi1_csr>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi1_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu2_disp0_mipi1>; + }; + }; + }; + }; + }; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +&usdhc1 { + /delete-property/ iommus; +}; + +&usdhc2 { + /delete-property/ iommus; +}; + +&usdhc3 { + /delete-property/ iommus; +}; + +&fec1 { + /delete-property/ iommus; +}; + +&fec2 { + /delete-property/ iommus; +}; + +&sata { + /delete-property/ iommus; +}; + +&usbotg3 { + /delete-property/ iommus; +}; + +&usbotg3_cdns3 { + /delete-property/ iommus; +}; + +&smmu { + /* xen only supports legacy bindings for now */ + #iommu-cells = <0>; +}; + +&dpu1 { + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + ; +}; + +&dpu2 { + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + ; +}; + +/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ +&edma0{ + fsl,sc_rsrc_id = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&edma1 { + xen,passthrough; +}; + +&acm { + xen,passthrough; +}; + +&asrc0 { + xen,passthrough; +}; + +&esai0 { + xen,passthrough; +}; + +&spdif0 { + xen,passthrough; +}; + +&spdif1 { + xen,passthrough; +}; + +&sai0 { + xen,passthrough; +}; + +&sai1 { + xen,passthrough; +}; + +&sai2 { + xen,passthrough; +}; + +&sai3 { + xen,passthrough; +}; + +&asrc1 { + xen,passthrough; +}; + +&amix { + xen,passthrough; +}; + +&asrc0_lpcg { + xen,passthrough; +}; + +&esai0_lpcg { + xen,passthrough; +}; + +&spdif0_lpcg { + xen,passthrough; +}; + +&spdif1_lpcg { + xen,passthrough; +}; + +&sai0_lpcg { + xen,passthrough; +}; + +&sai1_lpcg { + xen,passthrough; +}; + +&sai2_lpcg { + xen,passthrough; +}; + +&sai3_lpcg { + xen,passthrough; +}; + +&asrc1_lpcg { + xen,passthrough; +}; + +&mqs0_lpcg { + xen,passthrough; +}; + +&dsp_lpcg { + xen,passthrough; +}; + +&dsp_ram_lpcg { + xen,passthrough; +}; + +&sai4 { + xen,passthrough; +}; + +&sai5 { + xen,passthrough; +}; + +&esai1 { + xen,passthrough; +}; + +&sai6 { + xen,passthrough; +}; + +&sai7 { + xen,passthrough; +}; + +&sai4_lpcg { + xen,passthrough; +}; + +&sai5_lpcg { + xen,passthrough; +}; + +&esai1_lpcg { + xen,passthrough; +}; + +&sai6_lpcg { + xen,passthrough; +}; + +&sai7_lpcg { + xen,passthrough; +}; + +&amix_lpcg { + xen,passthrough; +}; + +&aud_rec0_lpcg { + xen,passthrough; +}; + +&aud_rec1_lpcg { + xen,passthrough; +}; + +&aud_pll_div0_lpcg { + xen,passthrough; +}; + +&aud_pll_div1_lpcg { + xen,passthrough; +}; + +&mclkout0_lpcg { + xen,passthrough; +}; + +&mclkout1_lpcg { + xen,passthrough; +}; + +/ { + +dma_subsys: bus@5a000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; + + /* edma0 called in imx8qm RM with the same address in edma2 of imx8qxp */ + edma214: dma-controller@5a2e0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a1f0000 0x10000>, + <0x5a2e0000 0x10000>, /* channel14 UART1 rx */ + <0x5a2f0000 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>; + power-domain-names = "edma0-chan14", "edma0-chan15"; + status = "okay"; + fsl,sc_rsrc_id = , + ; + }; +}; +}; + +&edma2 { + reg = <0x5a1f0000 0x10000>, + <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ + <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ + <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ + <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ + <0x5a2c0000 0x10000>, /* channel12 UART0 rx */ + <0x5a2d0000 0x10000>, /* channel13 UART0 tx */ + <0x5a300000 0x10000>, /* channel16 UART2 rx */ + <0x5a310000 0x10000>, /* channel17 UART2 tx */ + <0x5a320000 0x10000>, /* channel18 UART3 rx */ + <0x5a330000 0x10000>, /* channel19 UART3 tx */ + <0x5a340000 0x10000>, /* channel20 UART4 rx */ + <0x5a350000 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan6-rx", "edma0-chan7-tx", + "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan16-rx", "edma0-chan17-tx", + "edma0-chan18-rx", "edma0-chan19-tx", + "edma0-chan20-rx", "edma0-chan21-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan6", "edma0-chan7", + "edma0-chan12", "edma0-chan13", + "edma0-chan16", "edma0-chan17", + "edma0-chan18", "edma0-chan19", + "edma0-chan20", "edma0-chan21"; + status = "okay"; +}; + +&lpspi0 { +}; + +&lpuart1 { + dmas = <&edma214 15 0 0>, <&edma214 14 0 1>; +}; + +&lpuart2 { +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qp.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qp.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qp.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qp.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QP"; + compatible = "fsl,imx8qp", "fsl,imx8qm"; +}; + +&cpus { + cpu-map { + cluster1 { + /delete-node/ core1; + }; + }; + /delete-node/ cpu@101; +}; + +&gpu_3d0 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&gpu_3d1 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&imx8_gpu_ss {/**/ + operating-points = < + /*nominal*/ 625000 0 + 625000 0 +/*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ + >; +}; + +&thermal_zones { + cpu-thermal1 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qp-lpddr4-val.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qp.dtsi" +#include "imx8q-val.dtsi" + +/ { + model = "Freescale i.MX8QP Validation Board"; + compatible = "fsl,imx8qp-val", "fsl,imx8qp", "fsl,imx8qm"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8q-val.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8q-val.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8q-val.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8q-val.dtsi 2024-06-19 12:33:58.300192566 +0200 @@ -0,0 +1,997 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/ { + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&lsio_gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x1000000>; + no-map; + }; + dsp_reserved_heap: dsp_reserved_heap { + reg = <0 0x93400000 0 0xef0000>; + no-map; + }; + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay = <3000>; + enable-active-high; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai0>; + audio-codec = <&codec>; + audio-asrc = <&asrc0>; + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&iomuxc { + imx8qm-val { + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds1_pwm0: lvds1pwm0grp { + fsl,pins = < + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ + fsl,pins = < + IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 + IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&lsio_gpio2 { + status = "okay"; +}; + +&lsio_gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + rx-internal-delay-ps = <2000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + qca,disable-smarteee; + vddio-supply = <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + qca,disable-smarteee; + vddio-supply = <&vddio1>; + status = "disabled"; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + rx-internal-delay-ps = <2000>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <8>; + }; +}; + +&gpio0_mipi_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; + status = "okay"; +}; + +&gpio0_mipi_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1_gpio>; + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi1 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_hdmi { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 1>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + fxas2100x@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + }; + + fxos8700@1d { + compatible = "nxp,fxos8700"; + reg = <0x1d>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "isil,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <20 2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart3 { /* GPS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "disabled"; + + /* Camera 0 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cm41_intmux { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-17x17-val.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp.dtsi" +#include "imx8x-17x17-val.dtsi" + +/ { + model = "Freescale i.MX8QXP 17x17 Validation Board"; + compatible = "fsl,imx8qxp-17x17-val", "fsl,imx8qxp"; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ddr3l-val.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-lpddr4-val.dts" + +/ { + model = "Freescale i.MX8QXP DDR3L VALIDATION"; + compatible = "fsl,imx8qxp-ddr3l-val", "fsl,imx8qxp"; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0xc0000000 0 0x14000000>; + linux,cma-default; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -20,6 +21,7 @@ #size-cells = <2>; aliases { + dpu0 = &dpu1; ethernet0 = &fec1; ethernet1 = &fec2; gpio0 = &lsio_gpio0; @@ -34,6 +36,8 @@ i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; + ldb0 = &ldb1; + ldb1 = &ldb2; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; @@ -46,12 +50,30 @@ serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + csi0 = &mipi_csi_0; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + i2c5 = &i2c_rpbus_5; + i2c12 = &i2c_rpbus_12; + i2c13 = &i2c_rpbus_13; + i2c14 = &i2c_rpbus_14; + i2c15 = &i2c_rpbus_15; + mipi_dsi0 = &mipi0_dsi_host; + mipi_dsi1 = &mipi1_dsi_host; vpu_core0 = &vpu_core0; vpu_core1 = &vpu_core1; - vpu_core2 = &vpu_core2; }; - cpus { + cpus: cpus { #address-cells = <2>; #size-cells = <0>; @@ -160,37 +182,6 @@ interrupts = ; }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - decoder_boot: decoder-boot@84000000 { - reg = <0 0x84000000 0 0x2000000>; - no-map; - }; - - encoder_boot: encoder-boot@86000000 { - reg = <0 0x86000000 0 0x200000>; - no-map; - }; - - decoder_rpc: decoder-rpc@92000000 { - reg = <0 0x92000000 0 0x100000>; - no-map; - }; - - dsp_reserved: dsp@92400000 { - reg = <0 0x92400000 0 0x2000000>; - no-map; - }; - - encoder_rpc: encoder-rpc@94400000 { - reg = <0 0x94400000 0 0x700000>; - no-map; - }; - }; - pmu { compatible = "arm,cortex-a35-pmu"; interrupts = ; @@ -213,6 +204,8 @@ pd: power-controller { compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; + wakeup-irq = <235 236 237 258 262 267 271 + 345 346 347 348>; }; clk: clock-controller { @@ -228,11 +221,21 @@ compatible = "fsl,imx8qxp-scu-ocotp"; #address-cells = <1>; #size-cells = <1>; + read-only; + + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg = <0x2c6 6>; + }; }; scu_key: keys { compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; linux,keycodes = ; + wakeup-source; status = "disabled"; }; @@ -240,6 +243,11 @@ compatible = "fsl,imx8qxp-sc-rtc"; }; + secvio: secvio { + compatible = "fsl,imx-sc-secvio"; + nvmem = <&ocotp>; + }; + watchdog { compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; timeout-sec = <60>; @@ -251,6 +259,10 @@ }; }; + soc { + compatible = "fsl,imx8qxp-soc"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , /* Physical Secure */ @@ -259,6 +271,13 @@ ; /* Hypervisor */ }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + xtal32k: clock-xtal32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -306,16 +325,47 @@ }; }; + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + /* sorted in register address */ #include "imx8-ss-img.dtsi" + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm40.dtsi" #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-dc0.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" + #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-lcdif.dtsi" }; #include "imx8qxp-ss-img.dtsi" #include "imx8qxp-ss-adma.dtsi" #include "imx8qxp-ss-conn.dtsi" #include "imx8qxp-ss-lsio.dtsi" +#include "imx8qxp-ss-hsio.dtsi" +#include "imx8qxp-ss-dc.dtsi" +#include "imx8qxp-ss-lvds.dtsi" +#include "imx8qxp-ss-gpu.dtsi" + +&edma2 { + status = "okay"; +}; + +&A35_0 { + operating-points = < + /* kHz uV*/ + /* voltage is maintained by SCFW, so no need here */ + 1200000 0 + 900000 0 + >; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + clock-latency = <61036>; + #cooling-cells = <2>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,62 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&fec1 { + status = "disabled"; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_fec2_rmii>; + clocks = <&enet1_lpcg 4>, + <&enet1_lpcg 2>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_DISABLE_50>, + <&enet1_lpcg 0>, + <&enet1_lpcg 1>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + phy-reset-gpios = <&pca9557_a 3 GPIO_ACTIVE_LOW>; + phy-reset-duration = <20>; + phy-reset-post-delay = <100>; + /delete-property/ phy-supply; + /delete-property/ rx-internal-delay-ps; + /delete-property/ tx-internal-delay-ps; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + nxp,rmii-refclk-in; + }; + }; +}; + +&iomuxc { + pinctrl_fec2_rmii: fec2rmiigrp { + fsl,pins = < + IMX8QXP_ENET0_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT 0x06000020 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000020 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000020 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x06000020 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000020 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000020 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000020 + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000020 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-a0.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-lpddr4-val.dts" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,534 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2018 NXP + */ + +/dts-v1/; + +#include +#include "imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP LPDDR4 Validation Board"; + compatible = "fsl,imx8qxp-lpddr4-val", "fsl,imx8qxp"; + + chosen { + stdout-path = &lpuart0; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + + encoder_rpc: encoder-rpc@92200000 { + reg = <0 0x92200000 0 0x200000>; + no-map; + }; + + encoder_reserved: encoder_reserved@94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0xc0000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usbotg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai0>; + audio-codec = <&cs42888>; + audio-asrc = <&asrc0>; + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + status = "okay"; + }; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + qca,disable-smarteee; + vddio-supply = <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + qca,disable-smarteee; + vddio-supply = <&vddio1>; + status = "disabled"; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&usbotg3 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 497>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + mt35xu512aba0:flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 + IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; +}; + + pinctrl_lpi2c3: lpi2cgrp { + fsl,pins = < + IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 + IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-gpmi-nand.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + */ + +#include "imx8qxp-lpddr4-val.dts" + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + + IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c + IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c + IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c + IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c + + /* i.MX8QXP NAND use nand_re_dqs_pins */ + IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c + IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + + >; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; + fsl,use-minimum-ecc; +}; + +/* Disabled the usdhc1/usdhc2 since pin conflict */ +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qxp-lpddr4-val.dts" + +&iomuxc { + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK 0x6000040 + IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO 0x6000040 + IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI 0x6000040 + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 0x21 + >; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x6000040 + IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x6000040 + IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x6000040 + IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x6000040 + >; + }; +}; + +&lpspi0 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <5000000>; + reg = <0>; + }; +}; + +&lpspi2 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <10000000>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi-slave.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + */ + +#include "imx8qxp-lpddr4-val-lpspi.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi2 { + fsl,pins = < + IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x6000040 + IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x6000040 + IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x6000040 + IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x6000040 + >; +}; + +&lpspi2 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi2>; + /delete-property/ cs-gpios; + spi-slave; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,60 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx8qxp-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-cpu = <&sai1>; + audio-codec = <&mqs>; + audio-asrc = <&asrc1>; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_mqs: mqsgrp { + fsl,pins = < + IMX8QXP_SPDIF0_TX_ADMA_MQS_L 0xc6000061 + IMX8QXP_SPDIF0_RX_ADMA_MQS_R 0xc6000061 + >; + }; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,56 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; +}; + +&iomuxc { + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX 0xc6000040 + IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX 0xc6000040 + >; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&spdif0 { + compatible = "fsl,imx8qm-spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&spdif0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-a0.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek.dts" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dom0.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + + stdout-path = &lpuart0; + + module@0 { + bootargs = "earlycon=xen console=hvc0 root=/dev/mmcblk1p2 rootwait rw"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + /* The size will be override by uboot command */ + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + + }; + + reserved-memory { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x30000000>; + alloc-ranges = <0 0xc0000000 0 0x40000000>; + linux,cma-default; + }; + }; + + rtc0: rtc@23000000 { + interrupts = ; + xen,passthrough; + }; +}; + +&imx8_gpu_ss { + reg = <0xa8000000 0x58000000>, <0x0 0x10000000>; + status = "okay"; +}; + +&lsio_mu1 { + /* not map for dom0, dom0 will mmio trap to xen */ + xen,no-map; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-dpu-lcdif.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif-rpmsg.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-dpu-lcdif.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek.dts" +#include "imx8qxp-mek-dsi-rm67191.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/delete-node/ &adv_bridge0; +/delete-node/ &adv_bridge1; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&lvds_bridge0 { + status = "disabled"; +}; + +&lvds_bridge1 { + status = "disabled"; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&mipi0_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi0_panel_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + fsl,clock-drop-level = <2>; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port@0 { + reg = <0>; + panel1_in: endpoint { + remote-endpoint = <&mipi1_panel_out>; + }; + }; + }; + + ports { + /delete-node/ port@1; + + port@1 { + reg = <1>; + mipi1_panel_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67191-rpmsg.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8qxp-mek-dsi-rm67191.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67199.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek.dts" +#include "imx8qxp-mek-dsi-rm67191.dtsi" + +&mipi0_dsi_host { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&mipi1_dsi_host { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67199-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67199-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67199-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsi-rm67199-rpmsg.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8qxp-mek-dsi-rm67191.dtsi" + +&mipi0_dsi_host { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; + +&mipi1_dsi_host { + panel@0 { + compatible = "raydium,rm67199"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts 2024-06-19 12:33:58.308192703 +0200 @@ -1,297 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017~2018 NXP + * Copyright 2017-2020 NXP */ /dts-v1/; #include "imx8qxp.dtsi" +#include "imx8x-mek.dtsi" / { model = "Freescale i.MX8QXP MEK"; compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; - - chosen { - stdout-path = &lpuart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x40000000>; - }; - - reg_usdhc2_vmmc: usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "SD1_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&dsp { - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; - status = "okay"; - - i2c-mux@71 { - compatible = "nxp,pca9646", "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - pressure-sensor@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - pca9557_a: gpio@1a { - compatible = "nxp,pca9557"; - reg = <0x1a>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9557_b: gpio@1d { - compatible = "nxp,pca9557"; - reg = <0x1d>; - gpio-controller; - #gpio-cells = <2>; - }; - - light-sensor@44 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isl29023>; - compatible = "isil,isl29023"; - reg = <0x44>; - interrupt-parent = <&lsio_gpio1>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - }; - }; -}; - -&lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - status = "okay"; -}; - -&mu_m0 { - status = "okay"; -}; - -&mu1_m0 { - status = "okay"; -}; - -&scu_key { - status = "okay"; -}; - -&thermal_zones { - pmic-thermal0 { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; - - trips { - pmic_alert0: trip0 { - temperature = <110000>; - hysteresis = <2000>; - type = "passive"; - }; - - pmic_crit0: trip1 { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&pmic_alert0>; - cooling-device = - <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; - wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&vpu { - compatible = "nxp,imx8qxp-vpu"; - status = "okay"; -}; - -&vpu_core0 { - reg = <0x2d040000 0x10000>; - memory-region = <&decoder_boot>, <&decoder_rpc>; - status = "okay"; -}; - -&vpu_core1 { - reg = <0x2d050000 0x10000>; - memory-region = <&encoder_boot>, <&encoder_rpc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 - IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 - IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 - IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 - IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 - >; - }; - - pinctrl_ioexp_rst: ioexprstgrp { - fsl,pins = < - IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 - >; - }; - - pinctrl_isl29023: isl29023grp { - fsl,pins = < - IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 - IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 - >; - }; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 - IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - >; - }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,27 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-mek.dts" + +&esai0 { + status = "disabled"; +}; + +ðphy1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-sja1105.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-sja1105.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-sja1105.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-sja1105.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 NXP + */ + +#include "imx8qxp-mek-enet2.dts" + +/ { + clock_sja1105: clock-sja1105 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&iomuxc { + pinctrl_lpspi3: pinctrl_lpspi3grp { + fsl,pins = < + IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 + IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 + IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 + IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 0x0000021 + >; + }; +}; + +&pinctrl_fec2 { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8QXP_ENET0_MDC_CONN_ENET1_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000020 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000020 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000020 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000020 + IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000020 + IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000020 + IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000020 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000020 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000020 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000020 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000020 + IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000020 + >; +}; + +&fec1 { + status = "disabled"; +}; + +®_fec2_supply { + /delete-property/ enable-active-high; + gpio = <&max7322 0 GPIO_ACTIVE_LOW>; + regulator-always-on; +}; + +&lpspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <100000000>; + cs-gpios = <&lsio_gpio0 16 GPIO_ACTIVE_LOW>; + fsl,spi-num-chipselects = <1>; + spi-cpha; + status = "okay"; + + sja1105@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,sja1105q"; + reset-gpios = <&pca9557_a 3 GPIO_ACTIVE_LOW>; + spi-max-frequency = <12500000>; + spi-cpha; + clocks = <&clock_sja1105>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec2>; + phy-mode = "rgmii-id"; + tx-internal-delay-ps = <2000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "swp1"; + phy-handle = <&phy0>; + phy-mode = "mii"; + }; + + port@2 { + reg = <2>; + label = "swp2"; + phy-handle = <&phy1>; + phy-mode = "mii"; + }; + + port@3 { + reg = <3>; + label = "swp3"; + phy-handle = <&phy2>; + phy-mode = "rmii"; + }; + + port@4 { + reg = <4>; + label = "swp4"; + phy-handle = <&phy3>; + phy-mode = "rmii"; + }; + }; + }; +}; + +&fec2 { + phy-mode = "rgmii"; + /delete-property/ phy-handle; + /delete-property/ rx-internal-delay-ps; + tx-internal-delay-ps = <2000>; + status = "okay"; + + fixed-link { + speed=<1000>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@8 { + reg = <0x8>; + max-speed = <100>; + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@9 { + reg = <0x9>; + max-speed = <100>; + }; + + }; + + phy2: ethernet-phy@e { + reg = <0xe>; + max-speed = <100>; + #address-cells = <1>; + #size-cells = <0>; + + phy3: ethernet-phy@f { + reg = <0xf>; + max-speed = <100>; + }; + }; + + }; +}; + +ðphy1 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-enet2-tja1100.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,16 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-mek-enet2.dts" +#include "imx8qxp-enet2-tja1100.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Freescale i.MX8QXP MEK Inmate"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + system-controller { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: power-controller { + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #clock-cells = <2>; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qxp-iomuxc"; + }; + }; + + soc { + compatible = "fsl,imx8qxp-soc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + /* For early console */ + serial@5a060000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" +}; + +#include "imx8qxp-ss-lsio.dtsi" +#include "imx8qxp-ss-adma.dtsi" +#include "imx8qxp-ss-conn.dtsi" + +&edma0 { + status = "disabled"; +}; + +&edma1 { + status = "disabled"; +}; + +&acm { + status = "disabled"; +}; + +&iomuxc { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&lsio_gpio0 { + status = "disabled"; +}; + +&lsio_gpio1 { + status = "disabled"; +}; + +&lsio_gpio2 { + status = "disabled"; +}; + +&lsio_gpio3 { + status = "disabled"; +}; + +&lsio_gpio4 { + status = "disabled"; +}; + +&lsio_gpio5 { + status = "disabled"; +}; + +&lsio_gpio6 { + status = "disabled"; +}; + +&lsio_gpio7 { + status = "disabled"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; + /delete-property/ dma-names; + /delete-property/ dmas; +}; + +/delete-node/ &lpuart0; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds0-dual-channel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-it6263-lvds1-dual-channel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds0-panel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-jdi-wuxga-lvds1-panel.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-lcdif.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-lcdif-rpmsg.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8x-mek-lcdif.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +/dts-v1/; +#include "imx8qxp-mek.dts" +#include "imx8qxp-mek-ov5640.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640.dtsi 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +&isi_1 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_2 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&isi_3 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; + +&i2c_mipi_csi0 { + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&xtal24m>; + clock-names = "xclk"; + csi_id = <0>; + powerdown-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 8 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + /delete-node/max9286_mipi@6a; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-rpmsg.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2020 + +/dts-v1/; + +#include "imx8qxp-mek-rpmsg.dts" +#include "imx8qxp-mek-ov5640.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8qxp-mek-rpmsg.dts" + +&pcieb{ + status = "disabled"; +}; + +&pcieb_ep{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + ext_osc = <1>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + IMX_SC_R_MU_2A + >; + rsrcs = < + IMX_SC_R_SDHC_0 + IMX_SC_R_UART_2 + IMX_SC_R_MU_2A + >; + pads = < + /* emmc */ + IMX8QXP_EMMC0_CLK + IMX8QXP_EMMC0_CMD + IMX8QXP_EMMC0_DATA0 + IMX8QXP_EMMC0_DATA1 + IMX8QXP_EMMC0_DATA2 + IMX8QXP_EMMC0_DATA3 + IMX8QXP_EMMC0_DATA4 + IMX8QXP_EMMC0_DATA5 + IMX8QXP_EMMC0_DATA6 + IMX8QXP_EMMC0_DATA7 + IMX8QXP_EMMC0_STROBE + /* lpuart2 */ + IMX8QXP_UART2_TX + IMX8QXP_UART2_RX + >; + }; + }; + +}; + +&{/reserved-memory} { + + jh_reserved: jh@fdc00000 { + no-map; + reg = <0x0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@fdb00000 { + no-map; + reg = <0x0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@fd900000 { + no-map; + reg = <0x0 0xfd900000 0x0 0x00200000>; + }; + + pci_reserved: pci@fd700000 { + no-map; + reg = <0x0 0xfd700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@df7000000 { + no-map; + reg = <0x0 0xdf700000 0x0 0x1e000000>; + }; +}; + +&usdhc1 { + /delete-property/ compatible; +}; + +&lpuart2 { + /* Let inmate linux use this for console */ + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qxp-mek.dts" +#include "imx8x-mek-rpmsg.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-cs42888.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_reserved_heap; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sof-audio-cs42888 { + compatible = "simple-audio-card"; + label = "imx-cs42888"; + simple-audio-card,widgets = + "Line", "Line Out Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + status = "okay"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 0>; + }; + codec { + sound-dai = <&cs42888>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <8>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan21", "edma0-chan23"; + status = "okay"; +}; + +&dsp { + #sound-dai-cells = <1>; + compatible = "fsl,imx8qxp-dsp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + + clocks = <&clk_dummy>, <&clk_dummy>, <&clk_dummy>, <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, + <&clk_dummy>; + clock-names = "ipg", "ocram", "core", "esai0_core", "esai0_extal", "esai0_fsys", "esai0_spba"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; + memory-region = <&dsp_reserved>; + /delete-property/ firmware-name; + + reg = <0x596e8000 0x88000>; + tplg-name = "sof-imx8-cs42888.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + status = "disabled"; +}; + +&cs42888 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2022 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_reserved_heap; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sof-audio-cs42888 { + compatible = "simple-audio-card"; + label = "imx-cs42888"; + simple-audio-card,widgets = + "Line", "Line Out Jack", + "Line", "Line In Jack", + "Headphone", "Headphones", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; + + simple-audio-card,routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack", + "Headphones", "HP_L", + "Headphones", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + status = "okay"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&dsp 0>; + }; + codec { + sound-dai = <&cs42888>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + bitclock-master = <&sndcodec>; + frame-master = <&sndcodec>; + hp-det-gpio = <&lsio_gpio1 0 0>; + mic-det-gpio = <&lsio_gpio1 0 0>; + cpu { + sound-dai = <&dsp 1>; + }; + sndcodec: codec { + sound-dai = <&wm8960>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <6>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , + ; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan21", "edma0-chan23"; + status = "okay"; +}; + +&dsp { + #sound-dai-cells = <1>; + compatible = "fsl,imx8qxp-dsp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>, <&pinctrl_sai1>; + + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + + clocks = <&clk_dummy>, <&clk_dummy>, <&clk_dummy>, <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, + <&clk_dummy>, <&sai1_lpcg 1>, <&clk_dummy>, <&clk_dummy>, + <&sai1_lpcg 0>, <&clk_dummy>, <&clk_dummy>; + clock-names = "ipg", "ocram", "core", "esai0_core", "esai0_extal", "esai0_fsys", "esai0_spba", + "sai1_bus", "sai1_mclk0", "sai1_mclk1", "sai1_mclk2", "sai1_mclk3"; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <0>, <786432000>, <49152000>, <12288000>, <49152000>; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; + memory-region = <&dsp_reserved>; + /delete-property/ firmware-name; + + reg = <0x596e8000 0x88000>; + tplg-name = "sof-imx8-wm8960-cs4288.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&wm8960 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&cs42888 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-mek-sof-wm8960.dts 2024-06-19 12:33:58.304192634 +0200 @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2018 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_reserved_heap; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8960 { + status = "disabled"; + }; + + sof-sound-wm8960 { + compatible = "simple-audio-card"; + label = "wm8960-audio"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + hp-det-gpio = <&lsio_gpio1 0 0>; + mic-det-gpio = <&lsio_gpio1 0 0>; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Headphones", "HP_L", + "Headphones", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + simple-audio-card,dai-link { + format = "i2s"; + cpu { + sound-dai = <&dsp 1>; + }; + sndcodec: codec { + sound-dai = <&wm8960>; + }; + }; + }; +}; + +&edma0 { + compatible = "fsl,imx8qm-edma"; + reg = <0x591f0000 0x10000>, + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <6>; + interrupts = , /* spdif0 */ + , + , /* sai0 */ + , + , + ; + interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + + power-domains = <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan21", "edma0-chan23"; + status = "okay"; +}; + +&dsp { + #sound-dai-cells = <1>; + compatible = "fsl,imx8qxp-dsp"; + reg = <0x596e8000 0x88000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + + clock-names = "ipg", "ocram", "core", + "sai1_bus", "sai1_mclk0", "sai1_mclk1", "sai1_mclk2", "sai1_mclk3"; + clocks = <&clk_dummy>, <&clk_dummy>, <&clk_dummy>, + <&sai1_lpcg 1>, <&clk_dummy>, <&sai1_lpcg 0>, + <&clk_dummy>, <&clk_dummy>; + assigned-clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MISC1>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, + <&lsio_mu13 2 1>, + <&lsio_mu13 3 0>, + <&lsio_mu13 3 1>; + memory-region = <&dsp_reserved>; + /delete-property/ firmware-name; + + tplg-name = "sof-imx8-wm8960.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; + +&wm8960 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&asrc0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&cs42888 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -4,6 +4,14 @@ * Dong Aisheng */ +&dma_ipg_clk { + clock-frequency = <160000000>; +}; + +&audio_ipg_clk { + clock-frequency = <160000000>; +}; + &lpuart0 { compatible = "fsl,imx8qxp-lpuart"; }; @@ -35,3 +43,40 @@ &i2c3 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; }; + +&asrc0 { + compatible = "fsl,imx8qxp-asrc"; +}; + +&asrc1 { + compatible = "fsl,imx8qxp-asrc"; +}; + +&audio_subsys { + + dsp: dsp@596e8000 { + compatible = "fsl,imx8qxp-hifi4"; + reg = <0x596e8000 0x88000>; + clocks = <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "core", "ipg", "ocram"; + firmware-name = "imx/dsp/hifi4.bin"; + power-domains = <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu13 0 0>, + <&lsio_mu13 1 0>, + <&lsio_mu13 3 0>; + status = "disabled"; + }; +}; + +&dma_subsys { + lcdif_mux_regs: mux-regs@5a170000 { + compatible = "fsl,imx8qxp-lcdif-mux-regs", "syscon"; + reg = <0x5a170000 0x4>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +&dpu1 { + compatible = "fsl,imx8qxp-dpu"; + + dpu_disp0: port@0 { + reg = <0>; + + dpu_disp0_ldb1_ch0: endpoint@0 { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu_disp0_ldb1_ch1: endpoint@1 { + remote-endpoint = <&ldb1_ch1>; + }; + + dpu_disp0_mipi_dsi: endpoint@2 { + remote-endpoint = <&mipi0_dsi_in>; + }; + }; + + dpu_disp1: port@1 { + reg = <1>; + + dpu_disp1_ldb2_ch0: endpoint@0 { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu_disp1_ldb2_ch1: endpoint@1 { + remote-endpoint = <&ldb2_ch1>; + }; + + dpu_disp1_mipi_dsi: endpoint@2 { + remote-endpoint = <&mipi1_dsi_in>; + }; + + dpu_disp1_lcdif: endpoint@3 { + }; + }; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu_disp0>, <&dpu_disp1>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +&gpu0_subsys { + imx8_gpu_ss: imx8_gpu0_ss { + compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>; + reg = <0x80000000 0x80000000>, <0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Richard Zhu + */ + +&hsio_subsys { + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refb_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + bit-offset = <0 4 8 16>; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -11,3 +11,31 @@ &jpegenc { compatible = "nxp,imx8qxp-jpgenc"; }; + +&csi1_pxl_lpcg { + status = "disabled"; +}; + +&csi1_core_lpcg { + status = "disabled"; +}; + +&csi1_esc_lpcg { + status = "disabled"; +}; + +&irqsteer_csi1 { + status = "disabled"; +}; + +&i2c_mipi_csi1 { + status = "disabled"; +}; + +&gpio0_mipi_csi1 { + status = "disabled"; +}; + +&mipi_csi_1 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -6,26 +6,51 @@ &lsio_gpio0 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 1 56 12>, + <&iomuxc 13 69 4>, + <&iomuxc 19 75 4>, + <&iomuxc 24 80 1>, + <&iomuxc 25 82 7>; }; &lsio_gpio1 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 89 9>, + <&iomuxc 9 99 16>, + <&iomuxc 25 116 7>; }; &lsio_gpio2 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 123 1>, + <&iomuxc 1 126 2>, + <&iomuxc 3 129 1>; }; &lsio_gpio3 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 146 4>, + <&iomuxc 4 151 13>, + <&iomuxc 17 165 8>; }; &lsio_gpio4 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 7 9 6>, + <&iomuxc 13 16 6>, + <&iomuxc 19 23 2>, + <&iomuxc 21 26 2>, + <&iomuxc 23 30 6>, + <&iomuxc 29 37 3>; }; &lsio_gpio5 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 40 3>, + <&iomuxc 3 44 6>, + <&iomuxc 9 51 3>; }; &lsio_gpio6 { @@ -63,7 +88,3 @@ &lsio_mu6 { compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; }; - -&lsio_mu13 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; -}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +/ { + lvds_subsys: bus@56220000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56220000 0x0 0x56220000 0x30000>; + + mipi_ipg_clk: clock-mipi-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "mipi_ipg_clk"; + }; + + mipi_pll_div2_clk: clock-mipi-div2-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <432000000>; + clock-output-names = "mipi_pll_div2_clk"; + }; + + mipi0_lis_lpcg: clock-controller@56223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + bit-offset = <16>; + clock-output-names = "mipi0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi0_pwm_lpcg: clock-controller@5622300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>, + <&mipi_ipg_clk>; + bit-offset = <0 16 4>; + clock-output-names = "mipi0_pwm_lpcg_clk", + "mipi0_pwm_lpcg_ipg_clk", + "mipi0_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + }; + + mipi0_i2c0_lpcg: clock-controller@56223010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "mipi0_i2c0_lpcg_clk", + "mipi0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi1_lis_lpcg: clock-controller@56243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + bit-offset = <16>; + clock-output-names = "mipi1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi1_pwm_lpcg: clock-controller@5624300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5624300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>, + <&mipi_ipg_clk>; + bit-offset = <0 16 4>; + clock-output-names = "mipi1_pwm_lpcg_clk", + "mipi1_pwm_lpcg_ipg_clk", + "mipi1_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + }; + + mipi1_i2c0_lpcg: clock-controller@56243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "mipi1_i2c0_lpcg_clk", + "mipi1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + irqsteer_mipi_lvds0: irqsteer@56220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56220000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + lvds_region1: lvds_region@56221000 { + compatible = "syscon"; + reg = <0x56221000 0xf0>; + }; + + ldb1_phy: ldb_phy@56221000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x56221000 0x100>, <0x56228000 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>; + clock-names = "phy"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_0>; + status = "disabled"; + }; + + ldb1: ldb@562210e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass", + "aux_pixel", "aux_bypass"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_0>, + <&pd IMX_SC_R_LVDS_1>; + power-domain-names = "main", "aux"; + gpr = <&lvds_region1>; + fsl,auxldb = <&ldb2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu_disp0_ldb1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu_disp0_ldb1_ch1>; + }; + }; + }; + }; + + pwm_mipi_lvds0: pwm@56224000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56224000 0x1000>; + clocks = <&mipi0_pwm_lpcg 0>, + <&mipi0_pwm_lpcg 1>, + <&mipi0_pwm_lpcg 2>; + clock-names = "per", "ipg", "32k"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + status = "disabled"; + }; + + i2c0_mipi_lvds0: i2c@56226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + clocks = <&mipi0_i2c0_lpcg 0>, + <&mipi0_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + status = "disabled"; + }; + + mipi0_dphy: dphy@56228300 { + compatible = "fsl,imx8qm-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + }; + + mipi0_dsi_host: dsi_host@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qx-nwl-dsi"; + reg = <0x56228000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + phys = <&mipi0_dphy>; + phy-names = "dphy"; + csr = <&lvds_region1>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi0_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu_disp0_mipi_dsi>; + }; + }; + }; + }; + + irqsteer_mipi_lvds1: irqsteer@56240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi1_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + lvds_region2: lvds_region@56241000 { + compatible = "syscon"; + reg = <0x56241000 0xf0>; + }; + + ldb2_phy: ldb_phy@56241000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x56241000 0x100>, <0x56248000 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>; + clock-names = "phy"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_1>; + status = "disabled"; + }; + + ldb2: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass", + "aux_pixel", "aux_bypass"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_1>, + <&pd IMX_SC_R_LVDS_0>; + power-domain-names = "main", "aux"; + gpr = <&lvds_region2>; + fsl,auxldb = <&ldb1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu_disp1_ldb2_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu_disp1_ldb2_ch1>; + }; + }; + }; + }; + + pwm_mipi_lvds1: pwm@56244000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56244000 0x1000>; + clocks = <&mipi1_pwm_lpcg 0>, + <&mipi1_pwm_lpcg 1>, + <&mipi1_pwm_lpcg 2>; + clock-names = "per", "ipg", "32k"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + status = "disabled"; + }; + + i2c0_mipi_lvds1: i2c@56246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + clocks = <&mipi1_i2c0_lpcg 0>, + <&mipi1_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + status = "disabled"; + }; + + mipi1_dphy: dphy@56248300 { + compatible = "fsl,imx8qx-mipi-dphy"; + reg = <0x56248300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + }; + + mipi1_dsi_host: dsi_host@56248000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qx-nwl-dsi"; + reg = <0x56248000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>, + <&mipi_pll_div2_clk>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc", + "phy_parent"; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + phys = <&mipi1_dphy>; + phy-names = "dphy"; + csr = <&lvds_region2>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi1_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu_disp1_mipi_dsi>; + }; + }; + }; + }; + + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -16,7 +16,7 @@ audio_ipg_clk: clock-audio-ipg { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <120000000>; + clock-frequency = <175000000>; clock-output-names = "audio_ipg_clk"; }; @@ -27,8 +27,7 @@ clocks = <&audio_ipg_clk>, <&audio_ipg_clk>, <&audio_ipg_clk>; - clock-indices = , , - ; + bit-offset = <16 20 28>; clock-output-names = "dsp_lpcg_adb_clk", "dsp_lpcg_ipg_clk", "dsp_lpcg_core_clk"; @@ -40,29 +39,635 @@ reg = <0x59590000 0x10000>; #clock-cells = <1>; clocks = <&audio_ipg_clk>; - clock-indices = ; + bit-offset = <16>; clock-output-names = "dsp_ram_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_DSP_RAM>; }; - dsp: dsp@596e8000 { - compatible = "fsl,imx8qxp-dsp"; - reg = <0x596e8000 0x88000>; - clocks = <&dsp_lpcg IMX_LPCG_CLK_5>, - <&dsp_ram_lpcg IMX_LPCG_CLK_4>, - <&dsp_lpcg IMX_LPCG_CLK_7>; - clock-names = "ipg", "ocram", "core"; - power-domains = <&pd IMX_SC_R_MU_13A>, - <&pd IMX_SC_R_MU_13B>, - <&pd IMX_SC_R_DSP>, - <&pd IMX_SC_R_DSP_RAM>; - mbox-names = "txdb0", "txdb1", - "rxdb0", "rxdb1"; - mboxes = <&lsio_mu13 2 0>, - <&lsio_mu13 2 1>, - <&lsio_mu13 3 0>, - <&lsio_mu13 3 1>; - memory-region = <&dsp_reserved>; + acm: acm@59e00000 { + compatible = "nxp,imx8qxp-acm"; + reg = <0x59e00000 0x1D0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; + }; + + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc"; + reg = <0x59000000 0x10000>; + interrupts = , + ; + clocks = <&asrc0_lpcg 0>, + <&asrc0_lpcg 0>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>, + <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + fsl,asrc-clk-map = <0>; + power-domains = <&pd IMX_SC_R_ASRC_0>; + status = "disabled"; + }; + + esai0: esai@59010000 { + compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; + reg = <0x59010000 0x10000>; + interrupts = ; + clocks = <&esai0_lpcg 1>, + <&esai0_lpcg 0>, + <&esai0_lpcg 1>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma0 6 0 1>, <&edma0 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + status = "disabled"; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59020000 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&spdif0_lpcg 1>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif0_lpcg 0>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 8 0 5>, <&edma0 9 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + status = "disabled"; + }; + + spdif1: spdif@59030000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59030000 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&spdif1_lpcg 1>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif1_lpcg 0>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 10 0 5>, <&edma0 11 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_1>; + status = "disabled"; + }; + + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59040000 0x10000>; + interrupts = ; + clocks = <&sai0_lpcg 1>, + <&clk_dummy>, + <&sai0_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; + power-domains = <&pd IMX_SC_R_SAI_0>; + status = "disabled"; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59050000 0x10000>; + interrupts = ; + clocks = <&sai1_lpcg 1>, + <&clk_dummy>, + <&sai1_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; + power-domains = <&pd IMX_SC_R_SAI_1>; + status = "disabled"; + }; + + sai2: sai@59060000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59060000 0x10000>; + interrupts = ; + clocks = <&sai2_lpcg 1>, + <&clk_dummy>, + <&sai2_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 16 0 1>; + power-domains = <&pd IMX_SC_R_SAI_2>; + status = "disabled"; + }; + + sai3: sai@59070000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59070000 0x10000>; + interrupts = ; + clocks = <&sai3_lpcg 1>, + <&clk_dummy>, + <&sai3_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 17 0 1>; + power-domains = <&pd IMX_SC_R_SAI_3>; + status = "disabled"; + }; + + asrc1: asrc@59800000 { + compatible = "fsl,imx8qm-asrc"; + reg = <0x59800000 0x10000>; + interrupts = , + ; + clocks = <&asrc1_lpcg 0>, + <&asrc1_lpcg 0>, + <&aud_pll_div0_lpcg 0>, + <&aud_pll_div1_lpcg 0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>, + <&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + fsl,asrc-clk-map = <1>; + power-domains = <&pd IMX_SC_R_ASRC_1>; + status = "disabled"; + }; + + sai4: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = ; + clocks = <&sai4_lpcg 1>, + <&clk_dummy>, + <&sai4_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = ; + clocks = <&sai5_lpcg 1>, + <&clk_dummy>, + <&sai5_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma1 10 0 0>; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + amix: amix@59840000 { + compatible = "fsl,imx8qm-audmix"; + reg = <0x59840000 0x10000>; + clocks = <&amix_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_AMIX>; + dais = <&sai4>, <&sai5>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x59850000 0x10000>; + clocks = <&mqs0_lpcg 1>, + <&mqs0_lpcg 0>; + clock-names = "core", "mclk"; + power-domains = <&pd IMX_SC_R_MQS_0>; status = "disabled"; }; + + edma0: dma-controller@591F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x591f0000 0x10000>, + <0x59200000 0x10000>, /* asrc0 */ + <0x59210000 0x10000>, + <0x59220000 0x10000>, + <0x59230000 0x10000>, + <0x59240000 0x10000>, + <0x59250000 0x10000>, + <0x59260000 0x10000>, /* esai0 rx */ + <0x59270000 0x10000>, /* esai0 tx */ + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + <0x59300000 0x10000>, /* sai2 rx */ + <0x59310000 0x10000>, /* sai3 rx */ + <0x59350000 0x10000>, + <0x59370000 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <18>; + interrupts = , /* asrc 0 */ + , + , + , + , + , + , /* esai0 */ + , + , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , /* sai2 */ + , /* sai3 */ + , + ; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-tx", "edma0-chan5-tx", + "edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */ + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan16-rx", "edma0-chan17-rx", /* sai2, sai3 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH23>; + power-domain-names = "edma0-chan0", "edma0-chan1", + "edma0-chan2", "edma0-chan3", + "edma0-chan4", "edma0-chan5", + "edma0-chan6", "edma0-chan7", + "edma0-chan8", "edma0-chan9", + "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15", + "edma0-chan16", "edma0-chan17", + "edma0-chan21", "edma0-chan23"; + status = "okay"; + }; + + edma1: dma-controller@599F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x599F0000 0x10000>, + <0x59A00000 0x10000>, /* asrc1 */ + <0x59A10000 0x10000>, + <0x59A20000 0x10000>, + <0x59A30000 0x10000>, + <0x59A40000 0x10000>, + <0x59A50000 0x10000>, + <0x59A80000 0x10000>, /* sai4 rx */ + <0x59A90000 0x10000>, /* sai4 tx */ + <0x59AA0000 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <9>; + interrupts = , /* asrc 1 */ + , + , + , + , + , + , /* sai4 */ + , + ; /* sai5 */ + interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */ + "edma1-chan2-rx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */ + "edma1-chan10-tx"; /* sai5 */ + power-domains = <&pd IMX_SC_R_DMA_1_CH0>, + <&pd IMX_SC_R_DMA_1_CH1>, + <&pd IMX_SC_R_DMA_1_CH2>, + <&pd IMX_SC_R_DMA_1_CH3>, + <&pd IMX_SC_R_DMA_1_CH4>, + <&pd IMX_SC_R_DMA_1_CH5>, + <&pd IMX_SC_R_DMA_1_CH8>, + <&pd IMX_SC_R_DMA_1_CH9>, + <&pd IMX_SC_R_DMA_1_CH10>; + power-domain-names = "edma1-chan0", "edma1-chan1", + "edma1-chan2", "edma1-chan3", + "edma1-chan4", "edma1-chan5", + "edma1-chan8", "edma1-chan9", + "edma1-chan10"; + status = "okay"; + }; + + asrc0_lpcg: clock-controller@59400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59400000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + bit-offset = <16>; + clock-output-names = "asrc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_0>; + }; + + esai0_lpcg: clock-controller@59410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59410000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "esai0_lpcg_extal_clk", + "esai0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + }; + + spdif0_lpcg: clock-controller@59420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59420000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spdif0_lpcg_tx_clk", + "spdif0_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + }; + + spdif1_lpcg: clock-controller@59430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59430000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spdif1_lpcg_tx_clk", + "spdif1_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_1>; + status = "disabled"; + }; + + sai0_lpcg: clock-controller@59440000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59440000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai0_lpcg_mclk", + "sai0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_0>; + }; + + sai1_lpcg: clock-controller@59450000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59450000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai1_lpcg_mclk", + "sai1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_1>; + }; + + sai2_lpcg: clock-controller@59460000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59460000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai2_lpcg_mclk", + "sai2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_2>; + }; + + sai3_lpcg: clock-controller@59470000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59470000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai3_lpcg_mclk", + "sai3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_3>; + }; + + asrc1_lpcg: clock-controller@59c00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c00000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + bit-offset = <16>; + clock-output-names = "asrc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_1>; + }; + + sai4_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai4_lpcg_mclk", + "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + }; + + sai5_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "sai5_lpcg_mclk", + "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + }; + + amix_lpcg: clock-controller@59c40000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c40000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + bit-offset = <0>; + clock-output-names = "amix_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_AMIX>; + }; + + mqs0_lpcg: clock-controller@59c50000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c50000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "mqs0_lpcg_mclk", + "mqs0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MQS_0>; + }; + + aud_rec0_lpcg: clock-controller@59d00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d00000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + bit-offset = <0>; + clock-output-names = "aud_rec_clk0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; + }; + + aud_rec1_lpcg: clock-controller@59d10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d10000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>; + bit-offset = <0>; + clock-output-names = "aud_rec_clk1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; + }; + + aud_pll_div0_lpcg: clock-controller@59d20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>; + bit-offset = <0>; + clock-output-names = "aud_pll_div_clk0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; + }; + + aud_pll_div1_lpcg: clock-controller@59d30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d30000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>; + bit-offset = <0>; + clock-output-names = "aud_pll_div_clk1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; + }; + + mclkout0_lpcg: clock-controller@59d50000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d50000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>; + bit-offset = <0>; + clock-output-names = "mclkout0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; + }; + + mclkout1_lpcg: clock-controller@59d60000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d60000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>; + bit-offset = <0>; + clock-output-names = "mclkout1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MCLK_OUT_1>; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +cm40_subsys: bus@34000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x34000000 0x0 0x34000000 0x4000000>; + + cm40_ipg_clk: clock-cm40-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm40_ipg_clk"; + }; + + cm40_i2c: i2c@37230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x37230000 0x1000>; + interrupts = <9 0>; + interrupt-parent = <&cm40_intmux>; + clocks = <&cm40_i2c_lpcg 0>, + <&cm40_i2c_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + status = "disabled"; + }; + + cm40_i2c_lpcg: clock-controller@37630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x37630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>, + <&cm40_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "cm40_lpcg_i2c_clk", + "cm40_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + }; + + cm40_intmux: intmux@37400000 { + compatible = "fsl,imx8qxp-intmux", "fsl,imx-intmux"; + reg = <0x37400000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&cm40_ipg_clk>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; + status = "disabled"; + }; + + cm40_lpuart: serial@37220000 { + compatible = "fsl,imx8qxp-lpuart"; + reg = <0x37220000 0x1000>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&cm40_intmux>; + clocks = <&cm40_uart_lpcg 1>, <&cm40_uart_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_0_UART>; + status = "disabled"; + }; + + cm40_uart_lpcg: clock-controller@37620000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x37620000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>, + <&cm40_ipg_clk>; + bit-offset = <0 4>; + clock-output-names = "cm40_lpcg_uart_clk", + "cm40_lpcg_uart_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_0_UART>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +cm41_subsys: bus@38000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x38000000 0x0 0x38000000 0x4000000>; + + cm41_ipg_clk: clock-cm41-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm41_ipg_clk"; + }; + + cm41_i2c: i2c@3b230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x3b230000 0x1000>; + interrupts = <9 0>; + interrupt-parent = <&cm41_intmux>; + clocks = <&cm41_i2c_lpcg 0>, + <&cm41_i2c_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_1_I2C>; + status = "disabled"; + }; + + cm41_i2c_lpcg: clock-controller@3b630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x3b630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>, + <&cm41_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "cm41_lpcg_i2c_clk", + "cm41_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_1_I2C>; + }; + + cm41_intmux: intmux@3b400000 { + compatible = "fsl,imx8qxp-intmux", "fsl,imx-intmux"; + reg = <0x3b400000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&cm41_ipg_clk>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_1_INTMUX>; + status = "disabled"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -34,24 +34,68 @@ clock-output-names = "conn_ipg_clk"; }; + conn_bch_clk: clock-conn-bch { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "conn_bch_clk"; + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb", + "fsl,imx27-usb"; + reg = <0x5b0d0000 0x200>; + interrupt-parent = <&gic>; + interrupts = ; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&usb2_lpcg 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + power-domains = <&pd IMX_SC_R_USB_0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x5b0d0200 0x200>; + }; + + usbphy1: usbphy@5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", + "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x5b100000 0x1000>; + clocks = <&usb2_lpcg 1>; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + status = "disabled"; + }; + usdhc1: mmc@5b010000 { interrupts = ; reg = <0x5b010000 0x10000>; - clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, - <&sdhc0_lpcg IMX_LPCG_CLK_0>, - <&sdhc0_lpcg IMX_LPCG_CLK_5>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 2>, + <&sdhc0_lpcg 0>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <400000000>; power-domains = <&pd IMX_SC_R_SDHC_0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; usdhc2: mmc@5b020000 { interrupts = ; reg = <0x5b020000 0x10000>; - clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, - <&sdhc1_lpcg IMX_LPCG_CLK_0>, - <&sdhc1_lpcg IMX_LPCG_CLK_5>; + clocks = <&sdhc1_lpcg 1>, + <&sdhc1_lpcg 2>, + <&sdhc1_lpcg 0>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; @@ -61,11 +105,15 @@ usdhc3: mmc@5b030000 { interrupts = ; reg = <0x5b030000 0x10000>; - clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, - <&sdhc2_lpcg IMX_LPCG_CLK_0>, - <&sdhc2_lpcg IMX_LPCG_CLK_5>; + clocks = <&sdhc2_lpcg 1>, + <&sdhc2_lpcg 2>, + <&sdhc2_lpcg 0>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_2>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; @@ -75,11 +123,12 @@ , , ; - clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, - <&enet0_lpcg IMX_LPCG_CLK_2>, - <&enet0_lpcg IMX_LPCG_CLK_3>, - <&enet0_lpcg IMX_LPCG_CLK_0>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + clocks = <&enet0_lpcg 4>, + <&enet0_lpcg 2>, + <&enet0_lpcg 3>, + <&enet0_lpcg 0>, + <&enet0_lpcg 1>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; @@ -95,11 +144,12 @@ , , ; - clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, - <&enet1_lpcg IMX_LPCG_CLK_2>, - <&enet1_lpcg IMX_LPCG_CLK_3>, - <&enet1_lpcg IMX_LPCG_CLK_0>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + clocks = <&enet1_lpcg 4>, + <&enet1_lpcg 2>, + <&enet1_lpcg 3>, + <&enet1_lpcg 0>, + <&enet1_lpcg 1>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; @@ -109,6 +159,57 @@ status = "disabled"; }; + usb3_phy: usb-phy@5b160000 { + compatible = "nxp,salvo-phy"; + reg = <0x5B160000 0x40000>; + clocks = <&usb3_lpcg 4>; + clock-names = "salvo_phy_clk"; + power-domains = <&pd IMX_SC_R_USB_2_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbotg3: usb@5b110000 { + compatible = "fsl,imx8qm-usb3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x5B110000 0x10000>; + clocks = <&usb3_lpcg 1>, + <&usb3_lpcg 0>, + <&usb3_lpcg 5>, + <&usb3_lpcg 2>, + <&usb3_lpcg 3>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <125000000>, <12000000>, <250000000>; + power-domains = <&pd IMX_SC_R_USB_2>; + status = "disabled"; + + usbotg3_cdns3: usb@5b120000 { + compatible = "cdns,usb3"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + reg = <0x5B130000 0x10000>, /* memory area for HOST registers */ + <0x5B140000 0x10000>, /* memory area for DEVICE registers */ + <0x5B120000 0x10000>; /* memory area for OTG/DRD registers */ + reg-names = "xhci", "dev", "otg"; + phys = <&usb3_phy>; + phy-names = "cdns3,usb3-phy"; + cdns,on-chip-buff-size = /bits/ 16 <18>; + status = "disabled"; + }; + }; + /* LPCG clocks */ sdhc0_lpcg: clock-controller@5b200000 { compatible = "fsl,imx8qxp-lpcg"; @@ -116,8 +217,7 @@ #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; - clock-indices = , , - ; + bit-offset = <0 16 20>; clock-output-names = "sdhc0_lpcg_per_clk", "sdhc0_lpcg_ipg_clk", "sdhc0_lpcg_ahb_clk"; @@ -130,8 +230,7 @@ #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; - clock-indices = , , - ; + bit-offset = <0 16 20>; clock-output-names = "sdhc1_lpcg_per_clk", "sdhc1_lpcg_ipg_clk", "sdhc1_lpcg_ahb_clk"; @@ -144,8 +243,7 @@ #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; - clock-indices = , , - ; + bit-offset = <0 16 20>; clock-output-names = "sdhc2_lpcg_per_clk", "sdhc2_lpcg_ipg_clk", "sdhc2_lpcg_ahb_clk"; @@ -162,9 +260,7 @@ <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, <&conn_ipg_clk>, <&conn_ipg_clk>; - clock-indices = , , - , , - , ; + bit-offset = <0 4 8 12 16 20>; clock-output-names = "enet0_lpcg_timer_clk", "enet0_lpcg_txc_sampling_clk", "enet0_lpcg_ahb_clk", @@ -184,9 +280,7 @@ <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, <&conn_ipg_clk>, <&conn_ipg_clk>; - clock-indices = , , - , , - , ; + bit-offset = <0 4 8 12 16 20>; clock-output-names = "enet1_lpcg_timer_clk", "enet1_lpcg_txc_sampling_clk", "enet1_lpcg_ahb_clk", @@ -195,4 +289,98 @@ "enet1_lpcg_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_1>; }; + + usb2_lpcg: clock-controller@5b270000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b270000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; + bit-offset = <24 28>; + clock-output-names = "usboh3_ahb_clk", + "usboh3_phy_ipg_clk"; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + }; + + usb3_lpcg: clock-controller@5b280000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b280000 0x10000>; + #clock-cells = <1>; + bit-offset = <0 4 16 20 24 28>; + clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, + <&conn_ipg_clk>, + <&conn_ipg_clk>, + <&conn_ipg_clk>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; + clock-output-names = "usb3_app_clk", + "usb3_lpm_clk", + "usb3_ipg_clk", + "usb3_core_pclk", + "usb3_phy_clk", + "usb3_aclk"; + power-domains = <&pd IMX_SC_R_USB_2_PHY>; + }; + + rawnand_0_lpcg: clock-controller@5b290000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b290000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>, + <&conn_axi_clk>, + <&conn_axi_clk>; + bit-offset = <0 4 16 20>; + clock-output-names = "bch_clk", + "gpmi_clk", + "gpmi_apb_clk", + "bch_apb_clk"; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + rawnand_4_lpcg: clock-controller@5b290004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b290004 0x10000>; + #clock-cells = <1>; + clocks = <&conn_axi_clk>; + bit-offset = <16>; + clock-output-names = "apbhdma_hclk"; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + dma_apbh: dma-apbh@5b810000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x5b810000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&rawnand_4_lpcg 0>; + clock-names = "apbhdma_hclk"; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + gpmi: gpmi-nand@5b812000{ + compatible = "fsl,imx8qxp-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&rawnand_0_lpcg 1>, + <&rawnand_0_lpcg 2>, + <&rawnand_0_lpcg 0>, + <&rawnand_0_lpcg 3>; + clock-names = "gpmi_clk", "gpmi_apb_clk", + "bch_clk", "bch_apb_clk"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + power-domains = <&pd IMX_SC_R_NAND>; + assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <50000000>; + status = "disabled"; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,487 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019,2020 NXP + */ + +dc0_subsys: bus@56000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56000000 0x0 0x56000000 0x300000>; + + dc0_cfg_clk: clock-dc-cfg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "dc0_cfg_clk"; + }; + + dc0_axi_int_clk: clock-dc-axi-int { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "dc0_axi_int_clk"; + }; + + dc0_axi_ext_clk: clock-dc-axi-ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "dc0_axi_ext_clk"; + }; + + dc0_disp_lpcg: clock-controller@56010000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; + bit-offset = <0 4>; + clock-output-names = "dc0_disp0_lpcg_clk", "dc0_disp1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_dpr0_lpcg: clock-controller@56010018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010018 0x4>; + #clock-cells = <1>; + clocks = <&dc0_cfg_clk>, + <&dc0_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc0_dpr0_lpcg_apb_clk", + "dc0_dpr0_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_rtram0_lpcg: clock-controller@5601001c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5601001c 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc0_rtram0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + + dc0_prg0_lpcg: clock-controller@56010020 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010020 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg0_lpcg_rtram_clk", + "dc0_prg0_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg1_lpcg: clock-controller@56010024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010024 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg1_lpcg_rtram_clk", + "dc0_prg1_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg2_lpcg: clock-controller@56010028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010028 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg2_lpcg_rtram_clk", + "dc0_prg2_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_dpr1_lpcg: clock-controller@5601002c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5601002c 0x4>; + #clock-cells = <1>; + clocks = <&dc0_cfg_clk>, + <&dc0_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc0_dpr1_lpcg_apb_clk", + "dc0_dpr1_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_rtram1_lpcg: clock-controller@56010030 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010030 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc0_rtram1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg3_lpcg: clock-controller@56010034 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010034 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg3_lpcg_rtram_clk", + "dc0_prg3_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg4_lpcg: clock-controller@56010038 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010038 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg4_lpcg_rtram_clk", + "dc0_prg4_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg5_lpcg: clock-controller@5601003c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5601003c 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg5_lpcg_rtram_clk", + "dc0_prg5_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg6_lpcg: clock-controller@56010040 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010040 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg6_lpcg_rtram_clk", + "dc0_prg6_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg7_lpcg: clock-controller@56010044 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010044 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg7_lpcg_rtram_clk", + "dc0_prg7_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_prg8_lpcg: clock-controller@56010048 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010048 0x4>; + #clock-cells = <1>; + clocks = <&dc0_axi_ext_clk>, + <&dc0_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc0_prg8_lpcg_rtram_clk", + "dc0_prg8_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_irqsteer: irqsteer@56000000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56000000 0x10000>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&dc0_cfg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <512>; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + + dc0_pc: pixel-combiner@56020000 { + compatible = "fsl,imx8qxp-pixel-combiner", + "fsl,imx8qm-pixel-combiner"; + reg = <0x56020000 0x10000>; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg1: prg@56040000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56040000 0x10000>; + clocks = <&dc0_prg0_lpcg 0>, + <&dc0_prg0_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg2: prg@56050000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56050000 0x10000>; + clocks = <&dc0_prg1_lpcg 0>, + <&dc0_prg1_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg3: prg@56060000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56060000 0x10000>; + clocks = <&dc0_prg2_lpcg 0>, + <&dc0_prg2_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg4: prg@56070000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56070000 0x10000>; + clocks = <&dc0_prg3_lpcg 0>, + <&dc0_prg3_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg5: prg@56080000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56080000 0x10000>; + clocks = <&dc0_prg4_lpcg 0>, + <&dc0_prg4_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg6: prg@56090000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x56090000 0x10000>; + clocks = <&dc0_prg5_lpcg 0>, + <&dc0_prg5_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg7: prg@560a0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x560a0000 0x10000>; + clocks = <&dc0_prg6_lpcg 0>, + <&dc0_prg6_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg8: prg@560b0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x560b0000 0x10000>; + clocks = <&dc0_prg7_lpcg 0>, + <&dc0_prg7_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_prg9: prg@560c0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x560c0000 0x10000>; + clocks = <&dc0_prg8_lpcg 0>, + <&dc0_prg8_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr1_channel1: dpr-channel@560d0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x560d0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg1>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr1_channel2: dpr-channel@560e0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x560e0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg2>, <&dc0_prg1>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr1_channel3: dpr-channel@560f0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x560f0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg3>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr2_channel1: dpr-channel@56100000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x56100000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg4>, <&dc0_prg5>; + clocks = <&dc0_dpr1_lpcg 0>, + <&dc0_dpr1_lpcg 1>, + <&dc0_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr2_channel2: dpr-channel@56110000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x56110000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg6>, <&dc0_prg7>; + clocks = <&dc0_dpr1_lpcg 0>, + <&dc0_dpr1_lpcg 1>, + <&dc0_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dc0_dpr2_channel3: dpr-channel@56120000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x56120000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg8>, <&dc0_prg9>; + clocks = <&dc0_dpr1_lpcg 0>, + <&dc0_dpr1_lpcg 1>, + <&dc0_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; + status = "disabled"; + }; + + dpu1: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x56180000 0x40000>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <5>, + <0>, <1>, <2>, <3>, + <4>, <82>, <83>, <84>, + <85>, <209>, <210>, <211>, + <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "reserved", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>, + <&dc0_disp_lpcg 0>, <&dc0_disp_lpcg 1>; + clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg"; + power-domains = <&pd IMX_SC_R_DC_0>, + <&pd IMX_SC_R_DC_0_PLL_0>, + <&pd IMX_SC_R_DC_0_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, + <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, + <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, + <&dc0_dpr2_channel3>; + fsl,pixel-combiner = <&dc0_pc>; + status = "disabled"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019,2020 NXP + */ + +dc1_subsys: bus@57000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x57000000 0x0 0x57000000 0x300000>; + + dc1_cfg_clk: clock-dc-cfg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "dc1_cfg_clk"; + }; + + dc1_axi_int_clk: clock-dc-axi-int { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "dc1_axi_int_clk"; + }; + + dc1_axi_ext_clk: clock-dc-axi-ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "dc1_axi_ext_clk"; + }; + + dc1_disp_lpcg: clock-controller@57010000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>; + bit-offset = <0 4>; + clock-output-names = "dc1_disp0_lpcg_clk", "dc1_disp1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_dpr0_lpcg: clock-controller@57010018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010018 0x4>; + #clock-cells = <1>; + clocks = <&dc1_cfg_clk>, + <&dc1_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc1_dpr0_lpcg_apb_clk", + "dc1_dpr0_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_rtram0_lpcg: clock-controller@5701001c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5701001c 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc1_rtram0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + + dc1_prg0_lpcg: clock-controller@57010020 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010020 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg0_lpcg_rtram_clk", + "dc1_prg0_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg1_lpcg: clock-controller@57010024 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010024 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg1_lpcg_rtram_clk", + "dc1_prg1_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg2_lpcg: clock-controller@57010028 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010028 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg2_lpcg_rtram_clk", + "dc1_prg2_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_dpr1_lpcg: clock-controller@5701002c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5701002c 0x4>; + #clock-cells = <1>; + clocks = <&dc1_cfg_clk>, + <&dc1_axi_ext_clk>; + bit-offset = <16 20>; + clock-output-names = "dc1_dpr1_lpcg_apb_clk", + "dc1_dpr1_lpcg_b_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_rtram1_lpcg: clock-controller@57010030 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010030 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>; + bit-offset = <0>; + clock-output-names = "dc1_rtram1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg3_lpcg: clock-controller@57010034 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010034 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg3_lpcg_rtram_clk", + "dc1_prg3_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg4_lpcg: clock-controller@57010038 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010038 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg4_lpcg_rtram_clk", + "dc1_prg4_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg5_lpcg: clock-controller@5701003c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5701003c 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg5_lpcg_rtram_clk", + "dc1_prg5_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg6_lpcg: clock-controller@57010040 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010040 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg6_lpcg_rtram_clk", + "dc1_prg6_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg7_lpcg: clock-controller@57010044 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010044 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg7_lpcg_rtram_clk", + "dc1_prg7_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_prg8_lpcg: clock-controller@57010048 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010048 0x4>; + #clock-cells = <1>; + clocks = <&dc1_axi_ext_clk>, + <&dc1_cfg_clk>; + bit-offset = <0 16>; + clock-output-names = "dc1_prg8_lpcg_rtram_clk", + "dc1_prg8_lpcg_apb_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_irqsteer: irqsteer@57000000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x57000000 0x10000>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&dc1_cfg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <512>; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + + dc1_pc: pixel-combiner@57020000 { + compatible = "fsl,imx8qxp-pixel-combiner", + "fsl,imx8qm-pixel-combiner"; + reg = <0x57020000 0x10000>; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg1: prg@57040000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57040000 0x10000>; + clocks = <&dc1_prg0_lpcg 0>, + <&dc1_prg0_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg2: prg@57050000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57050000 0x10000>; + clocks = <&dc1_prg1_lpcg 0>, + <&dc1_prg1_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg3: prg@57060000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57060000 0x10000>; + clocks = <&dc1_prg2_lpcg 0>, + <&dc1_prg2_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg4: prg@57070000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57070000 0x10000>; + clocks = <&dc1_prg3_lpcg 0>, + <&dc1_prg3_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg5: prg@57080000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57080000 0x10000>; + clocks = <&dc1_prg4_lpcg 0>, + <&dc1_prg4_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg6: prg@57090000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x57090000 0x10000>; + clocks = <&dc1_prg5_lpcg 0>, + <&dc1_prg5_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg7: prg@570a0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x570a0000 0x10000>; + clocks = <&dc1_prg6_lpcg 0>, + <&dc1_prg6_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg8: prg@570b0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x570b0000 0x10000>; + clocks = <&dc1_prg7_lpcg 0>, + <&dc1_prg7_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_prg9: prg@570c0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x570c0000 0x10000>; + clocks = <&dc1_prg8_lpcg 0>, + <&dc1_prg8_lpcg 1>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr1_channel1: dpr-channel@570d0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x570d0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg1>; + clocks = <&dc1_dpr0_lpcg 0>, + <&dc1_dpr0_lpcg 1>, + <&dc1_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr1_channel2: dpr-channel@570e0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x570e0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg2>, <&dc1_prg1>; + clocks = <&dc1_dpr0_lpcg 0>, + <&dc1_dpr0_lpcg 1>, + <&dc1_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr1_channel3: dpr-channel@570f0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x570f0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg3>; + clocks = <&dc1_dpr0_lpcg 0>, + <&dc1_dpr0_lpcg 1>, + <&dc1_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel1: dpr-channel@57100000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57100000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg4>, <&dc1_prg5>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel2: dpr-channel@57110000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57110000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg6>, <&dc1_prg7>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel3: dpr-channel@57120000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57120000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc1_prg8>, <&dc1_prg9>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dpu2: dpu@57180000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x57180000 0x40000>; + interrupt-parent = <&dc1_irqsteer>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <5>, + <0>, <1>, <2>, <3>, + <4>, <82>, <83>, <84>, + <85>, <209>, <210>, <211>, + <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "reserved", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_1_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>, + <&dc1_disp_lpcg 0>, <&dc1_disp_lpcg 1>; + clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg"; + power-domains = <&pd IMX_SC_R_DC_1>, + <&pd IMX_SC_R_DC_1_PLL_0>, + <&pd IMX_SC_R_DC_1_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc1_dpr1_channel1>, + <&dc1_dpr1_channel2>, + <&dc1_dpr1_channel3>, + <&dc1_dpr2_channel1>, + <&dc1_dpr2_channel2>, + <&dc1_dpr2_channel3>; + fsl,pixel-combiner = <&dc1_pc>; + status = "disabled"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -11,7 +11,7 @@ ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; ddr_pmu0: ddr-pmu@5c020000 { - compatible = "fsl,imx8-ddr-pmu"; + compatible = "fsl,imx8qxp-ddr-pmu", "fsl,imx8-ddr-pmu"; reg = <0x5c020000 0x10000>; interrupts = ; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -22,9 +22,8 @@ lpuart0: serial@5a060000 { reg = <0x5a060000 0x1000>; - interrupts = ; - clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, - <&uart0_lpcg IMX_LPCG_CLK_0>; + interrupts = ; + clocks = <&uart0_lpcg 1>, <&uart0_lpcg 0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; @@ -34,47 +33,119 @@ lpuart1: serial@5a070000 { reg = <0x5a070000 0x1000>; - interrupts = ; - clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, - <&uart1_lpcg IMX_LPCG_CLK_0>; + interrupts = ; + clocks = <&uart1_lpcg 1>, <&uart1_lpcg 0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_1>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 11 0 0>, + <&edma2 10 0 1>; status = "disabled"; }; lpuart2: serial@5a080000 { reg = <0x5a080000 0x1000>; - interrupts = ; - clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, - <&uart2_lpcg IMX_LPCG_CLK_0>; + interrupts = ; + clocks = <&uart2_lpcg 1>, <&uart2_lpcg 0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_2>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 13 0 0>, + <&edma2 12 0 1>; status = "disabled"; }; lpuart3: serial@5a090000 { reg = <0x5a090000 0x1000>; - interrupts = ; - clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, - <&uart3_lpcg IMX_LPCG_CLK_0>; + interrupts = ; + clocks = <&uart3_lpcg 1>, <&uart3_lpcg 0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_3>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 15 0 0>, + <&edma2 14 0 1>; status = "disabled"; }; + emvsim0: sim0@5a0d0000 { + compatible = "fsl,imx8-emvsim"; + reg = <0x5a0d0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&emvsim0_lpcg 0>, + <&emvsim0_lpcg 1>; + clock-names = "sim", "ipg"; + assigned-clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_EMVSIM_0>, <&pd IMX_SC_R_BOARD_R2>; + power-domain-names = "sim_pd", "sim_aux_pd"; + status = "disabled"; + }; + + spi0_lpcg: clock-controller@5a400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a400000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi0_lpcg_clk", + "spi0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_0>; + }; + + spi1_lpcg: clock-controller@5a410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a410000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi1_lpcg_clk", + "spi1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_1>; + }; + + spi2_lpcg: clock-controller@5a420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a420000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi2_lpcg_clk", + "spi2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_2>; + }; + + spi3_lpcg: clock-controller@5a430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a430000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi3_lpcg_clk", + "spi3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_3>; + }; + uart0_lpcg: clock-controller@5a460000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a460000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; - clock-indices = , ; + bit-offset = <0 16>; clock-output-names = "uart0_lpcg_baud_clk", "uart0_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_UART_0>; @@ -86,7 +157,7 @@ #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; - clock-indices = , ; + bit-offset = <0 16>; clock-output-names = "uart1_lpcg_baud_clk", "uart1_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_UART_1>; @@ -98,7 +169,7 @@ #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; - clock-indices = , ; + bit-offset = <0 16>; clock-output-names = "uart2_lpcg_baud_clk", "uart2_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_UART_2>; @@ -110,17 +181,58 @@ #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; - clock-indices = , ; + bit-offset = <0 16>; clock-output-names = "uart3_lpcg_baud_clk", "uart3_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_UART_3>; }; + emvsim0_lpcg: clock-controller@5a4d0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a4d0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "emvsim0_lpcg_clk", + "emvsim0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_EMVSIM_0>; + }; + + adc0: adc@5a880000 { + compatible = "nxp,imx8qxp-adc"; + reg = <0x5a880000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adc0_lpcg 0>, + <&adc0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_0>; + status = "disabled"; + }; + + adc1: adc@5a890000 { + compatible = "fsl,imx8qxp-adc"; + reg = <0x5a890000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adc1_lpcg 0>, + <&adc1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_1>; + status = "disabled"; + }; + + i2c0: i2c@5a800000 { reg = <0x5a800000 0x4000>; - interrupts = ; - clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>, - <&i2c0_lpcg IMX_LPCG_CLK_4>; + interrupts = ; + clocks = <&i2c0_lpcg 0>, + <&i2c0_lpcg 1>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -130,9 +242,9 @@ i2c1: i2c@5a810000 { reg = <0x5a810000 0x4000>; - interrupts = ; - clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>, - <&i2c1_lpcg IMX_LPCG_CLK_4>; + interrupts = ; + clocks = <&i2c1_lpcg 0>, + <&i2c1_lpcg 1>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -142,9 +254,9 @@ i2c2: i2c@5a820000 { reg = <0x5a820000 0x4000>; - interrupts = ; - clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>, - <&i2c2_lpcg IMX_LPCG_CLK_4>; + interrupts = ; + clocks = <&i2c2_lpcg 0>, + <&i2c2_lpcg 1>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -154,9 +266,9 @@ i2c3: i2c@5a830000 { reg = <0x5a830000 0x4000>; - interrupts = ; - clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>, - <&i2c3_lpcg IMX_LPCG_CLK_4>; + interrupts = ; + clocks = <&i2c3_lpcg 0>, + <&i2c3_lpcg 1>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -170,7 +282,7 @@ #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; - clock-indices = , ; + bit-offset = <0 16>; clock-output-names = "i2c0_lpcg_clk", "i2c0_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_I2C_0>; @@ -182,7 +294,7 @@ #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; - clock-indices = , ; + bit-offset = <0 16>; clock-output-names = "i2c1_lpcg_clk", "i2c1_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_I2C_1>; @@ -194,7 +306,7 @@ #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; - clock-indices = , ; + bit-offset = <0 16>; clock-output-names = "i2c2_lpcg_clk", "i2c2_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_I2C_2>; @@ -206,9 +318,347 @@ #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; - clock-indices = , ; + bit-offset = <0 16>; clock-output-names = "i2c3_lpcg_clk", "i2c3_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_I2C_3>; }; + + edma2: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a1f0000 0x10000>, + <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ + <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ + <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */ + <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */ + <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */ + <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */ + <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ + <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ + <0x5a280000 0x10000>, /* channel8 UART0 rx */ + <0x5a290000 0x10000>, /* channel9 UART0 tx */ + <0x5a2a0000 0x10000>, /* channel10 UART1 rx */ + <0x5a2b0000 0x10000>, /* channel11 UART1 tx */ + <0x5a2c0000 0x10000>, /* channel12 UART2 rx */ + <0x5a2d0000 0x10000>, /* channel13 UART2 tx */ + <0x5a2e0000 0x10000>, /* channel14 UART3 rx */ + <0x5a2f0000 0x10000>; /* channel15 UART3 tx */ + #dma-cells = <3>; + dma-channels = <16>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma2-chan0-rx", "edma2-chan1-tx", + "edma2-chan2-rx", "edma2-chan3-tx", + "edma2-chan4-rx", "edma2-chan5-tx", + "edma2-chan6-rx", "edma2-chan7-tx", + "edma2-chan8-rx", "edma2-chan9-tx", + "edma2-chan10-rx", "edma2-chan11-tx", + "edma2-chan12-rx", "edma2-chan13-tx", + "edma2-chan14-rx", "edma2-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>; + power-domain-names = "edma2-chan0", "edma2-chan1", + "edma2-chan2", "edma2-chan3", + "edma2-chan4", "edma2-chan5", + "edma2-chan6", "edma2-chan7", + "edma2-chan8", "edma2-chan9", + "edma2-chan10", "edma2-chan11", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15"; + status = "disabled"; + }; + + edma3: dma-controller@5a9f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a9f0000 0x10000>, + <0x5aa00000 0x10000>, /* channel0 LPI2C0 rx */ + <0x5aa10000 0x10000>, /* channel1 LPI2C0 tx */ + <0x5aa20000 0x10000>, /* channel2 LPI2C1 rx */ + <0x5aa30000 0x10000>, /* channel3 LPI2C1 tx */ + <0x5aa40000 0x10000>, /* channel4 LPI2C2 rx */ + <0x5aa50000 0x10000>, /* channel5 LPI2C2 tx */ + <0x5aa60000 0x10000>, /* channel6 LPI2C3 rx */ + <0x5aa70000 0x10000>; /* channel7 LPI2C3 tx */ + #dma-cells = <3>; + dma-channels = <8>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "edma3-chan0-rx", "edma3-chan1-tx", + "edma3-chan2-rx", "edma3-chan3-tx", + "edma3-chan4-rx", "edma3-chan5-tx", + "edma3-chan6-rx", "edma3-chan7-tx"; + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, + <&pd IMX_SC_R_DMA_3_CH1>, + <&pd IMX_SC_R_DMA_3_CH2>, + <&pd IMX_SC_R_DMA_3_CH3>, + <&pd IMX_SC_R_DMA_3_CH4>, + <&pd IMX_SC_R_DMA_3_CH5>, + <&pd IMX_SC_R_DMA_3_CH6>, + <&pd IMX_SC_R_DMA_3_CH7>; + power-domain-names = "edma3-chan0", "edma3-chan1", + "edma3-chan2", "edma3-chan3", + "edma3-chan4", "edma3-chan5", + "edma3-chan6", "edma3-chan7"; + status = "disabled"; + }; + + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x5a8d0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_0>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x5a8e0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN1 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_1>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <1>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x5a8f0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN2 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_2>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <2>; + status = "disabled"; + }; + + adc0_lpcg: clock-controller@5ac80000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac80000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "adc0_lpcg_clk", + "adc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_0>; + }; + + adc1_lpcg: clock-controller@5ac90000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac90000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "adc1_lpcg_clk", + "adc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_1>; + }; + + lpspi0: spi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi0_lpcg 0>, + <&spi0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <20000000>; + power-domains = <&pd IMX_SC_R_SPI_0>; + dma-names = "tx","rx"; + dmas = <&edma2 1 0 0>, <&edma2 0 0 1>; + status = "disabled"; + }; + + lpspi1: spi@5a010000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a010000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi1_lpcg 0>, + <&spi1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_1>; + dma-names = "tx","rx"; + dmas = <&edma2 3 0 0>, <&edma2 2 0 1>; + status = "disabled"; + }; + + lpspi2: spi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a020000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi2_lpcg 0>, + <&spi2_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_2>; + dma-names = "tx","rx"; + dmas = <&edma2 5 0 0>, <&edma2 4 0 1>; + status = "disabled"; + }; + + lpspi3: spi@5a030000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a030000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi3_lpcg 0>, + <&spi3_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_3>; + dma-names = "tx","rx"; + dmas = <&edma2 7 0 0>, <&edma2 6 0 1>; + status = "disabled"; + }; + + can0_lpcg: clock-controller@5acd0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acd0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + bit-offset = <0 16 20>; + clock-output-names = "can0_lpcg_pe_clk", + "can0_lpcg_ipg_clk", + "can0_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_0>; + }; + + i2c_rpbus_0: i2c-rpbus-0 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_1: i2c-rpbus-1 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_5: i2c-rpbus-5 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_12: i2c-rpbus-12 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_13: i2c-rpbus-13 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_14: i2c-rpbus-14 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_15: i2c-rpbus-15 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + adma_pwm: pwm@5a190000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x5a190000 0x1000>; + clocks = <&adma_pwm_lpcg 0>, <&adma_pwm_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; + }; + + adma_pwm_lpcg: clock-controller@5a590000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a590000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "adma_pwm_lpcg_clk", + "adma_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +gpu0_subsys: bus@53100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x53100000 0x0 0x53100000 0x40000>, + <0x80000000 0x0 0x80000000 0x80000000>, + <0x0 0x0 0x0 0x10000000>; + + gpu_3d0: gpu@53100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x53100000 0x40000>; + interrupts = ; + clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <700000000>, <850000000>; + power-domains = <&pd IMX_SC_R_GPU_0_PID0>; + status = "disabled"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +gpu1_subsys: bus@54100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x54100000 0x0 0x54100000 0x40000>, + <0x80000000 0x0 0x80000000 0x80000000>, + <0x0 0x0 0x0 0x10000000>; + + gpu_3d1: gpu@54100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x54100000 0x40000>; + interrupts = ; + clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <800000000>, <1000000000>; + fsl,sc_gpu_pid = ; + power-domains = <&pd IMX_SC_R_GPU_1_PID0>; + status = "disabled"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Richard Zhu + */ +#include + +hsio_subsys: bus@5f000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + /* Only supports up to 32bits DMA, map all possible DDR as inbound ranges */ + dma-ranges = <0x80000000 0 0x80000000 0x80000000>; + ranges = <0x5f000000 0x0 0x5f000000 0x21000000>; + + xtal100m: clock-xtal100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "xtal_100MHz"; + }; + + hsio_refa_clk: clock-hsio-refa { + compatible = "gpio-gate-clock"; + clocks = <&xtal100m>; + #clock-cells = <0>; + enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; + }; + + hsio_refb_clk: clock-hsio-refb { + compatible = "gpio-gate-clock"; + clocks = <&xtal100m>; + #clock-cells = <0>; + enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + }; + + hsio_axi_clk: clock-hsio-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "hsio_axi_clk"; + }; + + hsio_per_clk: clock-hsio-per { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + clock-output-names = "hsio_per_clk"; + }; + + pcieb_lpcg: clock-controller@5f060000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f060000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; + bit-offset = <16 20 24>; + clock-output-names = "hsio_pcieb_mstr_axi_clk", + "hsio_pcieb_slv_axi_clk", + "hsio_pcieb_dbi_axi_clk"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + }; + + phyx1_crr1_lpcg: clock-controller@5f0b0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0b0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_phyx1_per_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; + + pcieb_crr3_lpcg: clock-controller@5f0d0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0d0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_pcieb_per_clk"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + }; + + misc_crr5_lpcg: clock-controller@5f0f0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0f0000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_per_clk>; + bit-offset = <16>; + clock-output-names = "hsio_misc_per_clk"; + power-domains = <&pd IMX_SC_R_HSIO_GPIO>; + }; + + phyx1_csr: csr@5f120000 { + compatible = "syscon"; + reg = <0x5f120000 0x8>; + }; + + pcieb_csr: csr@5f140000 { + compatible = "syscon"; + reg = <0x5f140000 0x18>; + }; + + misc_csr: csr@5f160000 { + compatible = "syscon"; + reg = <0x5f160000 0x8>; + }; + + phyx1: pcie-phy@5f1a0000 { + compatible = "fsl,imx8qm-pcie-phy"; + reg = <0x5f1a0000 0x10000>; + ctrl-csr = <&pcieb_csr>; + phy-csr = <&phyx1_csr>; + misc-csr = <&misc_csr>; + clocks = <&phyx1_lpcg 3>, <&phyx1_lpcg 0>, <&pcieb_crr3_lpcg 0>, + <&phyx1_crr1_lpcg 0>, <&misc_crr5_lpcg 0>; + clock-names = "apb_pclk", "pipe_pclk", "ctrl_ips_clk", + "phy_ips_clk", "misc_ips_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + #phy-cells = <0>; + hsio-cfg = ; + status = "disabled"; + }; + + pcieb: pcie@5f010000 { + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + reg = <0x5f010000 0x10000>, /* Controller reg */ + <0x7ff00000 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + local-addr = <0x80000000>; + ctrl-csr = <&pcieb_csr>; + phys = <&phyx1>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcieb_ep: pcie_ep@5f010000 { + compatible = "fsl,imx8qxp-pcie-ep"; + reg = <0x5f010000 0x00010000>, + <0x70000000 0x10000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + local-addr = <0x80000000>; + ctrl-csr = <&pcieb_csr>; + phys = <&phyx1>; + phy-names = "pcie-phy"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -4,10 +4,11 @@ * Zhou Guoniu */ img_subsys: bus@58000000 { - compatible = "simple-bus"; + compatible = "simple-pm-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x58000000 0x0 0x58000000 0x1000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>; img_ipg_clk: clock-img-ipg { compatible = "fixed-clock"; @@ -16,65 +17,589 @@ clock-output-names = "img_ipg_clk"; }; - jpegdec: jpegdec@58400000 { - reg = <0x58400000 0x00050000>; - interrupts = , - , - , - ; - clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, - <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; - clock-names = "per", "ipg"; - assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, - <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; - assigned-clock-rates = <200000000>, <200000000>; - power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>, - <&pd IMX_SC_R_MJPEG_DEC_S0>, - <&pd IMX_SC_R_MJPEG_DEC_S1>, - <&pd IMX_SC_R_MJPEG_DEC_S2>, - <&pd IMX_SC_R_MJPEG_DEC_S3>; - }; - - jpegenc: jpegenc@58450000 { - reg = <0x58450000 0x00050000>; - interrupts = , - , - , - ; - clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, - <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; - clock-names = "per", "ipg"; - assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, - <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; - assigned-clock-rates = <200000000>, <200000000>; - power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>, - <&pd IMX_SC_R_MJPEG_ENC_S0>, - <&pd IMX_SC_R_MJPEG_ENC_S1>, - <&pd IMX_SC_R_MJPEG_ENC_S2>, - <&pd IMX_SC_R_MJPEG_ENC_S3>; + img_axi_clk: clock-img-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "img_axi_clk"; + }; + + img_pxl_clk: clock-img-pxl { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + clock-output-names = "img_pxl_clk"; + }; + + csi0_core_lpcg: clock-controller@58223018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58223018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>; + bit-offset = <16>; + clock-output-names = "csi0_lpcg_core_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + csi0_esc_lpcg: clock-controller@5822301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5822301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>; + bit-offset = <16>; + clock-output-names = "csi0_lpcg_esc_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + csi1_core_lpcg: clock-controller@58243018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58243018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>; + bit-offset = <16>; + clock-output-names = "csi1_lpcg_core_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + csi1_esc_lpcg: clock-controller@5824301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5824301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>; + bit-offset = <16>; + clock-output-names = "csi1_lpcg_esc_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pi0_pxl_lpcg: clock-controller@58263018 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263018 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; + bit-offset = <0>; + clock-output-names = "pi0_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pi0_ipg_lpcg: clock-controller@58263004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58263004 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; + bit-offset = <16>; + clock-output-names = "pi0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pi0_misc_lpcg: clock-controller@5826301c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5826301c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>; + bit-offset = <0>; + clock-output-names = "pi0_lpcg_misc_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pdma0_lpcg: clock-controller@58500000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58500000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + }; + + pdma1_lpcg: clock-controller@58510000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58510000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH1>; }; - img_jpeg_dec_lpcg: clock-controller@585d0000 { + pdma2_lpcg: clock-controller@58520000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58520000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma2_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH2>; + }; + + pdma3_lpcg: clock-controller@58530000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58530000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma3_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH3>; + }; + + pdma4_lpcg: clock-controller@58540000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58540000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma4_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH4>; + }; + + pdma5_lpcg: clock-controller@58550000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58550000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma5_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH5>; + }; + + pdma6_lpcg: clock-controller@58560000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58560000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma6_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH6>; + }; + + pdma7_lpcg: clock-controller@58570000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58570000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "pdma7_lpcg_clk"; + power-domains = <&pd IMX_SC_R_ISI_CH7>; + }; + + csi0_pxl_lpcg: clock-controller@58580000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58580000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "csi0_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_CSI_0>; + }; + + csi1_pxl_lpcg: clock-controller@58590000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x58590000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "csi1_lpcg_pxl_clk"; + power-domains = <&pd IMX_SC_R_CSI_1>; + }; + + hdmi_rx_pxl_link_lpcg: clock-controller@585a0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x585a0000 0x10000>; + #clock-cells = <1>; + clocks = <&img_pxl_clk>; + bit-offset = <0>; + clock-output-names = "hdmi_rx_lpcg_pxl_link_clk"; + power-domains = <&pd IMX_SC_R_HDMI_RX>; + }; + + img_jpeg_dec_clk: clock-controller@585d0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x585d0000 0x10000>; #clock-cells = <1>; clocks = <&img_ipg_clk>, <&img_ipg_clk>; - clock-indices = , - ; - clock-output-names = "img_jpeg_dec_lpcg_clk", - "img_jpeg_dec_lpcg_ipg_clk"; + bit-offset = <0 16>; + clock-output-names = "img_jpeg_dec_clk", + "img_jpeg_dec_ipg_clk"; power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>; }; - img_jpeg_enc_lpcg: clock-controller@585f0000 { + img_jpeg_enc_clk: clock-controller@585f0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x585f0000 0x10000>; #clock-cells = <1>; clocks = <&img_ipg_clk>, <&img_ipg_clk>; - clock-indices = , - ; - clock-output-names = "img_jpeg_enc_lpcg_clk", - "img_jpeg_enc_lpcg_ipg_clk"; + bit-offset = <0 16>; + clock-output-names = "img_jpeg_enc_clk", + "img_jpeg_enc_ipg_clk"; power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>; }; + + irqsteer_csi0: irqsteer@58220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58220000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&img_ipg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + power-domains = <&pd IMX_SC_R_CSI_0>; + power-domain-names = "pd_csi"; + status = "disabled"; + }; + + irqsteer_csi1: irqsteer@58240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58240000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&img_ipg_clk>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + power-domains = <&pd IMX_SC_R_CSI_1>; + power-domain-names = "pd_csi"; + status = "disabled"; + }; + + irqsteer_parallel: irqsteer@58260000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58260000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&clk_dummy>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + power-domains = <&pd IMX_SC_R_PI_0>; + power-domain-names = "pd_pi"; + status = "disabled"; + }; + + gpio0_mipi_csi0: gpio@58222000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x58222000 0x1000>; + interrupts = <0>; + interrupt-parent = <&irqsteer_csi0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_CSI_0>; + power-domain-names = "pd_csi"; + }; + + i2c_mipi_csi0: i2c@58226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x58226000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_csi0>; + clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>; + status = "disabled"; + }; + + i2c0_parallel: i2c@58266000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x58266000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_parallel>; + clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_PI_0_I2C_0>; + status = "disabled"; + }; + + gpio0_mipi_csi1: gpio@58242000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x58242000 0x1000>; + interrupts = <0>; + interrupt-parent = <&irqsteer_csi1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_CSI_1>; + power-domain-names = "pd_csi"; + }; + + i2c_mipi_csi1: i2c@58246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x58246000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_csi1>; + clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>; + status = "disabled"; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x58100000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma0_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + interface = <2 0 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + + m2m_device{ + compatible = "imx-isi-m2m"; + status = "disabled"; + }; + }; + + isi_1: isi@58110000 { + compatible = "fsl,imx8-isi"; + reg = <0x58110000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma1_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH1>; + interface = <2 1 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_2: isi@58120000 { + compatible = "fsl,imx8-isi"; + reg = <0x58120000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma2_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH2>; + interface = <2 2 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_3: isi@58130000 { + compatible = "fsl,imx8-isi"; + reg = <0x58130000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma3_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH3>; + interface = <2 3 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_4: isi@58140000 { + compatible = "fsl,imx8-isi"; + reg = <0x58140000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma4_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH4>; + interface = <3 0 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_5: isi@58150000 { + compatible = "fsl,imx8-isi"; + reg = <0x58150000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma5_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH5>; + interface = <3 1 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_6: isi@58160000 { + compatible = "fsl,imx8-isi"; + reg = <0x58160000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma6_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH6>; + interface = <3 2 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_7: isi@58170000 { + compatible = "fsl,imx8-isi"; + reg = <0x58170000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&pdma7_lpcg 0>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH7>; + interface = <3 3 2>; + no-reset-control; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi_0: csi@58227000 { + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x58227000 0x1000>, + <0x58221000 0x1000>; + clocks = <&csi0_core_lpcg 0>, + <&csi0_esc_lpcg 0>, + <&csi0_pxl_lpcg 0>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&csi0_core_lpcg 0>, + <&csi0_esc_lpcg 0>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "disabled"; + }; + + mipi_csi_1: csi@58247000{ + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x58247000 0x1000>, + <0x58241000 0x1000>; + clocks = <&csi1_core_lpcg 0>, + <&csi1_esc_lpcg 0>, + <&csi1_pxl_lpcg 0>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&csi1_core_lpcg 0>, + <&csi1_esc_lpcg 0>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "disabled"; + }; + + parallel_csi: pcsi@58261000 { + compatible = "fsl,mxc-parallel-csi"; + reg = <0x58261000 0x1000>; + clocks = <&pi0_pxl_lpcg 0>, + <&pi0_ipg_lpcg 0>, + <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>; + clock-names = "pixel", "ipg", "div", "dpll"; + assigned-clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; + assigned-clock-parents = <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>; + assigned-clock-rates = <160000000>; /* 160MHz */ + power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_pi", "pd_isi_ch0"; + status = "disabled"; + }; + + jpegdec: jpegdec@58400000 { + compatible = "fsl,imx8-jpgdec"; + reg = <0x58400000 0x00050000 >; + interrupts = , + , + , + ; + clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_DEC_MP>, + <&pd IMX_SC_R_MJPEG_DEC_S0>, + <&pd IMX_SC_R_MJPEG_DEC_S1>, + <&pd IMX_SC_R_MJPEG_DEC_S2>, + <&pd IMX_SC_R_MJPEG_DEC_S3>; + power-domain-names = "pd_isi_ch0", "pd_dec_mp", + "pd_dec_s0", "pd_dec_s1", + "pd_dec_s2", "pd_dec_s3"; + status = "disabled"; + }; + + jpegenc: jpegenc@58450000 { + compatible = "fsl,imx8-jpgenc"; + reg = <0x58450000 0x00050000 >; + interrupts = , + , + , + ; + clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_ENC_MP>, + <&pd IMX_SC_R_MJPEG_ENC_S0>, + <&pd IMX_SC_R_MJPEG_ENC_S1>, + <&pd IMX_SC_R_MJPEG_ENC_S2>, + <&pd IMX_SC_R_MJPEG_ENC_S3>; + power-domain-names = "pd_isi_ch0", "pd_enc_mp", + "pd_enc_s0", "pd_enc_s1", + "pd_enc_s2", "pd_enc_s3"; + status = "disabled"; + }; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +lcdif_subsys: bus@5a180000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a180000 0x0 0x5a180000 0x500000>; + + ipg_dma_clk: clock-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "ipg_dma_clk"; + }; + + lcd_clk_lpcg: clock-controller@5a580000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a580000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, + <&ipg_dma_clk>; + bit-offset = <0 16>; + clock-output-names = "lcd_clk_lpcg", "lcd_ipg_clk"; + power-domains = <&pd IMX_SC_R_LCD_0>; + }; + + adma_lcdif: lcdif@5a180000 { + compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif"; + reg = <0x5a180000 0x10000>; + clocks = <&lcd_clk_lpcg 0>, + <&lcd_clk_lpcg 1>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>; + assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + assigned-clock-rates = <0>, <24000000>, <804000000>; + interrupts = ; + power-domains = <&pd IMX_SC_R_LCD_0>; + status = "disabled"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -11,7 +11,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, + <0x08000000 0x0 0x08000000 0x10000000>; lsio_mem_clk: clock-lsio-mem { compatible = "fixed-clock"; @@ -107,6 +108,20 @@ power-domains = <&pd IMX_SC_R_GPIO_7>; }; + flexspi0: spi@5d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8qxp-fspi"; + reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; + clock-names = "fspi", "fspi_en"; + power-domains = <&pd IMX_SC_R_FSPI_0>; + status = "disabled"; + }; + lsio_mu0: mailbox@5d1b0000 { reg = <0x5d1b0000 0x10000>; interrupts = ; @@ -158,10 +173,12 @@ }; lsio_mu13: mailbox@5d280000 { + compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu"; reg = <0x5d280000 0x10000>; interrupts = ; #mbox-cells = <2>; power-domains = <&pd IMX_SC_R_MU_13A>; + fsl,dsp_ap_mu_id = <13>; }; /* LPCG clocks */ @@ -174,9 +191,7 @@ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; - clock-indices = , , - , , - ; + bit-offset = <0 4 16 20 24>; clock-output-names = "pwm0_lpcg_ipg_clk", "pwm0_lpcg_ipg_hf_clk", "pwm0_lpcg_ipg_s_clk", @@ -194,9 +209,7 @@ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; - clock-indices = , , - , , - ; + bit-offset = <0 4 16 20 24>; clock-output-names = "pwm1_lpcg_ipg_clk", "pwm1_lpcg_ipg_hf_clk", "pwm1_lpcg_ipg_s_clk", @@ -214,9 +227,7 @@ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; - clock-indices = , , - , , - ; + bit-offset = <0 4 16 20 24>; clock-output-names = "pwm2_lpcg_ipg_clk", "pwm2_lpcg_ipg_hf_clk", "pwm2_lpcg_ipg_s_clk", @@ -234,9 +245,7 @@ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; - clock-indices = , , - , , - ; + bit-offset = <0 4 16 20 24>; clock-output-names = "pwm3_lpcg_ipg_clk", "pwm3_lpcg_ipg_hf_clk", "pwm3_lpcg_ipg_s_clk", @@ -254,9 +263,7 @@ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; - clock-indices = , , - , , - ; + bit-offset = <0 4 16 20 24>; clock-output-names = "pwm4_lpcg_ipg_clk", "pwm4_lpcg_ipg_hf_clk", "pwm4_lpcg_ipg_s_clk", @@ -274,9 +281,7 @@ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; - clock-indices = , , - , , - ; + bit-offset = <0 4 16 20 24>; clock-output-names = "pwm5_lpcg_ipg_clk", "pwm5_lpcg_ipg_hf_clk", "pwm5_lpcg_ipg_s_clk", @@ -294,9 +299,7 @@ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; - clock-indices = , , - , , - ; + bit-offset = <0 4 16 20 24>; clock-output-names = "pwm6_lpcg_ipg_clk", "pwm6_lpcg_ipg_hf_clk", "pwm6_lpcg_ipg_s_clk", @@ -314,9 +317,7 @@ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; - clock-indices = , , - , , - ; + bit-offset = <0 4 16 20 24>; clock-output-names = "pwm7_lpcg_ipg_clk", "pwm7_lpcg_ipg_hf_clk", "pwm7_lpcg_ipg_s_clk", diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include + +security_subsys: bus@31400000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x31400000 0x0 0x31400000 0x410000>; + + crypto: crypto@31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0x31400000 0x90000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x31400000 0x90000>; + fsl,sec-era = <9>; + power-domains = <&pd IMX_SC_R_CAAM_JR2>; + power-domain-names = "jr"; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + power-domains = <&pd IMX_SC_R_CAAM_JR2>; + power-domain-names = "jr"; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + power-domains = <&pd IMX_SC_R_CAAM_JR3>; + power-domain-names = "jr"; + }; + }; + + caam_sm: caam-sm@31800000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x31800000 0x10000>; + }; + + sec_mu2: mu@31560000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31560000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_2>; + status = "okay"; + }; + + sec_mu3: mu@31570000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31570000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_3>; + status = "okay"; + }; + + sec_mu4: mu@31580000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31580000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_4>; + status = "okay"; + }; +}; + +seco_mu1: seco_mu1 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&sec_mu2 2 0 + &sec_mu2 3 0>; + + fsl,seco_mu_id = <1>; + fsl,seco_max_users = <4>; + status = "okay"; +}; + +seco_mu2: seco_mu2 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&sec_mu3 2 0 + &sec_mu3 3 0>; + + fsl,seco_mu_id = <2>; + fsl,seco_max_users = <4>; + status = "okay"; +}; + +seco_mu3: seco_mu3 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&sec_mu4 2 0 + &sec_mu4 3 0>; + + fsl,seco_mu_id = <3>; + fsl,seco_max_users = <4>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-v2x.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include + +v2x_subsys: bus@2C000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x50000>; + + v2x_sv0: mu@2C000000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c000000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_0>; + status = "okay"; + }; + v2x_sv1: mu@2c010000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c010000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_1>; + status = "okay"; + }; + v2x_she: mu@2c020000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c020000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_2>; + status = "okay"; + }; + v2x_sg0: mu@2c030000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c030000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_3>; + status = "okay"; + }; + v2x_sg1: mu@2c040000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x2c040000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_V2X_MU_4>; + status = "okay"; + }; +}; + +v2x_mu_sv0: v2x_mu_sv0 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sv0 2 0 + &v2x_sv0 3 0>; + + fsl,seco_mu_id = <4>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x18>; + fsl,rsp_tag = /bits/ 8 <0xe2>; + status = "okay"; +}; +v2x_mu_sv1: v2x_mu_sv1 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sv1 2 0 + &v2x_sv1 3 0>; + + fsl,seco_mu_id = <5>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x19>; + fsl,rsp_tag = /bits/ 8 <0xe3>; + status = "okay"; +}; +v2x_mu_she: v2x_mu_she { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_she 2 0 + &v2x_she 3 0>; + + fsl,seco_mu_id = <6>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x1a>; + fsl,rsp_tag = /bits/ 8 <0xe4>; + status = "okay"; +}; +v2x_mu_sg0: v2x_mu_sg0 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sg0 2 0 + &v2x_sg0 3 0>; + + fsl,seco_mu_id = <7>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x1d>; + fsl,rsp_tag = /bits/ 8 <0xe7>; + status = "okay"; +}; +v2x_mu_sg1: v2x_mu_sg1 { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&v2x_sg1 2 0 + &v2x_sg1 3 0>; + + fsl,seco_mu_id = <8>; + fsl,seco_max_users = <2>; + fsl,cmd_tag = /bits/ 8 <0x1e>; + fsl,rsp_tag = /bits/ 8 <0xe8>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi 2024-06-19 12:33:58.276192156 +0200 @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2021 NXP + * Copyright 2018 NXP * Dong Aisheng */ @@ -12,13 +12,20 @@ power-domains = <&pd IMX_SC_R_VPU>; status = "disabled"; + vpu_lpcg: clock-controller@2c000000 { + compatible = "fsl,imx8qxp-lpcg-vpu"; + reg = <0x2c000000 0x2000000>; + #clock-cells = <1>; + status = "disabled"; + }; + mu_m0: mailbox@2d000000 { compatible = "fsl,imx6sx-mu"; reg = <0x2d000000 0x20000>; interrupts = ; #mbox-cells = <2>; power-domains = <&pd IMX_SC_R_VPU_MU_0>; - status = "disabled"; + status = "okay"; }; mu1_m0: mailbox@2d020000 { @@ -27,11 +34,11 @@ interrupts = ; #mbox-cells = <2>; power-domains = <&pd IMX_SC_R_VPU_MU_1>; - status = "disabled"; + status = "okay"; }; mu2_m0: mailbox@2d040000 { - compatible = "fsl,imx6sx-mu"; + compatible = "fsl,imx8-mu2-vpu-m0", "fsl,imx6sx-mu"; reg = <0x2d040000 0x20000>; interrupts = ; #mbox-cells = <2>; @@ -49,7 +56,6 @@ <&mu_m0 1 0>; status = "disabled"; }; - vpu_core1: vpu-core@2d090000 { reg = <0x2d090000 0x10000>; compatible = "nxp,imx8q-vpu-encoder"; @@ -60,7 +66,6 @@ <&mu1_m0 1 0>; status = "disabled"; }; - vpu_core2: vpu-core@2d0a0000 { reg = <0x2d0a0000 0x10000>; compatible = "nxp,imx8q-vpu-encoder"; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx8ulp-evk.dts" + +/ { + model = "NXP i.MX8ULP 9X9 EVK"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power-on { + label = "PowerOn"; + gpios = <&gpiof 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&iomuxc1 { + pinctrl_sai6: sai6grp { + fsl,pins = < + MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x43 + MX8ULP_PAD_PTE11__I2S6_TX_FS 0x43 + MX8ULP_PAD_PTE14__I2S6_TXD2 0x43 + MX8ULP_PAD_PTE6__I2S6_RXD0 0x43 + >; + }; +}; + +&pinctrl_dsi { + fsl,pins = < + MX8ULP_PAD_PTF21__PTF21 0x3 + >; +}; + +&pinctrl_enet { + fsl,pins = < + MX8ULP_PAD_PTF9__ENET0_MDC 0x43 + MX8ULP_PAD_PTF8__ENET0_MDIO 0x43 + MX8ULP_PAD_PTF5__ENET0_RXER 0x43 + MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x43 + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 + MX8ULP_PAD_PTF0__ENET0_RXD1 0x43 + MX8ULP_PAD_PTF4__ENET0_TXEN 0x43 + MX8ULP_PAD_PTF3__ENET0_TXD0 0x43 + MX8ULP_PAD_PTF2__ENET0_TXD1 0x43 + MX8ULP_PAD_PTF7__ENET0_REFCLK 0x43 + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 + >; + +}; + +&pinctrl_gpio_keys { + fsl,pins = < + MX8ULP_PAD_PTF11__PTF11 0x3 + >; +}; + +&pinctrl_otgid1 { + fsl,pins = < + MX8ULP_PAD_PTE16__USB0_ID 0x10003 + MX8ULP_PAD_PTE18__USB0_OC 0x10003 + >; +}; + +&pinctrl_otgid2 { + fsl,pins = < + MX8ULP_PAD_PTD23__USB1_ID 0x10003 + MX8ULP_PAD_PTE20__USB1_OC 0x10003 + >; +}; + +&i2c_rpbus_0 { + fxls8974@18 { + compatible = "nxp,fxls8974cf"; + reg = <0x18>; + drive-open-drain; + }; +}; + +&pinctrl_lpuart6 { + fsl,pins = < + MX8ULP_PAD_PTF18__LPUART6_TX 0x3 + MX8ULP_PAD_PTF19__LPUART6_RX 0x3 + MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x3 + MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x3 + >; +}; + +&lpspi5 { /* conflict with lpuart6 PAD_PTF16-19 */ + status = "disabled"; +}; + +&lpuart6 { + pinctrl-assert-gpios = <&pca6416_1 10 GPIO_ACTIVE_LOW>; +}; + +&sai5 { + status = "disabled"; +}; + +&sai6 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai6>; + pinctrl-1 = <&pinctrl_sai6>; + assigned-clocks = <&cgc2 IMX8ULP_CLK_SAI6_SEL>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + fsl,dataline = <1 0x01 0x04>; + status = "okay"; +}; + +&btcpu { + sound-dai = <&sai6>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-i3c.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-i3c.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-i3c.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-i3c.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx8ulp-9x9-evk.dts" + +&fec { + status = "disabled"; +}; + +&rpmsg_sensor { + status = "disabled"; +}; + +&i3c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i3c2>; + pinctrl-1 = <&pinctrl_i3c2>; + i2c-scl-hz = <400000>; + status = "okay"; + + lsm6dso_i3c: imu@6a,208006c0000 { + reg = <0x6a 0x208 0x6c0000>; + assigned-address = <0x6a>; + }; +}; + +&iomuxc1 { + pinctrl_i3c2: i3c2grp { + fsl,pins = < + MX8ULP_PAD_PTE19__I3C2_PUR 0x3 + MX8ULP_PAD_PTF6__I3C2_SCL 0x3 + MX8ULP_PAD_PTF7__I3C2_SDA 0x3 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpa.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpa.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpa.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpa.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx8ulp-9x9-evk.dts" +/ { + reserved-memory { + lpa_reserved: lpa_reserved@c0000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0xc0000000 0 0x10000000>; + }; + }; +}; + +&audio_reserved { + status = "disabled"; +}; + +&rpmsg_audio { + memory-region = <&lpa_reserved>; + fsl,enable-lpa; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpspi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpspi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpspi.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx8ulp-9x9-evk.dts" + +&lpuart6 { + status = "disabled"; +}; + +&sai6 { + status = "disabled"; +}; + +&lpspi5 { + pinctrl-assert-gpios = <&pca6416_1 10 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpspi-slave.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpspi-slave.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-lpspi-slave.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx8ulp-9x9-evk-lpspi.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi5 { + fsl,pins = < + MX8ULP_PAD_PTF16__LPSPI5_SIN 0x3 + MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x3 + MX8ULP_PAD_PTF18__LPSPI5_SCK 0x3 + MX8ULP_PAD_PTF19__LPSPI5_PCS0 0x3 + >; +}; + +&lpspi5 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi5>; + pinctrl-1 = <&pinctrl_lpspi5>; + /delete-property/ cs-gpios; + + spi-slave; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-rk055hdmipi4m.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-rk055hdmipi4m.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-rk055hdmipi4m.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-rk055hdmipi4m.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include "imx8ulp-9x9-evk.dts" +#include "imx8ulp-evk-rk055hdmipi4m.dtsi" + +&dsi { + panel@0 { + reset-gpios = <&gpiof 21 GPIO_ACTIVE_LOW>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-rk055hdmipi4mv2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-rk055hdmipi4mv2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-rk055hdmipi4mv2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-rk055hdmipi4mv2.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include "imx8ulp-9x9-evk.dts" +#include "imx8ulp-evk-rk055hdmipi4mv2.dtsi" + +&dsi { + panel@0 { + reset-gpios = <&gpiof 21 GPIO_ACTIVE_LOW>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-sof-btsco.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-sof-btsco.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-sof-btsco.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk-sof-btsco.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include "imx8ulp-9x9-evk.dts" + +/ { + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + dsp_reserved0: dsp@8e000000 { + reg = <0 0x8e000000 0 0x1000000>; + no-map; + }; + dsp_reserved1: dsp@8f000000 { + compatible = "shared-dma-pool"; + memory-region-names = "dsp_mem"; + reg = <0 0x8f000000 0 0x1000000>; + no-map; + }; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sof-sound-btsco { + compatible = "simple-audio-card"; + label = "btsco-audio"; + simple-audio-card,name = "bt-dsp-a"; + simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,frame-master = <&cpudai>; + + simple-audio-card,dai-link { + format = "i2s"; + cpudai: cpu { + sound-dai = <&dsp 1>; + }; + sndcodec: codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + }; +}; + +&rpmsg_audio { + status = "okay"; +}; + +&sai5 { + status = "disabled"; +}; + +&sai6 { + status = "disabled"; +}; + +&edma2 { + status = "disabled"; +}; + +&mu3 { + status = "okay"; +}; + +&dsp { + #sound-dai-cells = <1>; + compatible = "fsl,imx8ulp-dsp"; + memory-reserved = <&dsp_reserved0>; + memory-region = <&dsp_reserved1>; + reg = <0x21170000 0x20000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai6>; + pinctrl-1 = <&pinctrl_sai6>; + + assigned-clocks = <&cgc2 IMX8ULP_CLK_HIFI_SEL>, <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>; + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + assigned-clock-rates = <0>, <0>, <475200000>; + + clocks = <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, + <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>, + <&pcc5 IMX8ULP_CLK_MU3_B>, + <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc2 IMX8ULP_CLK_SAI6_SEL>, + <&pcc5 IMX8ULP_CLK_DMA2_MP>, + <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, + <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, + <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, + <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>; + clock-names = "core", "ipg", "ocram", "mu", + "bus", "mclk0", "mclk1", + "edma-mp-clk", + "edma2-chan0-clk", "edma2-chan1-clk", + "edma2-chan2-clk", "edma2-chan3-clk", + "edma2-chan4-clk", "edma2-chan5-clk", + "edma2-chan6-clk", "edma2-chan7-clk"; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&mu3 2 0>, + <&mu3 2 1>, + <&mu3 3 0>, + <&mu3 3 1>; + /delete-property/ firmware-name; + tplg-name = "sof-imx8ulp-9x9-btsco.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -7,6 +7,10 @@ #include #include #include +#include +#include +#include +#include #include "imx8ulp-pinfunc.h" @@ -17,9 +21,13 @@ aliases { ethernet0 = &fec; - gpio0 = &gpiod; - gpio1 = &gpioe; - gpio2 = &gpiof; + gpio4 = &gpiod; + gpio5 = &gpioe; + gpio6 = &gpiof; + i2c4 = &lpi2c4; + i2c5 = &lpi2c5; + i2c6 = &lpi2c6; + i2c7 = &lpi2c7; mmc0 = &usdhc0; mmc1 = &usdhc1; mmc2 = &usdhc2; @@ -27,6 +35,10 @@ serial1 = &lpuart5; serial2 = &lpuart6; serial3 = &lpuart7; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + isi0 = &isi_0; + csi0 = &mipi_csi0; }; cpus { @@ -39,6 +51,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; + cpu-idle-states = <&cpu_sleep>; }; A35_1: cpu@1 { @@ -47,11 +60,25 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; + cpu-idle-states = <&cpu_sleep>; }; A35_L2: l2-cache0 { compatible = "cache"; }; + + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + }; + }; }; gic: interrupt-controller@2d400000 { @@ -63,6 +90,15 @@ interrupts = ; }; + gpu: gpu { + compatible = "fsl,imx8-gpu-ss"; + cores = <&gpu3d>, <&gpu2d>; + reg = <0x0 0x80000000 0x0 0x80000000>, + <0x0 0x0 0x0 0x08000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + timeout-scale = <10>; + }; + pmu { compatible = "arm,cortex-a35-pmu"; interrupt-parent = <&gic>; @@ -76,6 +112,37 @@ method = "smc"; }; + imx8ulp-lpm { + compatible = "nxp,imx8ulp-lpm"; + clocks = <&cgc2 IMX8ULP_CLK_DDR_SEL >, <&cgc2 IMX8ULP_CLK_DDR_DIV>, + <&cgc2 IMX8ULP_CLK_PLL4 >, <&frosc>, <&cgc1 IMX8ULP_CLK_SPLL2>, + <&cgc1 IMX8ULP_CLK_A35_SEL>, <&cgc1 IMX8ULP_CLK_NIC_SEL>, <&cgc2 IMX8ULP_CLK_LPAV_AXI_SEL>, + <&cgc2 IMX8ULP_CLK_PLL4>; + clock-names = "ddr_sel", "ddr_div", "pll4", "frosc", "spll2", "a35_sel", + "nic_sel", "lpav_axi_sel", "pll4"; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 0>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , /* Physical Secure */ @@ -112,9 +179,9 @@ #clock-cells = <0>; }; - sram@2201f000 { + sram0: sram@22010000 { compatible = "mmio-sram"; - reg = <0x0 0x2201f000 0x0 0x1000>; + reg = <0x0 0x22010000 0x0 0x00010000>; #address-cells = <1>; #size-cells = <1>; @@ -146,11 +213,29 @@ }; }; + rtc-rpmsg { + compatible = "fsl,imx-rpmsg-rtc"; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; + ranges = <0x0 0x0 0x0 0x40000000>, + <0x60000000 0x0 0x60000000 0x1000000>; + + caam_sm: caam-sm@26000000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x26000000 0x8000>; + }; + + ocotp: efuse@27010000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx8ulp-ocotp", "syscon"; + reg = <0x27010000 0x1000>; + status = "okay"; + }; s4muap: mailbox@27020000 { compatible = "fsl,imx8ulp-mu-s4"; @@ -159,6 +244,35 @@ #mbox-cells = <2>; }; + ele_mu: ele-mu { + compatible = "fsl,imx-ele"; + mboxes = <&s4muap 0 0 &s4muap 1 0>; + mbox-names = "tx", "rx"; + fsl,ele_mu_did = <7>; + fsl,ele_mu_id = <2>; + fsl,ele_mu_max_users = <4>; + status = "okay"; + sram-pool = <&sram0>; + }; + + dsp: dsp@21170000 { + compatible = "fsl,imx8ulp-hifi4"; + reg = <0x21170000 0x20000>; + clocks = <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, + <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>, + <&pcc5 IMX8ULP_CLK_MU3_B>; + clock-names = "core", "ipg", "ocram", "mu"; + power-domains = <&scmi_devpd IMX8ULP_PD_HIFI4>; + firmware-name = "imx/dsp/hifi4.bin"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu3 0 0>, + <&mu3 1 0>, + <&mu3 3 0>; + fsl,dsp-ctrl = <&avd_sim>; + status = "disabled"; + }; + per_bridge3: bus@29000000 { compatible = "simple-bus"; reg = <0x29000000 0x800000>; @@ -166,6 +280,112 @@ #size-cells = <1>; ranges; + edma1: dma-controller@29010000 { + compatible = "fsl,imx8ulp-edma"; + reg = <0x29010000 0x10000>, + <0x29020000 0x10000>, <0x29030000 0x10000>, + <0x29040000 0x10000>, <0x29050000 0x10000>, + <0x29060000 0x10000>, <0x29070000 0x10000>, + <0x29080000 0x10000>, <0x29090000 0x10000>, + <0x290a0000 0x10000>, <0x290b0000 0x10000>, + <0x290c0000 0x10000>, <0x290d0000 0x10000>, + <0x290e0000 0x10000>, <0x290f0000 0x10000>, + <0x29100000 0x10000>, <0x29110000 0x10000>, + <0x29120000 0x10000>, <0x29130000 0x10000>, + <0x29140000 0x10000>, <0x29150000 0x10000>, + <0x29160000 0x10000>, <0x29170000 0x10000>, + <0x29180000 0x10000>, <0x29190000 0x10000>, + <0x291a0000 0x10000>, <0x291b0000 0x10000>, + <0x291c0000 0x10000>, <0x291d0000 0x10000>, + <0x291e0000 0x10000>, <0x291f0000 0x10000>, + <0x29200000 0x10000>, <0x29210000 0x10000>; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx", + "edma1-chan2-tx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan6-tx", "edma1-chan7-tx", + "edma1-chan8-tx", "edma1-chan9-tx", + "edma1-chan10-tx", "edma1-chan11-tx", + "edma1-chan12-tx", "edma1-chan13-tx", + "edma1-chan14-tx", "edma1-chan15-tx", + "edma1-chan16-tx", "edma1-chan17-tx", + "edma1-chan18-tx", "edma1-chan19-tx", + "edma1-chan20-tx", "edma1-chan21-tx", + "edma1-chan22-tx", "edma1-chan23-tx", + "edma1-chan24-tx", "edma1-chan25-tx", + "edma1-chan26-tx", "edma1-chan27-tx", + "edma1-chan28-tx", "edma1-chan29-tx", + "edma1-chan30-tx", "edma1-chan31-tx"; + clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, + <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, + <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, + <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, + <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, + <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, + <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, + <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, + <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, + <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, + <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, + <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, + <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, + <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, + <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, + <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, + <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; + clock-names = "edma-mp-clk", + "edma1-chan0-clk", "edma1-chan1-clk", + "edma1-chan2-clk", "edma1-chan3-clk", + "edma1-chan4-clk", "edma1-chan5-clk", + "edma1-chan6-clk", "edma1-chan7-clk", + "edma1-chan8-clk", "edma1-chan9-clk", + "edma1-chan10-clk", "edma1-chan11-clk", + "edma1-chan12-clk", "edma1-chan13-clk", + "edma1-chan14-clk", "edma1-chan15-clk", + "edma1-chan16-clk", "edma1-chan17-clk", + "edma1-chan18-clk", "edma1-chan19-clk", + "edma1-chan20-clk", "edma1-chan21-clk", + "edma1-chan22-clk", "edma1-chan23-clk", + "edma1-chan24-clk", "edma1-chan25-clk", + "edma1-chan26-clk", "edma1-chan27-clk", + "edma1-chan28-clk", "edma1-chan29-clk", + "edma1-chan30-clk", "edma1-chan31-clk"; + status = "okay"; + }; + mu: mailbox@29220000 { compatible = "fsl,imx8ulp-mu"; reg = <0x29220000 0x10000>; @@ -197,6 +417,8 @@ compatible = "fsl,imx8ulp-cgc1"; reg = <0x292c0000 0x10000>; #clock-cells = <1>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + assigned-clock-rates = <12288000>; }; pcc3: clock-controller@292d0000 { @@ -206,13 +428,83 @@ #reset-cells = <1>; }; + crypto: crypto@292e0000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x292e0000 0x10000>; + ranges = <0 0x292e0000 0x10000>; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + + sec_jr3: jr@4000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x4000 0x1000>; + interrupts = ; + }; + }; + tpm5: tpm@29340000 { compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; reg = <0x29340000 0x1000>; interrupts = ; - clocks = <&pcc3 IMX8ULP_CLK_TPM5>, - <&pcc3 IMX8ULP_CLK_TPM5>; + clocks = <&sosc>, <&sosc>; clock-names = "ipg", "per"; + status = "okay"; + }; + + flexio1: flexio@29350000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nxp,imx-flexio"; + reg = <0x29350000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_FLEXIO1>, + <&pcc3 IMX8ULP_CLK_FLEXIO1>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_FLEXIO1>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <24000000>; + status = "disabled"; + + flexio_i2c: flexio-i2c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx-flexio-i2c-master"; + clock-frequency = <100000>; + status = "disabled"; + }; + }; + + i3c2: i3c-master@29360000 { + #address-cells = <3>; + #size-cells = <0>; + compatible = "silvaco,i3c-master"; + reg = <0x29360000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_I3C2>, + <&pcc3 IMX8ULP_CLK_I3C2>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_I3C2>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + assigned-clock-rates = <24000000>; status = "disabled"; }; @@ -226,6 +518,8 @@ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 46 0 0>, <&edma1 45 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -239,6 +533,8 @@ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 48 0 0>, <&edma1 47 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -248,6 +544,11 @@ interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; + dmas = <&edma1 56 0 0>, <&edma1 55 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -257,6 +558,9 @@ interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + assigned-clock-rates = <24000000>; status = "disabled"; }; @@ -272,6 +576,8 @@ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 64 0 0>, <&edma1 63 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -287,6 +593,8 @@ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 66 0 0>, <&edma1 65 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; }; @@ -305,6 +613,21 @@ #reset-cells = <1>; }; + flexspi2: spi@29810000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x29810000 0x10000>, <0x60000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>, + <&pcc4 IMX8ULP_CLK_FLEXSPI2>; + clock-names = "fspi", "fspi_en"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; + status = "disabled"; + }; + lpi2c6: i2c@29840000 { compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x29840000 0x10000>; @@ -315,6 +638,8 @@ assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 50 0 0>, <&edma1 49 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -328,6 +653,8 @@ assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 52 0 0>, <&edma1 51 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -337,6 +664,11 @@ interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; clock-names = "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; + dmas = <&edma1 60 0 0>, <&edma1 59 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -346,6 +678,39 @@ interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; clock-names = "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; + dmas = <&edma1 62 0 0>, <&edma1 61 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + sai4: sai@29880000 { + compatible = "fsl,imx8ulp-sai", "fsl,imx7ulp-sai"; + reg = <0x29880000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 67 0 1>, <&edma1 68 0 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0 0x03 0x03>; + status = "disabled"; + }; + + sai5: sai@29890000 { + compatible = "fsl,imx8ulp-sai", "fsl,imx7ulp-sai"; + reg = <0x29890000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 69 0 1>, <&edma1 70 0 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0 0x0f 0x0f>; status = "disabled"; }; @@ -363,6 +728,9 @@ <&pcc4 IMX8ULP_CLK_USDHC0>; clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>, <&pcc4 IMX8ULP_CLK_USDHC0>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>; + assigned-clock-rates = <389283840>, <389283840>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; bus-width = <4>; @@ -378,6 +746,9 @@ <&pcc4 IMX8ULP_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, <&pcc4 IMX8ULP_CLK_USDHC1>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; + assigned-clock-rates = <194641920>, <194641920>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; bus-width = <4>; @@ -393,12 +764,75 @@ <&pcc4 IMX8ULP_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, <&pcc4 IMX8ULP_CLK_USDHC2>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; + assigned-clock-rates = <194641920>, <194641920>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; + usbotg1: usb@29900000 { + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb"; + reg = <0x29900000 0x200>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB0>; + power-domains = <&scmi_devpd IMX8ULP_PD_USB0>; + phys = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc1: usbmisc@29900200 { + compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc"; + #index-cells = <1>; + reg = <0x29900200 0x200>; + status = "disabled"; + }; + + usbphy1: usb-phy@29910000 { + compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy"; + reg = <0x29910000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbotg2: usb@29920000 { + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb"; + reg = <0x29920000 0x200>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB1>; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; + phys = <&usbphy2>; + fsl,usbmisc = <&usbmisc2 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc2: usbmisc@29920200 { + compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc"; + #index-cells = <1>; + reg = <0x29920200 0x200>; + status = "disabled"; + }; + + usbphy2: usb-phy@29930000 { + compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy"; + reg = <0x29930000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + fec: ethernet@29950000 { compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x29950000 0x10000>; @@ -445,6 +879,129 @@ #size-cells = <1>; ranges; + edma2: dma-controller@2d800000 { + compatible = "fsl,imx8ulp-edma"; + reg = <0x2d800000 0x10000>, + <0x2d810000 0x10000>, <0x2d820000 0x10000>, + <0x2d830000 0x10000>, <0x2d840000 0x10000>, + <0x2d850000 0x10000>, <0x2d860000 0x10000>, + <0x2d870000 0x10000>, <0x2d880000 0x10000>, + <0x2d890000 0x10000>, <0x2d8a0000 0x10000>, + <0x2d8b0000 0x10000>, <0x2d8c0000 0x10000>, + <0x2d8d0000 0x10000>, <0x2d8e0000 0x10000>, + <0x2d8f0000 0x10000>, <0x2d900000 0x10000>, + <0x2d910000 0x10000>, <0x2d920000 0x10000>, + <0x2d930000 0x10000>, <0x2d940000 0x10000>, + <0x2d950000 0x10000>, <0x2d960000 0x10000>, + <0x2d970000 0x10000>, <0x2d980000 0x10000>, + <0x2d990000 0x10000>, <0x2d9a0000 0x10000>, + <0x2d9b0000 0x10000>, <0x2d9c0000 0x10000>, + <0x2d9d0000 0x10000>, <0x2d9e0000 0x10000>, + <0x2d9f0000 0x10000>, <0x2da00000 0x10000>; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx", + "edma2-chan2-tx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx", + "edma2-chan6-tx", "edma2-chan7-tx", + "edma2-chan8-tx", "edma2-chan9-tx", + "edma2-chan10-tx", "edma2-chan11-tx", + "edma2-chan12-tx", "edma2-chan13-tx", + "edma2-chan14-tx", "edma2-chan15-tx", + "edma2-chan16-tx", "edma2-chan17-tx", + "edma2-chan18-tx", "edma2-chan19-tx", + "edma2-chan20-tx", "edma2-chan21-tx", + "edma2-chan22-tx", "edma2-chan23-tx", + "edma2-chan24-tx", "edma2-chan25-tx", + "edma2-chan26-tx", "edma2-chan27-tx", + "edma2-chan28-tx", "edma2-chan29-tx", + "edma2-chan30-tx", "edma2-chan31-tx"; + clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>, + <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, + <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, + <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, + <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, + <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, + <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, + <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, + <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, + <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, + <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, + <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, + <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, + <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, + <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, + <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, + <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; + clock-names = "edma-mp-clk", + "edma2-chan0-clk", "edma2-chan1-clk", + "edma2-chan2-clk", "edma2-chan3-clk", + "edma2-chan4-clk", "edma2-chan5-clk", + "edma2-chan6-clk", "edma2-chan7-clk", + "edma2-chan8-clk", "edma2-chan9-clk", + "edma2-chan10-clk", "edma2-chan11-clk", + "edma2-chan12-clk", "edma2-chan13-clk", + "edma2-chan14-clk", "edma2-chan15-clk", + "edma2-chan16-clk", "edma2-chan17-clk", + "edma2-chan18-clk", "edma2-chan19-clk", + "edma2-chan20-clk", "edma2-chan21-clk", + "edma2-chan22-clk", "edma2-chan23-clk", + "edma2-chan24-clk", "edma2-chan25-clk", + "edma2-chan26-clk", "edma2-chan27-clk", + "edma2-chan28-clk", "edma2-chan29-clk", + "edma2-chan30-clk", "edma2-chan31-clk"; + status = "okay"; + }; + + avd_sim: syscon@2da50000 { + compatible = "nxp,imx8ulp-avd-sim", "syscon", "simple-mfd"; + reg = <0x2da50000 0x38>; + clocks = <&pcc5 IMX8ULP_CLK_AVD_SIM>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; /* DSI_DPI2_EPDC_DCNANO_MUX_SEL */ + }; + + avd_sim_rst: reset-controller { + compatible = "nxp,imx8ulp-avd-sim-reset"; + #reset-cells = <1>; + }; + }; + cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>; @@ -457,6 +1014,292 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + sai6: sai@2da90000 { + compatible = "fsl,imx8ulp-sai", "fsl,imx7ulp-sai"; + reg = <0x2da90000 0x10000>; + interrupts = ; + clocks = <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 71 0 1>, <&edma2 72 0 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0 0x0f 0x0f>; + status = "disabled"; + }; + + sai7: sai@2daa0000 { + compatible = "fsl,imx8ulp-sai", "fsl,imx7ulp-sai"; + reg = <0x2daa0000 0x10000>; + interrupts = ; + clocks = <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 73 0 1>, <&edma2 74 0 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0 0x0f 0x0f>; + status = "disabled"; + }; + + spdif: spdif@2dab0000 { + compatible = "fsl,imx8ulp-spdif"; + reg = <0x2dab0000 0x10000>; + interrupts = ; + clocks = <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */ + <&sosc>, /* 0, extal */ + <&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */ + <&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */ + <&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma2 75 0 5>, <&edma2 76 0 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + isi_0: isi@2dac0000 { + compatible = "fsl,imx8ulp-isi", "fsl,imx8-isi"; + reg = <0x2dac0000 0x10000>; + interrupts = ; + clocks = <&pcc5 IMX8ULP_CLK_ISI>; + clock-names = "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_ISI>; + interface = <2 0 2>; + no-reset-control; + runtime_suspend; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + runtime_suspend; + status = "disabled"; + }; + }; + + mipi_csi0: csi@2dad0000 { + compatible = "fsl,imx8ulp-mipi-csi2", "fsl,mxc-mipi-csi2"; + reg = <0x2daf0000 0x10000>, + <0x2dad0000 0x10000>; + clocks = <&pcc5 IMX8ULP_CLK_CSI>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>, + <&pcc5 IMX8ULP_CLK_CSI_REGS>; + clock-names = "clk_core", "clk_ui", "clk_esc", "clk_regs"; + power-domains = <&scmi_devpd IMX8ULP_PD_MIPI_CSI>; + assigned-clocks = <&cgc2 IMX8ULP_CLK_PLL4_PFD1>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV1>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV2>, + <&pcc5 IMX8ULP_CLK_CSI>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>; + assigned-clock-parents = <0>, <0>, <0>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV1>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV2>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV2>; + assigned-clock-rates = <316800000>, + <316800000>, + <316800000>, + <105600000>, + <79200000>, + <79200000>; + runtime_suspend; + status = "disabled"; + }; + }; + + dsi: dsi@2db00000 { + compatible = "fsl,imx8ulp-nwl-dsi"; + reg = <0x2db00000 0x300>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, + <&pcc5 IMX8ULP_CLK_DSI>, + <&pcc5 IMX8ULP_CLK_DSI_TX_ESC>, + <&cgc2 IMX8ULP_CLK_DSI_PHY_REF>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref"; + power-domains = <&scmi_devpd IMX8ULP_PD_MIPI_DSI>; + assigned-clocks = <&pcc5 IMX8ULP_CLK_DSI>; + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV2>; + assigned-clock-rates = <79200000>; + interrupts = ; + mux-controls = <&mux 0>; + csr = <&avd_sim>; + phys = <&dphy>; + phy-names = "dphy"; + resets = <&avd_sim_rst IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N>, + <&avd_sim_rst IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N>, + <&avd_sim_rst IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N>, + <&pcc5 PCC5_DSI_SWRST>; + reset-names = "byte", "dpi", "esc", "pclk"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_dsi_to_dcnano_dpi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dcnano_dpi_to_mipi_dsi>; + }; + + mipi_dsi_to_epdc_dpi: endpoint@1 { + reg = <1>; + }; + }; + }; + }; + + dphy: phy@2db00300 { + compatible = "fsl,imx8ulp-mipi-dphy"; + reg = <0x2db00300 0x100>; + clocks = <&cgc2 IMX8ULP_CLK_DSI_PHY_REF>; + clock-names = "phy_ref"; + #phy-cells = <0>; + status = "disabled"; + }; + + epdc: epdc@2db30000 { + compatible = "fsl,imx7d-epdc"; + reg = <0x2db30000 0x10000>; + clocks = <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>, + <&pcc5 IMX8ULP_CLK_EPDC>, + <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>; + clock-names = "epdc_axi", "epdc_pix", "epdc_ahb"; + assigned-clocks = <&pcc5 IMX8ULP_CLK_EPDC>; + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV1>; + power-domains = <&scmi_devpd IMX8ULP_PD_PXP>; + interrupts = ; + status = "disabled"; + }; + + epxp: epxp@2db40000 { + compatible = "fsl,imx8ulp-pxp-dma", "fsl,imx7d-pxp-dma"; + reg = <0x2db40000 0x10000>; + clocks = <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>, + <&pcc5 IMX8ULP_CLK_PXP>; + clock-names = "pxp_ipg", "pxp_axi"; + power-domains = <&scmi_devpd IMX8ULP_PD_PXP>; + interrupts = ; + status = "disabled"; + }; + }; + + gpu3d: gpu3d@2e000000 { + compatible = "fsl,imx8-gpu"; + reg = <0x2e000000 0x10000>; + interrupts = ; + clocks = <&pcc5 IMX8ULP_CLK_GPU3D>, + <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>, + <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>; + power-domains = <&scmi_devpd IMX8ULP_PD_GPU3D>; + clock-names = "core", "shader", "axi", "ahb"; + assigned-clocks = <&cgc2 IMX8ULP_CLK_PLL4_PFD2>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD2_DIV2>, + <&pcc5 IMX8ULP_CLK_GPU3D>; + assigned-clock-parents = <0>, + <0>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD2_DIV2>; + assigned-clock-rates = <288000000>, + <288000000>, + <288000000>; + }; + + gpu2d: gpu2d@2e010000 { + compatible = "fsl,imx8-gpu"; + reg = <0x2e010000 0x40000>; + interrupts = ; + clocks = <&pcc5 IMX8ULP_CLK_GPU2D>, + <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>, + <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>; + power-domains = <&scmi_devpd IMX8ULP_PD_GPU2D>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&cgc2 IMX8ULP_CLK_PLL4_PFD2>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD2_DIV2>, + <&pcc5 IMX8ULP_CLK_GPU2D>; + assigned-clock-parents = <0>, + <0>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD2_DIV2>; + assigned-clock-rates = <288000000>, + <288000000>, + <288000000>; + }; + + dcnano: display-controller@2e050000 { + compatible = "nxp,imx8ulp-dcnano"; + reg = <0x2e050000 0x10000>; + interrupts = ; + clocks = <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>, + <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>, + <&pcc5 IMX8ULP_CLK_DC_NANO>; + clock-names = "axi", "ahb", "pixel"; + resets = <&pcc5 PCC5_DC_NANO_SWRST>; + power-domains = <&scmi_devpd IMX8ULP_PD_DCNANO>; + assigned-clocks = <&pcc5 IMX8ULP_CLK_DC_NANO>; + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD3_DIV2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dcnano_dpi: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dcnano_dpi_to_mipi_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_dsi_to_dcnano_dpi>; + }; + + dcnano_dpi_to_disp: endpoint@1 { + reg = <1>; + }; + }; + + dcnano_dbi: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dcnano_dbi_to_mipi_dsi: endpoint@0 { + reg = <0>; + }; + + dcnano_dbi_to_disp: endpoint@1 { + reg = <1>; + }; + }; + }; + }; + + ddrc: memory-controller@2e060000 { + compatible = "nxp,imx8ulp-ddrc"; + reg = <0x2e060000 0x10000>; + interrupts = ; }; gpiod: gpio@2e200080 { @@ -473,4 +1316,8 @@ gpio-ranges = <&iomuxc1 0 0 24>; }; }; + + rpmsg-lifecycle { + compatible = "nxp,rpmsg-lifecycle"; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts 2024-06-19 12:33:58.308192703 +0200 @@ -6,6 +6,8 @@ /dts-v1/; #include "imx8ulp.dtsi" +#include "imx8ulp-rpmsg.dtsi" +#include / { model = "NXP i.MX8ULP EVK"; @@ -15,11 +17,122 @@ stdout-path = &lpuart5; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power-on { + label = "PowerOn"; + gpios = <&gpiof 31 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x80000000>; }; + rpmsg_keys: rpmsg-keys { + compatible = "fsl,rpmsg-keys"; + + volume-up { + label = "VolumeUp"; + linux,code = ; + rpmsg-key,wakeup; + }; + + volume-down { + label = "VolumeDown"; + linux,code = ; + rpmsg-key,wakeup; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + linux,cma-default; + }; + + rsc_table: rsc-table@1fff8000{ + reg = <0 0x1fff8000 0 0x1000>; + no-map; + }; + + dsp_reserved: dsp_reserved@8e000000 { + reg = <0 0x8e000000 0 0x1000000>; + no-map; + }; + dsp_reserved_heap: dsp_reserved_heap { + reg = <0 0x8f000000 0 0xef0000>; + no-map; + }; + dsp_vdev0vring0: vdev0vring0@8fef0000 { + reg = <0 0x8fef0000 0 0x8000>; + no-map; + }; + dsp_vdev0vring1: vdev0vring1@8fef8000 { + reg = <0 0x8fef8000 0 0x8000>; + no-map; + }; + dsp_vdev0buffer: vdev0buffer@8ff00000 { + compatible = "shared-dma-pool"; + reg = <0 0x8ff00000 0 0x100000>; + no-map; + }; + + ele_reserved: ele-reserved@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x100000>; + no-map; + }; + + vdev0vring0: vdev0vring0@aff00000 { + reg = <0 0xaff00000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@aff08000 { + reg = <0 0xaff08000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@aff10000 { + reg = <0 0xaff10000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@aff18000 { + reg = <0 0xaff18000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xa8400000 0 0x100000>; + no-map; + }; + + audio_reserved: audio@a8500000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0xa8500000 0 0x100000>; + }; + + m33_reserved: m33_noncacheable_section@a8600000 { + no-map; + reg = <0 0xa8600000 0 0x1000000>; + }; + }; + clock_ext_rmii: clock-ext-rmii { compatible = "fixed-clock"; clock-frequency = <50000000>; @@ -34,6 +147,213 @@ clock-output-names = "ext_ts_clk"; #clock-cells = <0>; }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6408 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6408 0 GPIO_ACTIVE_LOW>; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai5>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + fsl,constraint-rate = <16000>, <32000>, <48000>, + <64000>, <96000>, <192000>; + }; + + rpmsg_audio: rpmsg-audio { + compatible = "fsl,imx8ulp-rpmsg-audio"; + model = "wm8960-audio"; + fsl,rpmsg-out; + fsl,rpmsg-in; + audio-codec = <&wm8960>; + memory-region = <&audio_reserved>; + audio-routing = + "LINPUT1", "MICB", + "LINPUT3", "MICB"; + status = "okay"; + }; +}; + +&dcnano { + status = "okay"; +}; + +&dphy { + status = "okay"; +}; + +&dsi { + status = "okay"; + ports { + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&it6161_from_dsim>; + }; + }; + }; +}; + +&dsp { + assigned-clocks = <&cgc2 IMX8ULP_CLK_HIFI_SEL>, <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>; + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0>; + assigned-clock-rates = <0>, <475200000>; + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + status = "okay"; +}; + +&flexspi2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexspi2_ptd>; + pinctrl-1 = <&pinctrl_flexspi2_ptd>; + status = "okay"; + + mx25uw51345gxdi00: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <200000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + +&i2c_rpbus_0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca6416_1: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960,lpa"; + reg = <0x1a>; + wlf,shared-lrclk; + clocks = <&wm8960_mclk>; + clock-names = "mclk"; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&cgc2 IMX8ULP_CLK_DSI_PHY_REF>; + clock-names = "xclk"; + powerdown-gpios = <&pca6416_1 8 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_LOW>; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; + + ite_bridge: it6161@6c { + compatible = "ite,it6161"; + reg = <0x6c>; + it6161-addr-hdmi-tx = <0x4c>; + enable-gpios = <&pca6416_1 9 GPIO_ACTIVE_LOW>; + interrupt-parent = <&rpmsg_gpioa>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + it6161_from_dsim: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; +}; + +&i2c_rpbus_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&imx8ulp_cm33 { + ipc-only; + rsc-da=<0x1fff8000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&lpspi5 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpspi5>; + pinctrl-1 = <&pinctrl_lpspi5>; + cs-gpios = <&gpiof 19 GPIO_ACTIVE_LOW>; + pinctrl-assert-gpios = <&pca6416_1 10 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "lwn,bk4"; + spi-max-frequency = <1000000>; + }; }; &lpuart5 { @@ -44,15 +364,156 @@ status = "okay"; }; -&usdhc0 { +&lpuart6 { + /* BT */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart6>; + pinctrl-1 = <&pinctrl_lpuart6>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&lpuart7 { + /* FT4232 PortD: need to connect J25/J26 2-3 */ pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart7>; + pinctrl-1 = <&pinctrl_lpuart7>; + status = "okay"; +}; + +&lpi2c7 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c7>; + pinctrl-1 = <&pinctrl_lpi2c7>; + status = "okay"; + + pcal6408: gpio@21 { + compatible = "nxp,pcal9554b"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&mu { + status = "okay"; +}; + +&mu3 { + status = "okay"; +}; + +&sai5 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai5>; + pinctrl-1 = <&pinctrl_sai5>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SAI5_SEL>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + fsl,dataline = <1 0x08 0x01>; + status = "okay"; +}; + +&spdif { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-1 = <&pinctrl_spdif>; + assigned-clocks = <&cgc2 IMX8ULP_CLK_SPDIF_SEL>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + status = "okay"; +}; + +&tpm_rpchip_0 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_otgid1>; + pinctrl-1 = <&pinctrl_otgid1>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + over-current-active-low; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; + fsl,tx-d-cal = <110>; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_otgid2>; + pinctrl-1 = <&pinctrl_otgid2>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + over-current-active-low; + status = "okay"; +}; + +&usbphy2 { + status = "okay"; + fsl,tx-d-cal = <110>; +}; + +&usbmisc2 { + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc0>; pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; non-removable; bus-width = <8>; status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_pte>; + pinctrl-1 = <&pinctrl_usdhc2_pte>; + pinctrl-2 = <&pinctrl_usdhc2_pte>; + pinctrl-3 = <&pinctrl_usdhc2_pte>; + mmc-pwrseq = <&usdhc2_pwrseq>; + vmmc-supply = <®_usdhc2_vmmc>; + max-frequency = <100000000>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpioe>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&ele_mu { + memory-region = <&ele_reserved>; +}; + &fec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_enet>; @@ -80,6 +541,12 @@ }; &iomuxc1 { + pinctrl_dsi: dsigrp { + fsl,pins = < + MX8ULP_PAD_PTF8__PTF8 0x3 + >; + }; + pinctrl_enet: enetgrp { fsl,pins = < MX8ULP_PAD_PTE15__ENET0_MDC 0x43 @@ -96,6 +563,38 @@ >; }; + pinctrl_flexspi2_ptd: flexspi2ptdgrp { + fsl,pins = < + + MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42 + MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42 + MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42 + MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42 + MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42 + MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42 + MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42 + MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42 + MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42 + MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42 + MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42 + >; + }; + + pinctrl_gpio_keys: gpiokeys { + fsl,pins = < + MX8ULP_PAD_PTF31__PTF31 0x3 + >; + }; + + pinctrl_lpspi5: lpspi5grp { + fsl,pins = < + MX8ULP_PAD_PTF16__LPSPI5_SIN 0x43 + MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x43 + MX8ULP_PAD_PTF18__LPSPI5_SCK 0x43 + MX8ULP_PAD_PTF19__PTF19 0x43 + >; + }; + pinctrl_lpuart5: lpuart5grp { fsl,pins = < MX8ULP_PAD_PTF14__LPUART5_TX 0x3 @@ -103,19 +602,115 @@ >; }; + pinctrl_lpuart6: lpuart6grp { + fsl,pins = < + MX8ULP_PAD_PTE10__LPUART6_TX 0x3 + MX8ULP_PAD_PTE11__LPUART6_RX 0x3 + MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x3 + MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x3 + >; + }; + + pinctrl_lpuart7: lpuart7grp { + fsl,pins = < + MX8ULP_PAD_PTF22__LPUART7_TX 0x3 + MX8ULP_PAD_PTF23__LPUART7_RX 0x3 + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20 + MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20 + >; + }; + + pinctrl_otgid1: usb1grp { + fsl,pins = < + MX8ULP_PAD_PTF2__USB0_ID 0x10003 + MX8ULP_PAD_PTF4__USB0_OC 0x10003 + >; + }; + + pinctrl_otgid2: usb2grp { + fsl,pins = < + MX8ULP_PAD_PTD23__USB1_ID 0x10003 + MX8ULP_PAD_PTF6__USB1_OC 0x10003 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x43 + MX8ULP_PAD_PTF27__I2S5_TX_FS 0x43 + MX8ULP_PAD_PTF28__I2S5_TXD0 0x43 + MX8ULP_PAD_PTF24__I2S5_RXD3 0x43 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX8ULP_PAD_PTF25__SPDIF_OUT1 0x43 + >; + }; + pinctrl_usdhc0: usdhc0grp { fsl,pins = < - MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 - MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 - MX8ULP_PAD_PTD10__SDHC0_D0 0x43 - MX8ULP_PAD_PTD9__SDHC0_D1 0x43 - MX8ULP_PAD_PTD8__SDHC0_D2 0x43 - MX8ULP_PAD_PTD7__SDHC0_D3 0x43 - MX8ULP_PAD_PTD6__SDHC0_D4 0x43 - MX8ULP_PAD_PTD5__SDHC0_D5 0x43 - MX8ULP_PAD_PTD4__SDHC0_D6 0x43 - MX8ULP_PAD_PTD3__SDHC0_D7 0x43 - MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 + MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002 + MX8ULP_PAD_PTD10__SDHC0_D0 0x3 + MX8ULP_PAD_PTD9__SDHC0_D1 0x3 + MX8ULP_PAD_PTD8__SDHC0_D2 0x3 + MX8ULP_PAD_PTD7__SDHC0_D3 0x3 + MX8ULP_PAD_PTD6__SDHC0_D4 0x3 + MX8ULP_PAD_PTD5__SDHC0_D5 0x3 + MX8ULP_PAD_PTD4__SDHC0_D6 0x3 + MX8ULP_PAD_PTD3__SDHC0_D7 0x3 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002 + >; + }; + + pinctrl_usdhc2_pte: usdhc2ptegrp { + fsl,pins = < + MX8ULP_PAD_PTE1__SDHC2_D0 0x3 + MX8ULP_PAD_PTE0__SDHC2_D1 0x3 + MX8ULP_PAD_PTE5__SDHC2_D2 0x3 + MX8ULP_PAD_PTE4__SDHC2_D3 0x3 + MX8ULP_PAD_PTE2__SDHC2_CLK 0x10002 + MX8ULP_PAD_PTE3__SDHC2_CMD 0x3 + MX8ULP_PAD_PTE7__PTE7 0x10003 >; }; + +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + bus-type = <4>; + }; + }; +}; + +&epxp { + status = "okay"; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-epdc.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-epdc.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-epdc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-epdc.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include "imx8ulp-evk-rk055hdmipi4m.dts" + +/ { + sound-spdif { + status = "disabled"; + }; +}; + +&i2c_rpbus_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + fp9931: fp9931@18 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pf9931>; + compatible = "fitipower,fp9931"; + reg = <0x18>; + status = "okay"; + + /* power up and down timings in mseconds */ + vgl-pwrup = <1>; + vneg-pwrup = <1>; + vgh-pwrup = <1>; + vpos-pwrup = <1>; + ss-time = <3>; + gpio-pmic-pwrgood = <&gpioe 17 0>; + gpio-pmic-wakeup = <&gpioe 18 0>; + + /* enable sequence for panel VB3300: + * + * V3P3->VGL->VNEG->VGH->VPOS->VCOM + */ + regulators { + /* fifth enabe VPOS */ + vpos_reg: VPOS-LDO { + regulator-name = "VPOS"; + regulator-min-microvolt = <7040000>; + regulator-max-microvolt = <15060000>; + }; + + /* third enable VNEG */ + vneg_reg: VNEG-LDO { + regulator-name = "VNEG"; + /* Real max value: -7040000 uV */ + regulator-min-microvolt = <7040000>; + /* Real min value: -15060000 uV */ + regulator-max-microvolt = <15060000>; + }; + + /* fourth enable VGH */ + vgh_reg: VGH-CHARGE-PUMP { + /* 15V to 30V with External Dividual Resistor */ + regulator-name = "VGH"; + }; + + /* second enable VGL */ + vgl_reg: VGL-CHARGE-PUMP { + /* -15V to -25V with External Dividual Resistor */ + regulator-name = "VGL"; + }; + + /* last enable VCOM */ + vcom_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -19608 uV */ + regulator-min-microvolt = <19608>; + /* Real min value: -5000000 uV */ + regulator-max-microvolt = <5000000>; + }; + + /* V3P3 is the first power need to be enabled + * according to VB3300 panel spec. + */ + v3p3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&iomuxc1 { + pinctrl_pf9931: pf9931grp-1 { + fsl,pins = < + MX8ULP_PAD_PTE17__PTE17 0x80000000 /* pwrgood */ + MX8ULP_PAD_PTE18__EPDC0_PWRWAKE 0x80000000 /* wakeup */ + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX8ULP_PAD_PTF23__EPDC0_D0 0x43 + MX8ULP_PAD_PTF22__EPDC0_D1 0x43 + MX8ULP_PAD_PTF21__EPDC0_D2 0x43 + MX8ULP_PAD_PTF20__EPDC0_D3 0x43 + MX8ULP_PAD_PTF19__EPDC0_D4 0x43 + MX8ULP_PAD_PTF18__EPDC0_D5 0x43 + MX8ULP_PAD_PTF17__EPDC0_D6 0x43 + MX8ULP_PAD_PTF16__EPDC0_D7 0x43 + MX8ULP_PAD_PTF24__EPDC0_SDCLK 0x43 + MX8ULP_PAD_PTF25__EPDC0_GDSP 0x43 + MX8ULP_PAD_PTF26__EPDC0_SDLE 0x43 + MX8ULP_PAD_PTF27__EPDC0_SDCE0 0x43 + + MX8ULP_PAD_PTF0__EPDC0_SDOE 0x43 + MX8ULP_PAD_PTE19__EPDC0_GDCLK 0x43 + MX8ULP_PAD_PTE20__EPDC0_GDOE 0x43 + MX8ULP_PAD_PTE21__EPDC0_GDRL 0x43 + + >; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + en-gpios = <&pca6416_1 10 GPIO_ACTIVE_HIGH>; /* switch */ + V3P3-supply = <&v3p3_reg>; + VCOM-supply = <&vcom_reg>; + VPOS-supply = <&vpos_reg>; + VNEG-supply = <&vneg_reg>; + status = "okay"; +}; + +&epxp { + status = "okay"; +}; + +&fec { + status = "disabled"; +}; + +&sai5 { /* conflict PAD_PTF23 */ + status = "disabled"; +}; + +&spdif {/* conflict PAD_PTF25 */ + status = "disabled"; +}; + +&lpspi5 {/* conflict PAD_PTF19 */ + status = "disabled"; +}; + +&lpuart7 {/* conflict PAD_PTF23 */ + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-flexio-i2c.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-flexio-i2c.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-flexio-i2c.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-flexio-i2c.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include "imx8ulp-evk.dts" + +/{ + aliases { + i2c8 = &flexio_i2c; + }; +}; + +&lpi2c7 { + status = "disabled"; + /delete-node/ gpio@21; +}; + +&flexio1 { + status = "okay"; +}; + +&flexio_i2c { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexio_i2c_master>; + pinctrl-1 = <&pinctrl_flexio_i2c_master>; + sda = /bits/ 8 <0xa>; + scl = /bits/ 8 <0xb>; + status = "okay"; + + pcal6408: gpio@21 { + compatible = "nxp,pcal9554b"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; +}; + +&iomuxc1 { + pinctrl_flexio_i2c_master: flexiogrp { + fsl,pins = < + MX8ULP_PAD_PTE12__FXIO1_D11 0x20 + MX8ULP_PAD_PTE13__FXIO1_D10 0x20 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-i3c.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-i3c.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-i3c.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-i3c.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include "imx8ulp-evk.dts" + +&fec { + status = "disabled"; +}; + +&lpspi5 { + status = "disabled"; +}; + +&rpmsg_sensor { + status = "disabled"; +}; + +&i3c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i3c2>; + pinctrl-1 = <&pinctrl_i3c2>; + pinctrl-assert-gpios = <&pca6416_1 10 GPIO_ACTIVE_HIGH>; + i2c-scl-hz = <400000>; + status = "okay"; + + lsm6dso_i3c: imu@6a,208006c0000 { + reg = <0x6a 0x208 0x6c0000>; + assigned-address = <0x6a>; + }; +}; + +&iomuxc1 { + pinctrl_i3c2: i3c2grp { + fsl,pins = < + MX8ULP_PAD_PTE15__I3C2_PUR 0x3 + MX8ULP_PAD_PTE22__I3C2_SCL 0x3 + MX8ULP_PAD_PTE23__I3C2_SDA 0x3 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-lpa.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-lpa.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-lpa.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-lpa.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx8ulp-evk.dts" +/ { + reserved-memory { + lpa_reserved: lpa_reserved@c0000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0xc0000000 0 0x10000000>; + }; + }; +}; + +&audio_reserved { + status = "disabled"; +}; + +&rpmsg_audio { + memory-region = <&lpa_reserved>; + fsl,enable-lpa; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-lpspi-slave.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-lpspi-slave.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-lpspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-lpspi-slave.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include "imx8ulp-evk.dts" + +/delete-node/&spidev0; + +&pinctrl_lpspi5 { + fsl,pins = < + MX8ULP_PAD_PTF16__LPSPI5_SIN 0x3 + MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x3 + MX8ULP_PAD_PTF18__LPSPI5_SCK 0x3 + MX8ULP_PAD_PTF19__LPSPI5_PCS0 0x3 + >; +}; + +&lpspi5 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi5>; + pinctrl-1 = <&pinctrl_lpspi5>; + /delete-property/ cs-gpios; + + spi-slave; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-nd.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-nd.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-nd.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-nd.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include "imx8ulp-evk.dts" + +/ { + imx8ulp-lpm { + sys-dvfs-enabled; + }; +}; + +&gpu3d { + assigned-clock-rates = <396000000>, <198000000>, <198000000>; +}; + +&gpu2d { + assigned-clock-rates = <396000000>, <198000000>, <198000000>; +}; + +&dcnano { + /* Place Holder */ +}; + +&mipi_csi0 { + assigned-clock-rates = <316800000>, + <316800000>, + <316800000>, + <105600000>, + <79200000>, + <46000000>; +}; + +&epdc { + /* Place Holder */ +}; + +&dsp { + assigned-clocks = <&cgc2 IMX8ULP_CLK_HIFI_SEL>, <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>; + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0>; + assigned-clock-rates = <0>, <264000000>; +}; + +&flexspi2 { + assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV2>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV2>; + assigned-clock-rates = <0>, <96000000>; +}; + +&mx25uw51345gxdi00 { + spi-max-frequency = <96000000>; +}; + +&i3c2 { + assigned-clock-rates = <24000000>; +}; + +&usdhc0 { + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>, <&pcc4 IMX8ULP_CLK_USDHC0>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>; + assigned-clock-rates = <194641920>, <194641920>; +}; + +&usdhc1 { + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>, <&pcc4 IMX8ULP_CLK_USDHC1>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>; + assigned-clock-rates = <96000000>, <96000000>; +}; + +&usdhc2 { + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>, <&pcc4 IMX8ULP_CLK_USDHC2>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>; + assigned-clock-rates = <96000000>, <96000000>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021,2022 NXP + */ + +#include "imx8ulp-evk.dts" +#include "imx8ulp-evk-rk055hdmipi4m.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + pwm_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&tpm_rpchip_0 2 50000 0>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <100>; + }; +}; + +/delete-node/ &ite_bridge; + +&dsi { + panel@0 { + compatible = "raydium,rm68200"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi>; + enable-gpios = <&pca6416_1 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; + power-supply = <®_5v>; + backlight = <&pwm_backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&i2c_rpbus_1 { + goodix@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&rpmsg_gpiob>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&rpmsg_gpiob 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4mv2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4mv2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4mv2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4mv2.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021,2022 NXP + */ + +#include "imx8ulp-evk.dts" +#include "imx8ulp-evk-rk055hdmipi4mv2.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4mv2.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4mv2.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4mv2.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4mv2.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + pwm_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&tpm_rpchip_0 2 50000 0>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <100>; + }; +}; + +/delete-node/ &ite_bridge; + +&dsi { + panel@0 { + compatible = "rocktech,hx8394f"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi>; + himax,dsi-lanes = <2>; + enable-gpios = <&pca6416_1 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; + vcc-supply = <®_5v>; + iovcc-supply = <®_5v>; + backlight = <&pwm_backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&i2c_rpbus_1 { + goodix@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&rpmsg_gpiob>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&rpmsg_gpiob 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-sof-btsco.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-sof-btsco.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-evk-sof-btsco.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-evk-sof-btsco.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include "imx8ulp-evk.dts" + +/ { + reserved-memory { + /delete-node/ dsp_reserved; + /delete-node/ dsp_vdev0vring0; + /delete-node/ dsp_vdev0vring1; + /delete-node/ dsp_vdev0buffer; + dsp_reserved0: dsp@8e000000 { + reg = <0 0x8e000000 0 0x1000000>; + no-map; + }; + dsp_reserved1: dsp@8f000000 { + compatible = "shared-dma-pool"; + memory-region-names = "dsp_mem"; + reg = <0 0x8f000000 0 0x1000000>; + no-map; + }; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sof-sound-btsco { + compatible = "simple-audio-card"; + label = "btsco-audio"; + simple-audio-card,name = "bt-dsp-a"; + simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,frame-master = <&cpudai>; + + simple-audio-card,dai-link { + format = "i2s"; + cpudai: cpu { + sound-dai = <&dsp 0>; + }; + sndcodec: codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + }; +}; + +&rpmsg_audio { + status = "okay"; +}; + +&sai5 { + status = "disabled"; +}; + +&sai6 { + status = "disabled"; +}; + +&edma2 { + status = "disabled"; +}; + +&mu3 { + status = "okay"; +}; + +&dsp { + #sound-dai-cells = <1>; + compatible = "fsl,imx8ulp-dsp"; + memory-reserved = <&dsp_reserved0>; + memory-region = <&dsp_reserved1>; + reg = <0x21170000 0x20000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai5>; + pinctrl-1 = <&pinctrl_sai5>; + + assigned-clocks = <&cgc2 IMX8ULP_CLK_HIFI_SEL>, <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>; + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + assigned-clock-rates = <0>, <0>, <475200000>; + + clocks = <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, + <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>, + <&pcc5 IMX8ULP_CLK_MU3_B>, + <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_SAI5_SEL>, + <&pcc5 IMX8ULP_CLK_DMA2_MP>, + <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, + <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, + <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, + <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>; + clock-names = "core", "ipg", "ocram", "mu", + "bus", "mclk0", "mclk1", + "edma-mp-clk", + "edma2-chan0-clk", "edma2-chan1-clk", + "edma2-chan2-clk", "edma2-chan3-clk", + "edma2-chan4-clk", "edma2-chan5-clk", + "edma2-chan6-clk", "edma2-chan7-clk"; + + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&mu3 2 0>, + <&mu3 2 1>, + <&mu3 3 0>, + <&mu3 3 1>; + /delete-property/ firmware-name; + tplg-name = "sof-imx8ulp-btsco.tplg"; + machine-drv-name = "asoc-simple-card"; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-rpmsg.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-rpmsg.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8ulp-rpmsg.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8ulp-rpmsg.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/ { + aliases { + gpio0 = &rpmsg_gpioa; + gpio1 = &rpmsg_gpiob; + i2c0 = &i2c_rpbus_0; + i2c1 = &i2c_rpbus_1; + pwm0 = &tpm_rpchip_0; + }; + + wm8960_mclk: wm8960-mclk { + compatible = "fixed-clock"; + clock-frequency = <12288000>; + clock-output-names = "wm8960_mclk"; + #clock-cells = <0>; + }; + + imx8ulp_cm33: imx8ulp-cm33 { + compatible = "fsl,imx8ulp-cm33"; + status = "disabled"; + }; + + i2c_rpbus_0: i2c-rpbus-0 { + compatible = "fsl,i2c-rpbus-v2"; + status = "disabled"; + }; + + i2c_rpbus_1: i2c-rpbus-1 { + compatible = "fsl,i2c-rpbus-v2"; + status = "disabled"; + }; + + rpmsg_gpioa: gpio@0 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <0>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpioa>; + status = "okay"; + }; + + rpmsg_gpiob: gpio@1 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <1>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpiob>; + status = "okay"; + }; + + tpm_rpchip_0: pwm { + compatible = "fsl,pwm-rpchip"; + #pwm-cells = <3>; + fsl,pwm-channel-number = <6>; + status = "disabled"; + }; + + rpmsg_sensor: rpmsg-sensor { + compatible = "nxp,rpmsg-iio-pedometer"; + status = "okay"; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-17x17-val.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8x-val.dtsi" + +/ { + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0xc0000000 0 0x14000000>; + linux,cma-default; + }; + }; + + regulators { + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pcieb: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "mpcie_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_a 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&iomuxc { + imx8qxp-lpddr4-arm2 { + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + >; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + /delete-node/ gpio@68; + /delete-node/ typec@3d; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + /delete-node/ gpio@18; + /delete-node/ gpio@19; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c_mipi_csi0 { + status = "disabled"; +}; + +&mipi_csi_0 { + status = "disabled"; +}; + +&gpio0_mipi_csi0 { + status = "disabled"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + vpcie-supply = <®_pcieb>; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + /delete-node/ mt35xu512aba@0; + + flash0: mt25qu512abb@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <8>; + }; +}; + +&adc0 { + status = "disabled"; +}; + +&usbotg1 { + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + panel { + compatible = "sii,43wvf1g"; + backlight = <&lcdif_backlight>; + status = "okay"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + display@disp1 { + compatible = "fsl,imx-lcdif-mux-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "bypass_div", "pixel"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + fsl,lcdif-mux-regs = <&lcdif_mux_regs>; + fsl,interface-pix-fmt = "rgb666"; + power-domains = <&pd IMX_SC_R_LCD_0>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&dpu_disp1_lcdif>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + lcdif_backlight: lcdif-backlight { + compatible = "pwm-backlight"; + pwms = <&adma_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&dpu_disp1_lcdif { + remote-endpoint = <&lcd_display_in>; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x40000000 + >; + }; +}; + +&sai1 { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&lpuart1 { + status = "disabled"; +}; + +&adma_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdifpwm>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,1671 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2020 NXP + */ + +#include +/ { + chosen { + stdout-path = &lpuart0; + }; + + brcmfmac: brcmfmac { + compatible = "cypress,brcmfmac"; + pinctrl-names = "init", "idle", "default"; + pinctrl-0 = <&pinctrl_wifi_init>; + pinctrl-1 = <&pinctrl_wifi_init>; + pinctrl-2 = <&pinctrl_wifi>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_mipi_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm_mipi_lvds1 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + cbtl04gp { + compatible = "nxp,cbtl04gp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + switch-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_LOW>; + reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpu_reserved: gpu_reserved@880000000 { + no-map; + reg = <0x8 0x80000000 0 0x10000000>; + }; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x1000000>; + no-map; + }; + dsp_reserved_heap: dsp_reserved_heap { + reg = <0 0x93400000 0 0xef0000>; + no-map; + }; + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + + encoder_rpc: encoder-rpc@94400000 { + reg = <0 0x94400000 0 0x700000>; + no-map; + }; + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0xc0000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <3480>; + enable-active-high; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pcieb: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "mpcie_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usbotg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai0>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai0>; + audio-codec = <&cs42888>; + audio-asrc = <&asrc0>; + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + status = "okay"; + }; + + sound-wm8960 { + compatible = "fsl,imx8x-mek-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8960>; + hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8962>; + hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + cm4 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + imx8x_cm4: imx8x_cm4@0 { + compatible = "fsl,imx8qxp-cm4"; + rsc-da = <0x90000000>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + fsl,resource-id = ; + fsl,entry-address = <0x34fe0000>; + status = "okay"; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, + <&pd IMX_SC_R_M4_0_MU_1A>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@90000000 { + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@900ff000 { + reg = <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + }; + + /* + * this dummy i2c mux. + * gpio actually will not impact selection. + * at actual boards, only 1 devices connectted. + * I2C client driver will check ID when probe. + * Only matched ID's driver probe successfully. + */ + i2cvmux: i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; /* use an unused gpio */ + i2c-parent = <&cm40_i2c>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = + <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + /* WCPU boards SCH-54536 */ + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = + <786432000>, <49152000>, <12288000>, <12288000>; + }; + }; + }; +}; + +&lsio_mu5 { + status = "okay"; +}; + +&cm40_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_cm40_i2c>; + pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; + scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_b 1 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&pi0_misc_lpcg 0>; + assigned-clocks = <&pi0_misc_lpcg 0>; + assigned-clock-rates = <24000000>; + clock-names = "xclk"; + powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ + bus-width = <8>; + vsync-active = <0>; + hsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; +}; + +&cm40_intmux { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; + +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&pwm_mipi_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; + status = "okay"; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds_bridge0: lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + adv_bridge0: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_0_in: endpoint { + remote-endpoint = <&mipi0_adv_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&mipi0_dphy { + status = "okay"; +}; + +&mipi0_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi0_adv_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; +}; + +&pwm_mipi_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; + status = "okay"; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + lvds_bridge1: lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + + port { + it6263_1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + adv_bridge1: adv7535@3d { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port@0 { + reg = <0>; + adv7535_1_in: endpoint { + remote-endpoint = <&mipi1_adv_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&mipi1_dphy { + status = "okay"; +}; + +&mipi1_dsi_host { + status = "okay"; + + ports { + port@1 { + reg = <1>; + mipi1_adv_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&dsp { + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,txm-rxs; + status = "okay"; +}; + +&sai0 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + qca,disable-smarteee; + vddio-supply = <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + qca,disable-smarteee; + vddio-supply = <&vddio1>; + status = "disabled"; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; + status = "disabled"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + nxp,fspi-dll-slvdly = <4>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9646", "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas21002c@21 { + compatible = "nxp,fxas21002c"; + reg = <0x21>; + interrupt-open-drain; + }; + + pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + /* WCPU boards SCH-54536 */ + ms5611@77 { + compatible = "meas,ms5611"; + reg = <0x77>; + }; + + icm20602@68 { + compatible = "invensense,icm20602"; + reg = <0x68>; + }; + + /* iam20380@69 no driver yet */ + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "isil,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; + + /* WCPU boards SCH-54536 */ + vcnl4035@60 { + compatible = "vishay,vcnl4035"; + reg = <0x60>; + }; + }; + + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&scu_key { + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&phyx1 { + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&pcieb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcieb>; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&vpu { + compatible = "nxp,imx8qxp-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d040000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d050000 0x10000>; + memory-region = <&encoder_boot>, <&encoder_rpc>; + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + memory-region=<&gpu_reserved>; + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_2 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_3 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&isi_4 { + interface = <6 0 2>; + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_cm40_i2c: cm40i2cgrp { + fsl,pins = < + IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c + IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_cm40_i2c_gpio: cm40i2cgrp-gpio { + fsl,pins = < + IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c + IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x00000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_ioexp_rst: ioexprstgrp { + fsl,pins = < + IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000021 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_pwm_mipi_lvds0: mipi_lvds0_pwm_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_pwm_mipi_lvds1: mipi_lvds1_pwm_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060 + IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040 + IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040 + IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 + IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 + IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 + IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 + IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_mipi_csi0: mipi_csi0 { + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + IMX8QXP_CSI_D00_CI_PI_D02 0xC0000041 + IMX8QXP_CSI_D01_CI_PI_D03 0xC0000041 + IMX8QXP_CSI_D02_CI_PI_D04 0xC0000041 + IMX8QXP_CSI_D03_CI_PI_D05 0xC0000041 + IMX8QXP_CSI_D04_CI_PI_D06 0xC0000041 + IMX8QXP_CSI_D05_CI_PI_D07 0xC0000041 + IMX8QXP_CSI_D06_CI_PI_D08 0xC0000041 + IMX8QXP_CSI_D07_CI_PI_D09 0xC0000041 + + IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041 + IMX8QXP_CSI_PCLK_CI_PI_PCLK 0xC0000041 + IMX8QXP_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 + IMX8QXP_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 + IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 + >; + }; + + pinctrl_wifi: wifigrp{ + fsl,pins = < + IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_wifi_init: wifi_initgrp{ + fsl,pins = < + /* reserve pin init/idle_state to support multiple wlan cards */ + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060 + IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x00000060 + IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060 + IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060 + IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060 + IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060 + IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060 + IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060 + IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060 + IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x00000060 + IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x00000060 + IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x00000060 + IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 0x00000060 + IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060 + IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060 + IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET 0x00000060 + IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x00000060 + IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060 + IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060 + >; + }; + + pinctrl_lcdifpwm: lcdifpwmgrp { + fsl,pins = < + IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000060 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds0-dual-channel.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +&i2c0_mipi_lvds0 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + fsl,dual-channel; +}; + +&ldb2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-it6263-lvds1-dual-channel.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +&i2c0_mipi_lvds1 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2 { + fsl,dual-channel; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds0-panel.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +/ { + lvds0_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +/delete-node/ &it6263_0_in; + +&ldb1 { + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_lvds0_in>; + }; + }; + }; +}; + +&ldb2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-jdi-wuxga-lvds1-panel.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight0>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +/delete-node/ &it6263_1_in; + +&ldb2 { + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&ldb1 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-lcdif.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +/ { + display-subsystem { + status = "disabled"; + }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&lcdif_backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&adapter_out>; + }; + }; + }; + + seiko_adapter: seiko-adapter { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,seiko-43wvfig"; + bus_mode = <18>; + + port@0 { + reg = <0>; + adapter_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + port@1 { + reg = <1>; + adapter_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + lcdif_backlight: lcdif-backlight { + compatible = "pwm-backlight"; + pwms = <&adma_pwm 0 100000 0>; + status = "okay"; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&iomuxc { + /delete-node/ pinctrl_hog; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&lpuart1 { + status = "disabled"; +}; + +&adma_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdifpwm>; + status = "okay"; +}; + +&adma_pwm_lpcg { + status = "okay"; +}; + + +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + port@0 { + lcdif_out: endpoint { + remote-endpoint = <&adapter_in>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-mek-rpmsg.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + + +/delete-node/ &cm40_i2c; +/delete-node/ &i2c1; + +/ { + aliases { + i2c1 = &i2c_rpbus_1; + }; +}; + +&i2c_rpbus_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2cvmux { + i2c-parent = <&i2c_rpbus_5>; +}; + +&i2c_rpbus_5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_b 1 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + fsl,txs-rxm; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&pi0_misc_lpcg 0>; + assigned-clocks = <&pi0_misc_lpcg 0>; + assigned-clock-rates = <24000000>; + clock-names = "xclk"; + powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ + bus-width = <8>; + vsync-active = <0>; + hsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; +}; + +&i2c_rpbus_12 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c_rpbus_14 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@21 { + compatible = "nxp,fxas21002c"; + reg = <0x21>; + interrupt-open-drain; + }; + + pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + /* WCPU boards SCH-54536 */ + ms5611@77 { + compatible = "meas,ms5611"; + reg = <0x77>; + }; + + icm20602@68 { + compatible = "invensense,icm20602"; + reg = <0x68>; + }; + /* iam20380@69 no driver yet */ +}; + +&i2c_rpbus_15 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "isil,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <2 2>; + }; + + /* WCPU boards SCH-54536 */ + vcnl4035@60 { + compatible = "vishay,vcnl4035"; + reg = <0x60>; + }; +}; + +&cm40_i2c_lpcg { + status = "disabled"; +}; + +&i2c1_lpcg { + status = "disabled"; +}; + +&can0_lpcg { + status = "disabled"; +}; + +®_can_en { + status = "disabled"; +}; + +®_can_stby { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&cm40_intmux { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&lpuart3 { + status = "disabled"; +}; + +&uart3_lpcg { + status = "disabled"; +}; + +&imx8x_cm4 { + /* Assume you have partitioned M4, so M4 is ont controled by Linux */ + /delete-property/ power-domains; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-val.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-val.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx8x-val.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx8x-val.dtsi 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,843 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ + +/ { + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay = <2720>; + enable-active-high; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_audio: fixedregulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_baseboard: fixedregulator@1 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "baseboard_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_adc_vref_1v8: adc_vref_1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai0>; + audio-codec = <&codec>; + audio-asrc = <&asrc0>; + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + status = "okay"; + }; +}; + +&acm { + status = "okay"; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_adc_vref_1v8>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&esai0 { + compatible = "fsl,imx8qm-esai"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + imx8qxp-lpddr4-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0xc600004c + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 + IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 + >; + }; + + pinctrl_csi0_lpi2c0: csi0lpi2c0grp { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 + IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_ptn5150: ptn5150 { + fsl,pins = < + IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_lpi2c1: lpi1cgrp { + fsl,pins = < + IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_lpi2c3: lpi2cgrp { + fsl,pins = < + IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 + IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x0600002c + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x0600002c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x0600002c + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x0600002c + IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x0600002c + IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x0600002c + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x0600002c + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x0600002c + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + rx-internal-delay-ps = <2000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + qca,disable-smarteee; + vddio-supply = <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + qca,disable-smarteee; + vddio-supply = <&vddio1>; + status = "disabled"; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + rx-internal-delay-ps = <2000>; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&gpio0_mipi_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <8>; + }; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 1>; + status = "okay"; + }; + + max9286_mipi@6a { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk_dummy>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + typec_ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + reg = <0x3d>; + connect-gpios = <&lsio_gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cm40_intmux { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-aud-hat.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-aud-hat.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-aud-hat.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-aud-hat.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-11x11-evk.dts" + +/ { + mic_leds { + compatible = "gpio-leds"; + mic0 { + label = "mic0"; + gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic1 { + label = "mic1"; + gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic2 { + label = "mic2"; + gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic3 { + label = "mic3"; + gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic4 { + label = "mic4"; + gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic5 { + label = "mic5"; + gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic6 { + label = "mic6"; + gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic7 { + label = "mic7"; + gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sw_keys { + compatible = "gpio-keys"; + + sw4: volume_down { + label = "Volume Down"; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; + + sw3: volume_up { + label = "Volume Up"; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + }; + + sw2: volume_mute { + label = "Volume Mute"; + gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; + + sw1: key_act { + label = "Key Act"; + gpios = <&pca9555 12 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + reg_vddext_3v3: regulator-vddext { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_audio_switch1: regulator-audio-switch1 { + compatible = "regulator-fixed"; + regulator-name = "audio-switch1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "cs42448-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-wm8962 { + status = "disabled"; + }; + + sound-cs42448 { + compatible = "fsl,imx-audio-card"; + model = "imx-cs42448"; + status = "okay"; + pri-dai-link { + link-name = "cs42448"; + format = "dsp_a"; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai3>; + }; + codec { + sound-dai = <&cs42448>; + }; + }; + }; + +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3audhat>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm2>; + status = "okay"; +}; + +&lpi2c4 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + dmas = <&edma2 10 0 0>, <&edma2 11 0 1>; + dma-names = "tx","rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4>; + status = "okay"; + + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pushbutton_irq>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_vddext_3v3>; + status = "okay"; + }; + + cs42448: cs42448@48 { + #sound-dai-cells = <0>; + compatible = "cirrus,cs42448"; + reg = <0x48>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + clock-names = "mclk"; + VA-supply = <®_audio_pwr>; + VD-supply = <®_audio_pwr>; + VLS-supply = <®_audio_pwr>; + VLC-supply = <®_audio_pwr>; + reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_swpdm_mute_irq: swpdm_mute_grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e + >; + }; + + pinctrl_pushbutton_irq: pushbutton_grp { + fsl,pins = < + MX93_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + + pinctrl_pdm2: pdm2grp { + fsl,pins = < + MX93_PAD_GPIO_IO04__PDM_CLK 0x31e + MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x31e + MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x31e + MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x31e + MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x31e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x40000b9e + MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x40000b9e + >; + }; + + pinctrl_sai3audhat: sai3audhat { + fsl,pins = < + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x31e + MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,825 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +/dts-v1/; + +#include +#include "imx93.dtsi" + +/ { + model = "NXP i.MX91P 11X11 EVK board"; + compatible = "fsl,imx91p-11x11-evk", "fsl,imx91p", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + + ele_reserved: ele-reserved@a4120000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>; + enable-active-low; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_vdd_12v: regulator-vdd-12v { + compatible = "regulator-fixed"; + regulator-name = "reg_vdd_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585gpio 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + pri-dai-link { + link-name = "XCVR PCM"; + cpu { + sound-dai = <&xcvr>; + }; + }; + }; +}; + +&A55_1 { + status = "fail"; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&ele_mu { + memory-region = <&ele_reserved>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + eee-broken-1000t; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + lsm6dsm@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + adp5585: mfd@34 { + compatible = "adi,adp5585"; + reg = <0x34>; + + adp5585gpio: gpio@34 { + compatible = "adp5585-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + adp5585pwm: pwm@34 { + compatible = "adp5585-pwm"; + #pwm-cells = <3>; + }; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110"; + reg = <0x51>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-assert-gpios = <&pcal6524 19 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + mmc-pwrseq = <&usdhc3_pwrseq>; + vmmc-supply = <®_usdhc3_vmmc>; + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&xcvr { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_SPDIF_GATE>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUD_XCVR_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SPDIF>, + <&clk IMX93_CLK_AUDIO_XCVR>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <12288000>, <200000000>; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__PDM_CLK 0x31e + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-flexspi-m2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-flexspi-m2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-flexspi-m2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-flexspi-m2.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-11x11-evk.dts" + +&usdhc3_pwrseq { + status = "disabled"; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexspi1>; + pinctrl-1 = <&pinctrl_flexspi1>; + /* + * For this spi-nor on M.2 card, need first enable the VPCIe_3.3v. + * Note, VPCIe_3.3v need about 1.74ms to change from 0v to 3.3v. + * U-boot already enable VPCIe_3.3v, so in linux, can ignore this + * 1.7ms, if u-boot do not enable VPCIe_3.3v first, then need to + * take care of the 1.74ms delay, better to build the flexspi driver + * as module in driver to avoid spi-nor probe fail. + */ + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>, /* enable VPCIe_3v3 */ + <&pcal6524 20 GPIO_ACTIVE_HIGH>, /* enable SPI-NOR VCC 1.8v */ + <&pcal6524 12 GPIO_ACTIVE_HIGH>; /* put SPI-NOR RST pin to 1.8v */ + status = "okay"; + + mt25qu512abb8e12: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins = < + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x3fe + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x3fe + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x3fe + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x3fe + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-i3c.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-i3c.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-i3c.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-i3c.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-11x11-evk.dts" + +/{ + aliases { + /delete-property/ i2c0; + }; +}; + +/delete-node/&lpi2c1; + +/* + * When add i2c devices on i3c bus, the reg property should be changed to: + * reg = <0x1a 0x00 0x50>; + * The first byte is still the address of the i2c device; + * The second byte is always 0x00; + * The third byte is the communication speed of this i2c device; + * 0x20 means 1MHz(FM+); + * 0x50 means 400KHz(FM); + * In compatibility mode, I3C will use the slowest setting of all targets + * for i2c communication. + */ +&i3c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i3c1>; + pinctrl-1 = <&pinctrl_i3c1>; + i2c-scl-hz = <400000>; + status = "okay"; + + /* i2c device */ + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a 0x00 0x50>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + /* i3c device with static i2c address*/ + lsm6dso_i3c: imu@6a,208006c0000 { + reg = <0x6a 0x208 0x6c0000>; + assigned-address = <0x6a>; + }; +}; + +&iomuxc { + pinctrl_i3c1: i3c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__I3C1_SCL 0x4000019e + MX93_PAD_I2C1_SDA__I3C1_SDA 0x4000019e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-ld.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-ld.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-ld.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-ld.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-11x11-evk.dts" + +&flexspi1 { + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&lpm { + clocks = <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_NIC_AXI>, <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_A55_PERIPH>, <&clk IMX93_CLK_A55_CORE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SYS_PLL_PFD0>, <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD2>, <&clk IMX93_CLK_SYS_PLL_PFD2_DIV2>; + no-od-mode; + ld-mode-enabled; + soc-supply = <&buck1>; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX93_CLK_USDHC1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX93_CLK_USDHC2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX93_CLK_USDHC3>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-lpspi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-lpspi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-lpspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-lpspi.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-11x11-evk.dts" + +&flexcan2 { + status = "disabled"; +}; + +&lpuart7 { + status = "disabled"; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + pinctrl-assert-gpios = <&adp5585gpio 4 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "lwn,bk4"; + spi-max-frequency = <1000000>; + }; +}; + +&iomuxc { + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__GPIO2_IO08 0x3fe + MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe + MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe + MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-lpspi-slave.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-lpspi-slave.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-lpspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-lpspi-slave.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-11x11-evk-lpspi.dts" + +/delete-node/&spidev0; + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + /delete-property/ cs-gpios; + + spi-slave; +}; + +&iomuxc { + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x3fe + MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe + MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe + MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-mqs.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-mqs.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-mqs.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-mqs.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-11x11-evk.dts" + +/ { + reg_audio_switch: regulator-audio-switch { + compatible = "regulator-fixed"; + regulator-name = "audio-switch"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585gpio 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-cpu = <&sai1>; + audio-codec = <&mqs1>; + }; +}; + +&sai1 { + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&mqs1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs1>; + clocks = <&clk IMX93_CLK_MQS1_GATE>; + clock-names = "mclk"; + status = "okay"; +}; + +&micfil { + status = "disabled"; +}; + +&iomuxc { + pinctrl_mqs1: mqs1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__MQS1_LEFT 0x31e + MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-mt9m114.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-mt9m114.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-mt9m114.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-mt9m114.dts 2024-06-19 12:33:58.308192703 +0200 @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-11x11-evk.dts" + +/ { + reg_mt9m114_dovdd: regulator-mt9m114-dovdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-dovdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <0>; + off-on-delay-us = <1000>; + gpio = <&pca9538 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_avdd: regulator-mt9m114-avdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <200>; + off-on-delay-us = <500>; + gpio = <&pca9538 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_dvdd: regulator-mt9m114-dvdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-dvdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <500>; + off-on-delay-us = <200>; + gpio = <&pca9538 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_extclk: regulator-mt9m114-extclk { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-extclk"; + startup-delay-us = <1000>; + off-on-delay-us = <0>; + gpio = <&pca9538 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_ctrl_9509: regulator-mt9m114-ctrl-9509 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-9509"; + gpio = <&pca9538 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mt9m114_ctrl_4t245: regulator-mt9m114-ctrl-4t245 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-4t245"; + gpio = <&pca9538 5 GPIO_ACTIVE_HIGH>; + enable-active-low; + regulator-always-on; + }; + + reg_mt9m114_ctrl_16t245: regulator-mt9m114-ctrl-16t245 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-16t245"; + gpio = <&pca9538 6 GPIO_ACTIVE_HIGH>; + enable-active-low; + regulator-always-on; + }; +}; + +&iomuxc { + pinctrl_parallel_csi: ci_pi { + fsl,pins = < + MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0xb9e + MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0xb9e + MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0xb9e + MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0xb9e + MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0xb9e + MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0xb9e + MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0xb9e + MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0xb9e + MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0xb9e + MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0xb9e + + MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0xb9e + MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0xb9e + MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0xb9e + MX93_PAD_GPIO_IO05__GPIO2_IO05 0x31e + MX93_PAD_GPIO_IO04__GPIO2_IO04 0x31e + >; + }; + + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = < + MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x40000b9e + MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x40000b9e + >; + }; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +&isi_0 { + interface = <6 0 2>; + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&mt9m114_ep>; + }; + }; +}; + +&lpi2c8 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8>; + pinctrl-assert-gpios = <&adp5585gpio 4 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9538: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + mt9m114: mt9m114@48 { + compatible = "on,mt9m114"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + reset-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + DOVDD-supply = <®_mt9m114_dovdd>; + AVDD-supply = <®_mt9m114_avdd>; + DVDD-supply = <®_mt9m114_dvdd>; + EXTCLK-supply = <®_mt9m114_extclk>; + mclk = <27000000>; + status = "okay"; + + port { + mt9m114_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; +}; + +&sai3 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-ontat-wvga-panel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-ontat-wvga-panel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-ontat-wvga-panel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-11x11-evk-ontat-wvga-panel.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-11x11-evk.dts" + +/ { + panel { + compatible = "ontat,kd50g21-40nt-a1"; + enable-gpios = <&adp5585gpio 4 GPIO_ACTIVE_HIGH>; + power-supply = <®_vdd_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; + assigned-clock-rates = <300000000>, <30000000>, <400000000>, <133333333>; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +¶llel_disp_fmt { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + fsl,interface-pix-fmt = "rgb666"; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +/* pin conflicts */ +&sai3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-aud-hat.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-aud-hat.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-aud-hat.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-aud-hat.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-9x9-qsb.dts" + +/ { + mic_leds { + compatible = "gpio-leds"; + mic0 { + label = "mic0"; + gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic1 { + label = "mic1"; + gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic2 { + label = "mic2"; + gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic3 { + label = "mic3"; + gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic4 { + label = "mic4"; + gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic5 { + label = "mic5"; + gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic6 { + label = "mic6"; + gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic7 { + label = "mic7"; + gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sw_keys { + compatible = "gpio-keys"; + + sw4: volume_down { + label = "Volume Down"; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; + + sw3: volume_up { + label = "Volume Up"; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + }; + + sw2: volume_mute { + label = "Volume Mute"; + gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; + + sw1: key_act { + label = "Key Act"; + gpios = <&pca9555 12 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + reg_vddext_3v3: regulator-vddext { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_pwr>; + regulator-name = "cs42448-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-wm8962 { + status = "disabled"; + }; + + sound-cs42448 { + compatible = "fsl,imx-audio-card"; + model = "imx-cs42448"; + status = "okay"; + pri-dai-link { + link-name = "cs42448"; + format = "dsp_a"; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai3>; + }; + codec { + sound-dai = <&cs42448>; + }; + }; + }; + +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3audhat>; + pinctrl-assert-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm2>; + status = "okay"; +}; + +&lpi2c4 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + dmas = <&edma2 10 0 0>, <&edma2 11 0 1>; + dma-names = "tx","rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4>; + status = "okay"; + + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&pcal6524>; + interrupts = <8 IRQ_TYPE_EDGE_BOTH>; + vcc-supply = <®_vddext_3v3>; + status = "okay"; + }; + + cs42448: cs42448@48 { + #sound-dai-cells = <0>; + compatible = "cirrus,cs42448"; + reg = <0x48>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + clock-names = "mclk"; + VA-supply = <®_audio_pwr>; + VD-supply = <®_audio_pwr>; + VLS-supply = <®_audio_pwr>; + VLC-supply = <®_audio_pwr>; + reset-gpio = <&pcal6524 6 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_swpdm_mute_irq: swpdm_mute_grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e + >; + }; + + pinctrl_pdm2: pdm2grp { + fsl,pins = < + MX93_PAD_GPIO_IO04__PDM_CLK 0x31e + MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x31e + MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x31e + MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x31e + MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x31e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x40000b9e + MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x40000b9e + >; + }; + + pinctrl_sai3audhat: sai3audhat { + fsl,pins = < + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x31e + MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x4000031e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_audio_pwr: audiopwrgrp { + fsl,pins = < + MX93_PAD_GPIO_IO01__GPIO2_IO01 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-can1.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-can1.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-can1.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-can1.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-9x9-qsb.dts" + +/{ + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 23 GPIO_ACTIVE_LOW>; + enable-active-low; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + /* config the MIC/CAN_SEL to high, chose B port */ + pinctrl-assert-gpios = <&pcal6524 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* micfi1 use the A port, conflict with can1 */ +&micfil { + status = "disabled"; +}; + +&iomuxc { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,632 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +/dts-v1/; + +#include +#include "imx93.dtsi" + +/ { + model = "NXP i.MX91P 9x9 Quick Start Board"; + compatible = "fsl,imx91p-9x9-qsb", "fsl,imx91p", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + + ele_reserved: ele-reserved@a4120000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_vdd_3v3: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; +}; + +&A55_1 { + status = "fail"; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&ele_mu { + memory-region = <&ele_reserved>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + lsm6dsm@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-assert-gpios = <&pcal6524 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-assert-gpios = <&pcal6524 17 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-assert-gpios = <&pcal6524 22 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + fsl,sai-synchronous-rx; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-2 = <&pinctrl_usdhc3>; + mmc-pwrseq = <&usdhc3_pwrseq>; + vmmc-supply = <®_usdhc3_vmmc>; + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&pcal6524>; + /* pcal6524 IO expander limitation: only support edge-triggered irq */ + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x31e + MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__PDM_CLK 0x31e + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-flexspi-m2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-flexspi-m2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-flexspi-m2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-flexspi-m2.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-9x9-qsb.dts" + +&usdhc3_pwrseq { + status = "disabled"; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexspi1>; + pinctrl-1 = <&pinctrl_flexspi1>; + /* + * For this spi-nor on M.2 card, need first enable the VPCIe_3.3v. + * Note, VPCIe_3.3v need about 1.74ms to change from 0v to 3.3v. + * U-boot already enable VPCIe_3.3v, so in linux, can ignore this + * 1.7ms, if u-boot do not eanble VPCIe_3.3v first, then need to + * take care of the 1.74ms delay, better to build the flexspi driver + * as module in driver to avoid spi-nor probe fail. + */ + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>, /* enable VPCIe_3v3 */ + <&pcal6524 20 GPIO_ACTIVE_HIGH>, /* enable SPI-NOR VCC 1.8v */ + <&pcal6524 12 GPIO_ACTIVE_HIGH>; /* put SPI-NOR RST pin to 1.8v */ + status = "okay"; + + mt25qu512abb8e12: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins = < + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x3fe + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x3fe + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x3fe + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x3fe + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-i3c.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-i3c.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-i3c.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-i3c.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-9x9-qsb.dts" + +/{ + aliases { + /delete-property/ i2c0; + }; +}; + +/delete-node/&lpi2c1; + +/* + * When add i2c devices on i3c bus, the reg property should be changed to: + * reg = <0x1a 0x00 0x50>; + * The first byte is still the address of the i2c device; + * The second byte is always 0x00; + * The third byte is the communication speed of this i2c device; + * 0x20 means 1MHz(FM+); + * 0x50 means 400KHz(FM); + * In compatibility mode, I3C will use the slowest setting of all targets + * for i2c communication. + */ +&i3c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i3c1>; + pinctrl-1 = <&pinctrl_i3c1>; + i2c-scl-hz = <400000>; + status = "okay"; + + /* i2c device */ + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a 0x00 0x50>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50 0x00 0x50>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + /* i3c device with static i2c address*/ + lsm6dso_i3c: imu@6a,208006c0000 { + reg = <0x6a 0x208 0x6c0000>; + assigned-address = <0x6a>; + }; +}; + +&iomuxc { + pinctrl_i3c1: i3c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__I3C1_SCL 0x4000019e + MX93_PAD_I2C1_SDA__I3C1_SDA 0x4000019e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-ld.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-ld.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-ld.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-ld.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-9x9-qsb.dts" + +&flexspi1 { + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&lpm { + clocks = <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_NIC_AXI>, <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_A55_PERIPH>, <&clk IMX93_CLK_A55_CORE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SYS_PLL_PFD0>, <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD2>, <&clk IMX93_CLK_SYS_PLL_PFD2_DIV2>; + no-od-mode; + ld-mode-enabled; + soc-supply = <&buck1>; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX93_CLK_USDHC1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX93_CLK_USDHC2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX93_CLK_USDHC3>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-lpspi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-lpspi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-lpspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-lpspi.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-9x9-qsb.dts" + +&sai3 { + status = "disabled"; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + /* + * Switch the SPI pins to RPi connector for testing. + * It will also control the pins of SAI3, so SAI3 is disabled above. + */ + pinctrl-assert-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "lwn,bk4"; + spi-max-frequency = <1000000>; + }; +}; + +&iomuxc { + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__GPIO2_IO08 0x3fe + MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe + MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe + MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-lpspi-slave.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-lpspi-slave.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-lpspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-lpspi-slave.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-9x9-qsb-lpspi.dts" + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + spi-slave; + /delete-property/ cs-gpios; + /delete-node/ spi@0; +}; + +&iomuxc { + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x3fe + MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe + MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe + MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-mt9m114.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-mt9m114.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-mt9m114.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-mt9m114.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-9x9-qsb.dts" + +/ { + reg_mt9m114_dovdd: regulator-mt9m114-dovdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-dovdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <0>; + off-on-delay-us = <1000>; + gpio = <&pca9538 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_avdd: regulator-mt9m114-avdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <200>; + off-on-delay-us = <500>; + gpio = <&pca9538 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_dvdd: regulator-mt9m114-dvdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-dvdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <500>; + off-on-delay-us = <200>; + gpio = <&pca9538 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_extclk: regulator-mt9m114-extclk { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-extclk"; + startup-delay-us = <1000>; + off-on-delay-us = <0>; + gpio = <&pca9538 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_ctrl_9509: regulator-mt9m114-ctrl-9509 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-9509"; + gpio = <&pca9538 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mt9m114_ctrl_4t245: regulator-mt9m114-ctrl-4t245 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-4t245"; + gpio = <&pca9538 5 GPIO_ACTIVE_HIGH>; + enable-active-low; + regulator-always-on; + }; + + reg_mt9m114_ctrl_16t245: regulator-mt9m114-ctrl-16t245 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-16t245"; + gpio = <&pca9538 6 GPIO_ACTIVE_HIGH>; + enable-active-low; + regulator-always-on; + }; +}; + +&iomuxc { + pinctrl_parallel_csi: ci_pi { + fsl,pins = < + MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0xb9e + MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0xb9e + MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0xb9e + MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0xb9e + MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0xb9e + MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0xb9e + MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0xb9e + MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0xb9e + MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0xb9e + MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0xb9e + + MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0xb9e + MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0xb9e + MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0xb9e + MX93_PAD_GPIO_IO05__GPIO2_IO05 0x31e + MX93_PAD_GPIO_IO04__GPIO2_IO04 0x31e + >; + }; + + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = < + MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x40000b9e + MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x40000b9e + >; + }; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +&isi_0 { + interface = <6 0 2>; + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&mt9m114_ep>; + }; + }; +}; + +&lpi2c8 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8>; + pinctrl-assert-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9538: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + mt9m114: mt9m114@48 { + compatible = "on,mt9m114"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + reset-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + DOVDD-supply = <®_mt9m114_dovdd>; + AVDD-supply = <®_mt9m114_avdd>; + DVDD-supply = <®_mt9m114_dvdd>; + EXTCLK-supply = <®_mt9m114_extclk>; + mclk = <27000000>; + status = "okay"; + + port { + mt9m114_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; +}; + +&sai3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-ontat-wvga-panel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-ontat-wvga-panel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-ontat-wvga-panel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-ontat-wvga-panel.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-9x9-qsb.dts" + +/ { + panel { + compatible = "ontat,kd50g21-40nt-a1"; + enable-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + power-supply = <®_vdd_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; + assigned-clock-rates = <300000000>, <30000000>, <400000000>, <133333333>; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +¶llel_disp_fmt { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + fsl,interface-pix-fmt = "rgb666"; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +/* pin conflicts */ +&sai3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-spi-nand-m2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-spi-nand-m2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-spi-nand-m2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx91p-9x9-qsb-spi-nand-m2.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx91p-9x9-qsb-flexspi-m2.dts" + +&flexspi1 { + /delete-node/ mt25qu512abb8e12; + + mt29f4g01abbfd: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <83000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-aud-hat.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-aud-hat.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-aud-hat.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-aud-hat.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk.dts" + +/ { + mic_leds { + compatible = "gpio-leds"; + mic0 { + label = "mic0"; + gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic1 { + label = "mic1"; + gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic2 { + label = "mic2"; + gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic3 { + label = "mic3"; + gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic4 { + label = "mic4"; + gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic5 { + label = "mic5"; + gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic6 { + label = "mic6"; + gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic7 { + label = "mic7"; + gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sw_keys { + compatible = "gpio-keys"; + + sw4: volume_down { + label = "Volume Down"; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; + + sw3: volume_up { + label = "Volume Up"; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + }; + + sw2: volume_mute { + label = "Volume Mute"; + gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; + + sw1: key_act { + label = "Key Act"; + gpios = <&pca9555 12 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + reg_vddext_3v3: regulator-vddext { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_audio_switch1: regulator-audio-switch1 { + compatible = "regulator-fixed"; + regulator-name = "audio-switch1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "cs42448-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-wm8962 { + status = "disabled"; + }; + + sound-cs42448 { + compatible = "fsl,imx-audio-card"; + model = "imx-cs42448"; + status = "okay"; + pri-dai-link { + link-name = "cs42448"; + format = "dsp_a"; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai3>; + }; + codec { + sound-dai = <&cs42448>; + }; + }; + }; + +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3audhat>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm2>; + status = "okay"; +}; + +&lpi2c4 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + dmas = <&edma2 10 0 0>, <&edma2 11 0 1>; + dma-names = "tx","rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4>; + status = "okay"; + + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pushbutton_irq>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_vddext_3v3>; + status = "okay"; + }; + + cs42448: cs42448@48 { + #sound-dai-cells = <0>; + compatible = "cirrus,cs42448"; + reg = <0x48>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + clock-names = "mclk"; + VA-supply = <®_audio_pwr>; + VD-supply = <®_audio_pwr>; + VLS-supply = <®_audio_pwr>; + VLC-supply = <®_audio_pwr>; + reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_swpdm_mute_irq: swpdm_mute_grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e + >; + }; + + pinctrl_pushbutton_irq: pushbutton_grp { + fsl,pins = < + MX93_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + + pinctrl_pdm2: pdm2grp { + fsl,pins = < + MX93_PAD_GPIO_IO04__PDM_CLK 0x31e + MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x31e + MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x31e + MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x31e + MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x31e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x40000b9e + MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x40000b9e + >; + }; + + pinctrl_sai3audhat: sai3audhat { + fsl,pins = < + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x31e + MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-boe-wxga-lvds-panel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-boe-wxga-lvds-panel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-boe-wxga-lvds-panel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-boe-wxga-lvds-panel.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk.dts" + +/ { + lvds_backlight: lvds_backlight { + compatible = "pwm-backlight"; + pwms = <&adp5585pwm 0 100000 0>; + enable-gpios = <&adp5585gpio 8 GPIO_ACTIVE_HIGH>; + power-supply = <®_vdd_12v>; + status = "okay"; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_panel { + compatible = "boe,ev121wxm-n10-1850"; + backlight = <&lvds_backlight>; + + port { + panel_lvds_in: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; +}; + +&adv7535 { + status = "disabled"; +}; + +&dphy { + status = "disabled"; +}; + +&dsi { + status = "disabled"; +}; + +&lcdif { + assigned-clock-rates = <498000000>, <71142857>, <400000000>, <133333333>; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@1 { + reg = <1>; + + lvds_out: endpoint { + remote-endpoint = <&panel_lvds_in>; + }; + }; + }; +}; + +&ldb_phy { + status = "okay"; +}; + +&lpi2c1 { + exc80h60: touch@2a { + compatible = "eeti,exc80h60"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctp_int>; + /* + * Need to do hardware rework here: + * remove R131, short R181 + */ + interrupt-parent = <&gpio2>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pcal6524 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_ctp_int: ctp_int_grp { + fsl,pins = < + MX93_PAD_GPIO_IO21__GPIO2_IO21 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts 2024-06-19 12:33:58.312192771 +0200 @@ -5,8 +5,13 @@ /dts-v1/; +#include #include "imx93.dtsi" +&ele_mu { + memory-region = <&ele_reserved>; +}; + / { model = "NXP i.MX93 11X11 EVK board"; compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; @@ -15,6 +20,90 @@ stdout-path = &lpuart1; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + + ethosu_mem: ethosu_region@C0000000 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 0xC0000000 0x0 0x10000000>; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + + ele_reserved: ele-reserved@a4120000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + cm33: imx93-cm33 { + compatible = "fsl,imx93-cm33"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1 + &mu1 1 1 + &mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + fsl,startup-delay-ms = <500>; + }; + + ethosu { + compatible = "arm,ethosu"; + fsl,cm33-proc = <&cm33>; + memory-region = <ðosu_mem>; + power-domains = <&mlmix>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>; + enable-active-low; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -23,16 +112,581 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_vdd_12v: regulator-vdd-12v { + compatible = "regulator-fixed"; + regulator-name = "reg_vdd_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585gpio 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_dvdd_sel: regulator-dvdd_sel { + compatible = "regulator-fixed"; + regulator-name = "DVDD_SEL"; + gpio = <&adp5585gpio_isp 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <2000>; + }; + + reg_dvdd_1v2: regulator-dvdd { + compatible = "regulator-fixed"; + regulator-name = "DVDD_1V2"; + gpio = <&adp5585gpio_isp 6 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + enable-active-high; + vin-supply = <®_dvdd_sel>; + }; + + reg_vdd_3v3: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + gpio = <&adp5585gpio_isp 5 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <4000>; enable-active-high; }; + + reg_vddio_1v8: regulator-vddo { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_1V8"; + gpio = <&adp5585gpio_isp 9 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <4000>; + enable-active-high; + vin-supply = <®_vdd_3v3>; + }; + + reg_vaa_sel: regulator-vaa_sel { + compatible = "regulator-fixed"; + regulator-name = "VAA_SEL"; + gpio = <&adp5585gpio_isp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_avdd_2v8: regulator-avdd { + compatible = "regulator-fixed"; + regulator-name = "AVDD_2V8"; + gpio = <&adp5585gpio_isp 7 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + vin-supply = <®_vaa_sel>; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + pri-dai-link { + link-name = "XCVR PCM"; + cpu { + sound-dai = <&xcvr>; + }; + }; + }; }; -&mu1 { +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; status = "okay"; }; -&mu2 { +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&xcvr { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_SPDIF_GATE>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUD_XCVR_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SPDIF>, + <&clk IMX93_CLK_AUDIO_XCVR>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <12288000>, <200000000>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&dphy { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_to_adv7535: endpoint { + remote-endpoint = <&adv7535_to_dsi>; + }; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + eee-broken-1000t; + }; + }; +}; + +&lcdif { + status = "okay"; + assigned-clock-rates = <445333333>, <148444444>, <400000000>, <133333333>; +}; + +&lpm { + soc-supply = <&buck1>; + status = "okay"; +}; + +/* + * When add, delete or change any target device setting in &lpi2c1, + * please synchronize the changes to the &i3c1 bus in imx93-11x11-evk-i3c.dts. + */ +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_to_dsi: endpoint { + remote-endpoint = <&dsi_to_adv7535>; + }; + }; + }; + + lsm6dsm@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + adp5585: mfd@34 { + compatible = "adi,adp5585"; + reg = <0x34>; + + adp5585gpio: gpio@34 { + compatible = "adp5585-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + adp5585pwm: pwm@34 { + compatible = "adp5585-pwm"; + #pwm-cells = <3>; + }; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; status = "okay"; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110"; + reg = <0x51>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + adp5585_isp: mfd-isp@34 { + compatible = "adi,adp5585"; + reg = <0x34>; + status = "okay"; + + adp5585gpio_isp: gpio-isp@34 { + compatible = "adp5585-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + adp5585pwm_isp: pwm-isp@34 { + compatible = "adp5585-pwm"; + #pwm-cells = <3>; + }; + }; + + ap1302: ap1302_mipi@3c { + compatible = "onsemi,ap1302"; + reg = <0x3c>; + reset-gpios = <&adp5585gpio 0 GPIO_ACTIVE_LOW>; + isp_en-gpios = <&adp5585gpio_isp 2 GPIO_ACTIVE_HIGH>; + DVDD-supply = <®_dvdd_1v2>; + VDDIO-supply = <®_vddio_1v8>; + AVDD-supply = <®_avdd_2v8>; + status = "okay"; + + port { + ar1302_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi_ep>; + }; + }; + }; }; &lpuart1 { /* console */ @@ -41,11 +695,71 @@ status = "okay"; }; +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-assert-gpios = <&pcal6524 19 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1>; - pinctrl-2 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; status = "okay"; @@ -54,8 +768,8 @@ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; bus-width = <4>; @@ -64,7 +778,102 @@ no-mmc; }; +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + mmc-pwrseq = <&usdhc3_pwrseq>; + vmmc-supply = <®_usdhc3_vmmc>; + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + &iomuxc { + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX93_PAD_UART1_RXD__LPUART1_RX 0x31e @@ -72,18 +881,62 @@ >; }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe >; }; @@ -100,15 +953,151 @@ >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2: usdhc2grp { fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__PDM_CLK 0x31e + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; +}; + +&epxp { + status = "okay"; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&mipi_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi_ep: endpoint { + remote-endpoint = <&ar1302_mipi_ep>; + data-lanes = <2>; + cfg-clk-range = <28>; + hs-clk-range = <0x2b>; + bus-type = <4>; + }; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-flexio-i2c.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-flexio-i2c.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-flexio-i2c.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-flexio-i2c.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk.dts" + +/{ + aliases { + i2c8 = &flexio_i2c; + }; +}; + +&lpi2c3 { + status = "disabled"; + /delete-node/ tcpc@51; +}; + +&flexio1 { + status = "okay"; +}; + +&flexio_i2c { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexio_i2c_master>; + pinctrl-1 = <&pinctrl_flexio_i2c_master>; + sda = /bits/ 8 <0x6>; + scl = /bits/ 8 <0x5>; + status = "okay"; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110"; + reg = <0x51>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&iomuxc { + pinctrl_flexio_i2c_master: flexiogrp { + fsl,pins = < + MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0xb9e + MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0xb9e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-flexspi-m2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-flexspi-m2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-flexspi-m2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-flexspi-m2.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk.dts" + +&usdhc3_pwrseq { + status = "disabled"; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexspi1>; + pinctrl-1 = <&pinctrl_flexspi1>; + /* + * For this spi-nor on M.2 card, need first enable the VPCIe_3.3v. + * Note, VPCIe_3.3v need about 1.74ms to change from 0v to 3.3v. + * U-boot already enable VPCIe_3.3v, so in linux, can ignore this + * 1.7ms, if u-boot do not eanble VPCIe_3.3v first, then need to + * take care of the 1.74ms delay, better to build the flexspi driver + * as module in driver to avoid spi-nor probe fail. + */ + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>, /* enable VPCIe_3v3 */ + <&pcal6524 20 GPIO_ACTIVE_HIGH>, /* enable SPI-NOR VCC 1.8v */ + <&pcal6524 12 GPIO_ACTIVE_HIGH>; /* put SPI-NOR RST pin to 1.8v */ + status = "okay"; + + mt25qu512abb8e12: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins = < + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x3fe + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x3fe + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x3fe + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x3fe + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-i3c.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-i3c.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-i3c.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-i3c.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk.dts" + +/{ + aliases { + /delete-property/ i2c0; + }; +}; + +/delete-node/&lpi2c1; + +/* + * When add i2c devices on i3c bus, the reg property should be changed to: + * reg = <0x1a 0x00 0x50>; + * The first byte is still the address of the i2c device; + * The second byte is always 0x00; + * The third byte is the communication speed of this i2c device; + * 0x20 means 1MHz(FM+); + * 0x50 means 400KHz(FM); + * In compatibility mode, I3C will use the slowest setting of all targets + * for i2c communication. + */ +&i3c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i3c1>; + pinctrl-1 = <&pinctrl_i3c1>; + i2c-scl-hz = <400000>; + status = "okay"; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d 0x00 0x50>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_to_dsi: endpoint { + remote-endpoint = <&dsi_to_adv7535>; + }; + }; + }; + + /* i3c device with static i2c address*/ + lsm6dso_i3c: imu@6a,208006c0000 { + reg = <0x6a 0x208 0x6c0000>; + assigned-address = <0x6a>; + }; + + /* i2c devices */ + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a 0x00 0x50>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; + +&iomuxc { + pinctrl_i3c1: i3c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__I3C1_SCL 0x4000019e + MX93_PAD_I2C1_SDA__I3C1_SDA 0x4000019e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-inmate.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-inmate.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-inmate.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-inmate.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include + +/ { + model = "NXP i.MX93 11x11 EVK"; + compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + mmc0 = &usdhc1; + serial1 = &lpuart2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48040000 0 0xc0000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + clk_400m: clock-400m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 227 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x80000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + lpuart2: serial@44390000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = ; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = ; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + }; +}; + +&lpuart2 { + clocks = <&osc_24m>; + clock-names = "ipg"; + status = "okay"; +}; + +&usdhc1 { + clocks = <&clk_dummy>, + <&clk_dummy>, + <&clk_400m>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-ld.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-ld.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-ld.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-ld.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx93-11x11-evk.dts" + +&flexspi1 { + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&lpm { + ld-mode-enabled; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX93_CLK_USDHC1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX93_CLK_USDHC2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX93_CLK_USDHC3>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpspi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpspi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpspi.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk.dts" + +&flexcan2 { + status = "disabled"; +}; + +&lpuart7 { + status = "disabled"; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + pinctrl-assert-gpios = <&adp5585gpio 4 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "lwn,bk4"; + spi-max-frequency = <1000000>; + }; +}; + +&iomuxc { + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__GPIO2_IO08 0x3fe + MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe + MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe + MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe + >; + }; +}; \ No newline at end of file diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpspi-slave.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpspi-slave.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpspi-slave.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk-lpspi.dts" + +/delete-node/&spidev0; + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + /delete-property/ cs-gpios; + + spi-slave; +}; + +&iomuxc { + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x3fe + MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe + MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe + MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe + >; + }; +}; \ No newline at end of file diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpuart.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpuart.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpuart.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-lpuart.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk.dts" + +/* Unbind lpuart5 from Bluetooth, use it for lpuart test. */ +&lpuart5 { + /delete-node/ bluetooth; +}; + +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +/* + * uart test port1. Note: don't use Bluetooth at the sametime. + * J1001: Pin27--TX Pin28--RX Pin3--CTS Pin5--RTS + */ +&pinctrl_uart5 { + fsl,pins = < + MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e + MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e + MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e + MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e + >; +}; + +&iomuxc { +/* uart test port2: J1001: Pin7--TX Pin29--RX Pin31--CTS Pin26--RTS */ + pinctrl_uart6: uart6grp { + fsl,pins = < + MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e + MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e + MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x31e + MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-mqs.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-mqs.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-mqs.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-mqs.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk.dts" + +/ { + reg_audio_switch: regulator-audio-switch { + compatible = "regulator-fixed"; + regulator-name = "audio-switch"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585gpio 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-cpu = <&sai1>; + audio-codec = <&mqs1>; + }; +}; + +&sai1 { + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&mqs1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs1>; + clocks = <&clk IMX93_CLK_MQS1_GATE>; + clock-names = "mclk"; + status = "okay"; +}; + +&micfil { + status = "disabled"; +}; + +&iomuxc { + pinctrl_mqs1: mqs1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__MQS1_LEFT 0x31e + MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-mt9m114.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-mt9m114.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-mt9m114.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-mt9m114.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk.dts" + +/ { + reg_mt9m114_dovdd: regulator-mt9m114-dovdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-dovdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <0>; + off-on-delay-us = <1000>; + gpio = <&pca9538 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_avdd: regulator-mt9m114-avdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <200>; + off-on-delay-us = <500>; + gpio = <&pca9538 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_dvdd: regulator-mt9m114-dvdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-dvdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <500>; + off-on-delay-us = <200>; + gpio = <&pca9538 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_extclk: regulator-mt9m114-extclk { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-extclk"; + startup-delay-us = <1000>; + off-on-delay-us = <0>; + gpio = <&pca9538 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_ctrl_9509: regulator-mt9m114-ctrl-9509 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-9509"; + gpio = <&pca9538 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mt9m114_ctrl_4t245: regulator-mt9m114-ctrl-4t245 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-4t245"; + gpio = <&pca9538 5 GPIO_ACTIVE_HIGH>; + enable-active-low; + regulator-always-on; + }; + + reg_mt9m114_ctrl_16t245: regulator-mt9m114-ctrl-16t245 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-16t245"; + gpio = <&pca9538 6 GPIO_ACTIVE_HIGH>; + enable-active-low; + regulator-always-on; + }; +}; + +&iomuxc { + pinctrl_parallel_csi: ci_pi { + fsl,pins = < + MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0xb9e + MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0xb9e + MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0xb9e + MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0xb9e + MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0xb9e + MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0xb9e + MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0xb9e + MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0xb9e + MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0xb9e + MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0xb9e + + MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0xb9e + MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0xb9e + MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0xb9e + MX93_PAD_GPIO_IO05__GPIO2_IO05 0x31e + MX93_PAD_GPIO_IO04__GPIO2_IO04 0x31e + >; + }; + + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = < + MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x40000b9e + MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x40000b9e + >; + }; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +&isi_0 { + interface = <6 0 2>; + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&mt9m114_ep>; + }; + }; +}; + +&mipi_csi { + status = "disabled"; +}; + +&lpi2c8 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8>; + pinctrl-assert-gpios = <&adp5585gpio 4 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9538: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + mt9m114: mt9m114@48 { + compatible = "on,mt9m114"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + reset-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + DOVDD-supply = <®_mt9m114_dovdd>; + AVDD-supply = <®_mt9m114_avdd>; + DVDD-supply = <®_mt9m114_dvdd>; + EXTCLK-supply = <®_mt9m114_extclk>; + mclk = <27000000>; + status = "okay"; + + port { + mt9m114_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; +}; + +&adp5585_isp { + status = "disabled"; +}; + +&ap1302 { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rm67199.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-11x11-evk.dts" + +&adv7535 { + status = "disabled"; +}; + +/delete-node/ &dsi_to_adv7535; +/delete-node/ &adv7535_to_dsi; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "raydium,rm67199"; + reg = <0>; + reset-gpio = <&adp5585gpio 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + width-mm = <68>; + height-mm = <121>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&lcdif { + assigned-clock-rates = <484000000>, <121000000>, <400000000>, <133333333>; +}; + +&lpi2c1 { + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + interrupt-parent = <&pcal6524>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&adp5585gpio 9 GPIO_ACTIVE_HIGH>; + edge-failling-trigger; + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-root.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-root.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-root.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-root.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include "imx93-11x11-evk.dts" + +/{ + interrupt-parent = <&gic>; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; +}; + +&clk { + init-on-array = ; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX93_PAD_UART2_TXD__LPUART2_TX 0x31e + MX93_PAD_UART2_RXD__LPUART2_RX 0x31e + >; + }; +}; + +&lpuart2 { + /delete-property/ dmas; + /delete-property/ dma-names; + status = "disabled"; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>; + assigned-clocks = <&clk IMX93_CLK_LPUART2>; + assigned-clock-parents = <&clk IMX93_CLK_24M>; +}; + +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc1_200mhz>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rpmsg.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx93-11x11-evk.dts" + +/delete-node/ &lpi2c1; +/delete-node/ ðosu_mem; + +/ { + /delete-node/ ethosu; + + aliases { + i2c0 = &i2c_rpbus_1; + }; + + reserved-memory { + micfil_reserved: micfil-rpmsg@a4220000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4220000 0 0x100000>; + no-map; + }; + + m33_reserved: m33@a5000000 { + no-map; + reg = <0 0xa5000000 0 0x1000000>; + }; + + audio_reserved: audio-rpmsg@c0000000 { + compatible = "shared-dma-pool"; + reg = <0 0xc0000000 0 0x10000000>; + no-map; + }; + }; + + sound-wm8962 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + sound-xcvr { + status = "disabled"; + }; + + rpmsg_audio: rpmsg_audio { + compatible = "fsl,imx93-rpmsg-audio"; + model = "wm8962-audio"; + fsl,platform = "rpmsg-audio-channel"; + fsl,enable-lpa; + fsl,rpmsg-out; + fsl,rpmsg-in; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, + <&clk IMX93_CLK_SAI3_GATE>, + <&clk IMX93_CLK_EDMA2_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "ipg", "mclk", "dma", "pll8k"; + audio-codec = <&codec>; + memory-region = <&audio_reserved>; + audio-routing = + "IN1R", "MICBIAS", + "IN1L", "MICBIAS"; + fsl,lpa-widgets = + "HPOUTL", "HPOUTR", "Playback", + "Capture", "IN1L", "IN1R"; + status = "okay"; + }; + + rpmsg_micfil: rpmsg_micfil { + compatible = "fsl,imx93-rpmsg-audio"; + model = "micfil-audio"; + fsl,platform = "rpmsg-micfil-channel"; + fsl,enable-lpa; + fsl,rpmsg-in; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + clocks = <&clk IMX93_CLK_PDM_IPG>, + <&clk IMX93_CLK_PDM_GATE>, + <&clk IMX93_CLK_EDMA1_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "ipg", "mclk", "dma", "pll8k"; + memory-region = <&micfil_reserved>; + status = "okay"; + }; + + i2c_rpbus_1: i2c-rpbus-1 { + compatible = "fsl,i2c-rpbus-v2"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_to_dsi: endpoint { + remote-endpoint = <&dsi_to_adv7535>; + }; + }; + }; + + lsm6dsm@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; + }; +}; + +&lpi2c2 { + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&lpi2c3 { + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&sai3 { + status = "disabled"; +}; + +&micfil { + status = "disabled"; +}; + +&edma1{ + status = "disabled"; +}; + +&edma2{ + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; + +&xcvr { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rpmsg-lpv.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rpmsg-lpv.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rpmsg-lpv.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-11x11-evk-rpmsg-lpv.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +/dts-v1/; + +#include "imx93-11x11-evk-rpmsg.dts" + +&rpmsg_audio { + /delete-property/ fsl,enable-lpa; + /delete-property/ fsl,rpmsg-in; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-aud-hat.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-aud-hat.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-aud-hat.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-aud-hat.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx93-14x14-evk.dts" + +/ { + mic-leds { + compatible = "gpio-leds"; + mic0 { + label = "mic0"; + gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic1 { + label = "mic1"; + gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic2 { + label = "mic2"; + gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic3 { + label = "mic3"; + gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic4 { + label = "mic4"; + gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic5 { + label = "mic5"; + gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic6 { + label = "mic6"; + gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic7 { + label = "mic7"; + gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sw-keys { + compatible = "gpio-keys"; + + sw4: volume-down { + label = "Volume Down"; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; + + sw3: volume-up { + label = "Volume Up"; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + }; + + sw2: volume-mute { + label = "Volume Mute"; + gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; + + sw1: key-act { + label = "Key Act"; + gpios = <&pca9555 12 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + reg_vddext_3v3: regulator-vddext { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_exp_sel: regulator-exp-sel { + compatible = "regulator-fixed"; + regulator-name = "exp-sel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524_2 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_pwr>; + regulator-name = "cs42448-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-cs42448 { + compatible = "fsl,imx-audio-card"; + model = "imx-cs42448"; + status = "okay"; + pri-dai-link { + link-name = "cs42448"; + format = "dsp_a"; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai3>; + }; + codec { + sound-dai = <&cs42448>; + }; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3audhat>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + fsl,sai-asynchronous; + status = "okay"; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&lpi2c4 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + dmas = <&edma2 10 0 0>, <&edma2 11 0 1>; + dma-names = "tx","rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4>; + status = "okay"; + + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pushbutton_irq>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_vddext_3v3>; + status = "okay"; + }; + + cs42448: audio-codec@48 { + #sound-dai-cells = <0>; + compatible = "cirrus,cs42448"; + reg = <0x48>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + clock-names = "mclk"; + VA-supply = <®_audio_pwr>; + VD-supply = <®_audio_pwr>; + VLS-supply = <®_audio_pwr>; + VLC-supply = <®_audio_pwr>; + reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_swpdm_mute_irq: swpdmmutegrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e + >; + }; + + pinctrl_pushbutton_irq: pushbuttonirqgrp { + fsl,pins = < + MX93_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX93_PAD_GPIO_IO04__PDM_CLK 0x31e + MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x31e + MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x31e + MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x31e + MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x31e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x40000b9e + MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x40000b9e + >; + }; + + pinctrl_sai3audhat: sai3audhatgrp { + fsl,pins = < + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x31e + MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_audio_pwr: audiopwrgrp { + fsl,pins = < + MX93_PAD_GPIO_IO01__GPIO2_IO01 0x31e + >; + }; +}; + +&flexcan2 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-dsi-serdes.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-dsi-serdes.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-dsi-serdes.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-dsi-serdes.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-14x14-evk.dts" + +&adv7535 { + status = "disabled"; +}; + +/delete-node/ &dsi_to_adv7535; +/delete-node/ &adv7535_to_dsi; + +&dsi { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&max96789_dsi_a_in>; + }; + }; + }; +}; + +&lpi2c1 { + max96789: mipi_dsi_serializer@40 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "maxim,max96789"; + reg = <0x40>; + v12p0-supply = <®_vdd_12v>; + status = "okay"; + + maxim,gmsl-links-types = <2 2>; + maxim,gmsl2-link-speed = <6>; + maxim,gmsl2-dual-link; + + /* DSI port 0 */ + max96789_dsi_bridge@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + compatible = "maxim,max96789-dsi"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + max96789_dsi_a_in: endpoint@0 { + reg = <0>; + + remote-endpoint = <&dsi_out>; + data-lanes = <1 2 3 4>; + }; + + max96789_video_out: endpoint@1 { + reg = <1>; + + remote-endpoint = <&max96752_video_in>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + /* gmsl a */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + max96752: mipi_dsi_deserializer@48 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "maxim,max96752"; + reg = <0x48>; + status = "okay"; + + maxim,gmsl2-link-speed = <6>; + maxim,gmsl2-dual-link; + + max96752_lvds_bridge { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "maxim,max96752-lvds"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + max96752_video_in: endpoint@0 { + reg = <0>; + + remote-endpoint = <&max96789_video_out>; + }; + + max96752_lvds_a_out: endpoint@1 { + reg = <1>; + + remote-endpoint = <&it6263_in>; + }; + }; + }; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_in: endpoint { + remote-endpoint = <&max96752_lvds_a_out>; + }; + }; + }; + }; + }; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,915 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include +#include "imx93.dtsi" + +&ele_mu { + memory-region = <&ele_reserved>; +}; + +/ { + model = "NXP i.MX93 14X14 EVK board"; + compatible = "fsl,imx93-14x14-evk", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + + ethosu_mem: ethosu_region@C0000000 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 0xC0000000 0x0 0x10000000>; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + + ele_reserved: ele-reserved@a4120000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + cm33: imx93-cm33 { + compatible = "fsl,imx93-cm33"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1 + &mu1 1 1 + &mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + fsl,startup-delay-ms = <500>; + }; + + ethosu { + compatible = "arm,ethosu"; + fsl,cm33-proc = <&cm33>; + memory-region = <ðosu_mem>; + power-domains = <&mlmix>; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524_2 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can1_en>; + }; + + reg_can1_en: regulator-can1-en { + compatible = "regulator-fixed"; + regulator-name = "can1-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524_2 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524_2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can2_en>; + }; + + reg_can2_en: regulator-can2-en { + compatible = "regulator-fixed"; + regulator-name = "can2-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524_2 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_vdd_12v: regulator-vdd-12v { + compatible = "regulator-fixed"; + regulator-name = "reg_vdd_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; + + reg_usdhc3_vmmc: usdhc3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "M2_WiFi_ON"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_dvdd_sel: regulator-dvdd_sel { + compatible = "regulator-fixed"; + regulator-name = "DVDD_SEL"; + gpio = <&adp5585gpio_isp 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <2000>; + }; + + reg_dvdd_1v2: regulator-dvdd { + compatible = "regulator-fixed"; + regulator-name = "DVDD_1V2"; + gpio = <&adp5585gpio_isp 6 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + enable-active-high; + vin-supply = <®_dvdd_sel>; + }; + + reg_vdd_3v3: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + gpio = <&adp5585gpio_isp 5 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <4000>; + enable-active-high; + }; + + reg_vddio_1v8: regulator-vddo { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_1V8"; + gpio = <&adp5585gpio_isp 9 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <4000>; + enable-active-high; + vin-supply = <®_vdd_3v3>; + }; + + reg_vaa_sel: regulator-vaa_sel { + compatible = "regulator-fixed"; + regulator-name = "VAA_SEL"; + gpio = <&adp5585gpio_isp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_avdd_2v8: regulator-avdd { + compatible = "regulator-fixed"; + regulator-name = "AVDD_2V8"; + gpio = <&adp5585gpio_isp 7 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + vin-supply = <®_vaa_sel>; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + pri-dai-link { + link-name = "XCVR PCM"; + cpu { + sound-dai = <&xcvr>; + }; + }; + }; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&xcvr { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_SPDIF_GATE>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUD_XCVR_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SPDIF>, + <&clk IMX93_CLK_AUDIO_XCVR>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <12288000>, <200000000>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&dphy { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_to_adv7535: endpoint { + remote-endpoint = <&adv7535_to_dsi>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + eee-broken-1000t; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&lcdif { + status = "okay"; + assigned-clock-rates = <445333333>, <148444444>, <400000000>, <133333333>; +}; + +/* + * When add, delete or change any target device setting in &lpi2c1, + * please synchronize the changes to the &i3c1 bus in imx93-11x11-evk-i3c.dts. + */ +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_to_dsi: endpoint { + remote-endpoint = <&dsi_to_adv7535>; + }; + }; + }; + + lsm6dsm@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9452"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + pcal6524_2: gpio@20 { + compatible = "nxp,pcal6524"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + adp5585_isp: mfd-isp@34 { + compatible = "adi,adp5585"; + reg = <0x34>; + status = "okay"; + + adp5585gpio_isp: gpio-isp@34 { + compatible = "adp5585-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + adp5585pwm_isp: pwm-isp@34 { + compatible = "adp5585-pwm"; + #pwm-cells = <3>; + }; + }; + + ap1302: ap1302_mipi@3c { + compatible = "onsemi,ap1302"; + reg = <0x3c>; + reset-gpios = <&pcal6524_2 0 GPIO_ACTIVE_LOW>; + isp_en-gpios = <&adp5585gpio_isp 2 GPIO_ACTIVE_HIGH>; + DVDD-supply = <®_dvdd_1v2>; + VDDIO-supply = <®_vddio_1v8>; + AVDD-supply = <®_avdd_2v8>; + status = "okay"; + + port { + ar1302_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi_ep>; + }; + }; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-assert-gpios = <&pcal6524 19 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + mmc-pwrseq = <&usdhc3_pwrseq>; + vmmc-supply = <®_usdhc3_vmmc>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; +}; + +&epxp { + status = "okay"; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&mipi_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi_ep: endpoint { + remote-endpoint = <&ar1302_mipi_ep>; + data-lanes = <2>; + cfg-clk-range = <28>; + hs-clk-range = <0x2b>; + bus-type = <4>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-flexspi-m2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-flexspi-m2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-flexspi-m2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-flexspi-m2.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx93-14x14-evk.dts" + +&usdhc3_pwrseq { + status = "disabled"; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexspi1>; + pinctrl-1 = <&pinctrl_flexspi1>; + pinctrl-assert-gpios = <&pcal6524 20 GPIO_ACTIVE_HIGH>, /* enable SPI-NOR VCC 1.8v */ + <&pcal6524 12 GPIO_ACTIVE_HIGH>; /* put SPI-NOR RST pin to 1.8v */ + status = "okay"; + + mt25qu512abb8e12: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins = < + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x3fe + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x3fe + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x3fe + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x3fe + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-lvds-it6263.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-lvds-it6263.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-lvds-it6263.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-lvds-it6263.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx93-14x14-evk.dts" + +&adv7535 { + status = "disabled"; +}; + +&dphy { + status = "disabled"; +}; + +&dsi { + status = "disabled"; +}; + + +&lcdif { + status = "okay"; + assigned-clock-rates = <1039500000>, <148444444>, <400000000>, <133333333>; +}; + +&lpi2c1 { + lvds_bridge: lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpio = <&pcal6524_2 6 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&ldb_out>; + }; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@1 { + reg = <1>; + + ldb_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&ldb_phy { + status = "okay"; +}; + +&iomuxc { + pinctrl_ctp_int: ctp_int_grp { + fsl,pins = < + MX93_PAD_GPIO_IO21__GPIO2_IO21 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-mqs.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-mqs.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-mqs.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-mqs.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx93-14x14-evk.dts" + +/ { + reg_mqs_switch: regulator-mqs-switch { + compatible = "regulator-fixed"; + regulator-name = "mqs-switch"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524_2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mqs_amp_en: regulator-mqs-amp-en { + compatible = "regulator-fixed"; + regulator-name = "mqs-amp-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524_2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-cpu = <&sai1>; + audio-codec = <&mqs1>; + }; + + sound-bt-sco { + status = "disabled"; + }; +}; + +&flexcan1 { + status = "disabled"; +}; + +&sai1 { + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&mqs1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs1>; + clocks = <&clk IMX93_CLK_MQS1_GATE>; + clock-names = "mclk"; + status = "okay"; +}; + +&iomuxc { + pinctrl_mqs1: mqs1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__MQS1_LEFT 0x31e + MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-rm67199.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-rm67199.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-rm67199.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-rm67199.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-14x14-evk.dts" + +&adv7535 { + status = "disabled"; +}; + +/delete-node/ &dsi_to_adv7535; +/delete-node/ &adv7535_to_dsi; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "raydium,rm67199"; + reg = <0>; + reset-gpio = <&pcal6524_2 4 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + width-mm = <68>; + height-mm = <121>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&lcdif { + assigned-clock-rates = <484000000>, <121000000>, <400000000>, <133333333>; +}; + +&lpi2c1 { + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + interrupt-parent = <&pcal6524>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pcal6524_2 7 GPIO_ACTIVE_HIGH>; + edge-failling-trigger; + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-sja1105.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-sja1105.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-sja1105.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-sja1105.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx93-14x14-evk.dts" + +/ { + clock_sja1105: clock-sja1105 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&lpi2c2 { + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_rgmii>; + phy-mode = "rgmii-rxid"; + phy-handle = <&fixed0>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_LOW>; + clk_csr = <5>; + status = "okay"; + + fixed0: fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <2500000>; + + phy0: ethernet-phy@8 { + reg = <0x8>; + max-speed = <100>; + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@9 { + reg = <0x9>; + max-speed = <100>; + }; + }; + + phy2: ethernet-phy@e { + reg = <0xe>; + max-speed = <100>; + #address-cells = <1>; + #size-cells = <0>; + + phy3: ethernet-phy@f { + reg = <0xf>; + max-speed = <100>; + }; + }; + + }; +}; + +&lpspi8 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi8>; + assigned-clocks = <&clk IMX93_CLK_LPSPI8>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>; + cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + /delete-property/ dma-names; + /delete-property/ dmas; + pinctrl-assert-gpios = <&pcal6524_2 3 GPIO_ACTIVE_LOW>; + status = "okay"; + + sja1105@0 { + compatible = "nxp,sja1105q"; + reg = <0x0>; + spi-max-frequency = <12500000>; + spi-cpha; + clocks = <&clock_sja1105>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&eqos>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "swp1"; + phy-handle = <&phy0>; + phy-mode = "mii"; + }; + + port@2 { + reg = <2>; + label = "swp2"; + phy-handle = <&phy1>; + phy-mode = "mii"; + }; + + port@3 { + reg = <3>; + label = "swp3"; + phy-handle = <&phy2>; + phy-mode = "rmii"; + }; + + port@4 { + reg = <4>; + label = "swp4"; + phy-handle = <&phy3>; + phy-mode = "rmii"; + }; + + }; + }; +}; + +&iomuxc { + pinctrl_lpspi8: lpspi8grp { + fsl,pins = < + MX93_PAD_GPIO_IO12__GPIO2_IO12 0x3fe + MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x3fe + MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x3fe + MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x3fe + >; + }; + + pinctrl_eqos_rgmii: eqosrgmiigrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x57e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x57e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-tja1103.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-tja1103.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-14x14-evk-tja1103.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-14x14-evk-tja1103.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx93-14x14-evk.dts" + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_rmii>; + phy-mode = "rmii"; + phy-handle = <&eqosphy>; + + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>; + + clk_csr = <5>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <2500000>; + reset-delay-us = <100000>; + reset-post-delay-us = <500000>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + + eqosphy: ethernet-phy@2 { + reg = <2>; + }; + }; +}; + +&iomuxc { + pinctrl_eqos_rmii: eqosrmiigrp { + fsl,pins = < + MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000057e + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x57e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-aud-hat.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-aud-hat.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-aud-hat.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-aud-hat.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + * + * Short J1710 and J1711 to use AUD-HAT Board + */ + +#include "imx93-9x9-qsb.dts" + +/ { + mic_leds { + compatible = "gpio-leds"; + mic0 { + label = "mic0"; + gpios = <&pca9555 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic1 { + label = "mic1"; + gpios = <&pca9555 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic2 { + label = "mic2"; + gpios = <&pca9555 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic3 { + label = "mic3"; + gpios = <&pca9555 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic4 { + label = "mic4"; + gpios = <&pca9555 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic5 { + label = "mic5"; + gpios = <&pca9555 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic6 { + label = "mic6"; + gpios = <&pca9555 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + mic7 { + label = "mic7"; + gpios = <&pca9555 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sw_keys { + compatible = "gpio-keys"; + + sw4: volume_down { + label = "Volume Down"; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; + + sw3: volume_up { + label = "Volume Up"; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + }; + + sw2: volume_mute { + label = "Volume Mute"; + gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; + + sw1: key_act { + label = "Key Act"; + gpios = <&pca9555 12 GPIO_ACTIVE_LOW>; + linux,code = ; + interrupt-parent = <&pca9555>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + reg_vddext_5v: regulator-vddext { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_pwr>; + regulator-name = "cs42448-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-wm8962 { + status = "disabled"; + }; + + sound-cs42448 { + compatible = "fsl,imx-audio-card"; + model = "imx-cs42448"; + status = "okay"; + pri-dai-link { + link-name = "cs42448"; + format = "dsp_a"; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + fsl,mclk-equal-bclk; + cpu { + sound-dai = <&sai3>; + }; + codec { + sound-dai = <&cs42448>; + }; + }; + }; + +}; + +®_rpi_3v3 { + regulator-always-on; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3audhat>; + pinctrl-assert-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm2>; + status = "okay"; +}; + +&lpi2c4 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + dmas = <&edma2 10 0 0>, <&edma2 11 0 1>; + dma-names = "tx","rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4>; + status = "okay"; + + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&pcal6524>; + interrupts = <8 IRQ_TYPE_EDGE_BOTH>; + vcc-supply = <®_rpi_3v3>; + status = "okay"; + }; + + cs42448: cs42448@48 { + #sound-dai-cells = <0>; + compatible = "cirrus,cs42448"; + reg = <0x48>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + clock-names = "mclk"; + VA-supply = <®_rpi_3v3>; + VD-supply = <®_vddext_5v>; + VLS-supply = <®_audio_pwr>; + VLC-supply = <®_audio_pwr>; + reset-gpio = <&pcal6524 6 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_swpdm_mute_irq: swpdm_mute_grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e + >; + }; + + pinctrl_pdm2: pdm2grp { + fsl,pins = < + MX93_PAD_GPIO_IO04__PDM_CLK 0x31e + MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x31e + MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x31e + MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x31e + MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x31e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x40000b9e + MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x40000b9e + >; + }; + + pinctrl_sai3audhat: sai3audhat { + fsl,pins = < + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x31e + MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x4000031e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_audio_pwr: audiopwrgrp { + fsl,pins = < + MX93_PAD_GPIO_IO01__GPIO2_IO01 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-9x9-qsb.dts" + +/{ + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 23 GPIO_ACTIVE_LOW>; + enable-active-low; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + /* config the MIC/CAN_SEL to high, chose B port */ + pinctrl-assert-gpios = <&pcal6524 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* micfi1 use the A port, conflict with can1 */ +&micfil { + status = "disabled"; +}; + +&iomuxc { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,794 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include +#include "imx93.dtsi" + +&ele_mu { + memory-region = <&ele_reserved>; +}; + +/ { + model = "NXP i.MX93 9x9 Quick Start Board"; + compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + + ethosu_mem: ethosu_region@C0000000 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 0xC0000000 0x0 0x10000000>; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + + ele_reserved: ele-reserved@a4120000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + cm33: imx93-cm33 { + compatible = "fsl,imx93-cm33"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1 + &mu1 1 1 + &mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + fsl,startup-delay-ms = <500>; + }; + + ethosu { + compatible = "arm,ethosu"; + fsl,cm33-proc = <&cm33>; + memory-region = <ðosu_mem>; + power-domains = <&mlmix>; + }; + + reg_rpi_3v3: regulator-rpi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + regulator-name = "VDD_RPI_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_vdd_3v3: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&lpm { + soc-supply = <&buck1>; + status = "okay"; +}; + +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + lsm6dsm@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-assert-gpios = <&pcal6524 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-assert-gpios = <&pcal6524 17 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-assert-gpios = <&pcal6524 22 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + fsl,sai-synchronous-rx; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + mmc-pwrseq = <&usdhc3_pwrseq>; + vmmc-supply = <®_usdhc3_vmmc>; + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&pcal6524>; + /* pcal6524 IO expander limitation: only support edge-triggered irq */ + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x31e + MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__PDM_CLK 0x31e + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e + >; + }; +}; + +&epxp { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-flexspi-m2.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-flexspi-m2.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-flexspi-m2.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-flexspi-m2.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-9x9-qsb.dts" + +&usdhc3_pwrseq { + status = "disabled"; +}; + +&usdhc3 { + status = "disabled"; +}; + +&flexspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexspi1>; + pinctrl-1 = <&pinctrl_flexspi1>; + /* + * For this spi-nor on M.2 card, need first enable the VPCIe_3.3v. + * Note, VPCIe_3.3v need about 1.74ms to change from 0v to 3.3v. + * U-boot already enable VPCIe_3.3v, so in linux, can ignore this + * 1.7ms, if u-boot do not eanble VPCIe_3.3v first, then need to + * take care of the 1.74ms delay, better to build the flexspi driver + * as module in driver to avoid spi-nor probe fail. + */ + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>, /* enable VPCIe_3v3 */ + <&pcal6524 20 GPIO_ACTIVE_HIGH>, /* enable SPI-NOR VCC 1.8v */ + <&pcal6524 12 GPIO_ACTIVE_HIGH>; /* put SPI-NOR RST pin to 1.8v */ + status = "okay"; + + mt25qu512abb8e12: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins = < + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x3fe + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x3fe + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x3fe + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x3fe + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-9x9-qsb.dts" + +/{ + aliases { + /delete-property/ i2c0; + }; +}; + +/delete-node/&lpi2c1; + +/* + * When add i2c devices on i3c bus, the reg property should be changed to: + * reg = <0x1a 0x00 0x50>; + * The first byte is still the address of the i2c device; + * The second byte is always 0x00; + * The third byte is the communication speed of this i2c device; + * 0x20 means 1MHz(FM+); + * 0x50 means 400KHz(FM); + * In compatibility mode, I3C will use the slowest setting of all targets + * for i2c communication. + */ +&i3c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i3c1>; + pinctrl-1 = <&pinctrl_i3c1>; + i2c-scl-hz = <400000>; + status = "okay"; + + /* i2c device */ + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a 0x00 0x50>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50 0x00 0x50>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + /* i3c device with static i2c address*/ + lsm6dso_i3c: imu@6a,208006c0000 { + reg = <0x6a 0x208 0x6c0000>; + assigned-address = <0x6a>; + }; +}; + +&iomuxc { + pinctrl_i3c1: i3c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__I3C1_SCL 0x4000019e + MX93_PAD_I2C1_SDA__I3C1_SDA 0x4000019e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ld.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ld.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ld.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ld.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx93-9x9-qsb.dts" + +&flexspi1 { + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&lpm { + ld-mode-enabled; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX93_CLK_USDHC1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX93_CLK_USDHC2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX93_CLK_USDHC3>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <266000000>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-lpspi.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-lpspi.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-lpspi.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-lpspi.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-9x9-qsb.dts" + +&sai3 { + status = "disabled"; +}; + +&lpspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + /* + * Switch the SPI pins to RPi connector for testing. + * It will also control the pins of SAI3, so SAI3 is disabled above. + */ + pinctrl-assert-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "lwn,bk4"; + spi-max-frequency = <1000000>; + }; +}; + +&iomuxc { + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__GPIO2_IO08 0x3fe + MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe + MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe + MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe + >; + }; +}; \ No newline at end of file diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-lpspi-slave.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-lpspi-slave.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-lpspi-slave.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-lpspi-slave.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-9x9-qsb-lpspi.dts" + +&lpspi3 { + #address-cells = <0>; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-1 = <&pinctrl_lpspi3>; + spi-slave; + /delete-property/ cs-gpios; + /delete-node/ spi@0; +}; + +&iomuxc { + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x3fe + MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe + MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe + MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe + >; + }; +}; \ No newline at end of file diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-mt9m114.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-mt9m114.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-mt9m114.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-mt9m114.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-9x9-qsb.dts" + +/ { + reg_mt9m114_dovdd: regulator-mt9m114-dovdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-dovdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <0>; + off-on-delay-us = <1000>; + gpio = <&pca9538 0 GPIO_ACTIVE_HIGH>; + vin-supply = <®_rpi_3v3>; + enable-active-high; + }; + + reg_mt9m114_avdd: regulator-mt9m114-avdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <200>; + off-on-delay-us = <500>; + gpio = <&pca9538 1 GPIO_ACTIVE_HIGH>; + vin-supply = <®_rpi_3v3>; + enable-active-high; + }; + + reg_mt9m114_dvdd: regulator-mt9m114-dvdd { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-dvdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <500>; + off-on-delay-us = <200>; + gpio = <&pca9538 2 GPIO_ACTIVE_HIGH>; + vin-supply = <®_rpi_3v3>; + enable-active-high; + }; + + reg_mt9m114_extclk: regulator-mt9m114-extclk { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-extclk"; + startup-delay-us = <1000>; + off-on-delay-us = <0>; + gpio = <&pca9538 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mt9m114_ctrl_9509: regulator-mt9m114-ctrl-9509 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-9509"; + gpio = <&pca9538 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mt9m114_ctrl_4t245: regulator-mt9m114-ctrl-4t245 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-4t245"; + gpio = <&pca9538 5 GPIO_ACTIVE_HIGH>; + enable-active-low; + regulator-always-on; + }; + + reg_mt9m114_ctrl_16t245: regulator-mt9m114-ctrl-16t245 { + compatible = "regulator-fixed"; + regulator-name = "mt9m114-ctrl-16t245"; + gpio = <&pca9538 6 GPIO_ACTIVE_HIGH>; + enable-active-low; + regulator-always-on; + }; +}; + +&iomuxc { + pinctrl_parallel_csi: ci_pi { + fsl,pins = < + MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0xb9e + MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0xb9e + MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0xb9e + MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0xb9e + MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0xb9e + MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0xb9e + MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0xb9e + MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0xb9e + MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0xb9e + MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0xb9e + + MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0xb9e + MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0xb9e + MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0xb9e + MX93_PAD_GPIO_IO05__GPIO2_IO05 0x31e + MX93_PAD_GPIO_IO04__GPIO2_IO04 0x31e + >; + }; + + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = < + MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x40000b9e + MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x40000b9e + >; + }; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +&isi_0 { + interface = <6 0 2>; + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&mt9m114_ep>; + }; + }; +}; + +&mipi_csi { + status = "disabled"; +}; + +&lpi2c8 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8>; + pinctrl-assert-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9538: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_rpi_3v3>; + status = "okay"; + }; + + mt9m114: mt9m114@48 { + compatible = "on,mt9m114"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + reset-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + DOVDD-supply = <®_mt9m114_dovdd>; + AVDD-supply = <®_mt9m114_avdd>; + DVDD-supply = <®_mt9m114_dvdd>; + EXTCLK-supply = <®_mt9m114_extclk>; + mclk = <27000000>; + status = "okay"; + + port { + mt9m114_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */ + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; +}; + +&sai3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-wvga-panel.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-wvga-panel.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-wvga-panel.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-wvga-panel.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-9x9-qsb.dts" + +/ { + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + }; + + panel { + compatible = "ontat,kd50g21-40nt-a1"; + backlight = <&backlight>; + power-supply = <®_rpi_3v3>; + enable-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; + assigned-clock-rates = <150000000>, <30000000>, <400000000>, <133333333>; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +¶llel_disp_fmt { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + fsl,interface-pix-fmt = "rgb666"; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +/* pin conflicts */ +&sai3 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-rpmsg.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-rpmsg.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-rpmsg.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-rpmsg.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +#include "imx93-9x9-qsb.dts" + +/delete-node/ &lpi2c1; +/delete-node/ ðosu_mem; + +/ { + /delete-node/ ethosu; + + aliases { + i2c0 = &i2c_rpbus_1; + }; + + reserved-memory { + micfil_reserved: micfil-rpmsg@a4220000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4220000 0 0x100000>; + no-map; + }; + + m33_reserved: m33@a5000000 { + no-map; + reg = <0 0xa5000000 0 0x1000000>; + }; + + audio_reserved: audio-rpmsg@c0000000 { + compatible = "shared-dma-pool"; + reg = <0 0xc0000000 0 0x10000000>; + no-map; + }; + }; + + sound-wm8962 { + status = "disabled"; + }; + + sound-micfil { + status = "disabled"; + }; + + sound-bt-sco { + status = "disabled"; + }; + + rpmsg_audio: rpmsg_audio { + compatible = "fsl,imx93-rpmsg-audio"; + model = "wm8962-audio"; + fsl,platform = "rpmsg-audio-channel"; + fsl,enable-lpa; + fsl,rpmsg-out; + fsl,rpmsg-in; + pinctrl-assert-gpios = <&pcal6524 22 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, + <&clk IMX93_CLK_SAI3_GATE>, + <&clk IMX93_CLK_EDMA2_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "ipg", "mclk", "dma", "pll8k"; + audio-codec = <&codec>; + memory-region = <&audio_reserved>; + audio-routing = + "IN1R", "MICBIAS", + "IN1L", "MICBIAS"; + fsl,lpa-widgets = + "HPOUTL", "HPOUTR", "Playback", + "Capture", "IN1L", "IN1R"; + status = "okay"; + }; + + rpmsg_micfil: rpmsg_micfil { + compatible = "fsl,imx93-rpmsg-audio"; + model = "micfil-audio"; + fsl,platform = "rpmsg-micfil-channel"; + fsl,enable-lpa; + fsl,rpmsg-in; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + clocks = <&clk IMX93_CLK_PDM_IPG>, + <&clk IMX93_CLK_PDM_GATE>, + <&clk IMX93_CLK_EDMA1_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "ipg", "mclk", "dma", "pll8k"; + memory-region = <&micfil_reserved>; + status = "okay"; + }; + + i2c_rpbus_1: i2c-rpbus-1 { + compatible = "fsl,i2c-rpbus-v2"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + lsm6dsm@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; + }; +}; + +&lpi2c2 { + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&lpi2c3 { + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&sai3 { + status = "disabled"; +}; + +&micfil { + status = "disabled"; +}; + +&edma1 { + status = "disabled"; +}; + +&edma2 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-rpmsg-lpv.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-rpmsg-lpv.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-rpmsg-lpv.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-rpmsg-lpv.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + */ + +/dts-v1/; + +#include "imx93-9x9-qsb-rpmsg.dts" + +&rpmsg_audio { + /delete-property/ fsl,enable-lpa; + /delete-property/ fsl,rpmsg-in; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -8,6 +8,7 @@ #include #include #include +#include #include "imx93-pinfunc.h" @@ -17,6 +18,10 @@ #size-cells = <2>; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; i2c0 = &lpi2c1; i2c1 = &lpi2c2; i2c2 = &lpi2c3; @@ -25,6 +30,8 @@ i2c5 = &lpi2c6; i2c6 = &lpi2c7; i2c7 = &lpi2c8; + ethernet0 = &fec; + ethernet1 = &eqos; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; @@ -36,18 +43,36 @@ serial5 = &lpuart6; serial6 = &lpuart7; serial7 = &lpuart8; + isi0 = &isi_0; + csi0 = &mipi_csi; + rtc0 = &bbnsm_rtc; }; cpus { #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <10000>; + exit-latency-us = <7000>; + min-residency-us = <27000>; + wakeup-latency-us = <15000>; + }; + }; + A55_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A55_1: cpu@100 { @@ -56,6 +81,7 @@ reg = <0x100>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; }; @@ -112,6 +138,38 @@ interrupt-parent = <&gic>; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -135,16 +193,113 @@ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; reg = <0x44230000 0x10000>; interrupts = ; + clocks = <&clk IMX93_CLK_MU1_B_GATE>; #mbox-cells = <2>; status = "disabled"; }; + edma1: dma-controller@44000000{ + compatible = "fsl,imx93-edma"; + reg = <0x44000000 0x10000>, + <0x44010000 0x10000>, <0x44020000 0x10000>, + <0x44030000 0x10000>, <0x44040000 0x10000>, + <0x44050000 0x10000>, <0x44060000 0x10000>, + <0x44070000 0x10000>, <0x44080000 0x10000>, + <0x44090000 0x10000>, <0x440a0000 0x10000>, + <0x440b0000 0x10000>, <0x440c0000 0x10000>, + <0x440d0000 0x10000>, <0x440e0000 0x10000>, + <0x440f0000 0x10000>, <0x44100000 0x10000>, + <0x44110000 0x10000>, <0x44120000 0x10000>, + <0x44130000 0x10000>, <0x44140000 0x10000>, + <0x44150000 0x10000>, <0x44160000 0x10000>, + <0x44170000 0x10000>, <0x44180000 0x10000>, + <0x44190000 0x10000>, <0x441a0000 0x10000>, + <0x441b0000 0x10000>, <0x441c0000 0x10000>, + <0x441d0000 0x10000>, <0x441e0000 0x10000>, + <0x441f0000 0x10000>; + #dma-cells = <3>; + dma-channels = <31>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx", + "edma1-chan2-tx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan6-tx", "edma1-chan7-tx", + "edma1-chan8-tx", "edma1-chan9-tx", + "edma1-chan10-tx", "edma1-chan11-tx", + "edma1-chan12-tx", "edma1-chan13-tx", + "edma1-chan14-tx", "edma1-chan15-tx", + "edma1-chan16-tx", "edma1-chan17-tx", + "edma1-chan18-tx", "edma1-chan19-tx", + "edma1-chan20-tx", "edma1-chan21-tx", + "edma1-chan22-tx", "edma1-chan23-tx", + "edma1-chan24-tx", "edma1-chan25-tx", + "edma1-chan26-tx", "edma1-chan27-tx", + "edma1-chan28-tx", "edma1-chan29-tx", + "edma1-chan30-tx", "edma1-err"; + clocks = <&clk IMX93_CLK_EDMA1_GATE>; + clock-names = "edma"; + status = "okay"; + }; + system_counter: timer@44290000 { compatible = "nxp,sysctr-timer"; reg = <0x44290000 0x30000>; interrupts = ; clocks = <&osc_24m>; clock-names = "per"; + nxp,no-divider; + }; + + tpm2: pwm@44320000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44320000 0x10000>; + clocks = <&clk IMX93_CLK_TPM2_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c1: i3c-master@44330000 { + #address-cells = <3>; + #size-cells = <0>; + compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; + reg = <0x44330000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; }; lpi2c1: i2c@44340000 { @@ -156,6 +311,8 @@ clocks = <&clk IMX93_CLK_LPI2C1_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 7 0 0>, <&edma1 8 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -168,6 +325,8 @@ clocks = <&clk IMX93_CLK_LPI2C2_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 9 0 0>, <&edma1 10 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -180,6 +339,8 @@ clocks = <&clk IMX93_CLK_LPSPI1_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 11 0 0>, <&edma1 12 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -192,11 +353,13 @@ clocks = <&clk IMX93_CLK_LPSPI2_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 13 0 0>, <&edma1 14 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; lpuart1: serial@44380000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x44380000 0x1000>; interrupts = ; clocks = <&clk IMX93_CLK_LPUART1_GATE>; @@ -205,11 +368,47 @@ }; lpuart2: serial@44390000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x44390000 0x1000>; interrupts = ; clocks = <&clk IMX93_CLK_LPUART2_GATE>; clock-names = "ipg"; + dmas = <&edma1 18 0 0>, <&edma1 19 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + flexcan1: can@443a0000 { + compatible = "fsl,imx93-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_CAN1_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&anomix_ns_gpr 0x14 0>; + status = "disabled"; + }; + + sai1: sai@443b0000 { + compatible = "fsl,imx93-sai"; + reg = <0x443b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 22 0 1>, <&edma1 21 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mqs1: mqs1 { + compatible = "fsl,imx93-mqs"; + gpr = <&anomix_ns_gpr>; status = "disabled"; }; @@ -219,12 +418,32 @@ status = "okay"; }; + bbnsm: bbnsm@44440000 { + compatible = "syscon", "simple-mfd"; + reg = <0x44440000 0x10000>; + + bbnsm_rtc: rtc { + compatible = "nxp,bbnsm-rtc"; + regmap = <&bbnsm>; + interrupts = ; + }; + + bbnsm_pwrkey: pwrkey { + compatible = "nxp,bbnsm-pwrkey"; + regmap = <&bbnsm>; + interrupts = ; + }; + }; + clk: clock-controller@44450000 { compatible = "fsl,imx93-ccm"; reg = <0x44450000 0x10000>; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; clock-names = "osc_32k", "osc_24m", "clk_ext1"; + assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>, <&clk IMX93_CLK_A55>; + assigned-clock-parents = <0>, <&clk IMX93_CLK_SYS_PLL_PFD0>; + assigned-clock-rates = <393216000>, <500000000>; status = "okay"; }; @@ -239,7 +458,7 @@ compatible = "fsl,imx93-src-slice"; reg = <0x44462400 0x400>, <0x44465800 0x400>; #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_MEDIA_AXI>, + clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, <&clk IMX93_CLK_MEDIA_APB>; }; @@ -256,6 +475,51 @@ compatible = "fsl,imx93-anatop", "syscon"; reg = <0x44480000 0x2000>; }; + + tmu: tmu@44482000 { + compatible = "fsl,imx93-tmu"; + reg = <0x44482000 0x1000>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + little-endian; + fsl,tmu-calibration = <0x0000000e 0x800000da + 0x00000029 0x800000e9 + 0x00000056 0x80000102 + 0x000000a2 0x8000012a + 0x00000116 0x80000166 + 0x00000195 0x800001a7 + 0x000001b2 0x800001b6>; + #thermal-sensor-cells = <1>; + }; + + micfil: micfil@44520000 { + compatible = "fsl,imx93-micfil"; + reg = <0x44520000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX93_CLK_PDM_IPG>, + <&clk IMX93_CLK_PDM_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "clkext3"; + dmas = <&edma1 29 0 5>; + dma-names = "rx"; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX93_CLK_ADC1_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; }; aips2: bus@42000000 { @@ -265,6 +529,148 @@ #size-cells = <1>; ranges; + edma2: dma-controller@42000000{ + compatible = "fsl,imx93-edma"; + reg = <0x42000000 0x10000>, + <0x42010000 0x8000>, <0x42018000 0x8000>, + <0x42020000 0x8000>, <0x42028000 0x8000>, + <0x42030000 0x8000>, <0x42038000 0x8000>, + <0x42040000 0x8000>, <0x42048000 0x8000>, + <0x42050000 0x8000>, <0x42058000 0x8000>, + <0x42060000 0x8000>, <0x42068000 0x8000>, + <0x42070000 0x8000>, <0x42078000 0x8000>, + <0x42080000 0x8000>, <0x42088000 0x8000>, + <0x42090000 0x8000>, <0x42098000 0x8000>, + <0x420a0000 0x8000>, <0x420a8000 0x8000>, + <0x420b0000 0x8000>, <0x420b8000 0x8000>, + <0x420c0000 0x8000>, <0x420c8000 0x8000>, + <0x420d0000 0x8000>, <0x420d8000 0x8000>, + <0x420e0000 0x8000>, <0x420e8000 0x8000>, + <0x420f0000 0x8000>, <0x420f8000 0x8000>, + <0x42100000 0x8000>, <0x42108000 0x8000>, + <0x42110000 0x8000>, <0x42118000 0x8000>, + <0x42120000 0x8000>, <0x42128000 0x8000>, + <0x42130000 0x8000>, <0x42138000 0x8000>, + <0x42140000 0x8000>, <0x42148000 0x8000>, + <0x42150000 0x8000>, <0x42158000 0x8000>, + <0x42160000 0x8000>, <0x42168000 0x8000>, + <0x42170000 0x8000>, <0x42178000 0x8000>, + <0x42180000 0x8000>, <0x42188000 0x8000>, + <0x42190000 0x8000>, <0x42198000 0x8000>, + <0x421a0000 0x8000>, <0x421a8000 0x8000>, + <0x421b0000 0x8000>, <0x421b8000 0x8000>, + <0x421c0000 0x8000>, <0x421c8000 0x8000>, + <0x421d0000 0x8000>, <0x421d8000 0x8000>, + <0x421e0000 0x8000>, <0x421e8000 0x8000>, + <0x421f0000 0x8000>, <0x421f8000 0x8000>, + <0x42200000 0x8000>, <0x42208000 0x8000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <64>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx", + "edma2-chan2-tx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx", + "edma2-chan6-tx", "edma2-chan7-tx", + "edma2-chan8-tx", "edma2-chan9-tx", + "edma2-chan10-tx", "edma2-chan11-tx", + "edma2-chan12-tx", "edma2-chan13-tx", + "edma2-chan14-tx", "edma2-chan15-tx", + "edma2-chan16-tx", "edma2-chan17-tx", + "edma2-chan18-tx", "edma2-chan19-tx", + "edma2-chan20-tx", "edma2-chan21-tx", + "edma2-chan22-tx", "edma2-chan23-tx", + "edma2-chan24-tx", "edma2-chan25-tx", + "edma2-chan26-tx", "edma2-chan27-tx", + "edma2-chan28-tx", "edma2-chan29-tx", + "edma2-chan30-tx", "edma2-chan31-tx", + "edma2-chan32-tx", "edma2-chan33-tx", + "edma2-chan34-tx", "edma2-chan35-tx", + "edma2-chan36-tx", "edma2-chan37-tx", + "edma2-chan38-tx", "edma2-chan39-tx", + "edma2-chan40-tx", "edma2-chan41-tx", + "edma2-chan42-tx", "edma2-chan43-tx", + "edma2-chan44-tx", "edma2-chan45-tx", + "edma2-chan46-tx", "edma2-chan47-tx", + "edma2-chan48-tx", "edma2-chan49-tx", + "edma2-chan50-tx", "edma2-chan51-tx", + "edma2-chan52-tx", "edma2-chan53-tx", + "edma2-chan54-tx", "edma2-chan55-tx", + "edma2-chan56-tx", "edma2-chan57-tx", + "edma2-chan58-tx", "edma2-chan59-tx", + "edma2-chan60-tx", "edma2-chan61-tx", + "edma2-chan62-tx", "edma2-chan63-tx", + "edma2-err"; + clocks = <&clk IMX93_CLK_EDMA2_GATE>; + clock-names = "edma"; + fsl,edma-axi; + status = "okay"; + }; + wakeupmix_gpr: syscon@42420000 { compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; reg = <0x42420000 0x1000>; @@ -274,10 +680,57 @@ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; reg = <0x42440000 0x10000>; interrupts = ; + clocks = <&clk IMX93_CLK_MU2_B_GATE>; #mbox-cells = <2>; status = "disabled"; }; + wdog3: wdog@42490000 { + compatible = "fsl,imx93-wdt"; + reg = <0x42490000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG3_GATE>; + timeout-sec = <40>; + fsl,ext-reset-output; + }; + + tpm4: pwm@424f0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424f0000 0x10000>; + clocks = <&clk IMX93_CLK_TPM4_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: pwm@42500000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42500000 0x10000>; + clocks = <&clk IMX93_CLK_TPM5_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42510000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42510000 0x10000>; + clocks = <&clk IMX93_CLK_TPM6_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c2: i3c-master@42520000 { + #address-cells = <3>; + #size-cells = <0>; + compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; + reg = <0x42520000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + lpi2c3: i2c@42530000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x42530000 0x10000>; @@ -287,6 +740,8 @@ clocks = <&clk IMX93_CLK_LPI2C3_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 8 0 0>, <&edma2 9 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -299,60 +754,186 @@ clocks = <&clk IMX93_CLK_LPI2C4_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 10 0 0>, <&edma2 11 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi3: spi@42550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI3_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI4_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; lpuart3: serial@42570000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42570000 0x1000>; interrupts = ; clocks = <&clk IMX93_CLK_LPUART3_GATE>; clock-names = "ipg"; + dmas = <&edma2 17 0 0>, <&edma2 18 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; lpuart4: serial@42580000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42580000 0x1000>; interrupts = ; clocks = <&clk IMX93_CLK_LPUART4_GATE>; clock-names = "ipg"; + dmas = <&edma2 19 0 0>, <&edma2 20 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; lpuart5: serial@42590000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42590000 0x1000>; interrupts = ; clocks = <&clk IMX93_CLK_LPUART5_GATE>; clock-names = "ipg"; + dmas = <&edma2 21 0 0>, <&edma2 22 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; lpuart6: serial@425a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x425a0000 0x1000>; interrupts = ; clocks = <&clk IMX93_CLK_LPUART6_GATE>; clock-names = "ipg"; + dmas = <&edma2 23 0 0>, <&edma2 24 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + flexcan2: can@425b0000 { + compatible = "fsl,imx93-flexcan"; + reg = <0x425b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_CAN2_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&wakeupmix_gpr 0x0C 2>; + status = "disabled"; + }; + + flexspi1: spi@425e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx93-fspi", "nxp,imx8mm-fspi"; + reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, + <&clk IMX93_CLK_FLEXSPI1_GATE>; + clock-names = "fspi", "fspi_en"; + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + status = "disabled"; + }; + + sai2: sai@42650000 { + compatible = "fsl,imx93-sai"; + reg = <0x42650000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI2_GATE>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 59 0 1>, <&edma2 58 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@42660000 { + compatible = "fsl,imx93-sai"; + reg = <0x42660000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 61 0 1>, <&edma2 60 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mqs2: mqs2 { + compatible = "fsl,imx93-mqs"; + gpr = <&wakeupmix_gpr>; + status = "disabled"; + }; + + xcvr: xcvr@42680000 { + compatible = "fsl,imx93-xcvr"; + reg = <0x42680000 0x800>, + <0x42680800 0x400>, + <0x42680c00 0x080>, + <0x42680e00 0x080>; + reg-names = "ram", "regs", "rxfifo", + "txfifo"; + interrupts = /* XCVR IRQ 0 */ + , + /* XCVR IRQ 1 */ + ; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_SPDIF_GATE>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUD_XCVR_GATE>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; lpuart7: serial@42690000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42690000 0x1000>; interrupts = ; clocks = <&clk IMX93_CLK_LPUART7_GATE>; clock-names = "ipg"; + dmas = <&edma2 87 0 0>, <&edma2 88 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; lpuart8: serial@426a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x426a0000 0x1000>; interrupts = ; clocks = <&clk IMX93_CLK_LPUART8_GATE>; clock-names = "ipg"; + dmas = <&edma2 89 0 0>, <&edma2 90 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -365,6 +946,8 @@ clocks = <&clk IMX93_CLK_LPI2C5_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 71 0 0>, <&edma2 72 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -377,6 +960,8 @@ clocks = <&clk IMX93_CLK_LPI2C6_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 73 0 0>, <&edma2 74 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -389,6 +974,8 @@ clocks = <&clk IMX93_CLK_LPI2C7_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 75 0 0>, <&edma2 76 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -401,9 +988,89 @@ clocks = <&clk IMX93_CLK_LPI2C8_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 77 0 0>, <&edma2 78 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi5: spi@426f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI5_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI6_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI7_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI8_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; + flexio1: flexio@425c0000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nxp,imx-flexio"; + reg = <0x425c0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_FLEXIO1_GATE>, + <&clk IMX93_CLK_FLEXIO1_GATE>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX93_CLK_FLEXIO1_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_FLEXIO1>; + assigned-clock-rates = <24000000>; + status = "disabled"; + + flexio_i2c: i2c-master { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx-flexio-i2c-master"; + clock-frequency = <100000>; + status = "disabled"; + }; + }; }; aips3: bus@42800000 { @@ -421,8 +1088,11 @@ <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC1_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <8>; - fsl,tuning-start-tap = <20>; + fsl,tuning-start-tap = <1>; fsl,tuning-step= <2>; status = "disabled"; }; @@ -435,12 +1105,66 @@ <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC2_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <4>; - fsl,tuning-start-tap = <20>; + fsl,tuning-start-tap = <1>; fsl,tuning-step= <2>; status = "disabled"; }; + fec: ethernet@42890000 { + compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec"; + reg = <0x42890000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX93_CLK_ENET1_GATE>, + <&clk IMX93_CLK_ENET1_GATE>, + <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <250000000>, <50000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; + status = "disabled"; + }; + + eqos: ethernet@428a0000 { + compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x428a0000 0x10000>; + interrupts = , + ; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>, + <&clk IMX93_CLK_ENET_QOS_GATE>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; + intf_mode = <&wakeupmix_gpr 0x28>; + clk_csr = <0>; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; + status = "disabled"; + }; + usdhc3: mmc@428b0000 { compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; reg = <0x428b0000 0x10000>; @@ -449,11 +1173,91 @@ <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC3_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC3>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <4>; - fsl,tuning-start-tap = <20>; + fsl,tuning-start-tap = <1>; fsl,tuning-step= <2>; status = "disabled"; }; + + epxp: epxp@4ae20000 { + compatible = "fsl,imx93-pxp-dma", "fsl,imx8ulp-pxp-dma"; + reg = <0x4ae20000 0x10000>; + interrupts = , + ; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>; + clock-names = "pxp_ipg", "pxp_axi"; + pxp-gpr = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_PXP>; + status = "disabled"; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + isi_0: isi@4ae40000{ + compatible = "fsl,imx93-isi", "fsl,imx8-isi"; + reg = <0x4ae40000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MEDIA_AXI>; + clock-names = "per", "axi"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333333>; + interface = <2 0 2>; + no-reset-control; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_ISI>; + gasket = <&media_blk_ctrl>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi: csi@4ae00000 { + compatible = "fsl,dwc-mipi-csi2-host"; + reg = <0x4ae00000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_MIPI_PHY_CFG>; + clock-names = "clk_core", "clk_pixel", "phy_cfg"; + assigned-clocks = <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_MIPI_PHY_CFG>; + assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_24M>; + assigned-clock-rates = <140000000>, <24000000>; + gasket = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_CSI>; + status = "disabled"; + }; + + parallel_csi: pcsi@4ac10070 { + compatible = "fsl,imx93-parallel-csi"; + reg = <0x4ac10070 0x10>; + clocks = <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_MEDIA_APB>; + clock-names = "pixel", "ipg"; + assigned-clocks = <&clk IMX93_CLK_CAM_PIX>; + assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <140000000>; + pi_gpr = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_CSI>; + status = "disabled"; + }; + }; }; gpio2: gpio@43810080 { @@ -513,6 +1317,31 @@ gpio-ranges = <&iomuxc 0 92 16>; }; + ocotp: efuse@47510000 { + compatible = "fsl,imx93-ocotp", "syscon", "simple-mfd"; + reg = <0x47510000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + imx93_uid: soc-uid@c0 { + reg = <0xc0 0x10>; + }; + + eth_mac1: mac-address@4ec { + reg = <0x4ec 0x6>; + }; + + eth_mac2: mac-address@4f2 { + reg = <0x4f2 0x6>; + }; + + imx93_soc: imx93-soc { + compatible = "fsl,imx93-soc"; + nvmem-cells = <&imx93_uid>; + nvmem-cell-names = "soc_unique_id"; + }; + }; + s4muap: mailbox@47520000 { compatible = "fsl,imx93-mu-s4"; reg = <0x47520000 0x10000>; @@ -523,8 +1352,8 @@ }; media_blk_ctrl: system-controller@4ac10000 { - compatible = "fsl,imx93-media-blk-ctrl", "syscon"; - reg = <0x4ac10000 0x10000>; + compatible = "fsl,imx93-media-blk-ctrl", "syscon", "simple-mfd"; + reg = <0x4ac10000 0x70>; power-domains = <&mediamix>; clocks = <&clk IMX93_CLK_MEDIA_APB>, <&clk IMX93_CLK_MEDIA_AXI>, @@ -539,7 +1368,266 @@ clock-names = "apb", "axi", "nic", "disp", "cam", "pxp", "lcdif", "isi", "csi", "dsi"; #power-domain-cells = <1>; + + dphy: dphy { + compatible = "fsl,imx93-mipi-dphy"; + clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>, + <&clk IMX93_CLK_24M>; + clock-names = "phy_cfg", "phy_ref"; + assigned-clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>; + assigned-clock-parents = <&clk IMX93_CLK_24M>; + assigned-clock-rates = <24000000>; + #phy-cells = <0>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + status = "disabled"; + }; + + parallel_disp_fmt: dpi { + compatible = "fsl,imx93-parallel-display-format"; + power-domains = <&mediamix>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_to_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dpi>; + }; + }; + }; + }; + }; + + ldb: ldb@4ac10020 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-ldb"; + clocks = <&clk IMX93_CLK_LVDS_GATE>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>; + gpr = <&media_blk_ctrl>; + power-domains = <&mediamix>; status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch0: endpoint { + remote-endpoint = <&lcdif_to_ldb>; + }; + }; + }; + }; + + ldb_phy: phy@4ac10024 { + compatible = "fsl,imx93-lvds-phy"; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&media_blk_ctrl>; + clocks = <&clk IMX93_CLK_MEDIA_APB>; + clock-names = "apb"; + power-domains = <&mediamix>; + status = "disabled"; + + ldb_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + ele_mu: ele-mu { + compatible = "fsl,imx93-ele"; + mboxes = <&s4muap 0 0 &s4muap 1 0>; + mbox-names = "tx", "rx"; + fsl,ele_mu_did = <3>; + fsl,ele_mu_id = <2>; + fsl,ele_mu_max_users = <4>; + status = "okay"; + }; + + dsi: dsi@4ae10000 { + compatible = "fsl,imx93-mipi-dsi"; + reg = <0x4ae10000 0x4000>; + interrupts = ; + clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>; + clock-names = "byte", "pclk", "pixel"; + assigned-clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <20000000>, <133333333>; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_to_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsi>; + }; + }; + }; }; + + lcdif: lcd-controller@4ae30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-lcdif"; + reg = <0x4ae30000 0x10000>; + interrupts = ; + fsl,gpr = <&media_blk_ctrl>; + clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_LCDIF_GATE>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_24M>, + <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>; + status = "disabled"; + + lcdif_disp: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + lcdif_to_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_to_lcdif>; + }; + + lcdif_to_ldb: endpoint@1 { + reg = <1>; + remote-endpoint = <&ldb_ch0>; + }; + + lcdif_to_dpi: endpoint@2 { + reg = <2>; + remote-endpoint = <&dpi_to_lcdif>; + }; + }; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg1: usb@4c100000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c100000 0x200>; + interrupts = ; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root_clk", "usb_wakeup_clk"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c100200 0x200>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg2: usb@4c200000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c200000 0x200>; + interrupts = ; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root_clk", "usb_wakeup_clk"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c200200 0x200>; + }; + + ddrmix_blk_ctrl: blk-ctrl@4e010000 { + compatible = "nxp,blk-ctrl-ddrmix", "syscon", "simple-mfd"; + reg = <0x4e010000 0x1000>; + }; + + ddr: memory-controller@4e300000 { + compatible = "nxp,imx9-memory-controller", "simple-mfd"; + reg = <0x4e300000 0x2000>; + interrupts = ; + little-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ddr-pmu@4e300dc0 { + compatible = "fsl,imx93-ddr-pmu"; + reg = <0x4e300dc0 0x200>; + interrupts = ; + }; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp>; + }; + + lpm: imx93-lpm { + compatible = "nxp,imx93-lpm"; + regmap = <&ddrmix_blk_ctrl>; + clocks = <&clk IMX93_CLK_M33>, <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_NIC_AXI>, <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_A55_PERIPH>, <&clk IMX93_CLK_A55_CORE>, <&clk IMX93_CLK_ML>, + <&clk IMX93_CLK_SYS_PLL_PFD0>, <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD2>, <&clk IMX93_CLK_SYS_PLL_PFD2_DIV2>; + clock-names = "m33_root", "wakeup_axi", "nic_axi", "media_axi", "a55_periph", + "a55_core", "ml_axi", "sys_pll_pfd0", "sys_pll_pfd0_div2", + "sys_pll_pfd1", "sys_pll_pfd1_div2", "sys_pll_pfd2", + "sys_pll_pfd2_div2"; + status = "disabled"; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + */ + +/dts-v1/; + +#include +#include "imx93-phycore-som.dtsi" + +/ { + model = "PHYTEC phyBOARD-Nash-i.MX93"; + compatible = "phytec,imx93-phyboard-nash", + "phytec,imx93-phycore-som", "fsl,imx93"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &bbnsm_rtc; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_can1_stb: regulator-can1-stb { + compatible = "regulator-fixed"; + gpio = <&gpio4 16 GPIO_ACTIVE_LOW>; + enable-active-low; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1_stb>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "CAN1_STB"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_SD"; + }; + + reg_vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC1V8"; + }; + + reg_vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC3V3"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "VREF_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +/* ADC */ +&adc1 { + /* 1.8V */ + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +/* Power-key */ +&bbnsm_pwrkey { + linux,keycode = ; + wakeup-source; +}; + +/* Ethernet */ +&eqos { + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,clk-output-sel = ; + }; +}; + +/* CAN */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stb>; + status = "okay"; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + /* RTC */ + i2c_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + trickle-resistor-ohms = <3000>; + wakeup-source; + }; + + /* EEPROM */ + eeprom@54 { + compatible = "atmel,24c32"; + reg = <0x54>; + pagesize = <32>; + vcc-supply = <®_vcc_1v8>; + }; + + /* EEPROM ID page */ + eepromid@5c { + compatible = "atmel,24c32"; + reg = <0x5c>; + pagesize = <32>; + size = <32>; + vcc-supply = <®_vcc_1v8>; + }; +}; + +&lpspi6 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* TPM */ + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* RS-232/RS-485 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +/* USB */ +&usbphynop1 { + vcc-supply = <&buck4>; +}; + +&usbphynop2 { + vcc-supply = <&buck4>; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +/* SD-Card */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x50e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x50e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1002 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + MX93_PAD_PDM_CLK__CAN1_TX 0x13e9 + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpspi6: lpspi6grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x3fe + MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe + MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe + MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe + >; + }; + + pinctrl_reg_can1_stb: regcan1stbgrp { + fsl,pins = < + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x30e + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__LPUART7_TX 0x30e + MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e + MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e + MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_default: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-av-010.dtso linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-av-010.dtso --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-av-010.dtso 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-av-010.dtso 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + */ + +#include +#include +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +/ { + compatible = "phytec,imx93-phyboard-nash"; +}; + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + brightness-levels= <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + power-supply = <®_vcc_3v3>; + pwms = <&tpm5 2 50000 0>; + }; + + panel { + compatible = "edt,etml1010g3dra"; + backlight = <&backlight>; + enable-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + power-supply = <®_vcc_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; + + reg_sound_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC-1V8-AUDIO"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + reg_sound_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC-3V3-AUDIO"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + sound-peb-av-10 { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd-peb-av-10"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Line", "Line In", + "Speaker", "Speaker", + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Speaker", "SPOP", + "Speaker", "SPOM", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&osc_mclk>; + }; + }; + + osc_mclk: oscillator-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; +}; + +&lcdif { + assigned-clock-rates = <498000000>, <71142857>, <400000000>, <133333333>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&ldb_phy { + status = "okay"; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + + codec: codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + AVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + IOVDD-supply = <®_sound_3v3>; + ai3x-gpio-func = <0xd 0x0>; + ai3x-micbias-vg = <2>; + }; + + eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_vcc_3v3>; + }; + + eepromid@5f { + compatible = "atmel,24c32"; + reg = <0x5f>; + pagesize = <32>; + size = <32>; + vcc-supply = <®_vcc_3v3>; + }; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&tpm5 { + status = "okay"; +}; + +&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX93_PAD_GPIO_IO18__TPM5_CH2 0x31e + MX93_PAD_GPIO_IO07__GPIO2_IO07 0x31e + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + MX93_PAD_GPIO_IO14__GPIO2_IO14 0x39e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x1202 + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x1202 + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x1402 + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x1402 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov , Christoph Stoidner + * + * Product homepage: + * phyBOARD-Segin carrier board is reused for the i.MX93 design. + * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ + */ + +/dts-v1/; + +#include +#include "imx93-phycore-som.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin-i.MX93"; + compatible = "phytec,imx93-phyboard-segin", + "phytec,imx93-phycore-som", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + /* M-R-SN65HVD234.A0 */ + reg_can1_en: regulator-can1 { + compatible = "regulator-fixed"; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "CAN1_EN"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_SD"; + }; + + reg_vcc_1v8_audio: regulator-vcc1v8-audio { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC1V8_AUDIO"; + }; + + reg_vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC3V3"; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&tlv320>; + clocks = <&clk IMX93_CLK_SAI1>; + }; + }; +}; + +/* Audio */ +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <19200000>; + fsl,sai-mclk-direction-output; + #sound-dai-cells = <0>; + status = "okay"; +}; + +/* Power-key */ +&bbnsm_pwrkey { + linux,keycode = ; + wakeup-source; +}; + +/* Ethernet */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>; + status = "okay"; +}; + +/* ENET2 MDIO */ +&mdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + compatible = "ethernet-phy-id0022.1561"; + + /* + * HACK: + * IMX93_CLK_ENET is the ref clock and should be running at 50Mhz. + * Using it here to tell the PHY we are running at 50MHz is not working. + * Let us simply use another clock here. + */ + /* clocks = <&clk IMX93_CLK_ENET>; */ + clocks = <&clk IMX93_CLK_ENET_REF_PHY>; + clock-names = "rmii-ref"; + }; +}; + +/* CAN */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_en>; + status = "okay"; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tlv320: audio-codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + AVDD-supply = <®_vcc_3v3>; + IOVDD-supply = <®_vcc_3v3>; + DRVDD-supply = <®_vcc_3v3>; + DVDD-supply = <®_vcc_1v8_audio>; + #sound-dai-cells = <0>; + }; + + i2c_rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbphynop1 { + vcc-supply = <&buck4>; +}; + +&usbphynop2 { + vcc-supply = <&buck4>; +}; + +/* eMMC */ +&usdhc1 { + no-1-8-v; +}; + +/* SD-Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + disable-wp; + no-sdio; + no-mmc; + status = "okay"; +}; + +&iomuxc { + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_UART2_RXD__SAI1_MCLK 0x1202 + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x1202 + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x1202 + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x1402 + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x1402 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000050e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x50e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e + MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x57e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x30e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_default: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + MX93_PAD_PDM_CLK__CAN1_TX 0x13e9 + >; + }; + + pinctrl_flexcan1_en: flexcan1engrp { + fsl,pins = < + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Andrej Picej + */ + +#include +#include +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +/ { + compatible = "phytec,imx93-phyboard-segin"; +}; + +&{/} { + panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&backlight_peb>; + power-supply = <®_vcc_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + backlight_peb: backlight { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + default-on; + }; + + reg_backlight_en: regulator-backlight-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_en>; + regulator-name = "Backlight"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&lcdif { + status = "okay"; + assigned-clock-rates = <150000000>, <30000000>, <400000000>, <133333333>; +}; + +¶llel_disp_fmt { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + fsl,interface-pix-fmt = "rgb666"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + + polytouch: edt-ft5x06@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + interrupt-parent = <&gpio4>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + vcc-supply = <®_vcc_3v3>; + iovcc-supply = <®_vcc_3v3>; + wakeup-source; + status = "okay"; + }; +}; + +&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x1133e + >; + }; + + pinctrl_backlight_en: backlightengrp { + fsl,pins = < + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1133e + >; + }; + + pinctrl_edt_ft5x06: edtft5x06grp { + fsl,pins = < + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x1133e + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x50e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x50e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x50e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x50e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x50e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x50e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x50e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x50e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x50e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x51e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x50e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x50e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x50e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x50e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x50e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x50e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x506 + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x506 + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x506 + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x506 + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x506 + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x506 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-eval-01.dtso linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-eval-01.dtso --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-eval-01.dtso 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-eval-01.dtso 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Andrej Picej + */ + +#include +#include +#include +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +/ { + compatible = "phytec,imx93-phyboard-segin"; +}; + +&{/} { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + sleep { + label = "Sleep Button"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + + user-led2 { + color = ; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_user_leds: userledsgrp { + fsl,pins = < + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phycore-no-emmc.dtso linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phycore-no-emmc.dtso --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phycore-no-emmc.dtso 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phycore-no-emmc.dtso 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "phytec,imx93-phycore-som"; +}; + +&usdhc1 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phycore-no-eth.dtso linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phycore-no-eth.dtso --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phycore-no-eth.dtso 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phycore-no-eth.dtso 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "phytec,imx93-phycore-som"; +}; + +ðphy1 { + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phycore-rpmsg.dtso linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phycore-rpmsg.dtso --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phycore-rpmsg.dtso 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phycore-rpmsg.dtso 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "phytec,imx93-phycore-som"; +}; + +&{/} { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021f000 { + reg = <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + }; + + cm33: imx93-cm33 { + compatible = "fsl,imx93-cm33"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1 + &mu1 1 1 + &mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + fsl,startup-delay-ms = <500>; + }; +}; + +&mu1 { + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi 2024-06-19 12:33:58.312192771 +0200 @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov , Christoph Stoidner + * + * Product homepage: + * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ + */ + +#include +#include "imx93.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX93"; + compatible = "phytec,imx93-phycore-som", "fsl,imx93"; + + reserved_memory: reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + + ele_reserved: ele-reserved@a4120000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ele_mu { + memory-region = <&ele_reserved>; +}; + +/* PXP */ +&epxp { + status = "okay"; +}; + +/* Ethernet */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>, <50000000>; + status = "okay"; + + mdio: mdio { + clock-frequency = <5000000>; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-id2000.a111", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +/* I2C3 */ +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "VDD_SOC"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "VDDQ_0V6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3_BUCK"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "VDD_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "PMIC_SNVS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <&buck4>; + }; + + eepromid@58 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x58>; + size = <32>; + vcc-supply = <&buck4>; + }; +}; + +&lpm { + soc-supply = <&buck1>; + ld-mode-enabled; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e + MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001386 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/Makefile linux-imx-phytec/arch/arm64/boot/dts/freescale/Makefile --- linux-6.1.55/arch/arm64/boot/dts/freescale/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/Makefile 2024-06-19 12:33:58.268192018 +0200 @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb @@ -13,11 +14,23 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb-dpdk.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-sdk.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-usdpaa.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-shared-mac9-only.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa-shared-mac10.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa-shared.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb @@ -50,81 +63,364 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-ab2.dtb imx8mm-ab2-m4.dtb imx8mm-ddr4-ab2.dtb imx8mm-ddr4-ab2-m4.dtb \ + imx8mm-ddr4-ab2-revb.dtb imx8mm-ddr4-ab2-m4-revb.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191.dtb \ + imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb imx8mm-evk-revb-qca-wifi.dtb \ + imx8mm-evk-ecspi-slave.dtb \ + imx8mm-evk-pcie-ep.dtb \ + imx8mm-evk-usd-wifi.dtb \ + imx8mm-evk-qca-wifi.dtb \ + imx8mm-evk-dpdk.dtb \ + imx8mm-evk-rm67199.dtb imx8mm-evk-rm67191-cmd-ram.dtb imx8mm-evk-rm67199-cmd-ram.dtb \ + imx8mm-evk-lk.dtb imx8mm-evk-rpmsg-wm8524-lpv.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-rpmsg-wm8524.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk-audio-tdm.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-8mic-revE.dtb imx8mm-evk-8mic-swpdm.dtb \ + imx8mm-evk-iqaudio-dacplus.dtb imx8mm-evk-iqaudio-dacpro.dtb imx8mm-evk-hifiberry-dacplus.dtb \ + imx8mm-evk-hifiberry-dac2.dtb imx8mm-evk-hifiberry-dacplusadc.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb imx8mm-ddr4-evk-rm67191.dtb imx8mm-ddr4-evk-revb.dtb \ + imx8mm-ddr4-evk-revb-rm67191.dtb \ + imx8mm-ddr4-evk-revb-rm67191-cmd-ram.dtb \ + imx8mm-ddr4-evk-root.dtb \ + imx8mm-ddr4-evk-inmate.dtb \ + imx8mm-ddr4-evk-pcie-ep.dtb \ + imx8mm-ddr4-evk-revb-rm67199.dtb \ + imx8mm-ddr4-evk-revb-rm67199-cmd-ram.dtb \ + imx8mm-ddr4-evk-rm67199.dtb \ + imx8mm-ddr4-evk-rm67191-cmd-ram.dtb \ + imx8mm-ddr4-evk-rm67199-cmd-ram.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-osm-s.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-evk-rm67199.dtb \ + imx8mn-evk-rm67191-cmd-ram.dtb imx8mn-evk-rm67199-cmd-ram.dtb \ + imx8mn-evk-rpmsg.dtb imx8mn-evk-8mic-revE.dtb \ + imx8mn-evk-8mic-swpdm.dtb imx8mn-evk-usd-wifi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb imx8mn-ddr4-evk-rm67191.dtb imx8mn-ddr4-evk-rm67199.dtb \ + imx8mn-ddr4-evk-rm67191-cmd-ram.dtb imx8mn-ddr4-evk-rm67199-cmd-ram.dtb \ + imx8mn-ddr4-evk-usd-wifi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk-rpmsg.dtb imx8mn-ddr3l-evk-rpmsg.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk-root.dtb imx8mn-ddr4-evk-inmate.dtb imx8mn-evk-root.dtb imx8mn-evk-inmate.dtb \ + imx8mn-evk-lk.dtb imx8mn-ddr4-evk-lk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk-ak5558.dtb imx8mn-ddr4-evk-ak5558.dtb imx8mn-evk-ak5558.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ab2.dtb imx8mn-ddr3l-ab2.dtb imx8mn-ddr4-ab2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk-iqaudio-dacplus.dtb imx8mn-evk-iqaudio-dacpro.dtb imx8mn-evk-hifiberry-dacplus.dtb \ + imx8mn-evk-hifiberry-dac2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-rm67191.dtb imx8mp-evk-it6263-lvds-dual-channel.dtb \ + imx8mp-evk-pcie-ep.dtb imx8mp-evk-rpmsg.dtb imx8mp-evk-ecspi-slave.dtb \ + imx8mp-evk-jdi-wuxga-lvds-panel.dtb imx8mp-evk-flexcan2.dtb \ + imx8mp-evk-root.dtb imx8mp-evk-inmate.dtb imx8mp-evk-ov2775.dtb \ + imx8mp-evk-ov2775-ov5640.dtb imx8mp-evk-basler-ov5640.dtb imx8mp-evk-basler.dtb \ + imx8mp-evk-basler-ov2775.dtb imx8mp-evk-dual-basler.dtb \ + imx8mp-evk-dual-ov2775.dtb imx8mp-evk-spdif-lb.dtb imx8mp-evk-dsp.dtb \ + imx8mp-evk-sof-wm8960.dtb imx8mp-evk-sof-pdm.dtb \ + imx8mp-evk-os08a20-ov5640.dtb imx8mp-evk-os08a20.dtb \ + imx8mp-evk-dual-os08a20.dtb \ + imx8mp-evk-iqaudio-dacplus.dtb imx8mp-evk-iqaudio-dacpro.dtb imx8mp-evk-hifiberry-dacplus.dtb \ + imx8mp-evk-hifiberry-dac2.dtb imx8mp-evk-hifiberry-dacplusadc.dtb \ + imx8mp-evk-usdhc1-m2.dtb imx8mp-evk-rm67199.dtb \ + imx8mp-evk-dpdk.dtb imx8mp-evk-8mic-swpdm.dtb imx8mp-evk-rpmsg-lpv.dtb imx8mp-evk-revA3-8mic-revE.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-ab2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-ndm.dtb + +imx8mp-evk-revb4-dtbs := imx8mp-evk.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-rm67191-dtbs := imx8mp-evk-rm67191.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-it6263-lvds-dual-channel-dtbs := imx8mp-evk-it6263-lvds-dual-channel.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-pcie-ep-dtbs := imx8mp-evk-pcie-ep.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-ecspi-slave-dtbs := imx8mp-evk-ecspi-slave.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-jdi-wuxga-lvds-panel-dtbs := imx8mp-evk-jdi-wuxga-lvds-panel.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-flexcan2-dtbs := imx8mp-evk-flexcan2.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-root-dtbs := imx8mp-evk-root.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-ov2775-dtbs := imx8mp-evk-ov2775.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-ov2775-ov5640-dtbs := imx8mp-evk-ov2775-ov5640.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-basler-ov5640-dtbs := imx8mp-evk-basler-ov5640.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-basler-dtbs := imx8mp-evk-basler.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-basler-ov2775-dtbs := imx8mp-evk-basler-ov2775.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-dual-basler-dtbs := imx8mp-evk-dual-basler.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-dual-ov2775-dtbs := imx8mp-evk-dual-ov2775.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-spdif-lb-dtbs := imx8mp-evk-spdif-lb.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-os08a20-ov5640-dtbs := imx8mp-evk-os08a20-ov5640.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-os08a20-dtbs := imx8mp-evk-os08a20.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-dual-os08a20-dtbs := imx8mp-evk-dual-os08a20.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-iqaudio-dacplus-dtbs := imx8mp-evk-iqaudio-dacplus.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-iqaudio-dacpro-dtbs := imx8mp-evk-iqaudio-dacpro.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-hifiberry-dacplus-dtbs := imx8mp-evk-hifiberry-dacplus.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-hifiberry-dac2-dtbs := imx8mp-evk-hifiberry-dac2.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-hifiberry-dacplusadc-dtbs := imx8mp-evk-hifiberry-dacplusadc.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-usdhc1-m2-dtbs := imx8mp-evk-usdhc1-m2.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-rm67199-dtbs := imx8mp-evk-rm67199.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-dpdk-dtbs := imx8mp-evk-dpdk.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-8mic-swpdm-dtbs := imx8mp-evk-8mic-swpdm.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-8mic-revE-dtbs := imx8mp-evk-revA3-8mic-revE.dtb imx8mp-evk-revb4.dtbo +imx8mp-ddr4-evk-revb4-dtbs := imx8mp-ddr4-evk.dtb imx8mp-evk-revb4.dtbo +imx8mp-evk-revb4-ndm-dtbs := imx8mp-evk-ndm.dtb imx8mp-evk-revb4.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-rm67191.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-it6263-lvds-dual-channel.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-pcie-ep.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-ecspi-slave.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-jdi-wuxga-lvds-panel.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-flexcan2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-root.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-ov2775.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-ov2775-ov5640.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-basler-ov5640.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-basler.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-basler-ov2775.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-dual-basler.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-dual-ov2775.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-spdif-lb.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-os08a20-ov5640.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-os08a20.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-dual-os08a20.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-iqaudio-dacplus.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-iqaudio-dacpro.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-hifiberry-dacplus.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-hifiberry-dac2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-hifiberry-dacplusadc.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-usdhc1-m2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-rm67199.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-dpdk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-8mic-swpdm.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-8mic-revE.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-ddr4-evk-revb4.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-ndm.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-sof-wm8962.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-rpmsg.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-revb4-rpmsg-lpv.dtb + +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb imx8mq-evk-usd-wifi.dtb \ + imx8mq-evk-usdhc2-m2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-ak4497.dtb imx8mq-evk-audio-tdm.dtb imx8mq-evk-pdm.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-root.dtb imx8mq-evk-inmate.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-lcdif-rm67191.dtb imx8mq-evk-lcdif-adv7535.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-lcdif-rm67199.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dcss-rm67191.dtb imx8mq-evk-dcss-adv7535.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dcss-rm67199.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dual-display.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r4.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-tqma8mq-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-mnt-reform2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-dp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-ddr3l-val.dtb imx8mq-ddr4-val.dtb imx8mq-ddr4-val-gpmi-nand.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-pcie-ep.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mq-wevk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb imx8ulp-evk-lpspi-slave.dtb \ + imx8ulp-evk-i3c.dtb imx8ulp-evk-rk055hdmipi4m.dtb imx8ulp-evk-rk055hdmipi4mv2.dtb \ + imx8ulp-evk-epdc.dtb imx8ulp-evk-sof-btsco.dtb \ + imx8ulp-evk-flexio-i2c.dtb imx8ulp-evk-nd.dtb imx8ulp-9x9-evk.dtb \ + imx8ulp-9x9-evk-rk055hdmipi4m.dtb imx8ulp-9x9-evk-rk055hdmipi4mv2.dtb \ + imx8ulp-9x9-evk-lpspi.dtb imx8ulp-9x9-evk-lpspi-slave.dtb \ + imx8ulp-9x9-evk-i3c.dtb imx8ulp-9x9-evk-sof-btsco.dtb \ + imx8ulp-evk-lpa.dtb imx8ulp-9x9-evk-lpa.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \ + imx8qm-mek-enet2-tja1100.dtb imx8qm-mek-rpmsg.dtb \ + imx8qm-mek-hdmi.dtb \ + imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \ + imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ + imx8qm-mek-pcie-ep.dtb \ + imx8qm-mek-usdhc3-m2.dtb imx8qm-mek-usd-wifi.dtb \ + imx8qm-mek-hdmi-rx.dtb \ + imx8qm-mek-hdmi-rx-ov5640.dtb \ + imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \ + imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \ + imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \ + imx8qm-lpddr4-val-ca72.dtb imx8qm-ddr4-val.dtb \ + imx8qm-lpddr4-val-lpspi.dtb imx8qm-lpddr4-val-lpspi-slave.dtb \ + imx8qm-mek-dsi-rm67191.dtb imx8qm-mek-dsi-rm67199.dtb \ + imx8qm-lpddr4-val-dp.dtb\ + imx8qp-lpddr4-val.dtb imx8dm-lpddr4-val.dtb imx8qm-pcieax2pciebx1.dtb \ + imx8qm-mek-cockpit-a53.dtb imx8qm-mek-cockpit-a72.dtb \ + imx8qm-mek-esai.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-dom0.dtb imx8qm-mek-domu.dtb \ + imx8qm-mek-root.dtb imx8qm-mek-inmate.dtb + +imx8qm-mek-revd-dtbs := imx8qm-mek.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-rpmsg-dtbs := imx8qm-mek-rpmsg.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-ov5640-dtbs := imx8qm-mek-ov5640.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-enet2-tja1100-dtbs := imx8qm-mek-enet2-tja1100.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-hdmi-dtbs := imx8qm-mek-hdmi.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-jdi-wuxga-lvds1-panel-dtbs := imx8qm-mek-jdi-wuxga-lvds1-panel.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-jdi-wuxga-lvds1-panel-rpmsg-dtbs := imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-pcie-ep-dtbs := imx8qm-mek-pcie-ep.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-usdhc3-m2-dtbs := imx8qm-mek-usdhc3-m2.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-usd-wifi-dtbs := imx8qm-mek-usd-wifi.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-hdmi-rx-dtbs := imx8qm-mek-hdmi-rx.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-hdmi-rx-ov5640-dtbs := imx8qm-mek-hdmi-rx-ov5640.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-ca53-dtbs := imx8qm-mek-ca53.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-ca72-dtbs := imx8qm-mek-ca72.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-dsi-rm67191-dtbs := imx8qm-mek-dsi-rm67191.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-dsi-rm67199-dtbs := imx8qm-mek-dsi-rm67199.dtb imx8qm-mek-revd.dtbo +imx8qm-pcieax2pciebx1-revd-dtbs := imx8qm-pcieax2pciebx1.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-esai-dtbs := imx8qm-mek-esai.dtb imx8qm-mek-revd.dtbo +imx8qm-mek-revd-root-dtbs := imx8qm-mek-root.dtb imx8qm-mek-revd.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-rpmsg.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-ov5640.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-enet2-tja1100.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-hdmi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-jdi-wuxga-lvds1-panel.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-jdi-wuxga-lvds1-panel-rpmsg.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-pcie-ep.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-usdhc3-m2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-usd-wifi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-hdmi-rx.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-hdmi-rx-ov5640.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-ca53.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-ca72.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-dsi-rm67191.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-dsi-rm67199.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-pcieax2pciebx1-revd.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-esai.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-revd-root.dtb + +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb \ + imx8dxl-evk-enet0.dtb imx8dxl-evk-enet0-tja1100.dtb \ + imx8dxl-evk-pcie-ep.dtb \ + imx8dxl-evk-lcdif.dtb \ + imx8dxl-evk-lpspi-slave.dtb \ + imx8dxl-evk-rpmsg.dtb \ + imx8dxl-ddr3l-evk.dtb \ + imx8dxl-ddr3l-evk-rpmsg.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-phantom-mek.dtb \ + imx8dxl-phantom-mek-rpmsg.dtb \ + imx8dxl-orangebox.dtb \ + imx8dxl-orangebox-sd.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-ov5640.dtb \ + imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-sja1105.dtb \ + imx8qxp-mek-enet2-tja1100.dtb \ + imx8qxp-mek-sof-cs42888.dtb imx8qxp-mek-sof-wm8960.dtb imx8qxp-mek-sof.dtb\ + imx8qxp-mek-rpmsg.dtb imx8qxp-mek-a0.dtb \ + imx8qxp-mek-it6263-lvds0-dual-channel.dtb \ + imx8qxp-mek-it6263-lvds1-dual-channel.dtb \ + imx8qxp-mek-it6263-lvds0-dual-channel-rpmsg.dtb \ + imx8qxp-mek-it6263-lvds1-dual-channel-rpmsg.dtb \ + imx8qxp-mek-jdi-wuxga-lvds0-panel.dtb \ + imx8qxp-mek-jdi-wuxga-lvds1-panel.dtb \ + imx8qxp-mek-jdi-wuxga-lvds0-panel-rpmsg.dtb \ + imx8qxp-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ + imx8qxp-mek-dsi-rm67191.dtb \ + imx8qxp-mek-dsi-rm67191-rpmsg.dtb \ + imx8qxp-mek-dsi-rm67199.dtb \ + imx8qxp-mek-dsi-rm67199-rpmsg.dtb \ + imx8qxp-mek-ov5640-rpmsg.dtb \ + imx8qxp-mek-dpu-lcdif.dtb \ + imx8qxp-mek-dpu-lcdif-rpmsg.dtb \ + imx8qxp-mek-pcie-ep.dtb \ + imx8dx-mek.dtb imx8dx-mek-rpmsg.dtb \ + imx8dx-mek-enet2-tja1100.dtb \ + imx8dx-mek-it6263-lvds0-dual-channel.dtb \ + imx8dx-mek-it6263-lvds1-dual-channel.dtb \ + imx8dx-mek-it6263-lvds0-dual-channel-rpmsg.dtb \ + imx8dx-mek-it6263-lvds1-dual-channel-rpmsg.dtb \ + imx8dx-mek-jdi-wuxga-lvds0-panel.dtb \ + imx8dx-mek-jdi-wuxga-lvds1-panel.dtb \ + imx8dx-mek-jdi-wuxga-lvds0-panel-rpmsg.dtb \ + imx8dx-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ + imx8dx-mek-ov5640.dtb \ + imx8dx-mek-ov5640-rpmsg.dtb \ + imx8dx-mek-dsi-rm67191.dtb \ + imx8dx-mek-dsi-rm67191-rpmsg.dtb \ + imx8qxp-mek-lcdif.dtb \ + imx8qxp-mek-lcdif-rpmsg.dtb \ + imx8qxp-lpddr4-val-a0.dtb \ + imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \ + imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \ + imx8qxp-lpddr4-val-spdif.dtb imx8qxp-lpddr4-val-gpmi-nand.dtb imx8dxp-lpddr4-val.dtb \ + imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-dom0.dtb imx8qxp-mek-root.dtb \ + imx8qxp-mek-inmate.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb \ + imx93-14x14-evk-tja1103.dtb imx93-14x14-evk-rm67199.dtb \ + imx93-14x14-evk-mqs.dtb imx93-14x14-evk-aud-hat.dtb \ + imx93-14x14-evk-lvds-it6263.dtb imx93-14x14-evk-sja1105.dtb \ + imx93-14x14-evk-flexspi-m2.dtb imx93-14x14-evk-dsi-serdes.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb \ + imx93-11x11-evk-inmate.dtb imx93-11x11-evk-root.dtb imx93-11x11-evk-flexio-i2c.dtb \ + imx93-11x11-evk-lpspi.dtb imx93-11x11-evk-lpspi-slave.dtb \ + imx93-11x11-evk-i3c.dtb imx93-11x11-evk-lpuart.dtb \ + imx93-11x11-evk-mqs.dtb imx93-11x11-evk-aud-hat.dtb \ + imx93-11x11-evk-rm67199.dtb imx93-11x11-evk-boe-wxga-lvds-panel.dtb \ + imx93-11x11-evk-flexspi-m2.dtb \ + imx93-11x11-evk-mt9m114.dtb \ + imx93-11x11-evk-ld.dtb \ + imx93-11x11-evk-rpmsg.dtb imx93-11x11-evk-rpmsg-lpv.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb \ + imx93-9x9-qsb-can1.dtb \ + imx93-9x9-qsb-flexspi-m2.dtb \ + imx93-9x9-qsb-ontat-wvga-panel.dtb \ + imx93-9x9-qsb-mt9m114.dtb \ + imx93-9x9-qsb-i3c.dtb \ + imx93-9x9-qsb-lpspi.dtb imx93-9x9-qsb-lpspi-slave.dtb \ + imx93-9x9-qsb-ld.dtb imx93-9x9-qsb-aud-hat.dtb \ + imx93-9x9-qsb-rpmsg.dtb imx93-9x9-qsb-rpmsg-lpv.dtb + +dtb-$(CONFIG_ARCH_MXC) += imx91p-9x9-qsb.dtb imx91p-9x9-qsb-aud-hat.dtb \ + imx91p-9x9-qsb-mt9m114.dtb \ + imx91p-9x9-qsb-flexspi-m2.dtb \ + imx91p-9x9-qsb-spi-nand-m2.dtb \ + imx91p-9x9-qsb-i3c.dtb \ + imx91p-9x9-qsb-lpspi.dtb \ + imx91p-9x9-qsb-lpspi-slave.dtb \ + imx91p-9x9-qsb-ld.dtb \ + imx91p-9x9-qsb-ontat-wvga-panel.dtb \ + imx91p-9x9-qsb-can1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91p-11x11-evk.dtb imx91p-11x11-evk-mt9m114.dtb \ + imx91p-11x11-evk-mqs.dtb imx91p-11x11-evk-aud-hat.dtb \ + imx91p-11x11-evk-ontat-wvga-panel.dtb \ + imx91p-11x11-evk-flexspi-m2.dtb \ + imx91p-11x11-evk-ld.dtb \ + imx91p-11x11-evk-i3c.dtb \ + imx91p-11x11-evk-lpspi.dtb \ + imx91p-11x11-evk-lpspi-slave.dtb + +dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb + +imx93-phyboard-nash-peb-av-010-dtbs += imx93-phyboard-nash.dtb \ + imx93-phyboard-nash-peb-av-010.dtbo +imx93-phyboard-segin-peb-av-02-dtbs += imx93-phyboard-segin.dtb \ + imx93-phyboard-segin-peb-av-02.dtbo +imx93-phyboard-segin-peb-eval-01-dtbs += imx93-phyboard-segin.dtb \ + imx93-phyboard-segin-peb-eval-01.dtbo +imx93-phycore-no-emmc-dtbs += imx93-phyboard-nash.dtb \ + imx93-phyboard-segin.dtb \ + imx93-phycore-no-emmc.dtbo +imx93-phycore-no-eth-dtbs += imx93-phyboard-nash.dtb \ + imx93-phyboard-segin.dtb \ + imx93-phycore-no-eth.dtbo +imx93-phycore-rpmsg-dtbs += imx93-phyboard-segin.dtb \ + imx93-phycore-rpmsg.dtbo -imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo -imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo -imx8mm-venice-gw72xx-0x-rs422-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs422.dtbo -imx8mm-venice-gw72xx-0x-rs485-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs485.dtbo -imx8mm-venice-gw73xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo -imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo -imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo -imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-peb-av-010.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-av-02.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-eval-01.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-no-emmc.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-no-eth.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtb @@ -137,4 +433,7 @@ dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb -dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb +dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb \ + s32v234-sbc.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-sof-cs42888.dtb imx8qm-mek-sof-wm8960.dtb \ + imx8qm-mek-revd-sof-wm8962.dtb imx8qm-mek-sof.dtb diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -0,0 +1,55 @@ +/* + * QorIQ BMan SDK Portals device tree nodes + * + * Copyright 2011-2016 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + */ + +&bportals { + bman-portal@0 { + cell-index = <0>; + }; + + bman-portal@10000 { + cell-index = <1>; + }; + + bman-portal@20000 { + cell-index = <2>; + }; + + bman-portal@30000 { + cell-index = <3>; + }; + + bman-portal@40000 { + cell-index = <4>; + }; + + bman-portal@50000 { + cell-index = <5>; + }; + + bman-portal@60000 { + cell-index = <6>; + }; + + bman-portal@70000 { + cell-index = <7>; + }; + + bman-portal@80000 { + cell-index = <8>; + }; + + bman-portal@90000 { + cell-index = <9>; + }; + + bman-bpids@0 { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <32 32>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -0,0 +1,72 @@ +/* + * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ] + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +fsldpaa: fsl,dpaa { + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + dma-coherent; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + dma-coherent; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + dma-coherent; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + dma-coherent; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + dma-coherent; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + dma-coherent; + }; + ethernet@8 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + dma-coherent; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -9,19 +9,20 @@ fman@1a00000 { fman0_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; fsl,fman-10g-port; + fsl,qman-channel-id = <0x800>; }; - ethernet@f0000 { + mac9: ethernet@f0000 { cell-index = <0x8>; compatible = "fsl,fman-memac"; reg = <0xf0000 0x1000>; @@ -29,7 +30,7 @@ pcsphy-handle = <&pcsphy6>; }; - mdio@f1000 { + mdio9: mdio@f1000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -9,19 +9,20 @@ fman@1a00000 { fman0_rx_0x11: port@91000 { cell-index = <0x11>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x91000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x31: port@b1000 { cell-index = <0x31>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb1000 0x1000>; fsl,fman-10g-port; + fsl,qman-channel-id = <0x801>; }; - ethernet@f2000 { + mac10: ethernet@f2000 { cell-index = <0x9>; compatible = "fsl,fman-memac"; reg = <0xf2000 0x1000>; @@ -29,7 +30,7 @@ pcsphy-handle = <&pcsphy7>; }; - mdio@f3000 { + mdio10: mdio@f3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; + fsl,qman-channel-id = <0x802>; }; ethernet@e0000 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; + fsl,qman-channel-id = <0x803>; }; ethernet@e2000 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman0_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; + fsl,qman-channel-id = <0x804>; }; ethernet@e4000 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman0_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; + fsl,qman-channel-id = <0x805>; }; ethernet@e6000 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman0_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; + fsl,qman-channel-id = <0x806>; }; ethernet@e8000 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -9,14 +9,15 @@ fman@1a00000 { fman0_rx_0x0d: port@8d000 { cell-index = <0xd>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; reg = <0x8d000 0x1000>; }; fman0_tx_0x2d: port@ad000 { cell-index = <0x2d>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; reg = <0xad000 0x1000>; + fsl,qman-channel-id = <0x807>; }; ethernet@ea000 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -0,0 +1,47 @@ +/* + * QorIQ FMan v3 OH ports device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + */ + +fman@1a00000 { + + fman0_oh1: port@82000 { + cell-index = <0>; + compatible = "fsl,fman-port-oh"; + reg = <0x82000 0x1000>; + }; + + fman0_oh2: port@83000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + }; + + fman0_oh3: port@84000 { + cell-index = <2>; + compatible = "fsl,fman-port-oh"; + reg = <0x84000 0x1000>; + }; + + fman0_oh4: port@85000 { + cell-index = <3>; + compatible = "fsl,fman-port-oh"; + reg = <0x85000 0x1000>; + }; + + fman0_oh5: port@86000 { + cell-index = <4>; + compatible = "fsl,fman-port-oh"; + reg = <0x86000 0x1000>; + }; + + fman0_oh6: port@87000 { + cell-index = <5>; + compatible = "fsl,fman-port-oh"; + reg = <0x87000 0x1000>; + }; + +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -23,45 +23,95 @@ ptimer-handle = <&ptp_timer0>; dma-coherent; + cc { + compatible = "fsl,fman-cc"; + }; + muram@0 { compatible = "fsl,fman-muram"; reg = <0x0 0x60000>; }; + bmi@80000 { + compatible = "fsl,fman-bmi"; + reg = <0x80000 0x400>; + }; + + qmi@80400 { + compatible = "fsl,fman-qmi"; + reg = <0x80400 0x400>; + }; + fman0_oh_0x2: port@82000 { cell-index = <0x2>; compatible = "fsl,fman-v3-port-oh"; reg = <0x82000 0x1000>; + fsl,qman-channel-id = <0x809>; }; fman0_oh_0x3: port@83000 { cell-index = <0x3>; compatible = "fsl,fman-v3-port-oh"; reg = <0x83000 0x1000>; + fsl,qman-channel-id = <0x80a>; }; fman0_oh_0x4: port@84000 { cell-index = <0x4>; compatible = "fsl,fman-v3-port-oh"; reg = <0x84000 0x1000>; + fsl,qman-channel-id = <0x80b>; }; fman0_oh_0x5: port@85000 { cell-index = <0x5>; compatible = "fsl,fman-v3-port-oh"; reg = <0x85000 0x1000>; + fsl,qman-channel-id = <0x80c>; }; fman0_oh_0x6: port@86000 { cell-index = <0x6>; compatible = "fsl,fman-v3-port-oh"; reg = <0x86000 0x1000>; + fsl,qman-channel-id = <0x80d>; }; fman0_oh_0x7: port@87000 { cell-index = <0x7>; compatible = "fsl,fman-v3-port-oh"; reg = <0x87000 0x1000>; + fsl,qman-channel-id = <0x80e>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + + vsps@dc000 { + compatible = "fsl,fman-vsps"; + reg = <0xdc000 0x1000>; }; mdio0: mdio@fc000 { @@ -80,7 +130,7 @@ }; ptp_timer0: ptp-timer@1afe000 { - compatible = "fsl,fman-ptp-timer"; + compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc"; reg = <0x0 0x1afe000 0x0 0x1000>; interrupts = ; clocks = <&clockgen QORIQ_CLK_FMAN 0>; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -0,0 +1,38 @@ +/* + * QorIQ QMan SDK Portals device tree nodes + * + * Copyright 2011-2016 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + */ + +&qportals { + qman-fqids@0 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <256 256>; + }; + + qman-fqids@1 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <32768 32768>; + }; + + qman-pools@0 { + compatible = "fsl,pool-channel-range"; + fsl,pool-channel-range = <0x401 0xf>; + }; + + qman-cgrids@0 { + compatible = "fsl,cgrid-range"; + fsl,cgrid-range = <0 256>; + }; + + qman-ceetm@0 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf00000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 32>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/s32v234.dtsi linux-imx-phytec/arch/arm64/boot/dts/freescale/s32v234.dtsi --- linux-6.1.55/arch/arm64/boot/dts/freescale/s32v234.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/s32v234.dtsi 2024-06-19 12:33:58.316192840 +0200 @@ -5,6 +5,8 @@ */ #include +#include +#include /memreserve/ 0x80000000 0x00010000; @@ -15,10 +17,28 @@ #size-cells = <2>; aliases { + can0 = &can0; + can1 = &can1; serial0 = &uart0; serial1 = &uart1; }; + clocks { + #address-cells = <1>; + #size-cells = <0>; + + firc { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + fxosc { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -112,12 +132,117 @@ reg = <0x0 0x40000000 0x0 0x7d000>; ranges; + edma: dma-controller@40002000 { + #dma-cells = <2>; + compatible = "fsl,s32v234-edma"; + reg = <0x0 0x40002000 0x0 0x2000>, + <0x0 0x40031000 0x0 0x1000>, + <0x0 0x400A1000 0x0 0x1000>; + dma-channels = <32>; + interrupts = , + , + ; + interrupt-names = "edma-tx_0-15", + "edma-tx_16-31", + "edma-err"; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clks S32V234_CLK_SYS6>, + <&clks S32V234_CLK_SYS6>; + status = "disabled"; + }; + + fec: ethernet@40032000 { + compatible = "fsl,s32v234-fec"; + reg = <0x0 0x40032000 0x0 0x1000>; + interrupt-names = "int0", "int1", "int2", "pps"; + interrupts = , + , + , + ; + clocks = <&clks S32V234_CLK_SYS6>, + <&clks S32V234_CLK_SYS3>, + <&clks S32V234_CLK_ENET_TIME>, + <&clks S32V234_CLK_ENET>, + <&clks S32V234_CLK_ENET_TIME>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", + "enet_out"; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + status = "disabled"; + }; + + clks: mc_cgm0@4003c000 { + compatible = "fsl,s32v234-mc_cgm0"; + reg = <0x0 0x4003C000 0x0 0x1000>; + #clock-cells = <1>; + }; + + mc_cgm1: mc_cgm1@4003F000 { + compatible = "fsl,s32v234-mc_cgm1"; + reg = <0x0 0x4003F000 0x0 0x1000>; + }; + + mc_cgm2: mc_cgm2@40042000 { + compatible = "fsl,s32v234-mc_cgm2"; + reg = <0x0 0x40042000 0x0 0x1000>; + }; + + mc_cgm3: mc_cgm3@40045000 { + compatible = "fsl,s32v234-mc_cgm3"; + reg = <0x0 0x40045000 0x0 0x1000>; + }; + + mc_me: mc_me@4004a000 { + compatible = "fsl,s32v234-mc_me"; + reg = <0x0 0x4004A000 0x0 0x1000>; + }; + uart0: serial@40053000 { compatible = "fsl,s32v234-linflexuart"; reg = <0x0 0x40053000 0x0 0x1000>; interrupts = ; + clocks = <&clks S32V234_CLK_LIN>; + clock-names = "lin"; + dmas = <&edma 0 20>, + <&edma 0 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + can0: flexcan@40055000 { + compatible = "fsl,s32v234-flexcan"; + reg = <0x0 0x40055000 0x0 0x1000>; + interrupts = ; + clocks = <&clks S32V234_CLK_CAN>, + <&clks S32V234_CLK_CAN>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + usdhc0: usdhc@4005d000 { + compatible = "fsl,s32v234-usdhc"; + reg = <0x0 0x4005D000 0x0 0x1000>; + interrupts = <0 28 4>; + clocks = <&clks S32V234_CLK_SDHC>, + <&clks S32V234_CLK_SDHC>, + <&clks S32V234_CLK_SDHC>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; status = "disabled"; }; + + siul2: siul@4006c000 { + compatible = "fsl,s32v234-siul2"; + reg = <0x0 0x4006C000 0x0 0x1794>; + status = "disabled"; + }; + + src: src@4007c000 { + compatible = "fsl,s32v234-src"; + reg = <0x0 0x4007C000 0x0 0x1000>; + #reset-cells = <1>; + }; }; aips1: bus@40080000 { @@ -132,6 +257,21 @@ compatible = "fsl,s32v234-linflexuart"; reg = <0x0 0x400bc000 0x0 0x1000>; interrupts = ; + clocks = <&clks S32V234_CLK_LIN>; + clock-names = "lin"; + dmas = <&edma 1 13>, + <&edma 1 12>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + can1: flexcan@400be000 { + compatible = "fsl,s32v234-flexcan"; + reg = <0x0 0x400be000 0x0 0x1000>; + interrupts = ; + clocks = <&clks S32V234_CLK_CAN>, + <&clks S32V234_CLK_CAN>; + clock-names = "ipg", "per"; status = "disabled"; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/s32v234-evb.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/s32v234-evb.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/s32v234-evb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/s32v234-evb.dts 2024-06-19 12:33:58.316192840 +0200 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2017,2019 NXP */ /dts-v1/; @@ -16,10 +16,105 @@ }; }; +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&edma { + status = "okay"; +}; + +&siul2 { + status = "okay"; + s32v234-evb { + + /* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the + * IMCR_IDX instead of MSCR_IDX, add 512 to it as the Reference + * Manual states. + */ + + pinctrl_can0: can0grp { + fsl,pins = < + S32V234_PAD_PA2__CAN_FD0_TXD + S32V234_PAD_PA3__CAN_FD0_RXD_OUT + S32V234_PAD_PA3__CAN_FD0_RXD_IN + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + S32V234_PAD_PA4__CAN_FD1_TXD + S32V234_PAD_PA5__CAN_FD1_RXD_OUT + S32V234_PAD_PA5__CAN_FD1_RXD_IN + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + S32V234_PAD_PA12__UART0_TXD + S32V234_PAD_PA11__UART0_RXD_OUT + S32V234_PAD_PA11__UART0_RXD_IN + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + S32V234_PAD_PA14__UART1_TXD + S32V234_PAD_PA13__UART1_RXD_OUT + S32V234_PAD_PA13__UART1_RXD_IN + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + S32V234_PAD_PK6__USDHC_CLK_OUT + S32V234_PAD_PK6__USDHC_CLK_IN + S32V234_PAD_PK7__USDHC_CMD_OUT + S32V234_PAD_PK7__USDHC_CMD_IN + S32V234_PAD_PK8__USDHC_DAT0_OUT + S32V234_PAD_PK8__USDHC_DAT0_IN + S32V234_PAD_PK9__USDHC_DAT1_OUT + S32V234_PAD_PK9__USDHC_DAT1_IN + S32V234_PAD_PK10__USDHC_DAT2_OUT + S32V234_PAD_PK10__USDHC_DAT2_IN + S32V234_PAD_PK11__USDHC_DAT3_OUT + S32V234_PAD_PK11__USDHC_DAT3_IN + S32V234_PAD_PK15__USDHC_DAT4_OUT + S32V234_PAD_PK15__USDHC_DAT4_IN + S32V234_PAD_PL0__USDHC_DAT5_OUT + S32V234_PAD_PL0__USDHC_DAT5_IN + S32V234_PAD_PL1__USDHC_DAT6_OUT + S32V234_PAD_PL1__USDHC_DAT6_IN + S32V234_PAD_PL2__USDHC_DAT7_OUT + S32V234_PAD_PL2__USDHC_DAT7_IN + >; + }; + }; +}; + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; status = "okay"; }; &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc0 { + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0>; status = "okay"; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/boot/dts/freescale/s32v234-sbc.dts linux-imx-phytec/arch/arm64/boot/dts/freescale/s32v234-sbc.dts --- linux-6.1.55/arch/arm64/boot/dts/freescale/s32v234-sbc.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/boot/dts/freescale/s32v234-sbc.dts 2024-06-19 12:33:58.316192840 +0200 @@ -0,0 +1,187 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 MicroSys Electronics GmbH + * Copyright 2018-2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; + +#include "s32v234.dtsi" + +/ { + model = "Freescale S32V234"; + compatible = "fsl,s32v234-sbc", "fsl,s32v234"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&edma { + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&siul2 { + status = "okay"; + + s32v234-sbc { + /* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the + * IMCR_IDX instead of MSCR_IDX, add 512 to it as the Reference + * Manual states. + */ + + pinctrl_can0: can0grp { + fsl,pins = < + S32V234_PAD_PA2__CAN_FD0_TXD + S32V234_PAD_PA3__CAN_FD0_RXD_OUT + S32V234_PAD_PA3__CAN_FD0_RXD_IN + /* + * Configure pin C12 as GPIO[6] in MSCR#6. + * Effect: the S-pin at CAN is not longer + * flowting at ~0.75V, but driven to low ~0.0V. + */ + S32V234_MSCR_PA6 (PAD_CTL_MUX_MODE_ALT0 \ + | PAD_CTL_OBE \ + | PAD_CTL_DSE_34 \ + | PAD_CTL_PUS_33K_UP) + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + S32V234_PAD_PA4__CAN_FD1_TXD + S32V234_PAD_PA5__CAN_FD1_RXD_OUT + S32V234_PAD_PA5__CAN_FD1_RXD_IN + /* + * Configure pin C11 as GPIO[7] in MSCR#7. + * Effect: the S-pin at CAN is not longer + * flowting at ~0.39V, but driven to low ~0.0V. + */ + S32V234_MSCR_PA7 (PAD_CTL_MUX_MODE_ALT0 \ + | PAD_CTL_OBE \ + | PAD_CTL_DSE_34 \ + | PAD_CTL_PUS_33K_UP) + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + S32V234_PAD_PC13__MDC + S32V234_PAD_PC14__MDIO_OUT + S32v234_PAD_PC14__MDIO_IN + S32V234_PAD_PC15__TXCLK_OUT + S32V234_PAD_PC15__TXCLK_IN + S32V234_PAD_PD0__RXCLK_OUT + S32V234_PAD_PD0__RXCLK_IN + S32V234_PAD_PD1__RX_D0_OUT + S32V234_PAD_PD1__RX_D0_IN + S32V234_PAD_PD2__RX_D1_OUT + S32V234_PAD_PD2__RX_D1_IN + S32V234_PAD_PD3__RX_D2_OUT + S32V234_PAD_PD3__RX_D2_IN + S32V234_PAD_PD4__RX_D3_OUT + S32V234_PAD_PD4__RX_D3_IN + S32V234_PAD_PD4__RX_DV_OUT + S32V234_PAD_PD4__RX_DV_IN + S32V234_PAD_PD7__TX_D0_OUT + S32V234_PAD_PD8__TX_D1_OUT + S32V234_PAD_PD9__TX_D2_OUT + S32V234_PAD_PD10__TX_D3_OUT + S32V234_PAD_PD11__TX_EN_OUT + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + S32V234_PAD_PA12__UART0_TXD + S32V234_PAD_PA11__UART0_RXD_OUT + S32V234_PAD_PA11__UART0_RXD_IN + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + S32V234_PAD_PA14__UART1_TXD + S32V234_PAD_PA13__UART1_RXD_OUT + S32V234_PAD_PA13__UART1_RXD_IN + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + S32V234_PAD_PK6__USDHC_CLK_OUT + S32V234_PAD_PK6__USDHC_CLK_IN + S32V234_PAD_PK7__USDHC_CMD_OUT + S32V234_PAD_PK7__USDHC_CMD_IN + S32V234_PAD_PK8__USDHC_DAT0_OUT + S32V234_PAD_PK8__USDHC_DAT0_IN + S32V234_PAD_PK9__USDHC_DAT1_OUT + S32V234_PAD_PK9__USDHC_DAT1_IN + S32V234_PAD_PK10__USDHC_DAT2_OUT + S32V234_PAD_PK10__USDHC_DAT2_IN + S32V234_PAD_PK11__USDHC_DAT3_OUT + S32V234_PAD_PK11__USDHC_DAT3_IN + S32V234_PAD_PK15__USDHC_DAT4_OUT + S32V234_PAD_PK15__USDHC_DAT4_IN + S32V234_PAD_PL0__USDHC_DAT5_OUT + S32V234_PAD_PL0__USDHC_DAT5_IN + S32V234_PAD_PL1__USDHC_DAT6_OUT + S32V234_PAD_PL1__USDHC_DAT6_IN + S32V234_PAD_PL2__USDHC_DAT7_OUT + S32V234_PAD_PL2__USDHC_DAT7_IN + >; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc0 { + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0>; + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/configs/defconfig linux-imx-phytec/arch/arm64/configs/defconfig --- linux-6.1.55/arch/arm64/configs/defconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/configs/defconfig 2024-06-19 12:33:58.400194276 +0200 @@ -27,6 +27,7 @@ CONFIG_CGROUP_BPF=y CONFIG_USER_NS=y CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y CONFIG_PROFILING=y @@ -36,13 +37,12 @@ CONFIG_ARCH_APPLE=y CONFIG_ARCH_BCM=y CONFIG_ARCH_BCM2835=y -CONFIG_ARCH_BCMBCA=y CONFIG_ARCH_BCM_IPROC=y -CONFIG_ARCH_BERLIN=y +CONFIG_ARCH_BCMBCA=y CONFIG_ARCH_BRCMSTB=y +CONFIG_ARCH_BERLIN=y CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_K3=y -CONFIG_ARCH_LAYERSCAPE=y CONFIG_ARCH_LG1K=y CONFIG_ARCH_HISI=y CONFIG_ARCH_KEEMBAY=y @@ -50,12 +50,14 @@ CONFIG_ARCH_MESON=y CONFIG_ARCH_MVEBU=y CONFIG_ARCH_NXP=y +CONFIG_ARCH_LAYERSCAPE=y CONFIG_ARCH_MXC=y +CONFIG_ARCH_S32=y +CONFIG_SOC_S32V234=y CONFIG_ARCH_NPCM=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_S32=y CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_INTEL_SOCFPGA=y CONFIG_ARCH_SYNQUACER=y @@ -80,6 +82,8 @@ CONFIG_COMPAT=y CONFIG_RANDOMIZE_BASE=y CONFIG_HIBERNATION=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y CONFIG_ENERGY_MODEL=y CONFIG_ARM_PSCI_CPUIDLE=y @@ -112,17 +116,6 @@ CONFIG_ACPI_APEI_EINJ=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64_CE=m -CONFIG_CRYPTO_SHA3_ARM64=m -CONFIG_CRYPTO_SM3_ARM64_CE=m -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_AES_ARM64_BS=m CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -172,6 +165,7 @@ CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y CONFIG_NET_SCHED=y +CONFIG_NET_SCH_MULTIQ=m CONFIG_NET_SCH_CBS=m CONFIG_NET_SCH_ETF=m CONFIG_NET_SCH_TAPRIO=m @@ -180,31 +174,42 @@ CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_FLOWER=m CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_ACT_GACT=m CONFIG_NET_ACT_MIRRED=m CONFIG_NET_ACT_GATE=m +CONFIG_LLC2=y +CONFIG_TSN=y +CONFIG_NET_SWITCHDEV=y CONFIG_QRTR_SMD=m CONFIG_QRTR_TUN=m +CONFIG_NET_PKTGEN=m CONFIG_CAN=m -CONFIG_CAN_FLEXCAN=m -CONFIG_CAN_RCAR=m -CONFIG_CAN_RCAR_CANFD=m -CONFIG_CAN_MCP251XFD=m CONFIG_BT=m CONFIG_BT_HIDP=m -# CONFIG_BT_LE is not set +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_LEDS=y # CONFIG_BT_DEBUGFS is not set CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_BCM=y CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m CONFIG_BT_QCOMSMD=m +CONFIG_BT_HCIVHCI=y CONFIG_CFG80211=m +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m CONFIG_MAC80211_LEDS=y CONFIG_RFKILL=m @@ -230,9 +235,10 @@ CONFIG_PCIE_ALTERA_MSI=y CONFIG_PCI_HOST_THUNDER_PEM=y CONFIG_PCI_HOST_THUNDER_ECAM=y +CONFIG_PCI_IMX6_HOST=y +CONFIG_PCI_IMX6_EP=y CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCIE_BRCMSTB=m -CONFIG_PCI_IMX6=y CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_HISI=y CONFIG_PCIE_QCOM=y @@ -256,11 +262,14 @@ CONFIG_INTEL_STRATIX10_SERVICE=y CONFIG_INTEL_STRATIX10_RSU=m CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_IMX_DSP=y CONFIG_IMX_SCU=y CONFIG_IMX_SCU_PD=y CONFIG_GNSS=m CONFIG_GNSS_MTK_SERIAL=m +CONFIG_FSL_MC_UAPI_SUPPORT=y CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -276,10 +285,14 @@ CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_BRCMNAND=m CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_GPMI_NAND=y CONFIG_MTD_NAND_QCOM=y CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m +CONFIG_XEN_BLKDEV_BACKEND=m CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_NVME=m CONFIG_QCOM_COINCELL=m @@ -300,6 +313,7 @@ CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y CONFIG_AHCI_BRCM=m +CONFIG_AHCI_IMX=y CONFIG_AHCI_CEVA=y CONFIG_AHCI_MVEBU=y CONFIG_AHCI_XGENE=y @@ -333,9 +347,12 @@ CONFIG_FSL_FMAN=y CONFIG_FSL_DPAA_ETH=y CONFIG_FSL_DPAA2_ETH=y +CONFIG_FSL_DPAA2_SWITCH=y CONFIG_FSL_ENETC=y CONFIG_FSL_ENETC_VF=y CONFIG_FSL_ENETC_QOS=y +CONFIG_FSL_ENETC_MDIO=y +CONFIG_ENETC_TSN=y CONFIG_HIX5HD2_GMAC=y CONFIG_HNS_DSAF=y CONFIG_HNS_ENET=y @@ -352,6 +369,7 @@ CONFIG_MLX4_EN=m CONFIG_MLX5_CORE=m CONFIG_MLX5_CORE_EN=y +CONFIG_MSCC_OCELOT_SWITCH=y CONFIG_QCOM_EMAC=m CONFIG_RMNET=m CONFIG_R8169=m @@ -362,9 +380,9 @@ CONFIG_SNI_AVE=y CONFIG_SNI_NETSEC=y CONFIG_STMMAC_ETH=m -CONFIG_DWMAC_TEGRA=m CONFIG_TI_K3_AM65_CPSW_NUSS=y CONFIG_QCOM_IPA=m +CONFIG_SFP=y CONFIG_MESON_GXL_PHY=m CONFIG_AQUANTIA_PHY=y CONFIG_BCM54140_PHY=m @@ -374,9 +392,14 @@ CONFIG_MICROSEMI_PHY=y CONFIG_AT803X_PHY=y CONFIG_REALTEK_PHY=y +CONFIG_NXP_TJA11XX_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_DP83867_PHY=y CONFIG_VITESSE_PHY=y +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_RCAR=m +CONFIG_CAN_RCAR_CANFD=m +CONFIG_CAN_MCP251XFD=m CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_USB_PEGASUS=m @@ -398,11 +421,13 @@ CONFIG_ATH11K_AHB=m CONFIG_ATH11K_PCI=m CONFIG_BRCMFMAC=m +CONFIG_HOSTAP=y CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m CONFIG_MWIFIEX_PCIE=m CONFIG_WL18XX=m CONFIG_WLCORE_SDIO=m +CONFIG_IVSHMEM_NET=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_ADC=m CONFIG_KEYBOARD_GPIO=y @@ -413,6 +438,7 @@ CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_GOODIX=m CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m CONFIG_INPUT_MISC=y CONFIG_INPUT_PM8941_PWRKEY=y CONFIG_INPUT_PM8XXX_VIBRATOR=m @@ -485,11 +511,14 @@ CONFIG_I2C_RK3X=y CONFIG_I2C_RZV2M=m CONFIG_I2C_S3C2410=y +CONFIG_I2C_RPBUS=y CONFIG_I2C_SH_MOBILE=y CONFIG_I2C_TEGRA=y CONFIG_I2C_UNIPHIER_F=y CONFIG_I2C_RCAR=y CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_I3C=y +CONFIG_SVC_I3C_MASTER=y CONFIG_SPI=y CONFIG_SPI_ARMADA_3700=y CONFIG_SPI_BCM2835=m @@ -519,6 +548,9 @@ CONFIG_SPI_TEGRA210_QUAD=m CONFIG_SPI_TEGRA114=m CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y CONFIG_SPMI=y CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_SINGLE=y @@ -538,6 +570,7 @@ CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_MSM8916=y +CONFIG_PINCTRL_S32V234=y CONFIG_PINCTRL_MSM8994=y CONFIG_PINCTRL_MSM8996=y CONFIG_PINCTRL_MSM8998=y @@ -556,7 +589,9 @@ CONFIG_PINCTRL_LPASS_LPI=m CONFIG_GPIO_ALTERA=m CONFIG_GPIO_DAVINCI=y +CONFIG_GPIO_SYSFS=y CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_IMX_RPMSG=y CONFIG_GPIO_MB86S7X=y CONFIG_GPIO_MPC8XXX=y CONFIG_GPIO_MXC=y @@ -573,6 +608,7 @@ CONFIG_GPIO_BD9571MWV=m CONFIG_GPIO_MAX77620=y CONFIG_GPIO_SL28CPLD=m +CONFIG_GPIO_QIXIS_CPLD=y CONFIG_POWER_RESET_MSM=y CONFIG_POWER_RESET_QCOM_PON=m CONFIG_POWER_RESET_XGENE=y @@ -589,19 +625,21 @@ CONFIG_SENSORS_GPIO_FAN=m CONFIG_SENSORS_JC42=m CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_FP9931=y CONFIG_SENSORS_LM90=m CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_SL28CPLD=m CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA3221=m +CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y -CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_IMX_SC_THERMAL=m CONFIG_IMX8MM_THERMAL=m CONFIG_QORIQ_THERMAL=m +CONFIG_DEVICE_THERMAL=y CONFIG_SUN8I_THERMAL=y CONFIG_ROCKCHIP_THERMAL=m CONFIG_RCAR_THERMAL=y @@ -626,8 +664,10 @@ CONFIG_S3C2410_WATCHDOG=y CONFIG_DW_WATCHDOG=y CONFIG_SUNXI_WATCHDOG=m +CONFIG_NPCM7XX_WATCHDOG=y CONFIG_IMX2_WDT=y CONFIG_IMX_SC_WDT=m +CONFIG_IMX7ULP_WDT=y CONFIG_QCOM_WDT=m CONFIG_MESON_GXBB_WATCHDOG=m CONFIG_MESON_WATCHDOG=m @@ -638,14 +678,15 @@ CONFIG_PM8916_WATCHDOG=m CONFIG_BCM2835_WDT=y CONFIG_BCM7038_WDT=m -CONFIG_NPCM7XX_WATCHDOG=y CONFIG_MFD_ALTERA_SYSMGR=y CONFIG_MFD_BD9571MWV=y CONFIG_MFD_AXP20X_I2C=y CONFIG_MFD_AXP20X_RSB=y CONFIG_MFD_EXYNOS_LPASS=m CONFIG_MFD_HI6421_PMIC=y +CONFIG_MFD_FP9931=y CONFIG_MFD_HI655X_PMIC=y +CONFIG_MFD_IMX_MIX=y CONFIG_MFD_MAX77620=y CONFIG_MFD_MT6360=y CONFIG_MFD_MT6397=y @@ -665,6 +706,7 @@ CONFIG_REGULATOR_HI655X=y CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_MAX8973=y +CONFIG_REGULATOR_FP9931=y CONFIG_REGULATOR_MP8859=y CONFIG_REGULATOR_MT6358=y CONFIG_REGULATOR_MT6359=y @@ -683,7 +725,19 @@ CONFIG_REGULATOR_VCTRL=m CONFIG_RC_CORE=m CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_RCMM_DECODER=m CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m CONFIG_IR_MESON=m CONFIG_IR_SUNXI=m CONFIG_MEDIA_SUPPORT=m @@ -703,6 +757,12 @@ CONFIG_VIDEO_RCAR_ISP=m CONFIG_VIDEO_RCAR_CSI2=m CONFIG_VIDEO_RCAR_VIN=m +CONFIG_VIDEO_MX8_CAPTURE=y +CONFIG_VIDEO_MXC_CAPTURE=y +CONFIG_VIDEO_MXC_CSI_CAMERA=y +CONFIG_VIDEO_IMX8_JPEG=m +CONFIG_MXC_MIPI_CSI=y +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y CONFIG_VIDEO_RENESAS_FCP=m CONFIG_VIDEO_RENESAS_FDP1=m CONFIG_VIDEO_RENESAS_VSP1=m @@ -711,10 +771,14 @@ CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m CONFIG_VIDEO_SUN6I_CSI=m +CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_OV5640=m CONFIG_VIDEO_OV5645=m CONFIG_DRM=m +CONFIG_IMX8MM_LCDIF_CORE=y +CONFIG_IMX_DPU_CORE=y +CONFIG_IMX_LCDIFV3_CORE=y CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_HDLCD=m CONFIG_DRM_MALI_DISPLAY=m @@ -738,17 +802,15 @@ CONFIG_DRM_RCAR_DW_HDMI=m CONFIG_DRM_RCAR_MIPI_DSI=m CONFIG_DRM_SUN4I=m -CONFIG_DRM_SUN6I_DSI=m -CONFIG_DRM_SUN8I_DW_HDMI=m -CONFIG_DRM_SUN8I_MIXER=m CONFIG_DRM_MSM=m -CONFIG_DRM_TEGRA=m CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_EDP=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m CONFIG_DRM_PANEL_RAYDIUM_RM67191=m +CONFIG_DRM_PANEL_RAYDIUM_RM68200=y +CONFIG_DRM_PANEL_ROCKTECK_HIMAX8394F=y CONFIG_DRM_PANEL_SITRONIX_ST7703=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m CONFIG_DRM_LONTIUM_LT8912B=m @@ -756,6 +818,10 @@ CONFIG_DRM_LONTIUM_LT9611UXC=m CONFIG_DRM_NWL_MIPI_DSI=m CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y +CONFIG_DRM_PANEL_WKS_101WX001=y +CONFIG_DRM_NXP_SEIKO_43WVFIG=y CONFIG_DRM_SII902X=m CONFIG_DRM_SIMPLE_BRIDGE=m CONFIG_DRM_THINE_THC63LVD1024=m @@ -764,9 +830,27 @@ CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_DRM_CDNS_MHDP8546=m CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_GP_AUDIO=y CONFIG_DRM_DW_HDMI_CEC=m +CONFIG_DRM_DW_MIPI_DSI=y CONFIG_DRM_IMX_DCSS=m CONFIG_DRM_V3D=m +CONFIG_DRM_CDNS_HDCP=y +CONFIG_DRM_CDNS_HDMI_CEC=y +CONFIG_DRM_ITE_IT6263=y +CONFIG_DRM_ITE_IT6161=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX8QM_LDB=y +CONFIG_DRM_IMX8QXP_LDB=y +CONFIG_DRM_IMX8MP_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_CDNS_MHDP=y +CONFIG_DRM_IMX_DCNANO=y CONFIG_DRM_VC4=m CONFIG_DRM_ETNAVIV=m CONFIG_DRM_HISI_HIBMC=m @@ -781,8 +865,10 @@ CONFIG_DRM_TIDSS=m CONFIG_FB=y CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_ARMCLCD=y CONFIG_FB_EFI=y CONFIG_BACKLIGHT_PWM=m +CONFIG_FB_MXC_EINK_V2_PANEL=y CONFIG_BACKLIGHT_LP855X=m CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set @@ -791,16 +877,31 @@ CONFIG_SND=y CONFIG_SND_HDA_TEGRA=m CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=y CONFIG_SND_BCM2835_SOC_I2S=m CONFIG_SND_SOC_FSL_ASRC=m CONFIG_SND_SOC_FSL_MICFIL=m CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_ESAI_CLIENT=y +CONFIG_SND_SOC_FSL_DAI=m +CONFIG_SND_SOC_FSL_MQS=y +CONFIG_SND_SOC_FSL_RPMSG=m CONFIG_SND_IMX_SOC=m CONFIG_SND_SOC_IMX_SGTL5000=m CONFIG_SND_SOC_IMX_SPDIF=m CONFIG_SND_SOC_FSL_ASOC_CARD=m CONFIG_SND_SOC_IMX_AUDMIX=m +CONFIG_SND_SOC_IMX_AK4458=y +CONFIG_SND_SOC_IMX_AK5558=y +CONFIG_SND_SOC_IMX_AK4497=y +CONFIG_SND_SOC_IMX_MICFIL=y +CONFIG_SND_SOC_IMX_RPMSG=y +CONFIG_SND_SOC_IMX_PDM_MIC=y +CONFIG_SND_SOC_IMX_DSP=m +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_SND_SOC_IMX_XCVR=y +CONFIG_SND_SOC_IMX_PCM512X=y CONFIG_SND_MESON_AXG_SOUND_CARD=m CONFIG_SND_MESON_GX_SOUND_CARD=m CONFIG_SND_SOC_QCOM=m @@ -820,6 +921,12 @@ CONFIG_SND_SUN8I_CODEC=m CONFIG_SND_SUN8I_CODEC_ANALOG=m CONFIG_SND_SUN50I_CODEC_ANALOG=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y +CONFIG_SND_SOC_SOF_IMX8=m +CONFIG_SND_SOC_SOF_IMX8M=m +CONFIG_SND_SOC_SOF_IMX8ULP=m CONFIG_SND_SUN4I_I2S=m CONFIG_SND_SUN4I_SPDIF=m CONFIG_SND_SOC_TEGRA=m @@ -836,7 +943,10 @@ CONFIG_SND_SOC_TEGRA210_ADX=m CONFIG_SND_SOC_TEGRA210_MIXER=m CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m +CONFIG_SND_SOC_CS42XX8=y +CONFIG_SND_SOC_CS42XX8_I2C=y CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_BT_SCO=y CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m CONFIG_SND_SOC_GTM601=m @@ -846,6 +956,7 @@ CONFIG_SND_SOC_RT5659=m CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_TAS571X=m CONFIG_SND_SOC_TLV320AIC32X4_I2C=m CONFIG_SND_SOC_WCD9335=m @@ -857,6 +968,8 @@ CONFIG_SND_SOC_WM8978=m CONFIG_SND_SOC_WSA881X=m CONFIG_SND_SOC_NAU8822=m +CONFIG_SND_SOC_RPMSG_WM8960=m +CONFIG_SND_SOC_RPMSG_AK4497=m CONFIG_SND_SOC_LPASS_WSA_MACRO=m CONFIG_SND_SOC_LPASS_VA_MACRO=m CONFIG_SND_SOC_LPASS_RX_MACRO=m @@ -887,7 +1000,9 @@ CONFIG_USB_CDNS3=m CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_IMX=y CONFIG_USB_MTU3=y +CONFIG_USB_UAS=y CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SUNXI=y CONFIG_USB_DWC3=y @@ -900,8 +1015,11 @@ CONFIG_USB_SERIAL_CP210X=m CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m CONFIG_USB_HSIC_USB3503=y CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=m CONFIG_USB_RENESAS_USB3=m @@ -916,10 +1034,23 @@ CONFIG_USB_CONFIGFS_RNDIS=y CONFIG_USB_CONFIGFS_EEM=y CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y CONFIG_USB_CONFIGFS_F_FS=y CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_TYPEC_SWITCH_GPIO=y CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_TPS6598X=m CONFIG_TYPEC_HD3SS3220=m @@ -976,6 +1107,7 @@ CONFIG_EDAC=y CONFIG_EDAC_GHES=y CONFIG_EDAC_LAYERSCAPE=m +CONFIG_EDAC_SYNOPSYS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=m CONFIG_RTC_DRV_HYM8563=m @@ -990,6 +1122,7 @@ CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF2131=m CONFIG_RTC_DRV_EFI=y CONFIG_RTC_DRV_CROS_EC=y CONFIG_RTC_DRV_FSL_FTM_ALARM=m @@ -1008,10 +1141,13 @@ CONFIG_DMA_SUN6I=m CONFIG_FSL_EDMA=y CONFIG_IMX_SDMA=m +CONFIG_FSL_QDMA=m +CONFIG_FSL_EDMA_V3=y CONFIG_K3_DMA=y CONFIG_MV_XOR=y CONFIG_MV_XOR_V2=y CONFIG_OWL_DMA=y +CONFIG_MXS_DMA=y CONFIG_PL330_DMA=y CONFIG_TEGRA186_GPC_DMA=y CONFIG_TEGRA20_APB_DMA=y @@ -1023,10 +1159,15 @@ CONFIG_RCAR_DMAC=y CONFIG_RENESAS_USB_DMAC=m CONFIG_RZ_DMAC=y +CONFIG_FSL_DPAA2_QDMA=m CONFIG_TI_K3_UDMA=y CONFIG_TI_K3_UDMA_GLUE_LAYER=y +CONFIG_DMATEST=y +CONFIG_UIO=y +CONFIG_UIO_PCI_GENERIC=y CONFIG_VFIO=y CONFIG_VFIO_PCI=y +CONFIG_VFIO_FSL_MC=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_MMIO=y @@ -1034,9 +1175,16 @@ CONFIG_XEN_GRANT_DEV_ALLOC=y CONFIG_STAGING=y CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_IMX_MEDIA=m CONFIG_VIDEO_MAX96712=m +CONFIG_VIDEO_IMX_CAPTURE=y +CONFIG_ION=y +CONFIG_ION_SYSTEM_HEAP=y +CONFIG_ION_CMA_HEAP=y +CONFIG_FSL_DPAA2=y +CONFIG_FSL_DPAA2_MAC=y +CONFIG_FSL_PPFE=y +CONFIG_FSL_PPFE_UTIL_DISABLED=y CONFIG_CHROME_PLATFORMS=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y @@ -1050,7 +1198,6 @@ CONFIG_COMMON_CLK_S2MPS11=y CONFIG_COMMON_CLK_PWM=y CONFIG_COMMON_CLK_VC5=y -CONFIG_COMMON_CLK_NPCM8XX=y CONFIG_COMMON_CLK_BD718XX=m CONFIG_CLK_RASPBERRYPI=m CONFIG_CLK_IMX8MM=y @@ -1126,6 +1273,7 @@ CONFIG_FSL_RCPM=y CONFIG_MTK_DEVAPC=m CONFIG_MTK_PMIC_WRAP=y +CONFIG_FSL_QIXIS=y CONFIG_QCOM_AOSS_QMP=y CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_CPR=y @@ -1174,17 +1322,17 @@ CONFIG_ARCH_TEGRA_194_SOC=y CONFIG_ARCH_TEGRA_234_SOC=y CONFIG_TI_SCI_PM_DOMAINS=y -CONFIG_ARM_IMX_BUS_DEVFREQ=m -CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m CONFIG_EXTCON_PTN5150=m CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_USBC_CROS_EC=y CONFIG_RENESAS_RPCIF=m CONFIG_IIO=y +CONFIG_FXLS8962AF_I2C=m CONFIG_EXYNOS_ADC=y CONFIG_MAX9611=m CONFIG_QCOM_SPMI_VADC=m CONFIG_QCOM_SPMI_ADC5=m +CONFIG_IMX8QXP_ADC=y CONFIG_ROCKCHIP_SARADC=m CONFIG_RZG2L_ADC=m CONFIG_TI_ADS1015=m @@ -1202,6 +1350,8 @@ CONFIG_PWM_BRCMSTB=m CONFIG_PWM_CROS_EC=m CONFIG_PWM_IMX27=m +CONFIG_PWM_FSL_FTM=m +CONFIG_PWM_RPCHIP=y CONFIG_PWM_MESON=m CONFIG_PWM_MTK_DISP=m CONFIG_PWM_MEDIATEK=m @@ -1220,12 +1370,18 @@ CONFIG_RESET_QCOM_PDC=m CONFIG_RESET_RZG2L_USBPHY_CTRL=y CONFIG_RESET_TI_SCI=y +CONFIG_RESET_IMX8ULP_SIM=y +CONFIG_PHY_CADENCE_SALVO=y CONFIG_PHY_XGENE=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_CADENCE_TORRENT=m CONFIG_PHY_CADENCE_SIERRA=m CONFIG_PHY_MIXEL_MIPI_DPHY=m CONFIG_PHY_FSL_IMX8M_PCIE=y +CONFIG_PHY_FSL_IMX8MP_LVDS=y +CONFIG_PHY_SAMSUNG_HDMI_PHY=y CONFIG_PHY_HI6220_USB=y CONFIG_PHY_HISTB_COMBPHY=y CONFIG_PHY_HISI_INNO_USB2=y @@ -1254,6 +1410,7 @@ CONFIG_PHY_TEGRA_XUSB=y CONFIG_PHY_AM654_SERDES=m CONFIG_PHY_J721E_WIZ=m +CONFIG_PHY_INPHI_IN112525_RETIMER=y CONFIG_ARM_CCI_PMU=m CONFIG_ARM_CCN=m CONFIG_ARM_CMN=m @@ -1267,14 +1424,14 @@ CONFIG_HISI_PMU=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_IMX_OCOTP_SCU=y +CONFIG_NVMEM_LAYERSCAPE_SFP=m +CONFIG_NVMEM_MESON_EFUSE=m CONFIG_NVMEM_MTK_EFUSE=y CONFIG_NVMEM_QCOM_QFPROM=y +CONFIG_NVMEM_RMEM=m CONFIG_NVMEM_ROCKCHIP_EFUSE=y CONFIG_NVMEM_SUNXI_SID=y CONFIG_NVMEM_UNIPHIER_EFUSE=y -CONFIG_NVMEM_MESON_EFUSE=m -CONFIG_NVMEM_RMEM=m -CONFIG_NVMEM_LAYERSCAPE_SFP=m CONFIG_FPGA=y CONFIG_FPGA_MGR_ALTERA_CVP=m CONFIG_FPGA_MGR_STRATIX10_SOC=m @@ -1285,14 +1442,10 @@ CONFIG_TEE=y CONFIG_OPTEE=y CONFIG_MUX_MMIO=y -CONFIG_SLIMBUS=m CONFIG_SLIM_QCOM_CTRL=m CONFIG_SLIM_QCOM_NGD_CTRL=m -CONFIG_INTERCONNECT=y -CONFIG_INTERCONNECT_IMX=m -CONFIG_INTERCONNECT_IMX8MM=m -CONFIG_INTERCONNECT_IMX8MN=m -CONFIG_INTERCONNECT_IMX8MQ=m +CONFIG_MXC_SIM=y +CONFIG_MXC_EMVSIM=y CONFIG_INTERCONNECT_QCOM=y CONFIG_INTERCONNECT_QCOM_MSM8916=m CONFIG_INTERCONNECT_QCOM_MSM8996=m @@ -1322,8 +1475,9 @@ CONFIG_VFAT_FS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_HUGETLBFS=y -CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y CONFIG_SQUASHFS=y CONFIG_NFS_FS=y CONFIG_NFS_V4=y @@ -1334,12 +1488,25 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_SECURITY=y +CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m CONFIG_CRYPTO_DEV_SUN8I_CE=m CONFIG_CRYPTO_DEV_FSL_CAAM=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m CONFIG_CRYPTO_DEV_QCOM_RNG=m CONFIG_CRYPTO_DEV_CCREE=m @@ -1366,3 +1533,16 @@ CONFIG_CORESIGHT_CPU_DEBUG=m CONFIG_CORESIGHT_CTI=m CONFIG_MEMTEST=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_SOURCE_ETM4X=y +CONFIG_IMX8_MEDIA_DEVICE=m +CONFIG_IMX8_ISI_HW=y +CONFIG_IMX8_ISI_CORE=y +CONFIG_IMX8_ISI_CAPTURE=y +CONFIG_IMX8_ISI_M2M=y +CONFIG_IMX8_MIPI_CSI2=y +CONFIG_IMX8_MIPI_CSI2_SAM=y +CONFIG_IMX8_PARALLEL_CSI=y +CONFIG_GMSL_MAX9286=y +CONFIG_MXC_PXP_V3=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/configs/imx8qm_cockpit.config linux-imx-phytec/arch/arm64/configs/imx8qm_cockpit.config --- linux-6.1.55/arch/arm64/configs/imx8qm_cockpit.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/configs/imx8qm_cockpit.config 2024-06-19 12:33:58.400194276 +0200 @@ -0,0 +1,3 @@ +CONFIG_IMX_SHMEM_NET=y +CONFIG_GIC_GENTLE_CONFIG=y +CONFIG_PANIC_TIMEOUT=-1 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/configs/imx9_phytec_distro.config linux-imx-phytec/arch/arm64/configs/imx9_phytec_distro.config --- linux-6.1.55/arch/arm64/configs/imx9_phytec_distro.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/configs/imx9_phytec_distro.config 2024-06-19 12:33:58.400194276 +0200 @@ -0,0 +1 @@ +# CONFIG_AUDIT is not set diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/configs/imx9_phytec_platform.config linux-imx-phytec/arch/arm64/configs/imx9_phytec_platform.config --- linux-6.1.55/arch/arm64/configs/imx9_phytec_platform.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/configs/imx9_phytec_platform.config 2024-06-19 12:33:58.400194276 +0200 @@ -0,0 +1,8 @@ +CONFIG_EEPROM_AT24=y +CONFIG_DP83822_PHY=y +CONFIG_DP83867_PHY=y +CONFIG_SND_SOC_TLV320AIC3X_I2C=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_DMABUF_HEAPS_DSP=n +CONFIG_PWM_IMX_TPM=y +CONFIG_USB_HIDDEV=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/configs/imx.config linux-imx-phytec/arch/arm64/configs/imx.config --- linux-6.1.55/arch/arm64/configs/imx.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/configs/imx.config 2024-06-19 12:33:58.400194276 +0200 @@ -0,0 +1,313 @@ +# imx specific options +# +# required by GPU +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_SQUASHFS_XZ=y +CONFIG_CGROUP_FREEZER=y + +# disable other ARCH +CONFIG_ARCH_AGILEX=n +CONFIG_ARCH_SUNXI=n +CONFIG_ARCH_ALPINE=n +CONFIG_ARCH_BCM2835=n +CONFIG_ARCH_BCM_IPROC=n +CONFIG_ARCH_BERLIN=n +CONFIG_ARCH_BRCMSTB=n +CONFIG_ARCH_EXYNOS=n +CONFIG_ARCH_K3=n +CONFIG_ARCH_LG1K=n +CONFIG_ARCH_HISI=n +CONFIG_ARCH_MEDIATEK=n +CONFIG_ARCH_MESON=n +CONFIG_ARCH_MVEBU=n +CONFIG_ARCH_QCOM=n +CONFIG_ARCH_RENESAS=n +CONFIG_ARCH_ROCKCHIP=n +CONFIG_ARCH_SEATTLE=n +CONFIG_ARCH_STRATIX10=n +CONFIG_ARCH_SYNQUACER=n +CONFIG_ARCH_TEGRA=n +CONFIG_ARCH_SPRD=n +CONFIG_ARCH_THUNDER=n +CONFIG_ARCH_THUNDER2=n +CONFIG_ARCH_UNIPHIER=n +CONFIG_ARCH_VEXPRESS=n +CONFIG_ARCH_XGENE=n +CONFIG_ARCH_ZX=n +CONFIG_ARCH_ZYNQMP=n +CONFIG_ARCH_ACTIONS=n +CONFIG_ARCH_VISCONTI=n +CONFIG_ARCH_APPLE=n +CONFIG_ARCH_BCM=n +CONFIG_ARCH_KEEMBAY=n +CONFIG_ARCH_NPCM=n +CONFIG_ARCH_INTEL_SOCFPGA=n + +# disable features +CONFIG_HIBERNATION=n + +# USB related +CONFIG_USB_OTG_WHITELIST=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_RTL8152=y +CONFIG_USB_USBNET=y + +# networking related +CONFIG_BRCMFMAC=n +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_DWMAC_IMX8=y +CONFIG_FEC_UIO=y +CONFIG_TLS=y +CONFIG_TLS_DEVICE=y + +# cpu-freq related +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y + +#remoteproc +CONFIG_IMX_REMOTEPROC=y +CONFIG_IMX_DSP_REMOTEPROC=m + +#xen +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_XEN_I2C_BACKEND=y +CONFIG_XEN_WDT=y + +#uio for jailhouse +CONFIG_UIO_IVSHMEM=y +CONFIG_VIRTIO_IVSHMEM=y + +# crypto related +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_TLS=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_XXHASH=m +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_DM_CRYPT=m + +# enable Trusted Keys based on CAAM +CONFIG_TRUSTED_KEYS=m +CONFIG_TRUSTED_KEYS_TPM=n +CONFIG_TRUSTED_KEYS_TEE=n +CONFIG_TRUSTED_KEYS_CAAM=y + +# enable DMABUF heaps +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_DMABUF_HEAPS_DSP=y + +#disabled drivers +CONFIG_COMMON_CLK_BD718XX=n +CONFIG_RFKILL=n +CONFIG_MWIFIEX=n +CONFIG_MWIFIEX_PCIE=n +CONFIG_ATH10K=n +CONFIG_ATH10K_PCI=n +CONFIG_ATH10K_SNOC=n + +#touch related +CONFIG_TOUCHSCREEN_EXC3000=m + +#adc related +CONFIG_IMX93_ADC=y + +#gpio related +CONFIG_GPIO_ADP5585=y +CONFIG_MFD_ADP5585=y + +#sensor related +CONFIG_FXAS21002C=y +CONFIG_FXOS8700_I2C=y +CONFIG_RPMSG_IIO_PEDOMETER=m +CONFIG_SENSORS_ISL29018=y +CONFIG_MPL3115=y + +#led related +CONFIG_LEDS_PCA995X=m + +#audio +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_IMX_CARD=m +CONFIG_RPMSG_CHAR=m +CONFIG_SND_SOC_SOF_COMPRESS=y +CONFIG_SND_ALOOP=m + +#rtc +CONFIG_RTC_DRV_IMX_RPMSG=y + +#key +CONFIG_KEYBOARD_RPMSG=y + +# enable AF_ALG +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_AEAD=m + +# ipv6 +CONFIG_IPV6=y +CONFIG_IPV6_SIT=m + +# build-in drivers +CONFIG_ARM_IMX_CPUFREQ_DT=y +CONFIG_BT=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y +CONFIG_PCI_EPF_TEST=y +CONFIG_PCI_ENDPOINT_TEST=y +CONFIG_BLK_DEV_NVME=y +CONFIG_KEYBOARD_SNVS_PWRKEY=y +CONFIG_KEYBOARD_IMX_SC_KEY=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_IMX_SC_THERMAL=y +CONFIG_IMX8MM_THERMAL=y +CONFIG_IMX_SC_WDT=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_DRM=y +CONFIG_MXC_GPU_VIV=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_NWL_MIPI_DSI=y +CONFIG_DRM_I2C_ADV7511=y +CONFIG_DRM_MXSFB=y +CONFIG_IMX8MM_LCDIF_CORE=y +CONFIG_IMX_LCDIFV3_CORE=y +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_PANEL_RAYDIUM_RM68200=y +CONFIG_DRM_PANEL_ROCKTECK_HIMAX8394F=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_PANEL_WKS_101WX001=y +CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y +CONFIG_DRM_SEC_MIPI_DSIM=y +CONFIG_DRM_NXP_SEIKO_43WVFIG=y +CONFIG_DRM_CDNS_MHDP=y +CONFIG_DRM_CDNS_HDMI=y +CONFIG_DRM_CDNS_DP=y +CONFIG_DRM_CDNS_AUDIO=y +CONFIG_DRM_CDNS_HDCP=y +CONFIG_DRM_CDNS_HDMI_CEC=y +CONFIG_DRM_DW_HDMI=y +CONFIG_DRM_DW_HDMI_GP_AUDIO=y +CONFIG_DRM_ITE_IT6263=y +CONFIG_DRM_ITE_IT6161=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX8MM_LCDIF=y +CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX8QM_LDB=y +CONFIG_DRM_IMX8QXP_LDB=y +CONFIG_DRM_IMX8MP_LDB=y +CONFIG_DRM_IMX93_LDB=y +CONFIG_DRM_IMX93_PARALLEL_DISPLAY_FORMAT=y +CONFIG_DRM_IMX_DW_MIPI_DSI=y +CONFIG_IMX8MP_HDMI_PAVI=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_DCNANO=y +CONFIG_DRM_IMX_DPU=y +CONFIG_DRM_IMX_DCSS=y +CONFIG_DRM_IMX_CDNS_MHDP=y +CONFIG_DRM_IMX_LCDIFV3=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_SND_SOC_FSL_EASRC=y +CONFIG_SND_SOC_FSL_ASOC_CARD=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_AUDIO_GRAPH_CARD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_PCI_WRAP=y +CONFIG_USB_CDNS3_IMX=y +CONFIG_USB_CDNS_SUPPORT=y +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_IMX_SC=y +CONFIG_PWM_IMX27=y +CONFIG_PWM_ADP5585=y +CONFIG_PHY_FSL_IMX93_MIPI_DPHY=y +CONFIG_PHY_MIXEL_MIPI_DPHY=y +CONFIG_FSL_IMX8_DDR_PMU=y +CONFIG_SND_SOC_WM8524=y +CONFIG_IIO_ST_LSM6DSX=y +CONFIG_MHDP_HDMIRX=y +CONFIG_MHDP_HDMIRX_CEC=y +CONFIG_VIDEO_AP1302=y +CONFIG_DWC_MIPI_CSI2_HOST=y +CONFIG_KEYBOARD_BBNSM_PWRKEY=y +CONFIG_RTC_DRV_BBNSM=y +CONFIG_FSL_IMX9_DDR_PMU=y +CONFIG_VIDEO_AMPHION_VPU=y +CONFIG_ETHOSU=y +CONFIG_VIDEO_MT9M114=y + +# add support for docker and VM +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_TABLES=y +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m + +# misc +CONFIG_MODVERSIONS=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/configs/imx_v8_defconfig linux-imx-phytec/arch/arm64/configs/imx_v8_defconfig --- linux-6.1.55/arch/arm64/configs/imx_v8_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/configs/imx_v8_defconfig 2024-06-19 12:33:58.400194276 +0200 @@ -0,0 +1,1133 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PROFILING=y +CONFIG_ARCH_KEEMBAY=y +CONFIG_ARCH_NXP=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_S32=y +CONFIG_SOC_S32V234=y +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_NUMA=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_CRASH_DUMP=y +CONFIG_XEN=y +CONFIG_ARCH_FORCE_MAX_ORDER=14 +CONFIG_COMPAT=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_ENERGY_MODEL=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ARM_IMX_CPUFREQ_DT=y +CONFIG_ARM_SCMI_CPUFREQ=y +CONFIG_QORIQ_CPUFREQ=y +CONFIG_ACPI=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_KSM=y +CONFIG_MEMORY_FAILURE=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_TLS=y +CONFIG_TLS_DEVICE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6_SIT=m +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_TABLES=y +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_CT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_IP_VS=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_MANGLE=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_GACT=m +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_GATE=m +CONFIG_TSN=y +CONFIG_QRTR=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_NET_PKTGEN=m +CONFIG_CAN=m +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_LEDS=y +# CONFIG_BT_DEBUGFS is not set +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIVHCI=y +CONFIG_BT_NXPUART=m +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +CONFIG_NFC=m +CONFIG_NFC_NCI=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PASID=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_XGENE=y +CONFIG_PCIE_ALTERA=y +CONFIG_PCIE_ALTERA_MSI=y +CONFIG_PCI_HOST_THUNDER_PEM=y +CONFIG_PCI_HOST_THUNDER_ECAM=y +CONFIG_PCI_IMX6_HOST=y +CONFIG_PCI_IMX6_EP=y +CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_HISI=y +CONFIG_PCIE_KIRIN=y +CONFIG_PCI_MESON=m +CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_FSL_MC_UAPI_SUPPORT=y +CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_IMX_DSP=y +CONFIG_IMX_EL_ENCLAVE=y +CONFIG_IMX_SCU=y +CONFIG_IMX_SCU_PD=y +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=m +CONFIG_XEN_BLKDEV_BACKEND=m +CONFIG_VIRTIO_BLK=y +CONFIG_BLK_DEV_NVME=y +CONFIG_SRAM=y +CONFIG_PCI_ENDPOINT_TEST=y +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_UACCE=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_HISI_SAS=y +CONFIG_SCSI_HISI_SAS_PCI=y +CONFIG_MEGARAID_SAS=y +CONFIG_SCSI_MPT3SAS=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_AHCI_CEVA=y +CONFIG_AHCI_XGENE=y +CONFIG_AHCI_QORIQ=y +CONFIG_SATA_SIL24=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_TUN=y +CONFIG_VETH=m +CONFIG_VIRTIO_NET=y +CONFIG_NET_DSA_MSCC_FELIX=m +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +CONFIG_NET_DSA_SJA1105_TAS=y +CONFIG_NET_DSA_SJA1105_VL=y +CONFIG_AMD_XGBE=y +CONFIG_ATL1C=m +CONFIG_BCMGENET=m +CONFIG_BNX2X=m +CONFIG_SYSTEMPORT=m +CONFIG_MACB=y +CONFIG_THUNDER_NIC_PF=y +CONFIG_FEC=y +CONFIG_FEC_UIO=y +CONFIG_FSL_FMAN=y +CONFIG_FSL_DPAA_ETH=y +CONFIG_FSL_DPAA2_ETH=y +CONFIG_FSL_DPAA2_MAC=y +CONFIG_FSL_DPAA2_SWITCH=y +CONFIG_FSL_ENETC=y +CONFIG_FSL_ENETC_VF=y +CONFIG_FSL_ENETC_QOS=y +CONFIG_ENETC_TSN=y +CONFIG_HIX5HD2_GMAC=y +CONFIG_HNS_DSAF=y +CONFIG_HNS_ENET=y +CONFIG_HNS3=y +CONFIG_HNS3_HCLGE=y +CONFIG_HNS3_ENET=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_IGB=y +CONFIG_IGBVF=y +CONFIG_MVMDIO=y +CONFIG_SKY2=y +CONFIG_MLX4_EN=m +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MSCC_OCELOT_SWITCH=y +CONFIG_QCOM_EMAC=m +CONFIG_RMNET=m +CONFIG_SMC91X=y +CONFIG_SMSC911X=y +CONFIG_STMMAC_ETH=y +CONFIG_DWMAC_GENERIC=m +CONFIG_AQUANTIA_PHY=y +CONFIG_BROADCOM_PHY=m +CONFIG_BCM54140_PHY=m +CONFIG_INPHI_PHY=y +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_MICREL_PHY=y +CONFIG_MICROSEMI_PHY=y +CONFIG_NXP_C45_TJA11XX_PHY=y +CONFIG_NXP_TJA11XX_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_ROCKCHIP_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_CAN_FLEXCAN=m +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_ZAURUS=m +CONFIG_HOSTAP=y +CONFIG_WL18XX=m +CONFIG_WLCORE_SDIO=m +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_IVSHMEM_NET=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADC=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_RPMSG=y +CONFIG_KEYBOARD_SNVS_PWRKEY=y +CONFIG_KEYBOARD_BBNSM_PWRKEY=y +CONFIG_KEYBOARD_IMX_SC_KEY=y +CONFIG_KEYBOARD_CROS_EC=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_AMBAKMI=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_I2C_INFINEON=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_GPIO=m +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_I2C_IMX_FLEXIO=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_RPBUS=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_I2C_SLAVE_EEPROM=y +CONFIG_I3C=y +CONFIG_SVC_I3C_MASTER=y +CONFIG_SPI=y +CONFIG_SPI_CADENCE_QUADSPI=y +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_NXP_FLEXSPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_FSL_DSPI=y +CONFIG_SPI_PL022=y +CONFIG_SPI_ROCKCHIP=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y +CONFIG_SPMI=y +CONFIG_PPS_CLIENT_GPIO=y +CONFIG_PINCTRL_MAX77620=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_IMX8MM=y +CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y +CONFIG_PINCTRL_IMX8MQ=y +CONFIG_PINCTRL_IMX8QM=y +CONFIG_PINCTRL_IMX8QXP=y +CONFIG_PINCTRL_IMX8DXL=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_PINCTRL_IMX93=y +CONFIG_PINCTRL_S32V234=y +CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_IMX_RPMSG=y +CONFIG_GPIO_MB86S7X=y +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_PL061=y +CONFIG_GPIO_WCD934X=m +CONFIG_GPIO_XGENE=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_ADP5585=y +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_MAX77620=y +CONFIG_GPIO_SL28CPLD=m +CONFIG_POWER_RESET_BRCMSTB=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_SBS=m +CONFIG_BATTERY_BQ27XXX=y +CONFIG_BATTERY_MAX17042=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_SENSORS_ARM_SCMI=y +CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_FP9931=y +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SL28CPLD=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA3221=m +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_IMX_SC_THERMAL=y +CONFIG_IMX8MM_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_QORIQ_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_SL28CPLD_WATCHDOG=m +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_ARM_SBSA_WATCHDOG=y +CONFIG_DW_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_IMX_SC_WDT=y +CONFIG_IMX7ULP_WDT=y +CONFIG_ARM_SMC_WATCHDOG=y +CONFIG_XEN_WDT=y +CONFIG_MFD_ADP5585=y +CONFIG_MFD_BD9571MWV=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_IMX_FLEXIO=y +CONFIG_MFD_HI6421_PMIC=y +CONFIG_MFD_FP9931=y +CONFIG_MFD_MAX77620=y +CONFIG_MFD_MAXIM_SERDES=y +CONFIG_MFD_MAX96752=y +CONFIG_MFD_MAX96752_I2C=y +CONFIG_MFD_MAX96789=y +CONFIG_MFD_MAX96789_I2C=y +CONFIG_MFD_MT6397=y +CONFIG_MFD_RK808=y +CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_SL28CPLD=y +CONFIG_MFD_ROHM_BD718XX=y +CONFIG_MFD_WCD934X=m +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_BD718XX=y +CONFIG_REGULATOR_BD9571MWV=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_HI6421V530=y +CONFIG_REGULATOR_MAX77620=y +CONFIG_REGULATOR_MAX8973=y +CONFIG_REGULATOR_FP9931=y +CONFIG_REGULATOR_MP8859=y +CONFIG_REGULATOR_MT6358=y +CONFIG_REGULATOR_MT6397=y +CONFIG_REGULATOR_PCA9450=y +CONFIG_REGULATOR_PF8X00=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_RK808=y +CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_VCTRL=m +CONFIG_RC_CORE=m +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +# CONFIG_DVB_NET is not set +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MX8_CAPTURE=y +CONFIG_VIDEO_MXC_CAPTURE=y +CONFIG_VIDEO_MXC_CSI_CAMERA=y +CONFIG_MXC_MIPI_CSI=y +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y +CONFIG_VIDEO_AMPHION_VPU=y +CONFIG_VIDEO_IMX8_JPEG=m +CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_OV5640=y +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_AP1302=y +CONFIG_VIDEO_MT9M114=y +CONFIG_IMX_DPU_CORE=y +CONFIG_IMX8MM_LCDIF_CORE=y +CONFIG_IMX_LCDIFV3_CORE=y +CONFIG_DRM=y +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_MALI_DISPLAY=m +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_RCAR_DW_HDMI=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_PANEL_RAYDIUM_RM68200=y +CONFIG_DRM_PANEL_ROCKTECK_HIMAX8394F=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_PANEL_WKS_101WX001=y +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y +CONFIG_DRM_MAX96752_LVDS=y +CONFIG_DRM_MAX96789_DSI=y +CONFIG_DRM_NWL_MIPI_DSI=y +CONFIG_DRM_NXP_SEIKO_43WVFIG=y +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_I2C_ADV7511=y +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +CONFIG_DRM_DW_HDMI_GP_AUDIO=y +CONFIG_DRM_DW_HDMI_CEC=m +CONFIG_DRM_ITE_IT6263=y +CONFIG_DRM_ITE_IT6161=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX8QM_LDB=y +CONFIG_DRM_IMX8QXP_LDB=y +CONFIG_DRM_IMX8MP_LDB=y +CONFIG_DRM_IMX93_LDB=y +CONFIG_DRM_IMX_DW_MIPI_DSI=y +CONFIG_DRM_IMX93_PARALLEL_DISPLAY_FORMAT=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_DCNANO=y +CONFIG_DRM_IMX_DCSS=y +CONFIG_DRM_IMX_CDNS_MHDP=y +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_HISI_HIBMC=m +CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_MXSFB=y +CONFIG_DRM_PL111=m +CONFIG_DRM_LIMA=m +CONFIG_DRM_PANFROST=m +CONFIG_FB=y +CONFIG_FB_ARMCLCD=y +CONFIG_FB_EFI=y +CONFIG_FB_MXC_EINK_V2_PANEL=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_LP855X=m +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_ALOOP=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_MQS=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_ESAI_CLIENT=y +CONFIG_SND_SOC_FSL_RPMSG=m +CONFIG_SND_IMX_SOC=m +CONFIG_SND_SOC_IMX_SGTL5000=m +CONFIG_SND_SOC_IMX_SPDIF=m +CONFIG_SND_SOC_FSL_ASOC_CARD=m +CONFIG_SND_SOC_IMX_AUDMIX=m +CONFIG_SND_SOC_IMX_HDMI=m +CONFIG_SND_SOC_IMX_CARD=m +CONFIG_SND_SOC_IMX_PCM512X=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y +CONFIG_SND_SOC_SOF_IMX8=m +CONFIG_SND_SOC_SOF_IMX8M=m +CONFIG_SND_SOC_SOF_IMX8ULP=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_BT_SCO=y +CONFIG_SND_SOC_CROS_EC_CODEC=m +CONFIG_SND_SOC_CS42XX8_I2C=y +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_MAX98927=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m +CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_WM8524=y +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_RPMSG_WM8960=m +CONFIG_SND_SOC_RPMSG_AK4497=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_AUDIO_GRAPH_CARD=y +CONFIG_HID_MULTITOUCH=m +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_OF=m +CONFIG_USB_CONN_GPIO=y +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_UAS=y +CONFIG_USB_CDNS_SUPPORT=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC2=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_ISP1760=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=y +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_HSIC_USB3503=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_SNP_UDC_PLAT=y +CONFIG_USB_BDC_UDC=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_SWITCH_GPIO=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ACPI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_F_SDH30=y +CONFIG_MMC_SPI=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_MMC_DW_HI3798CV200=y +CONFIG_MMC_DW_K3=y +CONFIG_MMC_MTK=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA995X=m +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_EDAC=y +CONFIG_EDAC_GHES=y +CONFIG_EDAC_LAYERSCAPE=m +CONFIG_EDAC_SYNOPSYS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_HYM8563=m +CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_S5M=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF2131=m +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_CROS_EC=y +CONFIG_RTC_DRV_FSL_FTM_ALARM=m +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_BBNSM=y +CONFIG_RTC_DRV_IMX_SC=y +CONFIG_RTC_DRV_IMX_RPMSG=y +CONFIG_DMADEVICES=y +CONFIG_BCM_SBA_RAID=m +CONFIG_FSL_EDMA=y +CONFIG_FSL_QDMA=m +CONFIG_FSL_EDMA_V3=y +CONFIG_IMX_SDMA=y +CONFIG_MV_XOR_V2=y +CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V3=y +CONFIG_PL330_DMA=y +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +CONFIG_DW_EDMA=y +CONFIG_DW_EDMA_PCIE=y +CONFIG_FSL_DPAA2_QDMA=m +CONFIG_DMATEST=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_DMABUF_HEAPS_DSP=y +CONFIG_UIO_PCI_GENERIC=y +CONFIG_UIO_IVSHMEM=y +CONFIG_VFIO=y +CONFIG_VFIO_PCI=y +CONFIG_VFIO_FSL_MC=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_IVSHMEM=y +CONFIG_XEN_GNTDEV=y +CONFIG_XEN_GRANT_DEV_ALLOC=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_IMX_CAPTURE=y +CONFIG_IMX8_MEDIA_DEVICE=m +CONFIG_MHDP_HDMIRX=y +CONFIG_MHDP_HDMIRX_CEC=y +CONFIG_FSL_DPAA2=y +CONFIG_FSL_PPFE=y +CONFIG_FSL_PPFE_UTIL_DISABLED=y +CONFIG_ETHOSU=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_I2C=y +CONFIG_CROS_EC_SPI=y +CONFIG_CROS_EC_CHARDEV=m +CONFIG_CLK_VEXPRESS_OSC=y +CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_SCMI=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_COMMON_CLK_FSL_SAI=y +CONFIG_COMMON_CLK_S2MPS11=y +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_VC5=y +CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y +CONFIG_CLK_IMX8QXP=y +CONFIG_CLK_IMX8ULP=y +CONFIG_CLK_IMX93=y +CONFIG_HWSPINLOCK=y +CONFIG_ARM_MHU=y +CONFIG_IMX_MBOX=y +CONFIG_PLATFORM_MHU=y +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_REMOTEPROC=y +CONFIG_IMX_REMOTEPROC=y +CONFIG_IMX_DSP_REMOTEPROC=m +CONFIG_SAMPLES=y +CONFIG_SAMPLE_RPMSG_CLIENT=m +CONFIG_RPMSG_TTY=m +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_QCOM=m +CONFIG_SOC_BRCMSTB=y +CONFIG_FSL_DPAA=y +CONFIG_FSL_MC_DPIO=y +CONFIG_FSL_RCPM=y +CONFIG_FSL_QIXIS=y +CONFIG_SOC_TI=y +CONFIG_EXTCON_PTN5150=m +CONFIG_EXTCON_USB_GPIO=y +CONFIG_EXTCON_USBC_CROS_EC=y +CONFIG_IIO=y +CONFIG_FXLS8962AF_I2C=m +CONFIG_VCNL4035=m +CONFIG_IMX8QXP_ADC=y +CONFIG_IMX93_ADC=y +CONFIG_MAX9611=m +CONFIG_QCOM_SPMI_VADC=m +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_IIO_CROS_EC_SENSORS_CORE=m +CONFIG_IIO_CROS_EC_SENSORS=m +CONFIG_FXAS21002C=y +CONFIG_FXOS8700_I2C=y +CONFIG_RPMSG_IIO_PEDOMETER=m +CONFIG_IIO_ST_LSM6DSX=y +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m +CONFIG_IIO_ST_GYRO_I2C_3AXIS=m +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_IIO_CROS_EC_LIGHT_PROX=m +CONFIG_SENSORS_ISL29018=y +CONFIG_VCNL4000=m +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_CROS_EC_BARO=m +CONFIG_MPL3115=y +CONFIG_MS5611=m +CONFIG_MS5611_I2C=m +CONFIG_INV_MPU6050_IIO=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_PWM=y +CONFIG_PWM_ADP5585=y +CONFIG_PWM_CROS_EC=m +CONFIG_PWM_FSL_FTM=m +CONFIG_PWM_IMX27=y +CONFIG_PWM_RPCHIP=y +CONFIG_PWM_SL28CPLD=m +CONFIG_SL28CPLD_INTC=y +CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8ULP_SIM=y +CONFIG_PHY_XGENE=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y +CONFIG_PHY_CADENCE_SALVO=y +CONFIG_PHY_FSL_IMX8MP_LVDS=y +CONFIG_PHY_FSL_IMX93_MIPI_DPHY=y +CONFIG_PHY_MIXEL_MIPI_DPHY=y +CONFIG_PHY_FSL_IMX8M_PCIE=y +CONFIG_PHY_FSL_IMX8Q_PCIE=y +CONFIG_PHY_SAMSUNG_HDMI_PHY=y +CONFIG_PHY_QCOM_USB_HS=y +CONFIG_PHY_SAMSUNG_USB2=y +CONFIG_ARM_CCI_PMU=m +CONFIG_ARM_CCN=m +CONFIG_ARM_CMN=m +CONFIG_ARM_SMMU_V3_PMU=m +CONFIG_ARM_DSU_PMU=m +CONFIG_FSL_IMX8_DDR_PMU=y +CONFIG_FSL_IMX9_DDR_PMU=y +CONFIG_ARM_SPE_PMU=m +CONFIG_ARM_DMC620_PMU=m +CONFIG_HISI_PMU=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_IMX_OCOTP_SCU=y +CONFIG_NVMEM_RMEM=m +CONFIG_FPGA=y +CONFIG_FPGA_BRIDGE=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_FPGA_REGION=m +CONFIG_OF_FPGA_REGION=m +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_MUX_MMIO=y +CONFIG_SLIM_QCOM_CTRL=m +CONFIG_MXC_SIM=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_EMVSIM=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_EFIVAR_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_9P_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_TRUSTED_KEYS=m +# CONFIG_TRUSTED_KEYS_TPM is not set +# CONFIG_TRUSTED_KEYS_TEE is not set +CONFIG_SECURITY=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARIA=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_TLS=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +CONFIG_CRYPTO_POLYVAL_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m +CONFIG_CRYPTO_DEV_FSL_CAAM=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m +CONFIG_CRYPTO_DEV_CCREE=m +CONFIG_CRYPTO_DEV_HISI_SEC2=m +CONFIG_CRYPTO_DEV_HISI_ZIP=m +CONFIG_CRYPTO_DEV_HISI_HPRE=m +CONFIG_CRYPTO_DEV_HISI_TRNG=m +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m +CONFIG_INDIRECT_PIO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC8=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +CONFIG_DEBUG_INFO_REDUCED=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_CATU=m +CONFIG_CORESIGHT_SINK_TPIU=m +CONFIG_CORESIGHT_SINK_ETBV10=m +CONFIG_CORESIGHT_SOURCE_ETM4X=y +CONFIG_CORESIGHT_STM=m +CONFIG_CORESIGHT_CPU_DEBUG=m +CONFIG_CORESIGHT_CTI=m +CONFIG_MEMTEST=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/configs/lsdk.config linux-imx-phytec/arch/arm64/configs/lsdk.config --- linux-6.1.55/arch/arm64/configs/lsdk.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/configs/lsdk.config 2024-06-19 12:33:58.400194276 +0200 @@ -0,0 +1,198 @@ +#uio +CONFIG_UIO=y +CONFIG_UIO_CIF=y +CONFIG_UIO_PDRV_GENIRQ=y +CONFIG_UIO_DMEM_GENIRQ=y +CONFIG_UIO_AEC=y +CONFIG_UIO_SERCOS3=y +CONFIG_UIO_PCI_GENERIC=y +CONFIG_UIO_NETX=y +CONFIG_UIO_MF624=y +# general options +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SLAB=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODVERSIONS=y +CONFIG_BLK_DEV_RAM=y +CONFIG_PID_IN_CONTEXTIDR=y +CONFIG_EXPERT=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_PROC_KCORE=y +# virtualization +CONFIG_VHOST_NET=y +CONFIG_KVM_ARM_MAX_VCPUS=8 + +# DPAA1 networking +# disable the DPAA1 upstream driver +CONFIG_FSL_DPAA=n +CONFIG_FSL_FMAN=n +CONFIG_FSL_DPAA_ETH=n +# enable the DPAA1 SDK driver +CONFIG_FSL_SDK_DPA=y +CONFIG_FSL_SDK_FMAN=y +CONFIG_FSL_SDK_DPAA_ETH=y + +# network and misc +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MSCC_FELIX=y +CONFIG_INET_ESP=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_CRYPTO_USER=y +CONFIG_DM_CRYPT=m +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_CFQ_GROUP_IOSCHED=y +CONFIG_TMPFS_XATTR=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y +CONFIG_NETFILTER_NETLINK=y +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_NAT=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_NF_TABLES=y +CONFIG_NFT_CT=y +CONFIG_NFT_RBTREE=y +CONFIG_NFT_MASQ=y +CONFIG_NFT_NAT=y +CONFIG_NFT_COMPAT=y +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_NAT_IPV4=y +CONFIG_NF_NAT_MASQUERADE_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_MANGLE=y +CONFIG_NF_TABLES_BRIDGE=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_T_NAT=y +CONFIG_BRIDGE_EBT_DNAT=y +CONFIG_BRIDGE_EBT_SNAT=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_SFP=y +CONFIG_PHY_FSL_LYNX_28G=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_XDP_SOCKETS=y + +# GPU +CONFIG_DRM=y +CONFIG_MXC_GPU_VIV=y + +# disable unneeded options and override default options set by defconfig to deduce the size of modules +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_BT is not set +# CONFIG_DRM_TEGRA is not set +# CONFIG_DRM_EXYNOS is not set +# CONFIG_DRM_MSM is not set +# CONFIG_DRM_VC4 is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_MESON is not set +# CONFIG_DRM_ROCKCHIP is not set +# CONFIG_DRM_RCAR_DU is not set +# CONFIG_USB_RENESAS_USBHS is not set +# CONFIG_QCOM_EMAC is not set +# CONFIG_SND_SOC_ROCKCHIP is not set + +CONFIG_IPV6=y +CONFIG_NF_NAT_IPV6=y +CONFIG_NF_NAT_MASQUERADE_IPV6=y +CONFIG_NF_REJECT_IPV6=y +CONFIG_IPV6_SIT=y +CONFIG_NF_LOG_IPV6=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_VLAN_8021Q=y +CONFIG_BRIDGE=y +CONFIG_MACVLAN=y +CONFIG_MACVTAP=y +CONFIG_BTRFS_FS=y +CONFIG_FUSE_FS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_TLS=y +CONFIG_TLS_DEVICE=y + +# lxc +CONFIG_UNIX_DIAG=y +CONFIG_PACKET_DIAG=y +CONFIG_NETLINK_DIAG=y +CONFIG_CGROUP_FREEZER=y + +# sound +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y + +# docker +CONFIG_OVERLAY_FS=y +CONFIG_BPF_SYSCALL=y +CONFIG_CGROUP_BPF=y +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_COUNTER=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NF_TABLES_IPV6=y + +# enable iommu passthrough by default for performance +CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y + +# disable the "disable_bypass" temporarily to workaround the MC issue with it +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=n + +# decrease the default number of CPUs to the maximum available on NXP +# platforms to increase performance +CONFIG_NR_CPUS=16 + +#Qos +CONFIG_NETFILTER_INGRESS=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_MQPRIO=y +CONFIG_NET_SCH_TAPRIO=y +CONFIG_NET_SCH_TBF=y +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=y +CONFIG_NET_CLS_TCINDEX=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_CLS_FLOWER=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_PEDIT=y +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_NET_ACT_VLAN=y +CONFIG_NET_ACT_SKBMOD=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_RTL8152=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_AX88179_178A=y +# CONFIG_NET_PKTGEN is not set + +#build-in drivers +CONFIG_FSL_DPAA2_SWITCH=y +CONFIG_QORIQ_THERMAL=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/configs/non-upstream-drivers.config linux-imx-phytec/arch/arm64/configs/non-upstream-drivers.config --- linux-6.1.55/arch/arm64/configs/non-upstream-drivers.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/configs/non-upstream-drivers.config 2024-06-19 12:33:58.400194276 +0200 @@ -0,0 +1,90 @@ +# Common drivers +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m + +# S32 support +CONFIG_SOC_S32V234=y +CONFIG_PINCTRL_S32V234=y + +# Layerscape support +CONFIG_ENETC_TSN=y +CONFIG_INPHI_PHY=y +CONFIG_FSL_DPAA2_MAC=y +CONFIG_FSL_PPFE=y +CONFIG_FSL_PPFE_UTIL_DISABLED=y +CONFIG_FSL_QIXIS=y + +# i.MX support +CONFIG_PCI_IMX6_HOST=y +CONFIG_PCI_IMX6_EP=y +CONFIG_IVSHMEM_NET=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m +CONFIG_I2C_RPBUS=y +CONFIG_GPIO_IMX_RPMSG=y +CONFIG_SENSORS_FP9931=y +CONFIG_DEVICE_THERMAL=y +CONFIG_MFD_FP9931=y +CONFIG_MFD_IMX_MIX=y +CONFIG_REGULATOR_FP9931=y +CONFIG_VIDEO_MX8_CAPTURE=y +CONFIG_VIDEO_MXC_CAPTURE=y +CONFIG_VIDEO_MXC_CSI_CAMERA=y +CONFIG_MXC_MIPI_CSI=y +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y +CONFIG_IMX_DPU_CORE=y +CONFIG_IMX_LCDIF_CORE=y +CONFIG_IMX_LCDIFV3_CORE=y +CONFIG_DRM_PANEL_ROCKTECK_HIMAX8394F=y +CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y +CONFIG_DRM_PANEL_WKS_101WX001=y +CONFIG_DRM_NXP_SEIKO_43WVFIG=y +CONFIG_DRM_DW_HDMI_GP_AUDIO=y +CONFIG_DRM_CDNS_HDMI_CEC=y +CONFIG_DRM_ITE_IT6263=y +CONFIG_DRM_ITE_IT6161=y +CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y +CONFIG_DRM_IMX8QM_LDB=y +CONFIG_DRM_IMX8QXP_LDB=y +CONFIG_DRM_IMX8MP_LDB=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_CDNS_MHDP=y +CONFIG_DRM_IMX_DCNANO=y +CONFIG_FB_MXC_EINK_V2_PANEL=y +CONFIG_SND_SOC_FSL_ESAI_CLIENT=y +CONFIG_SND_SOC_FSL_DAI=m +CONFIG_SND_SOC_IMX_AK4458=y +CONFIG_SND_SOC_IMX_AK5558=y +CONFIG_SND_SOC_IMX_AK4497=y +CONFIG_SND_SOC_IMX_MICFIL=y +CONFIG_SND_SOC_IMX_PDM_MIC=y +CONFIG_SND_SOC_IMX_DSP=m +CONFIG_SND_SOC_IMX_XCVR=y +CONFIG_SND_SOC_IMX_PCM512X=y +CONFIG_SND_SOC_SOF_IMX8ULP_SUPPORT=y +CONFIG_SND_SOC_SOF_IMX8ULP=y +CONFIG_SND_SOC_RPMSG_WM8960=m +CONFIG_SND_SOC_RPMSG_AK4497=m +CONFIG_TYPEC_SWITCH_GPIO=y +CONFIG_FSL_EDMA_V3=y +CONFIG_VIDEO_IMX_CAPTURE=y +CONFIG_ION_SYSTEM_HEAP=y +CONFIG_ION_CMA_HEAP=y +CONFIG_CLK_IMX8ULP=y +CONFIG_PWM_RPCHIP=y +CONFIG_RESET_IMX8ULP_SIM=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y +CONFIG_PHY_FSL_IMX8MP_LVDS=y +CONFIG_PHY_SAMSUNG_HDMI_PHY=y +CONFIG_MXC_SIM=y +CONFIG_MXC_EMVSIM=y +CONFIG_IMX8_MEDIA_DEVICE=m +CONFIG_IMX8_ISI_HW=y +CONFIG_IMX8_ISI_CORE=y +CONFIG_IMX8_ISI_CAPTURE=y +CONFIG_IMX8_ISI_M2M=y +CONFIG_IMX8_MIPI_CSI2=y +CONFIG_IMX8_MIPI_CSI2_SAM=y +CONFIG_IMX8_PARALLEL_CSI=y +CONFIG_GMSL_MAX9286=y +CONFIG_MXC_PXP_V3=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/configs/upstream-drivers.config linux-imx-phytec/arch/arm64/configs/upstream-drivers.config --- linux-6.1.55/arch/arm64/configs/upstream-drivers.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/arm64/configs/upstream-drivers.config 2024-06-19 12:33:58.400194276 +0200 @@ -0,0 +1,136 @@ +# To be submitted upstream +CONFIG_FSL_DPAA2=y +CONFIG_FSL_MC_UAPI_SUPPORT=y +CONFIG_VFIO_FSL_MC=y +CONFIG_MSCC_OCELOT_SWITCH=y +CONFIG_FSL_DPAA2_SWITCH=y +CONFIG_FSL_ENETC_MDIO=y +CONFIG_FSL_QDMA=m +CONFIG_FSL_DPAA2_QDMA=m +CONFIG_DMATEST=y +CONFIG_PWM_FSL_FTM=m +CONFIG_NXP_TJA11XX_PHY=y + +CONFIG_IMX_DSP=y +CONFIG_AHCI_IMX=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_IMX7ULP_WDT=y + +# updates to CONFIGs in upstream +CONFIG_RELAY=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_LLC2=y +CONFIG_TSN=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_PKTGEN=m +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIVHCI=y +CONFIG_BT_LE=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_UBI=y +CONFIG_XEN_BLKDEV_BACKEND=m +CONFIG_BRCMFMAC_PCIE=y +CONFIG_HOSTAP=y +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_I3C=y +CONFIG_SVC_I3C_MASTER=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y +CONFIG_GPIO_SYSFS=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_GPIO_CIR=m +CONFIG_VIDEO_IMX8_JPEG=m +CONFIG_VIDEO_OV5640=y +CONFIG_DRM_PANEL_RAYDIUM_RM68200=y +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_DCSS=y +CONFIG_FB_ARMCLCD=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC_FSL_MQS=y +CONFIG_SND_SOC_FSL_RPMSG=m +CONFIG_SND_SOC_FSL_ASOC_CARD=y +CONFIG_SND_SOC_IMX_RPMSG=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y +CONFIG_SND_SOC_SOF_IMX8_SUPPORT=y +CONFIG_SND_SOC_SOF_IMX8M_SUPPORT=y +CONFIG_SND_SOC_CS42XX8=y +CONFIG_SND_SOC_CS42XX8_I2C=y +CONFIG_SND_SOC_BT_SCO=y +CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_WM8524=y +CONFIG_USB_UAS=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_IMX=y +CONFIG_USB_CDNS_SUPPORT=y +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_MXS_PHY=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_EDAC_SYNOPSYS=y +CONFIG_MXS_DMA=y +CONFIG_UIO=y +CONFIG_UIO_PCI_GENERIC=y +CONFIG_ION=y +CONFIG_IMX8QXP_ADC=y +CONFIG_IIO_ST_LSM6DSX=y +CONFIG_PHY_CADENCE_SALVO=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_SOURCE_ETM4X=y + +# CONFIGs disabled +CONFIG_DRM_TEGRA=n +CONFIG_PCI_IMX6=n + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/include/asm/barrier.h linux-imx-phytec/arch/arm64/include/asm/barrier.h --- linux-6.1.55/arch/arm64/include/asm/barrier.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/include/asm/barrier.h 2024-06-19 12:33:58.408194413 +0200 @@ -54,9 +54,9 @@ #define __rmb() dsb(ld) #define __wmb() dsb(st) -#define __dma_mb() dmb(osh) -#define __dma_rmb() dmb(oshld) -#define __dma_wmb() dmb(oshst) +#define __dma_mb() dmb(sy) +#define __dma_rmb() dmb(ld) +#define __dma_wmb() dmb(st) #define io_stop_wc() dgh() diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/include/asm/io.h linux-imx-phytec/arch/arm64/include/asm/io.h --- linux-6.1.55/arch/arm64/include/asm/io.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/include/asm/io.h 2024-06-19 12:33:58.408194413 +0200 @@ -148,6 +148,8 @@ ioremap_prot((addr), (size), PROT_NORMAL_NC) #define ioremap_np(addr, size) \ ioremap_prot((addr), (size), PROT_DEVICE_nGnRnE) +#define ioremap_cache_ns(addr, size) \ + ioremap_prot((addr), (size), PROT_NORMAL_NS) /* * io{read,write}{16,32,64}be() macros diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/include/asm/kvm_pgtable.h linux-imx-phytec/arch/arm64/include/asm/kvm_pgtable.h --- linux-6.1.55/arch/arm64/include/asm/kvm_pgtable.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/include/asm/kvm_pgtable.h 2024-06-19 12:33:58.412194481 +0200 @@ -140,6 +140,8 @@ KVM_PGTABLE_PROT_R = BIT(2), KVM_PGTABLE_PROT_DEVICE = BIT(3), + KVM_PGTABLE_PROT_DEVICE_NS = BIT(4), + KVM_PGTABLE_PROT_DEVICE_SH = BIT(5), KVM_PGTABLE_PROT_SW0 = BIT(55), KVM_PGTABLE_PROT_SW1 = BIT(56), diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/include/asm/pgtable.h linux-imx-phytec/arch/arm64/include/asm/pgtable.h --- linux-6.1.55/arch/arm64/include/asm/pgtable.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/include/asm/pgtable.h 2024-06-19 12:33:58.416194549 +0200 @@ -561,6 +561,11 @@ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) #define pgprot_writecombine(prot) \ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) +#define pgprot_cached(prot) \ + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \ + PTE_PXN | PTE_UXN) +#define pgprot_cached_ns(prot) \ + __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED) #define pgprot_device(prot) \ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) #define pgprot_tagged(prot) \ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/include/asm/pgtable-prot.h linux-imx-phytec/arch/arm64/include/asm/pgtable-prot.h --- linux-6.1.55/arch/arm64/include/asm/pgtable-prot.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/include/asm/pgtable-prot.h 2024-06-19 12:33:58.416194549 +0200 @@ -57,6 +57,7 @@ #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE)) #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC)) #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) +#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) #define PROT_NORMAL_TAGGED (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED)) #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/include/asm/tlbflush.h linux-imx-phytec/arch/arm64/include/asm/tlbflush.h --- linux-6.1.55/arch/arm64/include/asm/tlbflush.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/include/asm/tlbflush.h 2024-06-19 12:33:58.416194549 +0200 @@ -16,6 +16,8 @@ #include #include +extern bool TKT340553_SW_WORKAROUND; + /* * Raw TLBI operations. * @@ -249,9 +251,16 @@ dsb(ishst); asid = __TLBI_VADDR(0, ASID(mm)); - __tlbi(aside1is, asid); - __tlbi_user(aside1is, asid); - dsb(ish); + if (TKT340553_SW_WORKAROUND) { + /* Flush the entire TLB */ + __tlbi(vmalle1is); + dsb(ish); + isb(); + } else { + __tlbi(aside1is, asid); + __tlbi_user(aside1is, asid); + dsb(ish); + } } static inline void flush_tlb_page_nosync(struct vm_area_struct *vma, @@ -261,8 +270,15 @@ dsb(ishst); addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); - __tlbi(vale1is, addr); - __tlbi_user(vale1is, addr); + if (TKT340553_SW_WORKAROUND) { + /* Flush the entire TLB */ + __tlbi(vmalle1is); + dsb(ish); + isb(); + } else { + __tlbi(vale1is, addr); + __tlbi_user(vale1is, addr); + } } static inline void flush_tlb_page(struct vm_area_struct *vma, @@ -307,6 +323,14 @@ dsb(ishst); asid = ASID(vma->vm_mm); + if (TKT340553_SW_WORKAROUND) { + /* Flush the entire TLB and exit */ + __tlbi(vmalle1is); + dsb(ish); + isb(); + return; + } + /* * When the CPU does not support TLB range operations, flush the TLB * entries one by one at the granularity of 'stride'. If the TLB @@ -357,6 +381,7 @@ } scale++; } + dsb(ish); } @@ -375,7 +400,8 @@ { unsigned long addr; - if ((end - start) > (MAX_TLBI_OPS * PAGE_SIZE)) { + if (((end - start) > (MAX_TLBI_OPS * PAGE_SIZE)) + || (TKT340553_SW_WORKAROUND)) { flush_tlb_all(); return; } @@ -399,7 +425,11 @@ unsigned long addr = __TLBI_VADDR(kaddr, 0); dsb(ishst); - __tlbi(vaae1is, addr); + if (TKT340553_SW_WORKAROUND) + /* Flush the entire TLB */ + __tlbi(vmalle1is); + else + __tlbi(vaae1is, addr); dsb(ish); isb(); } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/include/asm/virt.h linux-imx-phytec/arch/arm64/include/asm/virt.h --- linux-6.1.55/arch/arm64/include/asm/virt.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/include/asm/virt.h 2024-06-19 12:33:58.420194618 +0200 @@ -76,6 +76,7 @@ #define ARM64_VECTOR_TABLE_LEN SZ_2K +extern char __hyp_stub_vectors[]; void __hyp_set_vectors(phys_addr_t phys_vector_base); void __hyp_reset_vectors(void); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/Kconfig linux-imx-phytec/arch/arm64/Kconfig --- linux-6.1.55/arch/arm64/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/Kconfig 2024-06-19 12:33:58.244191608 +0200 @@ -1468,7 +1468,7 @@ Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. config ARCH_FORCE_MAX_ORDER - int + int "Maximum zone order" default "14" if ARM64_64K_PAGES default "12" if ARM64_16K_PAGES default "11" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/Kconfig.platforms linux-imx-phytec/arch/arm64/Kconfig.platforms --- linux-6.1.55/arch/arm64/Kconfig.platforms 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/Kconfig.platforms 2024-06-19 12:33:58.248191677 +0200 @@ -208,21 +208,36 @@ bool "ARMv8 based NXP i.MX SoC family" select ARM64_ERRATUM_843419 select ARM64_ERRATUM_845719 if COMPAT + select GPIOLIB select IMX_GPCV2 select IMX_GPCV2_PM_DOMAINS + select HAVE_IMX_BUSFREQ select PM select PM_GENERIC_DOMAINS select SOC_BUS select TIMER_IMX_SYS_CTR + select CLKSRC_IMX_TPM help This enables support for the ARMv8 based SoCs in the NXP i.MX family. +config HAVE_IMX_BUSFREQ + bool "i.MX8 busfreq" + config ARCH_S32 bool "NXP S32 SoC Family" + select ARCH_S32_CLK + select PINCTRL help This enables support for the NXP S32 family of processors. +if ARCH_S32 +menu "S32 SOC selection" + config SOC_S32V234 + bool "S32V234 SOC" +endmenu +endif + endif config ARCH_NPCM diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/kernel/cpufeature.c linux-imx-phytec/arch/arm64/kernel/cpufeature.c --- linux-6.1.55/arch/arm64/kernel/cpufeature.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/kernel/cpufeature.c 2024-06-19 12:33:58.424194686 +0200 @@ -948,9 +948,22 @@ } } +bool TKT340553_SW_WORKAROUND; static void __init init_cpu_hwcaps_indirect_list(void) { init_cpu_hwcaps_indirect_list_from_array(arm64_features); +#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE +#if defined(CONFIG_ARM64_ERRATUM_826319) || \ + defined(CONFIG_ARM64_ERRATUM_827319) || \ + defined(CONFIG_ARM64_ERRATUM_824069) + if (TKT340553_SW_WORKAROUND) { + struct midr_range *midr_range_list = + (struct midr_range *)(arm64_errata[0].midr_range_list); + + midr_range_list[0].rv_max = MIDR_CPU_VAR_REV(0, 4); + } +#endif +#endif init_cpu_hwcaps_indirect_list_from_array(arm64_errata); } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/kernel/hyp-stub.S linux-imx-phytec/arch/arm64/kernel/hyp-stub.S --- linux-6.1.55/arch/arm64/kernel/hyp-stub.S 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/kernel/hyp-stub.S 2024-06-19 12:33:58.424194686 +0200 @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -66,6 +67,7 @@ ventry el1_fiq_invalid // FIQ 32-bit EL1 ventry el1_error_invalid // Error 32-bit EL1 SYM_CODE_END(__hyp_stub_vectors) +EXPORT_SYMBOL_GPL(__hyp_stub_vectors) .align 11 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/kernel/pci.c linux-imx-phytec/arch/arm64/kernel/pci.c --- linux-6.1.55/arch/arm64/kernel/pci.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/kernel/pci.c 2024-06-19 12:33:58.428194755 +0200 @@ -13,11 +13,14 @@ #include #include #include +#include #include #include #include #include +#include "../../../drivers/pci/pcie/portdrv.h" + #ifdef CONFIG_ACPI /* * Try to assign the IRQ number when probing a new device @@ -32,6 +35,47 @@ #endif /* + * Check device tree if the service interrupts are there + */ +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask) +{ + int ret, count = 0; + struct device_node *np = NULL; + + if (dev->bus->dev.of_node) + np = dev->bus->dev.of_node; + + if (np == NULL) + return 0; + + if (!IS_ENABLED(CONFIG_OF_IRQ)) + return 0; + + /* If root port doesn't support MSI/MSI-X/INTx in RC mode, + * request irq for aer + */ + if (mask & PCIE_PORT_SERVICE_AER) { + ret = of_irq_get_byname(np, "aer"); + if (ret > 0) { + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret; + count++; + } + } + + if (mask & PCIE_PORT_SERVICE_PME) { + ret = of_irq_get_byname(np, "pme"); + if (ret > 0) { + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret; + count++; + } + } + + /* TODO: add more service interrupts if there it is in the device tree*/ + + return count; +} + +/* * raw_pci_read/write - Platform-specific PCI config space access. */ int raw_pci_read(unsigned int domain, unsigned int bus, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/kernel/smp.c linux-imx-phytec/arch/arm64/kernel/smp.c --- linux-6.1.55/arch/arm64/kernel/smp.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/kernel/smp.c 2024-06-19 12:33:58.432194823 +0200 @@ -923,10 +923,19 @@ return IRQ_HANDLED; } +#ifdef CONFIG_IMX_GPCV2 +extern void imx_gpcv2_raise_softirq(const struct cpumask *mask, + unsigned int irq); +#endif + static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) { trace_ipi_raise(target, ipi_types[ipinr]); __ipi_send_mask(ipi_desc[ipinr], target); + +#ifdef CONFIG_IMX_GPCV2 + imx_gpcv2_raise_softirq(target, ipinr); +#endif } static void ipi_setup(int cpu) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/kernel/traps.c linux-imx-phytec/arch/arm64/kernel/traps.c --- linux-6.1.55/arch/arm64/kernel/traps.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/kernel/traps.c 2024-06-19 12:33:58.432194823 +0200 @@ -543,6 +543,24 @@ uaccess_ttbr0_disable(); \ } +#define __user_cache_maint_ivau(insn, address, res) \ + do { \ + if (address >= TASK_SIZE_MAX) { \ + res = -EFAULT; \ + } else { \ + uaccess_ttbr0_enable(); \ + asm volatile ( \ + "1: " insn "\n" \ + " mov %w0, #0\n" \ + "2:\n" \ + _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) \ + : "=r" (res) \ + : "r" (address)); \ + uaccess_ttbr0_disable(); \ + } \ + } while (0) + +extern bool TKT340553_SW_WORKAROUND; static void user_cache_maint_handler(unsigned long esr, struct pt_regs *regs) { unsigned long tagged_address, address; @@ -570,7 +588,10 @@ __user_cache_maint("dc civac", address, ret); break; case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ - __user_cache_maint("ic ivau", address, ret); + if (TKT340553_SW_WORKAROUND) + __user_cache_maint_ivau("ic ialluis", address, ret); + else + __user_cache_maint("ic ivau", address, ret); break; default: force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/kvm/hyp/pgtable.c linux-imx-phytec/arch/arm64/kvm/hyp/pgtable.c --- linux-6.1.55/arch/arm64/kvm/hyp/pgtable.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/kvm/hyp/pgtable.c 2024-06-19 12:33:58.440194960 +0200 @@ -46,6 +46,8 @@ KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W | \ KVM_PTE_LEAF_ATTR_HI_S2_XN) +#define KVM_PTE_LEAF_ATTR_S2_DEVICE BIT(55) + #define KVM_INVALID_PTE_OWNER_MASK GENMASK(9, 2) #define KVM_MAX_OWNER_ID 1 @@ -163,6 +165,7 @@ pte |= attr & (KVM_PTE_LEAF_ATTR_LO | KVM_PTE_LEAF_ATTR_HI); pte |= FIELD_PREP(KVM_PTE_TYPE, type); pte |= KVM_PTE_VALID; + pte |= attr & KVM_PTE_LEAF_ATTR_S2_DEVICE; return pte; } @@ -636,7 +639,10 @@ bool device = prot & KVM_PGTABLE_PROT_DEVICE; kvm_pte_t attr = device ? KVM_S2_MEMATTR(pgt, DEVICE_nGnRE) : KVM_S2_MEMATTR(pgt, NORMAL); - u32 sh = KVM_PTE_LEAF_ATTR_LO_S2_SH_IS; + u32 sh = 0; + + if (!(prot & KVM_PGTABLE_PROT_DEVICE_NS)) + sh = KVM_PTE_LEAF_ATTR_LO_S2_SH_IS; if (!(prot & KVM_PGTABLE_PROT_X)) attr |= KVM_PTE_LEAF_ATTR_HI_S2_XN; @@ -652,6 +658,8 @@ attr |= FIELD_PREP(KVM_PTE_LEAF_ATTR_LO_S2_SH, sh); attr |= KVM_PTE_LEAF_ATTR_LO_S2_AF; attr |= prot & KVM_PTE_LEAF_ATTR_HI_SW; + if ((prot & KVM_PGTABLE_PROT_DEVICE_SH) || (prot & KVM_PGTABLE_PROT_DEVICE_NS)) + attr |= KVM_PTE_LEAF_ATTR_S2_DEVICE; *ptep = attr; return 0; @@ -758,7 +766,8 @@ } /* Perform CMOs before installation of the guest stage-2 PTE */ - if (mm_ops->dcache_clean_inval_poc && stage2_pte_cacheable(pgt, new)) + if (mm_ops->dcache_clean_inval_poc && stage2_pte_cacheable(pgt, new) && + !(new & KVM_PTE_LEAF_ATTR_S2_DEVICE)) mm_ops->dcache_clean_inval_poc(kvm_pte_follow(new, mm_ops), granule); @@ -1158,7 +1167,8 @@ struct kvm_pgtable_mm_ops *mm_ops = pgt->mm_ops; kvm_pte_t pte = *ptep; - if (!kvm_pte_valid(pte) || !stage2_pte_cacheable(pgt, pte)) + if (!kvm_pte_valid(pte) || !stage2_pte_cacheable(pgt, pte) || + (pte & KVM_PTE_LEAF_ATTR_S2_DEVICE)) return 0; if (mm_ops->dcache_clean_inval_poc) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/kvm/mmu.c linux-imx-phytec/arch/arm64/kvm/mmu.c --- linux-6.1.55/arch/arm64/kvm/mmu.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/kvm/mmu.c 2024-06-19 12:33:58.440194960 +0200 @@ -1145,6 +1145,23 @@ return 0; } +static enum kvm_pgtable_prot stage1_to_stage2_pgprot(pgprot_t prot) +{ + switch (pgprot_val(prot) & PTE_ATTRINDX_MASK) { + case PTE_ATTRINDX(MT_DEVICE_nGnRE): + case PTE_ATTRINDX(MT_DEVICE_nGnRnE): + return KVM_PGTABLE_PROT_DEVICE; + case PTE_ATTRINDX(MT_NORMAL_NC): + case PTE_ATTRINDX(MT_NORMAL): + case PTE_ATTRINDX(MT_NORMAL_TAGGED): + return (pgprot_val(prot) & PTE_SHARED) + ? KVM_PGTABLE_PROT_DEVICE_SH + : KVM_PGTABLE_PROT_DEVICE_NS; + } + + return KVM_PGTABLE_PROT_DEVICE; +} + static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, struct kvm_memory_slot *memslot, unsigned long hva, unsigned long fault_status) @@ -1339,8 +1356,16 @@ if (exec_fault) prot |= KVM_PGTABLE_PROT_X; - if (device) - prot |= KVM_PGTABLE_PROT_DEVICE; + if (device) { + pte_t *pte; + spinlock_t *ptl; + enum kvm_pgtable_prot prot_us; + + pte = get_locked_pte(current->mm, memslot->userspace_addr, &ptl); + prot_us = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte))); + pte_unmap_unlock(pte, ptl); + prot |= prot_us; + } else if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) prot |= KVM_PGTABLE_PROT_X; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/kvm/vgic/vgic-its.c linux-imx-phytec/arch/arm64/kvm/vgic/vgic-its.c --- linux-6.1.55/arch/arm64/kvm/vgic/vgic-its.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/kvm/vgic/vgic-its.c 2024-06-19 12:33:58.444195028 +0200 @@ -248,7 +248,7 @@ #define GIC_LPI_OFFSET 8192 #define VITS_TYPER_IDBITS 16 -#define VITS_TYPER_DEVBITS 16 +#define VITS_TYPER_DEVBITS 17 #define VITS_DTE_MAX_DEVID_OFFSET (BIT(14) - 1) #define VITS_ITE_MAX_EVENTID_OFFSET (BIT(16) - 1) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/arm64/mm/dma-mapping.c linux-imx-phytec/arch/arm64/mm/dma-mapping.c --- linux-6.1.55/arch/arm64/mm/dma-mapping.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/arm64/mm/dma-mapping.c 2024-06-19 12:33:58.448195096 +0200 @@ -78,3 +78,4 @@ xen_setup_dma_ops(dev); } +EXPORT_SYMBOL(arch_setup_dma_ops); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/b4420qds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/b4420qds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/b4420qds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/b4420qds-sdk.dts 2024-06-19 12:33:58.748200227 +0200 @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "b4420qds.dts" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/b4860qds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/b4860qds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/b4860qds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/b4860qds-sdk.dts 2024-06-19 12:33:58.748200227 +0200 @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "b4860qds.dts" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/b4si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/b4si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/b4si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/b4si-post.dtsi 2024-06-19 12:33:58.748200227 +0200 @@ -50,7 +50,7 @@ &ifc { #address-cells = <2>; #size-cells = <1>; - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; interrupts = <25 2 0 0>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/bsc9131rdb.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/bsc9131rdb.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/bsc9131rdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/bsc9131rdb.dts 2024-06-19 12:33:58.748200227 +0200 @@ -15,7 +15,7 @@ device_type = "memory"; }; - board_ifc: ifc: ifc@ff71e000 { + board_ifc: ifc: memory-controller@ff71e000 { /* NAND Flash on board */ ranges = <0x0 0x0 0x0 0xff800000 0x00004000>; reg = <0x0 0xff71e000 0x0 0x2000>; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi 2024-06-19 12:33:58.748200227 +0200 @@ -35,7 +35,7 @@ &ifc { #address-cells = <2>; #size-cells = <1>; - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; interrupts = <16 2 0 0 20 2 0 0>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/bsc9132qds.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/bsc9132qds.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/bsc9132qds.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/bsc9132qds.dts 2024-06-19 12:33:58.748200227 +0200 @@ -15,7 +15,7 @@ device_type = "memory"; }; - ifc: ifc@ff71e000 { + ifc: memory-controller@ff71e000 { /* NOR, NAND Flash on board */ ranges = <0x0 0x0 0x0 0x88000000 0x08000000 0x1 0x0 0x0 0xff800000 0x00010000>; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi 2024-06-19 12:33:58.748200227 +0200 @@ -35,7 +35,7 @@ &ifc { #address-cells = <2>; #size-cells = <1>; - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; /* FIXME: Test whether interrupts are split */ interrupts = <16 2 0 0 20 2 0 0>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/c293pcie.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/c293pcie.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/c293pcie.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/c293pcie.dts 2024-06-19 12:33:58.748200227 +0200 @@ -42,7 +42,7 @@ device_type = "memory"; }; - ifc: ifc@fffe1e000 { + ifc: memory-controller@fffe1e000 { reg = <0xf 0xffe1e000 0 0x2000>; ranges = <0x0 0x0 0xf 0xec000000 0x04000000 0x1 0x0 0xf 0xff800000 0x00010000 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/c293si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/c293si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/c293si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/c293si-post.dtsi 2024-06-19 12:33:58.748200227 +0200 @@ -35,7 +35,7 @@ &ifc { #address-cells = <2>; #size-cells = <1>; - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; interrupts = <19 2 0 0>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi 2024-06-19 12:33:58.752200295 +0200 @@ -199,6 +199,10 @@ /include/ "pq3-dma-0.dtsi" /include/ "pq3-etsec1-0.dtsi" + enet0: ethernet@24000 { + fsl,wake-on-filer; + fsl,pmc-handle = <&etsec1_clk>; + }; /include/ "pq3-etsec1-timer-0.dtsi" usb@22000 { @@ -222,9 +226,10 @@ }; /include/ "pq3-etsec1-2.dtsi" - - ethernet@26000 { + enet2: ethernet@26000 { cell-index = <1>; + fsl,wake-on-filer; + fsl,pmc-handle = <&etsec3_clk>; }; usb@2b000 { @@ -249,4 +254,9 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" + power@e0070 { + compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc"; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi 2024-06-19 12:33:58.752200295 +0200 @@ -188,4 +188,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi 2024-06-19 12:33:58.752200295 +0200 @@ -156,4 +156,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi 2024-06-19 12:33:58.752200295 +0200 @@ -193,4 +193,6 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010rdb_32b.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010rdb_32b.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010rdb_32b.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010rdb_32b.dtsi 2024-06-19 12:33:58.752200295 +0200 @@ -36,7 +36,7 @@ device_type = "memory"; }; -board_ifc: ifc: ifc@ffe1e000 { +board_ifc: ifc: memory-controller@ffe1e000 { /* NOR, NAND Flashes and CPLD on board */ ranges = <0x0 0x0 0x0 0xee000000 0x02000000 0x1 0x0 0x0 0xff800000 0x00010000 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010rdb_36b.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010rdb_36b.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010rdb_36b.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010rdb_36b.dtsi 2024-06-19 12:33:58.752200295 +0200 @@ -36,7 +36,7 @@ device_type = "memory"; }; -board_ifc: ifc: ifc@fffe1e000 { +board_ifc: ifc: memory-controller@fffe1e000 { /* NOR, NAND Flashes and CPLD on board */ ranges = <0x0 0x0 0xf 0xee000000 0x02000000 0x1 0x0 0xf 0xff800000 0x00010000 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi 2024-06-19 12:33:58.752200295 +0200 @@ -215,19 +215,3 @@ phy-connection-type = "sgmii"; }; }; - -&pci0 { - pcie@0 { - interrupt-map = < - /* IDSEL 0x0 */ - /* - *irq[4:5] are active-high - *irq[6:7] are active-low - */ - 0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0 - 0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0 - 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 - 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 - >; - }; -}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010rdb-pb_36b.dts 2024-06-19 12:33:58.752200295 +0200 @@ -56,3 +56,19 @@ }; /include/ "p1010si-post.dtsi" + +&pci0 { + pcie@0 { + interrupt-map = < + /* IDSEL 0x0 */ + /* + *irq[4:5] are active-high + *irq[6:7] are active-low + */ + 0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts 2024-06-19 12:33:58.752200295 +0200 @@ -29,3 +29,19 @@ }; /include/ "p1010si-post.dtsi" + +&pci0 { + pcie@0 { + interrupt-map = < + /* IDSEL 0x0 */ + /* + *irq[4:5] are active-high + *irq[6:7] are active-low + */ + 0000 0x0 0x0 0x1 &mpic 0x4 0x2 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x5 0x2 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 + >; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi 2024-06-19 12:33:58.756200364 +0200 @@ -35,7 +35,7 @@ &ifc { #address-cells = <2>; #size-cells = <1>; - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; interrupts = <16 2 0 0 19 2 0 0>; }; @@ -183,9 +183,23 @@ /include/ "pq3-etsec2-1.dtsi" /include/ "pq3-etsec2-2.dtsi" + enet0: ethernet@b0000 { + fsl,pmc-handle = <&etsec1_clk>; + }; + + enet1: ethernet@b1000 { + fsl,pmc-handle = <&etsec2_clk>; + }; + + enet2: ethernet@b2000 { + fsl,pmc-handle = <&etsec3_clk>; + }; + global-utilities@e0000 { compatible = "fsl,p1010-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi 2024-06-19 12:33:58.756200364 +0200 @@ -163,14 +163,17 @@ /include/ "pq3-etsec2-0.dtsi" enet0: enet0_grp2: ethernet@b0000 { + fsl,pmc-handle = <&etsec1_clk>; }; /include/ "pq3-etsec2-1.dtsi" enet1: enet1_grp2: ethernet@b1000 { + fsl,pmc-handle = <&etsec2_clk>; }; /include/ "pq3-etsec2-2.dtsi" enet2: enet2_grp2: ethernet@b2000 { + fsl,pmc-handle = <&etsec3_clk>; }; global-utilities@e0000 { @@ -178,6 +181,8 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; /include/ "pq3-etsec2-grp2-0.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi 2024-06-19 12:33:58.756200364 +0200 @@ -159,14 +159,17 @@ /include/ "pq3-etsec2-0.dtsi" enet0: enet0_grp2: ethernet@b0000 { + fsl,pmc-handle = <&etsec1_clk>; }; /include/ "pq3-etsec2-1.dtsi" enet1: enet1_grp2: ethernet@b1000 { + fsl,pmc-handle = <&etsec2_clk>; }; /include/ "pq3-etsec2-2.dtsi" enet2: enet2_grp2: ethernet@b2000 { + fsl,pmc-handle = <&etsec3_clk>; }; global-utilities@e0000 { @@ -174,6 +177,8 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + +/include/ "pq3-power.dtsi" }; &qe { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi 2024-06-19 12:33:58.756200364 +0200 @@ -225,11 +225,13 @@ /include/ "pq3-etsec2-0.dtsi" enet0: enet0_grp2: ethernet@b0000 { fsl,wake-on-filer; + fsl,pmc-handle = <&etsec1_clk>; }; /include/ "pq3-etsec2-1.dtsi" enet1: enet1_grp2: ethernet@b1000 { fsl,wake-on-filer; + fsl,pmc-handle = <&etsec2_clk>; }; global-utilities@e0000 { @@ -238,9 +240,10 @@ fsl,has-rstcr; }; - power@e0070{ - compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc"; - reg = <0xe0070 0x20>; +/include/ "pq3-power.dtsi" + power@e0070 { + compatible = "fsl,p1022-pmc", "fsl,mpc8536-pmc", + "fsl,mpc8548-pmc"; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p1023rdb-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1023rdb-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p1023rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p1023rdb-sdk.dts 2024-06-19 12:33:58.756200364 +0200 @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p1023rdb.dts" + +&soc { + fman0: fman@100000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + compatible = "fsl,fman", "simple-bus"; + ranges = <0 0x100000 0x100000>; + reg = <0x100000 0x100000>; + clock-frequency = <0>; + interrupts = < + 24 2 0 0 + 16 2 0 0>; + cc@0 { + compatible = "fsl,fman-cc"; + }; + muram@0 { + compatible = "fsl,fman-muram"; + reg = <0x0 0x10000>; + }; + bmi@80000 { + compatible = "fsl,fman-bmi"; + reg = <0x80000 0x400>; + }; + qmi@80400 { + compatible = "fsl,fman-qmi"; + reg = <0x80400 0x400>; + }; + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + fman0_rx0: port@88000 { + cell-index = <0>; + compatible = "fsl,fman-port-1g-rx"; + reg = <0x88000 0x1000>; + }; + fman0_rx1: port@89000 { + cell-index = <1>; + compatible = "fsl,fman-port-1g-rx"; + reg = <0x89000 0x1000>; + }; + fman0_tx0: port@a8000 { + cell-index = <0>; + compatible = "fsl,fman-port-1g-tx"; + reg = <0xa8000 0x1000>; + fsl,qman-channel-id = <0x40>; + }; + fman0_tx1: port@a9000 { + cell-index = <1>; + compatible = "fsl,fman-port-1g-tx"; + reg = <0xa9000 0x1000>; + fsl,qman-channel-id = <0x41>; + }; + fman0_oh1: port@82000 { + cell-index = <1>; + compatible = "fsl,fman-port-oh"; + reg = <0x82000 0x1000>; + fsl,qman-channel-id = <0x43>; + }; + fman0_oh2: port@83000 { + cell-index = <2>; + compatible = "fsl,fman-port-oh"; + reg = <0x83000 0x1000>; + fsl,qman-channel-id = <0x44>; + }; + fman0_oh3: port@84000 { + cell-index = <3>; + compatible = "fsl,fman-port-oh"; + reg = <0x84000 0x1000>; + fsl,qman-channel-id = <0x45>; + }; + fman0_oh4: port@85000 { + cell-index = <4>; + compatible = "fsl,fman-port-oh"; + reg = <0x85000 0x1000>; + fsl,qman-channel-id = <0x46>; + }; + enet0: ethernet@e0000 { + cell-index = <0>; + compatible = "fsl,fman-dtsec"; + reg = <0xe0000 0x1000>; + fsl,port-handles = <&fman0_rx0 &fman0_tx0>; + }; + enet1: ethernet@e2000 { + cell-index = <1>; + compatible = "fsl,fman-dtsec"; + reg = <0xe2000 0x1000>; + fsl,port-handles = <&fman0_rx1 &fman0_tx1>; + }; + mdio0: mdio@e1120 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-mdio"; + reg = <0xe1120 0xee0>; + interrupts = <26 1 0 0>; + }; + }; +}; + +&bportals { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <32 32>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi 2024-06-19 12:33:58.756200364 +0200 @@ -178,6 +178,10 @@ compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; }; /include/ "pq3-etsec1-0.dtsi" + enet0: ethernet@24000 { + fsl,pmc-handle = <&etsec1_clk>; + + }; /include/ "pq3-etsec1-timer-0.dtsi" ptp_clock@24e00 { @@ -186,7 +190,15 @@ /include/ "pq3-etsec1-1.dtsi" + enet1: ethernet@25000 { + fsl,pmc-handle = <&etsec2_clk>; + }; + /include/ "pq3-etsec1-2.dtsi" + enet2: ethernet@26000 { + fsl,pmc-handle = <&etsec3_clk>; + }; + /include/ "pq3-esdhc-0.dtsi" sdhc@2e000 { compatible = "fsl,p2020-esdhc", "fsl,esdhc"; @@ -202,8 +214,5 @@ fsl,has-rstcr; }; - pmc: power@e0070 { - compatible = "fsl,mpc8548-pmc"; - reg = <0xe0070 0x20>; - }; +/include/ "pq3-power.dtsi" }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p2041rdb-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/p2041rdb-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p2041rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p2041rdb-sdk.dts 2024-06-19 12:33:58.756200364 +0200 @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p2041rdb.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p3041ds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/p3041ds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p3041ds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p3041ds-sdk.dts 2024-06-19 12:33:58.756200364 +0200 @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p3041ds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@2 { + status = "disabled"; + }; + }; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p4080ds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/p4080ds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p4080ds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p4080ds-sdk.dts 2024-06-19 12:33:58.756200364 +0200 @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p4080ds.dts" + +/ { + + aliases { + phy_rgmii = &phyrgmii; + phy5_slot3 = &phy5slot3; + phy6_slot3 = &phy6slot3; + phy7_slot3 = &phy7slot3; + phy8_slot3 = &phy8slot3; + emi1_slot3 = &p4080mdio2; + emi1_slot4 = &p4080mdio1; + emi1_slot5 = &p4080mdio3; + emi1_rgmii = &p4080mdio0; + emi2_slot4 = &p4080xmdio1; + emi2_slot5 = &p4080xmdio3; + }; +}; + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-fman-1-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + ethernet@6 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + }; + ethernet@7 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + ethernet@8 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet8>; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet9>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p5020ds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/p5020ds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p5020ds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p5020ds-sdk.dts 2024-06-19 12:33:58.756200364 +0200 @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p5020ds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + status = "disabled"; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/p5040ds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/p5040ds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/p5040ds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/p5040ds-sdk.dts 2024-06-19 12:33:58.760200432 +0200 @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "p5040ds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-fman-1-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman1-portals-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + status = "disabled"; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + ethernet@6 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + status = "disabled"; + }; + ethernet@7 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + ethernet@8 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet8>; + }; + ethernet@9 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet9>; + }; + ethernet@10 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet10>; + }; + ethernet@11 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet11>; + }; + }; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/pq3-power.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/pq3-power.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/pq3-power.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/pq3-power.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -0,0 +1,48 @@ +/* + * PQ3 Power Management device tree stub + * + * Copyright 2012-2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +power@e0070 { + compatible = "fsl,mpc8548-pmc"; + reg = <0xe0070 0x20>; + + etsec1_clk: soc-clk@24 { + fsl,pmcdr-mask = <0x00000080>; + }; + etsec2_clk: soc-clk@25 { + fsl,pmcdr-mask = <0x00000040>; + }; + etsec3_clk: soc-clk@26 { + fsl,pmcdr-mask = <0x00000020>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-bman-portals-sdk.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-bman-portals-sdk.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-bman-portals-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-bman-portals-sdk.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -0,0 +1,80 @@ +/* + * QorIQ BMan Portal device tree stub for 10 portals + * + * Copyright 2011 - 2014 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&bportals { + bman-portal@0 { + cell-index = <0>; + }; + + bman-portal@4000 { + cell-index = <1>; + }; + + bman-portal@8000 { + cell-index = <2>; + }; + + bman-portal@c000 { + cell-index = <3>; + }; + + bman-portal@10000 { + cell-index = <4>; + }; + + bman-portal@14000 { + cell-index = <5>; + }; + + bman-portal@18000 { + cell-index = <6>; + }; + + bman-portal@1c000 { + cell-index = <7>; + }; + + bman-portal@20000 { + cell-index = <8>; + }; + + bman-portal@24000 { + cell-index = <9>; + }; + + bman-bpids@0 { + compatible = "fsl,bpid-range"; + fsl,bpid-range = <32 32>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-dpaa-eth.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-dpaa-eth.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-dpaa-eth.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-dpaa-eth.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -0,0 +1,62 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; }; fman0_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman0_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman0_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman0_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-chosen-fifo-resize.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-chosen-fifo-resize.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-chosen-fifo-resize.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-chosen-fifo-resize.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2018 NXP + */ + +/ { + chosen { + name = "chosen"; + dpaa-extended-args { + fman0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-extended-args"; + total-fifo-size = <0x27000>; + fman0_oh1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-op-extended-args"; + fifo-size = <0x800 0x0>; + num-dmas = <0x1 0x1>; + num-tnums = <0x1 0x4>; + }; + fman0_rx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman0_tx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman0_rx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-rx-extended-args"; + fifo-size = <0x7000 0x3000>; + num-dmas = <0x8 0x8>; + num-tnums = <0x10 0x8>; + }; + fman0_tx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-tx-extended-args"; + fifo-size = <0x4000 0x0>; + num-dmas = <0x8 0x0>; + num-tnums = <0x10 0x8>; + }; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-sdk.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-sdk.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-0-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-0-sdk.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 1g - 0 */ + port@a8000 { + fsl,qman-channel-id = <0x41>; + }; + /* tx - 1g - 1 */ + port@a9000 { + fsl,qman-channel-id = <0x42>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x43>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x44>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x45>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x40>; + }; + /* offline 0 */ + port@81000 { + fsl,qman-channel-id = <0x46>; + }; + /* offline 1 */ + port@82000 { + fsl,qman-channel-id = <0x47>; + }; + /* offline 2 */ + port@83000 { + fsl,qman-channel-id = <0x48>; + }; + /* offline 3 */ + port@84000 { + fsl,qman-channel-id = <0x49>; + }; + /* offline 4 */ + port@85000 { + fsl,qman-channel-id = <0x4a>; + }; + /* offline 5 */ + port@86000 { + fsl,qman-channel-id = <0x4b>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; }; fman1_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman1_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman1_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman1_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman1_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v2-port-rx"; + compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman1_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v2-port-tx"; + compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-chosen-fifo-resize.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-chosen-fifo-resize.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-chosen-fifo-resize.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-chosen-fifo-resize.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2018 NXP + */ + +/ { + chosen { + name = "chosen"; + dpaa-extended-args { + fman1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-extended-args"; + total-fifo-size = <0x27000>; + fman1_oh1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-op-extended-args"; + fifo-size = <0x800 0x0>; + num-dmas = <0x1 0x1>; + num-tnums = <0x1 0x4>; + }; + fman1_rx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx0-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx1-extd-args { + cell-index = <1>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx2-extd-args { + cell-index = <2>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx3-extd-args { + cell-index = <3>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-rx-extended-args"; + fifo-size = <0x2f00 0x2000>; + num-dmas = <0x1 0x1>; + num-tnums = <0x4 0x4>; + }; + fman1_tx4-extd-args { + cell-index = <4>; + compatible = "fsl,fman-port-1g-tx-extended-args"; + fifo-size = <0x2c00 0x0>; + num-dmas = <0x1 0x0>; + num-tnums = <0x4 0x4>; + }; + fman1_rx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-rx-extended-args"; + fifo-size = <0x7000 0x3000>; + num-dmas = <0x8 0x8>; + num-tnums = <0x10 0x8>; + }; + fman1_tx8-extd-args { + cell-index = <0>; + compatible = "fsl,fman-port-10g-tx-extended-args"; + fifo-size = <0x4000 0x0>; + num-dmas = <0x8 0x0>; + num-tnums = <0x10 0x8>; + }; + }; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-sdk.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-sdk.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman-1-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman-1-sdk.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman1 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 1g - 0 */ + port@a8000 { + fsl,qman-channel-id = <0x61>; + }; + /* tx - 1g - 1 */ + port@a9000 { + fsl,qman-channel-id = <0x62>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x63>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x64>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x65>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x60>; + }; + /* offline 0 */ + port@81000 { + fsl,qman-channel-id = <0x66>; + }; + /* offline 1 */ + port@82000 { + fsl,qman-channel-id = <0x67>; + }; + /* offline 2 */ + port@83000 { + fsl,qman-channel-id = <0x68>; + }; + /* offline 3 */ + port@84000 { + fsl,qman-channel-id = <0x69>; + }; + /* offline 4 */ + port@85000 { + fsl,qman-channel-id = <0x6a>; + }; + /* offline 5 */ + port@86000 { + fsl,qman-channel-id = <0x6b>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,7 +35,7 @@ fman@400000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x88000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; @@ -43,7 +43,7 @@ fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xa8000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,14 +35,14 @@ fman@400000 { fman0_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; fsl,fman-10g-port; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,7 +35,7 @@ fman@400000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x89000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; @@ -43,7 +43,7 @@ fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xa9000 0x1000>; fsl,fman-10g-port; fsl,fman-best-effort-port; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,14 +35,14 @@ fman@400000 { fman0_rx_0x11: port@91000 { cell-index = <0x11>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; reg = <0x91000 0x1000>; fsl,fman-10g-port; }; fman0_tx_0x31: port@b1000 { cell-index = <0x31>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; reg = <0xb1000 0x1000>; fsl,fman-10g-port; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman0_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman0_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman0_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman0_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman0_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@400000 { fman0_rx_0x0d: port@8d000 { cell-index = <0xd>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8d000 0x1000>; }; fman0_tx_0x2d: port@ad000 { cell-index = <0x2d>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xad000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-sdk.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-sdk.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-sdk.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman0 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 10g - 2 */ + port@a8000 { + fsl,qman-channel-id = <0x802>; + }; + /* tx - 10g - 3 */ + port@a9000 { + fsl,qman-channel-id = <0x803>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x804>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x805>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x806>; + }; + /* tx - 1g - 5 */ + port@ad000 { + fsl,qman-channel-id = <0x807>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x800>; + }; + /* tx - 10g - 1 */ + port@b1000 { + fsl,qman-channel-id = <0x801>; + }; + /* offline - 1 */ + port@82000 { + fsl,qman-channel-id = <0x809>; + }; + /* offline - 2 */ + port@83000 { + fsl,qman-channel-id = <0x80a>; + }; + /* offline - 3 */ + port@84000 { + fsl,qman-channel-id = <0x80b>; + }; + /* offline - 4 */ + port@85000 { + fsl,qman-channel-id = <0x80c>; + }; + /* offline - 5 */ + port@86000 { + fsl,qman-channel-id = <0x80d>; + }; + /* offline - 6 */ + port@87000 { + fsl,qman-channel-id = <0x80e>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + + vsps@dc000 { + compatible = "fsl,fman-vsps"; + reg = <0xdc000 0x1000>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,14 +35,14 @@ fman@500000 { fman1_rx_0x10: port@90000 { cell-index = <0x10>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x90000 0x1000>; fsl,fman-10g-port; }; fman1_tx_0x30: port@b0000 { cell-index = <0x30>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xb0000 0x1000>; fsl,fman-10g-port; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,14 +35,14 @@ fman@500000 { fman1_rx_0x11: port@91000 { cell-index = <0x11>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx"; reg = <0x91000 0x1000>; fsl,fman-10g-port; }; fman1_tx_0x31: port@b1000 { cell-index = <0x31>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx"; reg = <0xb1000 0x1000>; fsl,fman-10g-port; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x08: port@88000 { cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x88000 0x1000>; }; fman1_tx_0x28: port@a8000 { cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa8000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi 2024-06-19 12:33:58.760200432 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x09: port@89000 { cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x89000 0x1000>; }; fman1_tx_0x29: port@a9000 { cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xa9000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0a: port@8a000 { cell-index = <0xa>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8a000 0x1000>; }; fman1_tx_0x2a: port@aa000 { cell-index = <0x2a>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xaa000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0b: port@8b000 { cell-index = <0xb>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8b000 0x1000>; }; fman1_tx_0x2b: port@ab000 { cell-index = <0x2b>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xab000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0c: port@8c000 { cell-index = <0xc>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8c000 0x1000>; }; fman1_tx_0x2c: port@ac000 { cell-index = <0x2c>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xac000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -35,13 +35,13 @@ fman@500000 { fman1_rx_0x0d: port@8d000 { cell-index = <0xd>; - compatible = "fsl,fman-v3-port-rx"; + compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx"; reg = <0x8d000 0x1000>; }; fman1_tx_0x2d: port@ad000 { cell-index = <0x2d>; - compatible = "fsl,fman-v3-port-tx"; + compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx"; reg = <0xad000 0x1000>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-sdk.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-sdk.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-sdk.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +&fman1 { + compatible = "fsl,fman", "simple-bus"; + + /* tx - 1g - 0 */ + port@a8000 { + fsl,qman-channel-id = <0x822>; + }; + /* tx - 1g - 1 */ + port@a9000 { + fsl,qman-channel-id = <0x823>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x824>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x825>; + }; + /* tx - 1g - 4 */ + port@ac000 { + fsl,qman-channel-id = <0x826>; + }; + /* tx - 1g - 5 */ + port@ad000 { + fsl,qman-channel-id = <0x827>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x820>; + }; + /* tx - 10g - 1 */ + port@b1000 { + fsl,qman-channel-id = <0x821>; + }; + /* offline - 1 */ + port@82000 { + fsl,qman-channel-id = <0x829>; + }; + /* offline - 2 */ + port@83000 { + fsl,qman-channel-id = <0x82a>; + }; + /* offline - 3 */ + port@84000 { + fsl,qman-channel-id = <0x82b>; + }; + /* offline - 4 */ + port@85000 { + fsl,qman-channel-id = <0x82c>; + }; + /* offline - 5 */ + port@86000 { + fsl,qman-channel-id = <0x82d>; + }; + /* offline - 6 */ + port@87000 { + fsl,qman-channel-id = <0x82e>; + }; + + policer@c0000 { + compatible = "fsl,fman-policer"; + reg = <0xc0000 0x1000>; + }; + + keygen@c1000 { + compatible = "fsl,fman-keygen"; + reg = <0xc1000 0x1000>; + }; + + dma@c2000 { + compatible = "fsl,fman-dma"; + reg = <0xc2000 0x1000>; + }; + + fpm@c3000 { + compatible = "fsl,fman-fpm"; + reg = <0xc3000 0x1000>; + }; + + parser@c7000 { + compatible = "fsl,fman-parser"; + reg = <0xc7000 0x1000>; + }; + + vsps@dc000 { + compatible = "fsl,fman-vsps"; + reg = <0xdc000 0x1000>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals-sdk.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals-sdk.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals-sdk.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,51 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-fqids@0 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <256 256>; + }; + qman-fqids@1 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <32768 32768>; + }; + qman-pools@0 { + compatible = "fsl,pool-channel-range"; + fsl,pool-channel-range = <0x21 0xf>; + }; + qman-cgrids@0 { + compatible = "fsl,cgrid-range"; + fsl,cgrid-range = <0 256>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-32-sdk.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-32-sdk.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-32-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-32-sdk.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,42 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 - 2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-ceetm@0 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf00000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 32>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-8-sdk.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-8-sdk.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-8-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm0-8-sdk.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,42 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 - 2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-ceetm@0 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf00000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 8>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm1-32-sdk.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm1-32-sdk.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm1-32-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-qman3-ceetm1-32-sdk.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,42 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 - 2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-ceetm@1 { + compatible = "fsl,qman-ceetm"; + fsl,ceetm-lfqid-range = <0xf10000 0x1000>; + fsl,ceetm-sp-range = <0 16>; + fsl,ceetm-lni-range = <0 8>; + fsl,ceetm-channel-range = <0 32>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-qman3-portals-sdk.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-qman3-portals-sdk.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/qoriq-qman3-portals-sdk.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/qoriq-qman3-portals-sdk.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,51 @@ +/* + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&qportals { + qman-fqids@0 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <256 512>; + }; + qman-fqids@1 { + compatible = "fsl,fqid-range"; + fsl,fqid-range = <32768 32768>; + }; + qman-pools@0 { + compatible = "fsl,pool-channel-range"; + fsl,pool-channel-range = <0x401 0xf>; + }; + qman-cgrids@0 { + compatible = "fsl,cgrid-range"; + fsl,cgrid-range = <0 256>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1023rdb.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1023rdb.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1023rdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1023rdb.dts 2024-06-19 12:33:58.764200500 +0200 @@ -142,23 +142,23 @@ }; fman@400000 { - fm1mac1: ethernet@e0000 { + enet0: ethernet@e0000 { phy-handle = <&sgmii_rtk_phy2>; phy-connection-type = "sgmii"; sleep = <&rcpm 0x80000000>; }; - fm1mac2: ethernet@e2000 { + enet1: ethernet@e2000 { sleep = <&rcpm 0x40000000>; }; - fm1mac3: ethernet@e4000 { + enet2: ethernet@e4000 { phy-handle = <&sgmii_aqr_phy3>; phy-connection-type = "2500base-x"; sleep = <&rcpm 0x20000000>; }; - fm1mac4: ethernet@e6000 { + enet3: ethernet@e6000 { phy-handle = <&rgmii_rtk_phy1>; phy-connection-type = "rgmii"; sleep = <&rcpm 0x10000000>; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1023rdb-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1023rdb-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1023rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1023rdb-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1023rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -52,7 +52,7 @@ &ifc { #address-cells = <2>; #size-cells = <1>; - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; interrupts = <25 2 0 0>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1024qds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1024qds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1024qds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1024qds-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1024qds.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1024rdb.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1024rdb.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1024rdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1024rdb.dts 2024-06-19 12:33:58.764200500 +0200 @@ -91,7 +91,7 @@ board-control@2,0 { #address-cells = <1>; #size-cells = <1>; - compatible = "fsl,t1024-cpld"; + compatible = "fsl,t1024-cpld", "fsl,deepsleep-cpld"; reg = <3 0 0x300>; ranges = <0 3 0 0x300>; bank-width = <1>; @@ -174,23 +174,23 @@ }; fman@400000 { - fm1mac1: ethernet@e0000 { + enet0: ethernet@e0000 { phy-handle = <&xg_aqr105_phy3>; phy-connection-type = "xgmii"; sleep = <&rcpm 0x80000000>; }; - fm1mac2: ethernet@e2000 { + enet1: ethernet@e2000 { sleep = <&rcpm 0x40000000>; }; - fm1mac3: ethernet@e4000 { + enet2: ethernet@e4000 { phy-handle = <&rgmii_phy2>; phy-connection-type = "rgmii"; sleep = <&rcpm 0x20000000>; }; - fm1mac4: ethernet@e6000 { + enet3: ethernet@e6000 { phy-handle = <&rgmii_phy1>; phy-connection-type = "rgmii"; sleep = <&rcpm 0x10000000>; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1024rdb-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1024rdb-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1024rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1024rdb-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,28 @@ +#include "t1024rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1040d4rdb-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1040d4rdb-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1040d4rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1040d4rdb-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1040d4rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1040qds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1040qds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1040qds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1040qds-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1040qds.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1040rdb.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1040rdb.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1040rdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1040rdb.dts 2024-06-19 12:33:58.764200500 +0200 @@ -104,7 +104,7 @@ ifc: localbus@ffe124000 { cpld@3,0 { - compatible = "fsl,t1040rdb-cpld"; + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld"; }; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1040rdb-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1040rdb-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1040rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1040rdb-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1040rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 2024-06-19 12:33:58.764200500 +0200 @@ -52,7 +52,7 @@ &ifc { #address-cells = <2>; #size-cells = <1>; - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; interrupts = <25 2 0 0>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1042d4rdb-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1042d4rdb-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1042d4rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1042d4rdb-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1042d4rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1042qds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1042qds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1042qds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1042qds-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1042qds.dts" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1042rdb.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1042rdb.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1042rdb.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1042rdb.dts 2024-06-19 12:33:58.764200500 +0200 @@ -68,7 +68,7 @@ ifc: localbus@ffe124000 { cpld@3,0 { - compatible = "fsl,t1042rdb-cpld"; + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld"; }; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts 2024-06-19 12:33:58.764200500 +0200 @@ -41,7 +41,7 @@ ifc: localbus@ffe124000 { cpld@3,0 { - compatible = "fsl,t1042rdb_pi-cpld"; + compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld"; }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t1042rdb-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1042rdb-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t1042rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t1042rdb-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t1042rdb.dts" + + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-8-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t2080qds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t2080qds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t2080qds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t2080qds-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t2080qds.dts" + +/include/ "qoriq-fman-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t2080rdb-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t2080rdb-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t2080rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t2080rdb-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +#include "t2080rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + }; + ethernet@5 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + }; + ethernet@6 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + }; + ethernet@7 { + compatible = "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + }; +}; + +&bportals { + bman-portal@28000 { + cell-index = <0xa>; + }; + + bman-portal@2c000 { + cell-index = <0xb>; + }; + + bman-portal@30000 { + cell-index = <0xc>; + }; + + bman-portal@34000 { + cell-index = <0xd>; + }; + + bman-portal@38000 { + cell-index = <0xe>; + }; + + bman-portal@3c000 { + cell-index = <0xf>; + }; + + bman-portal@40000 { + cell-index = <0x10>; + }; + + bman-portal@44000 { + cell-index = <0x11>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t2081qds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t2081qds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t2081qds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t2081qds-sdk.dts 2024-06-19 12:33:58.764200500 +0200 @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "t2081qds.dts" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi 2024-06-19 12:33:58.768200569 +0200 @@ -50,7 +50,7 @@ &ifc { #address-cells = <2>; #size-cells = <1>; - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; interrupts = <25 2 0 0>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t4240qds-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t4240qds-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t4240qds-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t4240qds-sdk.dts 2024-06-19 12:33:58.768200569 +0200 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "t4240qds.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-dpaa-eth.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t4240rdb-sdk.dts linux-imx-phytec/arch/powerpc/boot/dts/fsl/t4240rdb-sdk.dts --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t4240rdb-sdk.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t4240rdb-sdk.dts 2024-06-19 12:33:58.768200569 +0200 @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2017-2018 NXP + */ + +/include/ "t4240rdb.dts" + +/include/ "qoriq-fman3-0-sdk.dtsi" +/include/ "qoriq-fman3-1-sdk.dtsi" +/include/ "qoriq-bman-portals-sdk.dtsi" +/include/ "qoriq-qman3-portals-sdk.dtsi" +/include/ "qoriq-qman3-ceetm0-32-sdk.dtsi" +/include/ "qoriq-qman3-ceetm1-32-sdk.dtsi" + +&soc { + fsldpaa: fsl,dpaa { + compatible = "simple-bus", "fsl,dpaa"; + ethernet@0 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet0>; + }; + ethernet@1 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet1>; + }; + ethernet@2 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet2>; + }; + ethernet@3 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet3>; + }; + ethernet@4 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet4>; + status = "disabled"; + }; + ethernet@5 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet5>; + status = "disabled"; + }; + ethernet@6 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet6>; + }; + ethernet@7 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet7>; + }; + ethernet@8 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet8>; + }; + ethernet@9 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet9>; + }; + ethernet@10 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet10>; + }; + ethernet@11 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet11>; + }; + ethernet@12 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet12>; + status = "disabled"; + }; + ethernet@13 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet13>; + status = "disabled"; + }; + ethernet@14 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet14>; + }; + ethernet@15 { + compatible = "fsl,t4240-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&enet15>; + }; + }; +}; + +&bportals { + bman-portal@28000 { + cell-index = <0xa>; + }; + + bman-portal@2c000 { + cell-index = <0xb>; + }; + + bman-portal@30000 { + cell-index = <0xc>; + }; + + bman-portal@34000 { + cell-index = <0xd>; + }; + + bman-portal@38000 { + cell-index = <0xe>; + }; + + bman-portal@3c000 { + cell-index = <0xf>; + }; + + bman-portal@40000 { + cell-index = <0x10>; + }; + + bman-portal@44000 { + cell-index = <0x11>; + }; + + bman-portal@48000 { + cell-index = <0x12>; + }; + + bman-portal@4c000 { + cell-index = <0x13>; + }; + + bman-portal@50000 { + cell-index = <0x14>; + }; + + bman-portal@54000 { + cell-index = <0x15>; + }; + + bman-portal@58000 { + cell-index = <0x16>; + }; + + bman-portal@5c000 { + cell-index = <0x17>; + }; + + bman-portal@60000 { + cell-index = <0x18>; + }; + + bman-portal@64000 { + cell-index = <0x19>; + }; + + bman-portal@68000 { + cell-index = <0x1a>; + }; + + bman-portal@6c000 { + cell-index = <0x1b>; + }; + + bman-portal@70000 { + cell-index = <0x1c>; + }; + + bman-portal@74000 { + cell-index = <0x1d>; + }; + + bman-portal@78000 { + cell-index = <0x1e>; + }; + + bman-portal@7c000 { + cell-index = <0x1f>; + }; + + bman-portal@80000 { + cell-index = <0x20>; + }; + + bman-portal@84000 { + cell-index = <0x21>; + }; + + bman-portal@88000 { + cell-index = <0x22>; + }; + + bman-portal@8c000 { + cell-index = <0x23>; + }; + + bman-portal@90000 { + cell-index = <0x24>; + }; + + bman-portal@94000 { + cell-index = <0x25>; + }; + + bman-portal@98000 { + cell-index = <0x26>; + }; + + bman-portal@9c000 { + cell-index = <0x27>; + }; + + bman-portal@a0000 { + cell-index = <0x28>; + }; + + bman-portal@a4000 { + cell-index = <0x29>; + }; + + bman-portal@a8000 { + cell-index = <0x2a>; + }; + + bman-portal@ac000 { + cell-index = <0x2b>; + }; + + bman-portal@b0000 { + cell-index = <0x2c>; + }; + + bman-portal@b4000 { + cell-index = <0x2d>; + }; + + bman-portal@b8000 { + cell-index = <0x2e>; + }; + + bman-portal@bc000 { + cell-index = <0x2f>; + }; + + bman-portal@c0000 { + cell-index = <0x30>; + }; + + bman-portal@c4000 { + cell-index = <0x31>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi linux-imx-phytec/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi --- linux-6.1.55/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi 2024-06-19 12:33:58.768200569 +0200 @@ -50,7 +50,7 @@ &ifc { #address-cells = <2>; #size-cells = <1>; - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; interrupts = <25 2 0 0>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/configs/85xx/p1023_sdk_defconfig linux-imx-phytec/arch/powerpc/configs/85xx/p1023_sdk_defconfig --- linux-6.1.55/arch/powerpc/configs/85xx/p1023_sdk_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/configs/85xx/p1023_sdk_defconfig 2024-06-19 12:33:58.784200842 +0200 @@ -0,0 +1,200 @@ +CONFIG_PPC_85xx=y +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_RCU_FANOUT=32 +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_P1023_RDB=y +CONFIG_P1023_RDS=y +# CONFIG_QUICC_ENGINE is not set +# CONFIG_CPM is not set +# CONFIG_CPM2 is not set +# CONFIG_QE_GPIO is not set +CONFIG_CPM2=y +CONFIG_HIGHMEM=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_MISC=m +CONFIG_MATH_EMULATION=y +CONFIG_SWIOTLB=y +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +# CONFIG_PCIEASPM is not set +CONFIG_PCI_MSI=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_ARPD=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_IP_SCTP=m +CONFIG_VLAN_8021Q=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_LEGACY=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_LOGGING=y +CONFIG_ATA=y +CONFIG_SATA_FSL=y +CONFIG_SATA_SIL24=y +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +CONFIG_HAS_FSL_QBMAN=y +CONFIG_FS_ENET=y +CONFIG_FSL_PQ_MDIO=y +CONFIG_FMAN_P1023=y +CONFIG_FSL_DPAA_ETH=y +CONFIG_E1000E=y +CONFIG_ATHEROS_PHY=y +CONFIG_PHYLIB=y +CONFIG_AT803X_PHY=y +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_FIXED_PHY=y +CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_HW_RANDOM=y +CONFIG_NVRAM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_CPM=m +CONFIG_I2C_MPC=y +CONFIG_GPIO_MPC8XXX=y +# CONFIG_HWMON is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_MON=y +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_STORAGE=y +CONFIG_EDAC=y +CONFIG_EDAC_MM_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_DMADEVICES=y +CONFIG_FSL_DMA=y +# CONFIG_NET_DMA is not set +CONFIG_STAGING=y +CONFIG_MEMORY=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_ADFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_CRAMFS=y +CONFIG_VXFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_CRC_T10DIF=y +CONFIG_FRAME_WARN=8092 +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +CONFIG_STRICT_DEVMEM=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/configs/fmanv3h.config linux-imx-phytec/arch/powerpc/configs/fmanv3h.config --- linux-6.1.55/arch/powerpc/configs/fmanv3h.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/configs/fmanv3h.config 2024-06-19 12:33:58.784200842 +0200 @@ -0,0 +1 @@ +CONFIG_FMAN_V3H=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/configs/fmanv3l.config linux-imx-phytec/arch/powerpc/configs/fmanv3l.config --- linux-6.1.55/arch/powerpc/configs/fmanv3l.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/configs/fmanv3l.config 2024-06-19 12:33:58.784200842 +0200 @@ -0,0 +1 @@ +CONFIG_FMAN_V3L=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/configs/sdk_dpaa.config linux-imx-phytec/arch/powerpc/configs/sdk_dpaa.config --- linux-6.1.55/arch/powerpc/configs/sdk_dpaa.config 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/configs/sdk_dpaa.config 2024-06-19 12:33:58.784200842 +0200 @@ -0,0 +1,7 @@ +CONFIG_STAGING=y +CONFIG_FSL_SDK_BMAN=y +CONFIG_FSL_SDK_QMAN=y +CONFIG_FSL_SDK_DPA=y +CONFIG_FSL_SDK_FMAN=y +CONFIG_FSL_SDK_DPAA_ETH=y +CONFIG_CORTINA_PHY=y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/include/asm/cacheflush.h linux-imx-phytec/arch/powerpc/include/asm/cacheflush.h --- linux-6.1.55/arch/powerpc/include/asm/cacheflush.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/include/asm/cacheflush.h 2024-06-19 12:33:58.792200979 +0200 @@ -44,6 +44,13 @@ clear_bit(PG_dcache_clean, &page->flags); } +extern void __flush_disable_L1(void); +#ifdef CONFIG_FSL_SOC_BOOKE +extern void flush_dcache_L1(void); +#else +#define flush_dcache_L1() do { } while (0) +#endif + void flush_icache_range(unsigned long start, unsigned long stop); #define flush_icache_range flush_icache_range diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/include/asm/cputable.h linux-imx-phytec/arch/powerpc/include/asm/cputable.h --- linux-6.1.55/arch/powerpc/include/asm/cputable.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/include/asm/cputable.h 2024-06-19 12:33:58.796201047 +0200 @@ -32,6 +32,14 @@ extern int machine_check_e500mc(struct pt_regs *regs); extern int machine_check_e500(struct pt_regs *regs); extern int machine_check_47x(struct pt_regs *regs); + +#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC) +extern void __flush_caches_e500v2(void); +extern void __flush_caches_e500mc(void); +extern void __flush_caches_e5500(void); +extern void __flush_caches_e6500(void); +#endif + int machine_check_8xx(struct pt_regs *regs); int machine_check_83xx(struct pt_regs *regs); @@ -59,6 +67,10 @@ /* flush caches inside the current cpu */ void (*cpu_down_flush)(void); +#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC) + /* flush caches of the cpu which is running the function */ + void (*cpu_flush_caches)(void); +#endif /* number of performance monitor counters */ unsigned int num_pmcs; enum powerpc_pmc_type pmc_type; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/include/asm/fsl_pm.h linux-imx-phytec/arch/powerpc/include/asm/fsl_pm.h --- linux-6.1.55/arch/powerpc/include/asm/fsl_pm.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/include/asm/fsl_pm.h 2024-06-19 12:33:58.796201047 +0200 @@ -7,6 +7,9 @@ #ifndef __PPC_FSL_PM_H #define __PPC_FSL_PM_H +#ifndef __ASSEMBLY__ +#include + #define E500_PM_PH10 1 #define E500_PM_PH15 2 #define E500_PM_PH20 3 @@ -42,6 +45,34 @@ extern const struct fsl_pm_ops *qoriq_pm_ops; +struct fsm_reg_vals { + u32 offset; + u32 value; +}; + +void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val); +void fsl_epu_setup_default(void __iomem *epu_base); +void fsl_npc_setup_default(void __iomem *npc_base); +void fsl_fsm_clean(void __iomem *base, struct fsm_reg_vals *val); +void fsl_epu_clean_default(void __iomem *epu_base); + +extern int fsl_dp_iomap(void); +extern void fsl_dp_iounmap(void); + +extern int fsl_enter_epu_deepsleep(void); +extern void fsl_dp_enter_low(void __iomem *ccsr_base, void __iomem *dcsr_base, + void __iomem *pld_base, int pld_flag); +extern void fsl_booke_deep_sleep_resume(void); + int __init fsl_rcpm_init(void); +void set_pm_suspend_state(suspend_state_t state); +suspend_state_t pm_suspend_state(void); + +void fsl_set_power_except(struct device *dev, int on); +#endif /* __ASSEMBLY__ */ + +#define T1040QDS_TETRA_FLAG 1 +#define T104xRDB_CPLD_FLAG 2 + #endif /* __PPC_FSL_PM_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/Kconfig linux-imx-phytec/arch/powerpc/Kconfig --- linux-6.1.55/arch/powerpc/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/Kconfig 2024-06-19 12:33:58.744200159 +0200 @@ -359,7 +359,7 @@ config ARCH_SUSPEND_POSSIBLE def_bool y depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \ - (PPC_85xx && !PPC_E500MC) || PPC_86xx || PPC_PSERIES \ + FSL_SOC_BOOKE || PPC_86xx || PPC_PSERIES \ || 44x || 40x config ARCH_SUSPEND_NONZERO_CPU @@ -1068,8 +1068,6 @@ config FSL_PMC bool - default y - depends on SUSPEND && (PPC_85xx || PPC_86xx) help Freescale MPC85xx/MPC86xx power management controller support (suspend/resume). For MPC83xx see platforms/83xx/suspend.c diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/kernel/85xx_entry_mapping.S linux-imx-phytec/arch/powerpc/kernel/85xx_entry_mapping.S --- linux-6.1.55/arch/powerpc/kernel/85xx_entry_mapping.S 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/kernel/85xx_entry_mapping.S 2024-06-19 12:33:58.820201457 +0200 @@ -166,6 +166,10 @@ and r6,r6,r20 ori r6,r6,MAS2_M_IF_NEEDED@l mtspr SPRN_MAS2,r6 +#ifdef ENTRY_DEEPSLEEP_SETUP + LOAD_REG_IMMEDIATE(r8, MEMORY_START) + ori r8,r8,(MAS3_SX|MAS3_SW|MAS3_SR) +#endif mtspr SPRN_MAS3,r8 tlbwe @@ -205,12 +209,18 @@ #error You need to specify the mapping or not use this at all. #endif +#ifdef ENTRY_DEEPSLEEP_SETUP + LOAD_REG_ADDR(r6, 2f) + mfmsr r7 + rlwinm r7,r7,0,~(MSR_IS|MSR_DS) +#else lis r7,MSR_KERNEL@h ori r7,r7,MSR_KERNEL@l bcl 20,31,$+4 /* Find our address */ 1: mflr r9 rlwimi r6,r9,0,20,31 addi r6,r6,(2f - 1b) +#endif mtspr SPRN_SRR0,r6 mtspr SPRN_SRR1,r7 rfi /* start execution out of TLB1[0] entry */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/kernel/asm-offsets.c linux-imx-phytec/arch/powerpc/kernel/asm-offsets.c --- linux-6.1.55/arch/powerpc/kernel/asm-offsets.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/kernel/asm-offsets.c 2024-06-19 12:33:58.820201457 +0200 @@ -324,6 +324,9 @@ OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features); OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup); OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore); +#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC) + OFFSET(CPU_FLUSH_CACHES, cpu_spec, cpu_flush_caches); +#endif OFFSET(pbe_address, pbe, address); OFFSET(pbe_orig_address, pbe, orig_address); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/kernel/cpu_setup_e500.S linux-imx-phytec/arch/powerpc/kernel/cpu_setup_e500.S --- linux-6.1.55/arch/powerpc/kernel/cpu_setup_e500.S 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/kernel/cpu_setup_e500.S 2024-06-19 12:33:58.820201457 +0200 @@ -331,3 +331,84 @@ /* L1 Data Cache of e6500 contains no modified data, no flush is required */ _GLOBAL(cpu_down_flush_e6500) blr + +_GLOBAL(__flush_caches_e500v2) + mflr r0 + bl flush_dcache_L1 + mtlr r0 + blr + +_GLOBAL(__flush_caches_e500mc) +_GLOBAL(__flush_caches_e5500) + mflr r0 + bl flush_dcache_L1 + bl flush_backside_L2_cache + mtlr r0 + blr + +/* L1 Data Cache of e6500 contains no modified data, no flush is required */ +_GLOBAL(__flush_caches_e6500) + blr + + /* r3 = virtual address of L2 controller, WIMG = 01xx */ +_GLOBAL(flush_disable_L2) + /* It's a write-through cache, so only invalidation is needed. */ + mbar + isync + lwz r4, 0(r3) + li r5, 1 + rlwimi r4, r5, 30, 0xc0000000 + stw r4, 0(r3) + + /* Wait for the invalidate to finish */ +1: lwz r4, 0(r3) + andis. r4, r4, 0x4000 + bne 1b + mbar + + blr + + /* r3 = virtual address of L2 controller, WIMG = 01xx */ +_GLOBAL(invalidate_enable_L2) + mbar + isync + lwz r4, 0(r3) + li r5, 3 + rlwimi r4, r5, 30, 0xc0000000 + stw r4, 0(r3) + + /* Wait for the invalidate to finish */ +1: lwz r4, 0(r3) + andis. r4, r4, 0x4000 + bne 1b + mbar + + blr + +/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */ +_GLOBAL(__flush_disable_L1) + mflr r10 + bl flush_dcache_L1 /* Flush L1 d-cache */ + mtlr r10 + + mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */ + li r5, 2 + rlwimi r4, r5, 0, 3 + + msync + isync + mtspr SPRN_L1CSR0, r4 + isync + +1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */ + andi. r4, r4, 2 + bne 1b + + mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */ + li r5, 2 + rlwimi r4, r5, 0, 3 + + mtspr SPRN_L1CSR1, r4 + isync + + blr diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/kernel/cpu_specs_85xx.h linux-imx-phytec/arch/powerpc/kernel/cpu_specs_85xx.h --- linux-6.1.55/arch/powerpc/kernel/cpu_specs_85xx.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/kernel/cpu_specs_85xx.h 2024-06-19 12:33:58.824201527 +0200 @@ -40,6 +40,7 @@ .machine_check = machine_check_e500, .platform = "ppc8548", .cpu_down_flush = cpu_down_flush_e500v2, + .cpu_flush_caches = __flush_caches_e500v2, }, { /* default match */ .pvr_mask = 0x00000000, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/kernel/cpu_specs_e500mc.h linux-imx-phytec/arch/powerpc/kernel/cpu_specs_e500mc.h --- linux-6.1.55/arch/powerpc/kernel/cpu_specs_e500mc.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/kernel/cpu_specs_e500mc.h 2024-06-19 12:33:58.824201527 +0200 @@ -31,6 +31,7 @@ .machine_check = machine_check_e500mc, .platform = "ppce500mc", .cpu_down_flush = cpu_down_flush_e500mc, + .cpu_flush_caches = __flush_caches_e500mc, }, #endif /* CONFIG_PPC32 */ { /* e5500 */ @@ -51,6 +52,7 @@ .machine_check = machine_check_e500mc, .platform = "ppce5500", .cpu_down_flush = cpu_down_flush_e5500, + .cpu_flush_caches = __flush_caches_e5500, }, { /* e6500 */ .pvr_mask = 0xffff0000, @@ -71,5 +73,6 @@ .machine_check = machine_check_e500mc, .platform = "ppce6500", .cpu_down_flush = cpu_down_flush_e6500, + .cpu_flush_caches = __flush_caches_e6500, }, }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/kernel/fsl_pm.c linux-imx-phytec/arch/powerpc/kernel/fsl_pm.c --- linux-6.1.55/arch/powerpc/kernel/fsl_pm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/kernel/fsl_pm.c 2024-06-19 12:33:58.828201595 +0200 @@ -0,0 +1,49 @@ +/* + * Freescale General Power Management Implementation + * + * Copyright 2018 NXP + * Author: Wang Dongsheng + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +static suspend_state_t pm_state; + +void set_pm_suspend_state(suspend_state_t state) +{ + pm_state = state; +} + +suspend_state_t pm_suspend_state(void) +{ + return pm_state; +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/kernel/head_64.S linux-imx-phytec/arch/powerpc/kernel/head_64.S --- linux-6.1.55/arch/powerpc/kernel/head_64.S 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/kernel/head_64.S 2024-06-19 12:33:58.828201595 +0200 @@ -869,7 +869,7 @@ /* * This subroutine clobbers r11 and r12 */ -enable_64b_mode: +_GLOBAL(enable_64b_mode) mfmsr r11 /* grab the current MSR */ #ifdef CONFIG_PPC_BOOK3E_64 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/kernel/Makefile linux-imx-phytec/arch/powerpc/kernel/Makefile --- linux-6.1.55/arch/powerpc/kernel/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/kernel/Makefile 2024-06-19 12:33:58.820201457 +0200 @@ -101,6 +101,7 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o obj-$(CONFIG_FA_DUMP) += fadump.o obj-$(CONFIG_PRESERVE_FA_DUMP) += fadump.o +obj-$(CONFIG_FSL_SOC) += fsl_pm.o obj-$(CONFIG_PPC_85xx) += idle_85xx.o obj-$(CONFIG_PPC_BOOK3S_32) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o obj-$(CONFIG_TAU) += tau_6xx.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/Makefile linux-imx-phytec/arch/powerpc/Makefile --- linux-6.1.55/arch/powerpc/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/Makefile 2024-06-19 12:33:58.744200159 +0200 @@ -288,6 +288,31 @@ $(call merge_into_defconfig,corenet_base.config,\ 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw dpaa) +PHONY += corenet32_smp_sdk_defconfig +corenet32_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_base.config,\ + 85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw sdk_dpaa) + +PHONY += corenet32_fmanv3l_smp_sdk_defconfig +corenet32_fmanv3l_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_base.config,\ + 85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw sdk_dpaa fmanv3l) + +PHONY += corenet64_smp_sdk_defconfig +corenet64_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_base.config,\ + 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw sdk_dpaa) + +PHONY += corenet64_fmanv3l_smp_sdk_defconfig +corenet64_fmanv3l_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_base.config,\ + 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw sdk_dpaa fmanv3l) + +PHONY += corenet64_fmanv3h_smp_sdk_defconfig +corenet64_fmanv3h_smp_sdk_defconfig: + $(call merge_into_defconfig,corenet_base.config,\ + 85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw sdk_dpaa fmanv3h) + PHONY += mpc86xx_defconfig mpc86xx_defconfig: $(call merge_into_defconfig,mpc86xx_base.config,\ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/mm/mmu_decl.h linux-imx-phytec/arch/powerpc/mm/mmu_decl.h --- linux-6.1.55/arch/powerpc/mm/mmu_decl.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/mm/mmu_decl.h 2024-06-19 12:33:58.876202415 +0200 @@ -86,6 +86,11 @@ #endif /* CONFIG_PPC_MMU_NOHASH */ +void settlbcam(int index, unsigned long virt, phys_addr_t phys, + unsigned long size, unsigned long flags, unsigned int pid); + +void cleartlbcam(unsigned long virt, unsigned int pid); + #ifdef CONFIG_PPC32 extern void mapin_ram(void); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/mm/nohash/e500.c linux-imx-phytec/arch/powerpc/mm/nohash/e500.c --- linux-6.1.55/arch/powerpc/mm/nohash/e500.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/mm/nohash/e500.c 2024-06-19 12:33:58.876202415 +0200 @@ -94,7 +94,7 @@ * an unsigned long (for example, 32-bit implementations cannot support a 4GB * size). */ -static void settlbcam(int index, unsigned long virt, phys_addr_t phys, +void settlbcam(int index, unsigned long virt, phys_addr_t phys, unsigned long size, unsigned long flags, unsigned int pid) { unsigned int tsize; @@ -135,6 +135,18 @@ tlbcam_addrs[index].phys = phys; } +void cleartlbcam(unsigned long virt, unsigned int pid) +{ + int i = 0; + for (i = 0; i < NUM_TLBCAMS; i++) { + if (tlbcam_addrs[i].start == virt) { + TLBCAM[i].MAS1 = 0; + loadcam_entry(i); + return; + } + } +} + static unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, phys_addr_t phys) { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/platforms/85xx/deepsleep.c linux-imx-phytec/arch/powerpc/platforms/85xx/deepsleep.c --- linux-6.1.55/arch/powerpc/platforms/85xx/deepsleep.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/platforms/85xx/deepsleep.c 2024-06-19 12:33:58.892202689 +0200 @@ -0,0 +1,349 @@ +/* + * Support deep sleep feature for T104x + * + * Copyright 2018 NXP + * Author: Chenhui Zhao + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SIZE_1MB 0x100000 +#define SIZE_2MB 0x200000 + +#define CPC_CPCHDBCR0 0x10f00 +#define CPC_CPCHDBCR0_SPEC_DIS 0x08000000 + +#define CCSR_SCFG_DPSLPCR 0xfc000 +#define CCSR_SCFG_DPSLPCR_WDRR_EN 0x1 +#define CCSR_SCFG_SPARECR2 0xfc504 +#define CCSR_SCFG_SPARECR3 0xfc508 + +#define CCSR_GPIO1_GPDIR 0x130000 +#define CCSR_GPIO1_GPODR 0x130004 +#define CCSR_GPIO1_GPDAT 0x130008 +#define CCSR_GPIO1_GPDIR_29 0x4 + +#define RCPM_BLOCK_OFFSET 0x00022000 +#define EPU_BLOCK_OFFSET 0x00000000 +#define NPC_BLOCK_OFFSET 0x00001000 + +#define CSTTACR0 0xb00 +#define CG1CR0 0x31c + +#define CCSR_LAW_BASE 0xC00 +#define DCFG_BRR 0xE4 /* boot release register */ +#define LCC_BSTRH 0x20 /* Boot space translation register high */ +#define LCC_BSTRL 0x24 /* Boot space translation register low */ +#define LCC_BSTAR 0x28 /* Boot space translation attribute register */ +#define RCPM_PCTBENR 0x1A0 /* Physical Core Timebase Enable Register */ +#define RCPM_BASE 0xE2000 +#define DCFG_BASE 0xE0000 + +/* 128 bytes buffer for restoring data broke by DDR training initialization */ +#define DDR_BUF_SIZE 128 +static u8 ddr_buff[DDR_BUF_SIZE] __aligned(64); + +static void *dcsr_base, *ccsr_base, *pld_base; +static int pld_flag; + +/* for law */ +struct fsl_law { + u32 lawbarh; /* LAWn base address high */ + u32 lawbarl; /* LAWn base address low */ + u32 lawar; /* LAWn attributes */ + u32 reserved; +}; + +struct fsl_law *saved_law; +static u32 num_laws; + +/* for nonboot cpu */ +struct fsl_bstr { + u32 bstrh; + u32 bstrl; + u32 bstar; + u32 cpu_mask; +}; +static struct fsl_bstr saved_bstr; + +int fsl_dp_iomap(void) +{ + struct device_node *np; + int ret = 0; + phys_addr_t ccsr_phy_addr, dcsr_phy_addr; + + saved_law = NULL; + ccsr_base = NULL; + dcsr_base = NULL; + pld_base = NULL; + + ccsr_phy_addr = get_immrbase(); + if (ccsr_phy_addr == -1) { + pr_err("%s: Can't get the address of CCSR\n", __func__); + ret = -EINVAL; + goto ccsr_err; + } + ccsr_base = ioremap(ccsr_phy_addr, SIZE_2MB); + if (!ccsr_base) { + ret = -ENOMEM; + goto ccsr_err; + } + + dcsr_phy_addr = get_dcsrbase(); + if (dcsr_phy_addr == -1) { + pr_err("%s: Can't get the address of DCSR\n", __func__); + ret = -EINVAL; + goto dcsr_err; + } + dcsr_base = ioremap(dcsr_phy_addr, SIZE_1MB); + if (!dcsr_base) { + ret = -ENOMEM; + goto dcsr_err; + } + + np = of_find_compatible_node(NULL, NULL, "fsl,tetra-fpga"); + if (np) { + pld_flag = T1040QDS_TETRA_FLAG; + } else { + np = of_find_compatible_node(NULL, NULL, "fsl,deepsleep-cpld"); + if (np) { + pld_flag = T104xRDB_CPLD_FLAG; + } else { + pr_err("%s: Can't find the FPGA/CPLD node\n", + __func__); + ret = -EINVAL; + goto pld_err; + } + } + pld_base = of_iomap(np, 0); + of_node_put(np); + + np = of_find_compatible_node(NULL, NULL, "fsl,corenet-law"); + if (!np) { + pr_err("%s: Can't find the node of \"law\"\n", __func__); + ret = -EINVAL; + goto alloc_err; + } + ret = of_property_read_u32(np, "fsl,num-laws", &num_laws); + if (ret) { + ret = -EINVAL; + goto alloc_err; + } + + saved_law = kzalloc(sizeof(*saved_law) * num_laws, GFP_KERNEL); + if (!saved_law) { + ret = -ENOMEM; + goto alloc_err; + } + of_node_put(np); + + return 0; + +alloc_err: + iounmap(pld_base); + pld_base = NULL; +pld_err: + iounmap(dcsr_base); + dcsr_base = NULL; +dcsr_err: + iounmap(ccsr_base); + ccsr_base = NULL; +ccsr_err: + return ret; +} + +void fsl_dp_iounmap(void) +{ + if (dcsr_base) { + iounmap(dcsr_base); + dcsr_base = NULL; + } + + if (ccsr_base) { + iounmap(ccsr_base); + ccsr_base = NULL; + } + + if (pld_base) { + iounmap(pld_base); + pld_base = NULL; + } + + kfree(saved_law); + saved_law = NULL; +} + +static void fsl_dp_ddr_save(void *ccsr_base) +{ + u32 ddr_buff_addr; + + /* + * DDR training initialization will break 128 bytes at the beginning + * of DDR, therefore, save them so that the bootloader will restore + * them. Assume that DDR is mapped to the address space started with + * CONFIG_PAGE_OFFSET. + */ + memcpy(ddr_buff, (void *)CONFIG_PAGE_OFFSET, DDR_BUF_SIZE); + + /* assume ddr_buff is in the physical address space of 4GB */ + ddr_buff_addr = (u32)(__pa(ddr_buff) & 0xffffffff); + + /* + * the bootloader will restore the first 128 bytes of DDR from + * the location indicated by the register SPARECR3 + */ + out_be32(ccsr_base + CCSR_SCFG_SPARECR3, ddr_buff_addr); +} + +static void fsl_dp_mp_save(void *ccsr) +{ + struct fsl_bstr *dst = &saved_bstr; + + dst->bstrh = in_be32(ccsr + LCC_BSTRH); + dst->bstrl = in_be32(ccsr + LCC_BSTRL); + dst->bstar = in_be32(ccsr + LCC_BSTAR); + dst->cpu_mask = in_be32(ccsr + DCFG_BASE + DCFG_BRR); +} + +static void fsl_dp_mp_restore(void *ccsr) +{ + struct fsl_bstr *src = &saved_bstr; + + out_be32(ccsr + LCC_BSTRH, src->bstrh); + out_be32(ccsr + LCC_BSTRL, src->bstrl); + out_be32(ccsr + LCC_BSTAR, src->bstar); + + /* release the nonboot cpus */ + out_be32(ccsr + DCFG_BASE + DCFG_BRR, src->cpu_mask); + + /* enable the time base */ + out_be32(ccsr + RCPM_BASE + RCPM_PCTBENR, src->cpu_mask); + /* read back to sync write */ + in_be32(ccsr + RCPM_BASE + RCPM_PCTBENR); +} + +static void fsl_dp_law_save(void *ccsr) +{ + int i; + struct fsl_law *dst = saved_law; + struct fsl_law *src = (void *)(ccsr + CCSR_LAW_BASE); + + for (i = 0; i < num_laws; i++) { + dst->lawbarh = in_be32(&src->lawbarh); + dst->lawbarl = in_be32(&src->lawbarl); + dst->lawar = in_be32(&src->lawar); + dst++; + src++; + } +} + +static void fsl_dp_law_restore(void *ccsr) +{ + int i; + struct fsl_law *src = saved_law; + struct fsl_law *dst = (void *)(ccsr + CCSR_LAW_BASE); + + for (i = 0; i < num_laws - 1; i++) { + out_be32(&dst->lawar, 0); + out_be32(&dst->lawbarl, src->lawbarl); + out_be32(&dst->lawbarh, src->lawbarh); + out_be32(&dst->lawar, src->lawar); + + /* Read back so that we sync the writes */ + in_be32(&dst->lawar); + src++; + dst++; + } +} + +static void fsl_dp_set_resume_pointer(void *ccsr_base) +{ + u32 resume_addr; + + /* the bootloader will finally jump to this address to return kernel */ +#ifdef CONFIG_PPC32 + resume_addr = (u32)(__pa(fsl_booke_deep_sleep_resume)); +#else + resume_addr = (u32)(__pa(*(u64 *)fsl_booke_deep_sleep_resume) + & 0xffffffff); +#endif + + /* use the register SPARECR2 to save the resume address */ + out_be32(ccsr_base + CCSR_SCFG_SPARECR2, resume_addr); + +} + +int fsl_enter_epu_deepsleep(void) +{ + fsl_dp_ddr_save(ccsr_base); + + fsl_dp_set_resume_pointer(ccsr_base); + + fsl_dp_mp_save(ccsr_base); + fsl_dp_law_save(ccsr_base); + /* enable Warm Device Reset request. */ + setbits32(ccsr_base + CCSR_SCFG_DPSLPCR, CCSR_SCFG_DPSLPCR_WDRR_EN); + + /* set GPIO1_29 as an output pin (not open-drain), and output 0 */ + clrbits32(ccsr_base + CCSR_GPIO1_GPDAT, CCSR_GPIO1_GPDIR_29); + clrbits32(ccsr_base + CCSR_GPIO1_GPODR, CCSR_GPIO1_GPDIR_29); + setbits32(ccsr_base + CCSR_GPIO1_GPDIR, CCSR_GPIO1_GPDIR_29); + + /* + * Disable CPC speculation to avoid deep sleep hang, especially + * in secure boot mode. This bit will be cleared automatically + * when resuming from deep sleep. + */ + setbits32(ccsr_base + CPC_CPCHDBCR0, CPC_CPCHDBCR0_SPEC_DIS); + + fsl_epu_setup_default(dcsr_base + EPU_BLOCK_OFFSET); + fsl_npc_setup_default(dcsr_base + NPC_BLOCK_OFFSET); + out_be32(dcsr_base + RCPM_BLOCK_OFFSET + CSTTACR0, 0x00001001); + out_be32(dcsr_base + RCPM_BLOCK_OFFSET + CG1CR0, 0x00000001); + + fsl_dp_enter_low(ccsr_base, dcsr_base, pld_base, pld_flag); + + fsl_dp_law_restore(ccsr_base); + fsl_dp_mp_restore(ccsr_base); + + /* disable Warm Device Reset request */ + clrbits32(ccsr_base + CCSR_SCFG_DPSLPCR, CCSR_SCFG_DPSLPCR_WDRR_EN); + + fsl_epu_clean_default(dcsr_base + EPU_BLOCK_OFFSET); + + return 0; +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/platforms/85xx/Kconfig linux-imx-phytec/arch/powerpc/platforms/85xx/Kconfig --- linux-6.1.55/arch/powerpc/platforms/85xx/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/platforms/85xx/Kconfig 2024-06-19 12:33:58.892202689 +0200 @@ -10,6 +10,8 @@ select SERIAL_8250_EXTENDED if SERIAL_8250 select SERIAL_8250_SHARE_IRQ if SERIAL_8250 select FSL_CORENET_RCPM if PPC_E500MC + select FSL_QORIQ_PM if SUSPEND && PPC_E500MC + select FSL_PMC if SUSPEND && !PPC_E500MC default y if FSL_SOC_BOOKE @@ -276,3 +278,7 @@ config TQM85xx bool + +config FSL_QORIQ_PM + bool + select FSL_SLEEP_FSM diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/platforms/85xx/Makefile linux-imx-phytec/arch/powerpc/platforms/85xx/Makefile --- linux-6.1.55/arch/powerpc/platforms/85xx/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/platforms/85xx/Makefile 2024-06-19 12:33:58.892202689 +0200 @@ -6,6 +6,8 @@ ifneq ($(CONFIG_FSL_CORENET_RCPM),y) obj-$(CONFIG_SMP) += mpc85xx_pm_ops.o endif +obj-$(CONFIG_SUSPEND) += sleep.o +obj-$(CONFIG_FSL_QORIQ_PM) += qoriq_pm.o deepsleep.o obj-y += common.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/platforms/85xx/qoriq_pm.c linux-imx-phytec/arch/powerpc/platforms/85xx/qoriq_pm.c --- linux-6.1.55/arch/powerpc/platforms/85xx/qoriq_pm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/platforms/85xx/qoriq_pm.c 2024-06-19 12:33:58.892202689 +0200 @@ -0,0 +1,222 @@ +/* + * Support Power Management feature + * + * Copyright 2018 NXP + * Author: Chenhui Zhao + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include + +#define FSL_SLEEP 0x1 +#define FSL_DEEP_SLEEP 0x2 + +int (*fsl_enter_deepsleep)(void); + +/* specify the sleep state of the present platform */ +unsigned int sleep_pm_state; +/* supported sleep modes by the present platform */ +static unsigned int sleep_modes; + +/** + * fsl_set_power_except - set which IP block is not powerdown when sleep, + * such as MAC, USB, etc. + * + * @dev: a pointer to the struct device + * @on: if 1, do not power down; if 0, power down. + */ +void fsl_set_power_except(struct device *dev, int on) +{ + u32 value[2]; + u32 pw_mask; + int ret; + struct device_node *mac_node; + const phandle *phandle_prop; + + if (dev && !strncmp(dev->bus->name, "usb", 3)) { + struct usb_device *udev = container_of(dev, + struct usb_device, dev); + struct device *controller = udev->bus->controller; + + ret = of_property_read_u32_array(controller->parent->of_node, + "sleep", value, 2); + } else + ret = of_property_read_u32_array(dev->of_node, "sleep", + value, 2); + + if (ret) { + /* search fman mac node */ + phandle_prop = of_get_property(dev->of_node, "fsl,fman-mac", + NULL); + if (phandle_prop == NULL) + goto err; + + mac_node = of_find_node_by_phandle(*phandle_prop); + ret = of_property_read_u32_array(mac_node, "sleep", value, 2); + of_node_put(mac_node); + if (ret) + goto err; + } + /* get the second value, it is a mask */ + pw_mask = value[1]; + qoriq_pm_ops->set_ip_power(on, pw_mask); + return; + +err: + dev_err(dev, "Can not set wakeup sources\n"); +} +EXPORT_SYMBOL_GPL(fsl_set_power_except); + +void qoriq_set_wakeup_source(struct device *dev, void *enable) +{ + if (!device_may_wakeup(dev)) + return; + + fsl_set_power_except(dev, *((int *)enable)); +} + +static int qoriq_suspend_enter(suspend_state_t state) +{ + int ret = 0; + int cpu; + + switch (state) { + case PM_SUSPEND_STANDBY: + + if (cur_cpu_spec->cpu_flush_caches) + cur_cpu_spec->cpu_flush_caches(); + + ret = qoriq_pm_ops->plat_enter_sleep(); + + break; + + case PM_SUSPEND_MEM: + + cpu = smp_processor_id(); + qoriq_pm_ops->irq_mask(cpu); + + ret = fsl_enter_deepsleep(); + + qoriq_pm_ops->irq_unmask(cpu); + + break; + + default: + ret = -EINVAL; + + } + + return ret; +} + +static int qoriq_suspend_valid(suspend_state_t state) +{ + set_pm_suspend_state(state); + + if (state == PM_SUSPEND_STANDBY && (sleep_modes & FSL_SLEEP)) + return 1; + + if (state == PM_SUSPEND_MEM && (sleep_modes & FSL_DEEP_SLEEP)) + return 1; + + set_pm_suspend_state(PM_SUSPEND_ON); + return 0; +} + +static int qoriq_suspend_begin(suspend_state_t state) +{ + const int enable = 1; + + dpm_for_each_dev((void *)&enable, qoriq_set_wakeup_source); + + if (state == PM_SUSPEND_MEM) + return fsl_dp_iomap(); + + return 0; +} + +static void qoriq_suspend_end(void) +{ + const int enable = 0; + + dpm_for_each_dev((void *)&enable, qoriq_set_wakeup_source); + + set_pm_suspend_state(PM_SUSPEND_ON); + fsl_dp_iounmap(); +} + +static const struct platform_suspend_ops qoriq_suspend_ops = { + .valid = qoriq_suspend_valid, + .enter = qoriq_suspend_enter, + .begin = qoriq_suspend_begin, + .end = qoriq_suspend_end, +}; + +static const struct of_device_id deepsleep_matches[] = { + { + .compatible = "fsl,t1040-rcpm", + }, + { + .compatible = "fsl,t1024-rcpm", + }, + { + .compatible = "fsl,t1023-rcpm", + }, + {}, +}; + +static int __init qoriq_suspend_init(void) +{ + struct device_node *np; + + sleep_modes = FSL_SLEEP; + sleep_pm_state = PLAT_PM_SLEEP; + + np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-rcpm-2.0"); + if (np) + sleep_pm_state = PLAT_PM_LPM20; + + np = of_find_matching_node_and_match(NULL, deepsleep_matches, NULL); + if (np) { + fsl_enter_deepsleep = fsl_enter_epu_deepsleep; + sleep_modes |= FSL_DEEP_SLEEP; + } + + suspend_set_ops(&qoriq_suspend_ops); + set_pm_suspend_state(PM_SUSPEND_ON); + + return 0; +} +arch_initcall(qoriq_suspend_init); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/platforms/85xx/sleep.S linux-imx-phytec/arch/powerpc/platforms/85xx/sleep.S --- linux-6.1.55/arch/powerpc/platforms/85xx/sleep.S 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/arch/powerpc/platforms/85xx/sleep.S 2024-06-19 12:33:58.892202689 +0200 @@ -0,0 +1,1192 @@ +/* + * Enter and leave deep sleep/sleep state + * + * Copyright 2018 NXP + * Author: Scott Wood + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. +*/ + +#include +#include +#include +#include +#include +#include + +/* + * the number of bytes occupied by one register + * the value of 8 is compatible with both 32-bit and 64-bit registers + */ +#define STRIDE_SIZE 8 + +/* GPR0 - GPR31 */ +#define BOOKE_GPR0_OFF 0x0000 +#define BOOKE_GPR_COUNT 32 +/* IVOR0 - IVOR42 */ +#define BOOKE_IVOR0_OFF (BOOKE_GPR0_OFF + BOOKE_GPR_COUNT * STRIDE_SIZE) +#define BOOKE_IVOR_COUNT 43 +/* SPRG0 - SPRG9 */ +#define BOOKE_SPRG0_OFF (BOOKE_IVOR0_OFF + BOOKE_IVOR_COUNT * STRIDE_SIZE) +#define BOOKE_SPRG_COUNT 10 +/* IVPR */ +#define BOOKE_IVPR_OFF (BOOKE_SPRG0_OFF + BOOKE_SPRG_COUNT * STRIDE_SIZE) + +#define BOOKE_LR_OFF (BOOKE_IVPR_OFF + STRIDE_SIZE) +#define BOOKE_MSR_OFF (BOOKE_LR_OFF + STRIDE_SIZE) +#define BOOKE_TBU_OFF (BOOKE_MSR_OFF + STRIDE_SIZE) +#define BOOKE_TBL_OFF (BOOKE_TBU_OFF + STRIDE_SIZE) +#define BOOKE_EPCR_OFF (BOOKE_TBL_OFF + STRIDE_SIZE) +#define BOOKE_HID0_OFF (BOOKE_EPCR_OFF + STRIDE_SIZE) +#define BOOKE_PIR_OFF (BOOKE_HID0_OFF + STRIDE_SIZE) +#define BOOKE_PID0_OFF (BOOKE_PIR_OFF + STRIDE_SIZE) +#define BOOKE_BUCSR_OFF (BOOKE_PID0_OFF + STRIDE_SIZE) + +#define BUFFER_SIZE (BOOKE_BUCSR_OFF + STRIDE_SIZE) + +#undef SAVE_GPR +#define SAVE_GPR(gpr, offset) \ + PPC_STL gpr, offset(r10) + +#define RESTORE_GPR(gpr, offset) \ + PPC_LL gpr, offset(r10) + +#define SAVE_SPR(spr, offset) \ + mfspr r0, spr ;\ + PPC_STL r0, offset(r10) + +#define RESTORE_SPR(spr, offset) \ + PPC_LL r0, offset(r10) ;\ + mtspr spr, r0 + +#define SAVE_ALL_GPR \ + SAVE_GPR(r1, BOOKE_GPR0_OFF + STRIDE_SIZE * 1) ;\ + SAVE_GPR(r2, BOOKE_GPR0_OFF + STRIDE_SIZE * 2) ;\ + SAVE_GPR(r13, BOOKE_GPR0_OFF + STRIDE_SIZE * 13) ;\ + SAVE_GPR(r14, BOOKE_GPR0_OFF + STRIDE_SIZE * 14) ;\ + SAVE_GPR(r15, BOOKE_GPR0_OFF + STRIDE_SIZE * 15) ;\ + SAVE_GPR(r16, BOOKE_GPR0_OFF + STRIDE_SIZE * 16) ;\ + SAVE_GPR(r17, BOOKE_GPR0_OFF + STRIDE_SIZE * 17) ;\ + SAVE_GPR(r18, BOOKE_GPR0_OFF + STRIDE_SIZE * 18) ;\ + SAVE_GPR(r19, BOOKE_GPR0_OFF + STRIDE_SIZE * 19) ;\ + SAVE_GPR(r20, BOOKE_GPR0_OFF + STRIDE_SIZE * 20) ;\ + SAVE_GPR(r21, BOOKE_GPR0_OFF + STRIDE_SIZE * 21) ;\ + SAVE_GPR(r22, BOOKE_GPR0_OFF + STRIDE_SIZE * 22) ;\ + SAVE_GPR(r23, BOOKE_GPR0_OFF + STRIDE_SIZE * 23) ;\ + SAVE_GPR(r24, BOOKE_GPR0_OFF + STRIDE_SIZE * 24) ;\ + SAVE_GPR(r25, BOOKE_GPR0_OFF + STRIDE_SIZE * 25) ;\ + SAVE_GPR(r26, BOOKE_GPR0_OFF + STRIDE_SIZE * 26) ;\ + SAVE_GPR(r27, BOOKE_GPR0_OFF + STRIDE_SIZE * 27) ;\ + SAVE_GPR(r28, BOOKE_GPR0_OFF + STRIDE_SIZE * 28) ;\ + SAVE_GPR(r29, BOOKE_GPR0_OFF + STRIDE_SIZE * 29) ;\ + SAVE_GPR(r30, BOOKE_GPR0_OFF + STRIDE_SIZE * 30) ;\ + SAVE_GPR(r31, BOOKE_GPR0_OFF + STRIDE_SIZE * 31) + +#define RESTORE_ALL_GPR \ + RESTORE_GPR(r1, BOOKE_GPR0_OFF + STRIDE_SIZE * 1) ;\ + RESTORE_GPR(r2, BOOKE_GPR0_OFF + STRIDE_SIZE * 2) ;\ + RESTORE_GPR(r13, BOOKE_GPR0_OFF + STRIDE_SIZE * 13) ;\ + RESTORE_GPR(r14, BOOKE_GPR0_OFF + STRIDE_SIZE * 14) ;\ + RESTORE_GPR(r15, BOOKE_GPR0_OFF + STRIDE_SIZE * 15) ;\ + RESTORE_GPR(r16, BOOKE_GPR0_OFF + STRIDE_SIZE * 16) ;\ + RESTORE_GPR(r17, BOOKE_GPR0_OFF + STRIDE_SIZE * 17) ;\ + RESTORE_GPR(r18, BOOKE_GPR0_OFF + STRIDE_SIZE * 18) ;\ + RESTORE_GPR(r19, BOOKE_GPR0_OFF + STRIDE_SIZE * 19) ;\ + RESTORE_GPR(r20, BOOKE_GPR0_OFF + STRIDE_SIZE * 20) ;\ + RESTORE_GPR(r21, BOOKE_GPR0_OFF + STRIDE_SIZE * 21) ;\ + RESTORE_GPR(r22, BOOKE_GPR0_OFF + STRIDE_SIZE * 22) ;\ + RESTORE_GPR(r23, BOOKE_GPR0_OFF + STRIDE_SIZE * 23) ;\ + RESTORE_GPR(r24, BOOKE_GPR0_OFF + STRIDE_SIZE * 24) ;\ + RESTORE_GPR(r25, BOOKE_GPR0_OFF + STRIDE_SIZE * 25) ;\ + RESTORE_GPR(r26, BOOKE_GPR0_OFF + STRIDE_SIZE * 26) ;\ + RESTORE_GPR(r27, BOOKE_GPR0_OFF + STRIDE_SIZE * 27) ;\ + RESTORE_GPR(r28, BOOKE_GPR0_OFF + STRIDE_SIZE * 28) ;\ + RESTORE_GPR(r29, BOOKE_GPR0_OFF + STRIDE_SIZE * 29) ;\ + RESTORE_GPR(r30, BOOKE_GPR0_OFF + STRIDE_SIZE * 30) ;\ + RESTORE_GPR(r31, BOOKE_GPR0_OFF + STRIDE_SIZE * 31) + +#define SAVE_ALL_SPRG \ + SAVE_SPR(SPRN_SPRG0, BOOKE_SPRG0_OFF + STRIDE_SIZE * 0) ;\ + SAVE_SPR(SPRN_SPRG1, BOOKE_SPRG0_OFF + STRIDE_SIZE * 1) ;\ + SAVE_SPR(SPRN_SPRG2, BOOKE_SPRG0_OFF + STRIDE_SIZE * 2) ;\ + SAVE_SPR(SPRN_SPRG3, BOOKE_SPRG0_OFF + STRIDE_SIZE * 3) ;\ + SAVE_SPR(SPRN_SPRG4, BOOKE_SPRG0_OFF + STRIDE_SIZE * 4) ;\ + SAVE_SPR(SPRN_SPRG5, BOOKE_SPRG0_OFF + STRIDE_SIZE * 5) ;\ + SAVE_SPR(SPRN_SPRG6, BOOKE_SPRG0_OFF + STRIDE_SIZE * 6) ;\ + SAVE_SPR(SPRN_SPRG7, BOOKE_SPRG0_OFF + STRIDE_SIZE * 7) ;\ + SAVE_SPR(SPRN_SPRG8, BOOKE_SPRG0_OFF + STRIDE_SIZE * 8) ;\ + SAVE_SPR(SPRN_SPRG9, BOOKE_SPRG0_OFF + STRIDE_SIZE * 9) + +#define RESTORE_ALL_SPRG \ + RESTORE_SPR(SPRN_SPRG0, BOOKE_SPRG0_OFF + STRIDE_SIZE * 0) ;\ + RESTORE_SPR(SPRN_SPRG1, BOOKE_SPRG0_OFF + STRIDE_SIZE * 1) ;\ + RESTORE_SPR(SPRN_SPRG2, BOOKE_SPRG0_OFF + STRIDE_SIZE * 2) ;\ + RESTORE_SPR(SPRN_SPRG3, BOOKE_SPRG0_OFF + STRIDE_SIZE * 3) ;\ + RESTORE_SPR(SPRN_SPRG4, BOOKE_SPRG0_OFF + STRIDE_SIZE * 4) ;\ + RESTORE_SPR(SPRN_SPRG5, BOOKE_SPRG0_OFF + STRIDE_SIZE * 5) ;\ + RESTORE_SPR(SPRN_SPRG6, BOOKE_SPRG0_OFF + STRIDE_SIZE * 6) ;\ + RESTORE_SPR(SPRN_SPRG7, BOOKE_SPRG0_OFF + STRIDE_SIZE * 7) ;\ + RESTORE_SPR(SPRN_SPRG8, BOOKE_SPRG0_OFF + STRIDE_SIZE * 8) ;\ + RESTORE_SPR(SPRN_SPRG9, BOOKE_SPRG0_OFF + STRIDE_SIZE * 9) + +#define SAVE_ALL_IVOR \ + SAVE_SPR(SPRN_IVOR0, BOOKE_IVOR0_OFF + STRIDE_SIZE * 0) ;\ + SAVE_SPR(SPRN_IVOR1, BOOKE_IVOR0_OFF + STRIDE_SIZE * 1) ;\ + SAVE_SPR(SPRN_IVOR2, BOOKE_IVOR0_OFF + STRIDE_SIZE * 2) ;\ + SAVE_SPR(SPRN_IVOR3, BOOKE_IVOR0_OFF + STRIDE_SIZE * 3) ;\ + SAVE_SPR(SPRN_IVOR4, BOOKE_IVOR0_OFF + STRIDE_SIZE * 4) ;\ + SAVE_SPR(SPRN_IVOR5, BOOKE_IVOR0_OFF + STRIDE_SIZE * 5) ;\ + SAVE_SPR(SPRN_IVOR6, BOOKE_IVOR0_OFF + STRIDE_SIZE * 6) ;\ + SAVE_SPR(SPRN_IVOR7, BOOKE_IVOR0_OFF + STRIDE_SIZE * 7) ;\ + SAVE_SPR(SPRN_IVOR8, BOOKE_IVOR0_OFF + STRIDE_SIZE * 8) ;\ + SAVE_SPR(SPRN_IVOR9, BOOKE_IVOR0_OFF + STRIDE_SIZE * 9) ;\ + SAVE_SPR(SPRN_IVOR10, BOOKE_IVOR0_OFF + STRIDE_SIZE * 10) ;\ + SAVE_SPR(SPRN_IVOR11, BOOKE_IVOR0_OFF + STRIDE_SIZE * 11) ;\ + SAVE_SPR(SPRN_IVOR12, BOOKE_IVOR0_OFF + STRIDE_SIZE * 12) ;\ + SAVE_SPR(SPRN_IVOR13, BOOKE_IVOR0_OFF + STRIDE_SIZE * 13) ;\ + SAVE_SPR(SPRN_IVOR14, BOOKE_IVOR0_OFF + STRIDE_SIZE * 14) ;\ + SAVE_SPR(SPRN_IVOR15, BOOKE_IVOR0_OFF + STRIDE_SIZE * 15) ;\ + SAVE_SPR(SPRN_IVOR35, BOOKE_IVOR0_OFF + STRIDE_SIZE * 35) ;\ + SAVE_SPR(SPRN_IVOR36, BOOKE_IVOR0_OFF + STRIDE_SIZE * 36) ;\ + SAVE_SPR(SPRN_IVOR37, BOOKE_IVOR0_OFF + STRIDE_SIZE * 37) ;\ + SAVE_SPR(SPRN_IVOR38, BOOKE_IVOR0_OFF + STRIDE_SIZE * 38) ;\ + SAVE_SPR(SPRN_IVOR39, BOOKE_IVOR0_OFF + STRIDE_SIZE * 39) ;\ + SAVE_SPR(SPRN_IVOR40, BOOKE_IVOR0_OFF + STRIDE_SIZE * 40) ;\ + SAVE_SPR(SPRN_IVOR41, BOOKE_IVOR0_OFF + STRIDE_SIZE * 41) + +#define RESTORE_ALL_IVOR \ + RESTORE_SPR(SPRN_IVOR0, BOOKE_IVOR0_OFF + STRIDE_SIZE * 0) ;\ + RESTORE_SPR(SPRN_IVOR1, BOOKE_IVOR0_OFF + STRIDE_SIZE * 1) ;\ + RESTORE_SPR(SPRN_IVOR2, BOOKE_IVOR0_OFF + STRIDE_SIZE * 2) ;\ + RESTORE_SPR(SPRN_IVOR3, BOOKE_IVOR0_OFF + STRIDE_SIZE * 3) ;\ + RESTORE_SPR(SPRN_IVOR4, BOOKE_IVOR0_OFF + STRIDE_SIZE * 4) ;\ + RESTORE_SPR(SPRN_IVOR5, BOOKE_IVOR0_OFF + STRIDE_SIZE * 5) ;\ + RESTORE_SPR(SPRN_IVOR6, BOOKE_IVOR0_OFF + STRIDE_SIZE * 6) ;\ + RESTORE_SPR(SPRN_IVOR7, BOOKE_IVOR0_OFF + STRIDE_SIZE * 7) ;\ + RESTORE_SPR(SPRN_IVOR8, BOOKE_IVOR0_OFF + STRIDE_SIZE * 8) ;\ + RESTORE_SPR(SPRN_IVOR9, BOOKE_IVOR0_OFF + STRIDE_SIZE * 9) ;\ + RESTORE_SPR(SPRN_IVOR10, BOOKE_IVOR0_OFF + STRIDE_SIZE * 10) ;\ + RESTORE_SPR(SPRN_IVOR11, BOOKE_IVOR0_OFF + STRIDE_SIZE * 11) ;\ + RESTORE_SPR(SPRN_IVOR12, BOOKE_IVOR0_OFF + STRIDE_SIZE * 12) ;\ + RESTORE_SPR(SPRN_IVOR13, BOOKE_IVOR0_OFF + STRIDE_SIZE * 13) ;\ + RESTORE_SPR(SPRN_IVOR14, BOOKE_IVOR0_OFF + STRIDE_SIZE * 14) ;\ + RESTORE_SPR(SPRN_IVOR15, BOOKE_IVOR0_OFF + STRIDE_SIZE * 15) ;\ + RESTORE_SPR(SPRN_IVOR35, BOOKE_IVOR0_OFF + STRIDE_SIZE * 35) ;\ + RESTORE_SPR(SPRN_IVOR36, BOOKE_IVOR0_OFF + STRIDE_SIZE * 36) ;\ + RESTORE_SPR(SPRN_IVOR37, BOOKE_IVOR0_OFF + STRIDE_SIZE * 37) ;\ + RESTORE_SPR(SPRN_IVOR38, BOOKE_IVOR0_OFF + STRIDE_SIZE * 38) ;\ + RESTORE_SPR(SPRN_IVOR39, BOOKE_IVOR0_OFF + STRIDE_SIZE * 39) ;\ + RESTORE_SPR(SPRN_IVOR40, BOOKE_IVOR0_OFF + STRIDE_SIZE * 40) ;\ + RESTORE_SPR(SPRN_IVOR41, BOOKE_IVOR0_OFF + STRIDE_SIZE * 41) + +/* reset time base to prevent from overflow */ +#define DELAY(count) \ + li r3, count; \ + li r4, 0; \ + mtspr SPRN_TBWL, r4; \ +101: mfspr r4, SPRN_TBRL; \ + cmpw r4, r3; \ + blt 101b + +#define FSL_DIS_ALL_IRQ \ + mfmsr r8; \ + rlwinm r8, r8, 0, ~MSR_CE; \ + rlwinm r8, r8, 0, ~MSR_ME; \ + rlwinm r8, r8, 0, ~MSR_EE; \ + rlwinm r8, r8, 0, ~MSR_DE; \ + mtmsr r8; \ + isync + +#ifndef CONFIG_PPC_E500MC +#define SS_TB 0x00 +#define SS_HID 0x08 /* 2 HIDs */ +#define SS_IAC 0x10 /* 2 IACs */ +#define SS_DAC 0x18 /* 2 DACs */ +#define SS_DBCR 0x20 /* 3 DBCRs */ +#define SS_PID 0x2c /* 3 PIDs */ +#define SS_SPRG 0x38 /* 8 SPRGs */ +#define SS_IVOR 0x58 /* 20 interrupt vectors */ +#define SS_TCR 0xa8 +#define SS_BUCSR 0xac +#define SS_L1CSR 0xb0 /* 2 L1CSRs */ +#define SS_MSR 0xb8 +#define SS_USPRG 0xbc +#define SS_GPREG 0xc0 /* r12-r31 */ +#define SS_LR 0x110 +#define SS_CR 0x114 +#define SS_SP 0x118 +#define SS_CURRENT 0x11c +#define SS_IVPR 0x120 +#define SS_BPTR 0x124 + + +#define STATE_SAVE_SIZE 0x128 + + .section .data + .align 5 +mpc85xx_sleep_save_area: + .space STATE_SAVE_SIZE +ccsrbase_low: + .long 0 +ccsrbase_high: + .long 0 +powmgtreq: + .long 0 + + .section .text + .align 12 + + /* + * r3 = high word of physical address of CCSR + * r4 = low word of physical address of CCSR + * r5 = JOG or deep sleep request + * JOG-0x00200000, deep sleep-0x00100000 + */ +_GLOBAL(mpc85xx_enter_deep_sleep) + lis r6, ccsrbase_low@ha + stw r4, ccsrbase_low@l(r6) + lis r6, ccsrbase_high@ha + stw r3, ccsrbase_high@l(r6) + + lis r6, powmgtreq@ha + stw r5, powmgtreq@l(r6) + + lis r10, mpc85xx_sleep_save_area@h + ori r10, r10, mpc85xx_sleep_save_area@l + + mfspr r5, SPRN_HID0 + mfspr r6, SPRN_HID1 + + stw r5, SS_HID+0(r10) + stw r6, SS_HID+4(r10) + + mfspr r4, SPRN_IAC1 + mfspr r5, SPRN_IAC2 + mfspr r6, SPRN_DAC1 + mfspr r7, SPRN_DAC2 + + stw r4, SS_IAC+0(r10) + stw r5, SS_IAC+4(r10) + stw r6, SS_DAC+0(r10) + stw r7, SS_DAC+4(r10) + + mfspr r4, SPRN_DBCR0 + mfspr r5, SPRN_DBCR1 + mfspr r6, SPRN_DBCR2 + + stw r4, SS_DBCR+0(r10) + stw r5, SS_DBCR+4(r10) + stw r6, SS_DBCR+8(r10) + + mfspr r4, SPRN_PID0 + mfspr r5, SPRN_PID1 + mfspr r6, SPRN_PID2 + + stw r4, SS_PID+0(r10) + stw r5, SS_PID+4(r10) + stw r6, SS_PID+8(r10) + + mfspr r4, SPRN_SPRG0 + mfspr r5, SPRN_SPRG1 + mfspr r6, SPRN_SPRG2 + mfspr r7, SPRN_SPRG3 + + stw r4, SS_SPRG+0x00(r10) + stw r5, SS_SPRG+0x04(r10) + stw r6, SS_SPRG+0x08(r10) + stw r7, SS_SPRG+0x0c(r10) + + mfspr r4, SPRN_SPRG4 + mfspr r5, SPRN_SPRG5 + mfspr r6, SPRN_SPRG6 + mfspr r7, SPRN_SPRG7 + + stw r4, SS_SPRG+0x10(r10) + stw r5, SS_SPRG+0x14(r10) + stw r6, SS_SPRG+0x18(r10) + stw r7, SS_SPRG+0x1c(r10) + + mfspr r4, SPRN_IVPR + stw r4, SS_IVPR(r10) + + mfspr r4, SPRN_IVOR0 + mfspr r5, SPRN_IVOR1 + mfspr r6, SPRN_IVOR2 + mfspr r7, SPRN_IVOR3 + + stw r4, SS_IVOR+0x00(r10) + stw r5, SS_IVOR+0x04(r10) + stw r6, SS_IVOR+0x08(r10) + stw r7, SS_IVOR+0x0c(r10) + + mfspr r4, SPRN_IVOR4 + mfspr r5, SPRN_IVOR5 + mfspr r6, SPRN_IVOR6 + mfspr r7, SPRN_IVOR7 + + stw r4, SS_IVOR+0x10(r10) + stw r5, SS_IVOR+0x14(r10) + stw r6, SS_IVOR+0x18(r10) + stw r7, SS_IVOR+0x1c(r10) + + mfspr r4, SPRN_IVOR8 + mfspr r5, SPRN_IVOR9 + mfspr r6, SPRN_IVOR10 + mfspr r7, SPRN_IVOR11 + + stw r4, SS_IVOR+0x20(r10) + stw r5, SS_IVOR+0x24(r10) + stw r6, SS_IVOR+0x28(r10) + stw r7, SS_IVOR+0x2c(r10) + + mfspr r4, SPRN_IVOR12 + mfspr r5, SPRN_IVOR13 + mfspr r6, SPRN_IVOR14 + mfspr r7, SPRN_IVOR15 + + stw r4, SS_IVOR+0x30(r10) + stw r5, SS_IVOR+0x34(r10) + stw r6, SS_IVOR+0x38(r10) + stw r7, SS_IVOR+0x3c(r10) + + mfspr r4, SPRN_IVOR32 + mfspr r5, SPRN_IVOR33 + mfspr r6, SPRN_IVOR34 + mfspr r7, SPRN_IVOR35 + + stw r4, SS_IVOR+0x40(r10) + stw r5, SS_IVOR+0x44(r10) + stw r6, SS_IVOR+0x48(r10) + stw r7, SS_IVOR+0x4c(r10) + + mfspr r4, SPRN_TCR + mfspr r5, SPRN_BUCSR + mfspr r6, SPRN_L1CSR0 + mfspr r7, SPRN_L1CSR1 + mfspr r8, SPRN_USPRG0 + + stw r4, SS_TCR(r10) + stw r5, SS_BUCSR(r10) + stw r6, SS_L1CSR+0(r10) + stw r7, SS_L1CSR+4(r10) + stw r8, SS_USPRG+0(r10) + + stmw r12, SS_GPREG(r10) + + mfmsr r4 + mflr r5 + mfcr r6 + + stw r4, SS_MSR(r10) + stw r5, SS_LR(r10) + stw r6, SS_CR(r10) + stw r1, SS_SP(r10) + stw r2, SS_CURRENT(r10) + +1: mftbu r4 + mftb r5 + mftbu r6 + cmpw r4, r6 + bne 1b + + stw r4, SS_TB+0(r10) + stw r5, SS_TB+4(r10) + + lis r5, ccsrbase_low@ha + lwz r4, ccsrbase_low@l(r5) + lis r5, ccsrbase_high@ha + lwz r3, ccsrbase_high@l(r5) + + /* Disable machine checks and critical exceptions */ + mfmsr r5 + rlwinm r5, r5, 0, ~MSR_CE + rlwinm r5, r5, 0, ~MSR_ME + mtmsr r5 + isync + + /* Use TLB1[15] to map the CCSR at 0xf0000000 */ + lis r5, 0x100f + mtspr SPRN_MAS0, r5 + lis r5, 0xc000 + ori r5, r5, 0x0500 + mtspr SPRN_MAS1, r5 + lis r5, 0xf000 + ori r5, r5, 0x000a + mtspr SPRN_MAS2, r5 + rlwinm r5, r4, 0, 0xfffff000 + ori r5, r5, 0x0005 + mtspr SPRN_MAS3, r5 + mtspr SPRN_MAS7, r3 + isync + tlbwe + isync + + lis r3, 0xf000 + lwz r4, 0x20(r3) + stw r4, SS_BPTR(r10) + + lis r3, 0xf002 /* L2 cache controller at CCSR+0x20000 */ + bl flush_disable_L2 + bl __flush_disable_L1 + + /* Enable I-cache, so as not to upset the bus + * with our loop. + */ + + mfspr r4, SPRN_L1CSR1 + ori r4, r4, 1 + mtspr SPRN_L1CSR1, r4 + isync + + /* Set boot page translation */ + lis r3, 0xf000 + lis r4, (mpc85xx_deep_resume - PAGE_OFFSET)@h + ori r4, r4, (mpc85xx_deep_resume - PAGE_OFFSET)@l + rlwinm r4, r4, 20, 0x000fffff + oris r4, r4, 0x8000 + stw r4, 0x20(r3) + lwz r4, 0x20(r3) /* read-back to flush write */ + twi 0, r4, 0 + isync + + /* Disable the decrementer */ + mfspr r4, SPRN_TCR + rlwinm r4, r4, 0, ~TCR_DIE + mtspr SPRN_TCR, r4 + + mfspr r4, SPRN_TSR + oris r4, r4, TSR_DIS@h + mtspr SPRN_TSR, r4 + + /* set PMRCCR[VRCNT] to wait power stable for 40ms */ + lis r3, 0xf00e + lwz r4, 0x84(r3) + clrlwi r4, r4, 16 + oris r4, r4, 0x12a3 + stw r4, 0x84(r3) + lwz r4, 0x84(r3) + + /* set deep sleep bit in POWMGTSCR */ + lis r3, powmgtreq@ha + lwz r8, powmgtreq@l(r3) + + lis r3, 0xf00e + lwz r4, 0x80(r3) + or r4, r4, r8 + stw r4, 0x80(r3) + lwz r4, 0x80(r3) /* read-back to flush write */ + twi 0, r4, 0 + isync + + mftb r5 +1: /* spin until either we enter deep sleep, or the sleep process is + * aborted due to a pending wakeup event. Wait some time between + * accesses, so we don't flood the bus and prevent the pmc from + * detecting an idle system. + */ + + mftb r4 + subf r7, r5, r4 + cmpwi r7, 1000 + blt 1b + mr r5, r4 + + lwz r6, 0x80(r3) + andis. r6, r6, 0x0010 + bne 1b + b 2f + +2: mfspr r4, SPRN_PIR + andi. r4, r4, 1 +99: bne 99b + + /* Establish a temporary 64MB 0->0 mapping in TLB1[1]. */ + lis r4, 0x1001 + mtspr SPRN_MAS0, r4 + lis r4, 0xc000 + ori r4, r4, 0x0800 + mtspr SPRN_MAS1, r4 + li r4, 0 + mtspr SPRN_MAS2, r4 + li r4, 0x0015 + mtspr SPRN_MAS3, r4 + li r4, 0 + mtspr SPRN_MAS7, r4 + isync + tlbwe + isync + + lis r3, (3f - PAGE_OFFSET)@h + ori r3, r3, (3f - PAGE_OFFSET)@l + mtctr r3 + bctr + + /* Locate the resume vector in the last word of the current page. */ + . = mpc85xx_enter_deep_sleep + 0xffc +mpc85xx_deep_resume: + b 2b + +3: + /* Restore the contents of TLB1[0]. It is assumed that it covers + * the currently executing code and the sleep save area, and that + * it does not alias our temporary mapping (which is at virtual zero). + */ + lis r3, (TLBCAM - PAGE_OFFSET)@h + ori r3, r3, (TLBCAM - PAGE_OFFSET)@l + + lwz r4, 0(r3) + lwz r5, 4(r3) + lwz r6, 8(r3) + lwz r7, 12(r3) + lwz r8, 16(r3) + + mtspr SPRN_MAS0, r4 + mtspr SPRN_MAS1, r5 + mtspr SPRN_MAS2, r6 + mtspr SPRN_MAS3, r7 + mtspr SPRN_MAS7, r8 + + isync + tlbwe + isync + + /* Access the ccsrbase address with TLB1[0] */ + lis r5, ccsrbase_low@ha + lwz r4, ccsrbase_low@l(r5) + lis r5, ccsrbase_high@ha + lwz r3, ccsrbase_high@l(r5) + + /* Use TLB1[15] to map the CCSR at 0xf0000000 */ + lis r5, 0x100f + mtspr SPRN_MAS0, r5 + lis r5, 0xc000 + ori r5, r5, 0x0500 + mtspr SPRN_MAS1, r5 + lis r5, 0xf000 + ori r5, r5, 0x000a + mtspr SPRN_MAS2, r5 + rlwinm r5, r4, 0, 0xfffff000 + ori r5, r5, 0x0005 + mtspr SPRN_MAS3, r5 + mtspr SPRN_MAS7, r3 + isync + tlbwe + isync + + lis r3, 0xf002 /* L2 cache controller at CCSR+0x20000 */ + bl invalidate_enable_L2 + + /* Access the MEM(r10) with TLB1[0] */ + lis r10, mpc85xx_sleep_save_area@h + ori r10, r10, mpc85xx_sleep_save_area@l + + lis r3, 0xf000 + lwz r4, SS_BPTR(r10) + stw r4, 0x20(r3) /* restore BPTR */ + + /* Program shift running space to PAGE_OFFSET */ + mfmsr r3 + lis r4, 1f@h + ori r4, r4, 1f@l + + mtsrr1 r3 + mtsrr0 r4 + rfi + +1: /* Restore the rest of TLB1, in ascending order so that + * the TLB1[1] gets invalidated first. + * + * XXX: It's better to invalidate the temporary mapping + * TLB1[15] for CCSR before restore any TLB1 entry include 0. + */ + lis r4, 0x100f + mtspr SPRN_MAS0, r4 + lis r4, 0 + mtspr SPRN_MAS1, r4 + isync + tlbwe + isync + + lis r3, (TLBCAM + 5*4 - 4)@h + ori r3, r3, (TLBCAM + 5*4 - 4)@l + li r4, 15 + mtctr r4 + +2: + lwz r5, 4(r3) + lwz r6, 8(r3) + lwz r7, 12(r3) + lwz r8, 16(r3) + lwzu r9, 20(r3) + + mtspr SPRN_MAS0, r5 + mtspr SPRN_MAS1, r6 + mtspr SPRN_MAS2, r7 + mtspr SPRN_MAS3, r8 + mtspr SPRN_MAS7, r9 + + isync + tlbwe + isync + bdnz 2b + + lis r10, mpc85xx_sleep_save_area@h + ori r10, r10, mpc85xx_sleep_save_area@l + + lwz r5, SS_HID+0(r10) + lwz r6, SS_HID+4(r10) + + isync + mtspr SPRN_HID0, r5 + isync + + msync + mtspr SPRN_HID1, r6 + isync + + lwz r4, SS_IAC+0(r10) + lwz r5, SS_IAC+4(r10) + lwz r6, SS_DAC+0(r10) + lwz r7, SS_DAC+4(r10) + + mtspr SPRN_IAC1, r4 + mtspr SPRN_IAC2, r5 + mtspr SPRN_DAC1, r6 + mtspr SPRN_DAC2, r7 + + lwz r4, SS_DBCR+0(r10) + lwz r5, SS_DBCR+4(r10) + lwz r6, SS_DBCR+8(r10) + + mtspr SPRN_DBCR0, r4 + mtspr SPRN_DBCR1, r5 + mtspr SPRN_DBCR2, r6 + + lwz r4, SS_PID+0(r10) + lwz r5, SS_PID+4(r10) + lwz r6, SS_PID+8(r10) + + mtspr SPRN_PID0, r4 + mtspr SPRN_PID1, r5 + mtspr SPRN_PID2, r6 + + lwz r4, SS_SPRG+0x00(r10) + lwz r5, SS_SPRG+0x04(r10) + lwz r6, SS_SPRG+0x08(r10) + lwz r7, SS_SPRG+0x0c(r10) + + mtspr SPRN_SPRG0, r4 + mtspr SPRN_SPRG1, r5 + mtspr SPRN_SPRG2, r6 + mtspr SPRN_SPRG3, r7 + + lwz r4, SS_SPRG+0x10(r10) + lwz r5, SS_SPRG+0x14(r10) + lwz r6, SS_SPRG+0x18(r10) + lwz r7, SS_SPRG+0x1c(r10) + + mtspr SPRN_SPRG4, r4 + mtspr SPRN_SPRG5, r5 + mtspr SPRN_SPRG6, r6 + mtspr SPRN_SPRG7, r7 + + lwz r4, SS_IVPR(r10) + mtspr SPRN_IVPR, r4 + + lwz r4, SS_IVOR+0x00(r10) + lwz r5, SS_IVOR+0x04(r10) + lwz r6, SS_IVOR+0x08(r10) + lwz r7, SS_IVOR+0x0c(r10) + + mtspr SPRN_IVOR0, r4 + mtspr SPRN_IVOR1, r5 + mtspr SPRN_IVOR2, r6 + mtspr SPRN_IVOR3, r7 + + lwz r4, SS_IVOR+0x10(r10) + lwz r5, SS_IVOR+0x14(r10) + lwz r6, SS_IVOR+0x18(r10) + lwz r7, SS_IVOR+0x1c(r10) + + mtspr SPRN_IVOR4, r4 + mtspr SPRN_IVOR5, r5 + mtspr SPRN_IVOR6, r6 + mtspr SPRN_IVOR7, r7 + + lwz r4, SS_IVOR+0x20(r10) + lwz r5, SS_IVOR+0x24(r10) + lwz r6, SS_IVOR+0x28(r10) + lwz r7, SS_IVOR+0x2c(r10) + + mtspr SPRN_IVOR8, r4 + mtspr SPRN_IVOR9, r5 + mtspr SPRN_IVOR10, r6 + mtspr SPRN_IVOR11, r7 + + lwz r4, SS_IVOR+0x30(r10) + lwz r5, SS_IVOR+0x34(r10) + lwz r6, SS_IVOR+0x38(r10) + lwz r7, SS_IVOR+0x3c(r10) + + mtspr SPRN_IVOR12, r4 + mtspr SPRN_IVOR13, r5 + mtspr SPRN_IVOR14, r6 + mtspr SPRN_IVOR15, r7 + + lwz r4, SS_IVOR+0x40(r10) + lwz r5, SS_IVOR+0x44(r10) + lwz r6, SS_IVOR+0x48(r10) + lwz r7, SS_IVOR+0x4c(r10) + + mtspr SPRN_IVOR32, r4 + mtspr SPRN_IVOR33, r5 + mtspr SPRN_IVOR34, r6 + mtspr SPRN_IVOR35, r7 + + lwz r4, SS_TCR(r10) + lwz r5, SS_BUCSR(r10) + lwz r6, SS_L1CSR+0(r10) + lwz r7, SS_L1CSR+4(r10) + lwz r8, SS_USPRG+0(r10) + + mtspr SPRN_TCR, r4 + mtspr SPRN_BUCSR, r5 + + msync + isync + mtspr SPRN_L1CSR0, r6 + isync + + mtspr SPRN_L1CSR1, r7 + isync + + mtspr SPRN_USPRG0, r8 + + lmw r12, SS_GPREG(r10) + + lwz r1, SS_SP(r10) + lwz r2, SS_CURRENT(r10) + lwz r4, SS_MSR(r10) + lwz r5, SS_LR(r10) + lwz r6, SS_CR(r10) + + msync + mtmsr r4 + isync + + mtlr r5 + mtcr r6 + + li r4, 0 + mtspr SPRN_TBWL, r4 + + lwz r4, SS_TB+0(r10) + lwz r5, SS_TB+4(r10) + + mtspr SPRN_TBWU, r4 + mtspr SPRN_TBWL, r5 + + lis r3, 1 + mtdec r3 + + blr + +#else /* CONFIG_PPC_E500MC */ + + .section .data + .align 6 +regs_buffer: + .space BUFFER_SIZE + + .section .text +/* + * Save CPU registers + * r3 : the base address of the buffer which stores the values of registers + */ +e5500_cpu_state_save: + /* store the base address to r10 */ + mr r10, r3 + + SAVE_ALL_GPR + SAVE_ALL_SPRG + SAVE_ALL_IVOR + + SAVE_SPR(SPRN_IVPR, BOOKE_IVPR_OFF) + SAVE_SPR(SPRN_PID0, BOOKE_PID0_OFF) + SAVE_SPR(SPRN_EPCR, BOOKE_EPCR_OFF) + SAVE_SPR(SPRN_HID0, BOOKE_HID0_OFF) + SAVE_SPR(SPRN_PIR, BOOKE_PIR_OFF) + SAVE_SPR(SPRN_BUCSR, BOOKE_BUCSR_OFF) +1: + mfspr r5, SPRN_TBRU + mfspr r4, SPRN_TBRL + SAVE_GPR(r5, BOOKE_TBU_OFF) + SAVE_GPR(r4, BOOKE_TBL_OFF) + mfspr r3, SPRN_TBRU + cmpw r3, r5 + bne 1b + + blr + +/* + * Restore CPU registers + * r3 : the base address of the buffer which stores the values of registers + */ +e5500_cpu_state_restore: + /* store the base address to r10 */ + mr r10, r3 + + RESTORE_ALL_GPR + RESTORE_ALL_SPRG + RESTORE_ALL_IVOR + + RESTORE_SPR(SPRN_IVPR, BOOKE_IVPR_OFF) + RESTORE_SPR(SPRN_PID0, BOOKE_PID0_OFF) + RESTORE_SPR(SPRN_EPCR, BOOKE_EPCR_OFF) + RESTORE_SPR(SPRN_HID0, BOOKE_HID0_OFF) + RESTORE_SPR(SPRN_PIR, BOOKE_PIR_OFF) + RESTORE_SPR(SPRN_BUCSR, BOOKE_BUCSR_OFF) + + li r0, 0 + mtspr SPRN_TBWL, r0 + RESTORE_SPR(SPRN_TBWU, BOOKE_TBU_OFF) + RESTORE_SPR(SPRN_TBWL, BOOKE_TBL_OFF) + + blr + +#define CPC_CPCCSR0 0x0 +#define CPC_CPCCSR0_CPCFL 0x800 + +/* + * Flush the CPC cache. + * r3 : the base address of CPC + */ +flush_cpc_cache: + lwz r6, CPC_CPCCSR0(r3) + ori r6, r6, CPC_CPCCSR0_CPCFL + stw r6, CPC_CPCCSR0(r3) + sync + + /* Wait until completing the flush */ +1: lwz r6, CPC_CPCCSR0(r3) + andi. r6, r6, CPC_CPCCSR0_CPCFL + bne 1b + + blr + +/* + * the last stage to enter deep sleep + * + */ + .align 6 +_GLOBAL(fsl_dp_enter_low) +deepsleep_start: + LOAD_REG_ADDR(r9, buf_tmp) + /* save the return address and MSR */ + mflr r8 + PPC_STL r8, 0(r9) + mfmsr r8 + PPC_STL r8, 8(r9) + mfspr r8, SPRN_TCR + PPC_STL r8, 16(r9) + mfcr r8 + PPC_STL r8, 24(r9) + li r8, 0 + mtspr SPRN_TCR, r8 + + /* save the parameters */ + PPC_STL r3, 32(r9) + PPC_STL r4, 40(r9) + PPC_STL r5, 48(r9) + PPC_STL r6, 56(r9) + + LOAD_REG_ADDR(r3, regs_buffer) + bl e5500_cpu_state_save + + /* restore the parameters */ + LOAD_REG_ADDR(r9, buf_tmp) + PPC_LL r31, 32(r9) + PPC_LL r30, 40(r9) + PPC_LL r29, 48(r9) + PPC_LL r28, 56(r9) + + /* flush caches inside CPU */ + LOAD_REG_ADDR(r3, cur_cpu_spec) + PPC_LL r3, 0(r3) + PPC_LL r3, CPU_FLUSH_CACHES(r3) + PPC_LCMPI 0, r3, 0 + beq 6f +#ifdef CONFIG_PPC64 + PPC_LL r3, 0(r3) +#endif + mtctr r3 + bctrl +6: + /* Flush the CPC cache */ +#define CPC_OFFSET 0x10000 + mr r3, r31 + addis r3, r3, CPC_OFFSET@h + bl flush_cpc_cache + + /* prefecth TLB */ +#define CCSR_GPIO1_GPDAT 0x130008 +#define CCSR_GPIO1_GPDAT_29 0x4 + LOAD_REG_IMMEDIATE(r11, CCSR_GPIO1_GPDAT) + add r11, r31, r11 + lwz r10, 0(r11) + +#define CCSR_RCPM_PCPH15SETR 0xe20b4 +#define CCSR_RCPM_PCPH15SETR_CORE0 0x1 + LOAD_REG_IMMEDIATE(r12, CCSR_RCPM_PCPH15SETR) + add r12, r31, r12 + lwz r10, 0(r12) + +#define CCSR_DDR_SDRAM_CFG_2 0x8114 +#define CCSR_DDR_SDRAM_CFG_2_FRC_SR 0x80000000 + LOAD_REG_IMMEDIATE(r13, CCSR_DDR_SDRAM_CFG_2) + add r13, r31, r13 + lwz r10, 0(r13) + +#define DCSR_EPU_EPGCR 0x000 +#define DCSR_EPU_EPGCR_GCE 0x80000000 + li r14, DCSR_EPU_EPGCR + add r14, r30, r14 + lwz r10, 0(r14) + +#define DCSR_EPU_EPECR15 0x33C +#define DCSR_EPU_EPECR15_IC0 0x80000000 + li r15, DCSR_EPU_EPECR15 + add r15, r30, r15 + lwz r10, 0(r15) + +#define CCSR_SCFG_QMIFRSTCR 0xfc40c +#define CCSR_SCFG_QMIFRSTCR_QMIFRST 0x80000000 + LOAD_REG_IMMEDIATE(r16, CCSR_SCFG_QMIFRSTCR) + add r16, r31, r16 + lwz r10, 0(r16) + +/* + * There are two kind of register maps, one for T1040QDS and + * the other for T104xRDB. + */ +#define T104XRDB_CPLD_MISCCSR 0x17 +#define T104XRDB_CPLD_MISCCSR_SLEEPEN 0x40 +#define T1040QDS_QIXIS_PWR_CTL2 0x21 +#define T1040QDS_QIXIS_PWR_CTL2_PCTL 0x2 + li r3, T1040QDS_QIXIS_PWR_CTL2 + PPC_LCMPI 0, r28, T1040QDS_TETRA_FLAG + beq 20f + li r3, T104XRDB_CPLD_MISCCSR +20: add r29, r29, r3 + lbz r10, 0(r29) + sync + + LOAD_REG_ADDR(r8, deepsleep_start) + LOAD_REG_ADDR(r9, deepsleep_end) + + /* prefecth code to cache so that executing code after disable DDR */ +1: icbtls 2, 0, r8 + addi r8, r8, 64 + cmpw r8, r9 + blt 1b + sync + + FSL_DIS_ALL_IRQ + + /* + * Place DDR controller in self refresh mode. + * From here on, can't access DDR any more. + */ + lwz r10, 0(r13) + oris r10, r10, CCSR_DDR_SDRAM_CFG_2_FRC_SR@h + stw r10, 0(r13) + lwz r10, 0(r13) + sync + + DELAY(500) + + /* + * Enable deep sleep signals by write external CPLD/FPGA register. + * The bootloader will disable them when wakeup from deep sleep. + */ + lbz r10, 0(r29) + li r3, T1040QDS_QIXIS_PWR_CTL2_PCTL + PPC_LCMPI 0, r28, T1040QDS_TETRA_FLAG + beq 22f + li r3, T104XRDB_CPLD_MISCCSR_SLEEPEN +22: or r10, r10, r3 + stb r10, 0(r29) + lbz r10, 0(r29) + sync + + /* + * Set GPIO1_29 to lock the signal MCKE down during deep sleep. + * The bootloader will clear it when wakeup. + */ + lwz r10, 0(r11) + ori r10, r10, CCSR_GPIO1_GPDAT_29 + stw r10, 0(r11) + lwz r10, 0(r11) + + DELAY(100) + + /* Reset QMan system bus interface */ + lwz r10, 0(r16) + oris r10, r10, CCSR_SCFG_QMIFRSTCR_QMIFRST@h + stw r10, 0(r16) + lwz r10, 0(r16) + + /* Enable all EPU Counters */ + li r10, 0 + oris r10, r10, DCSR_EPU_EPGCR_GCE@h + stw r10, 0(r14) + lwz r10, 0(r14) + + /* Enable SCU15 to trigger on RCPM Concentrator 0 */ + lwz r10, 0(r15) + oris r10, r10, DCSR_EPU_EPECR15_IC0@h + stw r10, 0(r15) + lwz r10, 0(r15) + + /* put Core0 in PH15 mode, trigger EPU FSM */ + lwz r10, 0(r12) + ori r10, r10, CCSR_RCPM_PCPH15SETR_CORE0 + stw r10, 0(r12) +2: + b 2b + + /* + * Leave some space to prevent prefeching instruction + * beyond deepsleep_end. The space also can be used as heap. + */ +buf_tmp: + .space 128 + .align 6 +deepsleep_end: + + .align 12 +#ifdef CONFIG_PPC32 +_GLOBAL(fsl_booke_deep_sleep_resume) + /* disable interrupts */ + FSL_DIS_ALL_IRQ + +#define ENTRY_DEEPSLEEP_SETUP +#define ENTRY_MAPPING_BOOT_SETUP +#include <../../kernel/85xx_entry_mapping.S> +#undef ENTRY_DEEPSLEEP_SETUP +#undef ENTRY_MAPPING_BOOT_SETUP + + li r3, 0 + mfspr r4, SPRN_PIR + bl call_setup_cpu + + /* Load each CAM entry */ + LOAD_REG_ADDR(r3, tlbcam_index) + lwz r3, 0(r3) + mtctr r3 + li r9, 0 +3: mr r3, r9 + bl loadcam_entry + addi r9, r9, 1 + bdnz 3b + + /* restore cpu registers */ + LOAD_REG_ADDR(r3, regs_buffer) + bl e5500_cpu_state_restore + + /* restore return address */ + LOAD_REG_ADDR(r3, buf_tmp) + lwz r4, 16(r3) + mtspr SPRN_TCR, r4 + lwz r4, 0(r3) + mtlr r4 + lwz r4, 8(r3) + mtmsr r4 + lwz r4, 24(r3) + mtcr r4 + + blr + +#else /* CONFIG_PPC32 */ + +_GLOBAL(fsl_booke_deep_sleep_resume) + /* disable interrupts */ + FSL_DIS_ALL_IRQ + + /* switch to 64-bit mode */ + bl .enable_64b_mode + + /* set TOC pointer */ + bl .relative_toc + + /* setup initial TLBs, switch to kernel space ... */ + bl .start_initialization_book3e + + /* address space changed, set TOC pointer again */ + bl .relative_toc + + /* call a cpu state restore handler */ + LOAD_REG_ADDR(r23, cur_cpu_spec) + ld r23,0(r23) + ld r23,CPU_SPEC_RESTORE(r23) + cmpdi 0,r23,0 + beq 1f + ld r23,0(r23) + mtctr r23 + bctrl +1: + LOAD_REG_ADDR(r3, regs_buffer) + bl e5500_cpu_state_restore + + /* Load each CAM entry */ + LOAD_REG_ADDR(r3, tlbcam_index) + lwz r3, 0(r3) + mtctr r3 + li r0, 0 +3: mr r3, r0 + bl loadcam_entry + addi r0, r0, 1 + bdnz 3b + + /* restore return address */ + LOAD_REG_ADDR(r3, buf_tmp) + ld r4, 16(r3) + mtspr SPRN_TCR, r4 + ld r4, 0(r3) + mtlr r4 + ld r4, 8(r3) + mtmsr r4 + ld r4, 24(r3) + mtcr r4 + + blr + +#endif /* CONFIG_PPC32 */ + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/platforms/86xx/Kconfig linux-imx-phytec/arch/powerpc/platforms/86xx/Kconfig --- linux-6.1.55/arch/powerpc/platforms/86xx/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/platforms/86xx/Kconfig 2024-06-19 12:33:58.896202758 +0200 @@ -5,6 +5,7 @@ depends on PPC_BOOK3S_32 select FSL_SOC select ALTIVEC + select FSL_PMC if SUSPEND help The Freescale E600 SoCs have 74xx cores. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/sysdev/fsl_pmc.c linux-imx-phytec/arch/powerpc/sysdev/fsl_pmc.c --- linux-6.1.55/arch/powerpc/sysdev/fsl_pmc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/sysdev/fsl_pmc.c 2024-06-19 12:33:58.928203305 +0200 @@ -16,54 +16,192 @@ #include #include #include +#include +#include + +#include +#include +#include struct pmc_regs { __be32 devdisr; __be32 devdisr2; - __be32 :32; - __be32 :32; - __be32 pmcsr; -#define PMCSR_SLP (1 << 17) + __be32 res1; + __be32 res2; + __be32 powmgtcsr; +#define POWMGTCSR_SLP 0x00020000 +#define POWMGTCSR_DPSLP 0x00100000 +#define POWMGTCSR_LOSSLESS 0x00400000 + __be32 res3[2]; + __be32 pmcdr; }; -static struct device *pmc_dev; static struct pmc_regs __iomem *pmc_regs; +static unsigned int pmc_flag; + +#define PMC_SLEEP 0x1 +#define PMC_DEEP_SLEEP 0x2 +#define PMC_LOSSLESS 0x4 + +/** + * mpc85xx_pmc_set_wake - enable devices as wakeup event source + * @dev: a device affected + * @enable: True to enable event generation; false to disable + * + * This enables the device as a wakeup event source, or disables it. + * + * RETURN VALUE: + * 0 is returned on success. + * -EINVAL is returned if device is not supposed to wake up the system. + * -ENODEV is returned if PMC is unavailable. + * Error code depending on the platform is returned if both the platform and + * the native mechanism fail to enable the generation of wake-up events + */ +int mpc85xx_pmc_set_wake(struct device *dev, bool enable) +{ + int ret = 0; + struct device_node *clk_np; + const u32 *prop; + u32 pmcdr_mask; + + if (!pmc_regs) { + dev_err(dev, "%s: PMC is unavailable\n", __func__); + return -ENODEV; + } + + if (enable && !device_may_wakeup(dev)) + return -EINVAL; + + clk_np = of_parse_phandle(dev->of_node, "fsl,pmc-handle", 0); + if (!clk_np) + return -EINVAL; + + prop = of_get_property(clk_np, "fsl,pmcdr-mask", NULL); + if (!prop) { + ret = -EINVAL; + goto out; + } + pmcdr_mask = be32_to_cpup(prop); + + if (enable) + /* clear to enable clock in low power mode */ + clrbits32(&pmc_regs->pmcdr, pmcdr_mask); + else + setbits32(&pmc_regs->pmcdr, pmcdr_mask); + +out: + of_node_put(clk_np); + return ret; +} +EXPORT_SYMBOL_GPL(mpc85xx_pmc_set_wake); + +/** + * mpc85xx_pmc_set_lossless_ethernet - enable lossless ethernet + * in (deep) sleep mode + * @enable: True to enable event generation; false to disable + */ +void mpc85xx_pmc_set_lossless_ethernet(int enable) +{ + if (pmc_flag & PMC_LOSSLESS) { + if (enable) + setbits32(&pmc_regs->powmgtcsr, POWMGTCSR_LOSSLESS); + else + clrbits32(&pmc_regs->powmgtcsr, POWMGTCSR_LOSSLESS); + } +} +EXPORT_SYMBOL_GPL(mpc85xx_pmc_set_lossless_ethernet); static int pmc_suspend_enter(suspend_state_t state) { - int ret; + int ret = 0; + int result; + + switch (state) { +#ifdef CONFIG_PPC_85xx + case PM_SUSPEND_MEM: +#ifdef CONFIG_SPE + enable_kernel_spe(); +#endif +#ifdef CONFIG_PPC_FPU + enable_kernel_fp(); +#endif + + pr_debug("%s: Entering deep sleep\n", __func__); + + local_irq_disable(); + mpc85xx_enter_deep_sleep(get_immrbase(), POWMGTCSR_DPSLP); + + pr_debug("%s: Resumed from deep sleep\n", __func__); + break; +#endif + + case PM_SUSPEND_STANDBY: + local_irq_disable(); + flush_dcache_L1(); + + setbits32(&pmc_regs->powmgtcsr, POWMGTCSR_SLP); + /* At this point, the CPU is asleep. */ + + /* Upon resume, wait for SLP bit to be clear. */ + result = spin_event_timeout( + (in_be32(&pmc_regs->powmgtcsr) & POWMGTCSR_SLP) == 0, + 10000, 10); + if (!result) { + pr_err("%s: timeout waiting for SLP bit " + "to be cleared\n", __func__); + ret = -ETIMEDOUT; + } + break; - setbits32(&pmc_regs->pmcsr, PMCSR_SLP); - /* At this point, the CPU is asleep. */ + default: + ret = -EINVAL; - /* Upon resume, wait for SLP bit to be clear. */ - ret = spin_event_timeout((in_be32(&pmc_regs->pmcsr) & PMCSR_SLP) == 0, - 10000, 10) ? 0 : -ETIMEDOUT; - if (ret) - dev_err(pmc_dev, "tired waiting for SLP bit to clear\n"); + } return ret; } static int pmc_suspend_valid(suspend_state_t state) { - if (state != PM_SUSPEND_STANDBY) - return 0; - return 1; + set_pm_suspend_state(state); + + if (((pmc_flag & PMC_SLEEP) && (state == PM_SUSPEND_STANDBY)) || + ((pmc_flag & PMC_DEEP_SLEEP) && (state == PM_SUSPEND_MEM))) + return 1; + + set_pm_suspend_state(PM_SUSPEND_ON); + return 0; +} + +static void pmc_suspend_end(void) +{ + set_pm_suspend_state(PM_SUSPEND_ON); } static const struct platform_suspend_ops pmc_suspend_ops = { .valid = pmc_suspend_valid, .enter = pmc_suspend_enter, + .end = pmc_suspend_end, }; -static int pmc_probe(struct platform_device *ofdev) +static int pmc_probe(struct platform_device *pdev) { - pmc_regs = of_iomap(ofdev->dev.of_node, 0); + struct device_node *np = pdev->dev.of_node; + + pmc_regs = of_iomap(np, 0); if (!pmc_regs) return -ENOMEM; - pmc_dev = &ofdev->dev; + pmc_flag = PMC_SLEEP; + if (of_device_is_compatible(np, "fsl,mpc8536-pmc")) + pmc_flag |= PMC_DEEP_SLEEP; + + if (of_device_is_compatible(np, "fsl,p1022-pmc")) + pmc_flag |= PMC_DEEP_SLEEP | PMC_LOSSLESS; + suspend_set_ops(&pmc_suspend_ops); + set_pm_suspend_state(PM_SUSPEND_ON); + + pr_info("Freescale PMC driver\n"); return 0; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/sysdev/fsl_soc.c linux-imx-phytec/arch/powerpc/sysdev/fsl_soc.c --- linux-6.1.55/arch/powerpc/sysdev/fsl_soc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/sysdev/fsl_soc.c 2024-06-19 12:33:58.932203373 +0200 @@ -41,6 +41,37 @@ extern void init_fec_ioports(struct fs_platform_info*); extern void init_smc_ioports(struct fs_uart_platform_info*); static phys_addr_t immrbase = -1; +static phys_addr_t dcsrbase = -1; + +phys_addr_t get_dcsrbase(void) +{ + struct device_node *np; + const __be32 *prop; + int size; + u32 naddr; + + if (dcsrbase != -1) + return dcsrbase; + + np = of_find_compatible_node(NULL, NULL, "fsl,dcsr"); + if (!np) + return -1; + + prop = of_get_property(np, "#address-cells", &size); + if (prop && size == 4) + naddr = be32_to_cpup(prop); + else + naddr = 2; + + prop = of_get_property(np, "ranges", NULL); + if (prop) + dcsrbase = of_translate_address(np, prop + naddr); + + of_node_put(np); + + return dcsrbase; +} +EXPORT_SYMBOL(get_dcsrbase); phys_addr_t get_immrbase(void) { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/arch/powerpc/sysdev/fsl_soc.h linux-imx-phytec/arch/powerpc/sysdev/fsl_soc.h --- linux-6.1.55/arch/powerpc/sysdev/fsl_soc.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/arch/powerpc/sysdev/fsl_soc.h 2024-06-19 12:33:58.932203373 +0200 @@ -7,6 +7,7 @@ struct spi_device; +extern phys_addr_t get_dcsrbase(void); extern phys_addr_t get_immrbase(void); #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) extern u32 get_brgfreq(void); @@ -44,5 +45,22 @@ void __noreturn fsl_hv_restart(char *cmd); void __noreturn fsl_hv_halt(void); +/* + * Cast the ccsrbar to 64-bit parameter so that the assembly + * code can be compatible with both 32-bit & 36-bit. + */ +extern void mpc85xx_enter_deep_sleep(u64 ccsrbar, u32 powmgtreq); + +#ifdef CONFIG_FSL_PMC +int mpc85xx_pmc_set_wake(struct device *dev, bool enable); +void mpc85xx_pmc_set_lossless_ethernet(int enable); +#else +static inline int mpc85xx_pmc_set_wake(struct device *dev, bool enable) +{ + return -ENODEV; +} +#define mpc85xx_pmc_set_lossless_ethernet(enable) do { } while (0) +#endif + #endif #endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/block/blk-map.c linux-imx-phytec/block/blk-map.c --- linux-6.1.55/block/blk-map.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/block/blk-map.c 2024-06-19 12:33:59.304209734 +0200 @@ -757,6 +757,12 @@ } EXPORT_SYMBOL(blk_rq_unmap_user); +#ifdef CONFIG_AHCI_IMX +extern void *sg_io_buffer_hack; +#else +#define sg_io_buffer_hack NULL +#endif + /** * blk_rq_map_kern - map kernel data to a request, for passthrough requests * @q: request queue where request should be inserted @@ -783,8 +789,13 @@ if (!len || !kbuf) return -EINVAL; +#ifdef CONFIG_AHCI_IMX + if ((kbuf != sg_io_buffer_hack) && (!blk_rq_aligned(q, addr, len) || + object_is_on_stack(kbuf) || blk_queue_may_bounce(q))) +#else if (!blk_rq_aligned(q, addr, len) || object_is_on_stack(kbuf) || blk_queue_may_bounce(q)) +#endif bio = bio_copy_kern(q, kbuf, len, gfp_mask, reading); else bio = bio_map_kern(q, kbuf, len, gfp_mask); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/crypto/Kconfig linux-imx-phytec/crypto/Kconfig --- linux-6.1.55/crypto/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/crypto/Kconfig 2024-06-19 12:33:59.316209939 +0200 @@ -893,6 +893,26 @@ combined with ESSIV the only feasible mode for h/w accelerated block encryption) +config CRYPTO_TLS + tristate "TLS support" + select CRYPTO_AEAD + select CRYPTO_BLKCIPHER + select CRYPTO_MANAGER + select CRYPTO_HASH + select CRYPTO_NULL + select CRYPTO_AUTHENC + help + Support for TLS 1.0 record encryption and decryption + + This module adds support for encryption/decryption of TLS 1.0 frames + using blockcipher algorithms. The name of the resulting algorithm is + "tls10(hmac(),cbc())". By default, the generic base + algorithms are used (e.g. aes-generic, sha1-generic), but hardware + accelerated versions will be used automatically if available. + + User-space applications (OpenSSL, GnuTLS) can offload TLS 1.0 + operations through AF_ALG or cryptodev interfaces + endmenu menu "Hashes, digests, and MACs" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/crypto/Makefile linux-imx-phytec/crypto/Makefile --- linux-6.1.55/crypto/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/crypto/Makefile 2024-06-19 12:33:59.316209939 +0200 @@ -160,6 +160,7 @@ obj-$(CONFIG_CRYPTO_CRC64_ROCKSOFT) += crc64_rocksoft_generic.o obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o authencesn.o obj-$(CONFIG_CRYPTO_LZO) += lzo.o lzo-rle.o +obj-$(CONFIG_CRYPTO_TLS) += tls.o obj-$(CONFIG_CRYPTO_LZ4) += lz4.o obj-$(CONFIG_CRYPTO_LZ4HC) += lz4hc.o obj-$(CONFIG_CRYPTO_XXHASH) += xxhash_generic.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/crypto/skcipher.c linux-imx-phytec/crypto/skcipher.c --- linux-6.1.55/crypto/skcipher.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/crypto/skcipher.c 2024-06-19 12:33:59.332210213 +0200 @@ -598,7 +598,8 @@ unsigned long alignmask = crypto_skcipher_alignmask(tfm); int err; - if (keylen < cipher->min_keysize || keylen > cipher->max_keysize) + if ((!tfm->base.is_hbk) + && (keylen < cipher->min_keysize || keylen > cipher->max_keysize)) return -EINVAL; if ((unsigned long)key & alignmask) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/crypto/tcrypt.c linux-imx-phytec/crypto/tcrypt.c --- linux-6.1.55/crypto/tcrypt.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/crypto/tcrypt.c 2024-06-19 12:33:59.336210281 +0200 @@ -248,7 +248,7 @@ const int *b_size; const char *key; const char *e; - void *assoc; + void *assoc, *assoc_out; char *iv; int ret; @@ -374,6 +374,8 @@ assoc = cur->axbuf[0]; memset(assoc, 0xff, aad_size); + assoc_out = cur->axbuf[1]; + memset(assoc_out, 0xff, aad_size); sg_init_aead(cur->sg, cur->xbuf, bs + (enc ? 0 : authsize), @@ -381,7 +383,7 @@ sg_init_aead(cur->sgout, cur->xoutbuf, bs + (enc ? authsize : 0), - assoc, aad_size); + assoc_out, aad_size); aead_request_set_ad(cur->req, aad_size); @@ -399,6 +401,9 @@ ret); break; } + + memset(assoc, 0xff, aad_size); + memset(assoc_out, 0xff, aad_size); } aead_request_set_crypt(cur->req, cur->sg, @@ -525,7 +530,7 @@ struct scatterlist *sg; struct scatterlist *sgout; const char *e; - void *assoc; + void *assoc, *assoc_out; char *iv; char *xbuf[XBUFSIZE]; char *xoutbuf[XBUFSIZE]; @@ -596,6 +601,8 @@ assoc = axbuf[0]; memset(assoc, 0xff, aad_size); + assoc_out = axbuf[1]; + memset(assoc_out, 0xff, aad_size); if ((*keysize + bs) > TVMEMSIZE * PAGE_SIZE) { pr_err("template (%u) too big for tvmem (%lu)\n", @@ -633,7 +640,7 @@ assoc, aad_size); sg_init_aead(sgout, xoutbuf, - bs + (enc ? authsize : 0), assoc, + bs + (enc ? authsize : 0), assoc_out, aad_size); aead_request_set_ad(req, aad_size); @@ -655,6 +662,9 @@ ret); break; } + + memset(assoc, 0xff, aad_size); + memset(assoc_out, 0xff, aad_size); } aead_request_set_crypt(req, sg, sgout, @@ -1762,6 +1772,10 @@ ret = min(ret, tcrypt_test("hmac(streebog512)")); break; + case 117: + ret += tcrypt_test("rsa"); + break; + case 150: ret = min(ret, tcrypt_test("ansi_cprng")); break; @@ -1844,6 +1858,12 @@ ret = min(ret, tcrypt_test("cfb(aria)")); ret = min(ret, tcrypt_test("ctr(aria)")); break; + case 193: + ret += tcrypt_test("tls11(hmac(sha1),cbc(aes))"); + break; + case 194: + ret += tcrypt_test("tls12(hmac(sha256),cbc(aes))"); + break; case 200: test_cipher_speed("ecb(aes)", ENCRYPT, sec, NULL, 0, speed_template_16_24_32); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/crypto/testmgr.c linux-imx-phytec/crypto/testmgr.c --- linux-6.1.55/crypto/testmgr.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/crypto/testmgr.c 2024-06-19 12:33:59.336210281 +0200 @@ -126,6 +126,13 @@ unsigned int count; }; +struct tls_test_suite { + struct { + struct tls_testvec *vecs; + unsigned int count; + } enc, dec; +}; + struct akcipher_test_suite { const struct akcipher_testvec *vecs; unsigned int count; @@ -150,6 +157,7 @@ struct hash_test_suite hash; struct cprng_test_suite cprng; struct drbg_test_suite drbg; + struct tls_test_suite tls; struct akcipher_test_suite akcipher; struct kpp_test_suite kpp; } suite; @@ -2656,6 +2664,227 @@ return 0; } +static int __test_tls(struct crypto_aead *tfm, int enc, + struct tls_testvec *template, unsigned int tcount, + const bool diff_dst) +{ + const char *algo = crypto_tfm_alg_driver_name(crypto_aead_tfm(tfm)); + unsigned int i, k, authsize; + char *q; + struct aead_request *req; + struct scatterlist *sg; + struct scatterlist *sgout; + const char *e, *d; + struct crypto_wait wait; + void *input; + void *output; + void *assoc; + char *iv; + char *key; + char *xbuf[XBUFSIZE]; + char *xoutbuf[XBUFSIZE]; + char *axbuf[XBUFSIZE]; + int ret = -ENOMEM; + + if (testmgr_alloc_buf(xbuf)) + goto out_noxbuf; + + if (diff_dst && testmgr_alloc_buf(xoutbuf)) + goto out_nooutbuf; + + if (testmgr_alloc_buf(axbuf)) + goto out_noaxbuf; + + iv = kzalloc(MAX_IVLEN, GFP_KERNEL); + if (!iv) + goto out_noiv; + + key = kzalloc(MAX_KEYLEN, GFP_KERNEL); + if (!key) + goto out_nokey; + + sg = kmalloc(sizeof(*sg) * 8 * (diff_dst ? 2 : 1), GFP_KERNEL); + if (!sg) + goto out_nosg; + + sgout = sg + 8; + + d = diff_dst ? "-ddst" : ""; + e = enc ? "encryption" : "decryption"; + + crypto_init_wait(&wait); + + req = aead_request_alloc(tfm, GFP_KERNEL); + if (!req) { + pr_err("alg: tls%s: Failed to allocate request for %s\n", + d, algo); + goto out; + } + + aead_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + crypto_req_done, &wait); + + for (i = 0; i < tcount; i++) { + input = xbuf[0]; + assoc = axbuf[0]; + + ret = -EINVAL; + if (WARN_ON(template[i].ilen > PAGE_SIZE || + template[i].alen > PAGE_SIZE)) + goto out; + + memcpy(assoc, template[i].assoc, template[i].alen); + memcpy(input, template[i].input, template[i].ilen); + + if (template[i].iv) + memcpy(iv, template[i].iv, MAX_IVLEN); + else + memset(iv, 0, MAX_IVLEN); + + crypto_aead_clear_flags(tfm, ~0); + + if (template[i].klen > MAX_KEYLEN) { + pr_err("alg: aead%s: setkey failed on test %d for %s: key size %d > %d\n", + d, i, algo, template[i].klen, MAX_KEYLEN); + ret = -EINVAL; + goto out; + } + memcpy(key, template[i].key, template[i].klen); + + ret = crypto_aead_setkey(tfm, key, template[i].klen); + if ((!ret) == template[i].fail) { + pr_err("alg: tls%s: setkey failed on test %d for %s: flags=%x\n", + d, i, algo, crypto_aead_get_flags(tfm)); + goto out; + } else if (ret) + continue; + + authsize = template[i].authlen; + ret = crypto_aead_setauthsize(tfm, authsize); + if (ret) { + pr_err("alg: aead%s: Failed to set authsize to %u on test %d for %s\n", + d, authsize, i, algo); + goto out; + } + + k = !!template[i].alen; + sg_init_table(sg, k + 1); + sg_set_buf(&sg[0], assoc, template[i].alen); + sg_set_buf(&sg[k], input, (enc ? template[i].rlen : + template[i].ilen)); + output = input; + + if (diff_dst) { + sg_init_table(sgout, k + 1); + sg_set_buf(&sgout[0], assoc, template[i].alen); + + output = xoutbuf[0]; + sg_set_buf(&sgout[k], output, + (enc ? template[i].rlen : template[i].ilen)); + } + + aead_request_set_crypt(req, sg, (diff_dst) ? sgout : sg, + template[i].ilen, iv); + + aead_request_set_ad(req, template[i].alen); + + ret = crypto_wait_req(enc ? crypto_aead_encrypt(req) + : crypto_aead_decrypt(req), &wait); + + switch (ret) { + case 0: + if (template[i].novrfy) { + /* verification was supposed to fail */ + pr_err("alg: tls%s: %s failed on test %d for %s: ret was 0, expected -EBADMSG\n", + d, e, i, algo); + /* so really, we got a bad message */ + ret = -EBADMSG; + goto out; + } + break; + case -EBADMSG: + /* verification failure was expected */ + if (template[i].novrfy) + continue; + fallthrough; + default: + pr_err("alg: tls%s: %s failed on test %d for %s: ret=%d\n", + d, e, i, algo, -ret); + goto out; + } + + q = output; + if (memcmp(q, template[i].result, template[i].rlen)) { + pr_err("alg: tls%s: Test %d failed on %s for %s\n", + d, i, e, algo); + hexdump(q, template[i].rlen); + pr_err("should be:\n"); + hexdump(template[i].result, template[i].rlen); + ret = -EINVAL; + goto out; + } + } + +out: + aead_request_free(req); + + kfree(sg); +out_nosg: + kfree(key); +out_nokey: + kfree(iv); +out_noiv: + testmgr_free_buf(axbuf); +out_noaxbuf: + if (diff_dst) + testmgr_free_buf(xoutbuf); +out_nooutbuf: + testmgr_free_buf(xbuf); +out_noxbuf: + return ret; +} + +static int test_tls(struct crypto_aead *tfm, int enc, + struct tls_testvec *template, unsigned int tcount) +{ + int ret; + /* test 'dst == src' case */ + ret = __test_tls(tfm, enc, template, tcount, false); + if (ret) + return ret; + /* test 'dst != src' case */ + return __test_tls(tfm, enc, template, tcount, true); +} + +static int alg_test_tls(const struct alg_test_desc *desc, const char *driver, + u32 type, u32 mask) +{ + struct crypto_aead *tfm; + int err = 0; + + tfm = crypto_alloc_aead(driver, type, mask); + if (IS_ERR(tfm)) { + pr_err("alg: aead: Failed to load transform for %s: %ld\n", + driver, PTR_ERR(tfm)); + return PTR_ERR(tfm); + } + + if (desc->suite.tls.enc.vecs) { + err = test_tls(tfm, ENCRYPT, desc->suite.tls.enc.vecs, + desc->suite.tls.enc.count); + if (err) + goto out; + } + + if (!err && desc->suite.tls.dec.vecs) + err = test_tls(tfm, DECRYPT, desc->suite.tls.dec.vecs, + desc->suite.tls.dec.count); + +out: + crypto_free_aead(tfm); + return err; +} + static int alg_test_aead(const struct alg_test_desc *desc, const char *driver, u32 type, u32 mask) { @@ -5629,6 +5858,24 @@ .hash = __VECS(streebog512_tv_template) } }, { + .alg = "tls11(hmac(sha1),cbc(aes))", + .test = alg_test_tls, + .suite = { + .tls = { + .enc = __VECS(tls_enc_tv_template), + .dec = __VECS(tls_dec_tv_template) + } + } + }, { + .alg = "tls12(hmac(sha256),cbc(aes))", + .test = alg_test_tls, + .suite = { + .tls = { + .enc = __VECS(tls12_enc_tv_template), + .dec = __VECS(tls12_dec_tv_template) + } + } + }, { .alg = "vmac64(aes)", .test = alg_test_hash, .suite = { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/crypto/testmgr.h linux-imx-phytec/crypto/testmgr.h --- linux-6.1.55/crypto/testmgr.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/crypto/testmgr.h 2024-06-19 12:33:59.344210418 +0200 @@ -21,7 +21,12 @@ #define _CRYPTO_TESTMGR_H #include +#include +#define MAX_DIGEST_SIZE 64 +#define MAX_TAP 8 + +#define MAX_KEYLEN 160 #define MAX_IVLEN 32 /* @@ -148,6 +153,21 @@ size_t expectedlen; }; +struct tls_testvec { + char *key; /* wrapped keys for encryption and authentication */ + char *iv; /* initialization vector */ + char *input; /* input data */ + char *assoc; /* associated data: seq num, type, version, input len */ + char *result; /* result data */ + unsigned char fail; /* the test failure is expected */ + unsigned char novrfy; /* dec verification failure expected */ + unsigned char klen; /* key length */ + unsigned short ilen; /* input data length */ + unsigned short alen; /* associated data length */ + unsigned short rlen; /* result length */ + unsigned short authlen; /* authentication length */ +}; + struct akcipher_testvec { const unsigned char *key; const unsigned char *params; @@ -179,6 +199,531 @@ static const char zeroed_string[48]; /* + * TLS1.1 synthetic test vectors + */ +static struct tls_testvec tls_enc_tv_template[] = { + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "iv0123456789abcd", + .input = "iv0123456789abcdSingle block msg", + .ilen = 32, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x00\x10", + .alen = 13, + .result = "\x4a\xd8\x67\x27\xec\x74\x48\x8e" + "\x5a\xca\xba\x13\x9c\xcf\x02\xae" + "\x6d\xc2\xeb\x76\xa1\x3b\xe2\x57" + "\x64\xaf\x38\x42\x67\x8e\x57\x3e" + "\xe7\x24\x44\x73\x0a\x23\x77\x07" + "\xbb\xc8\x1f\x4e\x2c\xd4\x56\xa4" + "\x16\x15\x38\x91\xed\x21\xec\x36" + "\xd3\x05\xeb\x10\x04\x00\x4e\xc0", + .rlen = 16 + 20 + 12 + 16, + .authlen = 20, + }, + /* Payload with payload len as zero leads to descriptor error. + */ +#if 0 + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "iv0123456789abcd", + .input = "iv0123456789abcd", + .ilen = 16, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x02\x00\x00", + .alen = 13, + .result = "\x31\x41\x4e\xea\x70\xc2\xb3\xa7" + "\x3e\xcb\x1a\xee\xa9\xe1\xfc\xc4" + "\x5d\xe0\xee\xaa\x6a\x83\x34\xb9" + "\x3d\x9c\x20\x44\x09\xca\x94\xb6" + "\x2d\xf9\xbd\x8a\x7b\x88\xdf\xec" + "\xd5\xbc\x27\x61\xa9\x61\x56\xb6", + .rlen = 20 + 12 + 16, + .authlen = 20, + }, +#endif + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "iv0123456789abcd", + .input = "iv0123456789abcd" + "285 bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext", + .ilen = 285 + 16, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x01\x1d", + .alen = 13, + .result = "\x4a\xd8\x67\x27\xec\x74\x48\x8e" + "\x5a\xca\xba\x13\x9c\xcf\x02\xae" + "\x79\x03\xd4\x14\x1c\x57\x86\x48" + "\xec\x5e\x59\x21\x41\xff\xb9\x2f" + "\x66\xe9\xc1\xc9\xe3\x01\x8c\x10" + "\xb6\xde\x8f\xb1\xc0\x66\x93\xc5" + "\xac\x10\xd6\x86\x35\x63\x2b\xc0" + "\x7a\x40\xfd\x0e\x39\x0a\xf5\x18" + "\x1a\xf7\x99\x3c\x45\xd8\xe4\x92" + "\xd3\x39\x83\x58\x04\x8f\xe0\x95" + "\x24\xee\x62\xc5\xdf\xf6\x4c\x25" + "\x22\x0e\xf7\xe3\x33\x04\x88\x5b" + "\x70\xf8\xf5\x39\x24\xa1\x58\xd2" + "\xf9\x4c\xf9\x64\x0a\xcf\x9f\x36" + "\x23\x43\xda\x44\xfc\x68\xd7\x23" + "\x83\xc2\xb7\xc6\xd7\x7f\xd2\xec" + "\xef\xd7\xfc\x6a\x64\xe9\x70\xdc" + "\x53\x98\xfa\xf2\x41\x24\x87\xbc" + "\x57\xc9\x1c\x38\xff\x4b\x95\x42" + "\xb5\x2c\xfe\xd2\x34\xe2\xa7\x28" + "\x61\x4a\x1d\xe0\x0f\x97\x62\x08" + "\xa6\xa9\x5c\x89\x5e\x42\x60\x71" + "\xda\xd9\xba\x95\x6f\x87\x9c\x00" + "\x7e\x0c\x7a\x6f\xb4\x99\x7e\x0e" + "\x6a\xe9\xab\x12\xda\x95\x25\x83" + "\x8f\xa2\xc2\x91\xb5\x3f\xae\xc3" + "\xf9\x03\xc9\x6d\xe7\xe7\x46\x61" + "\xdc\xbc\xf1\x17\xcc\x93\x33\xa5" + "\x06\x54\x45\x79\xcb\x1c\x67\x87" + "\x87\x35\x9b\xc3\xfd\x3c\xcc\x43" + "\xec\xac\xef\xfd\x3b\x35\xb3\xde" + "\x7d\x82\x57\x49\xc5\xe8\x47\xbe" + "\x70\xf2\xbf\x1c\x98\x1e\x3d\xa4" + "\x25\xa2\x65\x6c\xca\x04\x9a\x1d" + "\x01\x08\xa6\x36\xbe\x89\xd1\x4e" + "\x87\x7f\xae\x70\x79\x0d\x42\x2d" + "\x16\x6f\x00\xf5\x76\x51\xb4\x37" + "\xda\xc2\x54\xa6\x39\x16\x26\x21" + "\xb5\x78\x6e\xa1\xbb\x25\x80\xdf" + "\xdb\x99\xdb\xc2\xec\x83\xf5\x88" + "\x6d\x50\xba\xdd\x30\xb1\x72\xd9" + "\xfc\xce\x7a\xcb\xcf\xd9\x0d\xc9", + .rlen = 285 + 20 + 15 + 16, + .authlen = 20, + } +}; + +static struct tls_testvec tls_dec_tv_template[] = { + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "\x4a\xd8\x67\x27\xec\x74\x48\x8e" + "\x5a\xca\xba\x13\x9c\xcf\x02\xae", + .input = "\x6d\xc2\xeb\x76\xa1\x3b\xe2\x57" + "\x64\xaf\x38\x42\x67\x8e\x57\x3e" + "\xe7\x24\x44\x73\x0a\x23\x77\x07" + "\xbb\xc8\x1f\x4e\x2c\xd4\x56\xa4" + "\x16\x15\x38\x91\xed\x21\xec\x36" + "\xd3\x05\xeb\x10\x04\x00\x4e\xc0", + .ilen = 16 + 20 + 12, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x00\x30", + .alen = 13, + .result = "Single block msg", + .rlen = 16, + .authlen = 20, + }, + /* Payload with payload len as zero leads to descriptor error. + */ +#if 0 + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "\x31\x41\x4e\xea\x70\xc2\xb3\xa7" + "\x3e\xcb\x1a\xee\xa9\xe1\xfc\xc4", + .input = "\x5d\xe0\xee\xaa\x6a\x83\x34\xb9" + "\x3d\x9c\x20\x44\x09\xca\x94\xb6" + "\x2d\xf9\xbd\x8a\x7b\x88\xdf\xec" + "\xd5\xbc\x27\x61\xa9\x61\x56\xb6", + .ilen = 20 + 12, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x02\x00\x20", + .alen = 13, + .result = "", + .rlen = 0, + .authlen = 20, + }, +#endif + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, + .iv = "\x4a\xd8\x67\x27\xec\x74\x48\x8e" + "\x5a\xca\xba\x13\x9c\xcf\x02\xae", + .input = "\x79\x03\xd4\x14\x1c\x57\x86\x48" + "\xec\x5e\x59\x21\x41\xff\xb9\x2f" + "\x66\xe9\xc1\xc9\xe3\x01\x8c\x10" + "\xb6\xde\x8f\xb1\xc0\x66\x93\xc5" + "\xac\x10\xd6\x86\x35\x63\x2b\xc0" + "\x7a\x40\xfd\x0e\x39\x0a\xf5\x18" + "\x1a\xf7\x99\x3c\x45\xd8\xe4\x92" + "\xd3\x39\x83\x58\x04\x8f\xe0\x95" + "\x24\xee\x62\xc5\xdf\xf6\x4c\x25" + "\x22\x0e\xf7\xe3\x33\x04\x88\x5b" + "\x70\xf8\xf5\x39\x24\xa1\x58\xd2" + "\xf9\x4c\xf9\x64\x0a\xcf\x9f\x36" + "\x23\x43\xda\x44\xfc\x68\xd7\x23" + "\x83\xc2\xb7\xc6\xd7\x7f\xd2\xec" + "\xef\xd7\xfc\x6a\x64\xe9\x70\xdc" + "\x53\x98\xfa\xf2\x41\x24\x87\xbc" + "\x57\xc9\x1c\x38\xff\x4b\x95\x42" + "\xb5\x2c\xfe\xd2\x34\xe2\xa7\x28" + "\x61\x4a\x1d\xe0\x0f\x97\x62\x08" + "\xa6\xa9\x5c\x89\x5e\x42\x60\x71" + "\xda\xd9\xba\x95\x6f\x87\x9c\x00" + "\x7e\x0c\x7a\x6f\xb4\x99\x7e\x0e" + "\x6a\xe9\xab\x12\xda\x95\x25\x83" + "\x8f\xa2\xc2\x91\xb5\x3f\xae\xc3" + "\xf9\x03\xc9\x6d\xe7\xe7\x46\x61" + "\xdc\xbc\xf1\x17\xcc\x93\x33\xa5" + "\x06\x54\x45\x79\xcb\x1c\x67\x87" + "\x87\x35\x9b\xc3\xfd\x3c\xcc\x43" + "\xec\xac\xef\xfd\x3b\x35\xb3\xde" + "\x7d\x82\x57\x49\xc5\xe8\x47\xbe" + "\x70\xf2\xbf\x1c\x98\x1e\x3d\xa4" + "\x25\xa2\x65\x6c\xca\x04\x9a\x1d" + "\x01\x08\xa6\x36\xbe\x89\xd1\x4e" + "\x87\x7f\xae\x70\x79\x0d\x42\x2d" + "\x16\x6f\x00\xf5\x76\x51\xb4\x37" + "\xda\xc2\x54\xa6\x39\x16\x26\x21" + "\xb5\x78\x6e\xa1\xbb\x25\x80\xdf" + "\xdb\x99\xdb\xc2\xec\x83\xf5\x88" + "\x6d\x50\xba\xdd\x30\xb1\x72\xd9" + "\xfc\xce\x7a\xcb\xcf\xd9\x0d\xc9", + .ilen = 285 + 20 + 15, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x01\x40", + .alen = 13, + .result = "285 bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext", + .rlen = 285, + .authlen = 20, + } +}; + +/* + * TLS1.2 synthetic test vectors + */ +static struct tls_testvec tls12_enc_tv_template[] = { + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkeysizeis_32bytes_enckeyis16_bytes", + .klen = 8 + 32 + 16, + .iv = "iv0123456789abcd", + .input = "iv0123456789abcdSingle block msg", + .ilen = 32, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x00\x10", + .alen = 13, + .result = "\x4a\xd8\x67\x27\xec\x74\x48\x8e" + "\x5a\xca\xba\x13\x9c\xcf\x02\xae" + "\x6d\xc2\xeb\x76\xa1\x3b\xe2\x57" + "\x64\xaf\x38\x42\x67\x8e\x57\x3e" + "\xbd\xeb\x2e\xe0\x26\xeb\xfe\xb4" + "\x25\xcd\x36\x37\xc1\x81\xd1\x7f" + "\x05\xf0\x21\xef\x9c\xe9\x2d\x23" + "\x83\x00\x64\xd4\xad\x54\x6e\xe6" + "\x9d\xfd\xf1\xd6\xdf\xd9\x1b\x15" + "\xd7\x91\xba\x42\xca\xcb\xc5\xcf", + .rlen = 16 + 32 + 16 + 16, + .authlen = 32, + }, + /* Payload with payload len as zero leads to descriptor error. + */ +#if 0 + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkeysizeis_32bytes_enckeyis16_bytes", + .klen = 8 + 32 + 16, + .iv = "iv0123456789abcd", + .input = "iv0123456789abcd", + .ilen = 16, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x03\x00\x00", + .alen = 13, + .result = "\x31\x41\x4e\xea\x70\xc2\xb3\xa7" + "\x3e\xcb\x1a\xee\xa9\xe1\xfc\xc4" + "\xfe\x63\xd4\x16\x45\x84\x36\x59" + "\xb5\x81\xd7\x84\x5e\xb6\xd0\x18" + "\x2c\x1b\x7a\x14\xc9\x3f\xe5\xc8" + "\x0d\xec\xab\xcc\xcd\x97\x62\xa0" + "\x26\xe8\x2b\xf9\x49\xdb\xf8\x55" + "\x24\x59\xdd\x40\x89\xba\xed\x22", + .rlen = 32 + 16 + 16, + .authlen = 32, + }, +#endif + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkeysizeis_32bytes_enckeyis16_bytes", + .klen = 8 + 32 + 16, + .iv = "iv0123456789abcd", + .input = "iv0123456789abcd" + "285 bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext", + .ilen = 285 + 16, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x01\x1d", + .alen = 13, + .result = "\x4a\xd8\x67\x27\xec\x74\x48\x8e" + "\x5a\xca\xba\x13\x9c\xcf\x02\xae" + "\x79\x03\xd4\x14\x1c\x57\x86\x48" + "\xec\x5e\x59\x21\x41\xff\xb9\x2f" + "\x66\xe9\xc1\xc9\xe3\x01\x8c\x10" + "\xb6\xde\x8f\xb1\xc0\x66\x93\xc5" + "\xac\x10\xd6\x86\x35\x63\x2b\xc0" + "\x7a\x40\xfd\x0e\x39\x0a\xf5\x18" + "\x1a\xf7\x99\x3c\x45\xd8\xe4\x92" + "\xd3\x39\x83\x58\x04\x8f\xe0\x95" + "\x24\xee\x62\xc5\xdf\xf6\x4c\x25" + "\x22\x0e\xf7\xe3\x33\x04\x88\x5b" + "\x70\xf8\xf5\x39\x24\xa1\x58\xd2" + "\xf9\x4c\xf9\x64\x0a\xcf\x9f\x36" + "\x23\x43\xda\x44\xfc\x68\xd7\x23" + "\x83\xc2\xb7\xc6\xd7\x7f\xd2\xec" + "\xef\xd7\xfc\x6a\x64\xe9\x70\xdc" + "\x53\x98\xfa\xf2\x41\x24\x87\xbc" + "\x57\xc9\x1c\x38\xff\x4b\x95\x42" + "\xb5\x2c\xfe\xd2\x34\xe2\xa7\x28" + "\x61\x4a\x1d\xe0\x0f\x97\x62\x08" + "\xa6\xa9\x5c\x89\x5e\x42\x60\x71" + "\xda\xd9\xba\x95\x6f\x87\x9c\x00" + "\x7e\x0c\x7a\x6f\xb4\x99\x7e\x0e" + "\x6a\xe9\xab\x12\xda\x95\x25\x83" + "\x8f\xa2\xc2\x91\xb5\x3f\xae\xc3" + "\xf9\x03\xc9\x6d\xe7\xe7\x46\x61" + "\xdc\xbc\xf1\x17\xcc\x93\x33\xa5" + "\x06\x54\x45\x79\xcb\x1c\x67\x87" + "\x87\x35\x9b\xc3\xfd\x3c\xcc\x43" + "\xec\xac\xef\xfd\x3b\x35\xb3\xde" + "\x7d\x82\x57\x49\xc5\xe8\x47\xbe" + "\x70\xf2\xbf\x1c\x98\x1e\x3d\xa4" + "\x25\xa2\x65\x6c\xca\x04\x9a\x1d" + "\x01\x08\xa6\x36\xbe\x89\xd1\x4e" + "\x87\x7f\xae\x70\x79\x0d\x42\x2d" + "\xcc\x1b\x13\x34\xc5\x1d\xe7\x00" + "\x7f\x65\x72\xa3\x66\xe0\x55\x4f" + "\xf0\x81\x1a\xe0\x21\x4e\x00\xf4" + "\x53\x62\x37\x35\x70\x38\x82\x81" + "\x93\xac\x16\x00\x7a\xd8\xa1\x09" + "\xf6\x2a\x54\x51\x75\xf5\x22\xdb", + .rlen = 285 + 32 + 3 + 16, + .authlen = 32, + } +}; + +static struct tls_testvec tls12_dec_tv_template[] = { + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkeysizeis_32bytes_enckeyis16_bytes", + .klen = 8 + 32 + 16, + .iv = "\x4a\xd8\x67\x27\xec\x74\x48\x8e" + "\x5a\xca\xba\x13\x9c\xcf\x02\xae", + .input = "\x6d\xc2\xeb\x76\xa1\x3b\xe2\x57" + "\x64\xaf\x38\x42\x67\x8e\x57\x3e" + "\xbd\xeb\x2e\xe0\x26\xeb\xfe\xb4" + "\x25\xcd\x36\x37\xc1\x81\xd1\x7f" + "\x05\xf0\x21\xef\x9c\xe9\x2d\x23" + "\x83\x00\x64\xd4\xad\x54\x6e\xe6" + "\x9d\xfd\xf1\xd6\xdf\xd9\x1b\x15" + "\xd7\x91\xba\x42\xca\xcb\xc5\xcf", + .ilen = 64, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x00\x40", + .alen = 13, + .result = "Single block msg", + .rlen = 16, + .authlen = 32, + }, + /* Payload with payload len as zero leads to descriptor error. + */ +#if 0 + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkeysizeis_32bytes_enckeyis16_bytes", + .klen = 8 + 32 + 16, + .iv = "\x31\x41\x4e\xea\x70\xc2\xb3\xa7" + "\x3e\xcb\x1a\xee\xa9\xe1\xfc\xc4", + .input = "\xfe\x63\xd4\x16\x45\x84\x36\x59" + "\xb5\x81\xd7\x84\x5e\xb6\xd0\x18" + "\x2c\x1b\x7a\x14\xc9\x3f\xe5\xc8" + "\x0d\xec\xab\xcc\xcd\x97\x62\xa0" + "\x26\xe8\x2b\xf9\x49\xdb\xf8\x55" + "\x24\x59\xdd\x40\x89\xba\xed\x22", + .ilen = 32 + 16, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x03\x00\x30", + .alen = 13, + .result = "", + .rlen = 0, + .authlen = 32, + }, +#endif + { +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ +#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ +#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkeysizeis_32bytes_enckeyis16_bytes", + .klen = 8 + 32 + 16, + .iv = "\x4a\xd8\x67\x27\xec\x74\x48\x8e" + "\x5a\xca\xba\x13\x9c\xcf\x02\xae", + .input = "\x79\x03\xd4\x14\x1c\x57\x86\x48" + "\xec\x5e\x59\x21\x41\xff\xb9\x2f" + "\x66\xe9\xc1\xc9\xe3\x01\x8c\x10" + "\xb6\xde\x8f\xb1\xc0\x66\x93\xc5" + "\xac\x10\xd6\x86\x35\x63\x2b\xc0" + "\x7a\x40\xfd\x0e\x39\x0a\xf5\x18" + "\x1a\xf7\x99\x3c\x45\xd8\xe4\x92" + "\xd3\x39\x83\x58\x04\x8f\xe0\x95" + "\x24\xee\x62\xc5\xdf\xf6\x4c\x25" + "\x22\x0e\xf7\xe3\x33\x04\x88\x5b" + "\x70\xf8\xf5\x39\x24\xa1\x58\xd2" + "\xf9\x4c\xf9\x64\x0a\xcf\x9f\x36" + "\x23\x43\xda\x44\xfc\x68\xd7\x23" + "\x83\xc2\xb7\xc6\xd7\x7f\xd2\xec" + "\xef\xd7\xfc\x6a\x64\xe9\x70\xdc" + "\x53\x98\xfa\xf2\x41\x24\x87\xbc" + "\x57\xc9\x1c\x38\xff\x4b\x95\x42" + "\xb5\x2c\xfe\xd2\x34\xe2\xa7\x28" + "\x61\x4a\x1d\xe0\x0f\x97\x62\x08" + "\xa6\xa9\x5c\x89\x5e\x42\x60\x71" + "\xda\xd9\xba\x95\x6f\x87\x9c\x00" + "\x7e\x0c\x7a\x6f\xb4\x99\x7e\x0e" + "\x6a\xe9\xab\x12\xda\x95\x25\x83" + "\x8f\xa2\xc2\x91\xb5\x3f\xae\xc3" + "\xf9\x03\xc9\x6d\xe7\xe7\x46\x61" + "\xdc\xbc\xf1\x17\xcc\x93\x33\xa5" + "\x06\x54\x45\x79\xcb\x1c\x67\x87" + "\x87\x35\x9b\xc3\xfd\x3c\xcc\x43" + "\xec\xac\xef\xfd\x3b\x35\xb3\xde" + "\x7d\x82\x57\x49\xc5\xe8\x47\xbe" + "\x70\xf2\xbf\x1c\x98\x1e\x3d\xa4" + "\x25\xa2\x65\x6c\xca\x04\x9a\x1d" + "\x01\x08\xa6\x36\xbe\x89\xd1\x4e" + "\x87\x7f\xae\x70\x79\x0d\x42\x2d" + "\xcc\x1b\x13\x34\xc5\x1d\xe7\x00" + "\x7f\x65\x72\xa3\x66\xe0\x55\x4f" + "\xf0\x81\x1a\xe0\x21\x4e\x00\xf4" + "\x53\x62\x37\x35\x70\x38\x82\x81" + "\x93\xac\x16\x00\x7a\xd8\xa1\x09" + "\xf6\x2a\x54\x51\x75\xf5\x22\xdb", + .ilen = 320, + .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x00\x03\x01\x01\x40", + .alen = 13, + .result = "285 bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext285 bytes" + " plaintext285 bytes plaintext285 bytes plaintext285" + " bytes plaintext285 bytes plaintext", + .rlen = 285, + .authlen = 32, + } +}; + +/* * RSA test vectors. Borrowed from openSSL. */ static const struct akcipher_testvec rsa_tv_template[] = { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/crypto/tls.c linux-imx-phytec/crypto/tls.c --- linux-6.1.55/crypto/tls.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/crypto/tls.c 2024-06-19 12:33:59.344210418 +0200 @@ -0,0 +1,579 @@ +/* + * Copyright 2013 Freescale + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct tls_instance_ctx { + struct crypto_ahash_spawn auth; + struct crypto_skcipher_spawn enc; +}; + +struct crypto_tls_ctx { + unsigned int reqoff; + struct crypto_ahash *auth; + struct crypto_skcipher *enc; + struct crypto_sync_skcipher *null; +}; + +struct tls_request_ctx { + /* + * cryptlen holds the payload length in the case of encryption or + * payload_len + icv_len + padding_len in case of decryption + */ + unsigned int cryptlen; + /* working space for partial results */ + struct scatterlist tmp[2]; + struct scatterlist cipher[2]; + struct scatterlist dst[2]; + char tail[]; +}; + +struct async_op { + struct completion completion; + int err; +}; + +static void tls_async_op_done(struct crypto_async_request *req, int err) +{ + struct async_op *areq = req->data; + + if (err == -EINPROGRESS) + return; + + areq->err = err; + complete(&areq->completion); +} + +static int crypto_tls_setkey(struct crypto_aead *tls, const u8 *key, + unsigned int keylen) +{ + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); + struct crypto_ahash *auth = ctx->auth; + struct crypto_skcipher *enc = ctx->enc; + struct crypto_authenc_keys keys; + int err = -EINVAL; + + if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) + goto out; + + crypto_ahash_clear_flags(auth, CRYPTO_TFM_REQ_MASK); + crypto_ahash_set_flags(auth, crypto_aead_get_flags(tls) & + CRYPTO_TFM_REQ_MASK); + err = crypto_ahash_setkey(auth, keys.authkey, keys.authkeylen); + if (err) + goto out; + + crypto_skcipher_clear_flags(enc, CRYPTO_TFM_REQ_MASK); + crypto_skcipher_set_flags(enc, crypto_aead_get_flags(tls) & + CRYPTO_TFM_REQ_MASK); + err = crypto_skcipher_setkey(enc, keys.enckey, keys.enckeylen); + +out: + memzero_explicit(&keys, sizeof(keys)); + return err; +} + +/** + * crypto_tls_genicv - Calculate hmac digest for a TLS record + * @hash: (output) buffer to save the digest into + * @src: (input) scatterlist with the assoc and payload data + * @srclen: (input) size of the source buffer (assoclen + cryptlen) + * @req: (input) aead request + **/ +static int crypto_tls_genicv(u8 *hash, struct scatterlist *src, + unsigned int srclen, struct aead_request *req) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); + struct tls_request_ctx *treq_ctx = aead_request_ctx(req); + struct async_op ahash_op; + struct ahash_request *ahreq = (void *)(treq_ctx->tail + ctx->reqoff); + unsigned int flags = CRYPTO_TFM_REQ_MAY_SLEEP; + int err = -EBADMSG; + + /* Bail out if the request assoc len is 0 */ + if (!req->assoclen) + return err; + + init_completion(&ahash_op.completion); + + /* the hash transform to be executed comes from the original request */ + ahash_request_set_tfm(ahreq, ctx->auth); + /* prepare the hash request with input data and result pointer */ + ahash_request_set_crypt(ahreq, src, hash, srclen); + /* set the notifier for when the async hash function returns */ + ahash_request_set_callback(ahreq, aead_request_flags(req) & flags, + tls_async_op_done, &ahash_op); + + /* Calculate the digest on the given data. The result is put in hash */ + err = crypto_ahash_digest(ahreq); + if (err == -EINPROGRESS) { + err = wait_for_completion_interruptible(&ahash_op.completion); + if (!err) + err = ahash_op.err; + } + + return err; +} + +/** + * crypto_tls_gen_padicv - Calculate and pad hmac digest for a TLS record + * @hash: (output) buffer to save the digest and padding into + * @phashlen: (output) the size of digest + padding + * @req: (input) aead request + **/ +static int crypto_tls_gen_padicv(u8 *hash, unsigned int *phashlen, + struct aead_request *req) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + unsigned int hash_size = crypto_aead_authsize(tls); + unsigned int block_size = crypto_aead_blocksize(tls); + unsigned int srclen = req->cryptlen + hash_size; + unsigned int icvlen = req->cryptlen + req->assoclen; + unsigned int padlen; + int err; + + err = crypto_tls_genicv(hash, req->src, icvlen, req); + if (err) + goto out; + + /* add padding after digest */ + padlen = block_size - (srclen % block_size); + memset(hash + hash_size, padlen - 1, padlen); + + *phashlen = hash_size + padlen; +out: + return err; +} + +static int crypto_tls_copy_data(struct aead_request *req, + struct scatterlist *src, + struct scatterlist *dst, + unsigned int len) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); + SYNC_SKCIPHER_REQUEST_ON_STACK(skreq, ctx->null); + + skcipher_request_set_sync_tfm(skreq, ctx->null); + skcipher_request_set_callback(skreq, aead_request_flags(req), + NULL, NULL); + skcipher_request_set_crypt(skreq, src, dst, len, NULL); + + return crypto_skcipher_encrypt(skreq); +} + +static int crypto_tls_encrypt(struct aead_request *req) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); + struct tls_request_ctx *treq_ctx = aead_request_ctx(req); + struct skcipher_request *skreq; + struct scatterlist *cipher = treq_ctx->cipher; + struct scatterlist *tmp = treq_ctx->tmp; + struct scatterlist *sg, *src, *dst; + unsigned int cryptlen, phashlen; + u8 *hash = treq_ctx->tail; + int err; + + /* + * The hash result is saved at the beginning of the tls request ctx + * and is aligned as required by the hash transform. Enough space was + * allocated in crypto_tls_init_tfm to accommodate the difference. The + * requests themselves start later at treq_ctx->tail + ctx->reqoff so + * the result is not overwritten by the second (cipher) request. + */ + hash = (u8 *)ALIGN((unsigned long)hash + + crypto_ahash_alignmask(ctx->auth), + crypto_ahash_alignmask(ctx->auth) + 1); + + /* + * STEP 1: create ICV together with necessary padding + */ + err = crypto_tls_gen_padicv(hash, &phashlen, req); + if (err) + return err; + + /* + * STEP 2: Hash and padding are combined with the payload + * depending on the form it arrives. Scatter tables must have at least + * one page of data before chaining with another table and can't have + * an empty data page. The following code addresses these requirements. + * + * If the payload is empty, only the hash is encrypted, otherwise the + * payload scatterlist is merged with the hash. A special merging case + * is when the payload has only one page of data. In that case the + * payload page is moved to another scatterlist and prepared there for + * encryption. + */ + if (req->cryptlen) { + src = scatterwalk_ffwd(tmp, req->src, req->assoclen); + + sg_init_table(cipher, 2); + sg_set_buf(cipher + 1, hash, phashlen); + + if (sg_is_last(src)) { + sg_set_page(cipher, sg_page(src), req->cryptlen, + src->offset); + src = cipher; + } else { + unsigned int rem_len = req->cryptlen; + + for (sg = src; rem_len > sg->length; sg = sg_next(sg)) + rem_len -= min(rem_len, sg->length); + + sg_set_page(cipher, sg_page(sg), rem_len, sg->offset); + sg_chain(sg, 1, cipher); + } + } else { + sg_init_one(cipher, hash, phashlen); + src = cipher; + } + + /** + * If src != dst copy the associated data from source to destination. + * In both cases fast-forward passed the associated data in the dest. + */ + if (req->src != req->dst) { + err = crypto_tls_copy_data(req, req->src, req->dst, + req->assoclen); + if (err) + return err; + } + dst = scatterwalk_ffwd(treq_ctx->dst, req->dst, req->assoclen); + + /* + * STEP 3: encrypt the frame and return the result + */ + cryptlen = req->cryptlen + phashlen; + + /* + * The hash and the cipher are applied at different times and their + * requests can use the same memory space without interference + */ + skreq = (void *)(treq_ctx->tail + ctx->reqoff); + skcipher_request_set_tfm(skreq, ctx->enc); + skcipher_request_set_crypt(skreq, src, dst, cryptlen, req->iv); + skcipher_request_set_callback(skreq, aead_request_flags(req), + req->base.complete, req->base.data); + /* + * Apply the cipher transform. The result will be in req->dst when the + * asynchronuous call terminates + */ + err = crypto_skcipher_encrypt(skreq); + + return err; +} + +static int crypto_tls_decrypt(struct aead_request *req) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls); + struct tls_request_ctx *treq_ctx = aead_request_ctx(req); + unsigned int cryptlen = req->cryptlen; + unsigned int hash_size = crypto_aead_authsize(tls); + unsigned int block_size = crypto_aead_blocksize(tls); + struct skcipher_request *skreq = (void *)(treq_ctx->tail + ctx->reqoff); + struct scatterlist *tmp = treq_ctx->tmp; + struct scatterlist *src, *dst; + + u8 padding[255]; /* padding can be 0-255 bytes */ + u8 pad_size; + u16 *len_field; + u8 *ihash, *hash = treq_ctx->tail; + + int paderr = 0; + int err = -EINVAL; + int i; + struct async_op ciph_op; + + /* + * Rule out bad packets. The input packet length must be at least one + * byte more than the hash_size + */ + if (cryptlen <= hash_size || cryptlen % block_size) + goto out; + + /* + * Step 1 - Decrypt the source. Fast-forward past the associated data + * to the encrypted data. The result will be overwritten in place so + * that the decrypted data will be adjacent to the associated data. The + * last step (computing the hash) will have it's input data already + * prepared and ready to be accessed at req->src. + */ + src = scatterwalk_ffwd(tmp, req->src, req->assoclen); + dst = src; + + init_completion(&ciph_op.completion); + skcipher_request_set_tfm(skreq, ctx->enc); + skcipher_request_set_callback(skreq, aead_request_flags(req), + tls_async_op_done, &ciph_op); + skcipher_request_set_crypt(skreq, src, dst, cryptlen, req->iv); + err = crypto_skcipher_decrypt(skreq); + if (err == -EINPROGRESS) { + err = wait_for_completion_interruptible(&ciph_op.completion); + if (!err) + err = ciph_op.err; + } + if (err) + goto out; + + /* + * Step 2 - Verify padding + * Retrieve the last byte of the payload; this is the padding size. + */ + cryptlen -= 1; + scatterwalk_map_and_copy(&pad_size, dst, cryptlen, 1, 0); + + /* RFC recommendation for invalid padding size. */ + if (cryptlen < pad_size + hash_size) { + pad_size = 0; + paderr = -EBADMSG; + } + cryptlen -= pad_size; + scatterwalk_map_and_copy(padding, dst, cryptlen, pad_size, 0); + + /* Padding content must be equal with pad_size. We verify it all */ + for (i = 0; i < pad_size; i++) + if (padding[i] != pad_size) + paderr = -EBADMSG; + + /* + * Step 3 - Verify hash + * Align the digest result as required by the hash transform. Enough + * space was allocated in crypto_tls_init_tfm + */ + hash = (u8 *)ALIGN((unsigned long)hash + + crypto_ahash_alignmask(ctx->auth), + crypto_ahash_alignmask(ctx->auth) + 1); + /* + * Two bytes at the end of the associated data make the length field. + * It must be updated with the length of the cleartext message before + * the hash is calculated. + */ + len_field = sg_virt(req->src) + req->assoclen - 2; + cryptlen -= hash_size; + *len_field = htons(cryptlen); + + /* This is the hash from the decrypted packet. Save it for later */ + ihash = hash + hash_size; + scatterwalk_map_and_copy(ihash, dst, cryptlen, hash_size, 0); + + /* Now compute and compare our ICV with the one from the packet */ + err = crypto_tls_genicv(hash, req->src, cryptlen + req->assoclen, req); + if (!err) + err = memcmp(hash, ihash, hash_size) ? -EBADMSG : 0; + + if (req->src != req->dst) { + err = crypto_tls_copy_data(req, req->src, req->dst, cryptlen + + req->assoclen); + if (err) + goto out; + } + + /* return the first found error */ + if (paderr) + err = paderr; + +out: + aead_request_complete(req, err); + return err; +} + +static int crypto_tls_init_tfm(struct crypto_aead *tfm) +{ + struct aead_instance *inst = aead_alg_instance(tfm); + struct tls_instance_ctx *ictx = aead_instance_ctx(inst); + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tfm); + struct crypto_ahash *auth; + struct crypto_skcipher *enc; + struct crypto_sync_skcipher *null; + int err; + + auth = crypto_spawn_ahash(&ictx->auth); + if (IS_ERR(auth)) + return PTR_ERR(auth); + + enc = crypto_spawn_skcipher(&ictx->enc); + err = PTR_ERR(enc); + if (IS_ERR(enc)) + goto err_free_ahash; + + null = crypto_get_default_null_skcipher(); + err = PTR_ERR(null); + if (IS_ERR(null)) + goto err_free_skcipher; + + ctx->auth = auth; + ctx->enc = enc; + ctx->null = null; + + /* + * Allow enough space for two digests. The two digests will be compared + * during the decryption phase. One will come from the decrypted packet + * and the other will be calculated. For encryption, one digest is + * padded (up to a cipher blocksize) and chained with the payload + */ + ctx->reqoff = ALIGN(crypto_ahash_digestsize(auth) + + crypto_ahash_alignmask(auth), + crypto_ahash_alignmask(auth) + 1) + + max(crypto_ahash_digestsize(auth), + crypto_skcipher_blocksize(enc)); + + crypto_aead_set_reqsize(tfm, + sizeof(struct tls_request_ctx) + + ctx->reqoff + + max_t(unsigned int, + crypto_ahash_reqsize(auth) + + sizeof(struct ahash_request), + crypto_skcipher_reqsize(enc) + + sizeof(struct skcipher_request))); + + return 0; + +err_free_skcipher: + crypto_free_skcipher(enc); +err_free_ahash: + crypto_free_ahash(auth); + return err; +} + +static void crypto_tls_exit_tfm(struct crypto_aead *tfm) +{ + struct crypto_tls_ctx *ctx = crypto_aead_ctx(tfm); + + crypto_free_ahash(ctx->auth); + crypto_free_skcipher(ctx->enc); + crypto_put_default_null_skcipher(); +} + +static void crypto_tls_free(struct aead_instance *inst) +{ + struct tls_instance_ctx *ctx = aead_instance_ctx(inst); + + crypto_drop_skcipher(&ctx->enc); + crypto_drop_ahash(&ctx->auth); + kfree(inst); +} + +static int crypto_tls_create(struct crypto_template *tmpl, struct rtattr **tb) +{ + struct crypto_attr_type *algt; + struct aead_instance *inst; + struct hash_alg_common *auth; + struct crypto_alg *auth_base; + struct skcipher_alg *enc; + struct tls_instance_ctx *ctx; + u32 mask; + int err; + + algt = crypto_get_attr_type(tb); + if (IS_ERR(algt)) + return PTR_ERR(algt); + + if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) + return -EINVAL; + + err = crypto_check_attr_type(tb, CRYPTO_ALG_TYPE_AEAD, &mask); + if (err) + return err; + + inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL); + if (!inst) + return -ENOMEM; + ctx = aead_instance_ctx(inst); + + err = crypto_grab_ahash(&ctx->auth, aead_crypto_instance(inst), + crypto_attr_alg_name(tb[1]), 0, mask); + if (err) + goto err_free_inst; + auth = crypto_spawn_ahash_alg(&ctx->auth); + auth_base = &auth->base; + + err = crypto_grab_skcipher(&ctx->enc, aead_crypto_instance(inst), + crypto_attr_alg_name(tb[2]), 0, mask); + if (err) + goto err_free_inst; + enc = crypto_spawn_skcipher_alg(&ctx->enc); + + err = -ENAMETOOLONG; + if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, + "tls10(%s,%s)", auth_base->cra_name, + enc->base.cra_name) >= CRYPTO_MAX_ALG_NAME) + goto err_free_inst; + + if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, + "tls10(%s,%s)", auth_base->cra_driver_name, + enc->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME) + goto err_free_inst; + + inst->alg.base.cra_flags = (auth_base->cra_flags | + enc->base.cra_flags) & CRYPTO_ALG_ASYNC; + inst->alg.base.cra_priority = enc->base.cra_priority * 10 + + auth_base->cra_priority; + inst->alg.base.cra_blocksize = enc->base.cra_blocksize; + inst->alg.base.cra_alignmask = auth_base->cra_alignmask | + enc->base.cra_alignmask; + inst->alg.base.cra_ctxsize = sizeof(struct crypto_tls_ctx); + + inst->alg.ivsize = crypto_skcipher_alg_ivsize(enc); + inst->alg.chunksize = crypto_skcipher_alg_chunksize(enc); + inst->alg.maxauthsize = auth->digestsize; + + inst->alg.init = crypto_tls_init_tfm; + inst->alg.exit = crypto_tls_exit_tfm; + + inst->alg.setkey = crypto_tls_setkey; + inst->alg.encrypt = crypto_tls_encrypt; + inst->alg.decrypt = crypto_tls_decrypt; + + inst->free = crypto_tls_free; + + err = aead_register_instance(tmpl, inst); + if (err) { +err_free_inst: + crypto_tls_free(inst); + } + + return err; +} + +static struct crypto_template crypto_tls_tmpl = { + .name = "tls10", + .create = crypto_tls_create, + .module = THIS_MODULE, +}; + +static int __init crypto_tls_module_init(void) +{ + return crypto_register_template(&crypto_tls_tmpl); +} + +static void __exit crypto_tls_module_exit(void) +{ + crypto_unregister_template(&crypto_tls_tmpl); +} + +module_init(crypto_tls_module_init); +module_exit(crypto_tls_module_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("TLS 1.0 record encryption"); +MODULE_ALIAS_CRYPTO("tls10"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/admin-guide/perf/imx-ddr.rst linux-imx-phytec/Documentation/admin-guide/perf/imx-ddr.rst --- linux-6.1.55/Documentation/admin-guide/perf/imx-ddr.rst 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/admin-guide/perf/imx-ddr.rst 2024-06-19 12:33:57.160173072 +0200 @@ -2,6 +2,8 @@ Freescale i.MX8 DDR Performance Monitoring Unit (PMU) ===================================================== +1. PMU in DRC (DDR Controller) + There are no performance counters inside the DRAM controller, so performance signals are brought out to the edge of the controller where a set of 4 x 32 bit counters is implemented. This is controlled by the CSV modes programmed in counter @@ -13,8 +15,8 @@ interrupt is raised. If any other counter overflows, it continues counting, and no interrupt is raised. -The "format" directory describes format of the config (event ID) and config1 -(AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/ +The "format" directory describes format of the config (event ID) and config1/2 +(AXI filter setting) fields of the perf_event_attr structure, see /sys/bus/event_source/ devices/imx8_ddr0/format/. The "events" directory describes the events types hardware supported that can be used with perf tool, see /sys/bus/event_source/ devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented @@ -28,12 +30,11 @@ AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write) to count reading or writing matches filter setting. Filter setting is various from different DRAM controller implementations, which is distinguished by quirks -in the driver. You also can dump info from userspace, filter in "caps" directory -indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates -whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and -value 1 for supported. +in the driver. You also can dump info from userspace, "caps" directory show the +type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for +un-supported, and value 1 for supported. -* With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0). +* With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0, super_filter: 0). Filter is defined with two configuration parts: --AXI_ID defines AxID matching value. --AXI_MASKING defines which bits of AxID are meaningful for the matching. @@ -65,7 +66,49 @@ perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12 -* With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1). +* With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1, super_filter: 0). This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits counting the number of bytes (as opposed to the number of bursts) from DDR read and write transactions concurrently with another set of data counters. + +* With DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk(filter: 0, enhanced_filter: 0, super_filter: 1). + There is a limitation in previous AXI filter, it cannot filter different IDs + at the same time as the filter is shared between counters. This quirk is the + extension of AXI ID filter. One improvement is that counter 1-3 has their own + filter, means that it supports concurrently filter various IDs. Another + improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support + selecting address channel or data channel. + + Filter is defined with 2 configuration registers per counter 1-3. + --Counter N MASK COMP register - including AXI_ID and AXI_MASKING. + --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT. + + - 0: address channel + - 1: data channel + + PMU in DDR subsystem, only one single port0 exists, so axi_port is reserved + which should be 0. + + .. code-block:: bash + + perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd + perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd + + .. note:: + + axi_channel is inverted in userspace, and it will be reverted in driver + automatically. So that users do not need specify axi_channel if want to + monitor data channel from DDR transactions, since data channel is more + meaningful. + +2. PMU in DB (DRAM Block) + + There is a performance counter function included in the DB which allows + statistics to be captured for the various ports. The module is similar to + the one deployed in the DRC but has the ability to select one of the incoming + ports to gather statistics on it. The AXI IDs used is the one seen at one PORT. + + .. code-block:: bash + + perf stat -a -e imx8_db0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_port=0xPP,axi_channel=0xH/ cmd + perf stat -a -e imx8_db0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_port=0xPP,axi_channel=0xH/ cmd diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/arm/freescale/fsl,ele_mu.yaml linux-imx-phytec/Documentation/devicetree/bindings/arm/freescale/fsl,ele_mu.yaml --- linux-6.1.55/Documentation/devicetree/bindings/arm/freescale/fsl,ele_mu.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/arm/freescale/fsl,ele_mu.yaml 2024-06-19 12:33:57.204173824 +0200 @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,ele_mu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP EdgeLock Enclave MU driver + +maintainers: + - Pankaj Gupta + +description: | + Create char devices in /dev as channels of the form /dev/ele_muXchY with X + the id of the driver and Y for each users. It allows to send and receive + messages to the EdgeLock Enclave. + +properties: + compatible: + enum: + - fsl,imx-ele-mu + + mboxes: + description: + List of <&phandle type channel> - 4 channels for TX, 4 channels for RX, + 1 channel for TXDB (see mailbox/fsl,mu.txt) + maxItems: 9 + + mbox-names: + items: + - const: tx + - const: rx + + fsl,ele_mu_did: + description: + Identify the owner of mu(msg unit) with id mentioned at ele_mu_id + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0,1,2,3,4,5,6,7] + + fsl,ele_mu_id: + description: + Identify the driver instance, used to create the channels, default to 1 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0,1,2,3] + + fsl,ele_max_users: + description: + Number of channels to create, default to 4 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0,1,2,3,4,5,6,7,8,9] + + fsl,cmd_tag: + description: + Tag in message header for commands on this MU, default to 0x17 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + - enum: [0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e] + + fsl,rsp_tag: + description: + Tag in message header for responses on this MU, default to 0xe1 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + - enum: [0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8] + +required: + - compatible + - mboxes + - mbox-names + +examples: + - | + ele_mu: ele_mu { + compatible = "fsl,imx-ele-mu"; + mbox-names = "tx", "rx"; + mboxes = <&s4muap 2 0 + &s4muap 3 0>; + + fsl,ele_mu_id = <1>; + fsl,ele_max_users = <4>; + fsl,cmd_tag = /bits/ 8 <0x17>; + fsl,rsp_tag = /bits/ 8 <0xe1>; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml linux-imx-phytec/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml --- linux-6.1.55/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml 2024-06-19 12:33:57.204173824 +0200 @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,imx-sc-secvio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX Security Violation driver + +maintainers: + - Franck LENORMAND + +description: | + Receive security violation from the SNVS via the SCU firmware. Allow to + register notifier for additional processing + +properties: + compatible: + enum: + - fsl,imx-sc-secvio + +required: + - compatible diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/arm/freescale/fsl,s400-api.yaml linux-imx-phytec/Documentation/devicetree/bindings/arm/freescale/fsl,s400-api.yaml --- linux-6.1.55/Documentation/devicetree/bindings/arm/freescale/fsl,s400-api.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/arm/freescale/fsl,s400-api.yaml 2024-06-19 12:33:57.204173824 +0200 @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,s400-api.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S400 Baseline API module + +maintainers: + - Alice Guo + +description: | + In the Sentinel application, the security subsystem uses S4 MU-AP to + communicate and coordinate with the SoC host processor. The s400-api firmware + driver provides the services to transmit data to and receive data from the + S4 MU-AP. + +properties: + compatible: + items: + - const: fsl,imx8ulp-s400 + + mboxes: + description: | + Use the mailbox provided by S4 MU-AP device to communicate with the S400. + It should contain 2 mailboxes, one for transmitting messages and another + for receiving. + maxItems: 1 + + mbox-names: + items: + - const: tx + - const: rx + +required: + - compatible + - mboxes + - mbox-names + +additionalProperties: false + +examples: + - | + s400-api { + compatible = "fsl,imx8ulp-s400"; + mboxes = <&s4muap 0 0 &s4muap 1 0>; + mbox-names = "tx", "rx"; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml linux-imx-phytec/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml --- linux-6.1.55/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml 2024-06-19 12:33:57.204173824 +0200 @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,seco_mu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8 SECO MU driver + +maintainers: + - Aisheng Dong + +description: | + Create char devices in /dev as channels of the form /dev/seco_muXchY with X + the id of the driver and Y for each users. It allows to send and receive + messages to the SECO. + +properties: + compatible: + enum: + - fsl,imx-seco-mu + + mboxes: + description: + List of <&phandle type channel> - 4 channels for TX, 4 channels for RX, + 1 channel for TXDB (see mailbox/fsl,mu.txt) + maxItems: 9 + + mbox-names: + items: + - const: txdb + - const: rxdb + + fsl,seco_mu_id: + description: + Identify the driver instance, used to create the channels, default to 1 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0,1,2,3] + + fsl,seco_max_users: + description: + Number of channels to create, default to 4 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0,1,2,3,4,5,6,7,8,9] + + fsl,cmd_tag: + description: + Tag in message header for commands on this MU, default to 0x17 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + - enum: [0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e] + + fsl,rsp_tag: + description: + Tag in message header for responses on this MU, default to 0xe1 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + - enum: [0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8] + +required: + - compatible + - mboxes + - mbox-names + +examples: + - | + seco_mu: seco_mu { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&mu 2 0 + &mu 3 0>; + + fsl,seco_mu_id = <1>; + fsl,seco_max_users = <4>; + fsl,cmd_tag = /bits/ 8 <0x17>; + fsl,rsp_tag = /bits/ 8 <0xe1>; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/arm/fsl.yaml linux-imx-phytec/Documentation/devicetree/bindings/arm/fsl.yaml --- linux-6.1.55/Documentation/devicetree/bindings/arm/fsl.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/arm/fsl.yaml 2024-06-19 12:33:57.204173824 +0200 @@ -809,6 +809,12 @@ - fsl,imx7ulp-evk # i.MX7ULP Evaluation Kit - const: fsl,imx7ulp + - description: i.MX8DXL based Boards + items: + - enum: + - fsl,imx8dxl-evk # i.MX8DXL EVK Board + - const: fsl,imx8dxl + - description: i.MX8MM based Boards items: - enum: @@ -1067,6 +1073,13 @@ - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 + - description: PHYTEC phyCORE-i.MX93 SoM based boards + items: + - const: phytec,imx93-phyboard-nash # phyBOARD-Nash-i.MX93 + - const: phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93 + - const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM + - const: fsl,imx93 + - description: Freescale Vybrid Platform Device Tree Bindings diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctrl.yaml linux-imx-phytec/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctrl.yaml --- linux-6.1.55/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctrl.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctrl.yaml 2024-06-19 12:33:57.220174098 +0200 @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX BLK_CTRL + +description: | + i.MX BLK_CTRL is a conglomerate of different GPRs that are + dedicated to a specific subsystem. Because it usually contains + clocks amongst other things, it needs access to the i.MX clocks + API. All the other functionalities it provides can work just fine + from the clock subsystem tree. + +maintainers: + - Abel Vesa + +properties: + reg: + maxItems: 1 + + compatible: + items: + - const: fsl,imx8mp-blk-ctrl + - const: syscon + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - power-domains + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + audio-blk-ctrl: blk-ctrl@30e20000 { + compatible = "fsl,imx8mp-blk-ctrl", "syscon"; + reg = <0x30e20000 0x10000>; + power-domains = <&audiomix_pd>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt linux-imx-phytec/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt --- linux-6.1.55/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt 2024-06-19 12:33:57.224174166 +0200 @@ -0,0 +1,57 @@ +* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings + +The Low-Power Clock Gate (LPCG) modules contain a local programming +model to control the clock gates for the peripherals. An LPCG module +is used to locally gate the clocks for the associated peripheral. + +Note: +This level of clock gating is provided after the clocks are generated +by the SCU resources and clock controls. Thus even if the clock is +enabled by these control bits, it might still not be running based +on the base resource. + +Required properties: +- compatible: Should be one of: + "fsl,imx8qxp-lpcg" + "fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-lpcg". +- reg: Address and length of the register set. +- #clock-cells: Should be 1. One LPCG supports multiple clocks. +- clocks: Input parent clocks phandle array for each clock. +- bit-offset: An integer array indicating the bit offset for each clock. +- hw-autogate: Boolean array indicating whether supports HW autogate for + each clock. +- clock-output-names: Shall be the corresponding names of the outputs. + NOTE this property must be specified in the same order + as the clock bit-offset and hw-autogate property. +- power-domains: Should contain the power domain used by this clock. + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. + +Examples: + +#include + +sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b200000 0x10000>; + #clock-cells = <1>; + clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; +}; + +usdhc1: mmc@5b010000 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b010000 0x10000>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; + clock-names = "ipg", "per", "ahb"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml linux-imx-phytec/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml --- linux-6.1.55/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml 2024-06-19 12:33:57.224174166 +0200 @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8ulp-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP Clock Control Module Binding + +maintainers: + - Jacky Bai + +description: | + On i.MX8ULP, The clock sources generation, distribution and management is + under the control of several CGCs & PCCs modules. The CGC modules generate + and distribute clocks on the device. PCC modules control clock selection, + optional division and clock gating mode for peripherals + +properties: + compatible: + enum: + - fsl,imx8ulp-cgc1 + - fsl,imx8ulp-cgc2 + - fsl,imx8ulp-pcc3 + - fsl,imx8ulp-pcc4 + - fsl,imx8ulp-pcc5 + + reg: + maxItems: 1 + + clocks: + description: + specify the external clocks used by the CGC module, the clocks + are rosc, sosc, frosc, lposc + maxItems: 4 + + clock-names: + description: + specify the external clocks names used by the CGC module. the valid + clock names should rosc, sosc, frosc, lposc. + maxItems: 4 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8ulp-clock.h + for the full list of i.MX8ULP clock IDs. + + '#reset-cells': + const: 1 + description: + The reset consumer should specify the desired clock by having the reset + ID in its "resets" phandle cell. See include/dt-bindings/reset/imx8ulp-pcc-reset.h + for the full list of i.MX8ULP reset IDs. Only PCC3, PCC4 and PCC5 should specify + this property. + +required: + - compatible + - reg + - '#clock-cells' + +if: + properties: + compatible: + contains: + enum: + - fsl,imx8ulp-pcc3 + - fsl,imx8ulp-pcc4 + - fsl,imx8ulp-pcc5 +then: + required: + - '#reset-cells' + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + clock-controller@292c0000 { + compatible = "fsl,imx8ulp-cgc1"; + reg = <0x292c0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; + clock-names = "rosc", "sosc", "frosc", "lposc"; + #clock-cells = <1>; + }; + + - | + clock-controller@292d0000 { + compatible = "fsl,imx8ulp-pcc3"; + reg = <0x292d0000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt linux-imx-phytec/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt --- linux-6.1.55/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt 2024-06-19 12:33:57.232174303 +0200 @@ -0,0 +1,31 @@ +* NXP S32V234 Clock Generation Modules (MC_CGMs) + +The SoC supports four Clock Generation Modules, which provide registers for +system and peripherals clock source selection and division. See chapters 22 +("Clocking"), 23 ("Clock Generation Module (MC_CGM)") and 69 ("Mode Entry +Module (MC_ME)") in the reference manual[1]. + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: + Should be: + - "fsl,s32v234-mc_cgm0" for MC_CGM_0 + - "fsl,s32v234-mc_cgm1" for MC_CGM_1 + - "fsl,s32v234-mc_cgm2" for MC_CGM_2 + - "fsl,s32v234-mc_cgm3" for MC_CGM_3 +- reg: + Location and length of the register set +- #clock-cells (only for MC_CGM_0): + Should be <1>. See dt-bindings/clock/s32v234-clock.h for the clock + specifiers allowed in the clocks property of consumers. + +Example: +clks: mc_cgm0@4003c000 { + compatible = "fsl,s32v234-mc_cgm0"; + reg = <0x0 0x4003C000 0x0 0x1000>; + #clock-cells = <1>; +}; + +[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt linux-imx-phytec/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt --- linux-6.1.55/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt 2024-06-19 12:33:57.232174303 +0200 @@ -0,0 +1,16 @@ +* NXP S32V234 Mode Entry Module (MC_ME) + +See chapters 22 ("Clocking") and 69 ("Mode Entry Module (MC_ME)") in the +reference manual[1]. + +Required properties: +- compatible: Should be "fsl,s32v234-mc_me" +- reg: Location and length of the register set + +Example: +mc_me: mc_me@4004a000 { + compatible = "fsl,s32v234-mc_me"; + reg = <0x0 0x4004A000 0x0 0x1000>; +}; + +[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/crypto/fsl-sec4.txt linux-imx-phytec/Documentation/devicetree/bindings/crypto/fsl-sec4.txt --- linux-6.1.55/Documentation/devicetree/bindings/crypto/fsl-sec4.txt 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/crypto/fsl-sec4.txt 2024-06-19 12:33:57.240174440 +0200 @@ -62,6 +62,12 @@ Definition: A standard property. Define the 'ERA' of the SEC device. + - entropy-delay + Usage: optional + Value type: + Definition: A property which specifies the length (in system clocks) + of each Entropy sample taken. + - #address-cells Usage: required Value type: @@ -203,6 +209,26 @@ ===================================================================== +Secure memory (SM) Node + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,imx6q-caam-sm" + + - reg + Usage: required + Value type: + Definition: Specifies a two SM parameters: an offset from + the parent physical address and the length the SM registers. + +EXAMPLE + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x4000>; + }; + +===================================================================== Run Time Integrity Check (RTIC) Node Child node of the crypto node. Defines a register space that @@ -366,6 +392,91 @@ }; ===================================================================== +CAAM SNVS Node + Load the CAAM SNVS node. + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,imx6q-caam-snvs". + + - reg + Usage: required + Value type: + Definition: A standard property. Specifies the physical + address and length of the SEC4 configuration + registers. + + - clocks + Usage: required if i.MX clk driver defines an SNVS clock + Value type: + Definition: Phandle and clock specifier pair describing + the clock required for enabling and disabling SNVS. + + - clock-names + Usage: required if i.MX clk driver defines an SNVS clock + Value type: + Definition: Clock name string corresponding to the clock + in the clocks property. + +===================================================================== +Security Violation (SECVIO) Node + Reports security violations. + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,imx6q-caam-secvio". + + - interrupts + Usage: required + Value type: + Definition: Specifies the interrupts generated by this + device. The value of the interrupts property + consists of one interrupt specifier. The format + of the specifier is defined by the binding document + describing the node's interrupt parent. + + - jtag-tamper + Usage: optional-but-recommended + Value type: + Definition: + Security tamper on the JTAG + Must include "enabled" to enable. + + - watchdog-tamper + Usage: optional-but-recommended + Value type: + Definition: + Security tamper on the watchdog + Must include "enabled" to enable. + + - internal-boot-tamper + Usage: optional-but-recommended + Value type: + Definition: + Security tamper on the internal boot + Must include "enabled" to enable. + + - external-pin-tamper + Usage: optional-but-recommended + Value type: + Definition: + Security tamper on the external pin + Must include "enabled" to enable. + +EXAMPLE + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + +===================================================================== Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node A SNVS child node that defines SNVS LP RTC. @@ -394,18 +505,14 @@ value type: Definition: LP register offset. default it is 0x34. - - clocks - Usage: optional, required if SNVS LP RTC requires explicit - enablement of clocks - Value type: - Definition: a clock specifier describing the clock required for - enabling and disabling SNVS LP RTC. - - - clock-names - Usage: optional, required if SNVS LP RTC requires explicit - enablement of clocks - Value type: - Definition: clock name string should be "snvs-rtc". + - clocks + Usage: optional + Value type: + Definition: A standard property. Specifies the source clock for + snvs register access. If i.MX clk driver defines the clock node, + it needs user to specify the clocks in device tree for all modules + with snvs LP/HP registers access. The modules involved snvs LP/HP + registers access are snvs-power key, snvs-rtc, and caam. EXAMPLE sec_mon_rtc_lp@1 { @@ -444,6 +551,13 @@ Value type: Definition: Button can wake-up the system. + - emulate-press: + Usage: option + Value type: + Definition: For ONOFF key only trigger interrupt after release but + not press like i.mx6q/dl/sl, emulate press event before + release. + - regmap: Usage: required: Value type: @@ -550,4 +664,18 @@ }; }; + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + ===================================================================== diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml 2024-06-19 12:33:57.244174508 +0200 @@ -45,6 +45,26 @@ - const: cec - const: packet + adi,dsi-channel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Only for ADV7533 and ADV7535. DSI channel number to be used + when communicating with the DSI peripheral. + It should be one of 0, 1, 2 or 3. + + adi,addr-cec: + description: + Only for ADV7533 and ADV7535. The I2C DSI-CEC register map + address to be programmed into the MAIN register map. + adi,addr-edid: + description: + Only for ADV7533 and ADV7535. The I2C EDID register map + to be programmed into the MAIN register map. + adi,addr-pkt: + description: + Only for ADV7533 and ADV7535. The I2C PACKET register map + to be programmed into the MAIN register map. + clocks: description: Reference to the CEC clock. maxItems: 1 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/bridge/it6263.txt linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/it6263.txt --- linux-6.1.55/Documentation/devicetree/bindings/display/bridge/it6263.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/it6263.txt 2024-06-19 12:33:57.244174508 +0200 @@ -0,0 +1,27 @@ +ITE IT6263 LVDS to HDMI bridge bindings + +Required properties: + - compatible: "ite,it6263" + - reg: i2c address of the bridge + - video input: this subnode can contain a video input port node + to connect the bridge to a LVDS output interface (See this + documentation [1]). + +Optional properties: + - split-mode: boolean. if this exists, split mode is enabled, + otherwise, single mode is enabled. + - reset-gpios: OF device-tree gpio specification for SYSRSTN pin. + +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/bridge/maxim,max96752-lvds-bridge.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/maxim,max96752-lvds-bridge.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/bridge/maxim,max96752-lvds-bridge.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/maxim,max96752-lvds-bridge.yaml 2024-06-19 12:33:57.244174508 +0200 @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/maxim,max96752-lvds-bridge.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX96752 deserializer LVDS subdevice + +maintainers: + - Laurentiu Palcu + +description: | + The MAX96752/MAX96754 convert a single video stream received on a single- or dual-link GMSL2 input + to an LVDS(OLDI) output for driving display panels. Video data is mapped to OLDI output ports + A, B, or both. The output can drive with OLDI or VESA formats. + +properties: + compatible: + enum: + - maxim,max96752-lvds + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + maxim,dual-channel: + description: Indicates whether to activate dual-channel LVDS output or not. + type: boolean + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: LVDS output port + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: Input video stream. + + endpoint@1: + $ref: /schemas/graph.yaml#/properties/endpoint + description: Output video stream. + +required: + - compatible + - '#address-cells' + - '#size-cells' + - port + +additionalProperties: false diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/bridge/maxim,max96789-dsi-bridge.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/maxim,max96789-dsi-bridge.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/bridge/maxim,max96789-dsi-bridge.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/maxim,max96789-dsi-bridge.yaml 2024-06-19 12:33:57.244174508 +0200 @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/maxim,max96789-dsi-bridge.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX96789 serializer MIPI-DSI subdevice + +maintainers: + - Laurentiu Palcu + +description: | + The MAX96789/MAX96791 family of serializers convert dual MIPI DSI, four-lane input port data to + dual Maxim Integrated’s GMSL 1 or 2 high-speed serial link protocol. + +properties: + compatible: + enum: + - maxim,max96789-dsi + + reg: + description: The DSI input port number. + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: DSI input port + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + description: DSI controller + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + endpoint@1: + $ref: /schemas/graph.yaml#/properties/endpoint + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - port + +additionalProperties: false diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml 2024-06-19 12:33:57.244174508 +0200 @@ -19,7 +19,9 @@ properties: compatible: - const: fsl,imx8mq-nwl-dsi + enum: + - fsl,imx8mq-nwl-dsi + - fsl,imx8ulp-nwl-dsi reg: maxItems: 1 @@ -44,6 +46,7 @@ - description: TX_ESC clock (used in escape mode) - description: PHY_REF clock - description: LCDIF clock + - description: PHY_PARENT clock (optional) clock-names: items: @@ -52,6 +55,7 @@ - const: tx_esc - const: phy_ref - const: lcdif + - const: phy_parent mux-controls: description: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/bridge/nxp,seiko-43wvfig.txt linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/nxp,seiko-43wvfig.txt --- linux-6.1.55/Documentation/devicetree/bindings/display/bridge/nxp,seiko-43wvfig.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/nxp,seiko-43wvfig.txt 2024-06-19 12:33:57.244174508 +0200 @@ -0,0 +1,40 @@ +Legacy Freescale RA169Z20 adapter card for Seiko 43WVFIG panel, driver bindings + +This is an adapter card made for the 4.3", 800x480, LCD panel Seiko 43WVFIG. +The LCD panel is a 24bit DPI bus, while the adapter card has two ports: +18-bit and 24-bit data input. For the 18-bit data input, the adapter card +is demuxing some of the data lines, in order to feed all of the 24 lines +needed by the LCD. + +Required properties: +- compatible: "nxp,seiko-43wvfig" +- bus_mode: must be one of <18> or <24>, depending on the input port + used (18-bit or 24-bit) +- port: input and output port nodes with endpoint definitions as + defined in Documentation/devicetree/bindings/graph.txt; + the input port should be connected to an lcd controller + while the output port should be connected to the Seiko + 43wvfig LCD panel + +Example: + seiko_adapter: seiko-adapter { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,seiko-43wvfig"; + bus_mode = <18>; + + port@0 { + reg = <0>; + adapter_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + port@1 { + reg = <1>; + adapter_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + +- diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt --- linux-6.1.55/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt 2024-06-19 12:33:57.244174508 +0200 @@ -0,0 +1,60 @@ +Samsung MIPI DSIM bridge bindings + +The MIPI DSIM host controller drives the video signals from +display controller to video peripherals using DSI protocol. +This is an un-managed DSI bridge. In order to use this bridge, +an encoder or bridge must be implemented to manage the platform +specific initializations. + +Required properties: +- compatible: "fsl,imx8mm-mipi-dsim" +- reg: the register range of the MIPI DSIM controller +- interrupts: the interrupt number for this module +- clock, clock-names: phandles to the MIPI-DSI clocks described in + Documentation/devicetree/bindings/clock/clock-bindings.txt + "cfg" - DSIM access clock + "pll-ref" - DSIM PHY PLL reference clock +- assigned-clocks: phandles to clocks that requires initial configuration +- assigned-clock-rates: rates of the clocks that requires initial configuration +- pref-clk: Assign DPHY PLL reference clock frequency. If not exists, + DSIM bridge driver will use the default lock frequency + which is 27MHz. +- port: input and output port nodes with endpoint definitions as + defined in Documentation/devicetree/bindings/graph.txt; + the input port should be connected to an encoder or a + bridge that manages this MIPI DSIM host and the output + port should be connected to a panel or a bridge input + port + +Optional properties: +-dsi-gpr: a phandle which provides the MIPI DSIM control and gpr registers + +example: + mipi_dsi: mipi_dsi@32E10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x0 0x32e10000 0x0 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE_DIV>, + <&clk IMX8MM_CLK_DSI_PHY_REF_DIV>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE_SRC>, + <&clk IMX8MM_CLK_DSI_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>; + interrupts = ; + dsi-gpr = <&dispmix_gpr>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + }; + }; + + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/fsl,lcdif.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/fsl,lcdif.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/fsl,lcdif.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/fsl,lcdif.yaml 2024-06-19 12:33:57.248174577 +0200 @@ -56,6 +56,12 @@ $ref: /schemas/graph.yaml#/properties/port description: The LCDIF output port + max-memory-bandwidth: + - description: | + maximum bandwidth in bytes per second that the + controller can handle; if not present, the memory + interface is fast enough to handle all possible video modes + required: - compatible - reg diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/imx/fsl,imx93-mipi-dsi.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/imx/fsl,imx93-mipi-dsi.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/imx/fsl,imx93-mipi-dsi.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/imx/fsl,imx93-mipi-dsi.yaml 2024-06-19 12:33:57.248174577 +0200 @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx93-mipi-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX93 Synopsys DesignWare MIPI DSI host controller + +maintainers: + - Liu Ying + +description: + Synopsys DesignWare MIPI DSI host controller found in Freescale i.MX93 SoC. + +allOf: + - $ref: ../dsi-controller.yaml# + +properties: + compatible: + const: fsl,imx93-mipi-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + clocks: + items: + - description: byte clock + - description: apb clock + - description: pixel clock + + clock-names: + items: + - const: byte + - const: pclk + - const: pixel + + assigned-clocks: true + assigned-clock-parents: true + assigned-clock-rates: true + + phys: + maxItems: 1 + description: + Phandle to the phy module representing a MIPI DPHY. + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Input port node to receive pixel data from display controller. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port node to a panel or a bridge input port. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + - power-domains + - ports + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + dsi: dsi@4ae10000 { + compatible = "fsl,imx93-mipi-dsi"; + reg = <0x4ae10000 0x4000>; + interrupts = ; + clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>; + clock-names = "byte", "pclk", "pixel"; + assigned-clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <20000000>, <133333333>; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + dsi-lanes = <4>; + video-mode = <2>; + width-mm = <68>; + height-mm = <121>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_to_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsi>; + }; + }; + + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + +... diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt linux-imx-phytec/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt --- linux-6.1.55/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt 2024-06-19 12:33:57.248174577 +0200 @@ -110,6 +110,302 @@ fsl,pres = <&pre1>, <&pre2>, <&pre3>; }; +Freescale i.MX DPU +==================== + +Required properties: +- compatible: Should be "fsl,-dpu" +- reg: should be register base and length as documented in the + datasheet +- interrupt-parent: phandle pointing to the parent interrupt controller. +- interrupts, interrupt-names: Should contain interrupts and names as + documented in the datasheet. +- clocks, clock-names: phandles to the DPU clocks described in + Documentation/devicetree/bindings/clock/clock-bindings.txt + The following clocks are expected on i.MX8qxp: + "pll0" - PLL clock for display interface 0 + "pll1" - PLL clock for display interface 1 + "disp0" - pixel clock for display interface 0 + "disp1" - pixel clock for display interface 1 + The needed clock numbers for each are documented in + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- power-domains: phandles pointing to power domain. +- power-domain-names: power domain names relevant to power-domains phandles. +- fsl,dpr-channels: phandles to the DPR channels attached to this DPU, + sorted by memory map addresses. +- fsl,pixel-combiner: phandle to the pixel combiner unit attached to this DPU. +Optional properties: +- port@[0-1]: Port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + ports 0 and 1 should correspond to display interface 0 and + display interface 1, respectively. + +example: + +dpu: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-dpu"; + reg = <0x56180000 0x40000>; + interrupt-parent = <&irqsteer_dpu>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <0>, + <1>, <2>, <3>, <4>, + <82>, <83>, <84>, <85>, + <209>, <210>, <211>, <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&dc_lpcg IMX_DC0_PLL0_CLK>, + <&dc_lpcg IMX_DC0_PLL1_CLK>, + <&dc_lpcg IMX_DC0_DISP0_CLK>, + <&dc_lpcg IMX_DC0_DISP1_CLK>; + clock-names = "pll0", "pll1", "disp0", "disp1"; + power-domains = <&pd IMX_SC_R_DC_0>, + <&pd IMX_SC_R_DC_0_PLL_0>, + <&pd IMX_SC_R_DC_0_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, <&dc0_dpr2_channel3>; + fsl,pixel-combiner = <&dc0_pc>; + + dpu_disp0: port@0 { + reg = <0>; + + dpu_disp0_lvds0_ch0: endpoint@0 { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu_disp0_lvds0_ch1: endpoint@1 { + remote-endpoint = <&ldb1_ch1>; + }; + + dpu_disp0_mipi_dsi: endpoint@2 { + }; + }; + + dpu_disp1: port@1 { + reg = <1>; + + dpu_disp1_lvds1_ch0: endpoint@0 { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu_disp1_lvds1_ch1: endpoint@1 { + remote-endpoint = <&ldb2_ch1>; + }; + + dpu_disp1_mipi_dsi: endpoint@2 { + }; + }; +}; + +Freescale i.MX8 PC (Pixel Combiner) +============================================= +Required properties: +- compatible: should be "fsl,-pixel-combiner" +- reg: should be register base and length as documented in the + datasheet +- power-domains: phandle pointing to power domain + +example: + +pixel-combiner@56020000 { + compatible = "fsl,imx8qm-pixel-combiner"; + reg = <0x56020000 0x10000>; + power-domains = <&pd IMX_SC_R_DC_0>; +}; + +Freescale i.MX8 PRG (Prefetch Resolve Gasket) +============================================= +Required properties: +- compatible: should be "fsl,-prg" +- reg: should be register base and length as documented in the + datasheet +- clocks: phandles to the PRG apb and rtram clocks, as described in + Documentation/devicetree/bindings/clock/clock-bindings.txt and + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- clock-names: should be "apb" and "rtram" +- power-domains: phandle pointing to power domain + +example: + +prg@56040000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x56040000 0x10000>; + clocks = <&dc0_prg0_lpcg 0>, <&dc0_prg0_lpcg 1>; + clock-names = "apb", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; +}; + +Freescale i.MX8 DPRC (Display Prefetch Resolve Channel) +======================================================= +Required properties: +- compatible: should be "fsl,-dpr-channel" +- reg: should be register base and length as documented in the + datasheet +- fsl,sc-resource: SCU resource number as defined in + include/dt-bindings/firmware/imx/rsrc.h +- fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one + is the primary PRG and the second one(if available) is the auxiliary PRG + which is used to fetch luma chunk of a YUV frame with 2 planars. +- clocks: phandles to the DPRC apb, b and rtram clocks, as described in + Documentation/devicetree/bindings/clock/clock-bindings.txt and + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- clock-names: should be "apb", "b" and "rtram" +- power-domains: phandle pointing to power domain + +example: + +dpr-channel@560e0000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x560e0000 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg2>, <&dc0_prg1>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; +}; + +Freescale i.MX93 parallel display format +======================================== +Required properties: +- compatible: should be "fsl,imx93-parallel-display-format" +- power-domains: phandle pointing to power domain +- ports: It contains port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + Port 0 is the input port connected to the display controller, + port 1 is the output port connected to a panel or a bridge. +Optional properties: +- fsl,interface-pix-fmt: How this display is connected to the + display interface, can be "rgb565", "rgb666" and "rgb888". + +LCDIF mux display support +========================= + +Required properties: +- compatible: Should be "fsl,imx-lcdif-mux-display" +- #address-cells : should be <1> +- #size-cells : should be <0> +- pinctrl-names : should be "default" +- pinctrl-0 : phandle pointing to parallel display pin settings +- clocks : phandle to the LCD pixel bypass divider clock and the LCD pixel clock + as described in Documentation/devicetree/bindings/clock/clock-bindings.txt and + Documentation/devicetree/bindings/clock/imx8qxp-clock.txt. +- clock-names: should be "bypass_div" and "pixel" +- assigned-clocks: phandle to the LCD pixel selector clock +- assigned-clock-parents: phandle to the LCD pixel bypass divider clock +- fsl,lcdif-mux-regs: should be <&lcdif_mux_regs> on i.MX8qxp. + The phandle points to a syscon region containing + LCDIF mux control register. +- power-domains: phandle pointing to power domain +- port@[0-1]: Port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + Port 0 is the input port connected to the DPU display interface, + port 1 is the output port connected to a panel or a bridge. +Optional properties: +- fsl,interface-pix-fmt: How this display is connected to the + display interface, can be "rgb565", "rgb666" and "rgb888". + +example: + +display@disp1 { + compatible = "fsl,imx-lcdif-mux-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "bypass_div", "pixel"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + fsl,lcdif-mux-regs = <&lcdif_mux_regs>; + fsl,interface-pix-fmt = "rgb666"; + power-domains = <&pd IMX_SC_R_LCD_0>; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&dpu_disp1_lcdif>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +panel { + ... + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; +}; + Parallel display support ======================== diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/imx/ldb.txt linux-imx-phytec/Documentation/devicetree/bindings/display/imx/ldb.txt --- linux-6.1.55/Documentation/devicetree/bindings/display/imx/ldb.txt 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/imx/ldb.txt 2024-06-19 12:33:57.248174577 +0200 @@ -9,15 +9,26 @@ Required properties: - #address-cells : should be <1> - #size-cells : should be <0> - - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". - Both LDB versions are similar, but i.MX6 has an additional - multiplexer in the front to select any of the four IPU display - interfaces as input for each LVDS channel. + - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb" or + "fsl,imx8qm-ldb" or "fsl,imx8qxp-ldb" or "fsl,imx8mp-ldb" or + "fsl,imx93-ldb". + All LDB versions are similar. + i.MX6q/dl has an additional multiplexer in the front to select + any of the two or four IPU display interfaces as input for each + LVDS channel. + i.MX8qm LDB supports 10bit RGB input and needs an additional + phy. + i.MX8qxp and i.MX8mp LDB only supports one LVDS encoder + channel(either channel0 or channel1). + i.MX93 LDB only supports one LVDS encoder channel(channel0). - gpr : should be <&gpr> on i.MX53 and i.MX6q. The phandle points to the iomuxc-gpr region containing the LVDS control register. + - fsl,auxldb : phandle to auxiliary LDB which is used in dual channel mode. + Only required by i.MX8qxp. - clocks, clock-names : phandles to the LDB divider and selector clocks and to - the display interface selector clocks, as described in + the display interface selector clocks or pixel and + bypass clocks as described in Documentation/devicetree/bindings/clock/clock-bindings.txt The following clocks are expected on i.MX53: "di0_pll" - LDB LVDS channel 0 mux @@ -29,14 +40,27 @@ On i.MX6q the following additional clocks are needed: "di2_sel" - IPU2 DI0 mux "di3_sel" - IPU2 DI1 mux + The following clocks are expected on i.MX8qm and i.MX8qxp: + "pixel" - pixel clock + "bypass" - bypass clock + The following clocks are expected on i.MX8qxp: + "aux_pixel" - auxiliary pixel clock in dual channel mode + "aux_bypass" - auxiliary bypass clock in dual channel mode + The following clocks are expected on i.MX8mp and i.MX93: + "ldb" - ldb root clock The needed clock numbers for each are documented in Documentation/devicetree/bindings/clock/imx5-clock.yaml, and in - Documentation/devicetree/bindings/clock/imx6q-clock.yaml. + Documentation/devicetree/bindings/clock/imx6q-clock.yaml and in + Documentation/devicetree/bindings/clock/imx8qm-lpcg.txt, and in + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- power-domains : phandle pointing to power domain, only required by i.MX8qm, + i.MX8qxp, i.MX8mp and i.MX93. Optional properties: - - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q + - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q, i.MX8qm + i.MX8qxp, i.MX8mp and i.MX93 - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, - not used on i.MX6q + not used on i.MX6q, i.MX8qm, i.MX8qxp, i.MX8mp and i.MX93 - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should be configured - one input will be distributed on both outputs in dual channel mode @@ -57,9 +81,18 @@ (lvds-channel@[0,1], respectively). On i.MX6, there should be four input ports (port@[0-3]) that correspond to the four LVDS multiplexer inputs. - A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected - to a panel input port. Optionally, the output port can be left out if - display-timings are used instead. + On i.MX8qm, the two channels of LDB connect to one display interface of DPU. + On i.MX8mp, the two channels of LDB connect to LCDIFv3. + On i.MX93, the channel of LDB connect to LCDIFv3. + A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm, + i.MX8qxp, i.MX8mp and i.MX93) must be connected to a panel input port or + a bridge input port. + Optionally, the output port can be left out if display-timings are used + instead. + - phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm, i.MX8qxp, + i.MX8mp and i.MX93. + - phy-names: should be "ldb_phy". Valid only on i.MX8qm, i.MX8qxp, i.MX8mp + and i.MX93. Optional properties (required if display-timings are used): - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing @@ -69,6 +102,7 @@ This describes how the color bits are laid out in the serialized LVDS signal. - fsl,data-width : should be <18> or <24> + Additionally, <30> for i.MX8qm. example: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml 2024-06-19 12:33:57.248174577 +0200 @@ -46,6 +46,8 @@ - description: RTRAM clock - description: Pixel clock, can be driven either by HDMI phy clock or MIPI - description: DTRC clock, needed by video decompressor + - description: PLL source clock, usually VIDEO2_PLL, used when output is HDMI; + - description: PLL PHY reference clock, used when output is HDMI; clock-names: items: @@ -54,6 +56,8 @@ - const: rtrm - const: pix - const: dtrc + - const: pll_src + - const: pll_phy_ref assigned-clocks: items: @@ -91,8 +95,10 @@ interrupt-parent = <&irqsteer>; clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>, - <&clk IMX8MQ_CLK_DISP_DTRC>; - clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + <&clk IMX8MQ_CLK_DISP_DTRC>, <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_PHY_27MHZ>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", + "pll_src", "pll_phy_ref"; assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>, <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/imx/nxp,imx8ulp-dcnano.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/imx/nxp,imx8ulp-dcnano.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/imx/nxp,imx8ulp-dcnano.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/imx/nxp,imx8ulp-dcnano.yaml 2024-06-19 12:33:57.248174577 +0200 @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/nxp,imx8ulp-dcnano.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ulp DCNANO display controller + +maintainers: + - Liu Ying + +description: | + The NXP i.MX8ulp DCNANO display controller is a high-performance graphics + core that can be used for reading rendered images from the frame buffer. + In addition to providing hardware cursor patterns, the display controller + performs format conversions, dithering and gamma corrections. The display + controller supports either Display Pixel Interface-2(DPI-2) or Display Bus + Interface 2.0(DBI-2). + +properties: + compatible: + const: nxp,imx8ulp-dcnano + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: axi + - const: ahb + - const: pixel + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + assigned-clocks: true + assigned-clock-parents: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The DCNANO DPI-2 output port node. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: The DCNANO DBI-2 output port node. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + dcnano: display-controller@2e050000 { + compatible = "nxp,imx8ulp-dcnano"; + reg = <0x2e050000 0x10000>; + interrupts = ; + clocks = <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>, + <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>, + <&pcc5 IMX8ULP_CLK_DC_NANO>; + clock-names = "axi", "ahb", "pixel"; + resets = <&pcc5 PCC5_DC_NANO_SWRST>; + power-domains = <&scmi_devpd IMX8ULP_PD_DCNANO>; + assigned-clocks = <&pcc5 IMX8ULP_CLK_DC_NANO>; + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dcnano_dpi: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dcnano_dpi_to_mipi_dsi: endpoint@0 { + reg = <0>; + }; + + dcnano_dpi_to_disp: endpoint@1 { + reg = <1>; + }; + }; + + dcnano_dbi: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dcnano_dbi_to_mipi_dsi: endpoint@0 { + reg = <0>; + }; + + dcnano_dbi_to_disp: endpoint@1 { + reg = <1>; + }; + }; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt linux-imx-phytec/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt --- linux-6.1.55/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt 2024-06-19 12:33:57.252174645 +0200 @@ -0,0 +1,9 @@ +Japan Display Inc. 10.1" WUXGA (1920x1200) TFT LCD panel + +The panel has dual LVDS channels. + +Required properties: +- compatible: should be "jdi,tx26d202vm0bwa" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/panel/panel-simple.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/panel/panel-simple.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/panel/panel-simple.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/panel/panel-simple.yaml 2024-06-19 12:33:57.256174713 +0200 @@ -77,6 +77,8 @@ - auo,t215hvn01 # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel - avic,tm070ddh03 + # BOE EV121WXM-N10-1850 12.1" WXGA TFT LCD panel + - boe,ev121wxm-n10-1850 # BOE HV070WSA-100 7.01" WSVGA TFT LCD panel - boe,hv070wsa-100 # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel @@ -143,6 +145,8 @@ - edt,etm0700g0edh6 # Emerging Display Technology Corp. LVDS WSVGA TFT Display with capacitive touch - edt,etml0700y5dha + # Emerging Display Technology Corp. 10.1" LVDS WXGA TFT Display with capacitive touch + - edt,etml1010g3dra # Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with # capacitive touch - edt,etmv570g2dhu @@ -256,6 +260,8 @@ - okaya,rs800480t-7x0gp # Olimex 4.3" TFT LCD panel - olimex,lcd-olinuxino-43-ts + # On Tat Industrial Company 5" DPI TFT panel. + - ontat,kd50g21-40nt-a1 # On Tat Industrial Company 7" DPI TFT panel. - ontat,yx700wv03 # OrtusTech COM37H3M05DTC Blanview 3.7" VGA portrait TFT-LCD panel diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml 2024-06-19 12:33:57.256174713 +0200 @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/panel/raydium,rm67191.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Raydium RM67171 OLED LCD panel with MIPI-DSI protocol +title: Raydium RM67171/RM67199 OLED LCD panel with MIPI-DSI protocol maintainers: - Robert Chiras @@ -14,7 +14,9 @@ properties: compatible: - const: raydium,rm67191 + items: + - const: raydium,rm67191 + - const: raydium,rm67199 reg: true port: true @@ -38,8 +40,9 @@ 0 - burst-mode 1 - non-burst with sync event 2 - non-burst with sync pulse + 3 - command mode $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2] + enum: [0, 1, 2, 3] required: - compatible diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/panel/rocktech,himax8394f.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/panel/rocktech,himax8394f.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/panel/rocktech,himax8394f.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/panel/rocktech,himax8394f.yaml 2024-06-19 12:33:57.256174713 +0200 @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/rocktech,himax8394f.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rocktech Himax8394f 720x1280 TFT LCD panel + +maintainers: + - Liu Ying + +description: + Rocktech Himax8394f is a 720x1280 TFT LCD panel + connected using a MIPI-DSI video interface. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: rocktech,himax8394f + + reg: + maxItems: 1 + description: DSI virtual channel + + himax,dsi-lanes: + description: Number of DSI lanes to be used must be <1> or <2> or <3> or <4> + enum: [1, 2, 3, 4] + + enable-gpios: true + port: true + + vcc-supply: + description: A typical 2.8V supply(minimum 2.5V, maximum 3.6V). + + iovcc-supply: + description: A typical 1.8V supply(minimum 1.65V, maximum 3.6V). + + reset-gpios: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - himax,dsi-lanes + - vcc-supply + - iovcc-supply + +examples: + - | + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "rocktech,himax8394f"; + reg = <0>; + himax,dsi-lanes = <2>; + enable-gpios = <&pca6416_1 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; + vcc-supply = <®_5v>; + iovcc-supply = <®_5v>; + }; + }; +... diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/display/panel/wks,101wx001.yaml linux-imx-phytec/Documentation/devicetree/bindings/display/panel/wks,101wx001.yaml --- linux-6.1.55/Documentation/devicetree/bindings/display/panel/wks,101wx001.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/display/panel/wks,101wx001.yaml 2024-06-19 12:33:57.256174713 +0200 @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/wks,101wx001.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: WKS 101WX001 10.1" WXGA TFT LCD panel + +description: + The WKS 101WX001 is a 10.1" WXGA (1280 x 800) TFT LCD panel with a 24-bit RGB + parallel data interface. + +maintainers: + - Robert Chiras + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: wks,101wx001 + + label: false + port: true + + vcc-supply: + description: 5v analog power regulator + + blctr-gpios: + description: GPIO used for BL_CNTR pin, controlling the panel backlight + (this is not a pwm backlight, it's only a GPIO controlled + backlight) + maxItems: 1 + + pinctrl-assert-gpios: + description: Default states for various gpios used as selectors for on-board + muxes + +required: + - compatible + - port + +additionalProperties: false + +examples: + - | + #include + panel { + compatible = "wks,101wx001"; + blctr-gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&gpiob 3 GPIO_ACTIVE_LOW>, + <&gpiob 4 GPIO_ACTIVE_LOW>, + <&gpiob 6 GPIO_ACTIVE_LOW>, + <&gpiob 7 GPIO_ACTIVE_LOW>, + <&gpiob 8 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt linux-imx-phytec/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt --- linux-6.1.55/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt 2024-06-19 12:33:57.264174850 +0200 @@ -0,0 +1,128 @@ +* Freescale enhanced Direct Memory Access(eDMA-v3) Controller + + The eDMA-v3 controller is inherited from FSL eDMA, and firstly is intergrated + on Freescale i.MX8QM SOC chip. The eDMA channels have multiplex capability by + programmble memory-mapped registers. Specific DMA request source has fixed channel. + +* eDMA Controller +Required properties: +- compatible : + - "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8QM SoC + - "fsl,imx8qm-adma" for audio eDMA used on i.MX8QM + - "fsl,imx8ulp-edma" for eDMA used on i.MX8ULP + - "fsl,imx93-edma" for eDMA used on i.MX93 +- reg : Specifies base physical address(s) and size of the eDMA channel registers. + Each eDMA channel has separated register's address and size. The first one + is Manage Page address space. +- interrupts : A list of interrupt-specifiers, each channel has one interrupt. +- interrupt-names : Should contain below template: + "edmaX-chanX-Xx" + | | |---> receive/transmit, r or t + | |---> channel id, the max number is 32 + |---> edma controller instance, 0, 1, 2,..etc + +- #dma-cells : Must be <3>. + The 1st cell specifies the source ID. + The 2nd cell specifies the channel priority. + The 3rd cell specifies the channel attributes which include below: + BIT(0): transmit or receive: + 0: transmit, 1: receive. + BIT(1): local or remote access: + 0: local, 1: remote. + BIT(2): multiple fifo case or not(only in Audio cyclic now): + 0: not multiple fifo case, 1: multiple fifo case. + See the SoC's reference manual for all the supported request sources. +- dma-channels : Number of channels supported by the controller + +Optional properties : +- power-domains : Power domains for edma channel used. +- power-domain-names : Power domains name for edma channel used. +- clocks : A list of phandle and clock-specifier pairs, one for each entry in + clock-names. The first one is for Manage Page +- clock-names : A list of channel clock names. +- fsl,edma-axi : The bus type is AXI. + +Examples: +edma0: dma-controller@40018000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <4>; + interrupts = , + , + , + ; + interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan14-rx", "edma0-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>; + power-domain-names = "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15"; + status = "okay"; +}; + +or i.mx8ulp: + edma1: dma-controller@29010000 { + compatible = "fsl,imx8ulp-edma"; + reg = <0x29010000 0x10000>, + <0x29020000 0x10000>, + <0x29030000 0x10000>; + #dma-cells = <3>; + dma-channels = <2>; + interrupts = , + ; + interrupt-names = "edma1-chan0-tx", + "edma1-chan1-tx"; + clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, + <&pcc3 IMX8ULP_CLK_DMA1_CH0>, + <&pcc3 IMX8ULP_CLK_DMA1_CH1>; + clock-names = "edma-mp-clk", + "edma1-chan0-clk", + "edma1-chan1-clk"; + status = "okay"; + }; + +* DMA clients +DMA client drivers that uses the DMA function must use the format described +in the dma.txt file, using a three-cell specifier for each channel: the 1st +specifies the channel number, the 2nd specifies the priority, and the 3rd +specifies the channel type is for transmit or receive: 0: transmit, 1: receive. + +Examples: +lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART1_CLK>; + clock-names = "ipg"; + assigned-clock-names = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_1>, + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma0 15 0 0>, + <&edma0 14 0 1>; + status = "disabled"; +}; + +or i.mx8ulp: +lpuart5: serial@293a0000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x293a0000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_LPOSC>; + assigned-clock-rates = <24000000>; + dmas = <&edma1 58 0 0>, <&edma1 57 0 1>; + dma-names = "tx","rx"; + + status = "okay"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/dma/fsl,edma.yaml linux-imx-phytec/Documentation/devicetree/bindings/dma/fsl,edma.yaml --- linux-6.1.55/Documentation/devicetree/bindings/dma/fsl,edma.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/dma/fsl,edma.yaml 2024-06-19 12:33:57.264174850 +0200 @@ -21,6 +21,7 @@ - enum: - fsl,vf610-edma - fsl,imx7ulp-edma + - fsl,s32v234-edma - items: - const: fsl,ls1028a-edma - const: fsl,vf610-edma @@ -153,3 +154,25 @@ clock-names = "dma", "dmamux0"; clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; }; + + - | + #include + #include + edma: dma-controller@40002000 { + #dma-cells = <2>; + compatible = "fsl,s32v234-edma"; + reg = <0x0 0x40002000 0x0 0x2000>, + <0x0 0x40031000 0x0 0x1000>, + <0x0 0x400A1000 0x0 0x1000>; + dma-channels = <32>; + interrupts = , + , + ; + interrupt-names = "edma-tx_0-15", + "edma-tx_16-31", + "edma-err"; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clks S32V234_CLK_SYS6>, + <&clks S32V234_CLK_SYS6>; + }; /* S32V234 */ + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt linux-imx-phytec/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt --- linux-6.1.55/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt 2024-06-19 12:33:57.264174850 +0200 @@ -18,6 +18,21 @@ - dma-requests : Number of DMA requests supported. - #dma-requests : deprecated +* DMA capability limitation + +Specify the DMA capability limitations. +For example, some SoCs only support up to 32bit DMA capability, although +they are 64bit SoCs. + +- only-dma-mask32: 1 means that the SoCs only suppot up to 32bit DMA + capability. + +Example: + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + Example: dma: dma@10001000 { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt linux-imx-phytec/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt --- linux-6.1.55/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt 2024-06-19 12:33:57.264174850 +0200 @@ -9,6 +9,7 @@ "fsl,imx53-sdma" "fsl,imx6q-sdma" "fsl,imx7d-sdma" + "fsl,imx6sx-sdma" "fsl,imx6ul-sdma" "fsl,imx8mq-sdma" "fsl,imx8mm-sdma" @@ -55,8 +56,12 @@ 22 SSI Dual FIFO (needs firmware ver >= 2) 23 Shared ASRC 24 SAI - -The third cell specifies the transfer priority as below. + 25 HDMI Audio +The third cell specifies the transfer priority and software done +as below. + Bit31: sw_done + Bit15~Bit8: selector + Bit7~Bit0: priority level ID transfer priority ------------------------- @@ -64,6 +69,9 @@ 1 Medium 2 Low +For example: 0x80000000 means sw_done enabled for done0 sector and +High priority for PDM on i.mx8mm. + Optional properties: - gpr : The phandle to the General Purpose Register (GPR) node. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/gpio/fsl,qixis-cpld-gpio.yaml linux-imx-phytec/Documentation/devicetree/bindings/gpio/fsl,qixis-cpld-gpio.yaml --- linux-6.1.55/Documentation/devicetree/bindings/gpio/fsl,qixis-cpld-gpio.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/gpio/fsl,qixis-cpld-gpio.yaml 2024-06-19 12:33:57.272174987 +0200 @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/fsl,qixis-cpld-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO controller embedded in the NXP LX2160A-RDB QIXIS CPLD + +maintainers: + - Ioana Ciornei + +description: | + This module is part of the QIXIS CPLD found on some Layerscape boards such as LX2160ARDB. + For more details see ../mfd/fsl,qixis-cpld.yaml. + + Each controller supports a maximum of 8 GPIO lines and each line has fixed + direction which cannot be changed using a direction register. + +properties: + compatible: + enum: + - fsl,lx2160a-rdb-qixis-cpld-gpio + + reg: + maxItems: 1 + + "#gpio-cells": + const: 2 + + gpio-controller: true + + gpio-line-names: + minItems: 1 + maxItems: 8 + +required: + - compatible + - "#gpio-cells" + - gpio-controller + +additionalProperties: false diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt linux-imx-phytec/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt --- linux-6.1.55/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt 2024-06-19 12:33:57.272174987 +0200 @@ -0,0 +1,57 @@ +Device-Tree bindings for drivers/gpio/gpio-imx-rpmsg.c gpio driver over +rpmsg. On i.mx7ULP PTA PTB are connected on M4 side, so rpmsg gpio driver +needed to get/set gpio status from M4 side by rpmsg. + +Required properties: +- compatible : Should be "fsl,imx-rpmsg-gpio". +- port_idx : Specify the GPIO PORT index, PTA:0, PTB:1. +- gpio-controller : Mark the device node as a gpio controller. +- #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells : Should be 2. The first cell is the GPIO number. + The second cell bits[3:0] is used to specify trigger type and level flags: + 1 = low-to-high edge triggered. + 2 = high-to-low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. + +Note: Each GPIO port should have an alias correctly numbered in "aliases" +node. + +Examples: + +aliases { + gpio4 = &rpmsg_gpio0; + gpio5 = &rpmsg_gpio1; +}; + +rpmsg_gpio0: rpmsg-gpio0 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <0>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio0>; + status = "okay"; +}; + +rpmsg_gpio1: rpmsg-gpio1 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <1>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio1>; + status = "okay"; +}; + +&skeleton_node { + interrupt-parent = <&rpmsg_gpio1>; + interrupts = <7 2>; + wakeup-gpios = <&rpmsg_gpio1 7 GPIO_ACTIVE_LOW>; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml linux-imx-phytec/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml --- linux-6.1.55/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml 2024-06-19 12:33:57.272174987 +0200 @@ -102,6 +102,10 @@ wakeup-source: $ref: /schemas/types.yaml#/definitions/flag + out-default: + description: + set the output IO default voltage. Exp: out-default = /bits/ 16 ; + patternProperties: "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$": type: object diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/gpu/vivante,gc.yaml linux-imx-phytec/Documentation/devicetree/bindings/gpu/vivante,gc.yaml --- linux-6.1.55/Documentation/devicetree/bindings/gpu/vivante,gc.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/gpu/vivante,gc.yaml 2024-06-19 12:33:57.276175055 +0200 @@ -13,7 +13,19 @@ properties: compatible: - const: vivante,gc + items: + - enum: + - fsl,imx6q-gpu + - fsl,imx8-gpu + - fsl,imx8-gpu-ss + - fsl,imx8mm-gpu + - fsl,imx8mn-gpu + - fsl,imx8mp-gpu + - fsl,imx8mq-gpu + - fsl,imx8qm-gpu + - fsl,imx8qxp-gpu + - fsl,ls1028a-gpu + - const: vivante,gc reg: maxItems: 1 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/i2c/i2c-imx-flexio.yaml linux-imx-phytec/Documentation/devicetree/bindings/i2c/i2c-imx-flexio.yaml --- linux-6.1.55/Documentation/devicetree/bindings/i2c/i2c-imx-flexio.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/i2c/i2c-imx-flexio.yaml 2024-06-19 12:33:57.280175123 +0200 @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-imx-flexio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP iMX Flexible Input/Output (FlexIO) I2C Mode + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + items: + - const: nxp,imx-flexio-i2c-master + + clock-frequency: + minimun: 1 + default: 100000 + maximum: 400000 + + sda: + maxItems: 1 + + scl: + maxItems: 1 + +required: + - compatible + - clock-frequency + - sda + - scl + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include + + i2c-master { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx-flexio-i2c-master"; + clock-frequency = <100000>; + sda = /bits/ 8 <0xa>; + scl = /bits/ 8 <0xb>; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/i2c/i2c-rpmsg-imx.txt linux-imx-phytec/Documentation/devicetree/bindings/i2c/i2c-rpmsg-imx.txt --- linux-6.1.55/Documentation/devicetree/bindings/i2c/i2c-rpmsg-imx.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/i2c/i2c-rpmsg-imx.txt 2024-06-19 12:33:57.284175192 +0200 @@ -0,0 +1,29 @@ +* Freescale Virtual I2C RPMSG bus driver for i.MX + +Required properties: +- compatible : + - "fsl,i2c-rpbus" for I2C bus over RPMSG compatible on i.MX8QXP/QM soc +The i2c-rpbus node should define its bus id (which is the node communicating +with M4) in alias. + +Examples: + +aliases { + ... + i2c1 = &i2c_rpbus_1; + ... +}; + +&i2c_rpbus_1 { + compatible = "fsl,i2c-rpbus"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + devs_in_this_i2c_bus__for_example: pca6416@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml linux-imx-phytec/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml --- linux-6.1.55/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml 2024-06-19 12:33:57.284175192 +0200 @@ -14,12 +14,18 @@ SPI and I2C interface. https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf + https://www.nxp.com/docs/en/data-sheet/FXLS8967AF.pdf + https://www.nxp.com/docs/en/data-sheet/FXLS8974CF.pdf properties: compatible: + description: + These chips are compatible with each other, just have different IDs. enum: - nxp,fxls8962af - nxp,fxls8964af + - nxp,fxls8967af + - nxp,fxls8974cf reg: maxItems: 1 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/iio/imu/nxp,rpmsg_iio_pedometer.yaml linux-imx-phytec/Documentation/devicetree/bindings/iio/imu/nxp,rpmsg_iio_pedometer.yaml --- linux-6.1.55/Documentation/devicetree/bindings/iio/imu/nxp,rpmsg_iio_pedometer.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/iio/imu/nxp,rpmsg_iio_pedometer.yaml 2024-06-19 12:33:57.296175397 +0200 @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/imu/nxp,rpmsg_iio_pedometer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP virtual pedometer sensor through rpmsg + +maintainers: + - Haibo Chen + +description: | + For NXP iMX7ULP/iMX8ULP evk board, some sensors connect with M4 core, + A core has to communicate with sensors through virtual IO bus like + RPMSG. + +properties: + compatible: + enum: + - nxp,rpmsg-iio-pedometer + +required: + - compatible + +additionalProperties: false + +examples: + - | + rpmsg_sensor:rpmsg-sensor { + compatible = "nxp,rpmsg-iio-pedometer"; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/input/rpmsg-keys.txt linux-imx-phytec/Documentation/devicetree/bindings/input/rpmsg-keys.txt --- linux-6.1.55/Documentation/devicetree/bindings/input/rpmsg-keys.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/input/rpmsg-keys.txt 2024-06-19 12:33:57.304175534 +0200 @@ -0,0 +1,33 @@ +Device-Tree bindings for input/keyboard/rpmsg-keys.c keys driver over +rpmsg. On i.mx7ULP keys are connected on M4 side, so rpmsg-keys driver +needed to get the key status from M4 side by rpmsg. + +Required properties: + - compatible = "fsl,rpmsg-keys"; + +Each button/key looked as the sub node: +Required properties: + - label: the key name + - linux,code: the key value defined in + include/dt-bindings/input/input.h +Optional property: + - rpmsg-key,wakeup: wakeup feature, the keys can wakeup from + suspend if the keys with this property pressed. + +Example nodes: + rpmsg_keys: rpmsg-keys { + compatible = "fsl,rpmsg-keys"; + + volume-up { + label = "Volume Up"; + rpmsg-key,wakeup; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + rpmsg-key,wakeup; + linux,code = ; + }; + }; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt linux-imx-phytec/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt --- linux-6.1.55/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt 2024-06-19 12:33:57.304175534 +0200 @@ -0,0 +1,48 @@ +FocalTech touch controller + +The focaltech controller is connected to host processor via i2c. +The controller generates interrupts when the user touches the panel. +The host controller is expected to read the touch coordinates over +i2c and pass the coordinates to the rest of the system. + +Required properties: + - compatible : should be "focaltech,fts" + - reg : i2c slave address of the device, should be <0x38> + - interrupt-parent : parent of interrupt + - interrupts : irq gpio, "0x02" stands for that the irq triggered by falling edge. + - focaltech,irq-gpio : irq gpio, same as "interrupts" node. + - focaltech,reset-gpio : reset gpio + - focaltech,num-max-touches : maximum number of touches support + - focaltech,display-coords : display resolution in pixels. A four tuple consisting of minX, minY, maxX and maxY. + +Optional properties: + - focaltech,have-key : specify if virtual keys are supported + - focaltech,key-number : number of keys + - focaltech,keys : virtual key codes mapping to the coords + - focaltech,key-y-coord : constant y coordinate of keys, depends on the y resolution + - focaltech,key-x-coords : constant x coordinates of keys, depends on the x resolution + - focaltech,swap-xy : swap x-y coordinates + - focaltech,panel-type : set panel type, default is FT5416 panel + - focaltech,scaling-down-half : scale down the x-y coordiantes to half + + +Example: + i2c@f9927000 { + focaltech@38{ + compatible = "focaltech,fts"; + reg = <0x38>; + interrupt-parent = <&msm_gpio>; + interrupts = <13 0x02>; + focaltech,reset-gpio = <&msm_gpio 12 0x01>; + focaltech,irq-gpio = <&msm_gpio 13 0x02>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 1920>; + + focaltech,have-key; + focaltech,key-number = <3>; + focaltech,keys = <139 102 158>; + focaltech,key-y-coord = <2000>; + focaltech,key-x-coords = <200 600 800>; + focaltech,swap-xy; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt linux-imx-phytec/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt --- linux-6.1.55/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt 2024-06-19 12:33:57.308175603 +0200 @@ -0,0 +1,18 @@ +* VTL Touchscreen Controller + +Required properties: +- compatible: must be "vtl,ct365" +- reg: i2c slave address +- interrupt-parent: the phandle for the interrupt controller +- interrupts: touch controller interrupt +- gpios: the gpio pin to be used for reset + +Example: + + touchscreen@01 { + compatible = "vtl,ct365"; + reg = <0x01>; + interrupt-parent = <&gpio6>; + interrupts = <14 0>; + gpios = <&gpio4 10 0>; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/leds/leds-pca995x.txt linux-imx-phytec/Documentation/devicetree/bindings/leds/leds-pca995x.txt --- linux-6.1.55/Documentation/devicetree/bindings/leds/leds-pca995x.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/leds/leds-pca995x.txt 2024-06-19 12:33:57.320175808 +0200 @@ -0,0 +1,91 @@ +* NXP - pca995x LED driver + +The PCA995x family of chips are I2C-bus controlled 16-channel +constant current LED driver optimized for dimming and blinking +57 mA Red/Green/Blue/Amber (RGBA) LEDs. +Note that the top side markings of the pca995x chips are PCA9952 +and PCA9955. + +Required properties: +- compatible : should be one of : + "nxp,pca9955btw" + "nxp,pca995xtw" +- #address-cells: must be 1 +- #size-cells: must be 0 +- reg: I2C slave address. depends on the model and HW connections. + +Optional properties: +- reset-gpios: use a GPIO to control the reset line of the chip. + +LED sub-node properties: +- reg : number of LED line. + from 0 to 15 for the both pca9955btw & pca995xtw +- label : (optional) + see Documentation/devicetree/bindings/leds/common.txt +- linux,default-trigger : (optional) + see Documentation/devicetree/bindings/leds/common.txt + +Examples: + +/* TechNexion's voice HAT board */ +pca995tw: pca995xtw@60 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca995xtw"; + reset-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; + reg = <0x60>; + + led0 { + label = "blue0"; + linux,default-trigger = "none"; + reg = <0>; + }; + + led1 { + label = "green0"; + linux,default-trigger = "none"; + reg = <1>; + }; + + led2 { + label = "red0"; + linux,default-trigger = "none"; + reg = <2>; + }; +}; + +/* NXP's 8MIC board */ +pca995btw: pca995btw@7 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca995btw"; + reg = <0x07>; + + led0 { + label = "green0"; + linux,default-trigger = "none"; + reg = <0>; + }; + + led1 { + label = "blue0"; + linux,default-trigger = "none"; + reg = <1>; + }; + + led2 { + label = "red0"; + linux,default-trigger = "none"; + reg = <2>; + }; + + led3 { + label = "green1"; + linux,default-trigger = "none"; + reg = <3>; + }; +}; + +For more information please check the information bellow: +https://www.nxp.com/docs/en/data-sheet/PCA9952_PCA9955.pdf +https://www.nxp.com/docs/en/data-sheet/PCA9955B.pdf \ No newline at end of file diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml linux-imx-phytec/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml --- linux-6.1.55/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml 2024-06-19 12:33:57.320175808 +0200 @@ -29,8 +29,8 @@ - const: fsl,imx8ulp-mu - const: fsl,imx8-mu-scu - const: fsl,imx8-mu-seco - - const: fsl,imx93-mu-s4 - const: fsl,imx8ulp-mu-s4 + - const: fsl,imx93-mu-s4 - items: - const: fsl,imx93-mu - const: fsl,imx8ulp-mu @@ -51,7 +51,9 @@ - fsl,imx8qm-mu - fsl,imx8qxp-mu - const: fsl,imx6sx-mu - + - description: To communicate with i.MX8 SECO with fast IPC + items: + - const: fsl,imx8-mu-seco reg: maxItems: 1 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/media/imx8-isi.txt linux-imx-phytec/Documentation/devicetree/bindings/media/imx8-isi.txt --- linux-6.1.55/Documentation/devicetree/bindings/media/imx8-isi.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/media/imx8-isi.txt 2024-06-19 12:33:57.328175945 +0200 @@ -0,0 +1,33 @@ +NXP Image Sensor Interface +======================== + +The Image Sensor Interface (ISI) is used to obtain the image data for +processing in its pipeline channels. Each pipeline processes the image +line from a configured source and performs one or more functions that +are configured by software, such as down scaling, color space conversion, +de-interlacing, alpha insertion, cropping and rotation (horizontal and +vertical). The processed image is stored into programmable memory locations. + +Required properties: +- compatible: should be "fsl,imx8-isi", where SoC can be one of imx8qxp, imx8qm +- reg: the register base and size for the device registers +- interrupts: the ISI interrupt, high level active +- clock-names: should be "per" +- clocks: the ISI AXI clock +- interface: specify ISI input, virtual channel and output, + + Input : 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx : 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM + +Example: + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x58100000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&img_lpcg IMX_IMG_LPCG_PDMA0_CLK>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + interface = <2 0 2>; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/media/imx8-media-dev.txt linux-imx-phytec/Documentation/devicetree/bindings/media/imx8-media-dev.txt --- linux-6.1.55/Documentation/devicetree/bindings/media/imx8-media-dev.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/media/imx8-media-dev.txt 2024-06-19 12:33:57.328175945 +0200 @@ -0,0 +1,38 @@ +Virtual Media device +------------------------------- + +Virtual Media device is used to manage all modules in image capture subsystem +of imx8qxp/qm platform. ISI(Image Sensor Interface), MIPI CSI, Parallel CSI +device node should be under it. + +Required properties: + - compatible : must be "fsl,mxc-md"; + - reg : Must contain an entry for each entry in reg-names; + - #address-cells: should be <1>; + - #size-cells : should be <1>; + - ranges : use to handle address space + +Optional properties: + - parallel_csi: indicate that camera sensor use parallel interface + + + +For example: + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x58100000 0x10000>; + ... + }; + csi@58227000 { + compatible = "fsl,mxc-mipi-csi2"; + ... + }; + ... + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt linux-imx-phytec/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt --- linux-6.1.55/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt 2024-06-19 12:33:57.328175945 +0200 @@ -0,0 +1,73 @@ +Freescale i.MX8QXP/QM MIPI CSI2 +========================= + +mipi_csi2 node +-------------- + +This is the device node for the MIPI CSI-2 receiver core in i.MXQXP/QM SoC. + +Required properties: + +- compatible : "fsl,mxc-mipi-csi2"; +- reg : base address and length of the register set for the device; +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- clock-names : must contain "clk_core", "clk_esc" and "clk_pxl" entries, + matching entries in the clock property; +- assigned-clock-rates : the value should be 360MHz and 72MHz; +- power-domains : a phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details; +- power-domain-name : must contain "pd_csi", "pd_isi_ch0". + +Optional properties: +- virtual-channel: whether use mipi csi virtual channel + +The device node should contain one 'port' child nodes with one child 'endpoint' +node, according to the bindings defined in: + Documentation/devicetree/bindings/ media/video-interfaces.txt. + The following are properties specific to those nodes. + +port node +--------- + +- reg : (required) can take the values 0 which mean the port is a + sink port; + +endpoint node +------------- + +- data-lanes : (required) an array specifying active physical MIPI-CSI2 + data input lanes and their mapping to logical lanes; this + shall only be applied to port 0 (sink port), the array's + content is unused only its length is meaningful, + in this case the maximum length supported is 2; + +example: + + mipi_csi: csi@58227000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x58227000 0x1000>, + <0x58221000 0x1000>; + clocks = <&csi_lpcg IMX_CSI_LPCG_CSI0_CORE_CLK>, + <&csi_lpcg IMX_CSI_LPCG_CSI0_ESC_CLK>, + <&img_lpcg IMX_IMG_LPCG_CSI0_PXL_LINK_CLK>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&csi_lpcg IMX_CSI_LPCG_CSI0_CORE_CLK>, + <&csi_lpcg IMX_CSI_LPCG_CSI0_ESC_CLK>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; + + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/media/imx8-parallel-csi.txt linux-imx-phytec/Documentation/devicetree/bindings/media/imx8-parallel-csi.txt --- linux-6.1.55/Documentation/devicetree/bindings/media/imx8-parallel-csi.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/media/imx8-parallel-csi.txt 2024-06-19 12:33:57.328175945 +0200 @@ -0,0 +1,48 @@ +Freescale i.MX8QXP Parallel Capture Interface +========================= + +parallel interface node +-------------- + +This is the device node for the parallel capture interface in i.MX8QXP SoC. + +Required properties: +- compatible : "fsl,mxc-parallel-csi"; +- reg : base address and length of the register set for the device; +- clocks : list of clock specifiers +- clock-names : must contain "pixel", "ipg", "div" and "dpll" entries, + matching entries in the clock property; +- assigned-clocks : need to set the parent of pixel clock; +- assigned-clock-parent: set the pll as the parent of pixel clock; +- assigned-clock-rates : the value should be 160MHz; +- power-domains : a phandle to the power domain, see +- power-domain-name : must contain "pd_pi", "pd_isi_ch0". + +port node +- reg : can take the values 0 which mean the port is a sink port + +example: + parallel_csi: pcsi@58261000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,mxc-parallel-csi"; + reg = <0x58261000 0x1000>; + clocks = <&pi_lpcg IMX_PI_LPCG_PI0_PIXEL_CLK>, + <&pi_lpcg IMX_PI_LPCG_PI0_IPG_CLK>, + <&clk IMX_PARALLEL_PER_DIV_CLK>, + <&clk IMX_PARALLEL_DPLL_CLK>; + clock-names = "pixel", "ipg", "div", "dpll"; + assigned-clocks = <&clk IMX_PARALLEL_PER_DIV_CLK>; + assigned-clock-parents = <&clk IMX_PARALLEL_DPLL_CLK>; + assigned-clock-rates = <160000000>; /* 160MHz */ + power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_pi", "pd_isi_ch0"; + + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml linux-imx-phytec/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml --- linux-6.1.55/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml 2024-06-19 12:33:57.332176013 +0200 @@ -40,6 +40,7 @@ - fsl,p1021-memory-controller - fsl,p2020-memory-controller - fsl,qoriq-memory-controller + - nxp,imx9-memory-controller interrupts: maxItems: 1 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/mfd/fsl,qixis-cpld.yaml linux-imx-phytec/Documentation/devicetree/bindings/mfd/fsl,qixis-cpld.yaml --- linux-6.1.55/Documentation/devicetree/bindings/mfd/fsl,qixis-cpld.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/mfd/fsl,qixis-cpld.yaml 2024-06-19 12:33:57.336176081 +0200 @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/fsl,qixis-cpld.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP's QIXIS CPLD board management controller + +maintainers: + - Ioana Ciornei + +description: | + The board management controller found on some Layerscape boards contains + different IP blocks like GPIO controllers, interrupt controllers, reg-muxes + etc. + +properties: + compatible: + enum: + - fsl,lx2160a-qds-qixis-cpld + - fsl,lx2160a-rdb-qixis-cpld + + reg: + description: + I2C device address. + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^gpio(@[0-9a-f]+)?$": + $ref: ../gpio/fsl,qixis-cpld-gpio.yaml + +required: + - "#address-cells" + - "#size-cells" + - compatible + - reg + +additionalProperties: false + +examples: + - | + qixis@66 { + compatible = "fsl,lx2160a-rdb-qixis-cpld"; + reg = <0x66>; + #address-cells = <1>; + #size-cells = <0>; + + sfp2_csr: gpio@19 { + compatible = "fsl,lx2160a-rdb-qixis-cpld-gpio"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SFP2_TX_EN", "", + "", "", + "SFP2_RX_LOS", "SFP2_TX_FAULT", + "", "SFP2_MOD_ABS"; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/mfd/maxim,max96752.yaml linux-imx-phytec/Documentation/devicetree/bindings/mfd/maxim,max96752.yaml --- linux-6.1.55/Documentation/devicetree/bindings/mfd/maxim,max96752.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/mfd/maxim,max96752.yaml 2024-06-19 12:33:57.340176150 +0200 @@ -0,0 +1,195 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/maxim,max96752.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX96752 deserializer chip + +maintainers: + - Laurentiu Palcu + +description: | + The MAX96752/MAX96754 deserializers convert a single or dual-link GMSL serial input to single or + dual OLDI. They also send and receive side-channel and peripheral control data, enabling + full-duplex, single-wire transmission of video and bidirectional data, like I2S stereo audio + channels. + +properties: + compatible: + enum: + - maxim,max96752 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + description: | + The deserializer default I2C address can be overwritten to avoid collisions when more of the + same deserializers are used. + minItems: 1 + maxItems: 2 + + maxim,gmsl2-link-speed: + description: | + Specifies the link speed for the GMSL2 links: + 3 - 3Gbps GMSL2 link speed + 6 - 6Gbps GMSL2 link speed + If omitted, pin configuration will be used. + $ref: /schemas/types.yaml#/definitions/int32 + enum: [3, 6] + + maxim,gmsl2-dual-link: + description: | + Activate dual-link mode. This is useful if both GMSL connections go to the same remote device + and we want to benefit from the increased GMSL bandwidth for transmiting higher resolution + video streams. + type: boolean + + gpio-config: + description: | + The MAX96752 can replicate the transitions on a local GPIO input pin to a remote GPIO output + pin on the serializer chip or a remote GPIO input pin to a local GPIO output pin. Hence, + each GPIO pin will be a port with a remote-endpoint that will point to the remote chip GPIO + pin. + type: object + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^port@[0-9a-f]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: This is a GPIO tunnel. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + maxim,pin_config: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: GPIO pin configuration + items: + - description: Pin direction (0 - output, 1 - input) + - description: Pull resistor type (0 - no pull resistor, 1 - pull-up, 2 - pull-down) + - description: Pull strength (0 - 40Kohm, 1 - 1Mohm) + + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + description: | + Serializer GPIO pin that the local pin is linked to. If missing, the GPIO is just + a local driven GPIO. + + additionalProperties: false + + required: + - "#address-cells" + - "#size-cells" + - reg + - maxim,pin_config + + required: + - "#address-cells" + - "#size-cells" + + additionalProperties: false + + i2c-gate: + description: | + The deserializer can cut-off the local I2C bus to avoid address collision in dual-display + configurations when a serializer connects to 2 deserializers which have the same peripherals + connected on the same I2C bus. + $ref: /schemas/i2c/i2c-gate.yaml# + unevaluatedProperties: false + + max96752_lvds_bridge: + description: The LVDS video bridge. + type: object + $ref: /schemas/display/bridge/maxim,max96752-lvds-bridge.yaml + unevaluatedProperties: false + +required: + - compatible + - '#address-cells' + - '#size-cells' + - i2c-gate + +additionalProperties: false + +examples: + - | + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + max96752: mipi_dsi_deserializer@48 { + + #address-cells = <1>; + #size-cells = <0>; + + compatible = "maxim,max96752"; + reg = <0x48>, <0x49>; + + maxim,gmsl2-link-speed = <6>; + maxim,gmsl2-dual-link; + + max96752_lvds_bridge { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "maxim,max96752-lvds"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + max96752_video_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&max96789_video_out>; + }; + + max96752_lvds_a_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&it6263_in>; + }; + }; + }; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_in: endpoint { + remote-endpoint = <&max96752_lvds_a_out>; + }; + }; + }; + }; + }; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/mfd/maxim,max96789.yaml linux-imx-phytec/Documentation/devicetree/bindings/mfd/maxim,max96789.yaml --- linux-6.1.55/Documentation/devicetree/bindings/mfd/maxim,max96789.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/mfd/maxim,max96789.yaml 2024-06-19 12:33:57.340176150 +0200 @@ -0,0 +1,257 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/maxim,max96789.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX96789 serializer chip + +maintainers: + - Laurentiu Palcu + +description: | + The MAX96789/MAX96791 family of serializers convert dual MIPI DSI, four-lane input port data to + dual Maxim Integrated’s GMSL 1 or 2 high-speed serial link protocol. They also send and receive + side-channel and peripheral control data, enabling full-duplex, single-wire, transmission of video + and bidirectional data, like I2S stereo audio channels. + +properties: + compatible: + enum: + - maxim,max96789 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + + v12p0-supply: + description: Regulator that provides 12V power supply. + + maxim,gmsl-links-types: + description: | + Specifies the link types for each of the 2 GMSL ports. The device supports GMSL links of type + 1 and 2. If ommited, the pin configuration will be used instead. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - enum: [1, 2] + - enum: [1, 2] + + maxim,gmsl2-link-speed: + description: | + Specifies the link speed for the GMSL2 links: + 3 - 3Gbps GMSL2 link speed + 6 - 6Gbps GMSL2 link speed + If omitted, pin configuration will be used. + $ref: /schemas/types.yaml#/definitions/int32 + enum: [3, 6] + + maxim,gmsl2-dual-link: + description: | + Activate dual-link mode. This is useful if both GMSL connections go to the same remote device + and we want to benefit from the increased GMSL bandwidth for transmiting higher resolution + video streams. + type: boolean + + gpio-config: + description: | + The MAX96789 can replicate the transitions on a local GPIO input pin to a remote GPIO output + pin on the deserializer chip or a remote GPIO input pin to a local GPIO output pin. Hence, + each GPIO pin will be a port with a remote-endpoint that will point to the remote chip GPIO + pin. + type: object + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^port@[0-9a-f]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: This is a GPIO tunnel. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + maxim,pin_config: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: GPIO pin configuration + items: + - description: Pin direction (0 - output, 1 - input) + - description: Pull resistor type (0 - no pull resistor, 1 - pull-up, 2 - pull-down) + - description: Pull strength (0 - 40Kohm, 1 - 1Mohm) + + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + description: | + Deserializer GPIO pin that the local pin is linked to. If missing, the GPIO is just + a local driven GPIO. + + additionalProperties: false + + required: + - "#address-cells" + - "#size-cells" + - reg + - maxim,pin_config + + required: + - "#address-cells" + - "#size-cells" + + additionalProperties: false + + i2c-mux: + description: | + Each GMSL link is modelled as a child bus of an i2c bus multiplexer/switch as the device + extends the I2C bus to the remote deserializer chip. + type: object + $ref: /schemas/i2c/i2c-mux.yaml# + unevaluatedProperties: false + + patternProperties: + '^i2c@[01]$': + type: object + description: | + Child node of the I2C bus multiplexer that represents a GMSL link to a deserializer + device. The MAX96789 chip supports up to 2 GMSL links. + + properties: + reg: + description: The index of the GMSL channel. + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + required: + - reg + - '#address-cells' + - '#size-cells' + + additionalProperties: true + +patternProperties: + '^max96789_dsi_bridge@[01]$': + description: The DSI video bridge. + type: object + $ref: /schemas/display/bridge/maxim,max96789-dsi-bridge.yaml + unevaluatedProperties: false + +required: + - compatible + - '#address-cells' + - '#size-cells' + - i2c-mux + +additionalProperties: false + +examples: + - | + i2c@57226000 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0x57226000 0x1000>; + + max96789: mipi_dsi_serializer@40 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "maxim,max96789"; + reg = <0x40>; + status = "okay"; + + maxim,gmsl-links-types = <2 2>; + maxim,gmsl2-link-speed = <6>; + maxim,gmsl2-dual-link; + + /* DSI port 1 */ + max96789_dsi_bridge@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + compatible = "maxim,max96789-dsi"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + max96789_dsi_b_in: endpoint@0 { + reg = <0>; + + remote-endpoint = <&mipi0_out>; + data-lanes = <1 2 3 4>; + }; + + max96789_video_out: endpoint@1 { + reg = <1>; + + remote-endpoint = <&max96752_video_in>; + }; + }; + }; + + gpio-config { + #address-cells = <1>; + #size-cells = <0>; + + port@a { + #address-cells = <1>; + #size-cells = <0>; + + reg = <10>; + + /* input, pull-down, 1Mohm */ + maxim,pin_config = <1 2 1>; + + max96789_dsi_b_pwm: endpoint { + remote-endpoint = <&max96752_lvds_a_pwm>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + /* gmsl a */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + max96752: mipi_dsi_deserializer@48 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "maxim,max96752"; + reg = <0x48>; + + i2c-gate { + }; + }; + }; + }; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/mfd/nxp,imx8ulp-sim.yaml linux-imx-phytec/Documentation/devicetree/bindings/mfd/nxp,imx8ulp-sim.yaml --- linux-6.1.55/Documentation/devicetree/bindings/mfd/nxp,imx8ulp-sim.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/mfd/nxp,imx8ulp-sim.yaml 2024-06-19 12:33:57.340176150 +0200 @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/nxp,imx8ulp-sim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ulp System Integration Module Bindings + +maintainers: + - Liu Ying + +description: | + The System Integration Module (SIM) provides system control and chip + configuration registers. One typical use-case is for some other nodes to + acquire a reference to the syscon node by phandle, and the other typical + use-case is that the operating system should consider all subnodes of the + SIM module as separate child devices. + +properties: + $nodename: + pattern: "^syscon@[0-9a-f]+$" + + compatible: + items: + - enum: + - nxp,imx8ulp-avd-sim + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +patternProperties: + "^(reset-controller|mux-controller)$": + type: object + description: The possible child devices of the SIM module. + +required: + - compatible + - reg + - clocks + +allOf: + - if: + properties: + compatible: + contains: + const: nxp,imx8ulp-avd-sim + then: + required: + - reset-controller + - mux-controller + +additionalProperties: false + +examples: + - | + #include + syscon@2da50000 { + compatible = "nxp,imx8ulp-avd-sim", "syscon", "simple-mfd"; + reg = <0x2da50000 0x38>; + clocks = <&pcc5 IMX8ULP_CLK_AVD_SIM>; + + reset-controller { + compatible = "nxp,imx8ulp-avd-sim-reset"; + #reset-cells = <1>; + }; + + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/mfd/nxp,imx-flexio.yaml linux-imx-phytec/Documentation/devicetree/bindings/mfd/nxp,imx-flexio.yaml --- linux-6.1.55/Documentation/devicetree/bindings/mfd/nxp,imx-flexio.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/mfd/nxp,imx-flexio.yaml 2024-06-19 12:33:57.340176150 +0200 @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/nxp,imx-flexio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP iMX Flexible Input/Output (FlexIO) + +description: | + The FlexIO is a highly configurable module providing a wide range of functionality including + Emulation of a variety of serial/parallel communication protocols + Flexible 16-bit timers with support for a variety of trigger, reset, enable and disable conditions + Programmable logic blocks allowing the implementation of digital logic functions on-chip and + configurable interaction of internal and external modules + Programmable state machine for offloading basic system control functions from CPU + +properties: + "#address-cells": true + + "#size-cells": true + + compatible: + items: + const: nxp,imx-flexio + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + + clock-names: + items: + const: ipg + minItems: 1 + +patternProperties: + "^flexio-i2c+$": + # Child node + type: object + $ref: "../i2c/i2c-imx-flexio.yaml" + description: + FlexIO I2C mode. This child node should follow the bindings specified in + Documentation/devicetree/bindings/i2c/i2c-imx-flexio.yaml. + +required: + - "#address-cells" + - "#size-cells" + - compatible + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + flexio@29350000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nxp,imx-flexio"; + reg = <0x29350000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_FLEXIO1>, <&pcc3 IMX8ULP_CLK_FLEXIO1>; + clock-names = "per", "ipg"; + + i2c-master { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx-flexio-i2c-master"; + clock-frequency = <100000>; + sda = /bits/ 8 <0xa>; + scl = /bits/ 8 <0xb>; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/mlb/mxc_mlb.txt linux-imx-phytec/Documentation/devicetree/bindings/mlb/mxc_mlb.txt --- linux-6.1.55/Documentation/devicetree/bindings/mlb/mxc_mlb.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/mlb/mxc_mlb.txt 2024-06-19 12:33:57.348176286 +0200 @@ -0,0 +1,27 @@ +*MediaLB (MLB) for i.MX + +Required properties: +- compatible : + - "fsl,imx6sx-mlb50" for MLB compatible with the one integrated on i.MX6SX soc + - "fsl,imx6q-mlb150" for MLB compatible with the one integrated on i.MX6Q + - "fsl,imx8qxp-mlb150" for MLB compatible with the one integrated on i.MX8 soc +- reg : address and length for mlb registers +- interrupt-parent : core interrupt controller +- interrupts : MLB Break/Error interrupt and ahb interrupt + Two ahb interrupt for imx6, ahb_int[0] and ahb_int[1] + One ahb interrupt for imx8, ahb_int[0] +- clocks : mlb clock specifier + +Examples: + +mlb: mlb@5B060000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0 0x5B060000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, + <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_MLB_CLK>, + <&clk IMX8QM_MLB_HCLK>, + <&clk IMX8QM_MLB_IPG_CLK>; + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml linux-imx-phytec/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml --- linux-6.1.55/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml 2024-06-19 12:33:57.348176286 +0200 @@ -163,6 +163,16 @@ - const: default - const: sleep + fsl,sdio-async-interrupt-enabled: + description: | + Recommend for SDIO cards that enables SDIO async interrupt for SDR104 and SDR50 + operating modes. SDIO async interrupt uses DAT[1] to signal the card's interrupt. + uSDHC tuning mechanism must use DAT[0] and CMD signals to avoid a possible + conflict and incorrect delay line calculated by the uSDHC auto tuning mechanism. + Enabling this device tree property is only recommended for layouts that are + matching the SD interface length. + type: boolean + required: - compatible - reg diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml linux-imx-phytec/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml --- linux-6.1.55/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml 2024-06-19 12:33:57.352176355 +0200 @@ -79,6 +79,10 @@ in the FCB. Thus, partitions written from Linux with this feature turned on may not be accessible by the BootROM code. + fsl,max-nand-cs: + description: | + Maximum nand cs the board can support + required: - compatible - reg diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml linux-imx-phytec/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml --- linux-6.1.55/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml 2024-06-19 12:33:57.356176423 +0200 @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/bluetooth/nxp,88w8987-bt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Bluetooth chips + +description: + This binding describes UART-attached NXP bluetooth chips. These chips + are dual-radio chips supporting WiFi and Bluetooth. The bluetooth + works on standard H4 protocol over 4-wire UART. The RTS and CTS lines + are used during FW download. To enable power save mode, the host + asserts break signal over UART-TX line to put the chip into power save + state. De-asserting break wakes up the BT chip. + +maintainers: + - Neeraj Sanjay Kale + +properties: + compatible: + enum: + - nxp,88w8987-bt + - nxp,88w8997-bt + + fw-init-baudrate: + description: + Chip baudrate after FW is downloaded and initialized. + This property depends on the module vendor's + configuration. If this property is not specified, + 115200 is set as default. + +required: + - compatible + +additionalProperties: false + +examples: + - | + serial { + bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml linux-imx-phytec/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml --- linux-6.1.55/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml 2024-06-19 12:33:57.360176492 +0200 @@ -17,6 +17,7 @@ compatible: oneOf: - enum: + - fsl,imx93-flexcan - fsl,imx8qm-flexcan - fsl,imx8mp-flexcan - fsl,imx6q-flexcan diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/net/ethernet-controller.yaml linux-imx-phytec/Documentation/devicetree/bindings/net/ethernet-controller.yaml --- linux-6.1.55/Documentation/devicetree/bindings/net/ethernet-controller.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/net/ethernet-controller.yaml 2024-06-19 12:33:57.360176492 +0200 @@ -100,9 +100,12 @@ # 10GBASE-KR, XFI, SFI - 10gbase-kr + - 25gbase-kr + - 40gbase-kr4 - usxgmii - 10gbase-r - 25gbase-r + - 10g-qxgmii phy-mode: $ref: "#/properties/phy-connection-type" @@ -154,6 +157,7 @@ enum: - auto - in-band-status + - c73 fixed-link: oneOf: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt linux-imx-phytec/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt --- linux-6.1.55/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt 2024-06-19 12:33:57.364176560 +0200 @@ -0,0 +1,199 @@ +============================================================================= +NXP Programmable Packet Forwarding Engine Device Bindings + +CONTENTS + - PFE Node + - Ethernet Node + +============================================================================= +PFE Node + +DESCRIPTION + +PFE Node has all the properties associated with Packet Forwarding Engine block. + +PROPERTIES + +- compatible + Usage: required + Value type: + Definition: Must include "fsl,pfe" + +- reg + Usage: required + Value type: + Definition: A standard property. + Specifies the offset of the following registers: + - PFE configuration registers + - DDR memory used by PFE + +- fsl,pfe-num-interfaces + Usage: required + Value type: + Definition: Must be present. Value can be either one or two. + +- interrupts + Usage: required + Value type: + Definition: Three interrupts are specified in this property. + - HIF interrupt + - HIF NO COPY interrupt + - Wake On LAN interrupt + +- interrupt-names + Usage: required + Value type: + Definition: Following strings are defined for the 3 interrupts. + "pfe_hif" - HIF interrupt + "pfe_hif_nocpy" - HIF NO COPY interrupt + "pfe_wol" - Wake On LAN interrupt + +- memory-region + Usage: required + Value type: + Definition: phandle to a node describing reserved memory used by pfe. + Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + +- fsl,pfe-scfg + Usage: required + Value type: + Definition: phandle for scfg. + +- fsl,rcpm-wakeup + Usage: required + Value type: + Definition: phandle for rcpm. + +- clocks + Usage: required + Value type: + Definition: phandle for clockgen. + +- clock-names + Usage: required + Value type: + Definition: phandle for clock name. + +EXAMPLE + +pfe: pfe@04000000 { + compatible = "fsl,pfe"; + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ + reg-names = "pfe", "pfe-ddr"; + fsl,pfe-num-interfaces = <0x2>; + interrupts = <0 172 0x4>, /* HIF interrupt */ + <0 173 0x4>, /*HIF_NOCPY interrupt */ + <0 174 0x4>; /* WoL interrupt */ + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; + memory-region = <&pfe_reserved>; + fsl,pfe-scfg = <&scfg 0>; + fsl,rcpm-wakeup = <&rcpm 0xf0000020>; + clocks = <&clockgen 4 0>; + clock-names = "pfe"; + + status = "okay"; + pfe_mac0: ethernet@0 { + }; + + pfe_mac1: ethernet@1 { + }; +}; + +============================================================================= +Ethernet Node + +DESCRIPTION + +Ethernet Node has all the properties associated with PFE used by platforms to +connect to PHY: + +PROPERTIES + +- compatible + Usage: required + Value type: + Definition: Must include "fsl,pfe-gemac-port" + +- reg + Usage: required + Value type: + Definition: A standard property. + Specifies the gemacid of the interface. + +- fsl,gemac-bus-id + Usage: required + Value type: + Definition: Must be present. Value should be the id of the bus + connected to gemac. + +- fsl,gemac-phy-id (deprecated binding) + Usage: required + Value type: + Definition: This binding shouldn't be used with new platforms. + Must be present. Value should be the id of the phy + connected to gemac. + +- fsl,mdio-mux-val + Usage: required + Value type: + Definition: Must be present. Value can be either 0 or 2 or 3. + This value is used to configure the mux to enable mdio. + +- phy-mode + Usage: required + Value type: + Definition: Must include "sgmii" + +- fsl,pfe-phy-if-flags (deprecated binding) + Usage: required + Value type: + Definition: This binding shouldn't be used with new platforms. + Must be present. Value should be 0 by default. + If there is not phy connected, this need to be 1. + +- phy-handle + Usage: optional + Value type: + Definition: phandle to the PHY device connected to this device. + +- mdio : A required subnode which specifies the mdio bus in the PFE and used as +a container for phy nodes according to ../phy.txt. + +EXAMPLE + +ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,gemac-bus-id = <0x0>; /* BUS_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; +}; + + +ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,gemac-bus-id = <0x1>; /* BUS_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy2>; +}; + +mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@1 { + reg = <0x1>; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml linux-imx-phytec/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml --- linux-6.1.55/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml 2024-06-19 12:33:57.364176560 +0200 @@ -38,6 +38,18 @@ managed: true + num-lanes: + maximum: 4 + description: + The number of SerDes lanes used for this MAC. There must be at least this + many "phys" and "phy-names" elements. The first "num-lanes" represent + SerDes phys, while the remaining represent optional retimers in the + signal path. + + phys: true + + phy-names: true + required: - reg diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/net/imx-shmem-net.txt linux-imx-phytec/Documentation/devicetree/bindings/net/imx-shmem-net.txt --- linux-6.1.55/Documentation/devicetree/bindings/net/imx-shmem-net.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/net/imx-shmem-net.txt 2024-06-19 12:33:57.364176560 +0200 @@ -0,0 +1,37 @@ +i.MX SHMEM-NET implementations + +A network device to communicate with another domain. +Communication is done through shared memory + and synchronized by Mailbox Units of imx. +Use Mailbox Units side A to communicate with side B. + +Required properties: +- compatible : "fsl,imx-shmem-net". +- rxfirst: The flag that indicates the position of the RX buffer, + one of the two partitions must set it. +- mub-partition: The id number of the remote processors, + used on i.mx8qm for partition reset. The default + value is 3 in driver without this property. +- mbox-names: the mailbox channel names. +- mboxes: the mailboxes list containing: + MU name, channel type (0 for TX, 1 for RX) and channel id. +- memory-region: the coherent memory shared across domains. + +===================================================================== + +Example: + +imx_shmem_net: imx_shmem_net { + compatible = "fsl,imx-shmem-net"; + mub-partition = <1>; + mbox-names = "tx", "rx"; + mboxes = <&lsio_mu8b 0 1 + &lsio_mu8b 1 1>; + status = "disabled"; +}; + +&imx_shmem_net{ + memory-region = <&shmem_dma_reserved>; + status = "okay"; +}; + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/net/pcs/fsl,lynx-pcs.yaml linux-imx-phytec/Documentation/devicetree/bindings/net/pcs/fsl,lynx-pcs.yaml --- linux-6.1.55/Documentation/devicetree/bindings/net/pcs/fsl,lynx-pcs.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/net/pcs/fsl,lynx-pcs.yaml 2024-06-19 12:33:57.368176628 +0200 @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/fsl,lynx-pcs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Lynx PCS + +maintainers: + - Ioana Ciornei + +description: | + NXP Lynx 10G and 28G SerDes have Ethernet PCS devices which can be used as + protocol controllers. They are accessible over the Ethernet interface's MDIO + bus. + +properties: + compatible: + enum: + - fsl,lx2160a-lynx-pcs + - fsl,lynx-pcs + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + qsgmii_pcs1: ethernet-pcs@1 { + compatible = "fsl,lynx-pcs"; + reg = <1>; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/net/wireless/nxp,wifi-wake-host.yaml linux-imx-phytec/Documentation/devicetree/bindings/net/wireless/nxp,wifi-wake-host.yaml --- linux-6.1.55/Documentation/devicetree/bindings/net/wireless/nxp,wifi-wake-host.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/net/wireless/nxp,wifi-wake-host.yaml 2024-06-19 12:33:57.372176697 +0200 @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/nxp,wifi-wake-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP 89xx wireless devices + +maintainers: + - Sherry Sun + +description: + This node provides properties for controlling the NXP 89XX wireless device. + The node is expected to be specified as a child node to the PCIE/SDIO + controller that connects the device to the system. + +properties: + compatible: + const: nxp,wifi-wake-host + + interrupts: + maxItems: 1 + description: | + Specifies attributes for the out-of-band interrupt (host-wake). + + interrupt-names: + const: host-wake + description: | + Name of the out-of-band interrupt, which must be set to "host-wake". + +required: + - compatible + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include + + pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + disable-gpio = <&gpio5 10 1>; + reset-gpio = <&gpio5 12 1>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; + vph-supply = <&vgen5_reg>; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio5>; + interrupts = <11 8>; + interrupt-names = "host-wake"; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml linux-imx-phytec/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml --- linux-6.1.55/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml 2024-06-19 12:33:57.372176697 +0200 @@ -32,6 +32,7 @@ - fsl,imx7ulp-ocotp - fsl,imx8mq-ocotp - fsl,imx8mm-ocotp + - fsl,imx8ulp-ocotp - const: syscon - items: - enum: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/pci/baikal,bt1-pcie.yaml linux-imx-phytec/Documentation/devicetree/bindings/pci/baikal,bt1-pcie.yaml --- linux-6.1.55/Documentation/devicetree/bindings/pci/baikal,bt1-pcie.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/pci/baikal,bt1-pcie.yaml 2024-06-19 12:33:57.376176765 +0200 @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 PCIe Root Port Controller + +maintainers: + - Serge Semin + +description: + Embedded into Baikal-T1 SoC Root Complex controller with a single port + activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured + to have just a single Root Port function and is capable of establishing the + link up to Gen.3 speed on x4 lanes. It doesn't have embedded clock and reset + control module, so the proper interface initialization is supposed to be + performed by software. There four in- and four outbound iATU regions + which can be used to emit all required TLP types on the PCIe bus. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: baikal,bt1-pcie + + reg: + description: + DBI, DBI2 and at least 4KB outbound iATU-capable region for the + peripheral devices CFG-space access. + maxItems: 3 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: config + + interrupts: + description: + MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization + request and eight Read/Write eDMA IRQ lines are available. + maxItems: 14 + + interrupt-names: + items: + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 + - const: dma4 + - const: dma5 + - const: dma6 + - const: dma7 + - const: msi + - const: aer + - const: pme + - const: hp + - const: bw_mg + - const: l_eq + + clocks: + description: + DBI (attached to the APB bus), AXI-bus master and slave interfaces + are fed up by the dedicated application clocks. A common reference + clock signal is supposed to be attached to the corresponding Ref-pad + of the SoC. It will be redistributed amongst the controller core + sub-modules (pipe, core, aux, etc). + maxItems: 4 + + clock-names: + items: + - const: dbi + - const: mstr + - const: slv + - const: ref + + resets: + description: + A comprehensive controller reset logic is supposed to be implemented + by software, so almost all the possible application and core reset + signals are exposed via the system CCU module. + maxItems: 9 + + reset-names: + items: + - const: mstr + - const: slv + - const: pwr + - const: hot + - const: phy + - const: core + - const: pipe + - const: sticky + - const: non-sticky + + baikal,bt1-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the Baikal-T1 System Controller DT node. It's required to + access some additional PM, Reset-related and LTSSM signals. + + num-lanes: + maximum: 4 + + max-link-speed: + maximum: 3 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + pcie@1f052000 { + compatible = "baikal,bt1-pcie"; + device_type = "pci"; + reg = <0x1f052000 0x1000>, <0x1f053000 0x1000>, <0x1bdbf000 0x1000>; + reg-names = "dbi", "dbi2", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0x00000000 0x1bdb0000 0 0x00008000>, + <0x82000000 0 0x20000000 0x08000000 0 0x13db0000>; + bus-range = <0x0 0xff>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7", + "msi", "aer", "pme", "hp", "bw_mg", + "l_eq"; + + clocks = <&ccu_sys 1>, <&ccu_axi 6>, <&ccu_axi 7>, <&clk_pcie>; + clock-names = "dbi", "mstr", "slv", "ref"; + + resets = <&ccu_axi 6>, <&ccu_axi 7>, <&ccu_sys 7>, <&ccu_sys 10>, + <&ccu_sys 4>, <&ccu_sys 6>, <&ccu_sys 5>, <&ccu_sys 8>, + <&ccu_sys 9>; + reset-names = "mstr", "slv", "pwr", "hot", "phy", "core", "pipe", + "sticky", "non-sticky"; + + reset-gpios = <&port0 0 GPIO_ACTIVE_LOW>; + + num-lanes = <4>; + max-link-speed = <3>; + }; +... diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml linux-imx-phytec/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml --- linux-6.1.55/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml 2024-06-19 12:33:57.376176765 +0200 @@ -24,6 +24,17 @@ - fsl,imx8mq-pcie - fsl,imx8mm-pcie - fsl,imx8mp-pcie + - fsl,imx6q-pcie-ep + - fsl,imx6sx-pcie-ep + - fsl,imx6qp-pcie-ep + - fsl,imx7d-pcie-ep + - fsl,imx8mq-pcie-ep + - fsl,imx8mm-pcie-ep + - fsl,imx8mp-pcie-ep + - fsl,imx8qm-pcie + - fsl,imx8qxp-pcie + - fsl,imx8qm-pcie-ep + - fsl,imx8qxp-pcie-ep reg: items: @@ -154,6 +165,15 @@ the three PCIe PHY powers. This regulator can be supplied by both 1.8v and 3.3v voltage supplies (optional required). + hsio-cfg: + description: hsio configuration mode when the pcie node is supported. + mode 1: pciea 2 lanes and one sata ahci port. + mode 2: pciea 1 lane, pcieb 1 lane and one sata ahci port. + mode 3: pciea 2 lanes, pcieb 1 lane. + + local-addr: + description: the local address used in hsio module. + required: - compatible - reg diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/pci/layerscape-pci.txt linux-imx-phytec/Documentation/devicetree/bindings/pci/layerscape-pci.txt --- linux-6.1.55/Documentation/devicetree/bindings/pci/layerscape-pci.txt 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/pci/layerscape-pci.txt 2024-06-19 12:33:57.376176765 +0200 @@ -22,10 +22,12 @@ "fsl,ls1043a-pcie" "fsl,ls1012a-pcie" "fsl,ls1028a-pcie" + "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie" EP mode: "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" + "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep" - reg: base addresses and lengths of the PCIe controller register blocks. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml linux-imx-phytec/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml --- linux-6.1.55/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml 2024-06-19 12:33:57.380176833 +0200 @@ -14,10 +14,10 @@ description: |+ RK3568 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in - designware-pcie.txt. + snps,dw-pcie.yaml. allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/snps,dw-pcie.yaml# properties: compatible: diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml linux-imx-phytec/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml --- linux-6.1.55/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml 2024-06-19 12:33:57.380176833 +0200 @@ -0,0 +1,266 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DWC PCIe RP/EP controller + +maintainers: + - Jingoo Han + - Gustavo Pimentel + +description: + Generic Synopsys DesignWare PCIe Root Port and Endpoint controller + properties. + +select: false + +properties: + reg: + description: + DWC PCIe CSR space is normally accessed over the dedicated Data Bus + Interface - DBI. In accordance with the reference manual the register + configuration space belongs to the Configuration-Dependent Module (CDM) + and is split up into several sub-parts Standard PCIe configuration + space, Port Logic Registers (PL), Shadow Config-space Registers, + iATU/eDMA registers. The particular sub-space is selected by the + CDM/ELBI (dbi_cs) and CS2 (dbi_cs2) signals (selector bits). Such + configuration provides a flexible interface for the system engineers to + either map the particular space at a desired MMIO address or just leave + them in a contiguous memory space if pure Native or AXI Bridge DBI access + is selected. Note the PCIe CFG-space, PL and Shadow registers are + specific for each activated function, while the rest of the sub-spaces + are common for all of them (if there are more than one). + minItems: 2 + maxItems: 6 + + reg-names: + minItems: 2 + maxItems: 6 + + interrupts: + description: + There are two main sub-blocks which are normally capable of + generating interrupts. It's System Information Interface and MSI + interface. While the former one has some common for the Host and + Endpoint controllers IRQ-signals, the later interface is obviously + Root Complex specific since it's responsible for the incoming MSI + messages signalling. The System Information IRQ signals are mainly + responsible for reporting the generic PCIe hierarchy and Root + Complex events like VPD IO request, general AER, PME, Hot-plug, link + bandwidth change, link equalization request, INTx asserted/deasserted + Message detection, embedded DMA Tx/Rx/Error. + minItems: 1 + maxItems: 26 + + interrupt-names: + minItems: 1 + maxItems: 26 + + clocks: + description: + DWC PCIe reference manual explicitly defines a set of the clocks required + to get the controller working correctly. In general all of them can + be divided into two groups':' application and core clocks. Note the + platforms may have some of the clock sources unspecified in case if the + corresponding domains are fed up from a common clock source. + minItems: 1 + maxItems: 7 + + clock-names: + minItems: 1 + maxItems: 7 + items: + oneOf: + - description: + Data Bus Interface (DBI) clock. Clock signal for the AXI-bus + interface of the Configuration-Dependent Module, which is + basically the set of the controller CSRs. + const: dbi + - description: + Application AXI-bus Master interface clock. Basically this is + a clock for the controller DMA interface (PCI-to-CPU). + const: mstr + - description: + Application AXI-bus Slave interface clock. This is a clock for + the CPU-to-PCI memory IO interface. + const: slv + - description: + Controller Core-PCS PIPE interface clock. It's normally + supplied by an external PCS-PHY. + const: pipe + - description: + Controller Primary clock. It's assumed that all controller input + signals (except resets) are synchronous to this clock. + const: core + - description: + Auxiliary clock for the controller PMC domain. The controller + partitioning implies having some parts to operate with this + clock in some power management states. + const: aux + - description: + Generic reference clock. In case if there are several + interfaces fed up with a common clock source it's advisable to + define it with this name (for instance pipe, core and aux can + be connected to a single source of the periodic signal). + const: ref + - description: + Clock for the PHY registers interface. Originally this is + a PHY-viewport-based interface, but some platform may have + specifically designed one. + const: phy_reg + - description: + Vendor-specific clock names. Consider using the generic names + above for new bindings. + oneOf: + - description: See native 'dbi' clock for details + enum: [ pcie, pcie_apb_sys, aclk_dbi ] + - description: See native 'mstr/slv' clock for details + enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ] + - description: See native 'pipe' clock for details + enum: [ pcie_phy, pcie_phy_ref, link ] + - description: See native 'aux' clock for details + enum: [ pcie_aux ] + - description: See native 'ref' clock for details. + enum: [ gio ] + - description: See nativs 'phy_reg' clock for details + enum: [ pcie_apb_phy, pclk ] + + resets: + description: + DWC PCIe reference manual explicitly defines a set of the reset + signals required to be de-asserted to properly activate the controller + sub-parts. All of these signals can be divided into two sub-groups':' + application and core resets with respect to the main sub-domains they + are supposed to reset. Note the platforms may have some of these signals + unspecified in case if they are automatically handled or aggregated into + a comprehensive control module. + minItems: 1 + maxItems: 10 + + reset-names: + minItems: 1 + maxItems: 10 + items: + oneOf: + - description: Data Bus Interface (DBI) domain reset + const: dbi + - description: AXI-bus Master interface reset + const: mstr + - description: AXI-bus Slave interface reset + const: slv + - description: Application-dependent interface reset + const: app + - description: Controller Non-sticky CSR flags reset + const: non-sticky + - description: Controller sticky CSR flags reset + const: sticky + - description: PIPE-interface (Core-PCS) logic reset + const: pipe + - description: + Controller primary reset (resets everything except PMC module) + const: core + - description: PCS/PHY block reset + const: phy + - description: PMC hot reset signal + const: hot + - description: Cold reset signal + const: pwr + - description: + Vendor-specific reset names. Consider using the generic names + above for new bindings. + oneOf: + - description: See native 'app' reset for details + enum: [ apps, gio, apb ] + - description: See native 'phy' reset for details + enum: [ pciephy, link ] + - description: See native 'pwr' reset for details + enum: [ turnoff ] + + phys: + description: + There can be up to the number of possible lanes PHYs specified placed in + the phandle array in the line-based order. Obviously each the specified + PHYs are supposed to be able to work in the PCIe mode with a speed + implied by the DWC PCIe controller they are attached to. + minItems: 1 + maxItems: 16 + + phy-names: + minItems: 1 + maxItems: 16 + oneOf: + - description: Generic PHY names + items: + pattern: '^pcie[0-9]+$' + - description: + Vendor-specific PHY names. Consider using the generic + names above for new bindings. + items: + oneOf: + - pattern: '^pcie(-?phy[0-9]*)?$' + - pattern: '^p2u-[0-7]$' + + reset-gpio: + deprecated: true + description: + Reference to the GPIO-controlled PERST# signal. It is used to reset all + the peripheral devices available on the PCIe bus. + maxItems: 1 + + reset-gpios: + description: + Reference to the GPIO-controlled PERST# signal. It is used to reset all + the peripheral devices available on the PCIe bus. + maxItems: 1 + + max-link-speed: + maximum: 5 + + num-lanes: + description: + Number of PCIe link lanes to use. Can be omitted if the already brought + up link is supposed to be preserved. + maximum: 16 + + num-ob-windows: + $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true + description: + Number of outbound address translation windows. This parameter can be + auto-detected based on the iATU memory writability. So there is no + point in having a dedicated DT-property for it. + maximum: 256 + + num-ib-windows: + $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true + description: + Number of inbound address translation windows. In the same way as + for the outbound AT windows, this parameter can be auto-detected based + on the iATU memory writability. There is no point having a dedicated + DT-property for it either. + maximum: 256 + + num-viewport: + $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true + description: + Number of outbound view ports configured in hardware. It's the same as + the number of outbound AT windows. + maximum: 256 + + snps,enable-cdm-check: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enable automatic checking of CDM (Configuration Dependent Module) + registers for data corruption. CDM registers include standard PCIe + configuration space registers, Port Logic registers, DMA and iATU + registers. This feature has been available since DWC PCIe v4.80a. + + dma-coherent: true + +additionalProperties: true + +... diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml linux-imx-phytec/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml --- linux-6.1.55/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml 2024-06-19 12:33:57.380176833 +0200 @@ -13,76 +13,182 @@ description: | Synopsys DesignWare PCIe host controller endpoint +# Please create a separate DT-schema for your DWC PCIe Endpoint controller +# and make sure it's assigned with the vendor-specific compatible string. +select: + properties: + compatible: + const: snps,dw-pcie-ep + required: + - compatible + allOf: - $ref: /schemas/pci/pci-ep.yaml# + - $ref: /schemas/pci/snps,dw-pcie-common.yaml# properties: - compatible: - anyOf: - - {} - - const: snps,dw-pcie-ep - reg: - description: | - It should contain Data Bus Interface (dbi) and config registers for all - versions. - For designware core version >= 4.80, it may contain ATU address space. + description: + DBI, DBI2 reg-spaces and outbound memory window are required for the + normal controller functioning. iATU memory IO region is also required + if the space is unrolled (IP-core version >= 4.80a). minItems: 2 - maxItems: 4 + maxItems: 5 reg-names: minItems: 2 - maxItems: 4 + maxItems: 5 items: - enum: [dbi, dbi2, config, atu, addr_space, link, atu_dma, appl] + oneOf: + - description: + Basic DWC PCIe controller configuration-space accessible over + the DBI interface. This memory space is either activated with + CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region + with all spaces. Note iATU/eDMA CSRs are indirectly accessible + via the PL viewports on the DWC PCIe controllers older than + v4.80a. + const: dbi + - description: + Shadow DWC PCIe config-space registers. This space is selected + by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of + the PCI-SIG PCIe CFG-space with the shadow registers for some + PCI Header space, PCI Standard and Extended Structures. It's + mainly relevant for the end-point controller configuration, + but still there are some shadow registers available for the + Root Port mode too. + const: dbi2 + - description: + External Local Bus registers. It's an application-dependent + registers normally defined by the platform engineers. The space + can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can + be accessed over some platform-specific means (for instance + as a part of a system controller). + enum: [ elbi, app ] + - description: + iATU/eDMA registers common for all device functions. It's an + unrolled memory space with the internal Address Translation + Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1 + and CS2 = 1. For IP-core releases prior v4.80a, these registers + have been programmed via an indirect addressing scheme using a + set of viewport CSRs mapped into the PL space. Note iATU is + normally mapped to the 0x0 address of this region, while eDMA + is available at 0x80000 base address. + const: atu + - description: + Platform-specific eDMA registers. Some platforms may have eDMA + CSRs mapped in a non-standard base address. The registers offset + can be changed or the MS/LS-bits of the address can be attached + in an additional RTL block before the MEM-IO transactions reach + the DW PCIe slave interface. + const: dma + - description: + PHY/PCS configuration registers. Some platforms can have the + PCS and PHY CSRs accessible over a dedicated memory mapped + region, but mainly these registers are indirectly accessible + either by means of the embedded PHY viewport schema or by some + platform-specific method. + const: phy + - description: + Outbound iATU-capable memory-region which will be used to + generate various application-specific traffic on the PCIe bus + hierarchy. It's usage scenario depends on the endpoint + functionality, for instance it can be used to create MSI(X) + messages. + const: addr_space + - description: + Vendor-specific CSR names. Consider using the generic names above + for new bindings. + oneOf: + - description: See native 'elbi/app' CSR region for details. + enum: [ link, appl ] + - description: See native 'atu' CSR region for details. + enum: [ atu_dma ] + allOf: + - contains: + const: dbi + - contains: + const: addr_space + + interrupts: + description: + There is no mandatory IRQ signals for the normal controller functioning, + but in addition to the native set the platforms may have a link- or + PM-related IRQs specified. + minItems: 1 + maxItems: 20 + + interrupt-names: + minItems: 1 + maxItems: 20 + items: + oneOf: + - description: + Controller request to read or write virtual product data + from/to the VPD capability registers. + const: vpd + - description: + Link Equalization Request flag is set in the Link Status 2 + register (applicable if the corresponding IRQ is enabled in + the Link Control 3 register). + const: l_eq + - description: + Indicates that the eDMA Tx/Rx transfer is complete or that an + error has occurred on the corresponding channel. eDMA can have + eight Tx (Write) and Rx (Read) eDMA channels thus supporting up + to 16 IRQ signals all together. Write eDMA channels shall go + first in the ordered row as per default edma_int[*] bus setup. + pattern: '^dma([0-9]|1[0-5])?$' + - description: + PCIe protocol correctable error or a Data Path protection + correctable error is detected by the automotive/safety + feature. + const: sft_ce + - description: + Indicates that the internal safety mechanism has detected an + uncorrectable error. + const: sft_ue + - description: + Application-specific IRQ raised depending on the vendor-specific + events basis. + const: app + - description: + Vendor-specific IRQ names. Consider using the generic names above + for new bindings. + oneOf: + - description: See native "app" IRQ for details + enum: [ intr ] - reset-gpio: - description: GPIO pin number of PERST# signal - maxItems: 1 - deprecated: true - - reset-gpios: - description: GPIO controlled connection to PERST# signal - maxItems: 1 - - snps,enable-cdm-check: - type: boolean - description: | - This is a boolean property and if present enables - automatic checking of CDM (Configuration Dependent Module) registers - for data corruption. CDM registers include standard PCIe configuration - space registers, Port Logic registers, DMA and iATU (internal Address - Translation Unit) registers. - - num-ib-windows: - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 256 - description: number of inbound address translation windows - deprecated: true - - num-ob-windows: - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 256 - description: number of outbound address translation windows - deprecated: true + max-functions: + maximum: 32 required: + - compatible - reg - reg-names - - compatible additionalProperties: true examples: - | - bus { - #address-cells = <1>; - #size-cells = <1>; - pcie-ep@dfd00000 { - compatible = "snps,dw-pcie-ep"; - reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ - <0xdfc01000 0x0001000>, /* IP registers 2 */ - <0xd0000000 0x2000000>; /* Configuration space */ - reg-names = "dbi", "dbi2", "addr_space"; - }; + pcie-ep@dfd00000 { + compatible = "snps,dw-pcie-ep"; + reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ + <0xdfc01000 0x0001000>, /* IP registers 2 */ + <0xd0000000 0x2000000>; /* Configuration space */ + reg-names = "dbi", "dbi2", "addr_space"; + + interrupts = <23>, <24>; + interrupt-names = "dma0", "dma1"; + + clocks = <&sys_clk 12>, <&sys_clk 24>; + clock-names = "dbi", "ref"; + + resets = <&sys_rst 12>, <&sys_rst 24>; + reset-names = "dbi", "phy"; + + phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>; + phy-names = "pcie0", "pcie1", "pcie2", "pcie3"; + + max-link-speed = <3>; + max-functions = /bits/ 8 <4>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml linux-imx-phytec/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml --- linux-6.1.55/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml 2024-06-19 12:33:57.380176833 +0200 @@ -13,20 +13,25 @@ description: | Synopsys DesignWare PCIe host controller +# Please create a separate DT-schema for your DWC PCIe Root Port controller +# and make sure it's assigned with the vendor-specific compatible string. +select: + properties: + compatible: + const: snps,dw-pcie + required: + - compatible + allOf: - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/snps,dw-pcie-common.yaml# properties: - compatible: - anyOf: - - {} - - const: snps,dw-pcie - reg: - description: | - It should contain Data Bus Interface (dbi) and config registers for all - versions. - For designware core version >= 4.80, it may contain ATU address space. + description: + At least DBI reg-space and peripheral devices CFG-space outbound window + are required for the normal controller work. iATU memory IO region is + also required if the space is unrolled (IP-core version >= 4.80a). minItems: 2 maxItems: 5 @@ -34,71 +39,192 @@ minItems: 2 maxItems: 5 items: - enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl, - parf, cfg, link, ulreg, smu, mpu, apb, phy ] - - num-lanes: - description: | - number of lanes to use (this property should be specified unless - the link is brought already up in firmware) - maximum: 16 - - reset-gpio: - description: GPIO pin number of PERST# signal - maxItems: 1 - deprecated: true - - reset-gpios: - description: GPIO controlled connection to PERST# signal - maxItems: 1 - - interrupts: true - - interrupt-names: true - - clocks: true - - snps,enable-cdm-check: - type: boolean - description: | - This is a boolean property and if present enables - automatic checking of CDM (Configuration Dependent Module) registers - for data corruption. CDM registers include standard PCIe configuration - space registers, Port Logic registers, DMA and iATU (internal Address - Translation Unit) registers. - - num-viewport: - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 256 - description: | - number of view ports configured in hardware. If a platform - does not specify it, the driver autodetects it. - deprecated: true + oneOf: + - description: + Basic DWC PCIe controller configuration-space accessible over + the DBI interface. This memory space is either activated with + CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region + with all spaces. Note iATU/eDMA CSRs are indirectly accessible + via the PL viewports on the DWC PCIe controllers older than + v4.80a. + const: dbi + - description: + Shadow DWC PCIe config-space registers. This space is selected + by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of + the PCI-SIG PCIe CFG-space with the shadow registers for some + PCI Header space, PCI Standard and Extended Structures. It's + mainly relevant for the end-point controller configuration, + but still there are some shadow registers available for the + Root Port mode too. + const: dbi2 + - description: + External Local Bus registers. It's an application-dependent + registers normally defined by the platform engineers. The space + can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can + be accessed over some platform-specific means (for instance + as a part of a system controller). + enum: [ elbi, app ] + - description: + iATU/eDMA registers common for all device functions. It's an + unrolled memory space with the internal Address Translation + Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1 + and CS2 = 1. For IP-core releases prior v4.80a, these registers + have been programmed via an indirect addressing scheme using a + set of viewport CSRs mapped into the PL space. Note iATU is + normally mapped to the 0x0 address of this region, while eDMA + is available at 0x80000 base address. + const: atu + - description: + Platform-specific eDMA registers. Some platforms may have eDMA + CSRs mapped in a non-standard base address. The registers offset + can be changed or the MS/LS-bits of the address can be attached + in an additional RTL block before the MEM-IO transactions reach + the DW PCIe slave interface. + const: dma + - description: + PHY/PCS configuration registers. Some platforms can have the + PCS and PHY CSRs accessible over a dedicated memory mapped + region, but mainly these registers are indirectly accessible + either by means of the embedded PHY viewport schema or by some + platform-specific method. + const: phy + - description: + Outbound iATU-capable memory-region which will be used to access + the peripheral PCIe devices configuration space. + const: config + - description: + Vendor-specific CSR names. Consider using the generic names above + for new bindings. + oneOf: + - description: See native 'elbi/app' CSR region for details. + enum: [ apb, mgmt, link, ulreg, appl ] + - description: See native 'atu' CSR region for details. + enum: [ atu_dma ] + - description: Syscon-related CSR regions. + enum: [ smu, mpu ] + allOf: + - contains: + const: dbi + - contains: + const: config + + interrupts: + description: + DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt + signal is supposed to be specified for the host controller. + minItems: 1 + maxItems: 26 + + interrupt-names: + minItems: 1 + maxItems: 26 + items: + oneOf: + - description: + Controller request to read or write virtual product data + from/to the VPD capability registers. + const: vpd + - description: + Link Equalization Request flag is set in the Link Status 2 + register (applicable if the corresponding IRQ is enabled in + the Link Control 3 register). + const: l_eq + - description: + Indicates that the eDMA Tx/Rx transfer is complete or that an + error has occurred on the corresponding channel. eDMA can have + eight Tx (Write) and Rx (Read) eDMA channels thus supporting up + to 16 IRQ signals all together. Write eDMA channels shall go + first in the ordered row as per default edma_int[*] bus setup. + pattern: '^dma([0-9]|1[0-5])?$' + - description: + PCIe protocol correctable error or a Data Path protection + correctable error is detected by the automotive/safety + feature. + const: sft_ce + - description: + Indicates that the internal safety mechanism has detected an + uncorrectable error. + const: sft_ue + - description: + Application-specific IRQ raised depending on the vendor-specific + events basis. + const: app + - description: + DSP AXI MSI Interrupt detected. It gets de-asserted when there is + no more MSI interrupt pending. The interrupt is relevant to the + iMSI-RX - Integrated MSI Receiver (AXI bridge). + const: msi + - description: + Legacy A/B/C/D interrupt signal. Basically it's triggered by + receiving a Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message + from the downstream device. + pattern: "^int(a|b|c|d)$" + - description: + Error condition detected and a flag is set in the Root Error Status + register of the AER capability. It's asserted when the RC + internally generated an error or an error message is received by + the RC. + const: aer + - description: + PME message is received by the port. That means having the PME + status bit set in the Root Status register (the event is + supposed to be unmasked in the Root Control register). + const: pme + - description: + Hot-plug event is detected. That is a bit has been set in the + Slot Status register and the corresponding event is enabled in + the Slot Control register. + const: hp + - description: + Link Autonomous Bandwidth Status flag has been set in the Link + Status register (the event is supposed to be unmasked in the + Link Control register). + const: bw_au + - description: + Bandwidth Management Status flag has been set in the Link + Status register (the event is supposed to be unmasked in the + Link Control register). + const: bw_mg + - description: + Vendor-specific IRQ names. Consider using the generic names above + for new bindings. + oneOf: + - description: See native "app" IRQ for details + enum: [ intr ] + allOf: + - contains: + const: msi additionalProperties: true required: + - compatible - reg - reg-names - - compatible examples: - | - bus { - #address-cells = <1>; - #size-cells = <1>; - pcie@dfc00000 { - device_type = "pci"; - compatible = "snps,dw-pcie"; - reg = <0xdfc00000 0x0001000>, /* IP registers */ - <0xd0000000 0x0002000>; /* Configuration space */ - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, - <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; - interrupts = <25>, <24>; - #interrupt-cells = <1>; - num-lanes = <1>; - }; + pcie@dfc00000 { + compatible = "snps,dw-pcie"; + device_type = "pci"; + reg = <0xdfc00000 0x0001000>, /* IP registers */ + <0xd0000000 0x0002000>; /* Configuration space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + bus-range = <0x0 0xff>; + + interrupts = <25>, <24>; + interrupt-names = "msi", "hp"; + #interrupt-cells = <1>; + + reset-gpios = <&port0 0 1>; + + phys = <&pcie_phy>; + phy-names = "pcie"; + + num-lanes = <1>; + max-link-speed = <3>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml linux-imx-phytec/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml --- linux-6.1.55/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml 2024-06-19 12:33:57.380176833 +0200 @@ -19,6 +19,10 @@ - fsl,imx8mm-ddr-pmu - fsl,imx8mn-ddr-pmu - fsl,imx8mp-ddr-pmu + - fsl,imx8qxp-ddr-pmu + - fsl,imx8qm-ddr-pmu + - fsl,imx8dxl-ddr-pmu + - fsl,imx8dxl-db-pmu - items: - enum: - fsl,imx8mm-ddr-pmu diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml --- linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml 2024-06-19 12:33:57.384176902 +0200 @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright 2020 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8mp-lvds-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP LVDS PHY Device Tree Bindings + +maintainers: + - Liu Ying + +description: | + LVDS PHY found on i.MX8MP and i.MX93 SoCs. i.MX8MP LVDS PHY IP contains + two PHYs, each of which supports a four data lane LVDS channel. i.MX93 + LVDS PHY IP contains one PHY. + +properties: + compatible: + enum: + - fsl,imx8mp-lvds-phy + - fsl,imx93-lvds-phy + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to block control syscon + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + power-domains: + maxItems: 1 + + port@0: + type: object + description: A port node pointing to the PHY instance0's port node + properties: + reg: + maxItems: 1 + description: PHY instance number. + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + + port@1: + type: object + description: A port node pointing to the PHY instance1's port node + properties: + reg: + maxItems: 1 + description: PHY instance number + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + +required: + - compatible + - "#address-cells" + - "#size-cells" + - gpr + - clocks + - clock-names + - power-domains + - port@0 + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mp-lvds-phy + then: + required: + - port@1 + + - if: + properties: + compatible: + contains: + const: fsl,imx93-lvds-phy + then: + properties: + port@1: false + +additionalProperties: false + +examples: + - | + #include + ldb_phy: phy@32ec0128 { + compatible = "fsl,imx8mp-lvds-phy"; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&mediamix_blk_ctl>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "apb"; + power-domains = <&mediamix_pd>; + + ldb_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + +... diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml --- linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml 2024-06-19 12:33:57.384176902 +0200 @@ -32,6 +32,11 @@ description: A phandle to the regulator for USB VBUS. + vbus-power-supply: + description: + A phandle to the vbus power supply provider, used to to detect the + possible BC charger type of it. + required: - compatible - reg diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml --- linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml 2024-06-19 12:33:57.384176902 +0200 @@ -16,6 +16,8 @@ compatible: enum: - fsl,imx8mm-pcie-phy + - fsl,imx8mp-pcie-phy + - fsl,imx8qm-pcie-phy reg: maxItems: 1 @@ -28,11 +30,16 @@ - const: ref resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: - items: - - const: pciephy + oneOf: + - items: # for iMX8MM + - const: pciephy + - items: # for IMX8MP + - const: pciephy + - const: perst fsl,refclk-pad-mode: description: | @@ -60,6 +67,22 @@ description: A boolean property indicating the CLKREQ# signal is not supported in the board design (optional) + power-domains: + description: PCIe PHY power domain (optional). + maxItems: 1 + + hsio-cfg: + description: | + Specifies the different usecases supported by the HSIO(High Speed IO) + module. PCIEAX2SATA means two lanes PCIea and a single lane SATA. + PCIEAX1PCIEBX1SATA represents a single lane PCIea, a single lane + PCIeb and a single lane SATA. PCIEAX2PCIEBX1 on behalf of a two + lanes PCIea, a single lane PCIeb. + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants to + be used (optional). + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 3 ] + required: - "#phy-cells" - compatible diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,imx93-mipi-dphy.yaml linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,imx93-mipi-dphy.yaml --- linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,imx93-mipi-dphy.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,imx93-mipi-dphy.yaml 2024-06-19 12:33:57.384176902 +0200 @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx93-mipi-dphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX93 Synopsys DesignWare MIPI DPHY + +maintainers: + - Liu Ying + +properties: + compatible: + const: fsl,imx93-mipi-dphy + + "#phy-cells": + const: 0 + + clocks: + items: + - description: PHY configuration clock + - description: PHY reference clock + + clock-names: + items: + - const: phy_cfg + - const: phy_ref + + power-domains: + maxItems: 1 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + +required: + - compatible + - "#phy-cells" + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + dphy: dphy { + compatible = "fsl,imx93-mipi-dphy"; + clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>, <&clk IMX93_CLK_24M>; + clock-names = "phy_cfg", "phy_ref"; + assigned-clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>; + assigned-clock-parents = <&clk IMX93_CLK_24M>; + assigned-clock-rates = <24000000>; + #phy-cells = <0>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + }; + +... diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml --- linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml 2024-06-19 12:33:57.384176902 +0200 @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Lynx 10G SerDes PHY + +description: + The Lynx 10G is a multi-protocol SerDes block which handles networking, PCIe, + SATA, USB and other high-speed interfaces. It is present on most QorIQ and + Layerscape SoCs. The integration is SoC-specific, with the differences + consisting in register endianness, the number of lanes, protocol converters + available per lane and their location in the PCCR registers. Some SoCs have + multiple SerDes blocks and even those differ in their protocol configuration. + +maintainers: + - Vladimir Oltean + +properties: + compatible: + items: + - enum: + - fsl,ls1028a-serdes + - fsl,ls1046a-serdes1 + - fsl,ls1046a-serdes2 + - fsl,ls1088a-serdes1 + - fsl,ls2088a-serdes1 + - fsl,ls2088a-serdes2 + - const: fsl,lynx-10g + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + description: + Encodes lane number from consumer's perspective (lane A corresponds to 0). + This number corresponds to the lane as visible in the SerDes IP's + registers (such as LNaPSSR0), and this may not be necessarily identical + to the lane numbering scheme from the SoC's pinout. + + fsl,dcfg-handle: + description: + Should be a phandle to the DCFG block of the SoC. On some SoC + integrations, major reconfiguration of the networking SerDes protocol + requires an RCW override procedure, which is handled by the DCFG. + The RCW override procedure requires hardware validation for each SoC and + is currently not implemented. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + serdes_1: phy@1ea0000 { + compatible = "fsl,ls1028a-serdes", "fsl,lynx-10g"; + reg = <0x0 0x1ea0000 0x0 0xffff>; + #phy-cells = <1>; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,samsung-hdmi-phy.yaml linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,samsung-hdmi-phy.yaml --- linux-6.1.55/Documentation/devicetree/bindings/phy/fsl,samsung-hdmi-phy.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/phy/fsl,samsung-hdmi-phy.yaml 2024-06-19 12:33:57.384176902 +0200 @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,samsung-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freesclae iMX8MP HDMI PHY WITH SAMSUNG IP BLOCK + +maintainers: + - Sandor Yu + +properties: + compatible: + enum: + - fsl,samsung-hdmi-phy + + reg: + maxItems: 1 + + clock-output-names: + description: + The HDMI PHY Pixel output clock name. + + "#clock-cells": + const: 0 + + "#phy-cells": + const: 0 + + clocks: + maxItems: 2 + items: + - description: apb for system control and register configuration + - description: ref for crystal-oscillator reference PLL clock input. + + clock-names: + - const: apb + - const: ref + + reset: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#phy-cells" + - clocks + - clock-names + - reset + +optional: + - clock-output-names + +additionalProperties: false + +examples: + - | + hdmiphy: hdmiphy@32fdff00 { + compatible = "fsl,samsung-hdmi-phy"; + reg = <0x32fdff00 0x100>; + clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_APB_CLK>, + <&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>; + clock-names = "apb", "ref"; + resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PHY_RESET>; + clock-output-names = "hdmi_pclk"; + #phy-cells = <0>; + #clock-cells = <0>; + }; + + hdmi: hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi"; + ... + phys = <&hdmiphy>; + phy-names = "hdmi"; + ... + }; + + lcdif3: lcd-controller@32fc6000 { + compatible = "fsl,imx8mp-lcdif3"; + ... + clocks = <&hdmiphy 0>, ...; + clock-names = "pix", ...; + ... + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/phy/inphi,in112525.yaml linux-imx-phytec/Documentation/devicetree/bindings/phy/inphi,in112525.yaml --- linux-6.1.55/Documentation/devicetree/bindings/phy/inphi,in112525.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/phy/inphi,in112525.yaml 2024-06-19 12:33:57.384176902 +0200 @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/inphi,in112525.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Inphi IN112525 Retimer PHY binding + +maintainers: + - Ioana Ciornei + +properties: + compatible: + enum: + - inphi,in112525 + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + + &emdio2 { + status = "okay"; + + inphi_retimer: retimer@0 { + compatible = "inphi,in112525"; + reg = <0x0>; + #phy-cells = <1>; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml linux-imx-phytec/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml --- linux-6.1.55/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml 2024-06-19 12:33:57.384176902 +0200 @@ -22,6 +22,7 @@ enum: - fsl,imx8mq-mipi-dphy - fsl,imx8qxp-mipi-dphy + - fsl,imx8ulp-mipi-dphy reg: maxItems: 1 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt linux-imx-phytec/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt --- linux-6.1.55/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt 2024-06-19 12:33:57.384176902 +0200 @@ -9,6 +9,7 @@ * "fsl,imx6sx-usbphy" for imx6sx * "fsl,imx7ulp-usbphy" for imx7ulp * "fsl,imx8dxl-usbphy" for imx8dxl + * "fsl,imx8ulp-usbphy" for imx8ulp "fsl,imx23-usbphy" is still a fallback for other strings - reg: Should contain registers location and length - interrupts: Should contain phy interrupt diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/phy/phy-mixel-lvds-combo.txt linux-imx-phytec/Documentation/devicetree/bindings/phy/phy-mixel-lvds-combo.txt --- linux-6.1.55/Documentation/devicetree/bindings/phy/phy-mixel-lvds-combo.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/phy/phy-mixel-lvds-combo.txt 2024-06-19 12:33:57.388176971 +0200 @@ -0,0 +1,19 @@ +Mixel LVDS combo PHY + +Required properties: +- compatible: must be "mixel,lvds-combo-phy". +- reg: offset and length of the register block. +- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. +- clocks: clock phandle and specifier pair. +- clock-names: string, clock input name, must be "phy". +- power-domains: phandle pointing to power domain. + +Example: + ldb_phy@56221000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX_LVDS0_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt linux-imx-phytec/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt --- linux-6.1.55/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt 2024-06-19 12:33:57.388176971 +0200 @@ -0,0 +1,39 @@ +Mixel LVDS PHY + +This LVDS PHY supports two LVDS channels. + +Required properties: +- compatible: must be "mixel,lvds-phy". +- reg: offset and length of the register block. +- #address-cells: number of address cells for the LVDS channel subnodes, must + be <1>. +- #size-cells: number of size cells for the LVDS channel subnodes, must be <0>. +- clocks: clock phandle and specifier pair. +- clock-names: string, clock input name, must be "phy". +- power-domains: phandle pointing to power domain. + +The LVDS PHY device tree node should have the subnodes corresponding to the two +LVDS channels. These subnodes must contain the following properties: +- reg: the PHY ID. +- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. + +Example: + ldb_phy@56241000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,lvds-phy"; + reg = <0x0 0x56241000 0x0 0x100>; + clocks = <&clk IMX_LVDS0_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt linux-imx-phytec/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt --- linux-6.1.55/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt 2024-06-19 12:33:57.396177108 +0200 @@ -0,0 +1,19 @@ +* Freescale SIUL2 iomux controller + +See chapter 20 ("System Integration Unit Lite2 (SIUL2)") in the reference +manual[1]. + +Based on fsl,imx-pincontrol implementation. + +Required properties: +- compatible: "fsl,s32v234-siul2" +- fsl,pins: two integers array, represents a group of pins mux and config + setting. The format is fsl,pins = + PIN_FUNC_ID - id of MSCR to be modified + CONFIG - configuration to be written in the MSCR/IMCR register + + Even though IMCR register should be used as input register, it can be + set and addressed in the same way as MSCR, only instead of passing the + IMCR index, IMCR_IDX + 512 is passed[1]. + +[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt linux-imx-phytec/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt --- linux-6.1.55/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 2024-06-19 12:33:57.400177176 +0200 @@ -71,6 +71,13 @@ name for integer state ID 0, list entry 1 for state ID 1, and so on. +pinctrl-assert-gpios: + List of phandles, each pointing at a GPIO which is used by some + board design to steer pins between two peripherals on the board. + It plays like a board level pin multiplexer to choose different + functions for given pins by pulling up/down the GPIOs. See + bindings/gpio/gpio.txt for details of how to specify GPIO. + For example: /* For a client device requiring named states */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/power/fsl,imx8m-genpd.txt linux-imx-phytec/Documentation/devicetree/bindings/power/fsl,imx8m-genpd.txt --- linux-6.1.55/Documentation/devicetree/bindings/power/fsl,imx8m-genpd.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/power/fsl,imx8m-genpd.txt 2024-06-19 12:33:57.408177313 +0200 @@ -0,0 +1,49 @@ +Device Tree Bindings for Freescale i.MX8M Generic Power Domain +============================================================== +The binding for the i.MX8M Generic power Domain[1]. + +[1] Documentation/devicetree/bindings/power/power_domain.txt + +Required properties: + + - compatible: should be of: + - "fsl,imx8m-power-domain" + - #power-domain-cells: Number of cells in a PM domain Specifier, must be 0 + - domain-index: should be the domain index number need to pass to TF-A + - domain-name: the name of this pm domain + +Optional properties: + - clocks: a number of phandles to clocks that need to be enabled during + domain power-up sequence to ensure reset propagation into devices + located inside this power domain + - power-supply: Power supply used to power the domain + - parent-domains: the phandle to the parent power domain + - active-wakeup: keep the PM domain powered in case the attached device wakeup + is enabled. + - rpm-always-on: keep the PM domain powered except for system suspend. + +example: + vpu_g1_pd: vpug1-pd { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-index = <6>; + domain-name = "vpu_g1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + }; + + +Specifying Power domain for IP modules +====================================== + +IP cores belonging to a power domain should contain a 'power-domains' +property that is a phandle for PGC node representing the domain. + +Example of a device that is part of the vpu_g1 power domain: + vpu_g1: vpu_g1@38300000 { + /* ... */ + interrupts = ; + interrupt-names = "irq_hantro"; + /* ... */ + power-domains = <&vpu_g1_pd>; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt linux-imx-phytec/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt --- linux-6.1.55/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt 2024-06-19 12:33:57.412177381 +0200 @@ -9,15 +9,20 @@ "fsl,mpc8548-pmc" should be listed for any chip whose PMC is compatible. "fsl,mpc8536-pmc" should also be listed for any chip - whose PMC is compatible, and implies deep-sleep capability. + whose PMC is compatible, and implies deep-sleep capability and + wake on user defined packet(wakeup on ARP). + + "fsl,p1022-pmc" should be listed for any chip whose PMC is + compatible, and implies lossless Ethernet capability during sleep. "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is compatible; all statements below that apply to "fsl,mpc8548-pmc" also apply to "fsl,mpc8641d-pmc". Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these - bit assignments are indicated via the sleep specifier in each device's - sleep property. + bit assignments are indicated via the clock nodes. Device which has a + controllable clock source should have a "fsl,pmc-handle" property pointing + to the clock node. - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource is the PMC block, and the second resource is the Clock Configuration @@ -33,31 +38,35 @@ this is a phandle to an "fsl,gtm" node on which timer 4 can be used as a wakeup source from deep sleep. -Sleep specifiers: - - fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit - that is set in the cell, the corresponding bit in SCCR will be saved - and cleared on suspend, and restored on resume. This sleep controller - supports disabling and resuming devices at any time. - - fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of - which will be ORed into PMCDR upon suspend, and cleared from PMCDR - upon resume. The first two cells are as described for fsl,mpc8578-pmc. - This sleep controller only supports disabling devices during system - sleep, or permanently. - - fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the - first of which will be ORed into DEVDISR (and the second into - DEVDISR2, if present -- this cell should be zero or absent if the - hardware does not have DEVDISR2) upon a request for permanent device - disabling. This sleep controller does not support configuring devices - to disable during system sleep (unless supported by another compatible - match), or dynamically. +Clock nodes: +The clock nodes are to describe the masks in PM controller registers for each +soc clock. +- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be + ORed into PMCDR before suspend if the device using this clock is the wake-up + source and need to be running during low power mode; clear the mask if + otherwise. + +- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding + bit specified by the mask in SCCR will be saved and cleared on suspend, and + restored on resume. + +- fsl,devdisr-mask: Contain one or two cells, depending on the availability of + DEVDISR2 register. For compatible devices, the mask will be ORed into DEVDISR + or DEVDISR2 when the clock should be permenently disabled. Example: - power@b00 { - compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; - reg = <0xb00 0x100 0xa00 0x100>; - interrupts = <80 8>; + power@e0070 { + compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc"; + reg = <0xe0070 0x20>; + + etsec1_clk: soc-clk@24 { + fsl,pmcdr-mask = <0x00000080>; + }; + etsec2_clk: soc-clk@25 { + fsl,pmcdr-mask = <0x00000040>; + }; + etsec3_clk: soc-clk@26 { + fsl,pmcdr-mask = <0x00000020>; + }; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/pwm/pwm-rpmsg-imx.yaml linux-imx-phytec/Documentation/devicetree/bindings/pwm/pwm-rpmsg-imx.yaml --- linux-6.1.55/Documentation/devicetree/bindings/pwm/pwm-rpmsg-imx.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/pwm/pwm-rpmsg-imx.yaml 2024-06-19 12:33:57.416177450 +0200 @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-rpmsg-imx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX PWM over RPMSG driver + +maintainers: + - Clark Wang + +description: | + Acore may need to use some TPM resources of Mcore on some SoC platforms. + This driver provide a protocol to send pwm request through RPMSG to + Mcore and control the TPM modules on Mcore. + Mcore will operate its TPM modules according to the Acore request. + +properties: + "#pwm-cells": + const: 3 + + compatible: + enum: + - fsl,pwm-rpchip + + fsl,pwm-channel-number: + maxItems: 1 + +required: + - "#pwm-cells" + - compatible + - fsl,pwm-channel-number + +additionalProperties: false + +examples: + - | + tpm_rpchip_0: pwm { + compatible = "fsl,pwm-rpchip"; + fsl,pwm-channel-number = <6>; + #pwm-cells = <3>; + status = "okay"; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml linux-imx-phytec/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml --- linux-6.1.55/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml 2024-06-19 12:33:57.420177518 +0200 @@ -28,6 +28,8 @@ - nxp,pca9450a - nxp,pca9450b - nxp,pca9450c + - nxp,pca9451a + - nxp,pca9452 reg: maxItems: 1 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/regulator/pfuze100.yaml linux-imx-phytec/Documentation/devicetree/bindings/regulator/pfuze100.yaml --- linux-6.1.55/Documentation/devicetree/bindings/regulator/pfuze100.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/regulator/pfuze100.yaml 2024-06-19 12:33:57.420177518 +0200 @@ -56,6 +56,11 @@ IC (PMIC) on PMIC_STBY_REQ signal. As opposite to PMIC_STBY_REQ boards can implement PMIC_ON_REQ signal. + fsl,lpsr-mode: + $ref: /schemas/types.yaml#/definitions/flag + description: | + some registers need to be saved and restored in lpsr mode for pfuze3000. + regulators: type: object description: | diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml linux-imx-phytec/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml --- linux-6.1.55/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml 2024-06-19 12:33:57.424177586 +0200 @@ -22,6 +22,8 @@ - fsl,imx8mn-cm7 - fsl,imx8mp-cm7 - fsl,imx8mq-cm4 + - fsl,imx8qm-cm4 + - fsl,imx8qxp-cm4 - fsl,imx8ulp-cm33 - fsl,imx93-cm33 @@ -54,12 +56,26 @@ minItems: 1 maxItems: 32 + power-domains: + maxItems: 8 + fsl,auto-boot: $ref: /schemas/types.yaml#/definitions/flag description: Indicate whether need to load the default firmware and start the remote processor automatically. + fsl,entry-address: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Specify CPU entry address for SCU enabled processor. + + fsl,resource-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + This property is to specify the resource id of the remote processor in SoC + which supports SCFW + required: - compatible diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/reset/gpio-reset.txt linux-imx-phytec/Documentation/devicetree/bindings/reset/gpio-reset.txt --- linux-6.1.55/Documentation/devicetree/bindings/reset/gpio-reset.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/reset/gpio-reset.txt 2024-06-19 12:33:57.428177655 +0200 @@ -0,0 +1,36 @@ +GPIO reset controller +===================== + +A GPIO reset controller controls a single GPIO that is connected to the reset +pin of a peripheral IC. Please also refer to reset.txt in this directory for +common reset controller binding usage. + +Required properties: +- compatible: Should be "gpio-reset" +- reset-gpios: A gpio used as reset line. The gpio specifier for this property + depends on the gpio controller that provides the gpio. +- #reset-cells: 0, see below + +Optional properties: +- reset-delay-us: delay in microseconds. The gpio reset line will be asserted for + this duration to reset. +- reset-post-delay-ms: delay in milliseconds to wait after reset. +- initially-in-reset: boolean. If not set, the initial state should be a + deasserted reset line. If this property exists, the + reset line should be kept in reset. + +example: + +sii902x_reset: gpio-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + initially-in-reset; + #reset-cells = <0>; +}; + +/* Device with nRESET pin connected to GPIO5_0 */ +sii902x@39 { + /* ... */ + resets = <&sii902x_reset>; /* active-low GPIO5_0, 10 ms delay */ +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt linux-imx-phytec/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt --- linux-6.1.55/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt 2024-06-19 12:33:57.428177655 +0200 @@ -0,0 +1,58 @@ +NXP Display Mix clk-en Reset Controller +======================================= + +This binding describes a reset controller device that is used to enable +or disable the internal clocks for all the submodules(such as, LCDIF, +MIPI DSI, MIPI CSI, ISI and etc) included by the Display Mix subsystem +on IMX8MM and IMX8MN platforms. Like sft-rstn, only assert and deassert +functions are required for submodule internal clocks enable or disable, +that means the clk-en can be treated as a real reset controller. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "fsl,imx8mm-dispmix-clk-en" or + "fsl,imx8mn-dispmix-clk-en". +- reg: should be register base and length as documented in the datasheet. +- clocks: phandle and clock specifier to disp apb clock for register access. +- clock-names: should be "disp-apb". +- power-domains: phandle to dispmix power domain. +- reset-cells: 1, see below. + +example: + + dispmix_clk_en: dispmix-clk-en@32e28004 { + compatible = "fsl,imx8mn-dispmix-clk-en"; + reg = <0x0 0x32e28004 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp-apb"; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + +Specifying clk-en control of devices +==================================== + +Device nodes in Display Mix should specify the reset channel required in +their "resets" property, containing a phandle to the clk-en device node +and an index to specify which channel to use, as described in +Documentation/devicetree/bindings/reset/reset.txt. + +example: + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-clk-enable { + compatible = "lcdif,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_LCDIF_APB_CLK_EN>, + <&dispmix_clk_en IMX8MN_LCDIF_PIXEL_CLK_EN>; + }; + }; + +Macro definitions for the supported reset channels can be found in: +include/dt-bindings/reset/imx8mm-dispmix.h and +include/dt-bindings/reset/imx8mn-dispmix.h. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt linux-imx-phytec/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt --- linux-6.1.55/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt 2024-06-19 12:33:57.428177655 +0200 @@ -0,0 +1,57 @@ +NXP Display Mix mipi-rst Reset Controller +========================================= + +This binding describes a reset controller device that is used to reset +or de-reset the MIPI DPHY master direction(for MIPI DSI) and slave +direction(for MIPI CSI) included by the Display Mix subsystem on IMX8MM +and IMX8MN platforms. Like sft-rstn, only assert and deassert functions +are required for PHY reset or de-reset. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "fsl,imx8mm-dispmix-mipi-rst" or + "fsl,imx8mn-dispmix-mipi-rst". +- reg: should be register base and length as documented in the datasheet. +- clocks: phandle and clock specifier to disp apb clock for register access. +- clock-names: should be "disp-apb". +- power-domains: phandle to dispmix power domain. +- reset-cells: 1, see below. + +example: + + dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { + compatible = "fsl,imx8mn-dispmix-mipi-rst"; + reg = <0x0 0x32e28008 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp-apb"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + +Specifying mipi-rst control of devices +====================================== + +Device nodes in Display Mix should specify the reset channel required in +their "resets" property, containing a phandle to the mipi-rst device node +and an index to specify which channel to use, as described in +Documentation/devicetree/bindings/reset/reset.txt. + +example: + + mipi_dsi_resets: mipi-dsi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + dsi-mipi-reset { + compatible = "dsi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MN_MIPI_M_RESET>; + }; + }; + +Macro definitions for the supported reset channels can be found in: +include/dt-bindings/reset/imx8mm-dispmix.h and +include/dt-bindings/reset/imx8mn-dispmix.h. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt linux-imx-phytec/Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt --- linux-6.1.55/Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt 2024-06-19 12:33:57.428177655 +0200 @@ -0,0 +1,58 @@ +NXP Display Mix sft-rstn Reset Controller +========================================= + +This binding describes a reset controller device that is used to reset +or de-reset all the submodules(such as, LCDIF, MIPI DSI, MIPI CSI, ISI +and etc) included by the Display Mix subsystem on IMX8MM and IMX8MN +platforms. Only assert and deassert functions are required for submodule +reset or de-reset. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "fsl,imx8mm-dispmix-sft-rstn" or + "fsl,imx8mn-dispmix-sft-rstn". +- reg: should be register base and length as documented in the datasheet. +- clocks: phandle and clock specifier to disp apb clock for register access. +- clock-names: should be "disp-apb". +- power-domains: phandle to dispmix power domain. +- reset-cells: 1, see below. + +example: + + dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { + compatible = "fsl,imx8mm-dispmix-sft-rstn"; + reg = <0x0 0x32e28000 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp-apb"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + +Specifying sft-rstn control of devices +====================================== + +Device nodes in Display Mix should specify the reset channel required in +their "resets" property, containing a phandle to the sft-rstn device node +and an index to specify which channel to use, as described in +Documentation/devicetree/bindings/reset/reset.txt. + +example: + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-soft-resetn { + compatible = "lcdif,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_LCDIF_APB_CLK_RESET>, + <&dispmix_sft_rstn IMX8MN_LCDIF_PIXEL_CLK_RESET>; + }; + }; + +Macro definitions for the supported reset channels can be found in: +include/dt-bindings/reset/imx8mm-dispmix.h and +include/dt-bindings/reset/imx8mn-dispmix.h. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/reset/nxp,imx8ulp-sim-reset.yaml linux-imx-phytec/Documentation/devicetree/bindings/reset/nxp,imx8ulp-sim-reset.yaml --- linux-6.1.55/Documentation/devicetree/bindings/reset/nxp,imx8ulp-sim-reset.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/reset/nxp,imx8ulp-sim-reset.yaml 2024-06-19 12:33:57.428177655 +0200 @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nxp,imx8ulp-sim-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ulp System Integration Module Reset Controller + +maintainers: + - Liu Ying + +description: | + The i.MX8ulp SIM (System Integration Module) may contain reset controller to + reset peripherals. The reset controller is controlled by the SIM. So, the + reset controller's device node has to be a child node of the SIM's device + node. Peripherals that need access to reset lines should specify them as a + reset phandle in their corresponding device nodes as specified in reset.txt. + +properties: + compatible: + const: nxp,imx8ulp-avd-sim-reset + + '#reset-cells': + const: 1 + +required: + - compatible + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + syscon@2da50000 { + compatible = "nxp,imx8ulp-avd-sim", "syscon", "simple-mfd"; + reg = <0x2da50000 0x38>; + clocks = <&pcc5 IMX8ULP_CLK_AVD_SIM>; + + reset-controller { + compatible = "nxp,imx8ulp-avd-sim-reset"; + #reset-cells = <1>; + }; + + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; + }; + }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml linux-imx-phytec/Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml --- linux-6.1.55/Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml 2024-06-19 12:33:57.432177723 +0200 @@ -18,6 +18,11 @@ properties: compatible: const: fsl,imx8qxp-sc-rtc + read-only: + description: + For some use cases, like cockpit, one cockpit domain owns it + while other domain is just a reader. Its needed to provide + /dev/rtc funtion for applications. required: - compatible diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/rtc/microcrystal,rv3028.yaml linux-imx-phytec/Documentation/devicetree/bindings/rtc/microcrystal,rv3028.yaml --- linux-6.1.55/Documentation/devicetree/bindings/rtc/microcrystal,rv3028.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/rtc/microcrystal,rv3028.yaml 2024-06-19 12:33:57.432177723 +0200 @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/microcrystal,rv3028.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip RV-3028 RTC + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Alexandre Belloni + +properties: + compatible: + const: microcrystal,rv3028 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + trickle-resistor-ohms: + enum: + - 3000 + - 5000 + - 9000 + - 15000 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@51 { + compatible = "microcrystal,rv3028"; + reg = <0x51>; + pinctrl-0 = <&rtc_nint_pins>; + interrupts-extended = <&gpio1 16 IRQ_TYPE_LEVEL_HIGH>; + trickle-resistor-ohms = <3000>; + }; + }; + +... diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/rtc/nxp,pcf2131.yaml linux-imx-phytec/Documentation/devicetree/bindings/rtc/nxp,pcf2131.yaml --- linux-6.1.55/Documentation/devicetree/bindings/rtc/nxp,pcf2131.yaml 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/rtc/nxp,pcf2131.yaml 2024-06-19 12:33:57.432177723 +0200 @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nxp,pcf2131.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP PCF2131 Real Time Clock + +allOf: + - $ref: "rtc.yaml#" + +maintainers: + - Joy Zou + +properties: + compatible: + const: nxp,pcf2131 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + start-year: true + + reset-source: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + pinctrl-0 = <&rtc_nint_pins>; + interrupts-extended = <&gpio1 16 IRQ_TYPE_LEVEL_LOW>; + reset-source; + }; + }; + +... diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml linux-imx-phytec/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml --- linux-6.1.55/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml 2024-06-19 12:33:57.436177791 +0200 @@ -48,8 +48,6 @@ # Intersil ISL12022 Real-time Clock - isil,isl12022 # Real Time Clock Module with I2C-Bus - - microcrystal,rv3028 - # Real Time Clock Module with I2C-Bus - microcrystal,rv3029 # Real Time Clock - microcrystal,rv8523 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml linux-imx-phytec/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml --- linux-6.1.55/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml 2024-06-19 12:33:57.436177791 +0200 @@ -32,6 +32,22 @@ interrupts: maxItems: 1 + clocks: + maxItems: 1 + + clock-names: + const: lin + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + required: - compatible - reg @@ -45,4 +61,9 @@ compatible = "fsl,s32v234-linflexuart"; reg = <0x40053000 0x1000>; interrupts = <0 59 4>; + clocks = <&clks S32V234_CLK_LIN>; + clock-names = "lin"; + dmas = <&edma 0 20>, + <&edma 0 19>; + dma-names = "rx", "tx"; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt linux-imx-phytec/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt --- linux-6.1.55/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt 2024-06-19 12:33:57.440177860 +0200 @@ -0,0 +1,77 @@ +i.MX RPMSG platform implementations + +Distributed framework is used in IMX RPMSG implementation, refer to the +following requirements: + - The CAN functions contained in M core and RTOS should be ready and + complete functional in 50ms after AMP system is turned on. + - Partition reset. System wouldn't be stalled by the exceptions (e.x + the reset triggered by the system hang) occurred at the other side. + And the RPMSG mechanism should be recovered automactilly after the + partition reset is completed. +In this scenario, the M core and RTOS would be kicked off by bootloader +firstly, then A core and Linux would be loaded later. Both M core/RTOS +and A core/Linux are running independly. +One physical memory region used to store the vring is mandatory required +to pre-reserved and well-knowned by both A core and M core + +Required properties: +- compatible: "fsl,imx8qxp-rpmsg", "fsl,imx8mq-rpmsg", "fsl,imx8mm-rpmsg", + "fsl,imx8qm-rpmsg", "fsl,imx7ulp-rpmsg", "fsl,imx7d-rpmsg", + "fsl,imx6sx-rpmsg". +- vdev-nums: The number of the remote virtual devices. +- reg: The reserved phisical DDR memory used to store vring descriptors. + +Optional properties: +- rpmsg_dma_reserved: The reserved per device dma pool, that used to + allocate the shared memory buffers from the per device. + And it is optional for some platforms, since the system dma pool + is used to allocate the shared memory buffers directly on them. +- mub-partition: The partition ID of muB side, that's optional + and used on i.mx8qm/8qxp for partition reset. The default + value is 3 in driver without this property. + +===================================================================== +Mailbox used by iMX RPMSG + +- mboxes: mailboxes used in the RPMSG transactions. +- mbox-names: names of the mailboxes used in RPMSG. + - "tx":TX channel with 32bit transmit register and IRQ transmit + - "rx":RX channel with 32bit receive register and IRQ support + - "rxdb":RX doorbell channel. + +Example: +Rpmsg node in board dts file. +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + +SOC level dts node definitions: +rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; +}; +rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; +}; +rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + memory-region = <&rpmsg_dma_reserved>; + status = "disabled"; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/sound/simple-card.yaml linux-imx-phytec/Documentation/devicetree/bindings/sound/simple-card.yaml --- linux-6.1.55/Documentation/devicetree/bindings/sound/simple-card.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/sound/simple-card.yaml 2024-06-19 12:33:57.460178201 +0200 @@ -27,6 +27,14 @@ description: dai-link uses bit clock inversion $ref: /schemas/types.yaml#/definitions/flag + playback-only: + description: dai-link is used only for playback + $ref: /schemas/types.yaml#/definitions/flag + + capture-only: + description: dai-link is used only for capture + $ref: /schemas/types.yaml#/definitions/flag + dai-tdm-slot-num: description: see tdm-slot.txt. $ref: /schemas/types.yaml#/definitions/uint32 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml linux-imx-phytec/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml --- linux-6.1.55/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml 2024-06-19 12:33:57.468178339 +0200 @@ -25,9 +25,14 @@ - items: - enum: - fsl,ls1043a-qspi + - fsl,ls1012a-qspi - const: fsl,ls1021a-qspi - items: - enum: + - fsl,ls1088a-qspi + - const: fsl,ls2080a-qspi + - items: + - enum: - fsl,imx8mq-qspi - const: fsl,imx7d-qspi diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml linux-imx-phytec/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml --- linux-6.1.55/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml 2024-06-19 12:33:57.468178339 +0200 @@ -56,6 +56,13 @@ this property to re-config the chipselect value in the LPSPI driver. type: boolean + num-cs: + description: + number of chip selects. + minimum: 1 + maximum: 2 + default: 1 + required: - compatible - reg @@ -80,4 +87,5 @@ clock-names = "per", "ipg"; spi-slave; fsl,spi-only-use-cs1-sel; + num-cs = <2>; }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml linux-imx-phytec/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml --- linux-6.1.55/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml 2024-06-19 12:33:57.468178339 +0200 @@ -45,6 +45,13 @@ - const: fspi_en - const: fspi + nxp,fspi-individual-mode: + description: + if fspi porta and portb connect to individual devices, this property + inform the driver not to combine them together. + type: boolean + + required: - compatible - reg diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt linux-imx-phytec/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt --- linux-6.1.55/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt 2024-06-19 12:33:57.480178543 +0200 @@ -90,6 +90,7 @@ case, the "idle" state needs to pull down the data and strobe pin and the "active" state needs to pull up the strobe pin. - pinctrl-n: alternate pin modes +- ci-disable-lpm: Some chipidea hardware need to disable low power mode i.mx specific properties - fsl,usbmisc: phandler of non-core register device, with one diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/usb/snps,dwc3.yaml linux-imx-phytec/Documentation/devicetree/bindings/usb/snps,dwc3.yaml --- linux-6.1.55/Documentation/devicetree/bindings/usb/snps,dwc3.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/usb/snps,dwc3.yaml 2024-06-19 12:33:57.484178612 +0200 @@ -33,6 +33,14 @@ contains: oneOf: - const: snps,dwc3 + - const: fsl,ls1012a-dwc3 + - const: fsl,ls1021a-dwc3 + - const: fsl,ls1028a-dwc3 + - const: fsl,ls1043a-dwc3 + - const: fsl,ls1046a-dwc3 + - const: fsl,ls1088a-dwc3 + - const: fsl,ls2088a-dwc3 + - const: fsl,lx2160a-dwc3 - const: synopsys,dwc3 deprecated: true @@ -246,6 +254,13 @@ of resume. This option is to support certain legacy ULPI PHYs. type: boolean + snps,host-vbus-glitches: + description: + When set, power off all Root Hub ports immediately after + setting host mode to avoid vbus (negative) glitch happen in later + xhci reset. And the vbus will back to 5V automatically when reset done. + type: boolean + snps,is-utmi-l1-suspend: description: True when DWC3 asserts output signal utmi_l1_suspend_n, false when diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/usb/typec-switch-gpio.txt linux-imx-phytec/Documentation/devicetree/bindings/usb/typec-switch-gpio.txt --- linux-6.1.55/Documentation/devicetree/bindings/usb/typec-switch-gpio.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/devicetree/bindings/usb/typec-switch-gpio.txt 2024-06-19 12:33:57.484178612 +0200 @@ -0,0 +1,31 @@ +Typec orientation switch via a GPIO +----------------------------------- + +Required properties: +- compatible: should be set one of following: + - "nxp,ptn36043" or "nxp,cbtl04gp" for NXP Type-C SuperSpeed + active switch. + +- gpios: the GPIO used to switch the super speed active channel, + GPIO_ACTIVE_HIGH: GPIO state high for cc1; + GPIO_ACTIVE_LOW: GPIO state low for cc1. +- orientation-switch: must be present. + +Required sub-node: +- port: specify the remote endpoint of typec switch consumer. + +Example: + +ptn36043 { + compatible = "nxp,ptn36043"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ss_sel>; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/usb/usb-nop-xceiv.yaml linux-imx-phytec/Documentation/devicetree/bindings/usb/usb-nop-xceiv.yaml --- linux-6.1.55/Documentation/devicetree/bindings/usb/usb-nop-xceiv.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/usb/usb-nop-xceiv.yaml 2024-06-19 12:33:57.484178612 +0200 @@ -39,6 +39,11 @@ the VBus line. $ref: /schemas/types.yaml#/definitions/phandle + wakeup-source: + description: + Specify if the USB phy can detect the remote wakeup signal + while the system sleep. + required: - compatible - '#phy-cells' diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/usb/usb-xhci.yaml linux-imx-phytec/Documentation/devicetree/bindings/usb/usb-xhci.yaml --- linux-6.1.55/Documentation/devicetree/bindings/usb/usb-xhci.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/usb/usb-xhci.yaml 2024-06-19 12:33:57.484178612 +0200 @@ -25,6 +25,11 @@ description: Set if the controller has broken port disable mechanism type: boolean + usb3-resume-missing-cas: + description: set if the CAS(Cold Attach Status) may lose in case device + plugged in while system sleep. + type: boolean + imod-interval-ns: description: Interrupt moderation interval default: 5000 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/vendor-prefixes.yaml linux-imx-phytec/Documentation/devicetree/bindings/vendor-prefixes.yaml --- linux-6.1.55/Documentation/devicetree/bindings/vendor-prefixes.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/vendor-prefixes.yaml 2024-06-19 12:33:57.484178612 +0200 @@ -607,6 +607,8 @@ description: Injoinic Technology Corp. "^innolux,.*": description: Innolux Corporation + "^inphi,.*": + description: Inphi Corporation "^inside-secure,.*": description: INSIDE Secure "^insignal,.*": @@ -823,6 +825,8 @@ description: Mixel, Inc. "^miyoo,.*": description: Miyoo + "^mixel,.*": + description: Mixel, Inc "^mntre,.*": description: MNT Research GmbH "^modtronix,.*": diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml linux-imx-phytec/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml --- linux-6.1.55/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml 2024-06-19 12:33:57.488178681 +0200 @@ -30,8 +30,18 @@ clocks: maxItems: 1 + fsl,ext-reset-output: + description: + When set, wdog can generate external reset from the wdog_any pin. + type: boolean + timeout-sec: true + fsl,ext-reset-output: + description: + When set, wdog can generate external reset from the wdog_any pin. + type: boolean + required: - compatible - interrupts diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/mac-phy-support.rst linux-imx-phytec/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/mac-phy-support.rst --- linux-6.1.55/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/mac-phy-support.rst 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/mac-phy-support.rst 2024-06-19 12:33:57.604180664 +0200 @@ -181,10 +181,13 @@ - int dpaa2_mac_connect(struct dpaa2_mac *mac); - void dpaa2_mac_disconnect(struct dpaa2_mac *mac); -A phylink integration is necessary only when the partner DPMAC is not of TYPE_FIXED. -One can check for this condition using the below API:: +A phylink integration is necessary only when the partner DPMAC is not of +``TYPE_FIXED``. This means it is either of ``TYPE_PHY``, or of +``TYPE_BACKPLANE`` (the difference being the two that in the ``TYPE_BACKPLANE`` +mode, the MC firmware does not access the PCS registers). One can check for +this condition using the following helper:: - - bool dpaa2_mac_is_type_fixed(struct fsl_mc_device *dpmac_dev,struct fsl_mc_io *mc_io); + - static inline bool dpaa2_mac_is_type_phy(struct dpaa2_mac *mac); Before connection to a MAC, the caller must allocate and populate the dpaa2_mac structure with the associated net_device, a pointer to the MC portal diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/networking/phy.rst linux-imx-phytec/Documentation/networking/phy.rst --- linux-6.1.55/Documentation/networking/phy.rst 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/networking/phy.rst 2024-06-19 12:33:57.620180938 +0200 @@ -323,6 +323,20 @@ contrast with the 1000BASE-X phy mode used for Clause 38 and 39 PMDs, this interface mode has different autonegotiation and only supports full duplex. +``PHY_INTERFACE_MODE_10G_QXGMII`` + Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII + Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz + SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved + through symbol replication. The PCS expects the standard USXGMII code word. + +``PHY_INTERFACE_MODE_25GKR`` + This is the 25GBASE-R PCS as defined by IEEE 802.3 Clause 107, resolved + through Clause 73 autonegotiation. + +``PHY_INTERFACE_MODE_40GKR4`` + This is the 40GBASE-R PCS as defined by IEEE 802.3 Clause 84, resolved + through Clause 73 autonegotiation. + Pause frames / flow control =========================== diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/security/keys/secure-key.rst linux-imx-phytec/Documentation/security/keys/secure-key.rst --- linux-6.1.55/Documentation/security/keys/secure-key.rst 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/Documentation/security/keys/secure-key.rst 2024-06-19 12:33:57.656181554 +0200 @@ -0,0 +1,67 @@ +========== +Secure Key +========== + +Secure key is the new type added to kernel key ring service. +Secure key is a symmetric type key of minimum length 32 bytes +and with maximum possible length to be 128 bytes. It is produced +in kernel using the CAAM crypto engine. Userspace can only see +the blob for the corresponding key. All the blobs are displayed +or loaded in hex ascii. + +Secure key can be created on platforms which supports CAAM +hardware block. Secure key can also be used as a master key to +create the encrypted keys along with the existing key types in +kernel. + +Secure key uses CAAM hardware to generate the key and blobify its +content for userspace. Generated blobs are tied up with the hardware +secret key stored in CAAM, hence the same blob will not be able to +de-blobify with the different secret key on another machine. + +Usage:: + + keyctl add secure "new " + keyctl load secure "load " + keyctl print + +"keyctl add secure" option will create the random data of the +specified key len using CAAM and store it as a key in kernel. +Key contents will be displayed as blobs to the user in hex ascii. +User can input key len from 32 bytes to 128 bytes. + +"keyctl load secure" option will load the blob contents. In kernel, +key will be deirved using input blob and CAAM, along with the secret +key stored in CAAM. + +"keyctl print" will return the hex string of the blob corresponding to +key_id. Returned blob will be of key_len + 48 bytes. Extra 48 bytes are +the header bytes added by the CAAM. + +Example of secure key usage:: + +1. Create the secure key with name kmk-master of length 32 bytes:: + + $ keyctl add secure kmk-master "new 32" @u + 46001928 + + $keyctl show + Session Keyring + 1030783626 --alswrv 0 65534 keyring: _uid_ses.0 + 695927745 --alswrv 0 65534 \_ keyring: _uid.0 + 46001928 --als-rv 0 0 \_ secure: kmk-master + +2. Print the blob contents for the kmk-master key:: + + $ keyctl print 46001928 + d9743445b640f3d59c1670dddc0bc9c2 + 34fc9aab7dd05c965e6120025012f029b + 07faa4776c4f6ed02899e35a135531e9a + 6e5c2b51132f9d5aef28f68738e658296 + 3fe583177cfe50d2542b659a13039 + + $ keyctl pipe 46001928 > secure_key.blob + +3. Load the blob in the user key ring:: + + $ keyctl load secure kmk-master "load 'cat secure_key.blob'" @u diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/userspace-api/ioctl/ioctl-number.rst linux-imx-phytec/Documentation/userspace-api/ioctl/ioctl-number.rst --- linux-6.1.55/Documentation/userspace-api/ioctl/ioctl-number.rst 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/userspace-api/ioctl/ioctl-number.rst 2024-06-19 12:33:57.716182579 +0200 @@ -161,7 +161,8 @@ 'I' all linux/isdn.h conflict! 'I' 00-0F drivers/isdn/divert/isdn_divert.h conflict! 'I' 40-4F linux/mISDNif.h conflict! -'K' all linux/kd.h +'K' all linux/kd.h conflict! +'K' 00-01 linux/caam_keygen.h conflict! caam driver 'L' 00-1F linux/loop.h conflict! 'L' 10-1F drivers/scsi/mpt3sas/mpt3sas_ctl.h conflict! 'L' E0-FF linux/ppdd.h encrypted disk device driver diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst linux-imx-phytec/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst --- linux-6.1.55/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst 2024-06-19 12:33:57.740182989 +0200 @@ -88,6 +88,11 @@ - ``V4L2_PIX_FMT_H263`` - 'H263' - H263 video elementary stream. + * .. _V4L2-PIX-FMT-SPK: + + - ``V4L2_PIX_FMT_SPK`` + - 'SPK0' + - Sorenson Spark is an implementation of H.263 for use in Flash Video and Adobe Flash files * .. _V4L2-PIX-FMT-MPEG1: - ``V4L2_PIX_FMT_MPEG1`` @@ -232,6 +237,26 @@ Metadata associated with the frame to decode is required to be passed through the ``V4L2_CID_STATELESS_FWHT_PARAMS`` control. See the :ref:`associated Codec Control ID `. + * .. _V4L2-PIX-FMT-RV30: + + - ``V4L2_PIX_FMT_RV30`` + - 'RV30' + - RealVideo, or also spelled as Real Video, is a suite of + proprietary video compression formats developed by + RealNetworks - the specific format changes with the version. + RealVideo codecs are identified by four-character codes. + RV30 corresponds to RealVideo 8, suspected to be based + largely on an early draft of H.264 + * .. _V4L2-PIX-FMT-RV40: + + - ``V4L2_PIX_FMT_RV40`` + - 'RV40' + - RV40 represents RealVideo 9 and RealVideo 10. + RealVideo 9, suspected to be based on H.264. + RealVideo 10, aka RV9 EHQ, This refers to an improved encoder + for the RV9 format that is fully backwards compatible with + RV9 players - the format and decoder did not change, only + the encoder did. As a result, it uses the same FourCC. .. raw:: latex diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/userspace-api/media/v4l/pixfmt-packed-yuv.rst linux-imx-phytec/Documentation/userspace-api/media/v4l/pixfmt-packed-yuv.rst --- linux-6.1.55/Documentation/userspace-api/media/v4l/pixfmt-packed-yuv.rst 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/userspace-api/media/v4l/pixfmt-packed-yuv.rst 2024-06-19 12:33:57.740182989 +0200 @@ -257,6 +257,34 @@ - The padding bits contain undefined values that must be ignored by all applications and drivers. +The next table lists the packed YUV 4:4:4 formats with 12 bits per component. +Expand the bits per component to 16 bits, data in the high bits, zeros in the low bits, +arranged in little endian order, storing 1 pixel in 6 bytes. + +.. flat-table:: Packed YUV 4:4:4 Image Formats (12bpc) + :header-rows: 1 + :stub-columns: 0 + + * - Identifier + - Code + - Byte 1-0 + - Byte 3-2 + - Byte 5-4 + - Byte 7-6 + - Byte 9-8 + - Byte 11-10 + + * .. _V4L2-PIX-FMT-YUV48-12: + + - ``V4L2_PIX_FMT_YUV48_12`` + - 'Y312' + + - Y'\ :sub:`0` + - Cb\ :sub:`0` + - Cr\ :sub:`0` + - Y'\ :sub:`1` + - Cb\ :sub:`1` + - Cr\ :sub:`1` 4:2:2 Subsampling ================= @@ -339,6 +367,48 @@ .. raw:: latex + \normalsize + +The next lists the packed YUV 4:2:2 formats with more than 8 bits per component. +expand the bits per component to 16 bits, data in the high bits, zeros in the low bits, +arranged in little endian order. storing 2 pixels in 8 bytes. + +.. raw:: latex + + \footnotesize + +.. tabularcolumns:: |p{3.4cm}|p{1.2cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}| + +.. flat-table:: Packed YUV 4:2:2 Formats (more than 8bpc) + :header-rows: 1 + :stub-columns: 0 + + * - Identifier + - Code + - Byte 1-0 + - Byte 3-2 + - Byte 5-4 + - Byte 7-6 + - Byte 9-8 + - Byte 11-10 + - Byte 13-12 + - Byte 15-14 + * .. _V4L2-PIX-FMT-Y212: + + - ``V4L2_PIX_FMT_Y212`` + - 'Y212' + + - Y'\ :sub:`0` + - Cb\ :sub:`0` + - Y'\ :sub:`1` + - Cr\ :sub:`0` + - Y'\ :sub:`2` + - Cb\ :sub:`2` + - Y'\ :sub:`3` + - Cr\ :sub:`2` + +.. raw:: latex + \normalsize **Color Sample Location:** diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/userspace-api/media/v4l/pixfmt-rgb.rst linux-imx-phytec/Documentation/userspace-api/media/v4l/pixfmt-rgb.rst --- linux-6.1.55/Documentation/userspace-api/media/v4l/pixfmt-rgb.rst 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/userspace-api/media/v4l/pixfmt-rgb.rst 2024-06-19 12:33:57.744183058 +0200 @@ -762,6 +762,48 @@ \normalsize +12 Bits Per Component +============================== + +These formats store an RGB triplet in six or eight bytes, with 12 bits per component. +Expand the bits per component to 16 bits, data in the high bits, zeros in the low bits, +arranged in little endian order. + +.. raw:: latex + + \small + +.. flat-table:: RGB Formats With 12 Bits Per Component + :header-rows: 1 + + * - Identifier + - Code + - Byte 1-0 + - Byte 3-2 + - Byte 5-4 + - Byte 7-6 + * .. _V4L2-PIX-FMT-BGR48-12: + + - ``V4L2_PIX_FMT_BGR48_12`` + - 'B312' + + - B\ :sub:`15-4` + - G\ :sub:`15-4` + - R\ :sub:`15-4` + - + * .. _V4L2-PIX-FMT-ABGR64-12: + + - ``V4L2_PIX_FMT_ABGR64_12`` + - 'B412' + + - B\ :sub:`15-4` + - G\ :sub:`15-4` + - R\ :sub:`15-4` + - A\ :sub:`15-4` + +.. raw:: latex + + \normalsize Deprecated RGB Formats ====================== diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst linux-imx-phytec/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst --- linux-6.1.55/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst 2024-06-19 12:33:57.744183058 +0200 @@ -103,6 +103,17 @@ - ... - ... + * .. _V4L2-PIX-FMT-Y012: + + - ``V4L2_PIX_FMT_Y012`` + - 'Y012' + + - Y'\ :sub:`0`\ [3:0] `0000` + - Y'\ :sub:`0`\ [11:4] + - ... + - ... + - ... + * .. _V4L2-PIX-FMT-Y14: - ``V4L2_PIX_FMT_Y14`` diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst linux-imx-phytec/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst --- linux-6.1.55/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst 2024-06-19 12:33:57.744183058 +0200 @@ -123,6 +123,20 @@ - Cb, Cr - Yes - 4x4 tiles + * - V4L2_PIX_FMT_P012 + - 'P012' + - 12 + - 4:2:0 + - Cb, Cr + - Yes + - Linear + * - V4L2_PIX_FMT_P012M + - 'PM12' + - 12 + - 4:2:0 + - Cb, Cr + - Yes + - Linear * - V4L2_PIX_FMT_NV16 - 'NV16' - 8 @@ -273,7 +287,9 @@ .. _V4L2-PIX-FMT-NV12-16L16: .. _V4L2-PIX-FMT-NV12-32L32: .. _V4L2-PIX-FMT-NV12M-8L128: +.. _V4L2-PIX-FMT-NV12-8L128: .. _V4L2-PIX-FMT-NV12M-10BE-8L128: +.. _V4L2-PIX-FMT-NV12-10BE-8L128: .. _V4L2-PIX-FMT-MM21: Tiled NV12 @@ -319,6 +335,9 @@ The image height must be aligned to a multiple of 128. The layouts of the luma and chroma planes are identical. +``V4L2_PIX_FMT_NV12_8L128`` is similar to ``V4L2_PIX_FMT_NV12M_8L128`` but stores +two planes in one memory. + ``V4L2_PIX_FMT_NV12M_10BE_8L128`` is similar to ``V4L2_PIX_FMT_NV12M`` but stores 10 bits pixels in 2D 8x128 tiles, and stores tiles linearly in memory. the data is arranged in big endian order. @@ -334,6 +353,9 @@ byte 3: Y2(bits 5-0) Y3(bits 9-8) byte 4: Y3(bits 7-0) +``V4L2_PIX_FMT_NV12_10BE_8L128`` is similar to ``V4L2_PIX_FMT_NV12M_10BE_8L128`` but stores +two planes in one memory. + ``V4L2_PIX_FMT_MM21`` store luma pixel in 16x32 tiles, and chroma pixels in 16x16 tiles. The line stride must be aligned to a multiple of 16 and the image height must be aligned to a multiple of 32. The number of luma and chroma @@ -576,6 +598,86 @@ - Cb\ :sub:`10` - Cr\ :sub:`10` - Cb\ :sub:`11` + - Cr\ :sub:`11` + +.. _V4L2-PIX-FMT-P012: +.. _V4L2-PIX-FMT-P012M: + +P012 and P012M +-------------- + +P012 is like NV12 with 12 bits per component, expanded to 16 bits. +Data in the 12 high bits, zeros in the 4 low bits, arranged in little endian order. + +.. flat-table:: Sample 4x4 P012 Image + :header-rows: 0 + :stub-columns: 0 + + * - start + 0: + - Y'\ :sub:`00` + - Y'\ :sub:`01` + - Y'\ :sub:`02` + - Y'\ :sub:`03` + * - start + 8: + - Y'\ :sub:`10` + - Y'\ :sub:`11` + - Y'\ :sub:`12` + - Y'\ :sub:`13` + * - start + 16: + - Y'\ :sub:`20` + - Y'\ :sub:`21` + - Y'\ :sub:`22` + - Y'\ :sub:`23` + * - start + 24: + - Y'\ :sub:`30` + - Y'\ :sub:`31` + - Y'\ :sub:`32` + - Y'\ :sub:`33` + * - start + 32: + - Cb\ :sub:`00` + - Cr\ :sub:`00` + - Cb\ :sub:`01` + - Cr\ :sub:`01` + * - start + 40: + - Cb\ :sub:`10` + - Cr\ :sub:`10` + - Cb\ :sub:`11` + - Cr\ :sub:`11` + +.. flat-table:: Sample 4x4 P012M Image + :header-rows: 0 + :stub-columns: 0 + + * - start0 + 0: + - Y'\ :sub:`00` + - Y'\ :sub:`01` + - Y'\ :sub:`02` + - Y'\ :sub:`03` + * - start0 + 8: + - Y'\ :sub:`10` + - Y'\ :sub:`11` + - Y'\ :sub:`12` + - Y'\ :sub:`13` + * - start0 + 16: + - Y'\ :sub:`20` + - Y'\ :sub:`21` + - Y'\ :sub:`22` + - Y'\ :sub:`23` + * - start0 + 24: + - Y'\ :sub:`30` + - Y'\ :sub:`31` + - Y'\ :sub:`32` + - Y'\ :sub:`33` + * - + * - start1 + 0: + - Cb\ :sub:`00` + - Cr\ :sub:`00` + - Cb\ :sub:`01` + - Cr\ :sub:`01` + * - start1 + 8: + - Cb\ :sub:`10` + - Cr\ :sub:`10` + - Cb\ :sub:`11` - Cr\ :sub:`11` diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/ata/ahci_imx.c linux-imx-phytec/drivers/ata/ahci_imx.c --- linux-6.1.55/drivers/ata/ahci_imx.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/ata/ahci_imx.c 2024-06-19 12:33:59.408211513 +0200 @@ -18,6 +18,7 @@ #include #include #include +#include #include #include "ahci.h" @@ -43,42 +44,20 @@ /* Clock Reset Register */ IMX_CLOCK_RESET = 0x7f3f, IMX_CLOCK_RESET_RESET = 1 << 0, - /* IMX8QM HSIO AHCI definitions */ - IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET = 0x03, - IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET = 0x09, - IMX8QM_SATA_PHY_IMPED_RATIO_85OHM = 0x6c, - IMX8QM_LPCG_PHYX2_OFFSET = 0x00000, - IMX8QM_CSR_PHYX2_OFFSET = 0x90000, - IMX8QM_CSR_PHYX1_OFFSET = 0xa0000, - IMX8QM_CSR_PHYX_STTS0_OFFSET = 0x4, - IMX8QM_CSR_PCIEA_OFFSET = 0xb0000, - IMX8QM_CSR_PCIEB_OFFSET = 0xc0000, - IMX8QM_CSR_SATA_OFFSET = 0xd0000, - IMX8QM_CSR_PCIE_CTRL2_OFFSET = 0x8, - IMX8QM_CSR_MISC_OFFSET = 0xe0000, - - IMX8QM_LPCG_PHYX2_PCLK0_MASK = (0x3 << 16), - IMX8QM_LPCG_PHYX2_PCLK1_MASK = (0x3 << 20), - IMX8QM_PHY_APB_RSTN_0 = BIT(0), - IMX8QM_PHY_MODE_SATA = BIT(19), - IMX8QM_PHY_MODE_MASK = (0xf << 17), - IMX8QM_PHY_PIPE_RSTN_0 = BIT(24), - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0 = BIT(25), - IMX8QM_PHY_PIPE_RSTN_1 = BIT(26), - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1 = BIT(27), - IMX8QM_STTS0_LANE0_TX_PLL_LOCK = BIT(4), - IMX8QM_MISC_IOB_RXENA = BIT(0), - IMX8QM_MISC_IOB_TXENA = BIT(1), - IMX8QM_MISC_PHYX1_EPCS_SEL = BIT(12), - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 = BIT(24), - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 = BIT(25), - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 = BIT(28), - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0 = BIT(29), - IMX8QM_SATA_CTRL_RESET_N = BIT(12), - IMX8QM_SATA_CTRL_EPCS_PHYRESET_N = BIT(7), - IMX8QM_CTRL_BUTTON_RST_N = BIT(21), - IMX8QM_CTRL_POWER_UP_RST_N = BIT(23), - IMX8QM_CTRL_LTSSM_ENABLE = BIT(4), + /* IMX8QM SATA specific control registers */ + IMX8QM_SATA_PP2CFG_OFFSET = 0xac, + IMX8QM_SATA_PP2CFG_COMINIT_NEGATE_MIN = 0x28 << 24, + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP = 0x18 << 16, + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MAX = 0x2b << 8, + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MIN = 0x1b << 0, + IMX8QM_SATA_PP3CFG_OFFSET = 0xb0, + IMX8QM_SATA_PP3CFG_COMWAKE_NEGATE_MIN = 0x0e << 24, + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP = 0x08 << 16, + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MAX = 0x0f << 8, + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MIN = 0x01 << 0, + IMX8QM_SATA_AHCI_VEND_PTC = 0xc8, + IMX8QM_SATA_AHCI_VEND_PTC_RXWM_MASK = 0x7f, + IMX8QM_SATA_AHCI_VEND_PTC_RXWM = 0x29, }; enum ahci_imx_type { @@ -96,18 +75,17 @@ struct clk *ahb_clk; struct clk *epcs_tx_clk; struct clk *epcs_rx_clk; - struct clk *phy_apbclk; - struct clk *phy_pclk0; - struct clk *phy_pclk1; - void __iomem *phy_base; - struct gpio_desc *clkreq_gpiod; struct regmap *gpr; + struct phy *sata_phy; + struct phy *cali_phy0; + struct phy *cali_phy1; bool no_device; bool first_time; u32 phy_params; - u32 imped_ratio; }; +void *sg_io_buffer_hack; + static int ahci_imx_hotplug; module_param_named(hotplug, ahci_imx_hotplug, int, 0644); MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)"); @@ -449,201 +427,107 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv) { - u32 val, reg; - int i, ret; + u32 val; + int ret; struct imx_ahci_priv *imxpriv = hpriv->plat_data; struct device *dev = &imxpriv->ahci_pdev->dev; - /* configure the hsio for sata */ - ret = clk_prepare_enable(imxpriv->phy_pclk0); - if (ret < 0) { - dev_err(dev, "can't enable phy_pclk0.\n"); - return ret; - } - ret = clk_prepare_enable(imxpriv->phy_pclk1); - if (ret < 0) { - dev_err(dev, "can't enable phy_pclk1.\n"); - goto disable_phy_pclk0; - } ret = clk_prepare_enable(imxpriv->epcs_tx_clk); if (ret < 0) { dev_err(dev, "can't enable epcs_tx_clk.\n"); - goto disable_phy_pclk1; + return ret; } ret = clk_prepare_enable(imxpriv->epcs_rx_clk); if (ret < 0) { dev_err(dev, "can't enable epcs_rx_clk.\n"); - goto disable_epcs_tx_clk; - } - ret = clk_prepare_enable(imxpriv->phy_apbclk); - if (ret < 0) { - dev_err(dev, "can't enable phy_apbclk.\n"); - goto disable_epcs_rx_clk; + goto err_epcs_rx_clk; } - /* Configure PHYx2 PIPE_RSTN */ - regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET + - IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val); - if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { - /* The link of the PCIEA of HSIO is down */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_PHYX2_OFFSET, - IMX8QM_PHY_PIPE_RSTN_0 | - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0, - IMX8QM_PHY_PIPE_RSTN_0 | - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0); - } - regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET + - IMX8QM_CSR_PCIE_CTRL2_OFFSET, ®); - if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { - /* The link of the PCIEB of HSIO is down */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_PHYX2_OFFSET, - IMX8QM_PHY_PIPE_RSTN_1 | - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1, - IMX8QM_PHY_PIPE_RSTN_1 | - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1); - } - if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { - /* The links of both PCIA and PCIEB of HSIO are down */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_LPCG_PHYX2_OFFSET, - IMX8QM_LPCG_PHYX2_PCLK0_MASK | - IMX8QM_LPCG_PHYX2_PCLK1_MASK, - 0); - } - - /* set PWR_RST and BT_RST of csr_pciea */ - val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET; - regmap_update_bits(imxpriv->gpr, - val, - IMX8QM_CTRL_BUTTON_RST_N, - IMX8QM_CTRL_BUTTON_RST_N); - regmap_update_bits(imxpriv->gpr, - val, - IMX8QM_CTRL_POWER_UP_RST_N, - IMX8QM_CTRL_POWER_UP_RST_N); - - /* PHYX1_MODE to SATA */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_PHYX1_OFFSET, - IMX8QM_PHY_MODE_MASK, - IMX8QM_PHY_MODE_SATA); - /* - * BIT0 RXENA 1, BIT1 TXENA 0 - * BIT12 PHY_X1_EPCS_SEL 1. + * Since "REXT" pin is only present for "lane 0" of + * "PHY Instance 0", and it's calibration result will be + * stored, and shared with "lane 1" of "PHY Instance 0" + * and "lane0" of "PHY Instance 1". + * + * Initialize the "lane 0" and "lane 1" of "PHY Instance 0" + * here, although only "lane 0" of "PHY Instance 1" is used + * by SATA. */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_IOB_RXENA, - IMX8QM_MISC_IOB_RXENA); - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_IOB_TXENA, - 0); - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_PHYX1_EPCS_SEL, - IMX8QM_MISC_PHYX1_EPCS_SEL); - /* - * It is possible, for PCIe and SATA are sharing - * the same clock source, HPLL or external oscillator. - * When PCIe is in low power modes (L1.X or L2 etc), - * the clock source can be turned off. In this case, - * if this clock source is required to be toggling by - * SATA, then SATA functions will be abnormal. - * Set the override here to avoid it. - */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 | - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 | - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 | - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0, - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 | - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 | - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 | - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0); - - /* clear PHY RST, then set it */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_SATA_OFFSET, - IMX8QM_SATA_CTRL_EPCS_PHYRESET_N, - 0); - - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_SATA_OFFSET, - IMX8QM_SATA_CTRL_EPCS_PHYRESET_N, - IMX8QM_SATA_CTRL_EPCS_PHYRESET_N); - - /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_SATA_OFFSET, - IMX8QM_SATA_CTRL_RESET_N, - IMX8QM_SATA_CTRL_RESET_N); - udelay(1); - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_SATA_OFFSET, - IMX8QM_SATA_CTRL_RESET_N, - 0); - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_SATA_OFFSET, - IMX8QM_SATA_CTRL_RESET_N, - IMX8QM_SATA_CTRL_RESET_N); - - /* APB reset */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_PHYX1_OFFSET, - IMX8QM_PHY_APB_RSTN_0, - IMX8QM_PHY_APB_RSTN_0); - - for (i = 0; i < 100; i++) { - reg = IMX8QM_CSR_PHYX1_OFFSET + - IMX8QM_CSR_PHYX_STTS0_OFFSET; - regmap_read(imxpriv->gpr, reg, &val); - val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK; - if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK) - break; - udelay(1); + ret = phy_init(imxpriv->cali_phy0); + if (ret) { + dev_err(dev, "cali PHY init failed\n"); + goto err_cali_phy0_init; + } + + ret = phy_power_on(imxpriv->cali_phy0); + if (ret) { + dev_err(dev, "cali PHY power on failed\n"); + goto err_cali_phy0_power_on; + } + ret = phy_init(imxpriv->cali_phy1); + if (ret) { + dev_err(dev, "cali PHY1 init failed\n"); + goto err_cali_phy1_init; + } + ret = phy_power_on(imxpriv->cali_phy1); + if (ret) { + dev_err(dev, "cali PHY1 power on failed\n"); + goto err_cali_phy1_power_on; + } + + ret = phy_init(imxpriv->sata_phy); + if (ret) { + dev_err(dev, "sata PHY init failed\n"); + goto err_sata_phy_init; + } + + ret = phy_power_on(imxpriv->sata_phy); + if (ret) { + dev_err(dev, "sata PHY power up failed\n"); + goto err_sata_phy_power_on; } - if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) { - dev_err(dev, "TX PLL of the PHY is not locked\n"); - ret = -ENODEV; - } else { - writeb(imxpriv->imped_ratio, imxpriv->phy_base + - IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET); - writeb(imxpriv->imped_ratio, imxpriv->phy_base + - IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET); - reg = readb(imxpriv->phy_base + - IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET); - if (unlikely(reg != imxpriv->imped_ratio)) - dev_info(dev, "Can't set PHY RX impedance ratio.\n"); - reg = readb(imxpriv->phy_base + - IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET); - if (unlikely(reg != imxpriv->imped_ratio)) - dev_info(dev, "Can't set PHY TX impedance ratio.\n"); - usleep_range(50, 100); + /* + * When initialization of SATA PHY is done, the calibration PHYs + * can be turned off. + */ + phy_power_off(imxpriv->cali_phy1); + phy_exit(imxpriv->cali_phy1); + phy_power_off(imxpriv->cali_phy0); + phy_exit(imxpriv->cali_phy0); + + /* RxWaterMark setting */ + val = readl(hpriv->mmio + IMX8QM_SATA_AHCI_VEND_PTC); + val &= ~IMX8QM_SATA_AHCI_VEND_PTC_RXWM_MASK; + val |= IMX8QM_SATA_AHCI_VEND_PTC_RXWM; + writel(val, hpriv->mmio + IMX8QM_SATA_AHCI_VEND_PTC); + + val = IMX8QM_SATA_PP2CFG_COMINIT_NEGATE_MIN | + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP | + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MAX | + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MIN; + writel(val, hpriv->mmio + IMX8QM_SATA_PP2CFG_OFFSET); + val = IMX8QM_SATA_PP3CFG_COMWAKE_NEGATE_MIN | + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP | + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MAX | + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MIN; + writel(val, hpriv->mmio + IMX8QM_SATA_PP3CFG_OFFSET); - /* - * To reduce the power consumption, gate off - * the PHY clks - */ - clk_disable_unprepare(imxpriv->phy_apbclk); - clk_disable_unprepare(imxpriv->phy_pclk1); - clk_disable_unprepare(imxpriv->phy_pclk0); - return ret; - } + return 0; - clk_disable_unprepare(imxpriv->phy_apbclk); -disable_epcs_rx_clk: +err_sata_phy_power_on: + phy_exit(imxpriv->sata_phy); +err_sata_phy_init: + phy_power_off(imxpriv->cali_phy1); +err_cali_phy1_power_on: + phy_exit(imxpriv->cali_phy1); +err_cali_phy1_init: + phy_power_off(imxpriv->cali_phy0); +err_cali_phy0_power_on: + phy_exit(imxpriv->cali_phy0); +err_cali_phy0_init: clk_disable_unprepare(imxpriv->epcs_rx_clk); -disable_epcs_tx_clk: +err_epcs_rx_clk: clk_disable_unprepare(imxpriv->epcs_tx_clk); -disable_phy_pclk1: - clk_disable_unprepare(imxpriv->phy_pclk1); -disable_phy_pclk0: - clk_disable_unprepare(imxpriv->phy_pclk0); return ret; } @@ -697,6 +581,9 @@ } } else if (imxpriv->type == AHCI_IMX8QM) { ret = imx8_sata_enable(hpriv); + if (ret) + goto disable_clk; + } usleep_range(1000, 2000); @@ -735,6 +622,10 @@ break; case AHCI_IMX8QM: + if (imxpriv->sata_phy) { + phy_power_off(imxpriv->sata_phy); + phy_exit(imxpriv->sata_phy); + } clk_disable_unprepare(imxpriv->epcs_rx_clk); clk_disable_unprepare(imxpriv->epcs_tx_clk); break; @@ -759,7 +650,8 @@ ahci_error_handler(ap); - if (!(imxpriv->first_time) || ahci_imx_hotplug) + if (!(imxpriv->first_time) || ahci_imx_hotplug || + (imxpriv->type == AHCI_IMX8QM)) return; imxpriv->first_time = false; @@ -985,31 +877,33 @@ static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv) { - struct resource *phy_res; - struct platform_device *pdev = imxpriv->ahci_pdev; struct device_node *np = dev->of_node; - if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio)) - imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM; - phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); - if (phy_res) { - imxpriv->phy_base = devm_ioremap(dev, phy_res->start, - resource_size(phy_res)); - if (!imxpriv->phy_base) { - dev_err(dev, "error with ioremap\n"); - return -ENOMEM; - } - } else { - dev_err(dev, "missing *phy* reg region.\n"); - return -ENOMEM; + if (!(dev->bus_dma_limit)) { + dev->bus_dma_limit = DMA_BIT_MASK(32); + dev_info(dev, "imx8qm sata only supports 32bit dma.\n"); } - imxpriv->gpr = - syscon_regmap_lookup_by_phandle(np, "hsio"); + + imxpriv->gpr = syscon_regmap_lookup_by_phandle(np, "ctrl-csr"); if (IS_ERR(imxpriv->gpr)) { - dev_err(dev, "unable to find gpr registers\n"); + dev_err(dev, "unable to find hsio ctrl registers\n"); return PTR_ERR(imxpriv->gpr); } + imxpriv->sata_phy = devm_phy_get(dev, "sata-phy"); + if (IS_ERR(imxpriv->sata_phy)) + return dev_err_probe(dev, PTR_ERR(imxpriv->sata_phy), + "failed to get sata_phy\n"); + + imxpriv->cali_phy0 = devm_phy_get(dev, "cali-phy0"); + if (IS_ERR(imxpriv->cali_phy0)) + return dev_err_probe(dev, PTR_ERR(imxpriv->cali_phy0), + "failed to get cali_phy0\n"); + imxpriv->cali_phy1 = devm_phy_get(dev, "cali-phy1"); + if (IS_ERR(imxpriv->cali_phy1)) + return dev_err_probe(dev, PTR_ERR(imxpriv->cali_phy1), + "failed to get cali_phy1\n"); + imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx"); if (IS_ERR(imxpriv->epcs_tx_clk)) { dev_err(dev, "can't get epcs_tx_clk clock.\n"); @@ -1020,30 +914,6 @@ dev_err(dev, "can't get epcs_rx_clk clock.\n"); return PTR_ERR(imxpriv->epcs_rx_clk); } - imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0"); - if (IS_ERR(imxpriv->phy_pclk0)) { - dev_err(dev, "can't get phy_pclk0 clock.\n"); - return PTR_ERR(imxpriv->phy_pclk0); - } - imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1"); - if (IS_ERR(imxpriv->phy_pclk1)) { - dev_err(dev, "can't get phy_pclk1 clock.\n"); - return PTR_ERR(imxpriv->phy_pclk1); - } - imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk"); - if (IS_ERR(imxpriv->phy_apbclk)) { - dev_err(dev, "can't get phy_apbclk clock.\n"); - return PTR_ERR(imxpriv->phy_apbclk); - } - - /* Fetch GPIO, then enable the external OSC */ - imxpriv->clkreq_gpiod = devm_gpiod_get_optional(dev, "clkreq", - GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE); - if (IS_ERR(imxpriv->clkreq_gpiod)) - return PTR_ERR(imxpriv->clkreq_gpiod); - if (imxpriv->clkreq_gpiod) - gpiod_set_consumer_name(imxpriv->clkreq_gpiod, "SATA CLKREQ"); - return 0; } @@ -1081,12 +951,6 @@ return PTR_ERR(imxpriv->sata_ref_clk); } - imxpriv->ahb_clk = devm_clk_get(dev, "ahb"); - if (IS_ERR(imxpriv->ahb_clk)) { - dev_err(dev, "can't get ahb clock.\n"); - return PTR_ERR(imxpriv->ahb_clk); - } - if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { u32 reg_value; @@ -1107,7 +971,7 @@ IMX6Q_GPR13_SATA_SPD_MODE_3P0G | reg_value; } else if (imxpriv->type == AHCI_IMX8QM) { - ret = imx8_sata_probe(dev, imxpriv); + ret = imx8_sata_probe(dev, imxpriv); if (ret) return ret; } @@ -1163,20 +1027,48 @@ writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL); } - reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; - writel(reg_val, hpriv->mmio + IMX_TIMER1MS); + imxpriv->ahb_clk = devm_clk_get(dev, "ahb"); + if (IS_ERR(imxpriv->ahb_clk)) { + dev_info(dev, "no ahb clock.\n"); + } else { + /* + * AHB clock is only used to configure the vendor specified + * TIMER1MS register. Set it if the AHB clock is defined. + */ + reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; + writel(reg_val, hpriv->mmio + IMX_TIMER1MS); + } + + /* + * Due to IP bug on the Synopsis 3.00 SATA version, + * which is present on mx6q, and not on mx53, + * we should use sg_tablesize = 1 for reliable operation + */ + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { + dma_addr_t dma; + + ahci_platform_sht.sg_tablesize = 1; + + sg_io_buffer_hack = dma_alloc_coherent(dev, 0x10000, + &dma, GFP_KERNEL); + if (!sg_io_buffer_hack) { + ret = -ENOMEM; + goto disable_sata; + } + } ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, &ahci_platform_sht); if (ret) goto disable_sata; - return 0; + return ret; disable_sata: imx_sata_disable(hpriv); disable_clk: clk_disable_unprepare(imxpriv->sata_clk); + return ret; } @@ -1233,6 +1125,5 @@ module_platform_driver(imx_ahci_driver); MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver"); -MODULE_AUTHOR("Richard Zhu "); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:" DRV_NAME); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/ata/ahci_qoriq.c linux-imx-phytec/drivers/ata/ahci_qoriq.c --- linux-6.1.55/drivers/ata/ahci_qoriq.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/ata/ahci_qoriq.c 2024-06-19 12:33:59.408211513 +0200 @@ -48,6 +48,27 @@ #define ECC_DIS_ARMV8_CH2 0x80000000 #define ECC_DIS_LS1088A 0x40000000 +/* errata for lx2160 */ +#define RCWSR29_BASE 0x1E00170 +#define SERDES2_BASE 0x1EB0000 +#define DEVICE_CONFIG_REG_BASE 0x1E00000 +#define SERDES2_LNAX_RX_CR(x) (0x840 + (0x100 * (x))) +#define SERDES2_LNAX_RX_CBR(x) (0x8C0 + (0x100 * (x))) +#define SYS_VER_REG 0xA4 +#define LN_RX_RST 0x80000010 +#define LN_RX_RST_DONE 0x3 +#define LN_RX_MASK 0xf +#define LX2160A_VER1 0x1 + +#define SERDES2_LNAA 0 +#define SERDES2_LNAB 1 +#define SERDES2_LNAC 2 +#define SERDES2_LNAD 3 +#define SERDES2_LNAE 4 +#define SERDES2_LNAF 5 +#define SERDES2_LNAG 6 +#define SERDES2_LNAH 7 + enum ahci_qoriq_type { AHCI_LS1021A, AHCI_LS1028A, @@ -87,6 +108,126 @@ }; MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match); +static void fsl_sata_errata_379364(bool select) +{ + int val = 0; + void __iomem *rcw_base = NULL; + void __iomem *serdes_base = NULL; + void __iomem *dev_con_base = NULL; + + if (select) { + dev_con_base = ioremap(DEVICE_CONFIG_REG_BASE, PAGE_SIZE); + if (!dev_con_base) + return; + + val = (readl(dev_con_base + SYS_VER_REG) & GENMASK(7, 4)) >> 4; + if (val != LX2160A_VER1) + goto dev_unmap; + + /* + * Add few msec delay. + * Check for corresponding serdes lane RST_DONE . + * apply lane reset. + */ + + serdes_base = ioremap(SERDES2_BASE, PAGE_SIZE); + if (!serdes_base) + goto dev_unmap; + + rcw_base = ioremap(RCWSR29_BASE, PAGE_SIZE); + if (!rcw_base) + goto serdes_unmap; + + msleep(20); + + val = (readl(rcw_base) & GENMASK(25, 21)) >> 21; + + switch (val) { + case 1: + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAC)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAC)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAD)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAD)); + break; + + case 4: + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAG)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAG)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAH)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAH)); + break; + + case 5: + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAE)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAE)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAF)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAF)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAG)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAG)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAH)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAH)); + break; + + case 8: + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAC)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAC)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAD)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAD)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAE)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAE)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAF)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAF)); + break; + + case 12: + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAG)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAG)); + if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAH)) & + LN_RX_MASK) != LN_RX_RST_DONE) + writel(LN_RX_RST, serdes_base + + SERDES2_LNAX_RX_CR(SERDES2_LNAH)); + break; + + default: + break; + } + } else { + return; + } + + iounmap(rcw_base); +serdes_unmap: + iounmap(serdes_base); +dev_unmap: + iounmap(dev_con_base); +} + static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline) { @@ -102,6 +243,7 @@ bool online; int rc; bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A); + bool lx2160a_workaround = (qoriq_priv->type == AHCI_LX2160A); hpriv->stop_engine(ap); @@ -126,6 +268,8 @@ tf.status = ATA_BUSY; ata_tf_to_fis(&tf, 0, 0, d2h_fis); + fsl_sata_errata_379364(lx2160a_workaround); + rc = sata_link_hardreset(link, timing, deadline, &online, ahci_check_ready); @@ -285,9 +429,7 @@ qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data; if (unlikely(!ecc_initialized)) { - res = platform_get_resource_byname(pdev, - IORESOURCE_MEM, - "sata-ecc"); + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (res) { qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/ata/Kconfig linux-imx-phytec/drivers/ata/Kconfig --- linux-6.1.55/drivers/ata/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/ata/Kconfig 2024-06-19 12:33:59.408211513 +0200 @@ -206,6 +206,18 @@ If unsure, say N. +if AHCI_IMX + +config AHCI_IMX_PMP + bool "SATA Port Multiplier support on I.MX" + depends on SATA_PMP + default N + help + This option enables support for the PMP on Freescale i.MX SoC's. + + If unsure, say N. +endif # AHCI_IMX + config AHCI_CEVA tristate "CEVA AHCI SATA support" depends on OF diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/ata/libahci.c linux-imx-phytec/drivers/ata/libahci.c --- linux-6.1.55/drivers/ata/libahci.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/ata/libahci.c 2024-06-19 12:33:59.412211581 +0200 @@ -1520,6 +1520,14 @@ if (fbs_disabled) ahci_enable_fbs(ap); +#ifdef CONFIG_AHCI_IMX_PMP + if (ap->flags & (1 << 31)) { + if (ap->flags & (1 << 29)) + ap->flags |= (1 << 30); + ata_msleep(ap, 40); + } +#endif + return 0; fail: @@ -1872,6 +1880,11 @@ if (unlikely(resetting)) status &= ~PORT_IRQ_BAD_PMP; +#ifdef CONFIG_AHCI_IMX_PMP + status &= ~PORT_IRQ_BAD_PMP; + status &= ~PORT_IRQ_IF_ERR; +#endif + if (sata_lpm_ignore_phy_events(&ap->link)) { status &= ~PORT_IRQ_PHYRDY; ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); @@ -1947,6 +1960,12 @@ void __iomem *port_mmio = ahci_port_base(ap); u32 status; +#ifdef CONFIG_AHCI_IMX_PMP + status = readl(port_mmio + PORT_SCR_NTF); + if (status) + ap->flags |= (1 << 31); +#endif + status = readl(port_mmio + PORT_IRQ_STAT); writel(status, port_mmio + PORT_IRQ_STAT); @@ -2068,10 +2087,22 @@ { struct ahci_port_priv *pp = qc->ap->private_data; u8 *rx_fis = pp->rx_fis; +#ifdef CONFIG_AHCI_IMX_PMP + u8 *fis; +#endif if (pp->fbs_enabled) rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; +#ifdef CONFIG_AHCI_IMX_PMP + if (qc->ap->flags & (1 << 31)) { + if (!(qc->ap->flags & (1 << 30))) { + fis = pp->rx_fis + RX_FIS_D2H_REG; + memcpy(rx_fis + RX_FIS_D2H_REG, fis, 0x14); + } + } +#endif + /* * After a successful execution of an ATA PIO data-in command, * the device doesn't send D2H Reg FIS to update the TF and diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/ata/libata-eh.c linux-imx-phytec/drivers/ata/libata-eh.c --- linux-6.1.55/drivers/ata/libata-eh.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/ata/libata-eh.c 2024-06-19 12:33:59.412211581 +0200 @@ -548,6 +548,10 @@ /* finish or retry handled scmd's and clean up */ WARN_ON(!list_empty(&eh_work_q)); +#ifdef CONFIG_AHCI_IMX_PMP + ap->flags &= ~(0x7 << 29); +#endif + } /** @@ -1924,6 +1928,10 @@ if (ehc->i.flags & ATA_EHI_NO_AUTOPSY) return; +#ifdef CONFIG_AHCI_IMX_PMP + ata_msleep(ap, 20); +#endif + /* obtain and analyze SError */ rc = sata_scr_read(link, SCR_ERROR, &serror); if (rc == 0) { @@ -3567,6 +3575,11 @@ int rc, nr_fails; unsigned long flags, deadline; +#ifdef CONFIG_AHCI_IMX_PMP + if (ap->flags & (1 << 31)) + ap->flags |= (1 << 29); +#endif + /* prep for recovery */ ata_for_each_link(link, ap, EDGE) { struct ata_eh_context *ehc = &link->eh_context; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/ata/libata-pmp.c linux-imx-phytec/drivers/ata/libata-pmp.c --- linux-6.1.55/drivers/ata/libata-pmp.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/ata/libata-pmp.c 2024-06-19 12:33:59.412211581 +0200 @@ -12,6 +12,7 @@ #include #include "libata.h" #include "libata-transport.h" +#include "ahci.h" const struct ata_port_operations sata_pmp_port_ops = { .inherits = &sata_port_ops, @@ -253,8 +254,40 @@ return ""; } -#define PMP_GSCR_SII_POL 129 +#ifdef CONFIG_AHCI_IMX_PMP +struct hotplug_priv { + struct ata_port *ap; + void __iomem *port_mmio; + struct mutex mutex; + bool poll_thread_created; +}; +static struct hotplug_priv hpriv; + +static int poll_thread(void *t) +{ + u32 rc; + + for (;;) { + struct ata_port *ap = hpriv.ap; + rc = ata_wait_register(ap, hpriv.port_mmio + PORT_SCR_NTF, + 0x8000, 0, 1, 2); + + if (rc == 0) + continue; + + ata_port_info(ap, "i.MX8QM PMP SNotification detected.\n"); + mutex_lock(&(hpriv.mutex)); + hpriv.ap->flags |= (1 << 31); + sata_async_notification(hpriv.ap); + mutex_unlock(&(hpriv.mutex)); + } + + return 0; +} +#endif + +#define PMP_GSCR_SII_POL 129 static int sata_pmp_configure(struct ata_device *dev, int print_info) { struct ata_port *ap = dev->link->ap; @@ -324,6 +357,23 @@ "hotplug won't work on fan-out ports. Use warm-plug instead.\n"); } +#ifdef CONFIG_AHCI_IMX_PMP + /* create a polling thread for hotplug */ + if (hpriv.poll_thread_created) { + mutex_lock(&(hpriv.mutex)); + hpriv.ap = ap; + hpriv.port_mmio = ahci_port_base(ap); + mutex_unlock(&(hpriv.mutex)); + } else { + mutex_init(&(hpriv.mutex)); + hpriv.ap = ap; + hpriv.port_mmio = ahci_port_base(ap); + ata_port_info(ap, "i.MX8QM PMP SNotification polling thread created.\n"); + kernel_thread(poll_thread, NULL, CLONE_SIGHAND | SIGCHLD); + hpriv.poll_thread_created = true; + } +#endif + return 0; fail: @@ -1094,6 +1144,10 @@ */ void sata_pmp_error_handler(struct ata_port *ap) { +#ifdef CONFIG_AHCI_IMX_PMP + if (system_state >= SYSTEM_RUNNING) + ap->flags |= (1 << 31); +#endif ata_eh_autopsy(ap); ata_eh_report(ap); sata_pmp_eh_recover(ap); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/ata/libata-sata.c linux-imx-phytec/drivers/ata/libata-sata.c --- linux-6.1.55/drivers/ata/libata-sata.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/ata/libata-sata.c 2024-06-19 12:33:59.412211581 +0200 @@ -1346,6 +1346,9 @@ * downstream ports has changed, schedule EH. */ if (sntf & (1 << SATA_PMP_CTRL_PORT)) { +#ifdef CONFIG_AHCI_IMX_PMP + ap->flags |= (1 << 31); +#endif ata_port_schedule_eh(ap); return 1; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/ata/libata-scsi.c linux-imx-phytec/drivers/ata/libata-scsi.c --- linux-6.1.55/drivers/ata/libata-scsi.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/ata/libata-scsi.c 2024-06-19 12:33:59.416211649 +0200 @@ -4516,6 +4516,9 @@ ata_scsi_scan_host(ap, 0); mutex_unlock(&ap->scsi_scan_mutex); +#ifdef CONFIG_AHCI_IMX_PMP + ap->flags &= ~(0x7 << 29); +#endif } /** diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/base/dd.c linux-imx-phytec/drivers/base/dd.c --- linux-6.1.55/drivers/base/dd.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/base/dd.c 2024-06-19 12:33:59.444212129 +0200 @@ -111,14 +111,6 @@ */ mutex_unlock(&deferred_probe_mutex); - /* - * Force the device to the end of the dpm_list since - * the PM code assumes that the order we add things to - * the list is a good order for suspend but deferred - * probe makes that very unsafe. - */ - device_pm_move_to_tail(dev); - dev_dbg(dev, "Retrying from deferred list\n"); bus_probe_device(dev); mutex_lock(&deferred_probe_mutex); @@ -407,6 +399,14 @@ device_pm_check_callbacks(dev); /* + * Force the device to the end of the dpm_list since + * the PM code assumes that the order we add things to + * the list is a good order for suspend but deferred + * probe makes that very unsafe. + */ + device_pm_move_to_tail(dev); + + /* * Make sure the device is no longer in one of the deferred lists and * kick off retrying all pending devices */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/base/power/domain.c linux-imx-phytec/drivers/base/power/domain.c --- linux-6.1.55/drivers/base/power/domain.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/base/power/domain.c 2024-06-19 12:33:59.448212197 +0200 @@ -254,6 +254,40 @@ static inline void genpd_update_accounting(struct generic_pm_domain *genpd) {} #endif +void pm_genpd_disable_clks(struct generic_pm_domain *genpd) +{ + if (genpd->flags & GENPD_FLAG_PM_PD_CLK && genpd->num_clks > 0) + clk_bulk_disable_unprepare(genpd->num_clks, genpd->clks); +} + +int pm_genpd_enable_clks(struct generic_pm_domain *genpd) +{ + int ret; + + if (genpd->flags & GENPD_FLAG_PM_PD_CLK && genpd->num_clks > 0) { + ret = clk_bulk_prepare_enable(genpd->num_clks, genpd->clks); + if (ret) { + dev_err(&genpd->dev, "failed to enable clocks\n"); + return ret; + } + } + + return 0; +} + +int pm_genpd_of_add_clks(struct generic_pm_domain *genpd, struct device *dev) +{ + if (genpd->flags & GENPD_FLAG_PM_PD_CLK) { + genpd->num_clks = devm_clk_bulk_get_all(dev, &genpd->clks); + if (genpd->num_clks < 0) + return dev_err_probe(&genpd->dev, genpd->num_clks, + "Failed to get domain's clocks\n"); + } + + return 0; +} +EXPORT_SYMBOL_GPL(pm_genpd_of_add_clks); + static int _genpd_reeval_performance_state(struct generic_pm_domain *genpd, unsigned int state) { @@ -559,6 +593,9 @@ if (!genpd->power_off) goto out; + if (atomic_read(&genpd->sd_count) > 0) + return -EBUSY; + timed = timed && genpd->gd && !genpd->states[state_idx].fwnode; if (!timed) { ret = genpd->power_off(genpd); @@ -629,7 +666,7 @@ * (2) System suspend is in progress. */ if (!genpd_status_on(genpd) || genpd->prepared_count > 0) - return 0; + return -EAGAIN; /* * Abort power off for the PM domain in the following situations: @@ -675,9 +712,9 @@ if (!genpd->gov) genpd->state_idx = 0; - /* Don't power off, if a child domain is waiting to power on. */ - if (atomic_read(&genpd->sd_count) > 0) - return -EBUSY; + /* Choose the deepest state if no devices using this domain */ + if (!genpd->device_count) + genpd->state_idx = genpd->state_count - 1; ret = _genpd_power_off(genpd, true); if (ret) { @@ -692,8 +729,10 @@ list_for_each_entry(link, &genpd->child_links, child_node) { genpd_sd_counter_dec(link->parent); genpd_lock_nested(link->parent, depth + 1); - genpd_power_off(link->parent, false, depth + 1); + ret = genpd_power_off(link->parent, false, depth + 1); genpd_unlock(link->parent); + if (!ret) + pm_genpd_disable_clks(link->parent); } return 0; @@ -703,17 +742,20 @@ * genpd_power_on - Restore power to a given PM domain and its parents. * @genpd: PM domain to power up. * @depth: nesting count for lockdep. + * @pd_was_on: Return parameter that indicates whether PD was on before * * Restore power to @genpd and all of its parents so that it is possible to * resume a device belonging to it. */ -static int genpd_power_on(struct generic_pm_domain *genpd, unsigned int depth) +static int genpd_power_on(struct generic_pm_domain *genpd, unsigned int depth, bool *pd_was_on) { struct gpd_link *link; int ret = 0; - if (genpd_status_on(genpd)) + if (genpd_status_on(genpd)) { + *pd_was_on = true; return 0; + } /* * The list is guaranteed not to change while the loop below is being @@ -722,16 +764,24 @@ */ list_for_each_entry(link, &genpd->child_links, child_node) { struct generic_pm_domain *parent = link->parent; + bool pd_state = false; genpd_sd_counter_inc(parent); + ret = pm_genpd_enable_clks(parent); + if (ret) + return ret; + genpd_lock_nested(parent, depth + 1); - ret = genpd_power_on(parent, depth + 1); + ret = genpd_power_on(parent, depth + 1, &pd_state); genpd_unlock(parent); if (ret) { genpd_sd_counter_dec(parent); + pm_genpd_disable_clks(parent); goto err; + } else if (pd_state) { + pm_genpd_disable_clks(parent); } } @@ -750,8 +800,10 @@ child_node) { genpd_sd_counter_dec(link->parent); genpd_lock_nested(link->parent, depth + 1); - genpd_power_off(link->parent, false, depth + 1); + ret = genpd_power_off(link->parent, false, depth + 1); genpd_unlock(link->parent); + if (!ret) + pm_genpd_disable_clks(link->parent); } return ret; @@ -813,12 +865,16 @@ static void genpd_power_off_work_fn(struct work_struct *work) { struct generic_pm_domain *genpd; + int ret; genpd = container_of(work, struct generic_pm_domain, power_off_work); genpd_lock(genpd); - genpd_power_off(genpd, false, 0); + ret = genpd_power_off(genpd, false, 0); genpd_unlock(genpd); + + if (!ret) + pm_genpd_disable_clks(genpd); } /** @@ -937,9 +993,12 @@ genpd_lock(genpd); gpd_data->rpm_pstate = genpd_drop_performance_state(dev); - genpd_power_off(genpd, true, 0); + ret = genpd_power_off(genpd, true, 0); genpd_unlock(genpd); + if (!ret) + pm_genpd_disable_clks(genpd); + return 0; } @@ -957,6 +1016,7 @@ struct generic_pm_domain_data *gpd_data = dev_gpd_data(dev); struct gpd_timing_data *td = gpd_data->td; bool timed = td && pm_runtime_enabled(dev); + bool pd_was_on = false; ktime_t time_start = 0; s64 elapsed_ns; int ret; @@ -974,14 +1034,22 @@ if (irq_safe_dev_in_sleep_domain(dev, genpd)) goto out; + ret = pm_genpd_enable_clks(genpd); + if (ret) + return ret; + genpd_lock(genpd); - ret = genpd_power_on(genpd, 0); + ret = genpd_power_on(genpd, 0, &pd_was_on); if (!ret) genpd_restore_performance_state(dev, gpd_data->rpm_pstate); genpd_unlock(genpd); - if (ret) + if (ret) { + pm_genpd_disable_clks(genpd); return ret; + } else if (pd_was_on) { + pm_genpd_disable_clks(genpd); + } out: /* Measure resume latency. */ @@ -1020,6 +1088,8 @@ genpd_unlock(genpd); } + pm_genpd_disable_clks(genpd); + return ret; } @@ -1070,15 +1140,24 @@ * these cases the lock must be held. */ static void genpd_sync_power_off(struct generic_pm_domain *genpd, bool use_lock, - unsigned int depth) + unsigned int depth, bool *need_disable_clk) { struct gpd_link *link; - if (!genpd_status_on(genpd) || genpd_is_always_on(genpd)) + /* + * Give the power domain a chance to switch to the deepest state in + * case it's already off but in an intermediate low power state. + */ + genpd->state_idx_saved = genpd->state_idx; + + if (genpd_is_always_on(genpd)) return; - if (genpd->suspended_count != genpd->device_count - || atomic_read(&genpd->sd_count) > 0) + if (!genpd_status_on(genpd) && + genpd->state_idx == (genpd->state_count - 1)) + return; + + if (genpd->suspended_count != genpd->device_count) return; /* Check that the children are in their deepest (powered-off) state. */ @@ -1093,18 +1172,26 @@ if (_genpd_power_off(genpd, false)) return; + if (genpd->status == GENPD_STATE_OFF) + return; + genpd->status = GENPD_STATE_OFF; + *need_disable_clk = true; list_for_each_entry(link, &genpd->child_links, child_node) { + bool disable_clk = false; genpd_sd_counter_dec(link->parent); if (use_lock) genpd_lock_nested(link->parent, depth + 1); - genpd_sync_power_off(link->parent, use_lock, depth + 1); + genpd_sync_power_off(link->parent, use_lock, depth + 1, &disable_clk); if (use_lock) genpd_unlock(link->parent); + + if (disable_clk) + pm_genpd_disable_clks(link->parent); } } @@ -1119,26 +1206,38 @@ * these cases the lock must be held. */ static void genpd_sync_power_on(struct generic_pm_domain *genpd, bool use_lock, - unsigned int depth) + unsigned int depth, bool *pd_was_on) { struct gpd_link *link; - if (genpd_status_on(genpd)) + if (genpd_status_on(genpd)) { + *pd_was_on = true; return; + } list_for_each_entry(link, &genpd->child_links, child_node) { + bool pd_state = false; + genpd_sd_counter_inc(link->parent); + pm_genpd_enable_clks(link->parent); + if (use_lock) genpd_lock_nested(link->parent, depth + 1); - genpd_sync_power_on(link->parent, use_lock, depth + 1); + genpd_sync_power_on(link->parent, use_lock, depth + 1, &pd_state); if (use_lock) genpd_unlock(link->parent); + + if (pd_state) + pm_genpd_disable_clks(link->parent); } _genpd_power_on(genpd, false); + /* restore save power domain state after resume */ + genpd->state_idx = genpd->state_idx_saved; + genpd->status = GENPD_STATE_ON; } @@ -1194,6 +1293,7 @@ static int genpd_finish_suspend(struct device *dev, bool poweroff) { struct generic_pm_domain *genpd; + bool need_disable_clk = false; int ret = 0; genpd = dev_to_genpd(dev); @@ -1224,9 +1324,12 @@ genpd_lock(genpd); genpd->suspended_count++; - genpd_sync_power_off(genpd, true, 0); + genpd_sync_power_off(genpd, true, 0, &need_disable_clk); genpd_unlock(genpd); + if (need_disable_clk) + pm_genpd_disable_clks(genpd); + return 0; } @@ -1253,6 +1356,7 @@ static int genpd_resume_noirq(struct device *dev) { struct generic_pm_domain *genpd; + bool pd_was_on = false; int ret; dev_dbg(dev, "%s()\n", __func__); @@ -1264,11 +1368,18 @@ if (device_wakeup_path(dev) && genpd_is_active_wakeup(genpd)) return pm_generic_resume_noirq(dev); + ret = pm_genpd_enable_clks(genpd); + if (ret) + return ret; + genpd_lock(genpd); - genpd_sync_power_on(genpd, true, 0); + genpd_sync_power_on(genpd, true, 0, &pd_was_on); genpd->suspended_count--; genpd_unlock(genpd); + if (pd_was_on) + pm_genpd_disable_clks(genpd); + if (genpd->dev_ops.stop && genpd->dev_ops.start && !pm_runtime_status_suspended(dev)) { ret = genpd_start_dev(genpd, dev); @@ -1363,6 +1474,7 @@ static int genpd_restore_noirq(struct device *dev) { struct generic_pm_domain *genpd; + bool pd_was_on = false; int ret = 0; dev_dbg(dev, "%s()\n", __func__); @@ -1371,6 +1483,10 @@ if (IS_ERR(genpd)) return -EINVAL; + ret = pm_genpd_enable_clks(genpd); + if (ret) + return ret; + /* * At this point suspended_count == 0 means we are being run for the * first time for the given domain in the present cycle. @@ -1385,9 +1501,12 @@ genpd->status = GENPD_STATE_OFF; } - genpd_sync_power_on(genpd, true, 0); + genpd_sync_power_on(genpd, true, 0, &pd_was_on); genpd_unlock(genpd); + if (pd_was_on) + pm_genpd_disable_clks(genpd); + if (genpd->dev_ops.stop && genpd->dev_ops.start && !pm_runtime_status_suspended(dev)) { ret = genpd_start_dev(genpd, dev); @@ -1431,12 +1550,16 @@ static void genpd_switch_state(struct device *dev, bool suspend) { struct generic_pm_domain *genpd; + bool need_disable_clk = false; bool use_lock; genpd = dev_to_genpd_safe(dev); if (!genpd) return; + if (!suspend) + pm_genpd_enable_clks(genpd); + use_lock = genpd_is_irq_safe(genpd); if (use_lock) @@ -1444,14 +1567,17 @@ if (suspend) { genpd->suspended_count++; - genpd_sync_power_off(genpd, use_lock, 0); + genpd_sync_power_off(genpd, use_lock, 0, &need_disable_clk); } else { - genpd_sync_power_on(genpd, use_lock, 0); + genpd_sync_power_on(genpd, use_lock, 0, &need_disable_clk); genpd->suspended_count--; } if (use_lock) genpd_unlock(genpd); + + if (need_disable_clk) + pm_genpd_disable_clks(genpd); } /** @@ -2058,6 +2184,8 @@ genpd->device_count = 0; genpd->provider = NULL; genpd->has_provider = false; + genpd->clks = NULL; + genpd->num_clks = 0; genpd->accounting_time = ktime_get_mono_fast_ns(); genpd->domain.ops.runtime_suspend = genpd_runtime_suspend; genpd->domain.ops.runtime_resume = genpd_runtime_resume; @@ -2089,7 +2217,7 @@ /* Multiple states but no governor doesn't make sense. */ if (!gov && genpd->state_count > 1) - pr_warn("%s: no governor for states\n", genpd->name); + pr_debug("%s: no governor for states\n", genpd->name); ret = genpd_alloc_data(genpd); if (ret) @@ -2720,6 +2848,7 @@ { struct of_phandle_args pd_args; struct generic_pm_domain *pd; + bool pd_was_on = false; int pstate; int ret; @@ -2749,15 +2878,22 @@ dev->pm_domain->detach = genpd_dev_pm_detach; dev->pm_domain->sync = genpd_dev_pm_sync; + ret = pm_genpd_enable_clks(pd); + if (ret) + return ret; + if (power_on) { genpd_lock(pd); - ret = genpd_power_on(pd, 0); + ret = genpd_power_on(pd, 0, &pd_was_on); genpd_unlock(pd); } if (ret) { + pm_genpd_disable_clks(pd); genpd_remove_device(pd, dev); return -EPROBE_DEFER; + } else if (pd_was_on) { + pm_genpd_disable_clks(pd); } /* Set the default performance state */ @@ -2776,6 +2912,7 @@ err: dev_err(dev, "failed to set required performance state for power-domain %s: %d\n", pd->name, ret); + pm_genpd_disable_clks(pd); genpd_remove_device(pd, dev); return ret; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/base/regmap/regmap.c linux-imx-phytec/drivers/base/regmap/regmap.c --- linux-6.1.55/drivers/base/regmap/regmap.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/base/regmap/regmap.c 2024-06-19 12:33:59.452212265 +0200 @@ -801,6 +801,9 @@ map->lock_arg = map; } + if (config->disable_debugfs && !config->disable_locking) + regmap_debugfs_disable(map); + /* * When we write in fast-paths with regmap_bulk_write() don't allocate * scratch buffers with sleeping allocations. @@ -1236,8 +1239,6 @@ ret = regmap_attach_dev(dev, map, config); if (ret != 0) goto err_regcache; - } else { - regmap_debugfs_init(map); } return map; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/base/regmap/regmap-debugfs.c linux-imx-phytec/drivers/base/regmap/regmap-debugfs.c --- linux-6.1.55/drivers/base/regmap/regmap-debugfs.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/base/regmap/regmap-debugfs.c 2024-06-19 12:33:59.452212265 +0200 @@ -556,9 +556,10 @@ * a mutex or a spinlock, but if the regmap owner decided to disable * all locking mechanisms, this is no longer the case. For safety: * don't create the debugfs entries if locking is disabled. + * Or disabled explicitly in driver. */ if (map->debugfs_disable) { - dev_dbg(map->dev, "regmap locking disabled - not creating debugfs entries\n"); + dev_dbg(map->dev, "regmap debugfs disabled - not creating debugfs entries\n"); return; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/bluetooth/btnxpuart.c linux-imx-phytec/drivers/bluetooth/btnxpuart.c --- linux-6.1.55/drivers/bluetooth/btnxpuart.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/bluetooth/btnxpuart.c 2024-06-19 12:33:59.484212812 +0200 @@ -0,0 +1,1413 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * NXP Bluetooth driver + * Copyright 2023 NXP + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "h4_recv.h" + +#define MANUFACTURER_NXP 37 + +#define BTNXPUART_TX_STATE_ACTIVE 1 +#define BTNXPUART_FW_DOWNLOADING 2 +#define BTNXPUART_CHECK_BOOT_SIGNATURE 3 +#define BTNXPUART_SERDEV_OPEN 4 +#define BTNXPUART_IR_IN_PROGRESS 5 + +/* NXP HW err codes */ +#define BTNXPUART_IR_HW_ERR 0xb0 + +#define FIRMWARE_W8987 "nxp/uartuart8987_bt.bin" +#define FIRMWARE_W8997 "nxp/uartuart8997_bt_v4.bin" +#define FIRMWARE_W9098 "nxp/uartuart9098_bt_v1.bin" +#define FIRMWARE_IW416 "nxp/uartiw416_bt_v0.bin" +#define FIRMWARE_IW612 "nxp/uartspi_n61x_v1.bin.se" +#define FIRMWARE_IW624 "nxp/uartiw624_bt.bin" +#define FIRMWARE_SECURE_IW624 "nxp/uartiw624_bt.bin.se" +#define FIRMWARE_AW693 "nxp/uartaw693_bt.bin" +#define FIRMWARE_SECURE_AW693 "nxp/uartaw693_bt.bin.se" +#define FIRMWARE_HELPER "nxp/helper_uart_3000000.bin" + +#define CHIP_ID_W9098 0x5c03 +#define CHIP_ID_IW416 0x7201 +#define CHIP_ID_IW612 0x7601 +#define CHIP_ID_IW624a 0x8000 +#define CHIP_ID_IW624c 0x8001 +#define CHIP_ID_AW693 0x8200 + +#define FW_SECURE_MASK 0xc0 +#define FW_OPEN 0x00 +#define FW_AUTH_ILLEGAL 0x40 +#define FW_AUTH_PLAIN 0x80 +#define FW_AUTH_ENC 0xc0 + +#define HCI_NXP_PRI_BAUDRATE 115200 +#define HCI_NXP_SEC_BAUDRATE 3000000 + +#define MAX_FW_FILE_NAME_LEN 50 + +/* Default ps timeout period in milliseconds */ +#define PS_DEFAULT_TIMEOUT_PERIOD_MS 2000 + +/* wakeup methods */ +#define WAKEUP_METHOD_DTR 0 +#define WAKEUP_METHOD_BREAK 1 +#define WAKEUP_METHOD_EXT_BREAK 2 +#define WAKEUP_METHOD_RTS 3 +#define WAKEUP_METHOD_INVALID 0xff + +/* power save mode status */ +#define PS_MODE_DISABLE 0 +#define PS_MODE_ENABLE 1 + +/* Power Save Commands to ps_work_func */ +#define PS_CMD_EXIT_PS 1 +#define PS_CMD_ENTER_PS 2 + +/* power save state */ +#define PS_STATE_AWAKE 0 +#define PS_STATE_SLEEP 1 + +/* Bluetooth vendor command : Sleep mode */ +#define HCI_NXP_AUTO_SLEEP_MODE 0xfc23 +/* Bluetooth vendor command : Wakeup method */ +#define HCI_NXP_WAKEUP_METHOD 0xfc53 +/* Bluetooth vendor command : Set operational baudrate */ +#define HCI_NXP_SET_OPER_SPEED 0xfc09 +/* Bluetooth vendor command: Independent Reset */ +#define HCI_NXP_IND_RESET 0xfcfc + +/* Bluetooth Power State : Vendor cmd params */ +#define BT_PS_ENABLE 0x02 +#define BT_PS_DISABLE 0x03 + +/* Bluetooth Host Wakeup Methods */ +#define BT_HOST_WAKEUP_METHOD_NONE 0x00 +#define BT_HOST_WAKEUP_METHOD_DTR 0x01 +#define BT_HOST_WAKEUP_METHOD_BREAK 0x02 +#define BT_HOST_WAKEUP_METHOD_GPIO 0x03 + +/* Bluetooth Chip Wakeup Methods */ +#define BT_CTRL_WAKEUP_METHOD_DSR 0x00 +#define BT_CTRL_WAKEUP_METHOD_BREAK 0x01 +#define BT_CTRL_WAKEUP_METHOD_GPIO 0x02 +#define BT_CTRL_WAKEUP_METHOD_EXT_BREAK 0x04 +#define BT_CTRL_WAKEUP_METHOD_RTS 0x05 + +struct ps_data { + u8 target_ps_mode; /* ps mode to be set */ + u8 cur_psmode; /* current ps_mode */ + u8 ps_state; /* controller's power save state */ + u8 ps_cmd; + u8 h2c_wakeupmode; + u8 cur_h2c_wakeupmode; + u8 c2h_wakeupmode; + u8 c2h_wakeup_gpio; + u8 h2c_wakeup_gpio; + bool driver_sent_cmd; + u16 h2c_ps_interval; + u16 c2h_ps_interval; + struct hci_dev *hdev; + struct work_struct work; + struct timer_list ps_timer; +}; + +struct wakeup_cmd_payload { + u8 c2h_wakeupmode; + u8 c2h_wakeup_gpio; + u8 h2c_wakeupmode; + u8 h2c_wakeup_gpio; +} __packed; + +struct psmode_cmd_payload { + u8 ps_cmd; + __le16 c2h_ps_interval; +} __packed; + +struct btnxpuart_data { + const char *helper_fw_name; + const char *fw_name; +}; + +struct btnxpuart_dev { + struct hci_dev *hdev; + struct serdev_device *serdev; + + struct work_struct tx_work; + unsigned long tx_state; + struct sk_buff_head txq; + struct sk_buff *rx_skb; + + const struct firmware *fw; + u8 fw_name[MAX_FW_FILE_NAME_LEN]; + u32 fw_dnld_v1_offset; + u32 fw_v1_sent_bytes; + u32 fw_v3_offset_correction; + u32 fw_v1_expected_len; + u32 boot_reg_offset; + wait_queue_head_t fw_dnld_done_wait_q; + wait_queue_head_t check_boot_sign_wait_q; + + u32 new_baudrate; + u32 current_baudrate; + u32 fw_init_baudrate; + bool timeout_changed; + bool baudrate_changed; + bool helper_downloaded; + + struct ps_data psdata; + struct btnxpuart_data *nxp_data; +}; + +#define NXP_V1_FW_REQ_PKT 0xa5 +#define NXP_V1_CHIP_VER_PKT 0xaa +#define NXP_V3_FW_REQ_PKT 0xa7 +#define NXP_V3_CHIP_VER_PKT 0xab + +#define NXP_ACK_V1 0x5a +#define NXP_NAK_V1 0xbf +#define NXP_ACK_V3 0x7a +#define NXP_NAK_V3 0x7b +#define NXP_CRC_ERROR_V3 0x7c + +#define HDR_LEN 16 + +#define NXP_RECV_CHIP_VER_V1 \ + .type = NXP_V1_CHIP_VER_PKT, \ + .hlen = 4, \ + .loff = 0, \ + .lsize = 0, \ + .maxlen = 4 + +#define NXP_RECV_FW_REQ_V1 \ + .type = NXP_V1_FW_REQ_PKT, \ + .hlen = 4, \ + .loff = 0, \ + .lsize = 0, \ + .maxlen = 4 + +#define NXP_RECV_CHIP_VER_V3 \ + .type = NXP_V3_CHIP_VER_PKT, \ + .hlen = 4, \ + .loff = 0, \ + .lsize = 0, \ + .maxlen = 4 + +#define NXP_RECV_FW_REQ_V3 \ + .type = NXP_V3_FW_REQ_PKT, \ + .hlen = 9, \ + .loff = 0, \ + .lsize = 0, \ + .maxlen = 9 + +struct v1_data_req { + __le16 len; + __le16 len_comp; +} __packed; + +struct v1_start_ind { + __le16 chip_id; + __le16 chip_id_comp; +} __packed; + +struct v3_data_req { + __le16 len; + __le32 offset; + __le16 error; + u8 crc; +} __packed; + +struct v3_start_ind { + __le16 chip_id; + u8 loader_ver; + u8 crc; +} __packed; + +/* UART register addresses of BT chip */ +#define CLKDIVADDR 0x7f00008f +#define UARTDIVADDR 0x7f000090 +#define UARTMCRADDR 0x7f000091 +#define UARTREINITADDR 0x7f000092 +#define UARTICRADDR 0x7f000093 +#define UARTFCRADDR 0x7f000094 + +#define MCR 0x00000022 +#define INIT 0x00000001 +#define ICR 0x000000c7 +#define FCR 0x000000c7 + +#define POLYNOMIAL8 0x07 + +struct uart_reg { + __le32 address; + __le32 value; +} __packed; + +struct uart_config { + struct uart_reg clkdiv; + struct uart_reg uartdiv; + struct uart_reg mcr; + struct uart_reg re_init; + struct uart_reg icr; + struct uart_reg fcr; + __be32 crc; +} __packed; + +struct nxp_bootloader_cmd { + __le32 header; + __le32 arg; + __le32 payload_len; + __be32 crc; +} __packed; + +static u8 crc8_table[CRC8_TABLE_SIZE]; + +/* Default configurations */ +#define DEFAULT_H2C_WAKEUP_MODE WAKEUP_METHOD_BREAK +#define DEFAULT_PS_MODE PS_MODE_DISABLE +#define FW_INIT_BAUDRATE HCI_NXP_PRI_BAUDRATE + +static struct sk_buff *nxp_drv_send_cmd(struct hci_dev *hdev, u16 opcode, + u32 plen, + void *param) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct ps_data *psdata = &nxpdev->psdata; + struct sk_buff *skb; + + /* set flag to prevent nxp_enqueue from parsing values from this command and + * calling hci_cmd_sync_queue() again. + */ + psdata->driver_sent_cmd = true; + skb = __hci_cmd_sync(hdev, opcode, plen, param, HCI_CMD_TIMEOUT); + psdata->driver_sent_cmd = false; + + return skb; +} + +static void btnxpuart_tx_wakeup(struct btnxpuart_dev *nxpdev) +{ + if (schedule_work(&nxpdev->tx_work)) + set_bit(BTNXPUART_TX_STATE_ACTIVE, &nxpdev->tx_state); +} + +/* NXP Power Save Feature */ +static void ps_start_timer(struct btnxpuart_dev *nxpdev) +{ + struct ps_data *psdata = &nxpdev->psdata; + + if (!psdata) + return; + + if (psdata->cur_psmode == PS_MODE_ENABLE) + mod_timer(&psdata->ps_timer, jiffies + msecs_to_jiffies(psdata->h2c_ps_interval)); +} + +static void ps_cancel_timer(struct btnxpuart_dev *nxpdev) +{ + struct ps_data *psdata = &nxpdev->psdata; + + flush_work(&psdata->work); + del_timer_sync(&psdata->ps_timer); +} + +static void ps_control(struct hci_dev *hdev, u8 ps_state) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct ps_data *psdata = &nxpdev->psdata; + int status; + + if (psdata->ps_state == ps_state || + !test_bit(BTNXPUART_SERDEV_OPEN, &nxpdev->tx_state)) + return; + + switch (psdata->cur_h2c_wakeupmode) { + case WAKEUP_METHOD_DTR: + if (ps_state == PS_STATE_AWAKE) + status = serdev_device_set_tiocm(nxpdev->serdev, TIOCM_DTR, 0); + else + status = serdev_device_set_tiocm(nxpdev->serdev, 0, TIOCM_DTR); + break; + case WAKEUP_METHOD_BREAK: + default: + if (ps_state == PS_STATE_AWAKE) + status = serdev_device_break_ctl(nxpdev->serdev, 0); + else + status = serdev_device_break_ctl(nxpdev->serdev, -1); + bt_dev_dbg(hdev, "Set UART break: %s, status=%d", + str_on_off(ps_state == PS_STATE_SLEEP), status); + break; + } + if (!status) + psdata->ps_state = ps_state; + if (ps_state == PS_STATE_AWAKE) + btnxpuart_tx_wakeup(nxpdev); +} + +static void ps_work_func(struct work_struct *work) +{ + struct ps_data *data = container_of(work, struct ps_data, work); + + if (data->ps_cmd == PS_CMD_ENTER_PS && data->cur_psmode == PS_MODE_ENABLE) + ps_control(data->hdev, PS_STATE_SLEEP); + else if (data->ps_cmd == PS_CMD_EXIT_PS) + ps_control(data->hdev, PS_STATE_AWAKE); +} + +static void ps_timeout_func(struct timer_list *t) +{ + struct ps_data *data = from_timer(data, t, ps_timer); + struct hci_dev *hdev = data->hdev; + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + + if (test_bit(BTNXPUART_TX_STATE_ACTIVE, &nxpdev->tx_state)) { + ps_start_timer(nxpdev); + } else { + data->ps_cmd = PS_CMD_ENTER_PS; + schedule_work(&data->work); + } +} + +static void ps_setup(struct hci_dev *hdev) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct ps_data *psdata = &nxpdev->psdata; + + psdata->hdev = hdev; + INIT_WORK(&psdata->work, ps_work_func); + timer_setup(&psdata->ps_timer, ps_timeout_func, 0); +} + +static void ps_wakeup(struct btnxpuart_dev *nxpdev) +{ + struct ps_data *psdata = &nxpdev->psdata; + + if (psdata->ps_state != PS_STATE_AWAKE) { + psdata->ps_cmd = PS_CMD_EXIT_PS; + schedule_work(&psdata->work); + } +} + +static int send_ps_cmd(struct hci_dev *hdev, void *data) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct ps_data *psdata = &nxpdev->psdata; + struct psmode_cmd_payload pcmd; + struct sk_buff *skb; + u8 *status; + + if (psdata->target_ps_mode == PS_MODE_ENABLE) + pcmd.ps_cmd = BT_PS_ENABLE; + else + pcmd.ps_cmd = BT_PS_DISABLE; + pcmd.c2h_ps_interval = __cpu_to_le16(psdata->c2h_ps_interval); + + skb = nxp_drv_send_cmd(hdev, HCI_NXP_AUTO_SLEEP_MODE, sizeof(pcmd), &pcmd); + if (IS_ERR(skb)) { + bt_dev_err(hdev, "Setting Power Save mode failed (%ld)", PTR_ERR(skb)); + return PTR_ERR(skb); + } + + status = skb_pull_data(skb, 1); + if (status) { + if (!*status) + psdata->cur_psmode = psdata->target_ps_mode; + else + psdata->target_ps_mode = psdata->cur_psmode; + if (psdata->cur_psmode == PS_MODE_ENABLE) + ps_start_timer(nxpdev); + else + ps_wakeup(nxpdev); + bt_dev_dbg(hdev, "Power Save mode response: status=%d, ps_mode=%d", + *status, psdata->cur_psmode); + } + kfree_skb(skb); + + return 0; +} + +static int send_wakeup_method_cmd(struct hci_dev *hdev, void *data) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct ps_data *psdata = &nxpdev->psdata; + struct wakeup_cmd_payload pcmd; + struct sk_buff *skb; + u8 *status; + + pcmd.c2h_wakeupmode = psdata->c2h_wakeupmode; + pcmd.c2h_wakeup_gpio = psdata->c2h_wakeup_gpio; + switch (psdata->h2c_wakeupmode) { + case WAKEUP_METHOD_DTR: + pcmd.h2c_wakeupmode = BT_CTRL_WAKEUP_METHOD_DSR; + break; + case WAKEUP_METHOD_BREAK: + default: + pcmd.h2c_wakeupmode = BT_CTRL_WAKEUP_METHOD_BREAK; + break; + } + pcmd.h2c_wakeup_gpio = 0xff; + + skb = nxp_drv_send_cmd(hdev, HCI_NXP_WAKEUP_METHOD, sizeof(pcmd), &pcmd); + if (IS_ERR(skb)) { + bt_dev_err(hdev, "Setting wake-up method failed (%ld)", PTR_ERR(skb)); + return PTR_ERR(skb); + } + + status = skb_pull_data(skb, 1); + if (status) { + if (*status == 0) + psdata->cur_h2c_wakeupmode = psdata->h2c_wakeupmode; + else + psdata->h2c_wakeupmode = psdata->cur_h2c_wakeupmode; + bt_dev_dbg(hdev, "Set Wakeup Method response: status=%d, h2c_wakeupmode=%d", + *status, psdata->cur_h2c_wakeupmode); + } + kfree_skb(skb); + + return 0; +} + +static void ps_init(struct hci_dev *hdev) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct ps_data *psdata = &nxpdev->psdata; + + serdev_device_set_tiocm(nxpdev->serdev, 0, TIOCM_RTS); + usleep_range(5000, 10000); + serdev_device_set_tiocm(nxpdev->serdev, TIOCM_RTS, 0); + usleep_range(5000, 10000); + + psdata->ps_state = PS_STATE_AWAKE; + psdata->c2h_wakeupmode = BT_HOST_WAKEUP_METHOD_NONE; + psdata->c2h_wakeup_gpio = 0xff; + + psdata->cur_h2c_wakeupmode = WAKEUP_METHOD_INVALID; + psdata->h2c_ps_interval = PS_DEFAULT_TIMEOUT_PERIOD_MS; + switch (DEFAULT_H2C_WAKEUP_MODE) { + case WAKEUP_METHOD_DTR: + psdata->h2c_wakeupmode = WAKEUP_METHOD_DTR; + serdev_device_set_tiocm(nxpdev->serdev, 0, TIOCM_DTR); + serdev_device_set_tiocm(nxpdev->serdev, TIOCM_DTR, 0); + break; + case WAKEUP_METHOD_BREAK: + default: + psdata->h2c_wakeupmode = WAKEUP_METHOD_BREAK; + serdev_device_break_ctl(nxpdev->serdev, -1); + usleep_range(5000, 10000); + serdev_device_break_ctl(nxpdev->serdev, 0); + usleep_range(5000, 10000); + break; + } + + psdata->cur_psmode = PS_MODE_DISABLE; + psdata->target_ps_mode = DEFAULT_PS_MODE; + + if (psdata->cur_h2c_wakeupmode != psdata->h2c_wakeupmode) + hci_cmd_sync_queue(hdev, send_wakeup_method_cmd, NULL, NULL); + if (psdata->cur_psmode != psdata->target_ps_mode) + hci_cmd_sync_queue(hdev, send_ps_cmd, NULL, NULL); +} + +/* NXP Firmware Download Feature */ +static int nxp_download_firmware(struct hci_dev *hdev) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + int err = 0; + + nxpdev->fw_dnld_v1_offset = 0; + nxpdev->fw_v1_sent_bytes = 0; + nxpdev->fw_v1_expected_len = HDR_LEN; + nxpdev->boot_reg_offset = 0; + nxpdev->fw_v3_offset_correction = 0; + nxpdev->baudrate_changed = false; + nxpdev->timeout_changed = false; + nxpdev->helper_downloaded = false; + + serdev_device_set_baudrate(nxpdev->serdev, HCI_NXP_PRI_BAUDRATE); + serdev_device_set_flow_control(nxpdev->serdev, false); + nxpdev->current_baudrate = HCI_NXP_PRI_BAUDRATE; + + /* Wait till FW is downloaded */ + err = wait_event_interruptible_timeout(nxpdev->fw_dnld_done_wait_q, + !test_bit(BTNXPUART_FW_DOWNLOADING, + &nxpdev->tx_state), + msecs_to_jiffies(60000)); + if (err == 0) { + bt_dev_err(hdev, "FW Download Timeout."); + return -ETIMEDOUT; + } + + serdev_device_set_flow_control(nxpdev->serdev, true); + release_firmware(nxpdev->fw); + memset(nxpdev->fw_name, 0, sizeof(nxpdev->fw_name)); + + /* Allow the downloaded FW to initialize */ + msleep(1200); + + return 0; +} + +static void nxp_send_ack(u8 ack, struct hci_dev *hdev) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + u8 ack_nak[2]; + int len = 1; + + ack_nak[0] = ack; + if (ack == NXP_ACK_V3) { + ack_nak[1] = crc8(crc8_table, ack_nak, 1, 0xff); + len = 2; + } + serdev_device_write_buf(nxpdev->serdev, ack_nak, len); +} + +static bool nxp_fw_change_baudrate(struct hci_dev *hdev, u16 req_len) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct nxp_bootloader_cmd nxp_cmd5; + struct uart_config uart_config; + u32 clkdivaddr = CLKDIVADDR - nxpdev->boot_reg_offset; + u32 uartdivaddr = UARTDIVADDR - nxpdev->boot_reg_offset; + u32 uartmcraddr = UARTMCRADDR - nxpdev->boot_reg_offset; + u32 uartreinitaddr = UARTREINITADDR - nxpdev->boot_reg_offset; + u32 uarticraddr = UARTICRADDR - nxpdev->boot_reg_offset; + u32 uartfcraddr = UARTFCRADDR - nxpdev->boot_reg_offset; + + if (req_len == sizeof(nxp_cmd5)) { + nxp_cmd5.header = __cpu_to_le32(5); + nxp_cmd5.arg = 0; + nxp_cmd5.payload_len = __cpu_to_le32(sizeof(uart_config)); + /* FW expects swapped CRC bytes */ + nxp_cmd5.crc = __cpu_to_be32(crc32_be(0UL, (char *)&nxp_cmd5, + sizeof(nxp_cmd5) - 4)); + + serdev_device_write_buf(nxpdev->serdev, (u8 *)&nxp_cmd5, sizeof(nxp_cmd5)); + nxpdev->fw_v3_offset_correction += req_len; + } else if (req_len == sizeof(uart_config)) { + uart_config.clkdiv.address = __cpu_to_le32(clkdivaddr); + uart_config.clkdiv.value = __cpu_to_le32(0x00c00000); + uart_config.uartdiv.address = __cpu_to_le32(uartdivaddr); + uart_config.uartdiv.value = __cpu_to_le32(1); + uart_config.mcr.address = __cpu_to_le32(uartmcraddr); + uart_config.mcr.value = __cpu_to_le32(MCR); + uart_config.re_init.address = __cpu_to_le32(uartreinitaddr); + uart_config.re_init.value = __cpu_to_le32(INIT); + uart_config.icr.address = __cpu_to_le32(uarticraddr); + uart_config.icr.value = __cpu_to_le32(ICR); + uart_config.fcr.address = __cpu_to_le32(uartfcraddr); + uart_config.fcr.value = __cpu_to_le32(FCR); + /* FW expects swapped CRC bytes */ + uart_config.crc = __cpu_to_be32(crc32_be(0UL, (char *)&uart_config, + sizeof(uart_config) - 4)); + + serdev_device_write_buf(nxpdev->serdev, (u8 *)&uart_config, sizeof(uart_config)); + serdev_device_wait_until_sent(nxpdev->serdev, 0); + nxpdev->fw_v3_offset_correction += req_len; + return true; + } + return false; +} + +static bool nxp_fw_change_timeout(struct hci_dev *hdev, u16 req_len) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct nxp_bootloader_cmd nxp_cmd7; + + if (req_len != sizeof(nxp_cmd7)) + return false; + + nxp_cmd7.header = __cpu_to_le32(7); + nxp_cmd7.arg = __cpu_to_le32(0x70); + nxp_cmd7.payload_len = 0; + /* FW expects swapped CRC bytes */ + nxp_cmd7.crc = __cpu_to_be32(crc32_be(0UL, (char *)&nxp_cmd7, + sizeof(nxp_cmd7) - 4)); + serdev_device_write_buf(nxpdev->serdev, (u8 *)&nxp_cmd7, sizeof(nxp_cmd7)); + serdev_device_wait_until_sent(nxpdev->serdev, 0); + nxpdev->fw_v3_offset_correction += req_len; + return true; +} + +static u32 nxp_get_data_len(const u8 *buf) +{ + struct nxp_bootloader_cmd *hdr = (struct nxp_bootloader_cmd *)buf; + + return __le32_to_cpu(hdr->payload_len); +} + +static bool is_fw_downloading(struct btnxpuart_dev *nxpdev) +{ + return test_bit(BTNXPUART_FW_DOWNLOADING, &nxpdev->tx_state); +} + +static bool process_boot_signature(struct btnxpuart_dev *nxpdev) +{ + if (test_bit(BTNXPUART_CHECK_BOOT_SIGNATURE, &nxpdev->tx_state)) { + clear_bit(BTNXPUART_CHECK_BOOT_SIGNATURE, &nxpdev->tx_state); + wake_up_interruptible(&nxpdev->check_boot_sign_wait_q); + return false; + } + return is_fw_downloading(nxpdev); +} + +static int nxp_request_firmware(struct hci_dev *hdev, const char *fw_name) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + int err = 0; + + if (!fw_name) + return -ENOENT; + + if (!strlen(nxpdev->fw_name)) { + snprintf(nxpdev->fw_name, MAX_FW_FILE_NAME_LEN, "%s", fw_name); + + bt_dev_dbg(hdev, "Request Firmware: %s", nxpdev->fw_name); + err = request_firmware(&nxpdev->fw, nxpdev->fw_name, &hdev->dev); + if (err < 0) { + bt_dev_err(hdev, "Firmware file %s not found", nxpdev->fw_name); + clear_bit(BTNXPUART_FW_DOWNLOADING, &nxpdev->tx_state); + } + } + return err; +} + +/* for legacy chipsets with V1 bootloader */ +static int nxp_recv_chip_ver_v1(struct hci_dev *hdev, struct sk_buff *skb) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct v1_start_ind *req; + __u16 chip_id; + + req = skb_pull_data(skb, sizeof(*req)); + if (!req) + goto free_skb; + + chip_id = le16_to_cpu(req->chip_id ^ req->chip_id_comp); + if (chip_id == 0xffff && nxpdev->fw_dnld_v1_offset) { + nxpdev->fw_dnld_v1_offset = 0; + nxpdev->fw_v1_sent_bytes = 0; + nxpdev->fw_v1_expected_len = HDR_LEN; + release_firmware(nxpdev->fw); + memset(nxpdev->fw_name, 0, sizeof(nxpdev->fw_name)); + nxp_send_ack(NXP_ACK_V1, hdev); + } + +free_skb: + kfree_skb(skb); + return 0; +} + +static int nxp_recv_fw_req_v1(struct hci_dev *hdev, struct sk_buff *skb) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct btnxpuart_data *nxp_data = nxpdev->nxp_data; + struct v1_data_req *req; + __u16 len; + + if (!process_boot_signature(nxpdev)) + goto free_skb; + + req = skb_pull_data(skb, sizeof(*req)); + if (!req) + goto free_skb; + + len = __le16_to_cpu(req->len ^ req->len_comp); + if (len != 0xffff) { + bt_dev_dbg(hdev, "ERR: Send NAK"); + nxp_send_ack(NXP_NAK_V1, hdev); + goto free_skb; + } + nxp_send_ack(NXP_ACK_V1, hdev); + + len = __le16_to_cpu(req->len); + + if (!nxp_data->helper_fw_name) { + if (!nxpdev->timeout_changed) { + nxpdev->timeout_changed = nxp_fw_change_timeout(hdev, + len); + goto free_skb; + } + if (!nxpdev->baudrate_changed) { + nxpdev->baudrate_changed = nxp_fw_change_baudrate(hdev, + len); + if (nxpdev->baudrate_changed) { + serdev_device_set_baudrate(nxpdev->serdev, + HCI_NXP_SEC_BAUDRATE); + serdev_device_set_flow_control(nxpdev->serdev, true); + nxpdev->current_baudrate = HCI_NXP_SEC_BAUDRATE; + } + goto free_skb; + } + } + + if (!nxp_data->helper_fw_name || nxpdev->helper_downloaded) { + if (nxp_request_firmware(hdev, nxp_data->fw_name)) + goto free_skb; + } else if (nxp_data->helper_fw_name && !nxpdev->helper_downloaded) { + if (nxp_request_firmware(hdev, nxp_data->helper_fw_name)) + goto free_skb; + } + + if (!len) { + bt_dev_dbg(hdev, "FW Downloaded Successfully: %zu bytes", + nxpdev->fw->size); + if (nxp_data->helper_fw_name && !nxpdev->helper_downloaded) { + nxpdev->helper_downloaded = true; + serdev_device_wait_until_sent(nxpdev->serdev, 0); + serdev_device_set_baudrate(nxpdev->serdev, + HCI_NXP_SEC_BAUDRATE); + serdev_device_set_flow_control(nxpdev->serdev, true); + } else { + clear_bit(BTNXPUART_FW_DOWNLOADING, &nxpdev->tx_state); + wake_up_interruptible(&nxpdev->fw_dnld_done_wait_q); + } + goto free_skb; + } + if (len & 0x01) { + /* The CRC did not match at the other end. + * Simply send the same bytes again. + */ + len = nxpdev->fw_v1_sent_bytes; + bt_dev_dbg(hdev, "CRC error. Resend %d bytes of FW.", len); + } else { + nxpdev->fw_dnld_v1_offset += nxpdev->fw_v1_sent_bytes; + + /* The FW bin file is made up of many blocks of + * 16 byte header and payload data chunks. If the + * FW has requested a header, read the payload length + * info from the header, before sending the header. + * In the next iteration, the FW should request the + * payload data chunk, which should be equal to the + * payload length read from header. If there is a + * mismatch, clearly the driver and FW are out of sync, + * and we need to re-send the previous header again. + */ + if (len == nxpdev->fw_v1_expected_len) { + if (len == HDR_LEN) + nxpdev->fw_v1_expected_len = nxp_get_data_len(nxpdev->fw->data + + nxpdev->fw_dnld_v1_offset); + else + nxpdev->fw_v1_expected_len = HDR_LEN; + } else if (len == HDR_LEN) { + /* FW download out of sync. Send previous chunk again */ + nxpdev->fw_dnld_v1_offset -= nxpdev->fw_v1_sent_bytes; + nxpdev->fw_v1_expected_len = HDR_LEN; + } + } + + if (nxpdev->fw_dnld_v1_offset + len <= nxpdev->fw->size) + serdev_device_write_buf(nxpdev->serdev, nxpdev->fw->data + + nxpdev->fw_dnld_v1_offset, len); + nxpdev->fw_v1_sent_bytes = len; + +free_skb: + kfree_skb(skb); + return 0; +} + +static char *nxp_get_fw_name_from_chipid(struct hci_dev *hdev, u16 chipid, + u8 loader_ver) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + char *fw_name = NULL; + + switch (chipid) { + case CHIP_ID_W9098: + fw_name = FIRMWARE_W9098; + break; + case CHIP_ID_IW416: + fw_name = FIRMWARE_IW416; + break; + case CHIP_ID_IW612: + fw_name = FIRMWARE_IW612; + break; + case CHIP_ID_IW624a: + case CHIP_ID_IW624c: + nxpdev->boot_reg_offset = 1; + if ((loader_ver & FW_SECURE_MASK) == FW_OPEN) + fw_name = FIRMWARE_IW624; + else if ((loader_ver & FW_SECURE_MASK) != FW_AUTH_ILLEGAL) + fw_name = FIRMWARE_SECURE_IW624; + else + bt_dev_err(hdev, "Illegal loader version %02x", loader_ver); + break; + case CHIP_ID_AW693: + if ((loader_ver & FW_SECURE_MASK) == FW_OPEN) + fw_name = FIRMWARE_AW693; + else if ((loader_ver & FW_SECURE_MASK) != FW_AUTH_ILLEGAL) + fw_name = FIRMWARE_SECURE_AW693; + else + bt_dev_err(hdev, "Illegal loader version %02x", loader_ver); + break; + default: + bt_dev_err(hdev, "Unknown chip signature %04x", chipid); + break; + } + return fw_name; +} + +static int nxp_recv_chip_ver_v3(struct hci_dev *hdev, struct sk_buff *skb) +{ + struct v3_start_ind *req = skb_pull_data(skb, sizeof(*req)); + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + u16 chip_id; + u8 loader_ver; + + if (!process_boot_signature(nxpdev)) + goto free_skb; + + chip_id = le16_to_cpu(req->chip_id); + loader_ver = req->loader_ver; + if (!nxp_request_firmware(hdev, nxp_get_fw_name_from_chipid(hdev, + chip_id, loader_ver))) + nxp_send_ack(NXP_ACK_V3, hdev); + +free_skb: + kfree_skb(skb); + return 0; +} + +static int nxp_recv_fw_req_v3(struct hci_dev *hdev, struct sk_buff *skb) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct v3_data_req *req; + __u16 len; + __u32 offset; + + if (!process_boot_signature(nxpdev)) + goto free_skb; + + req = skb_pull_data(skb, sizeof(*req)); + if (!req || !nxpdev->fw) + goto free_skb; + + nxp_send_ack(NXP_ACK_V3, hdev); + + len = __le16_to_cpu(req->len); + + if (!nxpdev->timeout_changed) { + nxpdev->timeout_changed = nxp_fw_change_timeout(hdev, len); + goto free_skb; + } + + if (!nxpdev->baudrate_changed) { + nxpdev->baudrate_changed = nxp_fw_change_baudrate(hdev, len); + if (nxpdev->baudrate_changed) { + serdev_device_set_baudrate(nxpdev->serdev, + HCI_NXP_SEC_BAUDRATE); + serdev_device_set_flow_control(nxpdev->serdev, true); + nxpdev->current_baudrate = HCI_NXP_SEC_BAUDRATE; + } + goto free_skb; + } + + if (req->len == 0) { + bt_dev_dbg(hdev, "FW Downloaded Successfully: %zu bytes", + nxpdev->fw->size); + clear_bit(BTNXPUART_FW_DOWNLOADING, &nxpdev->tx_state); + wake_up_interruptible(&nxpdev->fw_dnld_done_wait_q); + goto free_skb; + } + if (req->error) + bt_dev_dbg(hdev, "FW Download received err 0x%02x from chip", + req->error); + + offset = __le32_to_cpu(req->offset); + if (offset < nxpdev->fw_v3_offset_correction) { + /* This scenario should ideally never occur. But if it ever does, + * FW is out of sync and needs a power cycle. + */ + bt_dev_err(hdev, "Something went wrong during FW download"); + bt_dev_err(hdev, "Please power cycle and try again"); + goto free_skb; + } + + serdev_device_write_buf(nxpdev->serdev, nxpdev->fw->data + offset - + nxpdev->fw_v3_offset_correction, len); + +free_skb: + kfree_skb(skb); + return 0; +} + +static int nxp_set_baudrate_cmd(struct hci_dev *hdev, void *data) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + __le32 new_baudrate = __cpu_to_le32(nxpdev->new_baudrate); + struct ps_data *psdata = &nxpdev->psdata; + struct sk_buff *skb; + u8 *status; + + if (!psdata) + return 0; + + skb = nxp_drv_send_cmd(hdev, HCI_NXP_SET_OPER_SPEED, 4, (u8 *)&new_baudrate); + if (IS_ERR(skb)) { + bt_dev_err(hdev, "Setting baudrate failed (%ld)", PTR_ERR(skb)); + return PTR_ERR(skb); + } + + status = (u8 *)skb_pull_data(skb, 1); + if (status) { + if (*status == 0) { + serdev_device_set_baudrate(nxpdev->serdev, nxpdev->new_baudrate); + nxpdev->current_baudrate = nxpdev->new_baudrate; + } + bt_dev_dbg(hdev, "Set baudrate response: status=%d, baudrate=%d", + *status, nxpdev->new_baudrate); + } + kfree_skb(skb); + + return 0; +} + +static int nxp_check_boot_sign(struct btnxpuart_dev *nxpdev) +{ + serdev_device_set_baudrate(nxpdev->serdev, HCI_NXP_PRI_BAUDRATE); + if (test_bit(BTNXPUART_IR_IN_PROGRESS, &nxpdev->tx_state)) + serdev_device_set_flow_control(nxpdev->serdev, false); + else + serdev_device_set_flow_control(nxpdev->serdev, true); + set_bit(BTNXPUART_CHECK_BOOT_SIGNATURE, &nxpdev->tx_state); + + return wait_event_interruptible_timeout(nxpdev->check_boot_sign_wait_q, + !test_bit(BTNXPUART_CHECK_BOOT_SIGNATURE, + &nxpdev->tx_state), + msecs_to_jiffies(1000)); +} + +static int nxp_set_ind_reset(struct hci_dev *hdev, void *data) +{ + static const u8 ir_hw_err[] = { HCI_EV_HARDWARE_ERROR, + 0x01, BTNXPUART_IR_HW_ERR }; + struct sk_buff *skb; + + skb = bt_skb_alloc(3, GFP_ATOMIC); + if (!skb) + return -ENOMEM; + + hci_skb_pkt_type(skb) = HCI_EVENT_PKT; + skb_put_data(skb, ir_hw_err, 3); + + /* Inject Hardware Error to upper stack */ + return hci_recv_frame(hdev, skb); +} + +/* NXP protocol */ +static int nxp_setup(struct hci_dev *hdev) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + int err = 0; + + if (nxp_check_boot_sign(nxpdev)) { + bt_dev_dbg(hdev, "Need FW Download."); + err = nxp_download_firmware(hdev); + if (err < 0) + return err; + } else { + bt_dev_dbg(hdev, "FW already running."); + clear_bit(BTNXPUART_FW_DOWNLOADING, &nxpdev->tx_state); + } + + serdev_device_set_baudrate(nxpdev->serdev, nxpdev->fw_init_baudrate); + nxpdev->current_baudrate = nxpdev->fw_init_baudrate; + + if (nxpdev->current_baudrate != HCI_NXP_SEC_BAUDRATE) { + nxpdev->new_baudrate = HCI_NXP_SEC_BAUDRATE; + hci_cmd_sync_queue(hdev, nxp_set_baudrate_cmd, NULL, NULL); + } + + ps_init(hdev); + + if (test_and_clear_bit(BTNXPUART_IR_IN_PROGRESS, &nxpdev->tx_state)) + hci_dev_clear_flag(hdev, HCI_SETUP); + + return 0; +} + +static void nxp_hw_err(struct hci_dev *hdev, u8 code) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + + switch (code) { + case BTNXPUART_IR_HW_ERR: + set_bit(BTNXPUART_IR_IN_PROGRESS, &nxpdev->tx_state); + hci_dev_set_flag(hdev, HCI_SETUP); + break; + default: + break; + } +} + +static int nxp_shutdown(struct hci_dev *hdev) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct sk_buff *skb; + u8 *status; + u8 pcmd = 0; + + if (test_bit(BTNXPUART_IR_IN_PROGRESS, &nxpdev->tx_state)) { + skb = nxp_drv_send_cmd(hdev, HCI_NXP_IND_RESET, 1, &pcmd); + if (IS_ERR(skb)) + return PTR_ERR(skb); + + status = skb_pull_data(skb, 1); + if (status) { + serdev_device_set_flow_control(nxpdev->serdev, false); + set_bit(BTNXPUART_FW_DOWNLOADING, &nxpdev->tx_state); + } + kfree_skb(skb); + } + + return 0; +} + +static int btnxpuart_queue_skb(struct hci_dev *hdev, struct sk_buff *skb) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + + /* Prepend skb with frame type */ + memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); + skb_queue_tail(&nxpdev->txq, skb); + btnxpuart_tx_wakeup(nxpdev); + return 0; +} + +static int nxp_enqueue(struct hci_dev *hdev, struct sk_buff *skb) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + struct ps_data *psdata = &nxpdev->psdata; + struct hci_command_hdr *hdr; + struct psmode_cmd_payload ps_parm; + struct wakeup_cmd_payload wakeup_parm; + __le32 baudrate_parm; + + /* if vendor commands are received from user space (e.g. hcitool), update + * driver flags accordingly and ask driver to re-send the command to FW. + * In case the payload for any command does not match expected payload + * length, let the firmware and user space program handle it, or throw + * an error. + */ + if (bt_cb(skb)->pkt_type == HCI_COMMAND_PKT && !psdata->driver_sent_cmd) { + hdr = (struct hci_command_hdr *)skb->data; + if (hdr->plen != (skb->len - HCI_COMMAND_HDR_SIZE)) + return btnxpuart_queue_skb(hdev, skb); + + switch (__le16_to_cpu(hdr->opcode)) { + case HCI_NXP_AUTO_SLEEP_MODE: + if (hdr->plen == sizeof(ps_parm)) { + memcpy(&ps_parm, skb->data + HCI_COMMAND_HDR_SIZE, hdr->plen); + if (ps_parm.ps_cmd == BT_PS_ENABLE) + psdata->target_ps_mode = PS_MODE_ENABLE; + else if (ps_parm.ps_cmd == BT_PS_DISABLE) + psdata->target_ps_mode = PS_MODE_DISABLE; + psdata->c2h_ps_interval = __le16_to_cpu(ps_parm.c2h_ps_interval); + hci_cmd_sync_queue(hdev, send_ps_cmd, NULL, NULL); + goto free_skb; + } + break; + case HCI_NXP_WAKEUP_METHOD: + if (hdr->plen == sizeof(wakeup_parm)) { + memcpy(&wakeup_parm, skb->data + HCI_COMMAND_HDR_SIZE, hdr->plen); + psdata->c2h_wakeupmode = wakeup_parm.c2h_wakeupmode; + psdata->c2h_wakeup_gpio = wakeup_parm.c2h_wakeup_gpio; + psdata->h2c_wakeup_gpio = wakeup_parm.h2c_wakeup_gpio; + switch (wakeup_parm.h2c_wakeupmode) { + case BT_CTRL_WAKEUP_METHOD_DSR: + psdata->h2c_wakeupmode = WAKEUP_METHOD_DTR; + break; + case BT_CTRL_WAKEUP_METHOD_BREAK: + default: + psdata->h2c_wakeupmode = WAKEUP_METHOD_BREAK; + break; + } + hci_cmd_sync_queue(hdev, send_wakeup_method_cmd, NULL, NULL); + goto free_skb; + } + break; + case HCI_NXP_SET_OPER_SPEED: + if (hdr->plen == sizeof(baudrate_parm)) { + memcpy(&baudrate_parm, skb->data + HCI_COMMAND_HDR_SIZE, hdr->plen); + nxpdev->new_baudrate = __le32_to_cpu(baudrate_parm); + hci_cmd_sync_queue(hdev, nxp_set_baudrate_cmd, NULL, NULL); + goto free_skb; + } + break; + case HCI_NXP_IND_RESET: + if (hdr->plen == 1) { + hci_cmd_sync_queue(hdev, nxp_set_ind_reset, NULL, NULL); + goto free_skb; + } + break; + default: + break; + } + } + + return btnxpuart_queue_skb(hdev, skb); + +free_skb: + kfree_skb(skb); + return 0; +} + +static struct sk_buff *nxp_dequeue(void *data) +{ + struct btnxpuart_dev *nxpdev = (struct btnxpuart_dev *)data; + + ps_wakeup(nxpdev); + ps_start_timer(nxpdev); + return skb_dequeue(&nxpdev->txq); +} + +/* btnxpuart based on serdev */ +static void btnxpuart_tx_work(struct work_struct *work) +{ + struct btnxpuart_dev *nxpdev = container_of(work, struct btnxpuart_dev, + tx_work); + struct serdev_device *serdev = nxpdev->serdev; + struct hci_dev *hdev = nxpdev->hdev; + struct sk_buff *skb; + int len; + + while ((skb = nxp_dequeue(nxpdev))) { + len = serdev_device_write_buf(serdev, skb->data, skb->len); + hdev->stat.byte_tx += len; + + skb_pull(skb, len); + if (skb->len > 0) { + skb_queue_head(&nxpdev->txq, skb); + break; + } + + switch (hci_skb_pkt_type(skb)) { + case HCI_COMMAND_PKT: + hdev->stat.cmd_tx++; + break; + case HCI_ACLDATA_PKT: + hdev->stat.acl_tx++; + break; + case HCI_SCODATA_PKT: + hdev->stat.sco_tx++; + break; + } + + kfree_skb(skb); + } + clear_bit(BTNXPUART_TX_STATE_ACTIVE, &nxpdev->tx_state); +} + +static int btnxpuart_open(struct hci_dev *hdev) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + int err = 0; + + err = serdev_device_open(nxpdev->serdev); + if (err) { + bt_dev_err(hdev, "Unable to open UART device %s", + dev_name(&nxpdev->serdev->dev)); + } else { + set_bit(BTNXPUART_SERDEV_OPEN, &nxpdev->tx_state); + } + return err; +} + +static int btnxpuart_close(struct hci_dev *hdev) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + + ps_wakeup(nxpdev); + serdev_device_close(nxpdev->serdev); + clear_bit(BTNXPUART_SERDEV_OPEN, &nxpdev->tx_state); + return 0; +} + +static int btnxpuart_flush(struct hci_dev *hdev) +{ + struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev); + + /* Flush any pending characters */ + serdev_device_write_flush(nxpdev->serdev); + skb_queue_purge(&nxpdev->txq); + + cancel_work_sync(&nxpdev->tx_work); + + kfree_skb(nxpdev->rx_skb); + nxpdev->rx_skb = NULL; + + return 0; +} + +static const struct h4_recv_pkt nxp_recv_pkts[] = { + { H4_RECV_ACL, .recv = hci_recv_frame }, + { H4_RECV_SCO, .recv = hci_recv_frame }, + { H4_RECV_EVENT, .recv = hci_recv_frame }, + { NXP_RECV_CHIP_VER_V1, .recv = nxp_recv_chip_ver_v1 }, + { NXP_RECV_FW_REQ_V1, .recv = nxp_recv_fw_req_v1 }, + { NXP_RECV_CHIP_VER_V3, .recv = nxp_recv_chip_ver_v3 }, + { NXP_RECV_FW_REQ_V3, .recv = nxp_recv_fw_req_v3 }, +}; + +static int btnxpuart_receive_buf(struct serdev_device *serdev, const u8 *data, + size_t count) +{ + struct btnxpuart_dev *nxpdev = serdev_device_get_drvdata(serdev); + + ps_start_timer(nxpdev); + + nxpdev->rx_skb = h4_recv_buf(nxpdev->hdev, nxpdev->rx_skb, data, count, + nxp_recv_pkts, ARRAY_SIZE(nxp_recv_pkts)); + if (IS_ERR(nxpdev->rx_skb)) { + int err = PTR_ERR(nxpdev->rx_skb); + /* Safe to ignore out-of-sync bootloader signatures */ + if (is_fw_downloading(nxpdev)) + return count; + bt_dev_err(nxpdev->hdev, "Frame reassembly failed (%d)", err); + nxpdev->rx_skb = NULL; + return err; + } + if (!is_fw_downloading(nxpdev)) + nxpdev->hdev->stat.byte_rx += count; + return count; +} + +static void btnxpuart_write_wakeup(struct serdev_device *serdev) +{ + serdev_device_write_wakeup(serdev); +} + +static const struct serdev_device_ops btnxpuart_client_ops = { + .receive_buf = btnxpuart_receive_buf, + .write_wakeup = btnxpuart_write_wakeup, +}; + +static int nxp_serdev_probe(struct serdev_device *serdev) +{ + struct hci_dev *hdev; + struct btnxpuart_dev *nxpdev; + + nxpdev = devm_kzalloc(&serdev->dev, sizeof(*nxpdev), GFP_KERNEL); + if (!nxpdev) + return -ENOMEM; + + nxpdev->nxp_data = (struct btnxpuart_data *)device_get_match_data(&serdev->dev); + + nxpdev->serdev = serdev; + serdev_device_set_drvdata(serdev, nxpdev); + + serdev_device_set_client_ops(serdev, &btnxpuart_client_ops); + + INIT_WORK(&nxpdev->tx_work, btnxpuart_tx_work); + skb_queue_head_init(&nxpdev->txq); + + init_waitqueue_head(&nxpdev->fw_dnld_done_wait_q); + init_waitqueue_head(&nxpdev->check_boot_sign_wait_q); + + device_property_read_u32(&nxpdev->serdev->dev, "fw-init-baudrate", + &nxpdev->fw_init_baudrate); + if (!nxpdev->fw_init_baudrate) + nxpdev->fw_init_baudrate = FW_INIT_BAUDRATE; + + set_bit(BTNXPUART_FW_DOWNLOADING, &nxpdev->tx_state); + + crc8_populate_msb(crc8_table, POLYNOMIAL8); + + /* Initialize and register HCI device */ + hdev = hci_alloc_dev(); + if (!hdev) { + dev_err(&serdev->dev, "Can't allocate HCI device\n"); + return -ENOMEM; + } + + nxpdev->hdev = hdev; + + hdev->bus = HCI_UART; + hci_set_drvdata(hdev, nxpdev); + + hdev->manufacturer = MANUFACTURER_NXP; + hdev->open = btnxpuart_open; + hdev->close = btnxpuart_close; + hdev->flush = btnxpuart_flush; + hdev->setup = nxp_setup; + hdev->send = nxp_enqueue; + hdev->hw_error = nxp_hw_err; + hdev->shutdown = nxp_shutdown; + SET_HCIDEV_DEV(hdev, &serdev->dev); + + if (hci_register_dev(hdev) < 0) { + dev_err(&serdev->dev, "Can't register HCI device\n"); + hci_free_dev(hdev); + return -ENODEV; + } + + ps_setup(hdev); + + return 0; +} + +static void nxp_serdev_remove(struct serdev_device *serdev) +{ + struct btnxpuart_dev *nxpdev = serdev_device_get_drvdata(serdev); + struct hci_dev *hdev = nxpdev->hdev; + + /* Restore FW baudrate to fw_init_baudrate if changed. + * This will ensure FW baudrate is in sync with + * driver baudrate in case this driver is re-inserted. + */ + if (nxpdev->current_baudrate != nxpdev->fw_init_baudrate) { + nxpdev->new_baudrate = nxpdev->fw_init_baudrate; + nxp_set_baudrate_cmd(hdev, NULL); + } + + ps_cancel_timer(nxpdev); + hci_unregister_dev(hdev); + hci_free_dev(hdev); +} + +static struct btnxpuart_data w8987_data __maybe_unused = { + .helper_fw_name = NULL, + .fw_name = FIRMWARE_W8987, +}; + +static struct btnxpuart_data w8997_data __maybe_unused = { + .helper_fw_name = FIRMWARE_HELPER, + .fw_name = FIRMWARE_W8997, +}; + +static const struct of_device_id nxpuart_of_match_table[] __maybe_unused = { + { .compatible = "nxp,88w8987-bt", .data = &w8987_data }, + { .compatible = "nxp,88w8997-bt", .data = &w8997_data }, + { } +}; +MODULE_DEVICE_TABLE(of, nxpuart_of_match_table); + +static struct serdev_device_driver nxp_serdev_driver = { + .probe = nxp_serdev_probe, + .remove = nxp_serdev_remove, + .driver = { + .name = "btnxpuart", + .of_match_table = of_match_ptr(nxpuart_of_match_table), + }, +}; + +module_serdev_device_driver(nxp_serdev_driver); + +MODULE_AUTHOR("Neeraj Sanjay Kale "); +MODULE_DESCRIPTION("NXP Bluetooth Serial driver"); +MODULE_LICENSE("GPL"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/bluetooth/Kconfig linux-imx-phytec/drivers/bluetooth/Kconfig --- linux-6.1.55/drivers/bluetooth/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/bluetooth/Kconfig 2024-06-19 12:33:59.480212744 +0200 @@ -442,4 +442,17 @@ Say Y here to compile support for HCI over Virtio into the kernel or say M to compile as a module. +config BT_NXPUART + tristate "NXP protocol support" + depends on SERIAL_DEV_BUS + select CRC32 + select CRC8 + help + NXP is serial driver required for NXP Bluetooth + devices with UART interface. + + Say Y here to compile support for NXP Bluetooth UART device into + the kernel, or say M here to compile as a module (btnxpuart). + + endmenu diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/bluetooth/Makefile linux-imx-phytec/drivers/bluetooth/Makefile --- linux-6.1.55/drivers/bluetooth/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/bluetooth/Makefile 2024-06-19 12:33:59.480212744 +0200 @@ -28,6 +28,7 @@ obj-$(CONFIG_BT_MTK) += btmtk.o obj-$(CONFIG_BT_VIRTIO) += virtio_bt.o +obj-$(CONFIG_BT_NXPUART) += btnxpuart.o obj-$(CONFIG_BT_HCIUART_NOKIA) += hci_nokia.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/bus/fsl-mc/dprc-driver.c linux-imx-phytec/drivers/bus/fsl-mc/dprc-driver.c --- linux-6.1.55/drivers/bus/fsl-mc/dprc-driver.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/bus/fsl-mc/dprc-driver.c 2024-06-19 12:33:59.488212881 +0200 @@ -624,7 +624,6 @@ struct irq_domain *mc_msi_domain; bool mc_io_created = false; bool msi_domain_set = false; - bool uapi_created = false; u16 major_ver, minor_ver; size_t region_size; int error; @@ -657,11 +656,6 @@ return error; mc_io_created = true; - } else { - error = fsl_mc_uapi_create_device_file(mc_bus); - if (error < 0) - return -EPROBE_DEFER; - uapi_created = true; } mc_msi_domain = fsl_mc_find_msi_domain(&mc_dev->dev); @@ -719,9 +713,6 @@ mc_dev->mc_io = NULL; } - if (uapi_created) - fsl_mc_uapi_remove_device_file(mc_bus); - return error; } EXPORT_SYMBOL_GPL(dprc_setup); @@ -740,9 +731,15 @@ { int error; + if (fsl_mc_is_root_dprc(&mc_dev->dev)) { + error = fsl_mc_uapi_create_device_file(to_fsl_mc_bus(mc_dev)); + if (error < 0) + return -EPROBE_DEFER; + } + error = dprc_setup(mc_dev); if (error < 0) - return error; + goto uapi_cleanup; /* * Discover MC objects in DPRC object: @@ -765,6 +762,10 @@ device_for_each_child(&mc_dev->dev, NULL, __fsl_mc_device_remove); dprc_cleanup: dprc_cleanup(mc_dev); +uapi_cleanup: + if (fsl_mc_is_root_dprc(&mc_dev->dev)) + fsl_mc_uapi_remove_device_file(to_fsl_mc_bus(mc_dev)); + return error; } @@ -773,7 +774,12 @@ */ static void dprc_teardown_irq(struct fsl_mc_device *mc_dev) { - struct fsl_mc_device_irq *irq = mc_dev->irqs[0]; + struct fsl_mc_device_irq *irq; + + if (!mc_dev->irqs) + return; + + irq = mc_dev->irqs[0]; (void)disable_dprc_irq(mc_dev); @@ -793,7 +799,6 @@ int dprc_cleanup(struct fsl_mc_device *mc_dev) { - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); int error; /* this function should be called only for DPRCs, it @@ -803,12 +808,11 @@ return -EINVAL; if (dev_get_msi_domain(&mc_dev->dev)) { + dprc_teardown_irq(mc_dev); fsl_mc_cleanup_irq_pool(mc_dev); dev_set_msi_domain(&mc_dev->dev, NULL); } - fsl_mc_cleanup_all_resource_pools(mc_dev); - /* if this step fails we cannot go further with cleanup as there is no way of * communicating with the firmware */ @@ -824,8 +828,6 @@ if (!fsl_mc_is_root_dprc(&mc_dev->dev)) { fsl_destroy_mc_io(mc_dev->mc_io); mc_dev->mc_io = NULL; - } else { - fsl_mc_uapi_remove_device_file(mc_bus); } return 0; @@ -837,32 +839,49 @@ * * @mc_dev: Pointer to fsl-mc device representing the DPRC * - * It removes the DPRC's child objects from Linux (not from the MC) and - * closes the DPRC device in the MC. - * It tears down the interrupts that were configured for the DPRC device. - * It destroys the interrupt pool associated with this MC bus. + * It removes the DPRC's child objects from Linux (not from the MC). */ static int dprc_remove(struct fsl_mc_device *mc_dev) { - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - if (!is_fsl_mc_bus_dprc(mc_dev)) return -EINVAL; - if (!mc_bus->irq_resources) - return -EINVAL; - - if (dev_get_msi_domain(&mc_dev->dev)) - dprc_teardown_irq(mc_dev); - device_for_each_child(&mc_dev->dev, NULL, __fsl_mc_device_remove); dprc_cleanup(mc_dev); + if (fsl_mc_is_root_dprc(&mc_dev->dev)) + fsl_mc_uapi_remove_device_file(to_fsl_mc_bus(mc_dev)); + dev_info(&mc_dev->dev, "DPRC device unbound from driver"); + return 0; } +/** + * dprc_shutdown - callback invoked when a DPRC should be quiesced + * + * @mc_dev: Pointer to fsl-mc device representing the DPRC + * + * Closes the DPRC device in the MC. + * It tears down the interrupts that were configured for the DPRC device. + * It destroys the interrupt pool associated with this MC bus. + */ +static void dprc_shutdown(struct fsl_mc_device *mc_dev) +{ + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); + + if (!is_fsl_mc_bus_dprc(mc_dev)) + return; + + if (!mc_bus->irq_resources) + return; + + dprc_cleanup(mc_dev); + + dev_info(&mc_dev->dev, "DPRC device shutdown"); +} + static const struct fsl_mc_device_id match_id_table[] = { { .vendor = FSL_MC_VENDOR_FREESCALE, @@ -879,6 +898,7 @@ .match_id_table = match_id_table, .probe = dprc_probe, .remove = dprc_remove, + .shutdown = dprc_shutdown, }; int __init dprc_driver_init(void) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/bus/fsl-mc/fsl-mc-allocator.c linux-imx-phytec/drivers/bus/fsl-mc/fsl-mc-allocator.c --- linux-6.1.55/drivers/bus/fsl-mc/fsl-mc-allocator.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/bus/fsl-mc/fsl-mc-allocator.c 2024-06-19 12:33:59.488212881 +0200 @@ -549,30 +549,6 @@ } } -static void fsl_mc_cleanup_resource_pool(struct fsl_mc_device *mc_bus_dev, - enum fsl_mc_pool_type pool_type) -{ - struct fsl_mc_resource *resource; - struct fsl_mc_resource *next; - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); - struct fsl_mc_resource_pool *res_pool = - &mc_bus->resource_pools[pool_type]; - int free_count = 0; - - list_for_each_entry_safe(resource, next, &res_pool->free_list, node) { - free_count++; - devm_kfree(&mc_bus_dev->dev, resource); - } -} - -void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev) -{ - int pool_type; - - for (pool_type = 0; pool_type < FSL_MC_NUM_POOL_TYPES; pool_type++) - fsl_mc_cleanup_resource_pool(mc_bus_dev, pool_type); -} - /* * fsl_mc_allocator_probe - callback invoked when an allocatable device is * being added to the system diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/bus/fsl-mc/fsl-mc-bus.c linux-imx-phytec/drivers/bus/fsl-mc/fsl-mc-bus.c --- linux-6.1.55/drivers/bus/fsl-mc/fsl-mc-bus.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/bus/fsl-mc/fsl-mc-bus.c 2024-06-19 12:33:59.488212881 +0200 @@ -457,10 +457,12 @@ struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); int error; - error = mc_drv->remove(mc_dev); - if (error < 0) { - dev_err(dev, "%s failed: %d\n", __func__, error); - return error; + if (mc_drv->remove) { + error = mc_drv->remove(mc_dev); + if (error < 0) { + dev_err(dev, "%s failed: %d\n", __func__, error); + return error; + } } return 0; @@ -468,10 +470,16 @@ static void fsl_mc_driver_shutdown(struct device *dev) { - struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(dev->driver); struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + struct fsl_mc_driver *mc_drv; - mc_drv->shutdown(mc_dev); + if (!dev->driver) + return; + + mc_drv = to_fsl_mc_driver(dev->driver); + + if (mc_drv->shutdown) + mc_drv->shutdown(mc_dev); } /* @@ -910,8 +918,10 @@ error_cleanup_dev: kfree(mc_dev->regions); - kfree(mc_bus); - kfree(mc_dev); + if (mc_bus) + kfree(mc_bus); + else + kfree(mc_dev); return error; } @@ -1233,19 +1243,18 @@ } /* - * fsl_mc_bus_remove - callback invoked when the root MC bus is being - * removed + * fsl_mc_bus_shutdown - callback invoked when the root MC bus is being + * shutdown */ -static int fsl_mc_bus_remove(struct platform_device *pdev) +static void fsl_mc_bus_shutdown(struct platform_device *pdev) { struct fsl_mc *mc = platform_get_drvdata(pdev); struct fsl_mc_io *mc_io; if (!fsl_mc_is_root_dprc(&mc->root_mc_bus_dev->dev)) - return -EINVAL; + return; mc_io = mc->root_mc_bus_dev->mc_io; - fsl_mc_device_remove(mc->root_mc_bus_dev); fsl_destroy_mc_io(mc_io); bus_unregister_notifier(&fsl_mc_bus_type, &fsl_mc_nb); @@ -1259,13 +1268,24 @@ (GCR1_P1_STOP | GCR1_P2_STOP), mc->fsl_mc_regs + FSL_MC_GCR1); } - - return 0; } -static void fsl_mc_bus_shutdown(struct platform_device *pdev) +/* + * fsl_mc_bus_remove - callback invoked when the root MC bus is being + * removed + */ +static int fsl_mc_bus_remove(struct platform_device *pdev) { - fsl_mc_bus_remove(pdev); + struct fsl_mc *mc = platform_get_drvdata(pdev); + + if (!fsl_mc_is_root_dprc(&mc->root_mc_bus_dev->dev)) + return -EINVAL; + + fsl_mc_device_remove(mc->root_mc_bus_dev); + + fsl_mc_bus_shutdown(pdev); + + return 0; } static const struct of_device_id fsl_mc_bus_match_table[] = { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/bus/fsl-mc/fsl-mc-private.h linux-imx-phytec/drivers/bus/fsl-mc/fsl-mc-private.h --- linux-6.1.55/drivers/bus/fsl-mc/fsl-mc-private.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/bus/fsl-mc/fsl-mc-private.h 2024-06-19 12:33:59.488212881 +0200 @@ -635,8 +635,6 @@ void fsl_mc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev); -void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev); - int __must_check fsl_mc_resource_allocate(struct fsl_mc_bus *mc_bus, enum fsl_mc_pool_type pool_type, struct fsl_mc_resource diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/bus/fsl-mc/fsl-mc-uapi.c linux-imx-phytec/drivers/bus/fsl-mc/fsl-mc-uapi.c --- linux-6.1.55/drivers/bus/fsl-mc/fsl-mc-uapi.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/bus/fsl-mc/fsl-mc-uapi.c 2024-06-19 12:33:59.488212881 +0200 @@ -48,6 +48,7 @@ DPRC_GET_POOL, DPRC_GET_POOL_COUNT, DPRC_GET_CONNECTION, + DPRC_GET_MEM, DPCI_GET_LINK_STATE, DPCI_GET_PEER_ATTR, DPAIOP_GET_SL_VERSION, @@ -194,6 +195,12 @@ .token = true, .size = 32, }, + [DPRC_GET_MEM] = { + .cmdid_value = 0x16D0, + .cmdid_mask = 0xFFF0, + .token = true, + .size = 12, + }, [DPCI_GET_LINK_STATE] = { .cmdid_value = 0x0E10, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/bus/fsl-mc/mc-sys.c linux-imx-phytec/drivers/bus/fsl-mc/mc-sys.c --- linux-6.1.55/drivers/bus/fsl-mc/mc-sys.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/bus/fsl-mc/mc-sys.c 2024-06-19 12:33:59.492212949 +0200 @@ -19,7 +19,7 @@ /* * Timeout in milliseconds to wait for the completion of an MC command */ -#define MC_CMD_COMPLETION_TIMEOUT_MS 500 +#define MC_CMD_COMPLETION_TIMEOUT_MS 15000 /* * usleep_range() min and max values used to throttle down polling diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/bus/simple-pm-bus.c linux-imx-phytec/drivers/bus/simple-pm-bus.c --- linux-6.1.55/drivers/bus/simple-pm-bus.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/bus/simple-pm-bus.c 2024-06-19 12:33:59.496213017 +0200 @@ -13,36 +13,11 @@ #include #include + static int simple_pm_bus_probe(struct platform_device *pdev) { - const struct device *dev = &pdev->dev; - const struct of_dev_auxdata *lookup = dev_get_platdata(dev); - struct device_node *np = dev->of_node; - const struct of_device_id *match; - - /* - * Allow user to use driver_override to bind this driver to a - * transparent bus device which has a different compatible string - * that's not listed in simple_pm_bus_of_match. We don't want to do any - * of the simple-pm-bus tasks for these devices, so return early. - */ - if (pdev->driver_override) - return 0; - - match = of_match_device(dev->driver->of_match_table, dev); - /* - * These are transparent bus devices (not simple-pm-bus matches) that - * have their child nodes populated automatically. So, don't need to - * do anything more. We only match with the device if this driver is - * the most specific match because we don't want to incorrectly bind to - * a device that has a more specific driver. - */ - if (match && match->data) { - if (of_property_match_string(np, "compatible", match->compatible) == 0) - return 0; - else - return -ENODEV; - } + const struct of_dev_auxdata *lookup = dev_get_platdata(&pdev->dev); + struct device_node *np = pdev->dev.of_node; dev_dbg(&pdev->dev, "%s\n", __func__); @@ -56,25 +31,14 @@ static int simple_pm_bus_remove(struct platform_device *pdev) { - const void *data = of_device_get_match_data(&pdev->dev); - - if (pdev->driver_override || data) - return 0; - dev_dbg(&pdev->dev, "%s\n", __func__); pm_runtime_disable(&pdev->dev); return 0; } -#define ONLY_BUS ((void *) 1) /* Match if the device is only a bus. */ - static const struct of_device_id simple_pm_bus_of_match[] = { { .compatible = "simple-pm-bus", }, - { .compatible = "simple-bus", .data = ONLY_BUS }, - { .compatible = "simple-mfd", .data = ONLY_BUS }, - { .compatible = "isa", .data = ONLY_BUS }, - { .compatible = "arm,amba-bus", .data = ONLY_BUS }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, simple_pm_bus_of_match); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/char/imx_amp/imx_sema4.c linux-imx-phytec/drivers/char/imx_amp/imx_sema4.c --- linux-6.1.55/drivers/char/imx_amp/imx_sema4.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/char/imx_amp/imx_sema4.c 2024-06-19 12:33:59.508213222 +0200 @@ -0,0 +1,412 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct imx_sema4_mutex_device *imx6_sema4; +static unsigned long sema4_flags; + + +/*! + * \brief mutex create function. + * + * This function allocates imx_sema4_mutex structure and returns a handle + * to it. The mutex to be created is identified by SEMA4 device number and mutex + * (gate) number. The handle is used to reference the created mutex in calls to + * other imx_sema4_mutex API functions. This function is to be called only + * once for each mutex. + * + * \param[in] dev_num SEMA4 device (module) number. + * \param[in] mutex_num Mutex (gate) number. + * + * \return NULL (Failure.) + * \return imx_sema4_mutex (Success.) + */ +struct imx_sema4_mutex * +imx_sema4_mutex_create(u32 dev_num, u32 mutex_num) +{ + struct imx_sema4_mutex *mutex_ptr = NULL; + + if (mutex_num >= SEMA4_NUM_GATES || dev_num >= SEMA4_NUM_DEVICES) + goto out; + + if (imx6_sema4->cpine_val & (1 < mutex_num)) { + pr_err("Error: requiring a allocated sema4.\n"); + pr_err("mutex_num %d cpine_val 0x%08x.\n", + mutex_num, imx6_sema4->cpine_val); + } + mutex_ptr = kzalloc(sizeof(*mutex_ptr), GFP_KERNEL); + if (!mutex_ptr) + goto out; + imx6_sema4->mutex_ptr[mutex_num] = mutex_ptr; + imx6_sema4->alloced |= 1 < mutex_num; + imx6_sema4->cpine_val |= idx_sema4[mutex_num]; + writew(imx6_sema4->cpine_val, imx6_sema4->ioaddr + SEMA4_CP0INE); + + mutex_ptr->valid = CORE_MUTEX_VALID; + mutex_ptr->gate_num = mutex_num; + init_waitqueue_head(&mutex_ptr->wait_q); + +out: + return mutex_ptr; +} +EXPORT_SYMBOL(imx_sema4_mutex_create); + +/*! + * \brief mutex destroy function. + * + * This function destroys a mutex. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return MQX_COMPONENT_DOES_NOT_EXIST (mutex component not installed.) + * \return MQX_INVALID_PARAMETER (Wrong input parameter.) + * \return COREMUTEX_OK (Success.) + * + */ +int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr) +{ + u32 mutex_num; + + if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID)) + return -EINVAL; + + mutex_num = mutex_ptr->gate_num; + if ((imx6_sema4->cpine_val & idx_sema4[mutex_num]) == 0) { + pr_err("Error: trying to destroy a un-allocated sema4.\n"); + pr_err("mutex_num %d cpine_val 0x%08x.\n", + mutex_num, imx6_sema4->cpine_val); + } + imx6_sema4->mutex_ptr[mutex_num] = NULL; + imx6_sema4->alloced &= ~(1 << mutex_num); + imx6_sema4->cpine_val &= ~(idx_sema4[mutex_num]); + writew(imx6_sema4->cpine_val, imx6_sema4->ioaddr + SEMA4_CP0INE); + + kfree(mutex_ptr); + + return 0; +} +EXPORT_SYMBOL(imx_sema4_mutex_destroy); + +/*! + * \brief Lock the mutex, shouldn't be interruted by INT. + * + * This function attempts to lock a mutex. If the mutex is already locked + * by another task the function return -EBUSY, and tell invoker wait until + * it is possible to lock the mutex. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return MQX_INVALID_POINTER (Wrong pointer to the mutex structure provided.) + * \return COREMUTEX_OK (mutex successfully locked.) + * + * \see imx_sema4_mutex_unlock + */ +int _imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0, i = 0; + + if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID)) + return -EINVAL; + + i = mutex_ptr->gate_num; + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* Check to see if this core already own it */ + if (mutex_ptr->gate_val == SEMA4_A9_LOCK) { + /* return -EBUSY, invoker should be in sleep, and re-lock ag */ + pr_err("%s -> %s %d already locked, wait! num %d val %d.\n", + __FILE__, __func__, __LINE__, + i, mutex_ptr->gate_val); + ret = -EBUSY; + goto out; + } else { + /* try to lock the mutex */ + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + mutex_ptr->gate_val |= SEMA4_A9_LOCK; + writeb(mutex_ptr->gate_val, imx6_sema4->ioaddr + i); + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* double check the mutex is locked, otherwise, return -EBUSY */ + if (mutex_ptr->gate_val != SEMA4_A9_LOCK) { + pr_debug("wait-locked num %d val %d.\n", + i, mutex_ptr->gate_val); + ret = -EBUSY; + } + } +out: + return ret; +} + +/* ! + * \brief Try to lock the core mutex. + * + * This function attempts to lock a mutex. If the mutex is successfully locked + * for the calling task, SEMA4_A9_LOCK is returned. If the mutex is already + * locked by another task, the function does not block but rather returns + * negative immediately. + * + * \param[in] mutex_ptr Pointer to core_mutex structure. + * + * \return SEMA4_A9_LOCK (mutex successfully locked.) + * \return negative (mutex not locked.) + * + */ +int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0; + + ret = _imx_sema4_mutex_lock(mutex_ptr); + if (ret == 0) + return SEMA4_A9_LOCK; + else + return ret; +} +EXPORT_SYMBOL(imx_sema4_mutex_trylock); + +/*! + * \brief Invoke _imx_sema4_mutex_lock to lock the mutex. + * + * This function attempts to lock a mutex. If the mutex is already locked + * by another task the function, sleep itself and schedule out. + * Wait until it is possible to lock the mutex. + * + * Invoker should add its own wait queue into the wait queue header of the + * required semaphore, set TASK_INTERRUPTIBLE and sleep on itself by + * schedule() when the lock is failed. Re-try to lock the semaphore when + * it is woke up by the sema4 isr. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return SEMA4_A9_LOCK (mutex successfully locked.) + * + * \see imx_sema4_mutex_unlock + */ +int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0; + + spin_lock_irqsave(&imx6_sema4->lock, sema4_flags); + ret = _imx_sema4_mutex_lock(mutex_ptr); + while (-EBUSY == ret) { + ret = _imx_sema4_mutex_lock(mutex_ptr); + if (ret == 0) + break; + } + + return ret; +} +EXPORT_SYMBOL(imx_sema4_mutex_lock); + +/*! + * \brief Unlock the mutex. + * + * This function unlocks the specified mutex. + * + * \param[in] mutex_ptr Pointer to mutex structure. + * + * \return -EINVAL (Wrong pointer to the mutex structure provided.) + * \return -EINVAL (This mutex has not been locked by this core.) + * \return 0 (mutex successfully unlocked.) + * + * \see imx_sema4_mutex_lock + */ +int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr) +{ + int ret = 0, i = 0; + + if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID)) + return -EINVAL; + + i = mutex_ptr->gate_num; + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* make sure it is locked by this core */ + if (mutex_ptr->gate_val != SEMA4_A9_LOCK) { + pr_err("%d Trying to unlock an unlock mutex.\n", __LINE__); + ret = -EINVAL; + goto out; + } + /* unlock it */ + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + writeb(mutex_ptr->gate_val | SEMA4_UNLOCK, imx6_sema4->ioaddr + i); + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + /* make sure it is locked by this core */ + if (mutex_ptr->gate_val == SEMA4_A9_LOCK) + pr_err("%d ERROR, failed to unlock the mutex.\n", __LINE__); + + spin_unlock_irqrestore(&imx6_sema4->lock, sema4_flags); +out: + return ret; +} +EXPORT_SYMBOL(imx_sema4_mutex_unlock); + +/* + * isr used by SEMA4, wake up the sleep tasks if there are the tasks waiting + * for locking semaphore. + * FIXME the bits order of the gatn, cpnie, cpnntf are not exact identified yet! + */ +static irqreturn_t imx_sema4_isr(int irq, void *dev_id) +{ + int i; + struct imx_sema4_mutex *mutex_ptr; + unsigned int mask; + struct imx_sema4_mutex_device *imx6_sema4 = dev_id; + + imx6_sema4->cpntf_val = readw(imx6_sema4->ioaddr + SEMA4_CP0NTF); + for (i = 0; i < SEMA4_NUM_GATES; i++) { + mask = idx_sema4[i]; + if ((imx6_sema4->cpntf_val) & mask) { + mutex_ptr = imx6_sema4->mutex_ptr[i]; + /* + * An interrupt is pending on this mutex, the only way + * to clear it is to lock it (either by this core or + * another). + */ + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + mutex_ptr->gate_val |= SEMA4_A9_LOCK; + writeb(mutex_ptr->gate_val, imx6_sema4->ioaddr + i); + mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= SEMA4_GATE_MASK; + if (mutex_ptr->gate_val == SEMA4_A9_LOCK) { + /* + * wake up the wait queue, whatever there + * are wait task or not. + * NOTE: check gate is locted or not in + * sema4_lock func by wait task. + */ + mutex_ptr->gate_val = + readb(imx6_sema4->ioaddr + i); + mutex_ptr->gate_val &= (~SEMA4_GATE_MASK); + mutex_ptr->gate_val |= SEMA4_UNLOCK; + + writeb(mutex_ptr->gate_val, + imx6_sema4->ioaddr + i); + wake_up(&mutex_ptr->wait_q); + } else { + pr_debug("can't lock gate%d %s retry!\n", i, + mutex_ptr->gate_val ? + "locked by m4" : ""); + } + } + } + + return IRQ_HANDLED; +} + +static const struct of_device_id imx_sema4_dt_ids[] = { + { .compatible = "fsl,imx6sx-sema4", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_sema4_dt_ids); + +static int imx_sema4_probe(struct platform_device *pdev) +{ + struct resource *res; + int ret; + + imx6_sema4 = devm_kzalloc(&pdev->dev, sizeof(*imx6_sema4), GFP_KERNEL); + if (!imx6_sema4) + return -ENOMEM; + + imx6_sema4->dev = &pdev->dev; + imx6_sema4->cpine_val = 0; + spin_lock_init(&imx6_sema4->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) { + dev_err(&pdev->dev, "unable to get imx sema4 resource 0\n"); + ret = -ENODEV; + goto err; + } + + imx6_sema4->ioaddr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(imx6_sema4->ioaddr)) { + ret = PTR_ERR(imx6_sema4->ioaddr); + goto err; + } + + imx6_sema4->irq = platform_get_irq(pdev, 0); + if (!imx6_sema4->irq) { + dev_err(&pdev->dev, "failed to get irq\n"); + ret = -ENODEV; + goto err; + } + + ret = devm_request_irq(&pdev->dev, imx6_sema4->irq, imx_sema4_isr, + IRQF_SHARED, "imx6sx-sema4", imx6_sema4); + if (ret) { + dev_err(&pdev->dev, "failed to request imx sema4 irq\n"); + ret = -ENODEV; + goto err; + } + + platform_set_drvdata(pdev, imx6_sema4); + +err: + return ret; +} + +static int imx_sema4_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver imx_sema4_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "imx-sema4", + .of_match_table = imx_sema4_dt_ids, + }, + .probe = imx_sema4_probe, + .remove = imx_sema4_remove, +}; + +static int __init imx_sema4_init(void) +{ + int ret; + + ret = platform_driver_register(&imx_sema4_driver); + if (ret) + pr_err("Unable to initialize sema4 driver\n"); + else + pr_info("imx sema4 driver is registered.\n"); + + return ret; +} + +static void __exit imx_sema4_exit(void) +{ + pr_info("imx sema4 driver is unregistered.\n"); + platform_driver_unregister(&imx_sema4_driver); +} + +module_exit(imx_sema4_exit); +module_init(imx_sema4_init); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IMX SEMA4 driver"); +MODULE_LICENSE("GPL"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/char/imx_amp/Kconfig linux-imx-phytec/drivers/char/imx_amp/Kconfig --- linux-6.1.55/drivers/char/imx_amp/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/char/imx_amp/Kconfig 2024-06-19 12:33:59.508213222 +0200 @@ -0,0 +1,9 @@ +# +# imx mcc +# + +config IMX_SEMA4 + bool "IMX SEMA4 driver" + depends on SOC_IMX6SX + help + Support for IMX SEMA4 driver, most people should say N here. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/char/imx_amp/Makefile linux-imx-phytec/drivers/char/imx_amp/Makefile --- linux-6.1.55/drivers/char/imx_amp/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/char/imx_amp/Makefile 2024-06-19 12:33:59.508213222 +0200 @@ -0,0 +1,5 @@ +# +# Makefile for imx mcc +# +# +obj-$(CONFIG_IMX_SEMA4) += imx_sema4.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/char/Kconfig linux-imx-phytec/drivers/char/Kconfig --- linux-6.1.55/drivers/char/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/char/Kconfig 2024-06-19 12:33:59.496213017 +0200 @@ -423,6 +423,8 @@ and SSM (Silicon Secured Memory). Intended consumers of this driver include crash and makedumpfile. +source "drivers/char/imx_amp/Kconfig" + config RANDOM_TRUST_CPU bool "Initialize RNG using CPU RNG instructions" default y diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/char/Makefile linux-imx-phytec/drivers/char/Makefile --- linux-6.1.55/drivers/char/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/char/Makefile 2024-06-19 12:33:59.496213017 +0200 @@ -45,3 +45,4 @@ obj-$(CONFIG_XILLYBUS_CLASS) += xillybus/ obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o obj-$(CONFIG_ADI) += adi.o +obj-$(CONFIG_HAVE_IMX_AMP) += imx_amp/ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-blk-ctrl.c linux-imx-phytec/drivers/clk/imx/clk-blk-ctrl.c --- linux-6.1.55/drivers/clk/imx/clk-blk-ctrl.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/imx/clk-blk-ctrl.c 2024-06-19 12:33:59.552213975 +0200 @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 NXP. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-blk-ctrl.h" + +struct reset_hw { + u32 offset; + u32 shift; + u32 mask; + unsigned long asserted; +}; + +struct pm_safekeep_info { + uint32_t *regs_values; + uint32_t *regs_offsets; + uint32_t regs_num; +}; + +struct imx_blk_ctrl_drvdata { + void __iomem *base; + struct reset_controller_dev rcdev; + struct reset_hw *rst_hws; + struct pm_safekeep_info pm_info; + + spinlock_t *lock; +}; + +static int imx_blk_ctrl_reset_set(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct imx_blk_ctrl_drvdata *drvdata = container_of(rcdev, + struct imx_blk_ctrl_drvdata, rcdev); + unsigned int offset = drvdata->rst_hws[id].offset; + unsigned int shift = drvdata->rst_hws[id].shift; + unsigned int mask = drvdata->rst_hws[id].mask; + void __iomem *reg_addr = drvdata->base + offset; + unsigned long flags; + u32 reg; + + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) + return -ENODEV; + + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) + pm_runtime_get_sync(rcdev->dev); + + spin_lock_irqsave(drvdata->lock, flags); + + reg = readl(reg_addr); + if (assert) + writel(reg & ~(mask << shift), reg_addr); + else + writel(reg | (mask << shift), reg_addr); + + spin_unlock_irqrestore(drvdata->lock, flags); + + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) + pm_runtime_put_sync(rcdev->dev); + + return 0; +} + +static int imx_blk_ctrl_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + imx_blk_ctrl_reset_set(rcdev, id, true); + return imx_blk_ctrl_reset_set(rcdev, id, false); +} + +static int imx_blk_ctrl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx_blk_ctrl_reset_set(rcdev, id, true); +} + +static int imx_blk_ctrl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx_blk_ctrl_reset_set(rcdev, id, false); +} + +static const struct reset_control_ops imx_blk_ctrl_reset_ops = { + .reset = imx_blk_ctrl_reset_reset, + .assert = imx_blk_ctrl_reset_assert, + .deassert = imx_blk_ctrl_reset_deassert, +}; + +static int imx_blk_ctrl_register_reset_controller(struct device *dev) +{ + struct imx_blk_ctrl_drvdata *drvdata = dev_get_drvdata(dev); + const struct imx_blk_ctrl_dev_data *dev_data = of_device_get_match_data(dev); + struct reset_hw *hws; + int max = dev_data->resets_max; + int i; + + drvdata->lock = &imx_ccm_lock; + + drvdata->rcdev.owner = THIS_MODULE; + drvdata->rcdev.nr_resets = max; + drvdata->rcdev.ops = &imx_blk_ctrl_reset_ops; + drvdata->rcdev.of_node = dev->of_node; + drvdata->rcdev.dev = dev; + + drvdata->rst_hws = devm_kzalloc(dev, sizeof(struct reset_hw) * max, + GFP_KERNEL); + hws = drvdata->rst_hws; + + for (i = 0; i < dev_data->hws_num; i++) { + struct imx_blk_ctrl_hw *hw = &dev_data->hws[i]; + + if (hw->type != BLK_CTRL_RESET) + continue; + + hws[hw->id].offset = hw->offset; + hws[hw->id].shift = hw->shift; + hws[hw->id].mask = hw->mask; + } + + return devm_reset_controller_register(dev, &drvdata->rcdev); +} +static struct clk_hw *imx_blk_ctrl_register_one_clock(struct device *dev, + struct imx_blk_ctrl_hw *hw) +{ + struct imx_blk_ctrl_drvdata *drvdata = dev_get_drvdata(dev); + void __iomem *base = drvdata->base; + struct clk_hw *clk_hw; + + switch (hw->type) { + case BLK_CTRL_CLK_MUX: + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, + base + hw->offset, + hw->shift, hw->width, + hw->parents, + hw->parents_count, + hw->flags); + break; + case BLK_CTRL_CLK_GATE: + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, + base + hw->offset, hw->shift); + break; + case BLK_CTRL_CLK_SHARED_GATE: + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, + hw->parents, + base + hw->offset, + hw->shift, + hw->shared_count); + break; + case BLK_CTRL_CLK_PLL14XX: + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, + base + hw->offset, hw->pll_tbl); + break; + default: + clk_hw = NULL; + }; + + return clk_hw; +} + +static int imx_blk_ctrl_register_clock_controller(struct device *dev) +{ + const struct imx_blk_ctrl_dev_data *dev_data = of_device_get_match_data(dev); + struct clk_hw_onecell_data *clk_hw_data; + struct clk_hw **hws; + int i; + + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, + dev_data->hws_num), GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num = dev_data->clocks_max; + hws = clk_hw_data->hws; + + for (i = 0; i < dev_data->hws_num; i++) { + struct imx_blk_ctrl_hw *hw = &dev_data->hws[i]; + struct clk_hw *tmp = imx_blk_ctrl_register_one_clock(dev, hw); + + if (!tmp) + continue; + hws[hw->id] = tmp; + } + + imx_check_clk_hws(hws, dev_data->clocks_max); + + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + clk_hw_data); +} + +static int imx_blk_ctrl_init_runtime_pm_safekeeping(struct device *dev) +{ + const struct imx_blk_ctrl_dev_data *dev_data = of_device_get_match_data(dev); + struct imx_blk_ctrl_drvdata *drvdata = dev_get_drvdata(dev); + struct pm_safekeep_info *pm_info = &drvdata->pm_info; + u32 regs_num = dev_data->pm_runtime_saved_regs_num; + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; + + if (!dev_data->pm_runtime_saved_regs_num) + return 0; + + pm_info->regs_values = devm_kzalloc(dev, + sizeof(u32) * regs_num, + GFP_KERNEL); + if (WARN_ON(IS_ERR(pm_info->regs_values))) + return PTR_ERR(pm_info->regs_values); + + pm_info->regs_offsets = kmemdup(regs_offsets, + regs_num * sizeof(u32), GFP_KERNEL); + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) + return PTR_ERR(pm_info->regs_offsets); + + pm_info->regs_num = regs_num; + + return 0; +} + +static int imx_blk_ctrl_probe(struct platform_device *pdev) +{ + struct imx_blk_ctrl_drvdata *drvdata; + struct device *dev = &pdev->dev; + int ret; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (WARN_ON(!drvdata)) + return -ENOMEM; + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(drvdata->base))) + return PTR_ERR(drvdata->base); + + dev_set_drvdata(dev, drvdata); + + ret = imx_blk_ctrl_init_runtime_pm_safekeeping(dev); + if (ret) + return ret; + + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + ret = imx_blk_ctrl_register_clock_controller(dev); + if (ret) { + pm_runtime_put(dev); + return ret; + } + + ret = imx_blk_ctrl_register_reset_controller(dev); + + pm_runtime_put(dev); + + return ret; +} + +static void imx_blk_ctrl_read_write(struct device *dev, bool write) +{ + struct imx_blk_ctrl_drvdata *drvdata = dev_get_drvdata(dev); + struct pm_safekeep_info *pm_info = &drvdata->pm_info; + void __iomem *base = drvdata->base; + unsigned long flags; + int i; + + if (!pm_info->regs_num) + return; + + spin_lock_irqsave(drvdata->lock, flags); + + for (i = 0; i < pm_info->regs_num; i++) { + u32 offset = pm_info->regs_offsets[i]; + + if (write) + writel(pm_info->regs_values[i], base + offset); + else + pm_info->regs_values[i] = readl(base + offset); + } + + spin_unlock_irqrestore(drvdata->lock, flags); + +} + +static int imx_blk_ctrl_runtime_suspend(struct device *dev) +{ + imx_blk_ctrl_read_write(dev, false); + + return 0; +} + +static int imx_blk_ctrl_runtime_resume(struct device *dev) +{ + imx_blk_ctrl_read_write(dev, true); + + return 0; +} + +static const struct dev_pm_ops imx_blk_ctrl_pm_ops = { + SET_RUNTIME_PM_OPS(imx_blk_ctrl_runtime_suspend, + imx_blk_ctrl_runtime_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static const struct of_device_id imx_blk_ctrl_of_match[] = { + { + .compatible = "fsl,imx8mp-audio-blk-ctrl-legacy", + .data = &imx8mp_audio_blk_ctrl_dev_data + }, + { + .compatible = "fsl,imx8mp-media-blk-ctrl-legacy", + .data = &imx8mp_media_blk_ctrl_dev_data + }, + { + .compatible = "fsl,imx8mp-hdmi-blk-ctrl-legacy", + .data = &imx8mp_hdmi_blk_ctrl_dev_data + }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_blk_ctrl_of_match); + +static struct platform_driver imx_blk_ctrl_driver = { + .probe = imx_blk_ctrl_probe, + .driver = { + .name = "imx-blk-ctrl", + .of_match_table = of_match_ptr(imx_blk_ctrl_of_match), + .pm = &imx_blk_ctrl_pm_ops, + }, +}; +module_platform_driver(imx_blk_ctrl_driver); +MODULE_LICENSE("GPL v2"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-blk-ctrl.h linux-imx-phytec/drivers/clk/imx/clk-blk-ctrl.h --- linux-6.1.55/drivers/clk/imx/clk-blk-ctrl.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/imx/clk-blk-ctrl.h 2024-06-19 12:33:59.552213975 +0200 @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __MACH_IMX_CLK_BLK_CTRL_H +#define __MACH_IMX_CLK_BLK_CTRL_H + +enum imx_blk_ctrl_hw_type { + BLK_CTRL_CLK_MUX, + BLK_CTRL_CLK_GATE, + BLK_CTRL_CLK_SHARED_GATE, + BLK_CTRL_CLK_PLL14XX, + BLK_CTRL_RESET, +}; + +struct imx_blk_ctrl_hw { + int type; + char *name; + u32 offset; + u32 shift; + u32 mask; + u32 width; + u32 flags; + u32 id; + void *parents; + u32 parents_count; + int *shared_count; + const struct imx_pll14xx_clk *pll_tbl; +}; + +struct imx_blk_ctrl_dev_data { + struct imx_blk_ctrl_hw *hws; + u32 hws_num; + + u32 clocks_max; + u32 resets_max; + + u32 pm_runtime_saved_regs_num; + u32 pm_runtime_saved_regs[]; +}; + +#define IMX_BLK_CTRL(_type, _name, _id, _offset, _shift, _width, _mask, _parents, _parents_count, _flags, sh_count, _pll_tbl) \ + { \ + .type = _type, \ + .name = _name, \ + .id = _id, \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + .mask = _mask, \ + .parents = _parents, \ + .parents_count = _parents_count, \ + .flags = _flags, \ + .shared_count = sh_count, \ + .pll_tbl = _pll_tbl, \ + } + +#define IMX_BLK_CTRL_CLK_MUX(_name, _id, _offset, _shift, _width, _parents) \ + IMX_BLK_CTRL(BLK_CTRL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), 0, NULL, NULL) + +#define IMX_BLK_CTRL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, _parents, _flags) \ + IMX_BLK_CTRL(BLK_CTRL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) + +#define IMX_BLK_CTRL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ + IMX_BLK_CTRL(BLK_CTRL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, NULL, NULL) + +#define IMX_BLK_CTRL_CLK_SHARED_GATE(_name, _id, _offset, _shift, _parents, sh_count) \ + IMX_BLK_CTRL(BLK_CTRL_CLK_SHARED_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, sh_count, NULL) + +#define IMX_BLK_CTRL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) \ + IMX_BLK_CTRL(BLK_CTRL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, _parents, 1, 0, NULL, _pll_tbl) + +#define IMX_BLK_CTRL_RESET(_id, _offset, _shift) \ + IMX_BLK_CTRL(BLK_CTRL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, 0, NULL, NULL) + +#define IMX_BLK_CTRL_RESET_MASK(_id, _offset, _shift, mask) \ + IMX_BLK_CTRL(BLK_CTRL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, 0, 0, NULL, NULL) + +extern const struct imx_blk_ctrl_dev_data imx8mp_audio_blk_ctrl_dev_data; +extern const struct imx_blk_ctrl_dev_data imx8mp_media_blk_ctrl_dev_data; +extern const struct imx_blk_ctrl_dev_data imx8mp_hdmi_blk_ctrl_dev_data; + +#endif + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk.c linux-imx-phytec/drivers/clk/imx/clk.c --- linux-6.1.55/drivers/clk/imx/clk.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk.c 2024-06-19 12:33:59.560214112 +0200 @@ -19,6 +19,7 @@ bool mcore_booted; EXPORT_SYMBOL_GPL(mcore_booted); +bool uart_from_osc; void imx_unregister_clocks(struct clk *clks[], unsigned int count) { @@ -199,6 +200,9 @@ static int __init imx_clk_disable_uart(void) { + if (imx_src_is_m4_enabled()) + return 0; + if (imx_keep_uart_clocks && imx_enabled_uart_clocks) { int i; @@ -212,6 +216,14 @@ return 0; } late_initcall_sync(imx_clk_disable_uart); + +static int __init setup_uart_clk(char *uart_rate) +{ + uart_from_osc = true; + return 1; +} +__setup("uart_from_osc", setup_uart_clk); + #endif MODULE_LICENSE("GPL v2"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-composite-7ulp.c linux-imx-phytec/drivers/clk/imx/clk-composite-7ulp.c --- linux-6.1.55/drivers/clk/imx/clk-composite-7ulp.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-composite-7ulp.c 2024-06-19 12:33:59.552213975 +0200 @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -14,6 +15,7 @@ #include "../clk-fractional-divider.h" #include "clk.h" +#define PCG_PR_MASK BIT(31) #define PCG_PCS_SHIFT 24 #define PCG_PCS_MASK 0x7 #define PCG_CGC_SHIFT 30 @@ -37,6 +39,9 @@ if (ret) return ret; + /* wait before release reset */ + udelay(1); + spin_lock_irqsave(gate->lock, flags); /* * release the sw reset for peripherals associated with @@ -48,6 +53,9 @@ spin_unlock_irqrestore(gate->lock, flags); + /* wait sync reset done */ + udelay(1); + return 0; } @@ -80,6 +88,10 @@ struct clk_hw *hw; u32 val; + val = readl(reg); + if (!(val & PCG_PR_MASK)) + return ERR_PTR(-ENODEV); + if (mux_present) { mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-composite-93.c linux-imx-phytec/drivers/clk/imx/clk-composite-93.c --- linux-6.1.55/drivers/clk/imx/clk-composite-93.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-composite-93.c 2024-06-19 12:33:59.552213975 +0200 @@ -222,7 +222,7 @@ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, &clk_mux_ro_ops, div_hw, &clk_divider_ro_ops, NULL, NULL, flags); - } else { + } else if (!mcore_booted) { gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) goto fail; @@ -238,6 +238,12 @@ &imx93_clk_composite_divider_ops, gate_hw, &imx93_clk_composite_gate_ops, flags | CLK_SET_RATE_NO_REPARENT); + } else { + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + mux_hw, &imx93_clk_composite_mux_ops, div_hw, + &imx93_clk_composite_divider_ops, NULL, + &imx93_clk_composite_gate_ops, + flags | CLK_SET_RATE_NO_REPARENT); } if (IS_ERR(hw)) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-fracn-gppll.c linux-imx-phytec/drivers/clk/imx/clk-fracn-gppll.c --- linux-6.1.55/drivers/clk/imx/clk-fracn-gppll.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-fracn-gppll.c 2024-06-19 12:33:59.552213975 +0200 @@ -67,6 +67,11 @@ * The Fvco should be in range 2.5Ghz to 5Ghz */ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { + PLL_FRACN_GP(1700000000U, 141, 0, 0, 1, 2), + PLL_FRACN_GP(1400000000U, 175, 0, 0, 1, 3), + PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4), + PLL_FRACN_GP(900000000U, 150, 0, 0, 1, 4), + PLL_FRACN_GP(800000000U, 200, 0, 0, 1, 6), PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6), PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6), @@ -74,7 +79,8 @@ PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), - PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10) + PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10), + PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12) }; struct imx_fracn_gppll_clk imx_fracn_gppll = { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-gate2.c linux-imx-phytec/drivers/clk/imx/clk-gate2.c --- linux-6.1.55/drivers/clk/imx/clk-gate2.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-gate2.c 2024-06-19 12:33:59.552213975 +0200 @@ -8,11 +8,13 @@ #include #include +#include #include #include #include #include #include +#include #include "clk.h" /** @@ -38,9 +40,8 @@ #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw) -static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable) +static void clk_gate2_do_hardware(struct clk_gate2 *gate, bool enable) { - struct clk_gate2 *gate = to_clk_gate2(hw); u32 reg; reg = readl(gate->reg); @@ -50,6 +51,39 @@ writel(reg, gate->reg); } +static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable) +{ + struct clk_gate2 *gate = to_clk_gate2(hw); + + if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { +#ifdef CONFIG_SOC_IMX6SX + if (!amp_power_mutex || !shared_mem) { + if (enable) + clk_gate2_do_hardware(gate, enable); + return; + } + + imx_sema4_mutex_lock(amp_power_mutex); + if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || + shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + if (!imx_update_shared_mem(hw, enable)) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + clk_gate2_do_hardware(gate, enable); + + imx_sema4_mutex_unlock(amp_power_mutex); +#endif + } else { + clk_gate2_do_hardware(gate, enable); + } +} + static int clk_gate2_enable(struct clk_hw *hw) { struct clk_gate2 *gate = to_clk_gate2(hw); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk.h linux-imx-phytec/drivers/clk/imx/clk.h --- linux-6.1.55/drivers/clk/imx/clk.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk.h 2024-06-19 12:33:59.560214112 +0200 @@ -5,6 +5,7 @@ #include #include #include +#include extern spinlock_t imx_ccm_lock; extern bool mcore_booted; @@ -23,6 +24,9 @@ void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count); extern void imx_cscmr1_fixup(u32 *val); +extern struct imx_sema4_mutex *amp_power_mutex; +extern struct imx_shared_mem *shared_mem; +extern bool uart_from_osc; enum imx_pllv1_type { IMX_PLLV1_IMX1, @@ -134,7 +138,7 @@ to_clk(imx_clk_hw_gate2(name, parent, reg, shift)) #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \ - to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL)) + to_clk(__imx_clk_hw_gate2(NULL, name, parent, reg, shift, cgr_val, 0, NULL)) #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \ to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)) @@ -167,25 +171,28 @@ imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0) #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \ - __imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE) + __imx_clk_hw_gate(NULL, name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE) #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \ - __imx_clk_hw_gate(name, parent, reg, shift, flags, 0) + __imx_clk_hw_gate(NULL, name, parent, reg, shift, flags, 0) + +#define imx_dev_clk_hw_gate(dev, name, parent, reg, shift) \ + __imx_clk_hw_gate(dev, name, parent, reg, shift, 0, 0) + +#define imx_dev_clk_hw_gate_shared(dev, name, parent, reg, shift, shared_count) \ + __imx_clk_hw_gate2(dev, name, parent, reg, shift, 0x1, 0, shared_count) #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \ - __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL) + __imx_clk_hw_gate2(NULL, name, parent, reg, shift, 0x3, flags, NULL) #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \ - __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count) + __imx_clk_hw_gate2(NULL, name, parent, reg, shift, 0x3, 0, shared_count) #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \ - __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count) - -#define imx_clk_hw_gate3(name, parent, reg, shift) \ - imx_clk_hw_gate3_flags(name, parent, reg, shift, 0) + __imx_clk_hw_gate2(NULL, name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count) #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \ - __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0) + __imx_clk_hw_gate(NULL, name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0) #define imx_clk_hw_gate4(name, parent, reg, shift) \ imx_clk_hw_gate4_flags(name, parent, reg, shift, 0) @@ -197,16 +204,19 @@ imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0) #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \ - __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0) + __imx_clk_hw_mux(NULL, name, reg, shift, width, parents, num_parents, 0, 0) #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ - __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0) + __imx_clk_hw_mux(NULL, name, reg, shift, width, parents, num_parents, flags, 0) + +#define imx_dev_clk_hw_mux_flags(dev, name, reg, shift, width, parents, num_parents, flags) \ + __imx_clk_hw_mux(dev, name, reg, shift, width, parents, num_parents, flags, 0) #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \ - __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY) + __imx_clk_hw_mux(NULL, name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY) #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ - __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0) + __imx_clk_hw_mux(NULL, name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0) #define imx_clk_hw_divider(name, parent, reg, shift, width) \ __imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT) @@ -254,6 +264,25 @@ IMX_PLLV3_AV_IMX7, }; +#define MAX_SHARED_CLK_NUMBER 100 +#define SHARED_MEM_MAGIC_NUMBER 0x12345678 +#define MCC_POWER_SHMEM_NUMBER (6) + +struct imx_shared_clk { + struct clk *self; + struct clk *parent; + void *m4_clk; + void *m4_clk_parent; + u8 ca9_enabled; + u8 cm4_enabled; +}; + +struct imx_shared_mem { + u32 ca9_valid; + u32 cm4_valid; + struct imx_shared_clk imx_clk[MAX_SHARED_CLK_NUMBER]; +}; + struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask); @@ -309,6 +338,13 @@ u8 width, void __iomem *busy_reg, u8 busy_shift, const char * const *parent_names, int num_parents); +int imx_update_shared_mem(struct clk_hw *hw, bool enable); + +static inline int clk_on_imx6sx(void) +{ + return of_machine_is_compatible("fsl,imx6sx"); +} + struct clk_hw *imx7ulp_clk_hw_composite(const char *name, const char * const *parent_names, int num_parents, bool mux_present, @@ -348,6 +384,15 @@ CLK_SET_RATE_PARENT, mult, div); } +static inline struct clk_hw *imx_clk_hw_divider_closest(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width) +{ + return clk_hw_register_divider(NULL, name, parent, 0, + reg, shift, width, CLK_DIVIDER_ROUND_CLOSEST, &imx_ccm_lock); +} + static inline struct clk_hw *__imx_clk_hw_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, @@ -357,33 +402,63 @@ reg, shift, width, 0, &imx_ccm_lock); } -static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent, +static inline struct clk_hw *__imx_clk_hw_gate(struct device *dev, const char *name, + const char *parent, void __iomem *reg, u8 shift, unsigned long flags, unsigned long clk_gate_flags) { - return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, + return clk_hw_register_gate(dev, name, parent, flags | CLK_SET_RATE_PARENT, reg, shift, clk_gate_flags, &imx_ccm_lock); } -static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent, +static inline struct clk_hw *__imx_clk_hw_gate2(struct device *dev, const char *name, + const char *parent, void __iomem *reg, u8 shift, u8 cgr_val, unsigned long flags, unsigned int *share_count) { - return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, - shift, cgr_val, 0x3, 0, &imx_ccm_lock, share_count); + return clk_hw_register_gate2(dev, name, parent, flags | CLK_SET_RATE_PARENT, reg, + shift, cgr_val, cgr_val, 0, &imx_ccm_lock, share_count); } -static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg, +static inline struct clk *imx_dev_clk_mux(struct device *dev, const char *name, + void __iomem *reg, u8 shift, u8 width, + const char * const *parents, int num_parents) +{ + return clk_register_mux(dev, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE, + reg, shift, width, 0, &imx_ccm_lock); +} + +static inline struct clk_hw *__imx_clk_hw_mux(struct device *dev, + const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, unsigned long flags, unsigned long clk_mux_flags) { - return clk_hw_register_mux(NULL, name, parents, num_parents, + return clk_hw_register_mux(dev, name, parents, num_parents, flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, clk_mux_flags, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + /* + * per design team's suggestion, clk root is NOT consuming + * much power, and clk root enable/disable does NOT have domain + * control, so they suggest to leave clk root always on when + * M4 is enabled. + */ + if (imx_src_is_m4_enabled()) + return clk_hw_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, 1, 1); + else + return clk_hw_register_gate(NULL, name, parent, + CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, 0, &imx_ccm_lock); +} + struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); @@ -460,4 +535,7 @@ unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); + +void clk_set_delta_k(struct clk_hw *hw, short int delta_k); +void clk_get_pll_setting(struct clk_hw *hw, u32 *pll_div_ctrl0, u32 *pll_div_ctrl1); #endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx6q.c linux-imx-phytec/drivers/clk/imx/clk-imx6q.c --- linux-6.1.55/drivers/clk/imx/clk-imx6q.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx6q.c 2024-06-19 12:33:59.556214044 +0200 @@ -27,7 +27,8 @@ static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; -static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; +static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", }; +static const char *axi_sels[] = { "periph", "axi_alt_sel", }; static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; static const char *gpu_axi_sels[] = { "axi", "ahb", }; static const char *pre_axi_sels[] = { "axi", "ahb", }; @@ -37,15 +38,17 @@ static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; +static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", }; +static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", }; static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; +static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; +static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; +static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; +static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_div_sel", "ldb_di1_div_sel", }; static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; static const char *pcie_axi_sels[] = { "axi", "ahb", }; static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; @@ -91,6 +94,7 @@ static struct clk_hw **hws; static struct clk_hw_onecell_data *clk_hw_data; +static void __iomem *ccm_base; static struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, @@ -252,6 +256,11 @@ #define CCM_CCSR 0x0c #define CCM_CS2CDR 0x2c +#define CCM_CSCDR3 0x3c +#define CCM_CCGR0 0x68 +#define CCM_CCGR3 0x74 + +#define ANATOP_PLL3_PFD 0xf0 #define CCSR_PLL3_SW_CLK_SEL BIT(0) @@ -388,6 +397,62 @@ #define PFD2_CLKGATE BIT(23) #define PFD3_CLKGATE BIT(31) +/* + * workaround for ERR010579, when switching the clock source of IPU clock + * root in CCM. even setting CCGR3[CG0]=0x0 to gate off clock before + * switching, IPU may hang due to no IPU clock from CCM. + */ +static void __init init_ipu_clk(void __iomem *anatop_base) +{ + u32 val, origin_podf; + + /* gate off the IPU1_IPU clock */ + val = readl_relaxed(ccm_base + CCM_CCGR3); + val &= ~0x3; + writel_relaxed(val, ccm_base + CCM_CCGR3); + + /* gate off IPU DCIC1/2 clocks */ + val = readl_relaxed(ccm_base + CCM_CCGR0); + val &= ~(0xf << 24); + writel_relaxed(val, ccm_base + CCM_CCGR0); + + /* set IPU_PODF to 3'b000 */ + val = readl_relaxed(ccm_base + CCM_CSCDR3); + origin_podf = val & (0x7 << 11); + val &= ~(0x7 << 11); + writel_relaxed(val, ccm_base + CCM_CSCDR3); + + /* disable PLL3_PFD1 */ + val = readl_relaxed(anatop_base + ANATOP_PLL3_PFD); + val &= ~(0x1 << 15); + writel_relaxed(val, anatop_base + ANATOP_PLL3_PFD); + + /* switch IPU_SEL clock to PLL3_PFD1 */ + val = readl_relaxed(ccm_base + CCM_CSCDR3); + val |= (0x3 << 9); + writel_relaxed(val, ccm_base + CCM_CSCDR3); + + /* restore the IPU PODF*/ + val = readl_relaxed(ccm_base + CCM_CSCDR3); + val |= origin_podf; + writel_relaxed(val, ccm_base + CCM_CSCDR3); + + /* enable PLL3_PFD1 */ + val = readl_relaxed(anatop_base + ANATOP_PLL3_PFD); + val |= (0x1 << 15); + writel_relaxed(val, anatop_base + ANATOP_PLL3_PFD); + + /* enable IPU1_IPU clock */ + val = readl_relaxed(ccm_base + CCM_CCGR3); + val |= 0x3; + writel_relaxed(val, ccm_base + CCM_CCGR3); + + /* enable IPU DCIC1/2 clock */ + val = readl_relaxed(ccm_base + CCM_CCGR0); + val |= (0xf << 24); + writel_relaxed(val, ccm_base + CCM_CCGR0); +} + static void disable_anatop_clocks(void __iomem *anatop_base) { unsigned int reg; @@ -600,6 +665,7 @@ np = ccm_node; base = of_iomap(np, 0); + ccm_base = base; WARN_ON(!base); /* name reg shift width parent_names num_parents */ @@ -609,7 +675,8 @@ hws[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); hws[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); - hws[IMX6QDL_CLK_AXI_SEL] = imx_clk_hw_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); + hws[IMX6QDL_CLK_AXI_ALT_SEL] = imx_clk_hw_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); + hws[IMX6QDL_CLK_AXI_SEL] = imx_clk_hw_mux("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels)); hws[IMX6QDL_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); hws[IMX6QDL_CLK_ASRC_SEL] = imx_clk_hw_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); hws[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); @@ -655,6 +722,8 @@ hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); } + hws[IMX6QDL_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT); + hws[IMX6QDL_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT); hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); @@ -723,6 +792,8 @@ hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6); hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7); hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7); + hws[IMX6QDL_CLK_LDB_DI0_DIV_7] = imx_clk_hw_fixed_factor("ldb_di0_div_7", "ldb_di0", 1, 7); + hws[IMX6QDL_CLK_LDB_DI1_DIV_7] = imx_clk_hw_fixed_factor("ldb_di1_div_7", "ldb_di1", 1, 7); } else { hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "pll3_60m", base + 0x20, 2, 6); @@ -730,6 +801,8 @@ hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); + hws[IMX6QDL_CLK_LDB_DI0_DIV_7] = imx_clk_hw_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7); + hws[IMX6QDL_CLK_LDB_DI1_DIV_7] = imx_clk_hw_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7); } if (clk_on_imx6dl()) @@ -915,8 +988,24 @@ clk_hw_register_clkdev(hws[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); clk_set_rate(hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, 540000000); - if (clk_on_imx6dl()) + if (clk_on_imx6dl()) { + init_ipu_clk(anatop_base); clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk); + clk_set_parent(hws[IMX6QDL_CLK_AXI_ALT_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk); + clk_set_parent(hws[IMX6QDL_CLK_AXI_SEL]->clk, hws[IMX6QDL_CLK_AXI_ALT_SEL]->clk); + /* set eim_slow to 135Mhz */ + clk_set_rate(hws[IMX6QDL_CLK_EIM_SLOW]->clk, 135000000); + + /* set epdc/pxp axi clock to 200Mhz */ + clk_set_parent(hws[IMX6QDL_CLK_IPU2_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk); + clk_set_rate(hws[IMX6QDL_CLK_IPU2]->clk, 200000000); + } else { + /* set eim_slow to 132Mhz */ + clk_set_rate(hws[IMX6QDL_CLK_EIM_SLOW]->clk, 132000000); + clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk); + + clk_set_parent(hws[IMX6QDL_CLK_IPU2_SEL]->clk, hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk); + } clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx6sl.c linux-imx-phytec/drivers/clk/imx/clk-imx6sl.c --- linux-6.1.55/drivers/clk/imx/clk-imx6sl.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx6sl.c 2024-06-19 12:33:59.556214044 +0200 @@ -433,10 +433,20 @@ /* Audio-related clocks configuration */ clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk); + /* Initialize Video PLLs to valid frequency (650MHz). */ + clk_set_rate(hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk, 650000000); + /* set PLL5 video as lcdif pix parent clock */ clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk, hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk); + /* Configure EPDC clocks */ + clk_set_parent(hws[IMX6SL_CLK_EPDC_PIX_SEL]->clk, + hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk); + clk_set_parent(hws[IMX6SL_CLK_EPDC_AXI_SEL]->clk, + hws[IMX6SL_CLK_PLL2_PFD2]->clk); + clk_set_rate(hws[IMX6SL_CLK_EPDC_AXI]->clk, 200000000); + clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk, hws[IMX6SL_CLK_PLL2_PFD2]->clk); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx6sll.c linux-imx-phytec/drivers/clk/imx/clk-imx6sll.c --- linux-6.1.55/drivers/clk/imx/clk-imx6sll.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx6sll.c 2024-06-19 12:33:59.556214044 +0200 @@ -350,6 +350,10 @@ clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_CLK2]->clk); clk_set_parent(hws[IMX6SLL_CLK_PERIPH_PRE]->clk, hws[IMX6SLL_CLK_PLL2_BUS]->clk); clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_PRE]->clk); + /* Configure EPDC clocks */ + clk_set_rate(hws[IMX6SLL_CLK_PLL3_PFD2]->clk, 320000000); + clk_set_parent(hws[IMX6SLL_CLK_EPDC_PRE_SEL]->clk, + hws[IMX6SLL_CLK_PLL3_PFD2]->clk); clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 132000000); } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx6sx.c linux-imx-phytec/drivers/clk/imx/clk-imx6sx.c --- linux-6.1.55/drivers/clk/imx/clk-imx6sx.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx6sx.c 2024-06-19 12:33:59.556214044 +0200 @@ -11,13 +11,18 @@ #include #include #include +#include #include #include #include #include +#include +#include #include "clk.h" +#define CCM_CCGR_OFFSET(index) (index * 2) + static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; @@ -84,6 +89,12 @@ static struct clk_hw **hws; static struct clk_hw_onecell_data *clk_hw_data; +struct imx_sema4_mutex *amp_power_mutex; + +static int clks_shared[MAX_SHARED_CLK_NUMBER]; + +struct imx_shared_mem *shared_mem; +static unsigned int shared_mem_paddr, shared_mem_size; static const struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, @@ -117,6 +128,39 @@ static u32 share_count_sai1; static u32 share_count_sai2; +/* + * As IMX6SX_CLK_M4_PRE_SEL is NOT a glitchless MUX, so when + * M4 is trying to change its clk parent, need to ask A9 to + * help do it, and M4 must be hold in wfi. To avoid glitch + * occur, need to gate M4 clk first before switching its parent. + */ +void imx6sx_set_m4_highfreq(bool high_freq) +{ + static struct clk *m4_high_freq_sel; + + imx_gpc_hold_m4_in_sleep(); + + clk_disable_unprepare(hws[IMX6SX_CLK_M4]->clk); + clk_set_parent(hws[IMX6SX_CLK_M4_SEL]->clk, + hws[IMX6SX_CLK_LDB_DI0]->clk); + + if (high_freq) { + /* FIXME: m4_high_freq_sel possible used without intialization? */ + clk_set_parent(hws[IMX6SX_CLK_M4_PRE_SEL]->clk, + m4_high_freq_sel); + } else { + m4_high_freq_sel = clk_get_parent(hws[IMX6SX_CLK_M4_PRE_SEL]->clk); + clk_set_parent(hws[IMX6SX_CLK_M4_PRE_SEL]->clk, + hws[IMX6SX_CLK_OSC]->clk); + } + + clk_set_parent(hws[IMX6SX_CLK_M4_SEL]->clk, + hws[IMX6SX_CLK_M4_PRE_SEL]->clk); + clk_prepare_enable(hws[IMX6SX_CLK_M4]->clk); + + imx_gpc_release_m4_in_sleep(); +} + static void __init imx6sx_clocks_init(struct device_node *ccm_node) { struct device_node *np; @@ -182,7 +226,7 @@ clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); - hws[IMX6SX_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); + hws[IMX6SX_CLK_PLL1_SYS] = imx_clk_hw_fixed_factor("pll1_sys", "pll1_bypass", 1, 1); hws[IMX6SX_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); hws[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); hws[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); @@ -398,7 +442,7 @@ hws[IMX6SX_CLK_GPT_BUS] = imx_clk_hw_gate2("gpt_bus", "perclk", base + 0x6c, 20); hws[IMX6SX_CLK_GPT_SERIAL] = imx_clk_hw_gate2("gpt_serial", "perclk", base + 0x6c, 22); hws[IMX6SX_CLK_GPU] = imx_clk_hw_gate2("gpu", "gpu_core_podf", base + 0x6c, 26); - hws[IMX6SX_CLK_OCRAM_S] = imx_clk_hw_gate2("ocram_s", "ahb", base + 0x6c, 28); + hws[IMX6SX_CLK_OCRAM_S] = imx_clk_hw_gate2_flags("ocram_s", "ahb", base + 0x6c, 28, CLK_IS_CRITICAL); hws[IMX6SX_CLK_CANFD] = imx_clk_hw_gate2("canfd", "can_podf", base + 0x6c, 30); /* CCGR2 */ @@ -482,13 +526,59 @@ hws[IMX6SX_CLK_CKO1] = imx_clk_hw_gate("cko1", "cko1_podf", base + 0x60, 7); hws[IMX6SX_CLK_CKO2] = imx_clk_hw_gate("cko2", "cko2_podf", base + 0x60, 24); + /* get those shared clk nodes if M4 is active */ + if (imx_src_is_m4_enabled()) { + u32 num; + + of_property_read_u32(np, "fsl,shared-clks-number", &num); + if (num > MAX_SHARED_CLK_NUMBER) + pr_err("clk: shared clk nodes exceed the max number!\n"); + of_property_read_u32_array(np, "fsl,shared-clks-index", + clks_shared, num); + if (of_property_read_u32(np, "fsl,shared-mem-addr", + &shared_mem_paddr)) + pr_err("clk: fsl,shared-mem-addr NOT found!\n"); + if (of_property_read_u32(np, "fsl,shared-mem-size", + &shared_mem_size)) + pr_err("clk: fsl,shared-mem-size NOT found!\n"); + } + /* mask handshake of mmdc */ imx_mmdc_mask_handshake(base, 0); imx_check_clk_hws(hws, IMX6SX_CLK_CLK_END); + /* + * QSPI2/GPMI_IO share the same clock source but with the + * different gate, need explicitely gate the QSPI2 & GPMI_IO + * during the clock init phase according to the SOC design. + */ + if (!imx_src_is_m4_enabled()) { + writel_relaxed(readl_relaxed(base + 0x78) & + ~(3 << CCM_CCGR_OFFSET(5)), base + 0x78); + writel_relaxed(readl_relaxed(base + 0x78) & + ~(3 << CCM_CCGR_OFFSET(14)), base + 0x78); + } + + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + /* + * As some of the modules need to access ocotp in MSL, + * need to make sure ocotp clk(CCM_CCGR2_CG6) is enabled + * during MSL, as on i.MX6SX, accessing OCOTP registers + * needs its clk on, it will be disabled by clk late + * init and managed by ocotp driver. + */ + writel_relaxed(readl_relaxed(base + 0x70) | 1 << 12, base + 0x70); + + /* maintain M4 usecount */ + if (imx_src_is_m4_enabled()) + clk_prepare_enable(hws[IMX6SX_CLK_M4]->clk); + + /* set perclk to from OSC */ + clk_set_parent(hws[IMX6SX_CLK_PERCLK_SEL]->clk, hws[IMX6SX_CLK_OSC]->clk); + if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { clk_prepare_enable(hws[IMX6SX_CLK_USBPHY1_GATE]->clk); clk_prepare_enable(hws[IMX6SX_CLK_USBPHY2_GATE]->clk); @@ -520,7 +610,7 @@ clk_set_rate(hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk, 393216000); clk_set_parent(hws[IMX6SX_CLK_SPDIF_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); - clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 98304000); + clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 24576000); clk_set_parent(hws[IMX6SX_CLK_AUDIO_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk); clk_set_rate(hws[IMX6SX_CLK_AUDIO_PODF]->clk, 24000000); @@ -535,6 +625,12 @@ clk_set_parent(hws[IMX6SX_CLK_ESAI_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); clk_set_rate(hws[IMX6SX_CLK_ESAI_PODF]->clk, 24576000); + /* Set the UART parent if needed. */ + if (uart_from_osc) + clk_set_parent(hws[IMX6SX_CLK_UART_SEL]->clk, hws[IMX6SX_CLK_OSC]->clk); + else + clk_set_parent(hws[IMX6SX_CLK_UART_SEL]->clk, hws[IMX6SX_CLK_PLL3_80M]->clk); + /* Set parent clock for vadc */ clk_set_parent(hws[IMX6SX_CLK_VID_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk); @@ -544,6 +640,9 @@ /* Update gpu clock from default 528M to 720M */ clk_set_parent(hws[IMX6SX_CLK_GPU_CORE_SEL]->clk, hws[IMX6SX_CLK_PLL3_PFD0]->clk); clk_set_parent(hws[IMX6SX_CLK_GPU_AXI_SEL]->clk, hws[IMX6SX_CLK_PLL3_PFD0]->clk); + if (!imx_src_is_m4_enabled()) + /* default parent of can_sel clock is invalid, manually set it here */ + clk_set_parent(hws[IMX6SX_CLK_CAN_SEL]->clk, hws[IMX6SX_CLK_PLL3_60M]->clk); clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk); clk_set_parent(hws[IMX6SX_CLK_QSPI2_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk); @@ -551,3 +650,64 @@ imx_register_uart_clocks(2); } CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init); + +int imx_update_shared_mem(struct clk_hw *hw, bool enable) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(clks_shared); i++) { + if (shared_mem->imx_clk[i].self == hw->clk) + break; + } + + if (i >= ARRAY_SIZE(clks_shared)) + return 1; + + /* update ca9 clk status in shared memory */ + if (enable) + shared_mem->imx_clk[i].ca9_enabled = 1; + else + shared_mem->imx_clk[i].ca9_enabled = 0; + + if (shared_mem->imx_clk[i].cm4_enabled == 0) + return 1; + + return 0; +} + +static int __init imx_amp_power_init(void) +{ + int i; + void __iomem *shared_mem_base; + + if (!(imx_src_is_m4_enabled() && clk_on_imx6sx())) + return 0; + + amp_power_mutex = imx_sema4_mutex_create(0, MCC_POWER_SHMEM_NUMBER); + + shared_mem_base = ioremap(shared_mem_paddr, shared_mem_size); + + if (!amp_power_mutex) { + pr_err("Failed to create sema4 mutex!\n"); + return 0; + } + + shared_mem = (struct imx_shared_mem *)shared_mem_base; + + for (i = 0; i < ARRAY_SIZE(clks_shared); i++) { + shared_mem->imx_clk[i].self = hws[clks_shared[i]]->clk; + shared_mem->imx_clk[i].ca9_enabled = 1; + pr_debug("%d: name %s, addr 0x%x\n", i, + __clk_get_name(shared_mem->imx_clk[i].self), + (u32)&(shared_mem->imx_clk[i])); + } + /* enable amp power management */ + shared_mem->ca9_valid = SHARED_MEM_MAGIC_NUMBER; + + pr_info("A9-M4 sema4 num %d, A9-M4 magic number 0x%x - 0x%x.\n", + amp_power_mutex->gate_num, shared_mem->ca9_valid, + shared_mem->cm4_valid); + + return 0; +} +late_initcall(imx_amp_power_init); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx6ul.c linux-imx-phytec/drivers/clk/imx/clk-imx6ul.c --- linux-6.1.55/drivers/clk/imx/clk-imx6ul.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx6ul.c 2024-06-19 12:33:59.556214044 +0200 @@ -500,6 +500,12 @@ clk_set_rate(hws[IMX6UL_CLK_ENET2_REF]->clk, 50000000); clk_set_rate(hws[IMX6UL_CLK_CSI]->clk, 24000000); + /* Set the UART parent if needed */ + if (uart_from_osc) + clk_set_parent(hws[IMX6UL_CLK_UART_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk); + else + clk_set_parent(hws[IMX6UL_CLK_UART_SEL]->clk, hws[IMX6UL_CLK_PLL3_80M]->clk); + if (clk_on_imx6ull()) clk_prepare_enable(hws[IMX6UL_CLK_AIPSTZ3]->clk); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx7d.c linux-imx-phytec/drivers/clk/imx/clk-imx7d.c --- linux-6.1.55/drivers/clk/imx/clk-imx7d.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx7d.c 2024-06-19 12:33:59.556214044 +0200 @@ -15,6 +15,7 @@ #include #include #include +#include #include "clk.h" @@ -24,6 +25,7 @@ static u32 share_count_nand; static u32 share_count_enet1; static u32 share_count_enet2; +static u32 share_count_pxp; static const struct clk_div_table test_div_table[] = { { .val = 3, .div = 1, }, @@ -498,14 +500,14 @@ hws[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_hw_mux2_flags("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel), CLK_SET_PARENT_GATE); hws[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_hw_mux2_flags("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel), CLK_SET_PARENT_GATE); hws[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel), CLK_SET_PARENT_GATE); - hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel)); hws[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel), CLK_SET_PARENT_GATE); - hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel)); hws[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_hw_mux2_flags("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel), CLK_SET_PARENT_GATE); hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel), CLK_SET_PARENT_GATE); hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel), CLK_SET_PARENT_GATE); hws[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel), CLK_SET_PARENT_GATE); - hws[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel), CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT); hws[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel), CLK_SET_PARENT_GATE); hws[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel), CLK_SET_PARENT_GATE); hws[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel), CLK_SET_PARENT_GATE); @@ -790,7 +792,6 @@ hws[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_hw_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0); hws[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_hw_gate4("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0); hws[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_hw_gate4("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0); - hws[IMX7D_PXP_CLK] = imx_clk_hw_gate4("pxp_clk", "main_axi_root_clk", base + 0x44c0, 0); hws[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_hw_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0); hws[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_hw_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0); hws[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_hw_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0); @@ -853,6 +854,8 @@ hws[IMX7D_USB_PHY1_CLK] = imx_clk_hw_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0); hws[IMX7D_USB_PHY2_CLK] = imx_clk_hw_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0); hws[IMX7D_ADC_ROOT_CLK] = imx_clk_hw_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); + hws[IMX7D_PXP_IPG_CLK] = imx_clk_hw_gate2_shared2("pxp_ipg_clk", "ipg_root_clk", base + 0x44c0, 0, &share_count_pxp); + hws[IMX7D_PXP_AXI_CLK] = imx_clk_hw_gate2_shared2("pxp_axi_clk", "main_axi_root_clk", base + 0x44c0, 0, &share_count_pxp); hws[IMX7D_GPT_3M_CLK] = imx_clk_hw_fixed_factor("gpt_3m", "osc", 1, 8); @@ -875,6 +878,12 @@ clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk); + if (imx_src_is_m4_enabled()) { + clk_set_parent(hws[IMX7D_ARM_M4_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_MAIN_240M_CLK]->clk); + clk_prepare_enable(hws[IMX7D_ARM_M4_ROOT_CLK]->clk); + clk_prepare_enable(hws[IMX7D_UART2_ROOT_CLK]->clk); + } + /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ clk_set_parent(hws[IMX7D_GPT1_ROOT_SRC]->clk, hws[IMX7D_OSC_24M_CLK]->clk); @@ -882,7 +891,9 @@ hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1); hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1); - imx_register_uart_clocks(7); + /* set parent of EPDC pixel clock */ + clk_set_parent(hws[IMX7D_EPDC_PIXEL_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_MAIN_CLK]->clk); + imx_register_uart_clocks(7); } CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8dxl-acm.c linux-imx-phytec/drivers/clk/imx/clk-imx8dxl-acm.c --- linux-6.1.55/drivers/clk/imx/clk-imx8dxl-acm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8dxl-acm.c 2024-06-19 12:33:59.556214044 +0200 @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-scu.h" +#include "clk-imx-acm-utils.h" + +#include + +struct imx8dxl_acm_priv { + struct clk_imx_acm_pm_domains dev_pm; + void __iomem *reg; + u32 regs[0x20]; +}; + +static const char *aud_clk_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "dummy", + "dummy", + "dummy", + "dummy", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", +}; + +static const char *mclk_out_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "dummy", + "dummy", + "spdif0_rx", + "dummy", + "dummy", + "dummy", +}; + +static const char *sai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *spdif_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *mqs_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static int imx8dxl_acm_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk_onecell_data *clk_data; + struct imx8dxl_acm_priv *priv; + struct resource *res; + struct clk **clks; + void __iomem *base; + int ret; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap(dev, res->start, resource_size(res)); + if (!base) + return -ENOMEM; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->reg = base; + + platform_set_drvdata(pdev, priv); + + clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->clks = devm_kcalloc(&pdev->dev, IMX_ADMA_ACM_CLK_END, + sizeof(*clk_data->clks), GFP_KERNEL); + if (!clk_data->clks) + return -ENOMEM; + + clk_data->clk_num = IMX_ADMA_ACM_CLK_END; + + clks = clk_data->clks; + + ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm); + if (ret) + return ret; + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + clks[IMX_ADMA_EXT_AUD_MCLK0] = imx_clk_fixed("ext_aud_mclk0", 0); + clks[IMX_ADMA_EXT_AUD_MCLK1] = imx_clk_fixed("ext_aud_mclk1", 0); + clks[IMX_ADMA_SPDIF0_RX] = imx_clk_fixed("spdif0_rx", 0); + clks[IMX_ADMA_SAI0_RX_BCLK] = imx_clk_fixed("sai0_rx_bclk", 0); + clks[IMX_ADMA_SAI0_TX_BCLK] = imx_clk_fixed("sai0_tx_bclk", 0); + clks[IMX_ADMA_SAI1_RX_BCLK] = imx_clk_fixed("sai1_rx_bclk", 0); + clks[IMX_ADMA_SAI1_TX_BCLK] = imx_clk_fixed("sai1_tx_bclk", 0); + clks[IMX_ADMA_SAI2_RX_BCLK] = imx_clk_fixed("sai2_rx_bclk", 0); + clks[IMX_ADMA_SAI3_RX_BCLK] = imx_clk_fixed("sai3_rx_bclk", 0); + + clks[IMX_ADMA_ACM_AUD_CLK0_SEL] = imx_dev_clk_mux(dev, "acm_aud_clk0_sel", base+0x000000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + clks[IMX_ADMA_ACM_AUD_CLK1_SEL] = imx_dev_clk_mux(dev, "acm_aud_clk1_sel", base+0x010000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + + clks[IMX_ADMA_ACM_MCLKOUT0_SEL] = imx_dev_clk_mux(dev, "acm_mclkout0_sel", base+0x020000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + clks[IMX_ADMA_ACM_MCLKOUT1_SEL] = imx_dev_clk_mux(dev, "acm_mclkout1_sel", base+0x030000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + + clks[IMX_ADMA_ACM_SAI0_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai0_mclk_sel", base+0x0E0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI1_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai1_mclk_sel", base+0x0F0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI2_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai2_mclk_sel", base+0x100000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI3_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai3_mclk_sel", base+0x110000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + + clks[IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_spdif0_mclk_sel", base+0x1A0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels)); + clks[IMX_ADMA_ACM_MQS_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_mqs_mclk_sel", base+0x1C0000, 0, 2, mqs_mclk_sels, ARRAY_SIZE(mqs_mclk_sels)); + + for (i = 0; i < clk_data->clk_num; i++) { + if (IS_ERR(clks[i])) + pr_warn("i.MX clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); + } + + ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); + + pm_runtime_put_sync(&pdev->dev); + + return ret; +} + +static int imx8dxl_acm_clk_remove(struct platform_device *pdev) +{ + struct imx8dxl_acm_priv *priv = dev_get_drvdata(&pdev->dev); + + pm_runtime_disable(&pdev->dev); + + clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm); + + return 0; +} + +static const struct of_device_id imx8dxl_acm_match[] = { + { .compatible = "nxp,imx8dxl-acm", }, + { /* sentinel */ } +}; + +static int __maybe_unused imx8dxl_acm_runtime_suspend(struct device *dev) +{ + struct imx8dxl_acm_priv *priv = dev_get_drvdata(dev); + + priv->regs[0] = readl_relaxed(priv->reg + 0x000000); + priv->regs[1] = readl_relaxed(priv->reg + 0x010000); + priv->regs[2] = readl_relaxed(priv->reg + 0x020000); + priv->regs[3] = readl_relaxed(priv->reg + 0x030000); + priv->regs[14] = readl_relaxed(priv->reg + 0x0E0000); + priv->regs[15] = readl_relaxed(priv->reg + 0x0F0000); + priv->regs[16] = readl_relaxed(priv->reg + 0x100000); + priv->regs[17] = readl_relaxed(priv->reg + 0x110000); + priv->regs[26] = readl_relaxed(priv->reg + 0x1A0000); + priv->regs[28] = readl_relaxed(priv->reg + 0x1C0000); + + return 0; +} + +static int __maybe_unused imx8dxl_acm_runtime_resume(struct device *dev) +{ + struct imx8dxl_acm_priv *priv = dev_get_drvdata(dev); + + writel_relaxed(priv->regs[0], priv->reg + 0x000000); + writel_relaxed(priv->regs[1], priv->reg + 0x010000); + writel_relaxed(priv->regs[2], priv->reg + 0x020000); + writel_relaxed(priv->regs[3], priv->reg + 0x030000); + writel_relaxed(priv->regs[14], priv->reg + 0x0E0000); + writel_relaxed(priv->regs[15], priv->reg + 0x0F0000); + writel_relaxed(priv->regs[16], priv->reg + 0x100000); + writel_relaxed(priv->regs[17], priv->reg + 0x110000); + writel_relaxed(priv->regs[26], priv->reg + 0x1A0000); + writel_relaxed(priv->regs[28], priv->reg + 0x1C0000); + + return 0; +} + +const struct dev_pm_ops imx8dxl_acm_pm_ops = { + SET_RUNTIME_PM_OPS(imx8dxl_acm_runtime_suspend, + imx8dxl_acm_runtime_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver imx8dxl_acm_clk_driver = { + .driver = { + .name = "imx8dxl-acm", + .of_match_table = imx8dxl_acm_match, + .pm = &imx8dxl_acm_pm_ops, + .suppress_bind_attrs = true, + }, + .probe = imx8dxl_acm_clk_probe, + .remove = imx8dxl_acm_clk_remove, +}; + +static int __init imx8dxl_acm_init(void) +{ + return platform_driver_register(&imx8dxl_acm_clk_driver); +} +fs_initcall(imx8dxl_acm_init); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8dxl-rsrc.c linux-imx-phytec/drivers/clk/imx/clk-imx8dxl-rsrc.c --- linux-6.1.55/drivers/clk/imx/clk-imx8dxl-rsrc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8dxl-rsrc.c 2024-06-19 12:33:59.556214044 +0200 @@ -47,11 +47,10 @@ IMX_SC_R_SDHC_2, IMX_SC_R_ENET_0, IMX_SC_R_ENET_1, - IMX_SC_R_MLB_0, IMX_SC_R_USB_1, IMX_SC_R_NAND, - IMX_SC_R_M4_0_I2C, IMX_SC_R_M4_0_UART, + IMX_SC_R_M4_0_I2C, IMX_SC_R_ELCDIF_PLL, IMX_SC_R_AUDIO_PLL_0, IMX_SC_R_AUDIO_PLL_1, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8mm.c linux-imx-phytec/drivers/clk/imx/clk-imx8mm.c --- linux-6.1.55/drivers/clk/imx/clk-imx8mm.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8mm.c 2024-06-19 12:33:59.556214044 +0200 @@ -4,7 +4,9 @@ */ #include +#include #include +#include #include #include #include @@ -296,6 +298,34 @@ static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws; +static int imx_clk_init_on(struct device_node *np, + struct clk_hw * const clks[]) +{ + u32 *array; + int i, ret, elems; + + elems = of_property_count_u32_elems(np, "init-on-array"); + if (elems < 0) + return elems; + array = kcalloc(elems, sizeof(elems), GFP_KERNEL); + if (!array) + return -ENOMEM; + + ret = of_property_read_u32_array(np, "init-on-array", array, elems); + if (ret) + return ret; + + for (i = 0; i < elems; i++) { + ret = clk_prepare_enable(clks[array[i]]->clk); + if (ret) + pr_err("clk_prepare_enable failed %d\n", array[i]); + } + + kfree(array); + + return 0; +} + static int imx8mm_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -432,7 +462,7 @@ /* BUS */ hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800); hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mm_enet_axi_sels, base + 0x8880); - hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900); + hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900); hws[IMX8MM_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980); hws[IMX8MM_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00); hws[IMX8MM_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80); @@ -609,6 +639,12 @@ goto unregister_hws; } + imx_clk_init_on(np, hws); + + clk_set_parent(hws[IMX8MM_CLK_CSI1_CORE]->clk, hws[IMX8MM_SYS_PLL2_1000M]->clk); + clk_set_parent(hws[IMX8MM_CLK_CSI1_PHY_REF]->clk, hws[IMX8MM_SYS_PLL2_1000M]->clk); + clk_set_parent(hws[IMX8MM_CLK_CSI1_ESC]->clk, hws[IMX8MM_SYS_PLL1_800M]->clk); + imx_register_uart_clocks(4); return 0; @@ -641,6 +677,83 @@ module_param(mcore_booted, bool, S_IRUGO); MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not"); +/* + * Debugfs interface for audio PLL K divider change dynamically. + * Monitor control for the Audio PLL K-Divider + */ +#ifdef CONFIG_DEBUG_FS + +#define KDIV_MASK GENMASK(15, 0) +#define MDIV_SHIFT 12 +#define MDIV_MASK GENMASK(21, 12) +#define PDIV_SHIFT 4 +#define PDIV_MASK GENMASK(9, 4) +#define SDIV_SHIFT 0 +#define SDIV_MASK GENMASK(2, 0) + +static int pll_delta_k_set(void *data, u64 val) +{ + struct clk_hw *hw; + short int delta_k; + + hw = data; + delta_k = (short int) (val & KDIV_MASK); + + clk_set_delta_k(hw, val); + + pr_debug("the delta k is %d\n", delta_k); + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(delta_k_fops, NULL, pll_delta_k_set, "%lld\n"); + +static int pll_setting_show(struct seq_file *s, void *data) +{ + struct clk_hw *hw; + u32 pll_div_ctrl0, pll_div_ctrl1; + u32 mdiv, pdiv, sdiv, kdiv; + + hw = s->private;; + + clk_get_pll_setting(hw, &pll_div_ctrl0, &pll_div_ctrl1); + mdiv = (pll_div_ctrl0 & MDIV_MASK) >> MDIV_SHIFT; + pdiv = (pll_div_ctrl0 & PDIV_MASK) >> PDIV_SHIFT; + sdiv = (pll_div_ctrl0 & SDIV_MASK) >> SDIV_SHIFT; + kdiv = (pll_div_ctrl1 & KDIV_MASK); + + seq_printf(s, "Mdiv: 0x%x; Pdiv: 0x%x; Sdiv: 0x%x; Kdiv: 0x%x\n", + mdiv, pdiv, sdiv, kdiv); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pll_setting); + +#ifndef MODULE +static int __init pll_debug_init(void) +{ + struct dentry *root, *audio_pll1, *audio_pll2; + + if (of_machine_is_compatible("fsl,imx8mm") && hws) { + /* create a root dir for audio pll monitor */ + root = debugfs_create_dir("audio_pll_monitor", NULL); + audio_pll1 = debugfs_create_dir("audio_pll1", root); + audio_pll2 = debugfs_create_dir("audio_pll2", root); + + debugfs_create_file_unsafe("delta_k", 0444, audio_pll1, + hws[IMX8MM_AUDIO_PLL1], &delta_k_fops); + debugfs_create_file("pll_parameter", 0x444, audio_pll1, + hws[IMX8MM_AUDIO_PLL1], &pll_setting_fops); + debugfs_create_file_unsafe("delta_k", 0444, audio_pll2, + hws[IMX8MM_AUDIO_PLL2], &delta_k_fops); + debugfs_create_file("pll_parameter", 0x444, audio_pll2, + hws[IMX8MM_AUDIO_PLL2], &pll_setting_fops); + } + + return 0; +} +late_initcall(pll_debug_init); +#endif /* MODULE */ +#endif /* CONFIG_DEBUG_FS */ + MODULE_AUTHOR("Bai Ping "); MODULE_DESCRIPTION("NXP i.MX8MM clock driver"); MODULE_LICENSE("GPL v2"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8mn.c linux-imx-phytec/drivers/clk/imx/clk-imx8mn.c --- linux-6.1.55/drivers/clk/imx/clk-imx8mn.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8mn.c 2024-06-19 12:33:59.556214044 +0200 @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -316,6 +317,34 @@ static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws; +static int imx_clk_init_on(struct device_node *np, + struct clk_hw * const clks[]) +{ + u32 *array; + int i, ret, elems; + + elems = of_property_count_u32_elems(np, "init-on-array"); + if (elems < 0) + return elems; + array = kcalloc(elems, sizeof(elems), GFP_KERNEL); + if (!array) + return -ENOMEM; + + ret = of_property_read_u32_array(np, "init-on-array", array, elems); + if (ret) + return ret; + + for (i = 0; i < elems; i++) { + ret = clk_prepare_enable(clks[array[i]]->clk); + if (ret) + pr_err("clk_prepare_enable failed %d\n", array[i]); + } + + kfree(array); + + return 0; +} + static int imx8mn_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -583,6 +612,7 @@ hws[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0); hws[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0); hws[IMX8MN_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7); + hws[IMX8MN_CLK_SAI7_IPG] = imx_clk_hw_gate2_shared2("sai7_ipg_clk", "ipg_audio_root", base + 0x4650, 0, &share_count_sai7); hws[IMX8MN_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc_24m", 1, 8); @@ -602,6 +632,12 @@ goto unregister_hws; } + imx_clk_init_on(np, hws); + + clk_set_parent(hws[IMX8MN_CLK_AUDIO_AHB]->clk, hws[IMX8MN_SYS_PLL1_800M]->clk); + clk_set_rate(hws[IMX8MN_CLK_AUDIO_AHB]->clk, 400000000); + clk_set_rate(hws[IMX8MN_CLK_IPG_AUDIO_ROOT]->clk, 400000000); + imx_register_uart_clocks(4); return 0; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8mp.c linux-imx-phytec/drivers/clk/imx/clk-imx8mp.c --- linux-6.1.55/drivers/clk/imx/clk-imx8mp.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8mp.c 2024-06-19 12:33:59.556214044 +0200 @@ -4,7 +4,10 @@ */ #include +#include +#include #include +#include #include #include #include @@ -14,11 +17,288 @@ #include #include "clk.h" +#include "clk-blk-ctrl.h" + +#define IMX_AUDIO_BLK_CTRL_CLKEN0 0x0 +#define IMX_AUDIO_BLK_CTRL_CLKEN1 0x4 +#define IMX_AUDIO_BLK_CTRL_EARC 0x200 +#define IMX_AUDIO_BLK_CTRL_SAI1_MCLK_SEL 0x300 +#define IMX_AUDIO_BLK_CTRL_SAI2_MCLK_SEL 0x304 +#define IMX_AUDIO_BLK_CTRL_SAI3_MCLK_SEL 0x308 +#define IMX_AUDIO_BLK_CTRL_SAI5_MCLK_SEL 0x30C +#define IMX_AUDIO_BLK_CTRL_SAI6_MCLK_SEL 0x310 +#define IMX_AUDIO_BLK_CTRL_SAI7_MCLK_SEL 0x314 +#define IMX_AUDIO_BLK_CTRL_PDM_CLK 0x318 +#define IMX_AUDIO_BLK_CTRL_SAI_PLL_GNRL_CTL 0x400 +#define IMX_AUDIO_BLK_CTRL_SAI_PLL_FDIVL_CTL0 0x404 +#define IMX_AUDIO_BLK_CTRL_SAI_PLL_FDIVL_CTL1 0x408 +#define IMX_AUDIO_BLK_CTRL_SAI_PLL_SSCG_CTL 0x40C +#define IMX_AUDIO_BLK_CTRL_SAI_PLL_MNIT_CTL 0x410 +#define IMX_AUDIO_BLK_CTRL_IPG_LP_CTRL 0x504 + +#define IMX_MEDIA_BLK_CTRL_SFT_RSTN 0x0 +#define IMX_MEDIA_BLK_CTRL_CLK_EN 0x4 static u32 share_count_nand; static u32 share_count_media; +static u32 share_count_audio; static u32 share_count_usb; +static int shared_count_pdm; + +/* descending order */ +static const struct imx_pll14xx_rate_table imx_blk_ctrl_sai_pll_tbl[] = { + PLL_1443X_RATE(245760000U, 328, 4, 3, 0xae15), + PLL_1443X_RATE(225792000U, 226, 3, 3, 0xcac1), + PLL_1443X_RATE(122880000U, 328, 4, 4, 0xae15), + PLL_1443X_RATE(112896000U, 226, 3, 4, 0xcac1), + PLL_1443X_RATE(61440000U, 328, 4, 5, 0xae15), + PLL_1443X_RATE(56448000U, 226, 3, 5, 0xcac1), + PLL_1443X_RATE(49152000U, 393, 3, 6, 0x374c), + PLL_1443X_RATE(45158400U, 241, 2, 6, 0xd845), + PLL_1443X_RATE(40960000U, 109, 1, 6, 0x3a07), +}; + +static const struct imx_pll14xx_clk imx_blk_ctrl_sai_pll = { + .type = PLL_1443X, + .rate_table = imx_blk_ctrl_sai_pll_tbl, + .rate_count = ARRAY_SIZE(imx_blk_ctrl_sai_pll_tbl), +}; + +static const char *imx_sai_mclk2_sels[] = {"sai1_root", "sai2_root", "sai3_root", "dummy", + "sai5_root", "sai6_root", "sai7_root", "sai1_mclk", + "sai2_mclk", "sai3_mclk", "dummy", + "sai5_mclk", "sai6_mclk", "sai7_mclk", "spdif1_ext_clk"}; +static const char *imx_sai1_mclk1_sels[] = {"sai1_root", "sai1_mclk", }; +static const char *imx_sai2_mclk1_sels[] = {"sai2_root", "sai2_mclk", }; +static const char *imx_sai3_mclk1_sels[] = {"sai3_root", "sai3_mclk", }; +static const char *imx_sai5_mclk1_sels[] = {"sai5_root", "sai5_mclk", }; +static const char *imx_sai6_mclk1_sels[] = {"sai6_root", "sai6_mclk", }; +static const char *imx_sai7_mclk1_sels[] = {"sai7_root", "sai7_mclk", }; +static const char *imx_pdm_sels[] = {"pdm_root", "sai_pll_div2", "dummy", "dummy" }; +static const char *imx_sai_pll_ref_sels[] = {"osc_24m", "dummy", "dummy", "dummy", }; +static const char *imx_sai_pll_bypass_sels[] = {"sai_pll", "sai_pll_ref_sel", }; + +static const char *imx_hdmi_phy_clks_sels[] = { "hdmi_glb_24m", "dummy",}; +static const char *imx_lcdif_clks_sels[] = { "dummy", "hdmi_glb_pix", }; +static const char *imx_hdmi_pipe_clks_sels[] = {"dummy","hdmi_glb_pix", }; + +static struct imx_blk_ctrl_hw imx8mp_hdmi_blk_ctrl_hws[] = { + /* clocks */ + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_apb", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_APB_CLK, 0x40, 0, "hdmi_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_b", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_B_CLK, 0x40, 1, "hdmi_axi"), + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_ref_266m", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_REF266M_CLK, 0x40, 2, "hdmi_ref_266m"), + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_24m", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL24M_CLK, 0x40, 4, "hdmi_24m"), + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_32k", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL32K_CLK, 0x40, 5, "osc_32k"), + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_pix", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_TX_PIX_CLK, 0x40, 7, "hdmi_phy"), + IMX_BLK_CTRL_CLK_GATE("hdmi_irq_steer", IMX8MP_CLK_HDMI_BLK_CTRL_IRQS_STEER_CLK, 0x40, 9, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_noc", IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDMI_CLK, 0x40, 10, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdcp_noc", IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDCP_CLK, 0x40, 11, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("lcdif3_apb", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_APB_CLK, 0x40, 16, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("lcdif3_b", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_B_CLK, 0x40, 17, "hdmi_glb_b"), + IMX_BLK_CTRL_CLK_GATE("lcdif3_pdi", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PDI_CLK, 0x40, 18, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("lcdif3_pxl", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PIX_CLK, 0x40, 19, "hdmi_glb_pix"), + IMX_BLK_CTRL_CLK_GATE("lcdif3_spu", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_SPU_CLK, 0x40, 20, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_fdcc_ref", IMX8MP_CLK_HDMI_BLK_CTRL_FDCC_REF_CLK, 0x50, 2, "hdmi_fdcc_tst"), + IMX_BLK_CTRL_CLK_GATE("hrv_mwr_apb", IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_APB_CLK, 0x50, 3, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hrv_mwr_b", IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_B_CLK, 0x50, 4, "hdmi_glb_axi"), + IMX_BLK_CTRL_CLK_GATE("hrv_mwr_cea", IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_CEA_CLK, 0x50, 5, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("vsfd_cea", IMX8MP_CLK_HDMI_BLK_CTRL_VSFD_CEA_CLK, 0x50, 6, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_hpi", IMX8MP_CLK_HDMI_BLK_CTRL_TX_HPI_CLK, 0x50, 13, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_apb", IMX8MP_CLK_HDMI_BLK_CTRL_TX_APB_CLK, 0x50, 14, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_cec", IMX8MP_CLK_HDMI_BLK_CTRL_TX_CEC_CLK, 0x50, 15, "hdmi_glb_32k"), + IMX_BLK_CTRL_CLK_GATE("hdmi_esm", IMX8MP_CLK_HDMI_BLK_CTRL_TX_ESM_CLK, 0x50, 16, "hdmi_glb_ref_266m"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_gpa", IMX8MP_CLK_HDMI_BLK_CTRL_TX_GPA_CLK, 0x50, 17, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_pix", IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIXEL_CLK, 0x50, 18, "hdmi_glb_pix"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_sfr", IMX8MP_CLK_HDMI_BLK_CTRL_TX_SFR_CLK, 0x50, 19, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_skp", IMX8MP_CLK_HDMI_BLK_CTRL_TX_SKP_CLK, 0x50, 20, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_prep", IMX8MP_CLK_HDMI_BLK_CTRL_TX_PREP_CLK, 0x50, 21, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_phy_apb", IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_APB_CLK, 0x50, 22, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_phy_int", IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_INT_CLK, 0x50, 24, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_sec_mem", IMX8MP_CLK_HDMI_BLK_CTRL_TX_SEC_MEM_CLK, 0x50, 25, "hdmi_glb_ref_266m"), + IMX_BLK_CTRL_CLK_GATE("hdmi_trng_skp", IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_SKP_CLK, 0x50, 27, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_vid_pix", IMX8MP_CLK_HDMI_BLK_CTRL_TX_VID_LINK_PIX_CLK, 0x50, 28, "hdmi_glb_pix"), + IMX_BLK_CTRL_CLK_GATE("hdmi_trng_apb", IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_APB_CLK, 0x50, 30, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_MUX("hdmi_phy_sel", IMX8MP_CLK_HDMI_BLK_CTRL_HTXPHY_CLK_SEL, 0x50, 10, 1, imx_hdmi_phy_clks_sels), + IMX_BLK_CTRL_CLK_MUX("lcdif_clk_sel", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_CLK_SEL, 0x50, 11, 1, imx_lcdif_clks_sels), + IMX_BLK_CTRL_CLK_MUX("hdmi_pipe_sel", IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIPE_CLK_SEL, 0x50, 12, 1, imx_hdmi_pipe_clks_sels), + + /* resets */ + IMX_BLK_CTRL_RESET_MASK(IMX8MP_HDMI_BLK_CTRL_HDMI_TX_RESET, 0x20, 6, 0x33), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_HDMI_PHY_RESET, 0x20, 12), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_HDMI_PAI_RESET, 0x20, 18), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_HDMI_PVI_RESET, 0x20, 22), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_HDMI_TRNG_RESET, 0x20, 20), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_IRQ_STEER_RESET, 0x20, 16), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_HDMI_HDCP_RESET, 0x20, 13), + IMX_BLK_CTRL_RESET_MASK(IMX8MP_HDMI_BLK_CTRL_LCDIF_RESET, 0x20, 4, 0x3), +}; + +static struct imx_blk_ctrl_hw imx8mp_media_blk_ctrl_hws[] = { + /* clocks */ + IMX_BLK_CTRL_CLK_GATE("mipi_dsi_pclk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK, 0x4, 0, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("mipi_dsi_clkref", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF, 0x4, 1, "media_mipi_phy1_ref"), + IMX_BLK_CTRL_CLK_GATE("mipi_csi_pclk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_PCLK, 0x4, 2, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("mipi_csi_aclk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_ACLK, 0x4, 3, "media_cam1_pix_root_clk"), + IMX_BLK_CTRL_CLK_GATE("lcdif_pixel_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_PIXEL, 0x4, 4, "media_disp1_pix_root_clk"), + IMX_BLK_CTRL_CLK_GATE("lcdif_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_APB, 0x4, 5, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isi_proc_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_PROC, 0x4, 6, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isi_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_APB, 0x4, 7, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("mipi_csi2_pclk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_PCLK, 0x4, 9, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("mipi_csi2_aclk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_ACLK, 0x4, 10, "media_cam2_pix_root_clk"), + IMX_BLK_CTRL_CLK_GATE("lcdif2_pixel_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_PIXEL, 0x4, 11, "media_disp2_pix_root_clk"), + IMX_BLK_CTRL_CLK_GATE("lcdif2_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_APB, 0x4, 12, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isp_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_COR, 0x4, 16, "media_isp_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isp_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AXI, 0x4, 17, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isp_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP_AHB, 0x4, 18, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("dwe_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_COR, 0x4, 19, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("dwe_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AXI, 0x4, 20, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("dwe_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AHB, 0x4, 21, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("mipi_dsi2_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI2, 0x4, 22, "media_mipi_phy1_ref"), + IMX_BLK_CTRL_CLK_GATE("lcdif_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_AXI, 0x4, 23, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("lcdif2_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_AXI, 0x4, 24, "media_axi_root_clk"), + + /* resets */ + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_PCLK, 0, 0), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_CLKREF, 0, 1), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_PCLK, 0, 2), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_ACLK, 0, 3), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_PIXEL, 0, 4), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_APB, 0, 5), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_PROC, 0, 6), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_APB, 0, 7), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_BUS_BLK, 0, 8), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_PCLK, 0, 9), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_ACLK, 0, 10), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_PIXEL, 0, 11), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_APB, 0, 12), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_COR, 0, 13), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AXI, 0, 14), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AHB, 0, 15), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_COR, 0, 16), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AXI, 0, 17), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AHB, 0, 18), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_COR, 0, 19), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AXI, 0, 20), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AHB, 0, 21), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI2, 0, 22), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_AXI, 0, 23), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_AXI, 0, 24) +}; + +static struct imx_blk_ctrl_hw imx8mp_audio_blk_ctrl_hws[] = { + /* clocks */ + IMX_BLK_CTRL_CLK_MUX("sai_pll_ref_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_REF_SEL, 0x400, 0, 2, imx_sai_pll_ref_sels), + IMX_BLK_CTRL_CLK_PLL14XX("sai_pll", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL, 0x400, "sai_pll_ref_sel", &imx_blk_ctrl_sai_pll), + IMX_BLK_CTRL_CLK_MUX_FLAGS("sai_pll_bypass", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_BYPASS, 0x400, 4, 1, imx_sai_pll_bypass_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTRL_CLK_GATE("sai_pll_out", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_OUT, 0x400, 13, "sai_pll_bypass"), + IMX_BLK_CTRL_CLK_MUX_FLAGS("sai1_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1_SEL, 0x300, 0, 1, imx_sai1_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTRL_CLK_MUX("sai1_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2_SEL, 0x300, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_MUX_FLAGS("sai2_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1_SEL, 0x304, 0, 1, imx_sai2_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTRL_CLK_MUX("sai2_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2_SEL, 0x304, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_MUX_FLAGS("sai3_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1_SEL, 0x308, 0, 1, imx_sai3_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTRL_CLK_MUX("sai3_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2_SEL, 0x308, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_MUX("sai5_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1_SEL, 0x30C, 0, 1, imx_sai5_mclk1_sels), + IMX_BLK_CTRL_CLK_MUX("sai5_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2_SEL, 0x30C, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_MUX("sai6_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1_SEL, 0x310, 0, 1, imx_sai6_mclk1_sels), + IMX_BLK_CTRL_CLK_MUX("sai6_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2_SEL, 0x310, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_MUX("sai7_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1_SEL, 0x314, 0, 1, imx_sai7_mclk1_sels), + IMX_BLK_CTRL_CLK_MUX("sai7_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2_SEL, 0x314, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_MUX_FLAGS("pdm_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_SEL, 0x318, 0, 2, imx_pdm_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTRL_CLK_GATE("sai1_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG, 0, 0, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai1_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1, 0, 1, "sai1_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai1_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2, 0, 2, "sai1_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai1_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK3, 0, 3, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("sai2_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_IPG, 0, 4, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai2_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1, 0, 5, "sai2_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai2_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2, 0, 6, "sai2_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai2_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK3, 0, 7, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("sai3_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG, 0, 8, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai3_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1, 0, 9, "sai3_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai3_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2, 0, 10, "sai3_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai3_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK3, 0, 11, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("sai5_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG, 0, 12, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai5_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1, 0, 13, "sai5_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai5_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2, 0, 14, "sai5_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai5_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK3, 0, 15, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("sai6_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_IPG, 0, 16, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai6_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1, 0, 17, "sai6_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai6_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2, 0, 18, "sai6_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai6_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK3, 0, 19, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("sai7_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_IPG, 0, 20, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai7_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1, 0, 21, "sai7_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai7_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2, 0, 22, "sai7_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai7_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK3, 0, 23, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("asrc_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_ASRC_IPG, 0, 24, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_SHARED_GATE("pdm_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG, 0, 25, "audio_ahb_root", &shared_count_pdm), + IMX_BLK_CTRL_CLK_SHARED_GATE("pdm_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT, 0, 25, "pdm_sel", &shared_count_pdm), + IMX_BLK_CTRL_CLK_GATE("sdma3_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT, 0, 27, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("spba2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SPBA2_ROOT, 0, 28, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("dsp_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT, 0, 29, "audio_axi_root"), + IMX_BLK_CTRL_CLK_GATE("dsp_dbg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT, 0, 30, "audio_axi_root"), + IMX_BLK_CTRL_CLK_GATE("earc_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_IPG, 0, 31, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("ocram_a_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG, 4, 0, "audio_axi_root"), + IMX_BLK_CTRL_CLK_GATE("aud2htx_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_AUD2HTX_IPG, 4, 1, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("edma_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_EDMA_ROOT, 4, 2, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("aud_pll_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT, 4, 3, "osc_24m"), + IMX_BLK_CTRL_CLK_GATE("mu2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_MU2_ROOT, 4, 4, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("mu3_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_MU3_ROOT, 4, 5, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("earc_phy_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_PHY, 4, 6, "sai_pll_out"), + + /* resets */ + IMX_BLK_CTRL_RESET(IMX8MP_AUDIO_BLK_CTRL_EARC_RESET, 0x200, 0), + IMX_BLK_CTRL_RESET(IMX8MP_AUDIO_BLK_CTRL_EARC_PHY_RESET, 0x200, 1), +}; + +const struct imx_blk_ctrl_dev_data imx8mp_hdmi_blk_ctrl_dev_data = { + .hws = imx8mp_hdmi_blk_ctrl_hws, + .hws_num = ARRAY_SIZE(imx8mp_hdmi_blk_ctrl_hws), + .clocks_max = IMX8MP_CLK_HDMI_BLK_CTRL_END, + .resets_max = IMX8MP_HDMI_BLK_CTRL_RESET_NUM, + .pm_runtime_saved_regs_num = 0 +}; +EXPORT_SYMBOL_GPL(imx8mp_hdmi_blk_ctrl_dev_data); + +const struct imx_blk_ctrl_dev_data imx8mp_media_blk_ctrl_dev_data = { + .hws = imx8mp_media_blk_ctrl_hws, + .hws_num = ARRAY_SIZE(imx8mp_media_blk_ctrl_hws), + .clocks_max = IMX8MP_CLK_MEDIA_BLK_CTRL_END, + .resets_max = IMX8MP_MEDIA_BLK_CTRL_RESET_NUM, + .pm_runtime_saved_regs_num = 2, + .pm_runtime_saved_regs = { + IMX_MEDIA_BLK_CTRL_SFT_RSTN, + IMX_MEDIA_BLK_CTRL_CLK_EN, + }, +}; +EXPORT_SYMBOL_GPL(imx8mp_media_blk_ctrl_dev_data); + +const struct imx_blk_ctrl_dev_data imx8mp_audio_blk_ctrl_dev_data = { + .hws = imx8mp_audio_blk_ctrl_hws, + .hws_num = ARRAY_SIZE(imx8mp_audio_blk_ctrl_hws), + .clocks_max = IMX8MP_CLK_AUDIO_BLK_CTRL_END, + .resets_max = IMX8MP_AUDIO_BLK_CTRL_RESET_NUM, + .pm_runtime_saved_regs_num = 16, + .pm_runtime_saved_regs = { + IMX_AUDIO_BLK_CTRL_CLKEN0, + IMX_AUDIO_BLK_CTRL_CLKEN1, + IMX_AUDIO_BLK_CTRL_EARC, + IMX_AUDIO_BLK_CTRL_SAI1_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_SAI2_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_SAI3_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_SAI5_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_SAI6_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_SAI7_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_PDM_CLK, + IMX_AUDIO_BLK_CTRL_SAI_PLL_GNRL_CTL, + IMX_AUDIO_BLK_CTRL_SAI_PLL_FDIVL_CTL0, + IMX_AUDIO_BLK_CTRL_SAI_PLL_FDIVL_CTL1, + IMX_AUDIO_BLK_CTRL_SAI_PLL_SSCG_CTL, + IMX_AUDIO_BLK_CTRL_SAI_PLL_MNIT_CTL, + IMX_AUDIO_BLK_CTRL_IPG_LP_CTRL + }, +}; +EXPORT_SYMBOL_GPL(imx8mp_audio_blk_ctrl_dev_data); + static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; @@ -404,6 +684,34 @@ static struct clk_hw **hws; static struct clk_hw_onecell_data *clk_hw_data; +static int imx_clk_init_on(struct device_node *np, + struct clk_hw * const clks[]) +{ + u32 *array; + int i, ret, elems; + + elems = of_property_count_u32_elems(np, "init-on-array"); + if (elems < 0) + return elems; + array = kcalloc(elems, sizeof(elems), GFP_KERNEL); + if (!array) + return -ENOMEM; + + ret = of_property_read_u32_array(np, "init-on-array", array, elems); + if (ret) + return ret; + + for (i = 0; i < elems; i++) { + ret = clk_prepare_enable(clks[array[i]]->clk); + if (ret) + pr_err("clk_prepare_enable failed %d\n", array[i]); + } + + kfree(array); + + return 0; +} + static int imx8mp_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -530,7 +838,7 @@ hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800); hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880); - hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900); + hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900); hws[IMX8MP_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_vpu_bus_sels, ccm_base + 0x8980); hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite_bus("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00); hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite_bus("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80); @@ -546,7 +854,7 @@ hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000); hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100); hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200); - hws[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_hw_composite("media_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300); + hws[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_hw_composite_bus("media_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300); hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1); @@ -687,13 +995,22 @@ hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media); hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media); hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT] = imx_clk_hw_gate2_shared2("media_mipi_phy1_ref_root", "media_mipi_phy1_ref", ccm_base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_LDB_ROOT] = imx_clk_hw_gate2_shared2("media_ldb_root_clk", "media_ldb", ccm_base + 0x45d0, 0, &share_count_media); hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media); hws[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0); hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0); hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0); hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0); - hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "audio_ahb", ccm_base + 0x4650, 0); + hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", ccm_base + 0x4650, 0, &share_count_audio); hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", hws[IMX8MP_CLK_A53_CORE]->clk, @@ -710,6 +1027,8 @@ return err; } + imx_clk_init_on(np, hws); + imx_register_uart_clocks(4); return 0; @@ -740,3 +1059,80 @@ MODULE_AUTHOR("Anson Huang "); MODULE_DESCRIPTION("NXP i.MX8MP clock driver"); MODULE_LICENSE("GPL v2"); + +#ifndef MODULE +/* + * Debugfs interface for audio PLL K divider change dynamically. + * Monitor control for the Audio PLL K-Divider + */ +#ifdef CONFIG_DEBUG_FS + +#define KDIV_MASK GENMASK(15, 0) +#define MDIV_SHIFT 12 +#define MDIV_MASK GENMASK(21, 12) +#define PDIV_SHIFT 4 +#define PDIV_MASK GENMASK(9, 4) +#define SDIV_SHIFT 0 +#define SDIV_MASK GENMASK(2, 0) + +static int pll_delta_k_set(void *data, u64 val) +{ + struct clk_hw *hw; + short int delta_k; + + hw = data; + delta_k = (short int) (val & KDIV_MASK); + + clk_set_delta_k(hw, val); + + pr_debug("the delta k is %d\n", delta_k); + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(delta_k_fops, NULL, pll_delta_k_set, "%lld\n"); + +static int pll_setting_show(struct seq_file *s, void *data) +{ + struct clk_hw *hw; + u32 pll_div_ctrl0, pll_div_ctrl1; + u32 mdiv, pdiv, sdiv, kdiv; + + hw = s->private; + + clk_get_pll_setting(hw, &pll_div_ctrl0, &pll_div_ctrl1); + mdiv = (pll_div_ctrl0 & MDIV_MASK) >> MDIV_SHIFT; + pdiv = (pll_div_ctrl0 & PDIV_MASK) >> PDIV_SHIFT; + sdiv = (pll_div_ctrl0 & SDIV_MASK) >> SDIV_SHIFT; + kdiv = (pll_div_ctrl1 & KDIV_MASK); + + seq_printf(s, "Mdiv: 0x%x; Pdiv: 0x%x; Sdiv: 0x%x; Kdiv: 0x%x\n", + mdiv, pdiv, sdiv, kdiv); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pll_setting); + +static int __init pll_debug_init(void) +{ + struct dentry *root, *audio_pll1, *audio_pll2; + + if (of_machine_is_compatible("fsl,imx8mp") && hws) { + /* create a root dir for audio pll monitor */ + root = debugfs_create_dir("audio_pll_monitor", NULL); + audio_pll1 = debugfs_create_dir("audio_pll1", root); + audio_pll2 = debugfs_create_dir("audio_pll2", root); + + debugfs_create_file_unsafe("delta_k", 0444, audio_pll1, + hws[IMX8MP_AUDIO_PLL1], &delta_k_fops); + debugfs_create_file("pll_parameter", 0x444, audio_pll1, + hws[IMX8MP_AUDIO_PLL1], &pll_setting_fops); + debugfs_create_file_unsafe("delta_k", 0444, audio_pll2, + hws[IMX8MP_AUDIO_PLL2], &delta_k_fops); + debugfs_create_file("pll_parameter", 0x444, audio_pll2, + hws[IMX8MP_AUDIO_PLL2], &pll_setting_fops); + } + + return 0; +} +late_initcall(pll_debug_init); +#endif /* CONFIG_DEBUG_FS */ +#endif /* MODULE */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8mq.c linux-imx-phytec/drivers/clk/imx/clk-imx8mq.c --- linux-6.1.55/drivers/clk/imx/clk-imx8mq.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8mq.c 2024-06-19 12:33:59.556214044 +0200 @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -13,6 +14,7 @@ #include #include #include +#include #include "clk.h" @@ -281,6 +283,34 @@ static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws; +static int imx_clk_init_on(struct device_node *np, + struct clk_hw * const clks[]) +{ + u32 *array; + int i, ret, elems; + + elems = of_property_count_u32_elems(np, "init-on-array"); + if (elems < 0) + return elems; + array = kzalloc(elems * sizeof(elems), GFP_KERNEL); + if (!array) + return -ENOMEM; + + ret = of_property_read_u32_array(np, "init-on-array", array, elems); + if (ret) + return ret; + + for (i = 0; i < elems; i++) { + ret = clk_prepare_enable(clks[array[i]]->clk); + if (ret) + pr_err("clk_prepare_enable failed %d\n", array[i]); + } + + kfree(array); + + return 0; +} + static int imx8mq_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -343,6 +373,13 @@ hws[IMX8MQ_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux("audio_pll2_bypass", base + 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels)); hws[IMX8MQ_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux("video_pll1_bypass", base + 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels)); + /* unbypass all the plls */ + clk_set_parent(hws[IMX8MQ_GPU_PLL_BYPASS]->clk, hws[IMX8MQ_GPU_PLL]->clk); + clk_set_parent(hws[IMX8MQ_VPU_PLL_BYPASS]->clk, hws[IMX8MQ_VPU_PLL]->clk); + clk_set_parent(hws[IMX8MQ_AUDIO_PLL1_BYPASS]->clk, hws[IMX8MQ_AUDIO_PLL1]->clk); + clk_set_parent(hws[IMX8MQ_AUDIO_PLL2_BYPASS]->clk, hws[IMX8MQ_AUDIO_PLL2]->clk); + clk_set_parent(hws[IMX8MQ_VIDEO_PLL1_BYPASS]->clk, hws[IMX8MQ_VIDEO_PLL1]->clk); + /* PLL OUT GATE */ hws[IMX8MQ_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x28, 21); hws[IMX8MQ_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x18, 21); @@ -601,6 +638,16 @@ goto unregister_hws; } + /* enable all the clocks just for bringup */ + imx_clk_init_on(np, hws); + + clk_set_parent(hws[IMX8MQ_CLK_CSI1_CORE]->clk, hws[IMX8MQ_SYS1_PLL_266M]->clk); + clk_set_parent(hws[IMX8MQ_CLK_CSI1_PHY_REF]->clk, hws[IMX8MQ_SYS2_PLL_1000M]->clk); + clk_set_parent(hws[IMX8MQ_CLK_CSI1_ESC]->clk, hws[IMX8MQ_SYS1_PLL_800M]->clk); + clk_set_parent(hws[IMX8MQ_CLK_CSI2_CORE]->clk, hws[IMX8MQ_SYS1_PLL_266M]->clk); + clk_set_parent(hws[IMX8MQ_CLK_CSI2_PHY_REF]->clk, hws[IMX8MQ_SYS2_PLL_1000M]->clk); + clk_set_parent(hws[IMX8MQ_CLK_CSI2_ESC]->clk, hws[IMX8MQ_SYS1_PLL_800M]->clk); + imx_register_uart_clocks(4); return 0; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8qm-acm.c linux-imx-phytec/drivers/clk/imx/clk-imx8qm-acm.c --- linux-6.1.55/drivers/clk/imx/clk-imx8qm-acm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8qm-acm.c 2024-06-19 12:33:59.556214044 +0200 @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-scu.h" +#include "clk-imx-acm-utils.h" + +#include + +struct imx8qm_acm_priv { + struct clk_imx_acm_pm_domains dev_pm; + void __iomem *reg; + u32 regs[32]; +}; + +static const char *aud_clk_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "dummy", + "hdmi_rx_mclk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "esai1_rx_clk", + "esai1_rx_hf_clk", + "esai1_tx_clk", + "esai1_tx_hf_clk", + "spdif0_rx", + "spdif1_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", + "sai4_rx_bclk", +}; + +static const char *mclk_out_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "dummy", + "hdmi_rx_mclk", + "spdif0_rx", + "spdif1_rx", + "sai4_rx_bclk", + "sai6_rx_bclk", +}; + +static const char *sai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *asrc_mux_clk_sels[] = { + "sai4_rx_bclk", + "sai5_tx_bclk", + "dummy", + "dummy", +}; + +static const char *esai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *spdif_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *mqs_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static int imx8qm_acm_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk_onecell_data *clk_data; + struct imx8qm_acm_priv *priv; + struct resource *res; + struct clk **clks; + void __iomem *base; + int ret; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap(dev, res->start, resource_size(res)); + if (!base) + return -ENOMEM; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->reg = base; + + platform_set_drvdata(pdev, priv); + + clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->clks = devm_kcalloc(&pdev->dev, IMX_ADMA_ACM_CLK_END, + sizeof(*clk_data->clks), GFP_KERNEL); + if (!clk_data->clks) + return -ENOMEM; + + clk_data->clk_num = IMX_ADMA_ACM_CLK_END; + + clks = clk_data->clks; + + ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm); + if (ret) + return ret; + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + clks[IMX_ADMA_EXT_AUD_MCLK0] = imx_clk_fixed("ext_aud_mclk0", 0); + clks[IMX_ADMA_EXT_AUD_MCLK1] = imx_clk_fixed("ext_aud_mclk1", 0); + clks[IMX_ADMA_ESAI0_RX_CLK] = imx_clk_fixed("esai0_rx_clk", 0); + clks[IMX_ADMA_ESAI0_RX_HF_CLK] = imx_clk_fixed("esai0_rx_hf_clk", 0); + clks[IMX_ADMA_ESAI0_TX_CLK] = imx_clk_fixed("esai0_tx_clk", 0); + clks[IMX_ADMA_ESAI0_TX_HF_CLK] = imx_clk_fixed("esai0_tx_hf_clk", 0); + clks[IMX_ADMA_ESAI1_RX_CLK] = imx_clk_fixed("esai1_rx_clk", 0); + clks[IMX_ADMA_ESAI1_RX_HF_CLK] = imx_clk_fixed("esai1_rx_hf_clk", 0); + clks[IMX_ADMA_ESAI1_TX_CLK] = imx_clk_fixed("esai1_tx_clk", 0); + clks[IMX_ADMA_ESAI1_TX_HF_CLK] = imx_clk_fixed("esai1_tx_hf_clk", 0); + clks[IMX_ADMA_SPDIF0_RX] = imx_clk_fixed("spdif0_rx", 0); + clks[IMX_ADMA_SPDIF1_RX] = imx_clk_fixed("spdif1_rx", 0); + clks[IMX_ADMA_SAI0_RX_BCLK] = imx_clk_fixed("sai0_rx_bclk", 0); + clks[IMX_ADMA_SAI0_TX_BCLK] = imx_clk_fixed("sai0_tx_bclk", 0); + clks[IMX_ADMA_SAI1_RX_BCLK] = imx_clk_fixed("sai1_rx_bclk", 0); + clks[IMX_ADMA_SAI1_TX_BCLK] = imx_clk_fixed("sai1_tx_bclk", 0); + clks[IMX_ADMA_SAI2_RX_BCLK] = imx_clk_fixed("sai2_rx_bclk", 0); + clks[IMX_ADMA_SAI3_RX_BCLK] = imx_clk_fixed("sai3_rx_bclk", 0); + clks[IMX_ADMA_SAI4_RX_BCLK] = imx_clk_fixed("sai4_rx_bclk", 0); + clks[IMX_ADMA_SAI5_TX_BCLK] = imx_clk_fixed("sai5_tx_bclk", 0); + clks[IMX_ADMA_SAI6_RX_BCLK] = imx_clk_fixed("sai6_rx_bclk", 0); + clks[IMX_ADMA_HDMI_RX_MCLK] = imx_clk_fixed("hdmi_rx_mclk", 0); + + + clks[IMX_ADMA_ACM_AUD_CLK0_SEL] = imx_dev_clk_mux(dev, "acm_aud_clk0_sel", base+0x000000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + clks[IMX_ADMA_ACM_AUD_CLK1_SEL] = imx_dev_clk_mux(dev, "acm_aud_clk1_sel", base+0x010000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + + clks[IMX_ADMA_ACM_MCLKOUT0_SEL] = imx_dev_clk_mux(dev, "acm_mclkout0_sel", base+0x020000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + clks[IMX_ADMA_ACM_MCLKOUT1_SEL] = imx_dev_clk_mux(dev, "acm_mclkout1_sel", base+0x030000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + + clks[IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_asrc0_mclk_sel", base+0x040000, 0, 2, asrc_mux_clk_sels, ARRAY_SIZE(asrc_mux_clk_sels)); + + clks[IMX_ADMA_ACM_ESAI0_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_esai0_mclk_sel", base+0x060000, 0, 2, esai_mclk_sels, ARRAY_SIZE(esai_mclk_sels)); + clks[IMX_ADMA_ACM_ESAI1_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_esai1_mclk_sel", base+0x070000, 0, 2, esai_mclk_sels, ARRAY_SIZE(esai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI0_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai0_mclk_sel", base+0x0E0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI1_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai1_mclk_sel", base+0x0F0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI2_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai2_mclk_sel", base+0x100000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI3_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai3_mclk_sel", base+0x110000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI4_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai4_mclk_sel", base+0x120000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI5_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai5_mclk_sel", base+0x130000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI6_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai6_mclk_sel", base+0x140000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI7_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai7_mclk_sel", base+0x150000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + + clks[IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_spdif0_mclk_sel", base+0x1A0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels)); + clks[IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_spdif1_mclk_sel", base+0x1B0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels)); + clks[IMX_ADMA_ACM_MQS_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_mqs_mclk_sel", base+0x1C0000, 0, 2, mqs_mclk_sels, ARRAY_SIZE(mqs_mclk_sels)); + + for (i = 0; i < clk_data->clk_num; i++) { + if (IS_ERR(clks[i])) + pr_warn("i.MX clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); + } + + ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); + + pm_runtime_put_sync(&pdev->dev); + + return ret; +} + +static int imx8qm_acm_clk_remove(struct platform_device *pdev) +{ + struct imx8qm_acm_priv *priv = dev_get_drvdata(&pdev->dev); + + pm_runtime_disable(&pdev->dev); + + clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm); + + return 0; +} + +static const struct of_device_id imx8qm_acm_match[] = { + { .compatible = "nxp,imx8qm-acm", }, + { /* sentinel */ } +}; + +static int __maybe_unused imx8qm_acm_runtime_suspend(struct device *dev) +{ + struct imx8qm_acm_priv *priv = dev_get_drvdata(dev); + + priv->regs[0] = readl_relaxed(priv->reg + 0x000000); + priv->regs[1] = readl_relaxed(priv->reg + 0x010000); + priv->regs[2] = readl_relaxed(priv->reg + 0x020000); + priv->regs[3] = readl_relaxed(priv->reg + 0x030000); + priv->regs[4] = readl_relaxed(priv->reg + 0x040000); + priv->regs[6] = readl_relaxed(priv->reg + 0x060000); + priv->regs[7] = readl_relaxed(priv->reg + 0x070000); + priv->regs[14] = readl_relaxed(priv->reg + 0x0E0000); + priv->regs[15] = readl_relaxed(priv->reg + 0x0F0000); + priv->regs[16] = readl_relaxed(priv->reg + 0x100000); + priv->regs[17] = readl_relaxed(priv->reg + 0x110000); + priv->regs[18] = readl_relaxed(priv->reg + 0x120000); + priv->regs[19] = readl_relaxed(priv->reg + 0x130000); + priv->regs[20] = readl_relaxed(priv->reg + 0x140000); + priv->regs[21] = readl_relaxed(priv->reg + 0x150000); + priv->regs[26] = readl_relaxed(priv->reg + 0x1A0000); + priv->regs[27] = readl_relaxed(priv->reg + 0x1B0000); + priv->regs[28] = readl_relaxed(priv->reg + 0x1C0000); + + return 0; +} + +static int __maybe_unused imx8qm_acm_runtime_resume(struct device *dev) +{ + struct imx8qm_acm_priv *priv = dev_get_drvdata(dev); + + writel_relaxed(priv->regs[0], priv->reg + 0x000000); + writel_relaxed(priv->regs[1], priv->reg + 0x010000); + writel_relaxed(priv->regs[2], priv->reg + 0x020000); + writel_relaxed(priv->regs[3], priv->reg + 0x030000); + writel_relaxed(priv->regs[4], priv->reg + 0x040000); + writel_relaxed(priv->regs[6], priv->reg + 0x060000); + writel_relaxed(priv->regs[7], priv->reg + 0x070000); + writel_relaxed(priv->regs[14], priv->reg + 0x0E0000); + writel_relaxed(priv->regs[15], priv->reg + 0x0F0000); + writel_relaxed(priv->regs[16], priv->reg + 0x100000); + writel_relaxed(priv->regs[17], priv->reg + 0x110000); + writel_relaxed(priv->regs[18], priv->reg + 0x120000); + writel_relaxed(priv->regs[19], priv->reg + 0x130000); + writel_relaxed(priv->regs[20], priv->reg + 0x140000); + writel_relaxed(priv->regs[21], priv->reg + 0x150000); + writel_relaxed(priv->regs[26], priv->reg + 0x1A0000); + writel_relaxed(priv->regs[27], priv->reg + 0x1B0000); + writel_relaxed(priv->regs[28], priv->reg + 0x1C0000); + + return 0; +} + +static const struct dev_pm_ops imx8qm_acm_pm_ops = { + SET_RUNTIME_PM_OPS(imx8qm_acm_runtime_suspend, + imx8qm_acm_runtime_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver imx8qm_acm_clk_driver = { + .driver = { + .name = "imx8qm-acm", + .of_match_table = imx8qm_acm_match, + .pm = &imx8qm_acm_pm_ops, + .suppress_bind_attrs = true, + }, + .probe = imx8qm_acm_clk_probe, + .remove = imx8qm_acm_clk_remove, +}; + +static int __init imx8qm_acm_init(void) +{ + return platform_driver_register(&imx8qm_acm_clk_driver); +} +fs_initcall(imx8qm_acm_init); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8qm-rsrc.c linux-imx-phytec/drivers/clk/imx/clk-imx8qm-rsrc.c --- linux-6.1.55/drivers/clk/imx/clk-imx8qm-rsrc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8qm-rsrc.c 2024-06-19 12:33:59.556214044 +0200 @@ -43,6 +43,8 @@ IMX_SC_R_FTM_0, IMX_SC_R_FTM_1, IMX_SC_R_CAN_0, + IMX_SC_R_CAN_1, + IMX_SC_R_CAN_2, IMX_SC_R_GPU_0_PID0, IMX_SC_R_GPU_1_PID0, IMX_SC_R_PWM_0, @@ -65,7 +67,6 @@ IMX_SC_R_SDHC_2, IMX_SC_R_ENET_0, IMX_SC_R_ENET_1, - IMX_SC_R_MLB_0, IMX_SC_R_USB_2, IMX_SC_R_NAND, IMX_SC_R_LVDS_0, @@ -79,8 +80,8 @@ IMX_SC_R_M4_0_I2C, IMX_SC_R_M4_1_I2C, IMX_SC_R_AUDIO_PLL_0, - IMX_SC_R_VPU_UART, - IMX_SC_R_VPUCORE, + IMX_SC_R_ENET_0_A2, + IMX_SC_R_ENET_1_A0, IMX_SC_R_MIPI_0, IMX_SC_R_MIPI_0_PWM_0, IMX_SC_R_MIPI_0_I2C_0, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8qxp-acm.c linux-imx-phytec/drivers/clk/imx/clk-imx8qxp-acm.c --- linux-6.1.55/drivers/clk/imx/clk-imx8qxp-acm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8qxp-acm.c 2024-06-19 12:33:59.556214044 +0200 @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-scu.h" +#include "clk-imx-acm-utils.h" + +#include + +struct imx8qxp_acm_priv { + struct clk_imx_acm_pm_domains dev_pm; + void __iomem *reg; + u32 regs[0x20]; +}; + +static const char *aud_clk_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", +}; + +static const char *mclk_out_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "dummy", + "dummy", + "spdif0_rx", + "dummy", + "dummy", + "sai4_rx_bclk", +}; + +static const char *sai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *esai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *spdif_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char *mqs_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static int imx8qxp_acm_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk_onecell_data *clk_data; + struct imx8qxp_acm_priv *priv; + struct resource *res; + struct clk **clks; + void __iomem *base; + int ret; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap(dev, res->start, resource_size(res)); + if (!base) + return -ENOMEM; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->reg = base; + + platform_set_drvdata(pdev, priv); + + clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->clks = devm_kcalloc(&pdev->dev, IMX_ADMA_ACM_CLK_END, + sizeof(*clk_data->clks), GFP_KERNEL); + if (!clk_data->clks) + return -ENOMEM; + + clk_data->clk_num = IMX_ADMA_ACM_CLK_END; + + clks = clk_data->clks; + + ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm); + if (ret) + return ret; + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + clks[IMX_ADMA_EXT_AUD_MCLK0] = imx_clk_fixed("ext_aud_mclk0", 0); + clks[IMX_ADMA_EXT_AUD_MCLK1] = imx_clk_fixed("ext_aud_mclk1", 0); + clks[IMX_ADMA_ESAI0_RX_CLK] = imx_clk_fixed("esai0_rx_clk", 0); + clks[IMX_ADMA_ESAI0_RX_HF_CLK] = imx_clk_fixed("esai0_rx_hf_clk", 0); + clks[IMX_ADMA_ESAI0_TX_CLK] = imx_clk_fixed("esai0_tx_clk", 0); + clks[IMX_ADMA_ESAI0_TX_HF_CLK] = imx_clk_fixed("esai0_tx_hf_clk", 0); + clks[IMX_ADMA_SPDIF0_RX] = imx_clk_fixed("spdif0_rx", 0); + clks[IMX_ADMA_SAI0_RX_BCLK] = imx_clk_fixed("sai0_rx_bclk", 0); + clks[IMX_ADMA_SAI0_TX_BCLK] = imx_clk_fixed("sai0_tx_bclk", 0); + clks[IMX_ADMA_SAI1_RX_BCLK] = imx_clk_fixed("sai1_rx_bclk", 0); + clks[IMX_ADMA_SAI1_TX_BCLK] = imx_clk_fixed("sai1_tx_bclk", 0); + clks[IMX_ADMA_SAI2_RX_BCLK] = imx_clk_fixed("sai2_rx_bclk", 0); + clks[IMX_ADMA_SAI3_RX_BCLK] = imx_clk_fixed("sai3_rx_bclk", 0); + clks[IMX_ADMA_SAI4_RX_BCLK] = imx_clk_fixed("sai4_rx_bclk", 0); + + + clks[IMX_ADMA_ACM_AUD_CLK0_SEL] = imx_dev_clk_mux(dev, "acm_aud_clk0_sel", base+0x000000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + clks[IMX_ADMA_ACM_AUD_CLK1_SEL] = imx_dev_clk_mux(dev, "acm_aud_clk1_sel", base+0x010000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + + clks[IMX_ADMA_ACM_MCLKOUT0_SEL] = imx_dev_clk_mux(dev, "acm_mclkout0_sel", base+0x020000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + clks[IMX_ADMA_ACM_MCLKOUT1_SEL] = imx_dev_clk_mux(dev, "acm_mclkout1_sel", base+0x030000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + + clks[IMX_ADMA_ACM_ESAI0_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_esai0_mclk_sel", base+0x060000, 0, 2, esai_mclk_sels, ARRAY_SIZE(esai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI0_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai0_mclk_sel", base+0x0E0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI1_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai1_mclk_sel", base+0x0F0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI2_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai2_mclk_sel", base+0x100000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI3_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai3_mclk_sel", base+0x110000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI4_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai4_mclk_sel", base+0x140000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI5_MCLK_SEL] = imx_dev_clk_mux(dev, "acm_sai5_mclk_sel", base+0x150000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + + clks[IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_spdif0_mclk_sel", base+0x1A0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels)); + clks[IMX_ADMA_ACM_MQS_TX_CLK_SEL] = imx_dev_clk_mux(dev, "acm_mqs_mclk_sel", base+0x1C0000, 0, 2, mqs_mclk_sels, ARRAY_SIZE(mqs_mclk_sels)); + + for (i = 0; i < clk_data->clk_num; i++) { + if (IS_ERR(clks[i])) + pr_warn("i.MX clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); + } + + ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); + + pm_runtime_put_sync(&pdev->dev); + + return ret; +} + +static int imx8qxp_acm_clk_remove(struct platform_device *pdev) +{ + struct imx8qxp_acm_priv *priv = dev_get_drvdata(&pdev->dev); + + pm_runtime_disable(&pdev->dev); + + clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm); + + return 0; +} + +static const struct of_device_id imx8qxp_acm_match[] = { + { .compatible = "nxp,imx8qxp-acm", }, + { /* sentinel */ } +}; + +static int __maybe_unused imx8qxp_acm_runtime_suspend(struct device *dev) +{ + struct imx8qxp_acm_priv *priv = dev_get_drvdata(dev); + + priv->regs[0] = readl_relaxed(priv->reg + 0x000000); + priv->regs[1] = readl_relaxed(priv->reg + 0x010000); + priv->regs[2] = readl_relaxed(priv->reg + 0x020000); + priv->regs[3] = readl_relaxed(priv->reg + 0x030000); + priv->regs[6] = readl_relaxed(priv->reg + 0x060000); + priv->regs[14] = readl_relaxed(priv->reg + 0x0E0000); + priv->regs[15] = readl_relaxed(priv->reg + 0x0F0000); + priv->regs[16] = readl_relaxed(priv->reg + 0x100000); + priv->regs[17] = readl_relaxed(priv->reg + 0x110000); + priv->regs[20] = readl_relaxed(priv->reg + 0x140000); + priv->regs[21] = readl_relaxed(priv->reg + 0x150000); + priv->regs[26] = readl_relaxed(priv->reg + 0x1A0000); + priv->regs[28] = readl_relaxed(priv->reg + 0x1C0000); + + return 0; +} + +static int __maybe_unused imx8qxp_acm_runtime_resume(struct device *dev) +{ + struct imx8qxp_acm_priv *priv = dev_get_drvdata(dev); + + writel_relaxed(priv->regs[0], priv->reg + 0x000000); + writel_relaxed(priv->regs[1], priv->reg + 0x010000); + writel_relaxed(priv->regs[2], priv->reg + 0x020000); + writel_relaxed(priv->regs[3], priv->reg + 0x030000); + writel_relaxed(priv->regs[6], priv->reg + 0x060000); + writel_relaxed(priv->regs[14], priv->reg + 0x0E0000); + writel_relaxed(priv->regs[15], priv->reg + 0x0F0000); + writel_relaxed(priv->regs[16], priv->reg + 0x100000); + writel_relaxed(priv->regs[17], priv->reg + 0x110000); + writel_relaxed(priv->regs[20], priv->reg + 0x140000); + writel_relaxed(priv->regs[21], priv->reg + 0x150000); + writel_relaxed(priv->regs[26], priv->reg + 0x1A0000); + writel_relaxed(priv->regs[28], priv->reg + 0x1C0000); + + return 0; +} + +const struct dev_pm_ops imx8qxp_acm_pm_ops = { + SET_RUNTIME_PM_OPS(imx8qxp_acm_runtime_suspend, + imx8qxp_acm_runtime_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver imx8qxp_acm_clk_driver = { + .driver = { + .name = "imx8qxp-acm", + .of_match_table = imx8qxp_acm_match, + .pm = &imx8qxp_acm_pm_ops, + .suppress_bind_attrs = true, + }, + .probe = imx8qxp_acm_clk_probe, + .remove = imx8qxp_acm_clk_remove, +}; + +static int __init imx8qxp_acm_init(void) +{ + return platform_driver_register(&imx8qxp_acm_clk_driver); +} +fs_initcall(imx8qxp_acm_init); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8qxp.c linux-imx-phytec/drivers/clk/imx/clk-imx8qxp.c --- linux-6.1.55/drivers/clk/imx/clk-imx8qxp.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8qxp.c 2024-06-19 12:33:59.556214044 +0200 @@ -67,6 +67,22 @@ "lcd_pxl_bypass_div_clk", }; +static const char *const lvds0_sels[] = { + "clk_dummy", + "clk_dummy", + "clk_dummy", + "clk_dummy", + "lvds0_bypass_clk", +}; + +static const char * const lvds1_sels[] = { + "clk_dummy", + "clk_dummy", + "clk_dummy", + "clk_dummy", + "lvds1_bypass_clk", +}; + static const char * const mipi_sels[] = { "clk_dummy", "clk_dummy", @@ -91,6 +107,11 @@ "clk_dummy", }; +static inline bool clk_on_imx8dxl(struct device_node *node) +{ + return of_device_is_compatible(node, "fsl,imx8dxl-clk") != 0; +} + static int imx8qxp_clk_probe(struct platform_device *pdev) { struct device_node *ccm_node = pdev->dev.of_node; @@ -116,7 +137,6 @@ imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER); imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER); imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER); - imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER); imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER); imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER); imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER); @@ -148,10 +168,10 @@ imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER); imx_clk_scu("adc1_clk", IMX_SC_R_ADC_1, IMX_SC_PM_CLK_PER); imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("elcdif_pll", IMX_SC_R_ELCDIF_PLL, IMX_SC_PM_CLK_PLL); imx_clk_scu2("lcd_clk", lcd_sels, ARRAY_SIZE(lcd_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER); - imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0); imx_clk_scu("lcd_pxl_bypass_div_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_BYPASS); - imx_clk_scu("elcdif_pll", IMX_SC_R_ELCDIF_PLL, IMX_SC_PM_CLK_PLL); + imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0); /* Audio SS */ imx_clk_scu("audio_pll0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL); @@ -170,13 +190,15 @@ imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK); imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS); imx_clk_gate_gpr_scu("enet0_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true); - imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0); + if (!clk_on_imx8dxl(ccm_node)) { + imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0); + } imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER); imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV); imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK); imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS); imx_clk_gate_gpr_scu("enet1_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true); - imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0); imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS); imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER); imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER); @@ -184,26 +206,26 @@ imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC); /* Display controller SS */ - imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0); - imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1); imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL); imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL); imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1); imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS); - imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0); - imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1); imx_clk_scu("dc1_pll0_clk", IMX_SC_R_DC_1_PLL_0, IMX_SC_PM_CLK_PLL); imx_clk_scu("dc1_pll1_clk", IMX_SC_R_DC_1_PLL_1, IMX_SC_PM_CLK_PLL); imx_clk_scu("dc1_bypass0_clk", IMX_SC_R_DC_1_VIDEO0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1); imx_clk_scu("dc1_bypass1_clk", IMX_SC_R_DC_1_VIDEO1, IMX_SC_PM_CLK_BYPASS); /* MIPI-LVDS SS */ imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS); imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER); - imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2); - imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS); - imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3); + imx_clk_scu("lvds0_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu2("lvds0_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu2("lvds0_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3); imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS); imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS); imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY); @@ -213,10 +235,9 @@ imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS); imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER); - imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2); - imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS); - imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3); - + imx_clk_scu("lvds1_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu2("lvds1_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2); + imx_clk_scu2("lvds1_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3); imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS); imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS); imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8qxp-lpcg.c linux-imx-phytec/drivers/clk/imx/clk-imx8qxp-lpcg.c --- linux-6.1.55/drivers/clk/imx/clk-imx8qxp-lpcg.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8qxp-lpcg.c 2024-06-19 12:33:59.556214044 +0200 @@ -16,168 +16,12 @@ #include #include "clk-scu.h" -#include "clk-imx8qxp-lpcg.h" - -#include - -/* - * struct imx8qxp_lpcg_data - Description of one LPCG clock - * @id: clock ID - * @name: clock name - * @parent: parent clock name - * @flags: common clock flags - * @offset: offset of this LPCG clock - * @bit_idx: bit index of this LPCG clock - * @hw_gate: whether supports HW autogate - * - * This structure describes one LPCG clock - */ -struct imx8qxp_lpcg_data { - int id; - char *name; - char *parent; - unsigned long flags; - u32 offset; - u8 bit_idx; - bool hw_gate; -}; - -/* - * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks - * @lpcg: LPCG clocks array of one subsystem - * @num_lpcg: the number of LPCG clocks - * @num_max: the maximum number of LPCG clocks - * - * This structure describes each subsystem LPCG clocks information - * which then will be used to create respective LPCGs clocks - */ -struct imx8qxp_ss_lpcg { - const struct imx8qxp_lpcg_data *lpcg; - u8 num_lpcg; - u8 num_max; -}; - -static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = { - { IMX_ADMA_LPCG_UART0_IPG_CLK, "uart0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_0_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_UART0_BAUD_CLK, "uart0_lpcg_baud_clk", "uart0_clk", 0, ADMA_LPUART_0_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_UART1_IPG_CLK, "uart1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_1_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_UART1_BAUD_CLK, "uart1_lpcg_baud_clk", "uart1_clk", 0, ADMA_LPUART_1_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_UART2_IPG_CLK, "uart2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_2_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_UART2_BAUD_CLK, "uart2_lpcg_baud_clk", "uart2_clk", 0, ADMA_LPUART_2_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_UART3_IPG_CLK, "uart3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_3_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_UART3_BAUD_CLK, "uart3_lpcg_baud_clk", "uart3_clk", 0, ADMA_LPUART_3_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_I2C0_IPG_CLK, "i2c0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_0_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_I2C0_CLK, "i2c0_lpcg_clk", "i2c0_clk", 0, ADMA_LPI2C_0_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_I2C1_IPG_CLK, "i2c1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_1_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_I2C1_CLK, "i2c1_lpcg_clk", "i2c1_clk", 0, ADMA_LPI2C_1_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_I2C2_IPG_CLK, "i2c2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_2_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, }, - { IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, }, - - { IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, }, - { IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, }, - { IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, }, - { IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, }, -}; - -static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = { - .lpcg = imx8qxp_lpcg_adma, - .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_adma), - .num_max = IMX_ADMA_LPCG_CLK_END, -}; - -static const struct imx8qxp_lpcg_data imx8qxp_lpcg_conn[] = { - { IMX_CONN_LPCG_SDHC0_PER_CLK, "sdhc0_lpcg_per_clk", "sdhc0_clk", 0, CONN_USDHC_0_LPCG, 0, 0, }, - { IMX_CONN_LPCG_SDHC0_IPG_CLK, "sdhc0_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_0_LPCG, 16, 0, }, - { IMX_CONN_LPCG_SDHC0_HCLK, "sdhc0_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_0_LPCG, 20, 0, }, - { IMX_CONN_LPCG_SDHC1_PER_CLK, "sdhc1_lpcg_per_clk", "sdhc1_clk", 0, CONN_USDHC_1_LPCG, 0, 0, }, - { IMX_CONN_LPCG_SDHC1_IPG_CLK, "sdhc1_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_1_LPCG, 16, 0, }, - { IMX_CONN_LPCG_SDHC1_HCLK, "sdhc1_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_1_LPCG, 20, 0, }, - { IMX_CONN_LPCG_SDHC2_PER_CLK, "sdhc2_lpcg_per_clk", "sdhc2_clk", 0, CONN_USDHC_2_LPCG, 0, 0, }, - { IMX_CONN_LPCG_SDHC2_IPG_CLK, "sdhc2_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_2_LPCG, 16, 0, }, - { IMX_CONN_LPCG_SDHC2_HCLK, "sdhc2_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_2_LPCG, 20, 0, }, - { IMX_CONN_LPCG_ENET0_ROOT_CLK, "enet0_ipg_root_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 0, 0, }, - { IMX_CONN_LPCG_ENET0_TX_CLK, "enet0_tx_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 4, 0, }, - { IMX_CONN_LPCG_ENET0_AHB_CLK, "enet0_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_0_LPCG, 8, 0, }, - { IMX_CONN_LPCG_ENET0_IPG_S_CLK, "enet0_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_0_LPCG, 20, 0, }, - { IMX_CONN_LPCG_ENET0_IPG_CLK, "enet0_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_0_LPCG, 16, 0, }, - { IMX_CONN_LPCG_ENET1_ROOT_CLK, "enet1_ipg_root_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 0, 0, }, - { IMX_CONN_LPCG_ENET1_TX_CLK, "enet1_tx_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 4, 0, }, - { IMX_CONN_LPCG_ENET1_AHB_CLK, "enet1_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_1_LPCG, 8, 0, }, - { IMX_CONN_LPCG_ENET1_IPG_S_CLK, "enet1_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_1_LPCG, 20, 0, }, - { IMX_CONN_LPCG_ENET1_IPG_CLK, "enet1_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_1_LPCG, 16, 0, }, -}; - -static const struct imx8qxp_ss_lpcg imx8qxp_ss_conn = { - .lpcg = imx8qxp_lpcg_conn, - .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_conn), - .num_max = IMX_CONN_LPCG_CLK_END, -}; - -static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = { - { IMX_LSIO_LPCG_PWM0_IPG_CLK, "pwm0_lpcg_ipg_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM0_IPG_HF_CLK, "pwm0_lpcg_ipg_hf_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM0_IPG_S_CLK, "pwm0_lpcg_ipg_s_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK, "pwm0_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_0_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK, "pwm0_lpcg_ipg_mstr_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM1_IPG_CLK, "pwm1_lpcg_ipg_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM1_IPG_HF_CLK, "pwm1_lpcg_ipg_hf_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM1_IPG_S_CLK, "pwm1_lpcg_ipg_s_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK, "pwm1_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_1_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK, "pwm1_lpcg_ipg_mstr_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM2_IPG_CLK, "pwm2_lpcg_ipg_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM2_IPG_HF_CLK, "pwm2_lpcg_ipg_hf_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM2_IPG_S_CLK, "pwm2_lpcg_ipg_s_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK, "pwm2_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_2_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK, "pwm2_lpcg_ipg_mstr_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM3_IPG_CLK, "pwm3_lpcg_ipg_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM3_IPG_HF_CLK, "pwm3_lpcg_ipg_hf_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM3_IPG_S_CLK, "pwm3_lpcg_ipg_s_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK, "pwm3_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_3_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK, "pwm3_lpcg_ipg_mstr_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM4_IPG_CLK, "pwm4_lpcg_ipg_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM4_IPG_HF_CLK, "pwm4_lpcg_ipg_hf_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM4_IPG_S_CLK, "pwm4_lpcg_ipg_s_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK, "pwm4_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_4_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK, "pwm4_lpcg_ipg_mstr_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM5_IPG_CLK, "pwm5_lpcg_ipg_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM5_IPG_HF_CLK, "pwm5_lpcg_ipg_hf_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM5_IPG_S_CLK, "pwm5_lpcg_ipg_s_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK, "pwm5_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_5_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK, "pwm5_lpcg_ipg_mstr_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 24, 0, }, - { IMX_LSIO_LPCG_PWM6_IPG_CLK, "pwm6_lpcg_ipg_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 0, 0, }, - { IMX_LSIO_LPCG_PWM6_IPG_HF_CLK, "pwm6_lpcg_ipg_hf_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 4, 0, }, - { IMX_LSIO_LPCG_PWM6_IPG_S_CLK, "pwm6_lpcg_ipg_s_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 16, 0, }, - { IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK, "pwm6_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_6_LPCG, 20, 0, }, - { IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, }, -}; - -static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = { - .lpcg = imx8qxp_lpcg_lsio, - .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio), - .num_max = IMX_LSIO_LPCG_CLK_END, -}; #define IMX_LPCG_MAX_CLKS 8 -static struct clk_hw *imx_lpcg_of_clk_src_get(struct of_phandle_args *clkspec, - void *data) -{ - struct clk_hw_onecell_data *hw_data = data; - unsigned int idx = clkspec->args[0] / 4; - - if (idx >= hw_data->num) { - pr_err("%s: invalid index %u\n", __func__, idx); - return ERR_PTR(-EINVAL); - } - - return hw_data->hws[idx]; -} - -static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev, - struct device_node *np) +static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; const char *output_names[IMX_LPCG_MAX_CLKS]; const char *parent_names[IMX_LPCG_MAX_CLKS]; unsigned int bit_offset[IMX_LPCG_MAX_CLKS]; @@ -185,88 +29,78 @@ struct clk_hw **clk_hws; struct resource *res; void __iomem *base; + bool autogate; int count; - int idx; int ret; int i; - if (!of_device_is_compatible(np, "fsl,imx8qxp-lpcg")) - return -EINVAL; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(base)) return PTR_ERR(base); - count = of_property_count_u32_elems(np, "clock-indices"); + count = of_property_count_u32_elems(np, "bit-offset"); if (count < 0) { dev_err(&pdev->dev, "failed to count clocks\n"); return -EINVAL; } - /* - * A trick here is that we set the num of clks to the MAX instead - * of the count from clock-indices because one LPCG supports up to - * 8 clock outputs which each of them is fixed to 4 bits. Then we can - * easily get the clock by clk-indices (bit-offset) / 4. - * And the cost is very limited few pointers. - */ - - clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, - IMX_LPCG_MAX_CLKS), GFP_KERNEL); + clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, count), + GFP_KERNEL); if (!clk_data) return -ENOMEM; - clk_data->num = IMX_LPCG_MAX_CLKS; + clk_data->num = count; clk_hws = clk_data->hws; - ret = of_property_read_u32_array(np, "clock-indices", bit_offset, - count); + ret = of_property_read_u32_array(np, "bit-offset", bit_offset, + clk_data->num); if (ret < 0) { - dev_err(&pdev->dev, "failed to read clock-indices\n"); + dev_err(&pdev->dev, "failed to read clocks bit-offset\n"); return -EINVAL; } - ret = of_clk_parent_fill(np, parent_names, count); - if (ret != count) { + ret = of_clk_parent_fill(np, parent_names, clk_data->num); + if (ret != clk_data->num) { dev_err(&pdev->dev, "failed to get clock parent names\n"); - return count; + return -EINVAL; } ret = of_property_read_string_array(np, "clock-output-names", - output_names, count); - if (ret != count) { + output_names, clk_data->num); + if (ret != clk_data->num) { dev_err(&pdev->dev, "failed to read clock-output-names\n"); return -EINVAL; } + autogate = of_property_read_bool(np, "hw-autogate"); + pm_runtime_get_noresume(&pdev->dev); pm_runtime_set_active(&pdev->dev); pm_runtime_set_autosuspend_delay(&pdev->dev, 500); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_enable(&pdev->dev); - for (i = 0; i < count; i++) { - idx = bit_offset[i] / 4; - if (idx >= IMX_LPCG_MAX_CLKS) { + for (i = 0; i < clk_data->num; i++) { + if (bit_offset[i] > 31) { dev_warn(&pdev->dev, "invalid bit offset of clock %d\n", i); ret = -EINVAL; goto unreg; } - clk_hws[idx] = imx_clk_lpcg_scu_dev(&pdev->dev, output_names[i], - parent_names[i], 0, base, - bit_offset[i], false); - if (IS_ERR(clk_hws[idx])) { + clk_hws[i] = imx_clk_lpcg_scu_dev(&pdev->dev, output_names[i], + parent_names[i], 0, base, + bit_offset[i], autogate); + if (IS_ERR(clk_hws[i])) { dev_warn(&pdev->dev, "failed to register clock %d\n", - idx); - ret = PTR_ERR(clk_hws[idx]); + i); + ret = PTR_ERR(clk_hws[i]); goto unreg; } } - ret = devm_of_clk_add_hw_provider(&pdev->dev, imx_lpcg_of_clk_src_get, + ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, clk_data); if (ret) goto unreg; @@ -278,9 +112,8 @@ unreg: while (--i >= 0) { - idx = bit_offset[i] / 4; - if (clk_hws[idx]) - imx_clk_lpcg_scu_unregister(clk_hws[idx]); + if (clk_hws[i]) + imx_clk_lpcg_scu_unregister(clk_hws[i]); } pm_runtime_disable(&pdev->dev); @@ -288,74 +121,7 @@ return ret; } -static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - struct clk_hw_onecell_data *clk_data; - const struct imx8qxp_ss_lpcg *ss_lpcg; - const struct imx8qxp_lpcg_data *lpcg; - struct resource *res; - struct clk_hw **clks; - void __iomem *base; - int ret; - int i; - - /* try new binding to parse clocks from device tree first */ - ret = imx_lpcg_parse_clks_from_dt(pdev, np); - if (!ret) - return 0; - - ss_lpcg = of_device_get_match_data(dev); - if (!ss_lpcg) - return -ENODEV; - - /* - * Please don't replace this with devm_platform_ioremap_resource. - * - * devm_platform_ioremap_resource calls devm_ioremap_resource which - * differs from devm_ioremap by also calling devm_request_mem_region - * and preventing other mappings in the same area. - * - * On imx8 the LPCG nodes map entire subsystems and overlap - * peripherals, this means that using devm_platform_ioremap_resource - * will cause many devices to fail to probe including serial ports. - */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; - base = devm_ioremap(dev, res->start, resource_size(res)); - if (!base) - return -ENOMEM; - - clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, - ss_lpcg->num_max), GFP_KERNEL); - if (!clk_data) - return -ENOMEM; - - clk_data->num = ss_lpcg->num_max; - clks = clk_data->hws; - - for (i = 0; i < ss_lpcg->num_lpcg; i++) { - lpcg = ss_lpcg->lpcg + i; - clks[lpcg->id] = imx_clk_lpcg_scu(lpcg->name, lpcg->parent, - lpcg->flags, base + lpcg->offset, - lpcg->bit_idx, lpcg->hw_gate); - } - - for (i = 0; i < clk_data->num; i++) { - if (IS_ERR(clks[i])) - pr_warn("i.MX clk %u: register failed with %ld\n", - i, PTR_ERR(clks[i])); - } - - return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); -} - static const struct of_device_id imx8qxp_lpcg_match[] = { - { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, }, - { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, }, - { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, }, { .compatible = "fsl,imx8qxp-lpcg", NULL }, { /* sentinel */ } }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8qxp-lpcg.h linux-imx-phytec/drivers/clk/imx/clk-imx8qxp-lpcg.h --- linux-6.1.55/drivers/clk/imx/clk-imx8qxp-lpcg.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8qxp-lpcg.h 2024-06-19 12:33:59.556214044 +0200 @@ -42,7 +42,6 @@ #define CONN_ENET_0_LPCG 0x30000 #define CONN_ENET_1_LPCG 0x40000 #define CONN_DTCP_LPCG 0x50000 -#define CONN_MLB_LPCG 0x60000 #define CONN_USB_2_LPCG 0x70000 #define CONN_USB_3_LPCG 0x80000 #define CONN_NAND_LPCG 0x90000 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8qxp-rsrc.c linux-imx-phytec/drivers/clk/imx/clk-imx8qxp-rsrc.c --- linux-6.1.55/drivers/clk/imx/clk-imx8qxp-rsrc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8qxp-rsrc.c 2024-06-19 12:33:59.556214044 +0200 @@ -54,15 +54,17 @@ IMX_SC_R_SDHC_2, IMX_SC_R_ENET_0, IMX_SC_R_ENET_1, - IMX_SC_R_MLB_0, IMX_SC_R_USB_2, IMX_SC_R_NAND, IMX_SC_R_LVDS_0, IMX_SC_R_LVDS_1, + IMX_SC_R_M4_0_UART, IMX_SC_R_M4_0_I2C, IMX_SC_R_ELCDIF_PLL, IMX_SC_R_AUDIO_PLL_0, IMX_SC_R_PI_0, + IMX_SC_R_PI_0_PWM_0, + IMX_SC_R_PI_0_I2C_0, IMX_SC_R_PI_0_PLL, IMX_SC_R_MIPI_0, IMX_SC_R_MIPI_0_PWM_0, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx8ulp.c linux-imx-phytec/drivers/clk/imx/clk-imx8ulp.c --- linux-6.1.55/drivers/clk/imx/clk-imx8ulp.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx8ulp.c 2024-06-19 12:33:59.560214112 +0200 @@ -198,10 +198,10 @@ clks[IMX8ULP_CLK_NIC_SEL] = imx_clk_hw_mux2("nic_sel", base + 0x34, 28, 2, nic_sels, ARRAY_SIZE(nic_sels)); clks[IMX8ULP_CLK_NIC_AD_DIVPLAT] = imx_clk_hw_divider_flags("nic_ad_divplat", "nic_sel", base + 0x34, 21, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); - clks[IMX8ULP_CLK_NIC_PER_DIVPLAT] = imx_clk_hw_divider_flags("nic_per_divplat", "nic_ad_divplat", base + 0x34, 14, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); - clks[IMX8ULP_CLK_XBAR_AD_DIVPLAT] = imx_clk_hw_divider_flags("xbar_ad_divplat", "nic_ad_divplat", base + 0x38, 14, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); - clks[IMX8ULP_CLK_XBAR_DIVBUS] = imx_clk_hw_divider_flags("xbar_divbus", "xbar_ad_divplat", base + 0x38, 7, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); - clks[IMX8ULP_CLK_XBAR_AD_SLOW] = imx_clk_hw_divider_flags("xbar_ad_slow", "xbar_divbus", base + 0x38, 0, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); + clks[IMX8ULP_CLK_NIC_PER_DIVPLAT] = imx_clk_hw_divider_flags("nic_per_divplat", "nic_ad_divplat", base + 0x34, 14, 6, CLK_SET_RATE_PARENT); + clks[IMX8ULP_CLK_XBAR_AD_DIVPLAT] = imx_clk_hw_divider_flags("xbar_ad_divplat", "nic_ad_divplat", base + 0x38, 14, 6, CLK_SET_RATE_PARENT); + clks[IMX8ULP_CLK_XBAR_DIVBUS] = imx_clk_hw_divider_flags("xbar_divbus", "xbar_ad_divplat", base + 0x38, 7, 6, CLK_SET_RATE_PARENT); + clks[IMX8ULP_CLK_XBAR_AD_SLOW] = imx_clk_hw_divider_flags("xbar_ad_slow", "xbar_divbus", base + 0x38, 0, 6, CLK_SET_RATE_PARENT); clks[IMX8ULP_CLK_SOSC_DIV1_GATE] = imx_clk_hw_gate_dis("sosc_div1_gate", "sosc", base + 0x108, 7); clks[IMX8ULP_CLK_SOSC_DIV2_GATE] = imx_clk_hw_gate_dis("sosc_div2_gate", "sosc", base + 0x108, 15); @@ -255,9 +255,9 @@ clks[IMX8ULP_CLK_HIFI_DIVCORE] = imx_clk_hw_divider("hifi_core_div", "hifi_sel", base + 0x14, 21, 6); clks[IMX8ULP_CLK_HIFI_DIVPLAT] = imx_clk_hw_divider("hifi_plat_div", "hifi_core_div", base + 0x14, 14, 6); - clks[IMX8ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x40, 28, 3, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_PARENT_GATE); - clks[IMX8ULP_CLK_DDR_DIV] = imx_clk_hw_divider_flags("ddr_div", "ddr_sel", base + 0x40, 21, 6, CLK_IS_CRITICAL); - clks[IMX8ULP_CLK_LPAV_AXI_SEL] = imx_clk_hw_mux("lpav_sel", base + 0x3c, 28, 2, lpav_sels, ARRAY_SIZE(lpav_sels)); + clks[IMX8ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x40, 28, 3, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_GET_RATE_NOCACHE); + clks[IMX8ULP_CLK_DDR_DIV] = imx_clk_hw_divider_flags("ddr_div", "ddr_sel", base + 0x40, 21, 6, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE); + clks[IMX8ULP_CLK_LPAV_AXI_SEL] = imx_clk_hw_mux2("lpav_sel", base + 0x3c, 28, 2, lpav_sels, ARRAY_SIZE(lpav_sels)); clks[IMX8ULP_CLK_LPAV_AXI_DIV] = imx_clk_hw_divider_flags("lpav_axi_div", "lpav_sel", base + 0x3c, 21, 6, CLK_IS_CRITICAL); clks[IMX8ULP_CLK_LPAV_AHB_DIV] = imx_clk_hw_divider_flags("lpav_ahb_div", "lpav_axi_div", base + 0x3c, 14, 6, CLK_IS_CRITICAL); clks[IMX8ULP_CLK_LPAV_BUS_DIV] = imx_clk_hw_divider_flags("lpav_bus_div", "lpav_axi_div", base + 0x3c, 7, 6, CLK_IS_CRITICAL); @@ -275,14 +275,14 @@ clks[IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE] = imx_clk_hw_gate_dis("pll4_pfd2_div2_gate", "pll4_pfd2", base + 0x60c, 15); clks[IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE] = imx_clk_hw_gate_dis("pll4_pfd3_div1_gate", "pll4_pfd3", base + 0x60c, 23); clks[IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE] = imx_clk_hw_gate_dis("pll4_pfd3_div2_gate", "pll4_pfd3", base + 0x60c, 31); - clks[IMX8ULP_CLK_PLL4_PFD0_DIV1] = imx_clk_hw_divider("pll4_pfd0_div1", "pll4_pfd0_div1_gate", base + 0x608, 0, 6); - clks[IMX8ULP_CLK_PLL4_PFD0_DIV2] = imx_clk_hw_divider("pll4_pfd0_div2", "pll4_pfd0_div2_gate", base + 0x608, 8, 6); - clks[IMX8ULP_CLK_PLL4_PFD1_DIV1] = imx_clk_hw_divider("pll4_pfd1_div1", "pll4_pfd1_div1_gate", base + 0x608, 16, 6); - clks[IMX8ULP_CLK_PLL4_PFD1_DIV2] = imx_clk_hw_divider("pll4_pfd1_div2", "pll4_pfd1_div2_gate", base + 0x608, 24, 6); - clks[IMX8ULP_CLK_PLL4_PFD2_DIV1] = imx_clk_hw_divider("pll4_pfd2_div1", "pll4_pfd2_div1_gate", base + 0x60c, 0, 6); - clks[IMX8ULP_CLK_PLL4_PFD2_DIV2] = imx_clk_hw_divider("pll4_pfd2_div2", "pll4_pfd2_div2_gate", base + 0x60c, 8, 6); - clks[IMX8ULP_CLK_PLL4_PFD3_DIV1] = imx_clk_hw_divider("pll4_pfd3_div1", "pll4_pfd3_div1_gate", base + 0x60c, 16, 6); - clks[IMX8ULP_CLK_PLL4_PFD3_DIV2] = imx_clk_hw_divider("pll4_pfd3_div2", "pll4_pfd3_div2_gate", base + 0x60c, 24, 6); + clks[IMX8ULP_CLK_PLL4_PFD0_DIV1] = imx_clk_hw_divider_closest("pll4_pfd0_div1", "pll4_pfd0_div1_gate", base + 0x608, 0, 6); + clks[IMX8ULP_CLK_PLL4_PFD0_DIV2] = imx_clk_hw_divider_closest("pll4_pfd0_div2", "pll4_pfd0_div2_gate", base + 0x608, 8, 6); + clks[IMX8ULP_CLK_PLL4_PFD1_DIV1] = imx_clk_hw_divider_closest("pll4_pfd1_div1", "pll4_pfd1_div1_gate", base + 0x608, 16, 6); + clks[IMX8ULP_CLK_PLL4_PFD1_DIV2] = imx_clk_hw_divider_closest("pll4_pfd1_div2", "pll4_pfd1_div2_gate", base + 0x608, 24, 6); + clks[IMX8ULP_CLK_PLL4_PFD2_DIV1] = imx_clk_hw_divider_closest("pll4_pfd2_div1", "pll4_pfd2_div1_gate", base + 0x60c, 0, 6); + clks[IMX8ULP_CLK_PLL4_PFD2_DIV2] = imx_clk_hw_divider_closest("pll4_pfd2_div2", "pll4_pfd2_div2_gate", base + 0x60c, 8, 6); + clks[IMX8ULP_CLK_PLL4_PFD3_DIV1] = imx_clk_hw_divider_closest("pll4_pfd3_div1", "pll4_pfd3_div1_gate", base + 0x60c, 16, 6); + clks[IMX8ULP_CLK_PLL4_PFD3_DIV2] = imx_clk_hw_divider_closest("pll4_pfd3_div2", "pll4_pfd3_div2_gate", base + 0x60c, 24, 6); clks[IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE] = imx_clk_hw_gate_dis("cgc2_sosc_div1_gate", "sosc", base + 0x108, 7); clks[IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE] = imx_clk_hw_gate_dis("cgc2_sosc_div2_gate", "sosc", base + 0x108, 15); @@ -333,7 +333,6 @@ clks[IMX8ULP_CLK_WDOG4] = imx8ulp_clk_hw_composite("wdog4", pcc3_periph_bus_sels, ARRAY_SIZE(pcc3_periph_bus_sels), true, true, true, base + 0xac, 1); clks[IMX8ULP_CLK_LPIT1] = imx8ulp_clk_hw_composite("lpit1", pcc3_periph_bus_sels, ARRAY_SIZE(pcc3_periph_bus_sels), true, true, true, base + 0xc8, 1); clks[IMX8ULP_CLK_TPM4] = imx8ulp_clk_hw_composite("tpm4", pcc3_periph_bus_sels, ARRAY_SIZE(pcc3_periph_bus_sels), true, true, true, base + 0xcc, 1); - clks[IMX8ULP_CLK_TPM5] = imx8ulp_clk_hw_composite("tpm5", pcc3_periph_bus_sels, ARRAY_SIZE(pcc3_periph_bus_sels), true, true, true, base + 0xd0, 1); clks[IMX8ULP_CLK_FLEXIO1] = imx8ulp_clk_hw_composite("flexio1", pcc3_periph_bus_sels, ARRAY_SIZE(pcc3_periph_bus_sels), true, true, true, base + 0xd4, 1); clks[IMX8ULP_CLK_I3C2] = imx8ulp_clk_hw_composite("i3c2", pcc3_periph_bus_sels, ARRAY_SIZE(pcc3_periph_bus_sels), true, true, true, base + 0xd8, 1); clks[IMX8ULP_CLK_LPI2C4] = imx8ulp_clk_hw_composite("lpi2c4", pcc3_periph_bus_sels, ARRAY_SIZE(pcc3_periph_bus_sels), true, true, true, base + 0xdc, 1); @@ -376,8 +375,9 @@ clks[IMX8ULP_CLK_DMA1_CH29] = imx_clk_hw_gate("pcc_dma1_ch29", "xbar_ad_divplat", base + 0x7c, 30); clks[IMX8ULP_CLK_DMA1_CH30] = imx_clk_hw_gate("pcc_dma1_ch30", "xbar_ad_divplat", base + 0x80, 30); clks[IMX8ULP_CLK_DMA1_CH31] = imx_clk_hw_gate("pcc_dma1_ch31", "xbar_ad_divplat", base + 0x84, 30); - clks[IMX8ULP_CLK_MU0_B] = imx_clk_hw_gate("mu0_b", "xbar_ad_divplat", base + 0x88, 30); + clks[IMX8ULP_CLK_MU0_B] = imx_clk_hw_gate_flags("mu0_b", "xbar_ad_divplat", base + 0x88, 30, CLK_IS_CRITICAL); clks[IMX8ULP_CLK_MU3_A] = imx_clk_hw_gate("mu3_a", "xbar_ad_divplat", base + 0x8c, 30); + clks[IMX8ULP_CLK_TPM5] = imx_clk_hw_gate_flags("tpm5", "sosc_div2", base + 0xd0, 30, CLK_IS_CRITICAL); imx_check_clk_hws(clks, clk_data->num); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx93.c linux-imx-phytec/drivers/clk/imx/clk-imx93.c --- linux-6.1.55/drivers/clk/imx/clk-imx93.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-imx93.c 2024-06-19 12:33:59.560214112 +0200 @@ -3,6 +3,7 @@ * Copyright 2021 NXP. */ +#include #include #include #include @@ -32,7 +33,9 @@ static u32 share_count_sai2; static u32 share_count_sai3; static u32 share_count_mub; +static u32 share_count_pdm; +static const char *a55_core_sels[] = {"a55_alt", "arm_pll"}; static const char *parent_names[MAX_SEL][4] = { {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll"}, {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2"}, @@ -55,7 +58,7 @@ /* a55/m33/bus critical clk for system run */ { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL }, { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, - { IMX93_CLK_A55, "a55_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL }, { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, @@ -64,13 +67,9 @@ { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, }, { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, }, { IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_LPIT1, "lpit1_root", 0x0600, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_LPIT2, "lpit2_root", 0x0680, LOW_SPEED_IO_SEL, }, { IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, }, { IMX93_CLK_LPTMR2, "lptmr2_root", 0x0780, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_TPM1, "tpm1_root", 0x0800, TPM_SEL, }, { IMX93_CLK_TPM2, "tpm2_root", 0x0880, TPM_SEL, }, - { IMX93_CLK_TPM3, "tpm3_root", 0x0900, TPM_SEL, }, { IMX93_CLK_TPM4, "tpm4_root", 0x0980, TPM_SEL, }, { IMX93_CLK_TPM5, "tpm5_root", 0x0a00, TPM_SEL, }, { IMX93_CLK_TPM6, "tpm6_root", 0x0a80, TPM_SEL, }, @@ -113,10 +112,11 @@ { IMX93_CLK_CCM_CKO2, "ccm_cko2_root", 0x1d00, CKO2_SEL, }, { IMX93_CLK_CCM_CKO3, "ccm_cko3_root", 0x1d80, CKO1_SEL, }, { IMX93_CLK_CCM_CKO4, "ccm_cko4_root", 0x1e00, CKO2_SEL, }, - { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL}, { IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", 0x1f00, LOW_SPEED_IO_SEL, }, { IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, }, { IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, }, + { IMX93_CLK_NIC_AXI, "nic_axi_root", 0x2080, FAST_SEL, CLK_IS_CRITICAL, }, { IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, }, { IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, }, { IMX93_CLK_MEDIA_AXI, "media_axi_root", 0x2280, FAST_SEL, }, @@ -153,7 +153,7 @@ unsigned long flags; u32 *shared_count; } ccgr_array[] = { - { IMX93_CLK_A55_GATE, "a55", "a55_root", 0x8000, }, + { IMX93_CLK_A55_GATE, "a55_alt", "a55_alt_root", 0x8000, }, /* M33 critical clk for system run */ { IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL }, { IMX93_CLK_ADC1_GATE, "adc1", "adc_root", 0x82c0, }, @@ -177,13 +177,13 @@ { IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, }, { IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, }, { IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, }, - { IMX93_CLK_LPIT1_GATE, "lpit1", "lpit1_root", 0x8a00, }, - { IMX93_CLK_LPIT2_GATE, "lpit2", "lpit2_root", 0x8a40, }, + { IMX93_CLK_LPIT1_GATE, "lpit1", "bus_aon_root", 0x8a00, }, + { IMX93_CLK_LPIT2_GATE, "lpit2", "bus_wakeup_root", 0x8a40, }, { IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, }, { IMX93_CLK_LPTMR2_GATE, "lptmr2", "lptmr2_root", 0x8ac0, }, - { IMX93_CLK_TPM1_GATE, "tpm1", "tpm1_root", 0x8b00, }, + { IMX93_CLK_TPM1_GATE, "tpm1", "bus_aon_root", 0x8b00, }, { IMX93_CLK_TPM2_GATE, "tpm2", "tpm2_root", 0x8b40, }, - { IMX93_CLK_TPM3_GATE, "tpm3", "tpm3_root", 0x8b80, }, + { IMX93_CLK_TPM3_GATE, "tpm3", "bus_wakeup_root", 0x8b80, }, { IMX93_CLK_TPM4_GATE, "tpm4", "tpm4_root", 0x8bc0, }, { IMX93_CLK_TPM5_GATE, "tpm5", "tpm5_root", 0x8c00, }, { IMX93_CLK_TPM6_GATE, "tpm6", "tpm6_root", 0x8c40, }, @@ -232,17 +232,18 @@ { IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, }, { IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_axi_root", 0x9700, }, { IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, }, - { IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, }, + { IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, CLK_IGNORE_UNUSED }, { IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "osc_24m", 0x9a80, }, - { IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, }, + { IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, 0, &share_count_pdm}, + { IMX93_CLK_PDM_IPG, "pdm_ipg_clk", "bus_aon_root", 0x9ac0, 0, &share_count_pdm}, { IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, }, { IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, }, { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, }, { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, }, - { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, }, - { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, }, - { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, }, - { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, }, + { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, CLK_IGNORE_UNUSED, }, + { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, CLK_IGNORE_UNUSED, }, + { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, CLK_IGNORE_UNUSED, }, + { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, CLK_IS_CRITICAL }, { IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, }, { IMX93_CLK_TSTMR2_GATE, "tstmr2", "bus_wakeup_root", 0x9f00, }, { IMX93_CLK_TMC_GATE, "tmc", "osc_24m", 0x9f40, }, @@ -252,6 +253,34 @@ static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **clks; +static int imx_clk_init_on(struct device_node *np, + struct clk_hw * const clks[]) +{ + u32 *array; + int i, ret, elems; + + elems = of_property_count_u32_elems(np, "init-on-array"); + if (elems < 0) + return elems; + array = kcalloc(elems, sizeof(elems), GFP_KERNEL); + if (!array) + return -ENOMEM; + + ret = of_property_read_u32_array(np, "init-on-array", array, elems); + if (ret) + return ret; + + for (i = 0; i < elems; i++) { + ret = clk_prepare_enable(clks[array[i]]->clk); + if (ret) + pr_err("clk_prepare_enable failed %d\n", array[i]); + } + + kfree(array); + + return 0; +} + static int imx93_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -292,6 +321,8 @@ goto unregister_hws; } + clks[IMX93_CLK_ARM_PLL] = imx_clk_fracn_gppll("arm_pll", "osc_24m", anatop_base + 0x1000, + &imx_fracn_gppll); clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", anatop_base + 0x1200, &imx_fracn_gppll); clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", anatop_base + 0x1400, @@ -319,6 +350,12 @@ ccgr->shared_count); } + clks[IMX93_CLK_A55_SEL] = imx_clk_hw_mux2("a55_sel", base + 0x4820, 0, 1, a55_core_sels, ARRAY_SIZE(a55_core_sels)); + clks[IMX93_CLK_A55_CORE] = imx_clk_hw_cpu("a55_core", "a55_sel", clks[IMX93_CLK_A55_SEL]->clk, + clks[IMX93_CLK_A55_SEL]->clk, + clks[IMX93_CLK_ARM_PLL]->clk, + clks[IMX93_CLK_A55_GATE]->clk); + imx_check_clk_hws(clks, IMX93_CLK_END); ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); @@ -327,6 +364,8 @@ goto unregister_hws; } + imx_clk_init_on(np, clks); + return 0; unregister_hws: @@ -350,6 +389,8 @@ }, }; module_platform_driver(imx93_clk_driver); +module_param(mcore_booted, bool, S_IRUGO); +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not"); MODULE_DESCRIPTION("NXP i.MX93 clock driver"); MODULE_LICENSE("GPL v2"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx-acm-utils.c linux-imx-phytec/drivers/clk/imx/clk-imx-acm-utils.c --- linux-6.1.55/drivers/clk/imx/clk-imx-acm-utils.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/imx/clk-imx-acm-utils.c 2024-06-19 12:33:59.552213975 +0200 @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2020 NXP + +#include +#include +#include "clk-imx-acm-utils.h" + +/** + * clk_imx_acm_attach_pm_domains + */ +int clk_imx_acm_attach_pm_domains(struct device *dev, + struct clk_imx_acm_pm_domains *dev_pm) +{ + int ret; + int i; + + dev_pm->num_domains = of_count_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells"); + if (dev_pm->num_domains <= 1) + return 0; + + dev_pm->pd_dev = devm_kmalloc_array(dev, dev_pm->num_domains, + sizeof(*dev_pm->pd_dev), + GFP_KERNEL); + if (!dev_pm->pd_dev) + return -ENOMEM; + + dev_pm->pd_dev_link = devm_kmalloc_array(dev, + dev_pm->num_domains, + sizeof(*dev_pm->pd_dev_link), + GFP_KERNEL); + if (!dev_pm->pd_dev_link) + return -ENOMEM; + + for (i = 0; i < dev_pm->num_domains; i++) { + dev_pm->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i); + if (IS_ERR(dev_pm->pd_dev[i])) + return PTR_ERR(dev_pm->pd_dev[i]); + + dev_pm->pd_dev_link[i] = device_link_add(dev, + dev_pm->pd_dev[i], + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (IS_ERR(dev_pm->pd_dev_link[i])) { + dev_pm_domain_detach(dev_pm->pd_dev[i], false); + ret = PTR_ERR(dev_pm->pd_dev_link[i]); + goto detach_pm; + } + } + return 0; + +detach_pm: + while (--i >= 0) { + device_link_del(dev_pm->pd_dev_link[i]); + dev_pm_domain_detach(dev_pm->pd_dev[i], false); + } + return ret; +} + +/** + * fsl_dev_detach_pm_domains + */ +int clk_imx_acm_detach_pm_domains(struct device *dev, + struct clk_imx_acm_pm_domains *dev_pm) +{ + int i; + + if (dev_pm->num_domains <= 1) + return 0; + + for (i = 0; i < dev_pm->num_domains; i++) { + device_link_del(dev_pm->pd_dev_link[i]); + dev_pm_domain_detach(dev_pm->pd_dev[i], false); + } + + return 0; +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-imx-acm-utils.h linux-imx-phytec/drivers/clk/imx/clk-imx-acm-utils.h --- linux-6.1.55/drivers/clk/imx/clk-imx-acm-utils.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/imx/clk-imx-acm-utils.h 2024-06-19 12:33:59.552213975 +0200 @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright 2020 NXP */ + +#ifndef _CLK_IMX_ACM_UTILS_H +#define _CLK_IMX_ACM_UTILS_H + +#include + +struct clk_imx_acm_pm_domains { + struct device **pd_dev; + struct device_link **pd_dev_link; + int num_domains; +}; + +int clk_imx_acm_attach_pm_domains(struct device *dev, + struct clk_imx_acm_pm_domains *dev_pm); +int clk_imx_acm_detach_pm_domains(struct device *dev, + struct clk_imx_acm_pm_domains *dev_pm); +#endif /* _CLK_IMX_ACM_UTILS_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-lpcg-scu.c linux-imx-phytec/drivers/clk/imx/clk-lpcg-scu.c --- linux-6.1.55/drivers/clk/imx/clk-lpcg-scu.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-lpcg-scu.c 2024-06-19 12:33:59.560214112 +0200 @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -41,6 +42,31 @@ #define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw) +/* e10858 -LPCG clock gating register synchronization errata */ +static void do_lpcg_workaround(u32 rate, void __iomem *reg, u32 val) +{ + writel(val, reg); + + if (rate >= 24000000 || rate == 0) { + u32 reg1; + + /* + * The time taken to access the LPCG registers from the AP core + * through the interconnect is longer than the minimum delay + * of 4 clock cycles required by the errata. + * Adding a readl will provide sufficient delay to prevent + * back-to-back writes. + */ + reg1 = readl(reg); + } else { + /* + * For clocks running below 24MHz, wait a minimum of + * 4 clock cycles. + */ + ndelay(4 * (DIV_ROUND_UP(1000000000, rate))); + } +} + static int clk_lpcg_scu_enable(struct clk_hw *hw) { struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); @@ -57,7 +83,8 @@ val |= CLK_GATE_SCU_LPCG_HW_SEL; reg |= val << clk->bit_idx; - writel(reg, clk->reg); + + do_lpcg_workaround(clk_hw_get_rate(hw), clk->reg, reg); spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); @@ -74,7 +101,7 @@ reg = readl_relaxed(clk->reg); reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); - writel(reg, clk->reg); + do_lpcg_workaround(clk_hw_get_rate(hw), clk->reg, reg); spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); } @@ -135,6 +162,9 @@ { struct clk_lpcg_scu *clk = dev_get_drvdata(dev); + if (!strncmp("hdmi_lpcg", clk_hw_get_name(&clk->hw), strlen("hdmi_lpcg"))) + return 0; + clk->state = readl_relaxed(clk->reg); dev_dbg(dev, "save lpcg state 0x%x\n", clk->state); @@ -145,13 +175,16 @@ { struct clk_lpcg_scu *clk = dev_get_drvdata(dev); + if (!strncmp("hdmi_lpcg", clk_hw_get_name(&clk->hw), strlen("hdmi_lpcg"))) + return 0; + /* * FIXME: Sometimes writes don't work unless the CPU issues * them twice */ writel(clk->state, clk->reg); - writel(clk->state, clk->reg); + do_lpcg_workaround(0, clk->reg, clk->state); dev_dbg(dev, "restore lpcg state 0x%x\n", clk->state); return 0; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-pfd.c linux-imx-phytec/drivers/clk/imx/clk-pfd.c --- linux-6.1.55/drivers/clk/imx/clk-pfd.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-pfd.c 2024-06-19 12:33:59.560214112 +0200 @@ -5,9 +5,11 @@ */ #include +#include #include #include #include +#include #include "clk.h" /** @@ -32,20 +34,57 @@ #define CLR 0x8 #define OTG 0xc -static int clk_pfd_enable(struct clk_hw *hw) +static void clk_pfd_do_hardware(struct clk_pfd *pfd, bool enable) +{ + if (enable) + writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); + else + writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); +} + +static void clk_pfd_do_shared_clks(struct clk_hw *hw, bool enable) { struct clk_pfd *pfd = to_clk_pfd(hw); - writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); + if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { +#ifdef CONFIG_SOC_IMX6SX + if (!amp_power_mutex || !shared_mem) { + if (enable) + clk_pfd_do_hardware(pfd, enable); + return; + } + + imx_sema4_mutex_lock(amp_power_mutex); + if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || + shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + if (!imx_update_shared_mem(hw, enable)) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + clk_pfd_do_hardware(pfd, enable); + + imx_sema4_mutex_unlock(amp_power_mutex); +#endif + } else { + clk_pfd_do_hardware(pfd, enable); + } +} + +static int clk_pfd_enable(struct clk_hw *hw) +{ + clk_pfd_do_shared_clks(hw, true); return 0; } static void clk_pfd_disable(struct clk_hw *hw) { - struct clk_pfd *pfd = to_clk_pfd(hw); - - writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); + clk_pfd_do_shared_clks(hw, false); } static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-pll14xx.c linux-imx-phytec/drivers/clk/imx/clk-pll14xx.c --- linux-6.1.55/drivers/clk/imx/clk-pll14xx.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-pll14xx.c 2024-06-19 12:33:59.560214112 +0200 @@ -62,6 +62,8 @@ PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(594000000U, 198, 2, 2, 0), PLL_1443X_RATE(519750000U, 173, 2, 2, 16384), + PLL_1443X_RATE(393216000U, 262, 2, 3, 9437), + PLL_1443X_RATE(361267200U, 361, 3, 3, 17511), }; struct imx_pll14xx_clk imx_1443x_pll = { @@ -102,7 +104,22 @@ static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, int sdiv, int kdiv, unsigned long prate) { + const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; + unsigned long rate = 0; u64 fvco = prate; + int i; + + /* + * Sometimes, the recalculated rate has deviation due to + * the frac part. So find the accurate pll rate from the table + * first, if no match rate in the table, use the rate calculated + * from the equation below. + */ + for (i = 0; i < pll->rate_count; i++) { + if (rate_table[i].pdiv == pdiv && rate_table[i].mdiv == mdiv && + rate_table[i].sdiv == sdiv && rate_table[i].kdiv == kdiv) + rate = rate_table[i].rate; + } /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ fvco *= (mdiv * 65536 + kdiv); @@ -110,7 +127,7 @@ do_div(fvco, pdiv << sdiv); - return fvco; + return rate ? (unsigned long) rate : (unsigned long)fvco; } static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, @@ -460,6 +477,26 @@ writel_relaxed(val, pll->base + GNRL_CTL); } +void clk_set_delta_k(struct clk_hw *hw, short int delta_k) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + short int k; + u32 val; + + val = readl_relaxed(pll->base + 8); + k = (val & KDIV_MASK) + delta_k; + writel_relaxed(k, pll->base + 8); +} + +void clk_get_pll_setting(struct clk_hw *hw, u32 *pll_div_ctrl0, + u32 *pll_div_ctrl1) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + + *pll_div_ctrl0 = readl_relaxed(pll->base + 4); + *pll_div_ctrl1 = readl_relaxed(pll->base + 8); +} + static const struct clk_ops clk_pll1416x_ops = { .prepare = clk_pll14xx_prepare, .unprepare = clk_pll14xx_unprepare, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-pllv3.c linux-imx-phytec/drivers/clk/imx/clk-pllv3.c --- linux-6.1.55/drivers/clk/imx/clk-pllv3.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-pllv3.c 2024-06-19 12:33:59.560214112 +0200 @@ -8,9 +8,11 @@ #include #include #include +#include #include #include #include +#include #include "clk.h" #define PLL_NUM_OFFSET 0x10 @@ -65,36 +67,82 @@ if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) return 0; - return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK, - 500, PLL_LOCK_TIMEOUT); + if (!(imx_src_is_m4_enabled() && clk_on_imx6sx())) + return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK, + 500, PLL_LOCK_TIMEOUT); + else + return readl_relaxed_poll_timeout_atomic(pll->base, val, val & BM_PLL_LOCK, + 10, PLL_LOCK_TIMEOUT); } -static int clk_pllv3_prepare(struct clk_hw *hw) +static int clk_pllv3_do_hardware(struct clk_hw *hw, bool enable) { struct clk_pllv3 *pll = to_clk_pllv3(hw); + int ret; u32 val; val = readl_relaxed(pll->base); - if (pll->powerup_set) - val |= pll->power_bit; - else - val &= ~pll->power_bit; - writel_relaxed(val, pll->base); + if (enable) { + if (pll->powerup_set) + val |= pll->power_bit; + else + val &= ~pll->power_bit; + writel_relaxed(val, pll->base); + + ret = clk_pllv3_wait_lock(pll); + if (ret) + return ret; + } else { + if (pll->powerup_set) + val &= ~pll->power_bit; + else + val |= pll->power_bit; + writel_relaxed(val, pll->base); + } - return clk_pllv3_wait_lock(pll); + return 0; } -static void clk_pllv3_unprepare(struct clk_hw *hw) +static void clk_pllv3_do_shared_clks(struct clk_hw *hw, bool enable) { - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 val; + if (imx_src_is_m4_enabled() && clk_on_imx6sx()) { +#ifdef CONFIG_SOC_IMX6SX + if (!amp_power_mutex || !shared_mem) { + if (enable) + clk_pllv3_do_hardware(hw, enable); + return; + } + + imx_sema4_mutex_lock(amp_power_mutex); + if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER || + shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + + if (!imx_update_shared_mem(hw, enable)) { + imx_sema4_mutex_unlock(amp_power_mutex); + return; + } + clk_pllv3_do_hardware(hw, enable); + + imx_sema4_mutex_unlock(amp_power_mutex); +#endif + } else { + clk_pllv3_do_hardware(hw, enable); + } +} - val = readl_relaxed(pll->base); - if (pll->powerup_set) - val &= ~pll->power_bit; - else - val |= pll->power_bit; - writel_relaxed(val, pll->base); +static int clk_pllv3_prepare(struct clk_hw *hw) +{ + clk_pllv3_do_shared_clks(hw, true); + + return 0; +} + +static void clk_pllv3_unprepare(struct clk_hw *hw) +{ + clk_pllv3_do_shared_clks(hw, false); } static int clk_pllv3_is_prepared(struct clk_hw *hw) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/clk-scu.c linux-imx-phytec/drivers/clk/imx/clk-scu.c --- linux-6.1.55/drivers/clk/imx/clk-scu.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/clk-scu.c 2024-06-19 12:33:59.560214112 +0200 @@ -9,11 +9,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include "clk-scu.h" @@ -577,6 +579,7 @@ clk->rate = clk_scu_recalc_rate(&clk->hw, 0); else clk->rate = clk_hw_get_rate(&clk->hw); + clk->is_enabled = clk_hw_is_enabled(&clk->hw); if (clk->parent) @@ -650,9 +653,34 @@ rsrc_id == IMX_SC_R_A72) return 0; + /* + * Temp fix to avoid the uart clk attached pd power off uart_0 + */ + if (rsrc_id == IMX_SC_R_UART_0 && xen_initial_domain()) + return 0; + return of_genpd_add_device(&genpdspec, dev); } +static bool imx_clk_is_resource_owned(u32 rsrc) +{ + /* + * A-core resources are special. SCFW reports they are not "owned" by + * current partition but linux can still adjust them for cpufreq. + * + * So force this to return false when running as a VM guest and always + * true otherwise. + */ + if (rsrc == IMX_SC_R_A53 || rsrc == IMX_SC_R_A72 || + rsrc == IMX_SC_R_A35) { + if (xen_domain() && !xen_initial_domain()) + return false; + return true; + } + + return imx_sc_rm_is_resource_owned(ccm_ipc_handle, rsrc); +} + struct clk_hw *imx_clk_scu_alloc_dev(const char *name, const char * const *parents, int num_parents, u32 rsrc_id, u8 clk_type) @@ -670,6 +698,9 @@ if (!imx_scu_clk_is_valid(rsrc_id)) return ERR_PTR(-EINVAL); + if (!imx_clk_is_resource_owned(rsrc_id)) + return NULL; + pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE); if (!pdev) { pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n", diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/Kconfig linux-imx-phytec/drivers/clk/imx/Kconfig --- linux-6.1.55/drivers/clk/imx/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/Kconfig 2024-06-19 12:33:59.552213975 +0200 @@ -103,6 +103,7 @@ tristate "IMX8ULP CCM Clock Driver" depends on ARCH_MXC || COMPILE_TEST select MXC_CLK + select RESET_CONTROLLER help Build the driver for i.MX8ULP CCM Clock Driver diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/imx/Makefile linux-imx-phytec/drivers/clk/imx/Makefile --- linux-6.1.55/drivers/clk/imx/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/imx/Makefile 2024-06-19 12:33:59.552213975 +0200 @@ -26,7 +26,7 @@ obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctrl.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_CLK_IMX93) += clk-imx93.o @@ -36,6 +36,7 @@ clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o \ clk-imx8dxl-rsrc.o clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o +obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp-acm.o clk-imx8qm-acm.o clk-imx8dxl-acm.o clk-imx-acm-utils.o obj-$(CONFIG_CLK_IMX8ULP) += clk-imx8ulp.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/Kconfig linux-imx-phytec/drivers/clk/Kconfig --- linux-6.1.55/drivers/clk/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/Kconfig 2024-06-19 12:33:59.524213496 +0200 @@ -457,6 +457,7 @@ source "drivers/clk/ralink/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/rockchip/Kconfig" +source "drivers/clk/s32/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/socfpga/Kconfig" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/Makefile linux-imx-phytec/drivers/clk/Makefile --- linux-6.1.55/drivers/clk/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clk/Makefile 2024-06-19 12:33:59.524213496 +0200 @@ -110,6 +110,7 @@ obj-y += ralink/ obj-y += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_S32) += s32/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-y += socfpga/ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/clk-core.c linux-imx-phytec/drivers/clk/s32/clk-core.c --- linux-6.1.55/drivers/clk/s32/clk-core.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/clk-core.c 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#include +#include +#include +#include +#include +#include "clk.h" + +void __init s32_check_clocks(struct clk *clks[], unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + if (IS_ERR(clks[i])) + pr_err("S32 clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); +} + +static struct clk * __init s32_obtain_fixed_clock_from_dt(const char *name) +{ + struct of_phandle_args phandle; + struct clk *clk = ERR_PTR(-ENODEV); + char *path; + + path = kasprintf(GFP_KERNEL, "/clocks/%s", name); + if (!path) + return ERR_PTR(-ENOMEM); + + phandle.np = of_find_node_by_path(path); + kfree(path); + + if (phandle.np) { + clk = of_clk_get_from_provider(&phandle); + of_node_put(phandle.np); + } + return clk; +} + +struct clk * __init s32_obtain_fixed_clock( + const char *name, unsigned long rate) +{ + struct clk *clk; + + clk = s32_obtain_fixed_clock_from_dt(name); + if (IS_ERR(clk)) + clk = s32_clk_fixed(name, rate); + return clk; +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/clk.h linux-imx-phytec/drivers/clk/s32/clk.h --- linux-6.1.55/drivers/clk/s32/clk.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/clk.h 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#ifndef __MACH_S32_CLK_H +#define __MACH_S32_CLK_H + +#include +#include + +#define PNAME(x) \ + static const char *x[] __initconst + +void s32_check_clocks(struct clk *clks[], unsigned int count); + +struct clk *s32_obtain_fixed_clock( + const char *name, unsigned long rate); + +static inline struct clk *s32_clk_fixed(const char *name, unsigned long rate) +{ + return clk_register_fixed_rate(NULL, name, NULL, 0, rate); +} + +static inline struct clk *s32_clk_divider(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width, + spinlock_t *lock) +{ + struct clk *tmp_clk = clk_register_divider(NULL, name, parent, + CLK_SET_RATE_PARENT, + reg, shift, width, 0, lock); + + return tmp_clk; +} + +static inline struct clk *s32_clk_mux(const char *name, void __iomem *reg, + u8 shift, u8 width, const char **parents, + u8 num_parents, spinlock_t *lock) +{ + return clk_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, lock); +} + +static inline struct clk *s32_clk_fixed_factor(const char *name, + const char *parent, + unsigned int mult, + unsigned int div) +{ + return clk_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, mult, div); +} + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/Kconfig linux-imx-phytec/drivers/clk/s32/Kconfig --- linux-6.1.55/drivers/clk/s32/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/Kconfig 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,4 @@ +config ARCH_S32_CLK + bool "Enable S32 CLK Framework" + help + Support for the Clock Framework on S32 SoCs. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/Makefile linux-imx-phytec/drivers/clk/s32/Makefile --- linux-6.1.55/drivers/clk/s32/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/Makefile 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,2 @@ +obj-$(CONFIG_ARCH_S32_CLK) += clk-core.o +obj-$(CONFIG_ARCH_S32_CLK) += s32v234/ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/s32v234/clk.c linux-imx-phytec/drivers/clk/s32/s32v234/clk.c --- linux-6.1.55/drivers/clk/s32/s32v234/clk.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/s32v234/clk.c 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#include +#include +#include + +#include "clk.h" + +static void __iomem *mc_cgm0_base; +static void __iomem *mc_cgm1_base; +static void __iomem *mc_cgm2_base; +static void __iomem *mc_cgm3_base; +static void __iomem *mc_me_base; +static void __iomem *src_base; + +DEFINE_SPINLOCK(s32v234_lock); + +/* sources for multiplexer clocks, this is used multiple times */ +PNAME(osc_sels) = {"firc", "fxosc", }; + +PNAME(sys_sels) = {"firc", "fxosc", "armpll_dfs0", }; + +PNAME(can_sels) = {"firc", "fxosc", "dummy", + "periphpll_phi0_div5", }; + +PNAME(lin_sels) = {"firc", "fxosc", "dummy", + "periphpll_phi0_div3", "dummy", "dummy", + "dummy", "dummy", "sys6",}; + +PNAME(sdhc_sels) = {"firc", "fxosc", "dummy", "dummy", + "enetpll_dfs3",}; + +PNAME(enet_sels) = {"firc", "fxosc", "dummy", + "dummy", "enetpll_phi0",}; + +PNAME(enet_time_sels) = {"firc", "fxosc", "dummy", + "dummy", "enetpll_phi0",}; + +static struct clk *clk[S32V234_CLK_END]; +static struct clk_onecell_data clk_data; + +static void __init s32v234_clocks_init(struct device_node *mc_cgm0_node) +{ + struct device_node *np; + + clk[S32V234_CLK_DUMMY] = s32_clk_fixed("dummy", 0); + clk[S32V234_CLK_FXOSC] = s32_obtain_fixed_clock("fxosc", 0); + clk[S32V234_CLK_FIRC] = s32_obtain_fixed_clock("firc", 0); + + np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_me"); + mc_me_base = of_iomap(np, 0); + if (WARN_ON(!mc_me_base)) + return; + + np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-src"); + src_base = of_iomap(np, 0); + if (WARN_ON(!src_base)) + return; + + np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_cgm1"); + mc_cgm1_base = of_iomap(np, 0); + if (WARN_ON(!mc_cgm1_base)) + return; + + np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_cgm2"); + mc_cgm2_base = of_iomap(np, 0); + if (WARN_ON(!mc_cgm2_base)) + return; + + np = of_find_compatible_node(NULL, NULL, "fsl,s32v234-mc_cgm3"); + mc_cgm3_base = of_iomap(np, 0); + if (WARN_ON(!mc_cgm3_base)) + return; + + np = mc_cgm0_node; + mc_cgm0_base = of_iomap(np, 0); + if (WARN_ON(!mc_cgm0_base)) + return; + + enable_cpumodes_onperipheralconfig(mc_me_base, MC_ME_RUN_PCn_DRUN | + MC_ME_RUN_PCn_RUN0 | + MC_ME_RUN_PCn_RUN1 | + MC_ME_RUN_PCn_RUN2 | + MC_ME_RUN_PCn_RUN3, + 0); + + /* turn on XOSC and FIRC */ + enable_clocks_sources(MC_ME_MODE_MC_MVRON, MC_ME_MODE_MC_XOSCON | + MC_ME_MODE_MC_FIRCON, + MC_ME_RUNn_MC(mc_me_base, 0)); + + /* transition the core to RUN0 mode */ + entry_to_target_mode(mc_me_base, MC_ME_MCTL_RUN0); + + clk[S32V234_CLK_ARMPLL_SRC_SEL] = s32_clk_mux("armpll_sel", + SRC_GPR1, SRC_GPR1_ARMPLL_SRC_SEL_OFFSET, + SRC_GPR1_XPLL_SRC_SEL_SIZE, + osc_sels, ARRAY_SIZE(osc_sels), &s32v234_lock); + + clk[S32V234_CLK_PERIPHPLL_SRC_SEL] = s32_clk_mux("periphpll_sel", + SRC_GPR1, SRC_GPR1_PERIPHPLL_SRC_SEL_OFFSET, + SRC_GPR1_XPLL_SRC_SEL_SIZE, + osc_sels, ARRAY_SIZE(osc_sels), &s32v234_lock); + + clk[S32V234_CLK_ENETPLL_SRC_SEL] = s32_clk_mux("enetpll_sel", + SRC_GPR1, SRC_GPR1_ENETPLL_SRC_SEL_OFFSET, + SRC_GPR1_XPLL_SRC_SEL_SIZE, + osc_sels, ARRAY_SIZE(osc_sels), &s32v234_lock); + + /* ARM_PLL */ + clk[S32V234_CLK_ARMPLL_VCO] = s32v234_clk_plldig(S32_PLLDIG_ARM, + "armpll_vco", "armpll_sel", ARMPLL_PLLDIG(mc_cgm0_base), + ARMPLL_PLLDIG_PLLDV_MFD, ARMPLL_PLLDIG_PLLDV_MFN, + ARMPLL_PLLDIG_PLLDV_RFDPHI0, ARMPLL_PLLDIG_PLLDV_RFDPHI1); + + clk[S32V234_CLK_ARMPLL_PHI0] = s32v234_clk_plldig_phi(S32_PLLDIG_ARM, + "armpll_phi0", "armpll_vco", + ARMPLL_PLLDIG(mc_cgm0_base), 0); + + clk[S32V234_CLK_ARMPLL_PHI1] = s32v234_clk_plldig_phi(S32_PLLDIG_ARM, + "armpll_phi1", "armpll_vco", + ARMPLL_PLLDIG(mc_cgm0_base), 1); + + clk[S32V234_CLK_ARMPLL_DFS0] = s32v234_clk_dfs(S32_PLLDIG_ARM, + "armpll_dfs0", "armpll_phi1", + ARMPLL_PLLDIG_DFS(mc_cgm0_base), 0, + ARMPLL_PLLDIG_DFS0_MFN); + + clk[S32V234_CLK_ARMPLL_DFS1] = s32v234_clk_dfs(S32_PLLDIG_ARM, + "armpll_dfs1", "armpll_phi1", + ARMPLL_PLLDIG_DFS(mc_cgm0_base), 1, + ARMPLL_PLLDIG_DFS1_MFN); + + clk[S32V234_CLK_ARMPLL_DFS2] = s32v234_clk_dfs(S32_PLLDIG_ARM, + "armpll_dfs2", "armpll_phi1", + ARMPLL_PLLDIG_DFS(mc_cgm0_base), 2, + ARMPLL_PLLDIG_DFS2_MFN); + + clk[S32V234_CLK_SYS_SEL] = s32_clk_mux("sys_sel", + MC_ME_RUNn_MC(mc_me_base, 0), + MC_ME_MODE_MC_SYSCLK_OFFSET, + MC_ME_MODE_MC_SYSCLK_SIZE, + sys_sels, ARRAY_SIZE(sys_sels), &s32v234_lock); + + clk[S32V234_CLK_SYS3] = s32_clk_divider("sys3", "sys_sel", + CGM_SC_DCn(mc_cgm0_base, 0), MC_CGM_SC_DCn_PREDIV_OFFSET, + MC_CGM_SC_DCn_PREDIV_SIZE, &s32v234_lock); + + clk[S32V234_CLK_SYS6] = s32_clk_divider("sys6", "sys_sel", + CGM_SC_DCn(mc_cgm0_base, 1), MC_CGM_SC_DCn_PREDIV_OFFSET, + MC_CGM_SC_DCn_PREDIV_SIZE, &s32v234_lock); + + clk[S32V234_CLK_SYS6_DIV2] = s32_clk_divider("sys6_div2", "sys_sel", + CGM_SC_DCn(mc_cgm0_base, 2), MC_CGM_SC_DCn_PREDIV_OFFSET, + MC_CGM_SC_DCn_PREDIV_SIZE, &s32v234_lock); + + /* PERIPH_PLL */ + clk[S32V234_CLK_PERIPHPLL_VCO] = s32v234_clk_plldig(S32_PLLDIG_PERIPH, + "periphpll_vco", "periphpll_sel", + PERIPHPLL_PLLDIG(mc_cgm0_base), + PERIPHPLL_PLLDIG_PLLDV_MFD, PERIPHPLL_PLLDIG_PLLDV_MFN, + PERIPHPLL_PLLDIG_PLLDV_RFDPHI0, + PERIPHPLL_PLLDIG_PLLDV_RFDPHI1); + + clk[S32V234_CLK_PERIPHPLL_PHI0] = + s32v234_clk_plldig_phi(S32_PLLDIG_PERIPH, + "periphpll_phi0", "periphpll_vco", + PERIPHPLL_PLLDIG(mc_cgm0_base), 0); + + clk[S32V234_CLK_PERIPHPLL_PHI1] = + s32v234_clk_plldig_phi(S32_PLLDIG_PERIPH, + "periphpll_phi1", "periphpll_vco", + PERIPHPLL_PLLDIG(mc_cgm0_base), 1); + + clk[S32V234_CLK_PERIPHPLL_PHI0_DIV3] = s32_clk_fixed_factor( + "periphpll_phi0_div3", "periphpll_phi0", 1, 3); + + clk[S32V234_CLK_PERIPHPLL_PHI0_DIV5] = s32_clk_fixed_factor( + "periphpll_phi0_div5", "periphpll_phi0", 1, 5); + + clk[S32V234_CLK_CAN_SEL] = s32_clk_mux("can_sel", + CGM_ACn_SC(mc_cgm0_base, 6), + MC_CGM_ACn_SEL_OFFSET, + MC_CGM_ACn_SEL_SIZE, + can_sels, ARRAY_SIZE(can_sels), &s32v234_lock); + + /* CAN Clock */ + clk[S32V234_CLK_CAN] = s32_clk_divider("can", "can_sel", + CGM_ACn_DCm(mc_cgm0_base, 6, 0), + MC_CGM_ACn_DCm_PREDIV_OFFSET, + MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); + + /* Lin Clock */ + clk[S32V234_CLK_LIN_SEL] = s32_clk_mux("lin_sel", + CGM_ACn_SC(mc_cgm0_base, 3), + MC_CGM_ACn_SEL_OFFSET, + MC_CGM_ACn_SEL_SIZE, + lin_sels, ARRAY_SIZE(lin_sels), &s32v234_lock); + + clk[S32V234_CLK_LIN] = s32_clk_divider("lin", "lin_sel", + CGM_ACn_DCm(mc_cgm0_base, 3, 0), + MC_CGM_ACn_DCm_PREDIV_OFFSET, + MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); + + clk[S32V234_CLK_LIN_IPG] = s32_clk_fixed_factor("lin_ipg", + "lin", 1, 2); + + /* enable PERIPHPLL */ + enable_clocks_sources(0, MC_ME_MODE_MC_PERIPHPLL, + MC_ME_RUNn_MC(mc_me_base, 0)); + + /* ENET_PLL */ + clk[S32V234_CLK_ENETPLL_VCO] = s32v234_clk_plldig(S32_PLLDIG_ENET, + "enetpll_vco", "enetpll_sel", ENETPLL_PLLDIG(mc_cgm0_base), + ENETPLL_PLLDIG_PLLDV_MFD, ENETPLL_PLLDIG_PLLDV_MFN, + ENETPLL_PLLDIG_PLLDV_RFDPHI0, ENETPLL_PLLDIG_PLLDV_RFDPHI1); + + clk[S32V234_CLK_ENETPLL_PHI0] = s32v234_clk_plldig_phi(S32_PLLDIG_ENET, + "enetpll_phi0", "enetpll_vco", + ENETPLL_PLLDIG(mc_cgm0_base), 0); + + clk[S32V234_CLK_ENETPLL_PHI1] = s32v234_clk_plldig_phi(S32_PLLDIG_ENET, + "enetpll_phi1", "enetpll_vco", + ENETPLL_PLLDIG(mc_cgm0_base), 1); + + clk[S32V234_CLK_ENETPLL_DFS0] = s32v234_clk_dfs(S32_PLLDIG_ENET, + "enetpll_dfs0", "enetpll_phi1", + ENETPLL_PLLDIG_DFS(mc_cgm0_base), 0, + ENETPLL_PLLDIG_DFS0_MFN); + + clk[S32V234_CLK_ENETPLL_DFS1] = s32v234_clk_dfs(S32_PLLDIG_ENET, + "enetpll_dfs1", "enetpll_phi1", + ENETPLL_PLLDIG_DFS(mc_cgm0_base), 1, + ENETPLL_PLLDIG_DFS1_MFN); + + clk[S32V234_CLK_ENETPLL_DFS2] = s32v234_clk_dfs(S32_PLLDIG_ENET, + "enetpll_dfs2", "enetpll_phi1", + ENETPLL_PLLDIG_DFS(mc_cgm0_base), 2, + ENETPLL_PLLDIG_DFS2_MFN); + + clk[S32V234_CLK_ENETPLL_DFS3] = s32v234_clk_dfs(S32_PLLDIG_ENET, + "enetpll_dfs3", "enetpll_phi1", + ENETPLL_PLLDIG_DFS(mc_cgm0_base), 3, + ENETPLL_PLLDIG_DFS3_MFN); + + /* ENET Clock */ + clk[S32V234_CLK_ENET_SEL] = s32_clk_mux("enet_sel", + CGM_ACn_SC(mc_cgm2_base, 2), + MC_CGM_ACn_SEL_OFFSET, + MC_CGM_ACn_SEL_SIZE, + enet_sels, ARRAY_SIZE(enet_sels), &s32v234_lock); + + clk[S32V234_CLK_ENET_TIME_SEL] = s32_clk_mux("enet_time_sel", + CGM_ACn_SC(mc_cgm0_base, 7), + MC_CGM_ACn_SEL_OFFSET, + MC_CGM_ACn_SEL_SIZE, + enet_time_sels, ARRAY_SIZE(enet_time_sels), &s32v234_lock); + + clk[S32V234_CLK_ENET] = s32_clk_divider("enet", "enet_sel", + CGM_ACn_DCm(mc_cgm2_base, 2, 0), + MC_CGM_ACn_DCm_PREDIV_OFFSET, + MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); + + clk[S32V234_CLK_ENET_TIME] = s32_clk_divider("enet_time", + "enet_time_sel", + CGM_ACn_DCm(mc_cgm0_base, 7, 1), + MC_CGM_ACn_DCm_PREDIV_OFFSET, + MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); + + /* SDHC Clock */ + clk[S32V234_CLK_SDHC_SEL] = s32_clk_mux("sdhc_sel", + CGM_ACn_SC(mc_cgm0_base, 15), + MC_CGM_ACn_SEL_OFFSET, + MC_CGM_ACn_SEL_SIZE, + sdhc_sels, ARRAY_SIZE(sdhc_sels), &s32v234_lock); + + clk[S32V234_CLK_SDHC] = s32_clk_divider("sdhc", "sdhc_sel", + CGM_ACn_DCm(mc_cgm0_base, 15, 0), + MC_CGM_ACn_DCm_PREDIV_OFFSET, + MC_CGM_ACn_DCm_PREDIV_SIZE, &s32v234_lock); + + /* set the system clock */ + enable_sysclock(MC_ME_MODE_MC_SYSCLK(0x2), + MC_ME_RUNn_MC(mc_me_base, 0)); + + /* transition the core to RUN0 mode */ + entry_to_target_mode(mc_me_base, MC_ME_MCTL_RUN0); + + /* Add the clocks to provider list */ + clk_data.clks = clk; + clk_data.clk_num = ARRAY_SIZE(clk); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +} + +CLK_OF_DECLARE(S32V234, "fsl,s32v234-mc_cgm0", s32v234_clocks_init); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/s32v234/clk-dfs.c linux-imx-phytec/drivers/clk/s32/s32v234/clk-dfs.c --- linux-6.1.55/drivers/clk/s32/s32v234/clk-dfs.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/s32v234/clk-dfs.c 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,236 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "clk.h" + +/** + * struct clk_dfs - S32 DFS clock + * @clk_hw: clock source + * @reg: DFS register address + * @idx: the index of DFS encoded in the register + * + * DFS clock found on S32 series. Each register for DFS has 4 clk_dfs + * data encoded, and member idx is used to specify the one. + * Only ARMPLL(3 DFS), ENETPLL(4 DFS) and DDRPLL(3 DFS) has DFS outputs. + */ +struct clk_dfs { + struct clk_hw hw; + void __iomem *reg; + enum s32v234_plldig_type plltype; + u8 idx; + u32 mfn; +}; + +#define to_clk_dfs(_hw) container_of(_hw, struct clk_dfs, hw) + +static int get_pllx_dfs_nr(enum s32v234_plldig_type plltype) +{ + switch (plltype) { + case S32_PLLDIG_ARM: + return ARMPLL_DFS_NR; + case S32_PLLDIG_ENET: + return ENETPLL_DFS_NR; + case S32_PLLDIG_DDR: + return DDRPLL_DFS_NR; + case S32_PLLDIG_PERIPH: + case S32_PLLDIG_VIDEO: + pr_warn("Current selected PLL has no DFS\n"); + break; + } + + return -EINVAL; +} +static unsigned long get_pllx_dfsy_max_rate(enum s32v234_plldig_type plltype, + int dfsno) +{ + switch (plltype) { + case S32_PLLDIG_ARM: + switch (dfsno) { + case 0: + return ARMPLL_DFS0_MAX_RATE; + case 1: + return ARMPLL_DFS1_MAX_RATE; + case 2: + return ARMPLL_DFS2_MAX_RATE; + } + break; + case S32_PLLDIG_ENET: + switch (dfsno) { + case 0: + return ENETPLL_DFS0_MAX_RATE; + case 1: + return ENETPLL_DFS1_MAX_RATE; + case 2: + return ENETPLL_DFS2_MAX_RATE; + case 3: + return ENETPLL_DFS3_MAX_RATE; + } + break; + case S32_PLLDIG_DDR: + switch (dfsno) { + case 0: + return DDRPLL_DFS0_MAX_RATE; + case 1: + return DDRPLL_DFS1_MAX_RATE; + case 2: + return DDRPLL_DFS2_MAX_RATE; + } + break; + case S32_PLLDIG_PERIPH: + case S32_PLLDIG_VIDEO: + pr_warn("Current selected PLL has no DFS."); + break; + default: + pr_warn("Unsupported PLL. Use %d or %d\n", + S32_PLLDIG_ARM, S32_PLLDIG_VIDEO); + break; + } + + return -EINVAL; +} +static int clk_dfs_enable(struct clk_hw *hw) +{ + /* + * TODO: When SOC is available, this function + * should be tested and implemented for DFS + * if it is possible + */ + return 0; +} + +static void clk_dfs_disable(struct clk_hw *hw) +{ + /* + * TODO: When SOC is available, this function + * should be tested and implemented for DFS + * if it is possible + */ +} + +static unsigned long clk_dfs_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_dfs *dfs = to_clk_dfs(hw); + u32 mfn, mfi, rate; + u32 dvport = readl_relaxed(DFS_DVPORTn(dfs->reg, dfs->idx)); + + mfn = (dvport & DFS_DVPORTn_MFN_MASK) >> DFS_DVPORTn_MFN_OFFSET; + mfi = (dvport & DFS_DVPORTn_MFI_MASK) >> DFS_DVPORTn_MFI_OFFSET; + mfi <<= 8; + rate = parent_rate / (mfi + mfn); + rate <<= 8; + + return rate; +} + +static long clk_dfs_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_dfs *dfs = to_clk_dfs(hw); + unsigned long max_allowed_rate; + + max_allowed_rate = get_pllx_dfsy_max_rate(dfs->plltype, dfs->idx); + + if (rate > max_allowed_rate) + rate = max_allowed_rate; + + return rate; +} + +static int clk_dfs_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_dfs *dfs = to_clk_dfs(hw); + u32 mfi; + u32 portreset = readl_relaxed(DFS_PORTRESET(dfs->reg)); + + writel_relaxed(DFS_CTRL_DLL_RESET, DFS_CTRL(dfs->reg)); + writel_relaxed(portreset | ~DFS_PORTRESET_PORTRESET_SET(dfs->idx), + DFS_PORTRESET(dfs->reg)); + + mfi = parent_rate/rate; + writel_relaxed(DFS_DVPORTn_MFI_SET(mfi) | + DFS_DVPORTn_MFN_SET(dfs->mfn), + DFS_DVPORTn(dfs->reg, dfs->idx)); + + writel_relaxed(~DFS_CTRL_DLL_RESET, DFS_CTRL(dfs->reg)); + + while (readl_relaxed(DFS_PORTSR(dfs->reg)) & (1 << (dfs->idx))) + ; + + return 0; +} + +static int clk_dfs_is_enabled(struct clk_hw *hw) +{ + struct clk_dfs *dfs = to_clk_dfs(hw); + + /* Check if current DFS output port is locked */ + if (readl_relaxed(DFS_PORTSR(dfs->reg)) & (1 << (dfs->idx))) + return 0; + + return 1; +} + +static const struct clk_ops clk_dfs_ops = { + .enable = clk_dfs_enable, + .disable = clk_dfs_disable, + .recalc_rate = clk_dfs_recalc_rate, + .round_rate = clk_dfs_round_rate, + .set_rate = clk_dfs_set_rate, + .is_enabled = clk_dfs_is_enabled, +}; + +struct clk *s32v234_clk_dfs(enum s32v234_plldig_type type, const char *name, + const char *parent_name, void __iomem *reg, + u8 idx, u32 mfn) +{ + struct clk_dfs *dfs; + struct clk *clk; + struct clk_init_data init; + + /* PERIPH and VIDEO PLL do not have DFS */ + if (type == S32_PLLDIG_PERIPH || type == S32_PLLDIG_VIDEO) + return ERR_PTR(-EINVAL); + + /* check if DFS index is valid for current pll */ + if (idx >= get_pllx_dfs_nr(type)) + return ERR_PTR(-EINVAL); + + dfs = kzalloc(sizeof(*dfs), GFP_KERNEL); + if (!dfs) + return ERR_PTR(-ENOMEM); + + dfs->reg = reg; + dfs->idx = idx; + dfs->mfn = mfn; + dfs->plltype = type; + + init.name = name; + init.ops = &clk_dfs_ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + dfs->hw.init = &init; + + clk = clk_register(NULL, &dfs->hw); + if (IS_ERR(clk)) + kfree(dfs); + + return clk; +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/s32v234/clk.h linux-imx-phytec/drivers/clk/s32/s32v234/clk.h --- linux-6.1.55/drivers/clk/s32/s32v234/clk.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/s32v234/clk.h 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#ifndef __MACH_S32V234_CLK_H +#define __MACH_S32V234_CLK_H + +#include +#include +#include "mc_cgm.h" +#include "mc_me.h" +#include "pll.h" +#include "src.h" +#include "dfs.h" +#include "../clk.h" + +struct clk *s32v234_clk_plldig(enum s32v234_plldig_type type, const char *name, + const char *parent_name, void __iomem *base, + u32 plldv_mfd, u32 plldv_mfn, + u32 plldv_rfdphi, u32 plldv_rfdphi1); + +struct clk *s32v234_clk_plldig_phi(enum s32v234_plldig_type type, + const char *name, const char *parent, + void __iomem *base, u32 phi); + +struct clk *s32v234_clk_dfs(enum s32v234_plldig_type type, const char *name, + const char *parent_name, + void __iomem *reg, u8 idx, u32 mfn); +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/s32v234/clk-plldig.c linux-imx-phytec/drivers/clk/s32/s32v234/clk-plldig.c --- linux-6.1.55/drivers/clk/s32/s32v234/clk-plldig.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/s32v234/clk-plldig.c 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include "clk.h" + +/* + * struct clk_plldig - S32 PLLDIG clock + * @clk_hw: clock source + * @base: base address of PLL registers + * @plldv_mfd: multiplication loop factor divider + * @plldv_rfdphi: PHI reduced frequency divider + * @plldv_rfdphi1: PHI reduced frequency divider + * + * PLLDIG clock version 1, found on S32 series. + */ +struct clk_plldig { + struct clk_hw hw; + void __iomem *base; + enum s32v234_plldig_type type; + u32 plldv_mfd; + u32 pllfd_mfn; + u32 plldv_rfdphi; + u32 plldv_rfdphi1; +}; + +#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw) + +static unsigned long get_pllx_max_vco_rate(enum s32v234_plldig_type plltype) +{ + switch (plltype) { + case S32_PLLDIG_PERIPH: + return PERIPHPLL_MAX_VCO_RATE; + default: + pr_warn("Unsupported PLL.\n"); + return -EINVAL; + } +} + +static unsigned long get_pllx_phiy_max_rate(enum s32v234_plldig_type plltype, + unsigned int phino) +{ + switch (plltype) { + case S32_PLLDIG_PERIPH: + switch (phino) { + case 0: + return PERIPHPLL_MAX_PHI0_MAX_RATE; + case 1: + return PERIPHPLL_MAX_PHI1_MAX_RATE; + default: + break; + } + break; + default: + pr_warn("Unsupported PLL.\n"); + break; + } + return -EINVAL; +} + +static int clk_plldig_prepare(struct clk_hw *hw) +{ + return 0; +} + +static void clk_plldig_unprepare(struct clk_hw *hw) +{ +} + +static unsigned long clk_plldig_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_plldig *pll = to_clk_plldig(hw); + u32 plldv = readl_relaxed(PLLDIG_PLLDV(pll->base)); + u32 pllfd = readl_relaxed(PLLDIG_PLLFD(pll->base)); + u32 prediv, mfd, mfn, vco; + + prediv = (plldv & PLLDIG_PLLDV_PREDIV_MASK) + >> PLLDIG_PLLDV_PREDIV_OFFSET; + mfd = (plldv & PLLDIG_PLLDV_MFD_MASK); + + mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK); + + if (prediv == 0) + prediv = 1; + + /* + * This formula is from platform reference manual + * (Rev. 1, 6/2015), PLLDIG chapter. + */ + vco = (parent_rate / prediv) * (mfd + mfn / 20480); + + return vco; +} + +static long clk_plldig_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_plldig *pll = to_clk_plldig(hw); + unsigned long max_allowed_rate = get_pllx_max_vco_rate(pll->type); + + if (rate > max_allowed_rate) + rate = max_allowed_rate; + else if (rate < MIN_VCO_RATE) + rate = MIN_VCO_RATE; + + return rate; +} + +static int clk_plldig_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_plldig *pll = to_clk_plldig(hw); + u32 pllfd, prediv; + + unsigned long max_allowed_rate = get_pllx_max_vco_rate(pll->type); + unsigned long phi0_max_rate = get_pllx_phiy_max_rate(pll->type, 0); + unsigned long phi1_max_rate = get_pllx_phiy_max_rate(pll->type, 1); + + if (rate < MIN_VCO_RATE || rate > max_allowed_rate) + return -EINVAL; + + if (((rate / pll->plldv_rfdphi) > phi0_max_rate) || + ((rate / pll->plldv_rfdphi) > phi1_max_rate)) + return -EINVAL; + + pllfd = readl_relaxed(PLLDIG_PLLFD(pll->base)); + prediv = (parent_rate / rate) * + (pll->plldv_mfd + pll->pllfd_mfn / 20480); + + writel_relaxed(PLLDIG_PLLDV_RFDPHI1_SET(pll->plldv_rfdphi1) | + PLLDIG_PLLDV_RFDPHI_SET(pll->plldv_rfdphi) | + PLLDIG_PLLDV_PREDIV_SET(prediv) | + PLLDIG_PLLDV_MFD_SET(pll->plldv_mfd), + PLLDIG_PLLDV(pll->base)); + + writel_relaxed(pllfd | PLLDIG_PLLFD_MFN_SET(pll->pllfd_mfn), + PLLDIG_PLLFD(pll->base)); + + /* + * To be implemented the wait_lock or an equivalent state + * return clk_plldig_wait_lock(pll); + */ + return 0; +} + +static const struct clk_ops clk_plldig_ops = { + .prepare = clk_plldig_prepare, + .unprepare = clk_plldig_unprepare, + .recalc_rate = clk_plldig_recalc_rate, + .round_rate = clk_plldig_round_rate, + .set_rate = clk_plldig_set_rate, +}; + +struct clk *s32v234_clk_plldig_phi(enum s32v234_plldig_type type, + const char *name, const char *parent, + void __iomem *base, u32 phi) +{ + u32 plldv, rfd_phi; + + if (!base) + return ERR_PTR(-ENOMEM); + + plldv = readl_relaxed(PLLDIG_PLLDV(base)); + + switch (phi) { + /* PHI0 */ + case 0: + rfd_phi = (plldv & PLLDIG_PLLDV_RFDPHI_MASK) + >> PLLDIG_PLLDV_RFDPHI_OFFSET; + break; + /* PHI1 */ + case 1: + rfd_phi = (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) + >> PLLDIG_PLLDV_RFDPHI1_OFFSET; + + if (rfd_phi == 0) + rfd_phi = 1; + + break; + default: + return ERR_PTR(-EINVAL); + } + + return clk_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, 1, rfd_phi); +} + +struct clk *s32v234_clk_plldig(enum s32v234_plldig_type type, const char *name, + const char *parent_name, void __iomem *base, + u32 plldv_mfd, u32 pllfd_mfn, + u32 plldv_rfdphi, u32 plldv_rfdphi1) +{ + struct clk_plldig *pll; + const struct clk_ops *ops; + struct clk *clk; + struct clk_init_data init; + + if (plldv_rfdphi > PLLDIG_PLLDV_RFDPHI_MAXVALUE) + return ERR_PTR(-EINVAL); + + if (plldv_rfdphi1 > PLLDIG_PLLDV_RFDPHI1_MAXVALUE) + return ERR_PTR(-EINVAL); + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + ops = &clk_plldig_ops; + + pll->base = base; + pll->type = type; + pll->plldv_mfd = plldv_mfd; + pll->pllfd_mfn = pllfd_mfn; + pll->plldv_rfdphi = plldv_rfdphi; + pll->plldv_rfdphi1 = plldv_rfdphi1; + + init.name = name; + init.ops = ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/s32v234/dfs.h linux-imx-phytec/drivers/clk/s32/s32v234/dfs.h --- linux-6.1.55/drivers/clk/s32/s32v234/dfs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/s32v234/dfs.h 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef _DFS_S32V234_H +#define _DFS_S32V234_H + +/* DFS Control Register (DFS_CTRL) */ +#define DFS_CTRL(base) ((base) + 0x00000018) +#define DFS_CTRL_DLL_LOLIE (1 << 0) +#define DFS_CTRL_DLL_RESET (1 << 1) + +/* DFS Port Status (DFS_PORTSR) */ +#define DFS_PORTSR(base) ((base) + 0x0000000C) +#define DFS_PORTSR_MASK (0x0000000F) +#define DFS_PORTSR_OFFSET (28) + +/* DFS Port Reset Register (DFS_PORTRESET) */ +#define DFS_PORTRESET(base) ((base) + 0x00000014) +#define DFS_PORTRESET_PORTRESET_SET(val) \ + (DFS_PORTRESET_PORTRESET_MASK | \ + (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) \ + << DFS_PORTRESET_PORTRESET_OFFSET)) +#define DFS_PORTRESET_PORTRESET_MAXVAL (0xF) +#define DFS_PORTRESET_PORTRESET_MASK (0x0000000F) +#define DFS_PORTRESET_PORTRESET_OFFSET (28) + +/* DFS Divide Register Portn (DFS_DVPORTn) */ +#define DFS_DVPORTn(base, n) ((base) + (0x0000001C + \ + ((n) * sizeof(u32)))) +#define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & \ + (((val) & DFS_DVPORTn_MFI_MAXVAL) \ + << DFS_DVPORTn_MFI_OFFSET)) +#define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & \ + (((val) & DFS_DVPORTn_MFN_MAXVAL) \ + << DFS_DVPORTn_MFN_OFFSET)) +#define DFS_DVPORTn_MFI_MASK (0x0000FF00) +#define DFS_DVPORTn_MFN_MASK (0x000000FF) +#define DFS_DVPORTn_MFI_MAXVAL (0xFF) +#define DFS_DVPORTn_MFN_MAXVAL (0xFF) +#define DFS_DVPORTn_MFI_OFFSET (8) +#define DFS_DVPORTn_MFN_OFFSET (0) +#define DFS_MAXNUMBER (4) + +/* + * Naming convention for PLL: + * ARMPLL - PLL0 + * PERIPHPLL - PLL1 + * ENETPLL - PLL2 + * DDRPLL - PLL3 + * VIDEOPLL - PLL4 + */ + +/* The max values for PLL DFS is in Hz */ +/* ARMPLL */ +#define ARMPLL_DFS0_MAX_RATE (266000000) +#define ARMPLL_DFS1_MAX_RATE (600000000) +#define ARMPLL_DFS2_MAX_RATE (600000000) +/* ENETPLL */ +#define ENETPLL_DFS0_MAX_RATE (350000000) +#define ENETPLL_DFS1_MAX_RATE (350000000) +#define ENETPLL_DFS2_MAX_RATE (416000000) +#define ENETPLL_DFS3_MAX_RATE (104000000) +/* DDRPLL */ +#define DDRPLL_DFS0_MAX_RATE (500000000) +#define DDRPLL_DFS1_MAX_RATE (500000000) +#define DDRPLL_DFS2_MAX_RATE (350000000) + +#define ARMPLL_DFS_NR (3) +#define ENETPLL_DFS_NR (4) +#define DDRPLL_DFS_NR (3) + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/s32v234/Makefile linux-imx-phytec/drivers/clk/s32/s32v234/Makefile --- linux-6.1.55/drivers/clk/s32/s32v234/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/s32v234/Makefile 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_S32_CLK) += clk.o clk-plldig.o clk-dfs.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/s32v234/mc_cgm.h linux-imx-phytec/drivers/clk/s32/s32v234/mc_cgm.h --- linux-6.1.55/drivers/clk/s32/s32v234/mc_cgm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/s32v234/mc_cgm.h 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP + */ +#ifndef _MC_CGM_H +#define _MC_CGM_H + +#define ARMPLL_PLLDIG(mc_cgm) (mc_cgm) +#define ARMPLL_PLLDIG_DFS(mc_cgm) ((mc_cgm) + 0x40) +#define ARMPLL_PLLDIG_PLLDV_MFD (50) +#define ARMPLL_PLLDIG_PLLDV_MFN (0) +#define ARMPLL_PLLDIG_PLLDV_RFDPHI0 (1) +#define ARMPLL_PLLDIG_PLLDV_RFDPHI1 (1) +#define ARMPLL_PLLDIG_DFS0_MFN (195) +#define ARMPLL_PLLDIG_DFS1_MFN (171) +#define ARMPLL_PLLDIG_DFS2_MFN (171) + +#define PERIPHPLL_PLLDIG(mc_cgm) ((mc_cgm) + 0x80) +#define PERIPHPLL_PLLDIG_PLLDV_MFD (30) +#define PERIPHPLL_PLLDIG_PLLDV_MFN (0) +#define PERIPHPLL_PLLDIG_PLLDV_RFDPHI0 (0x1) +#define PERIPHPLL_PLLDIG_PLLDV_RFDPHI1 (0x1) + +#define ENETPLL_PLLDIG(mc_cgm) ((mc_cgm) + 0x100) +#define ENETPLL_PLLDIG_DFS(mc_cgm) ((mc_cgm) + 0x100 + 0x40) +#define ENETPLL_PLLDIG_PLLDV_MFD (50) +#define ENETPLL_PLLDIG_PLLDV_MFN (0) +#define ENETPLL_PLLDIG_PLLDV_RFDPHI0 (0x1) +#define ENETPLL_PLLDIG_PLLDV_RFDPHI1 (0x1) +#define ENETPLL_PLLDIG_DFS0_MFN (220) +#define ENETPLL_PLLDIG_DFS1_MFN (220) +#define ENETPLL_PLLDIG_DFS2_MFN (33) +#define ENETPLL_PLLDIG_DFS3_MFN (1) + +/* MC_CGM_SC_SS */ +#define CGM_SC_SS(mc_cgm) (((mc_cgm) + 0x7E4)) + +/* MC_CGM_SC_DCn */ +#define CGM_SC_DCn(mc_cgm, dc) (((mc_cgm) + 0x7E8) + ((dc) * 0x4)) + +#define MC_CGM_SC_DCn_PREDIV_OFFSET (16) +#define MC_CGM_SC_DCn_PREDIV_SIZE (3) +#define MC_CGM_SC_DCn_DE (1 << 31) +#define MC_CGM_SC_SEL_OFFSET (24) +#define MC_CGM_SC_SEL_SIZE (4) + +/* MC_CGM_ACn_DCm */ +#define CGM_ACn_DCm(mc_cgm, ac, dc) (((mc_cgm) + 0x808) + ((ac) * 0x20)\ + + ((dc) * 0x4)) + +#define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & \ + ((val) \ + << MC_CGM_ACn_DCm_PREDIV_OFFSET)) +#define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000) +#define MC_CGM_ACn_DCm_PREDIV_OFFSET (16) +#define MC_CGM_ACn_DCm_PREDIV_SIZE (5) +#define MC_CGM_ACn_DCm_DE (1 << 31) + +/* MC_CGM_ACn_SC/MC_CGM_ACn_SS */ +#define CGM_ACn_SC(mc_cgm, ac) (((mc_cgm) + 0x800) + ((ac) * 0x20)) +#define CGM_ACn_SS(mc_cgm, ac) (((mc_cgm) + 0x804) + ((ac) * 0x24)) +#define MC_CGM_ACn_SEL_MASK (0x07000000) +#define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & \ + (((source) & 0x7) \ + << MC_CGM_ACn_SEL_OFFSET)) +#define MC_CGM_ACn_SEL_OFFSET (24) +#define MC_CGM_ACn_SEL_SIZE (4) + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/s32v234/mc_me.h linux-imx-phytec/drivers/clk/s32/s32v234/mc_me.h --- linux-6.1.55/drivers/clk/s32/s32v234/mc_me.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/s32v234/mc_me.h 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP + */ + +#ifndef _MC_ME_H +#define _MC_ME_H + +/* MC_ME registers definitions */ +/* MC_ME_GS */ + #define MC_ME_GS(mc_me) ((mc_me) + 0x00000000) + +/* MC_ME_MCTL */ +#define MC_ME_MCTL(mc_me) ((mc_me) + 0x00000004) +#define MC_ME_MCTL_RESET (0x0 << 28) +#define MC_ME_MCTL_TEST (0x1 << 28) +#define MC_ME_MCTL_DRUN (0x3 << 28) +#define MC_ME_MCTL_RUN0 (0x4 << 28) +#define MC_ME_MCTL_RUN1 (0x5 << 28) +#define MC_ME_MCTL_RUN2 (0x6 << 28) +#define MC_ME_MCTL_RUN3 (0x7 << 28) + +#define MC_ME_GS_S_MTRANS (1 << 27) + +#define MC_ME_MCTL_KEY (0x00005AF0) +#define MC_ME_MCTL_INVERTEDKEY (0x0000A50F) + +/* + * MC_ME_RESET_MC/MC_ME_TEST_MC + * MC_ME_DRUN_MC + * MC_ME_RUNn_MC + */ +#define MC_ME_RESET_MC(mc_me) ((mc_me) + 0x00000020) +#define MC_ME_TEST_MC(mc_me) ((mc_me) + 0x00000024) +#define MC_ME_DRUN_MC(mc_me) ((mc_me) + 0x0000002C) +#define MC_ME_RUNn_MC(mc_me, n) ((mc_me) + 0x00000030 + 0x4 * (n)) +#define MC_ME_MODE_MC_SYSCLK_OFFSET (0) +#define MC_ME_MODE_MC_SYSCLK_SIZE (0x3) +#define MC_ME_MODE_MC_SYSCLK(val) (MC_ME_MODE_MC_SYSCLK_MASK & (val)) +#define MC_ME_MODE_MC_SYSCLK_MASK (0x0000000F) +#define MC_ME_MODE_MC_FIRCON (1 << 4) +#define MC_ME_MODE_MC_XOSCON (1 << 5) +#define MC_ME_MODE_MC_ARMPLL (1 << 6) +#define MC_ME_MODE_MC_PERIPHPLL (1 << 7) +#define MC_ME_MODE_MC_ENETPLL (1 << 8) +#define MC_ME_MODE_MC_DDRPLL (1 << 9) +#define MC_ME_MODE_MC_VIDEOPLL (1 << 10) +#define MC_ME_MODE_MC_MVRON (1 << 20) + +/* MC_ME_DRUN_SEC_CC_I */ +#define MC_ME_DRUN_SEC_CC_I(mc_me) ((mc_me) + 0x260) +/* MC_ME_RUNn_SEC_CC_I */ +#define MC_ME_RUNn_SEC_CC_I(mc_me, n) ((mc_me) + 0x270 + (n) * 0x10) +#define MC_ME_MODE_SEC_CC_I_SYSCLK1_OFFSET (4) +#define MC_ME_MODE_SEC_CC_I_SYSCLK2_OFFSET (8) +#define MC_ME_MODE_SEC_CC_I_SYSCLK3_OFFSET (12) +/* Consider only the defined clocks */ +#define MC_ME_MODE_SEC_CC_I_SYSCLK1_SIZE (0x3) +#define MC_ME_MODE_SEC_CC_I_SYSCLK2_SIZE (0x3) +#define MC_ME_MODE_SEC_CC_I_SYSCLK3_SIZE (0x3) + +/* MC_ME_RUN_PCn */ +#define MC_ME_RUN_PCn(mc_me, n) (mc_me + 0x00000080 + 0x4 * (n)) + +#define MC_ME_RUN_PCn_MAX_IDX (7) +#define MC_ME_RUN_PCn_RESET (1 << 0) +#define MC_ME_RUN_PCn_TEST (1 << 1) +#define MC_ME_RUN_PCn_DRUN (1 << 3) +#define MC_ME_RUN_PCn_RUN0 (1 << 4) +#define MC_ME_RUN_PCn_RUN1 (1 << 5) +#define MC_ME_RUN_PCn_RUN2 (1 << 6) +#define MC_ME_RUN_PCn_RUN3 (1 << 7) + +#define MC_ME_PCTLn(mc_me, n) (mc_me + 0xC0 + 4 * (n >> 2) + \ + (3 - (n) % 4)) + +static inline void entry_to_target_mode(void __iomem *mc_me, u32 mode) +{ + writel_relaxed(mode | MC_ME_MCTL_KEY, MC_ME_MCTL(mc_me)); + writel_relaxed(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL(mc_me)); + while ((readl_relaxed(MC_ME_GS(mc_me)) & + MC_ME_GS_S_MTRANS) != 0x00000000) + ; +} + +static inline void enable_cpumodes_onperipheralconfig(void __iomem *mc_me, + u32 modes, u32 run_pc_idx) +{ + WARN_ON(run_pc_idx > MC_ME_RUN_PCn_MAX_IDX); + if (run_pc_idx > MC_ME_RUN_PCn_MAX_IDX) + return; + + writel_relaxed(modes, MC_ME_RUN_PCn(mc_me, run_pc_idx)); +} + +static inline void enable_clocks_sources(u32 flags, u32 clks, + void __iomem *xrun_mc_addr) +{ + writel_relaxed(readl_relaxed(xrun_mc_addr) | flags | clks, + xrun_mc_addr); +} + +static inline void enable_sysclock(u32 clk, void __iomem *xrun_mc_addr) +{ + writel_relaxed(readl_relaxed(xrun_mc_addr) & clk, + xrun_mc_addr); +} + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/s32v234/pll.h linux-imx-phytec/drivers/clk/s32/s32v234/pll.h --- linux-6.1.55/drivers/clk/s32/s32v234/pll.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/s32v234/pll.h 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017-2018 NXP + */ +#ifndef _PLL_S32V234_H +#define _PLL_S32V234_H + +/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */ +#define PLLDIG_PLLDV(base) ((base) + 0x00000028) +#define PLLDIG_PLLDV_MFD_SET(val) (PLLDIG_PLLDV_MFD_MASK & (val)) +#define PLLDIG_PLLDV_MFD_MASK (0x000000FF) + +#define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & \ + (((val) & \ + PLLDIG_PLLDV_RFDPHI_MAXVALUE) \ + << PLLDIG_PLLDV_RFDPHI_OFFSET)) +#define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000) +#define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F) + +#define PLLDIG_PLLDV_RFDPHI_OFFSET (16) + +#define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & \ + (((val) & \ + PLLDIG_PLLDV_RFDPHI1_MAXVALUE) \ + << PLLDIG_PLLDV_RFDPHI1_OFFSET)) +#define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000) +#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F) +#define PLLDIG_PLLDV_RFDPHI1_OFFSET (25) + +#define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & \ + (((val) & \ + PLLDIG_PLLDV_PREDIV_MAXVALUE) \ + << PLLDIG_PLLDV_PREDIV_OFFSET)) +#define PLLDIG_PLLDV_PREDIV_MASK (0x00007000) +#define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7) +#define PLLDIG_PLLDV_PREDIV_OFFSET (12) + +/* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */ +#define PLLDIG_PLLFD(base) ((base) + 0x00000030) +#define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val)) +#define PLLDIG_PLLFD_MFN_MASK (0x00007FFF) + +/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */ +#define PLLDIG_PLLCAL1(base) ((base) + 0x00000038) +#define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & \ + ((val) \ + << PLLDIG_PLLCAL1_NDAC1_OFFSET)) +#define PLLDIG_PLLCAL1_NDAC1_OFFSET (24) +#define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000) + +/* Naming convention for PLL: + * ARMPLL - PLL0 + * PERIPHPLL - PLL1 + * ENETPLL - PLL2 + * DDRPLL - PLL3 + * VIDEOPLL - PLL4 + */ +/* The min,max values for PLL VCO (Hz) */ +#define PERIPHPLL_MAX_VCO_RATE (1200000000) + +/* The min,max values for PLL PHI0 and PHI1 outputs (Hz) */ +#define PERIPHPLL_MAX_PHI0_MAX_RATE (400000000) +#define PERIPHPLL_MAX_PHI1_MAX_RATE (100000000) + +/* The maximum value for PLL VCO according to data sheet */ +#define MAX_VCO_RATE (1300000000) +#define MIN_VCO_RATE (650000000) + +enum s32v234_plldig_type { + S32_PLLDIG_ARM, + S32_PLLDIG_PERIPH, + S32_PLLDIG_ENET, + S32_PLLDIG_DDR, + S32_PLLDIG_VIDEO, +}; + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clk/s32/s32v234/src.h linux-imx-phytec/drivers/clk/s32/s32v234/src.h --- linux-6.1.55/drivers/clk/s32/s32v234/src.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/clk/s32/s32v234/src.h 2024-06-19 12:33:59.628215275 +0200 @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ +#ifndef _SRC_H +#define _SRC_H + +/* Source Reset Control: General Purpose Register 1 */ +#define SRC_GPR1 (src_base + 0x100) +#define SRC_GPR1_ARMPLL_SRC_SEL_OFFSET (27) +#define SRC_GPR1_ENETPLL_SRC_SEL_OFFSET (28) +#define SRC_GPR1_DDRPLL_SRC_SEL_OFFSET (29) +#define SRC_GPR1_PERIPHPLL_SRC_SEL_OFFSET (30) +#define SRC_GPR1_VIDEOPLL_SRC_SEL_OFFSET (31) +#define SRC_GPR1_XPLL_SRC_SEL_SIZE (1) + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clocksource/timer-imx-gpt.c linux-imx-phytec/drivers/clocksource/timer-imx-gpt.c --- linux-6.1.55/drivers/clocksource/timer-imx-gpt.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clocksource/timer-imx-gpt.c 2024-06-19 12:33:59.672216027 +0200 @@ -454,12 +454,16 @@ return -ENOMEM; imxtm->base = of_iomap(np, 0); - if (!imxtm->base) - return -ENXIO; + if (!imxtm->base) { + ret = -ENXIO; + goto err_kfree; + } imxtm->irq = irq_of_parse_and_map(np, 0); - if (imxtm->irq <= 0) - return -EINVAL; + if (imxtm->irq <= 0) { + ret = -EINVAL; + goto err_kfree; + } imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); @@ -472,11 +476,15 @@ ret = _mxc_timer_init(imxtm); if (ret) - return ret; + goto err_kfree; initialized = 1; return 0; + +err_kfree: + kfree(imxtm); + return ret; } static int __init imx1_timer_init_dt(struct device_node *np) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/clocksource/timer-imx-tpm.c linux-imx-phytec/drivers/clocksource/timer-imx-tpm.c --- linux-6.1.55/drivers/clocksource/timer-imx-tpm.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/clocksource/timer-imx-tpm.c 2024-06-19 12:33:59.676216095 +0200 @@ -83,20 +83,28 @@ static int tpm_set_next_event(unsigned long delta, struct clock_event_device *evt) { - unsigned long next, now; + unsigned long next, prev, now; - next = tpm_read_counter(); - next += delta; + prev = tpm_read_counter(); + next = prev + delta; writel(next, timer_base + TPM_C0V); now = tpm_read_counter(); /* + * Need to wait CNT increase at least 1 cycle to make sure + * the C0V has been updated into HW. + */ + if ((next & 0xffffffff) != readl(timer_base + TPM_C0V)) + while (now == tpm_read_counter()) + ; + + /* * NOTE: We observed in a very small probability, the bus fabric * contention between GPU and A7 may results a few cycles delay * of writing CNT registers which may cause the min_delta event got * missed, so we need add a ETIME check here in case it happened. */ - return (int)(next - now) <= 0 ? -ETIME : 0; + return (now - prev) >= delta ? -ETIME : 0; } static int tpm_set_state_oneshot(struct clock_event_device *evt) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/cpufreq/imx6q-cpufreq.c linux-imx-phytec/drivers/cpufreq/imx6q-cpufreq.c --- linux-6.1.55/drivers/cpufreq/imx6q-cpufreq.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/cpufreq/imx6q-cpufreq.c 2024-06-19 12:33:59.716216780 +0200 @@ -3,6 +3,7 @@ * Copyright (C) 2013 Freescale Semiconductor, Inc. */ +#include #include #include #include @@ -14,14 +15,27 @@ #include #include #include +#include #define PU_SOC_VOLTAGE_NORMAL 1250000 #define PU_SOC_VOLTAGE_HIGH 1275000 #define FREQ_1P2_GHZ 1200000000 +#define FREQ_396_MHZ 396000 -static struct regulator *arm_reg; -static struct regulator *pu_reg; -static struct regulator *soc_reg; +#define PU_SOC_VOLTAGE_NORMAL 1250000 +#define PU_SOC_VOLTAGE_HIGH 1275000 +#define DC_VOLTAGE_MIN 1300000 +#define DC_VOLTAGE_MAX 1400000 +#define FREQ_1P2_GHZ 1200000000 +#define FREQ_396_MHZ 396000 +#define FREQ_528_MHZ 528000 +#define FREQ_198_MHZ 198000 +#define FREQ_24_MHZ 24000 + +struct regulator *arm_reg; +struct regulator *pu_reg; +struct regulator *soc_reg; +struct regulator *dc_reg; enum IMX6_CPUFREQ_CLKS { ARM, @@ -29,12 +43,15 @@ STEP, PLL1_SW, PLL2_PFD2_396M, + PLL1, + PLL1_BYPASS, + PLL1_BYPASS_SRC, /* MX6UL requires two more clks */ PLL2_BUS, SECONDARY_SEL, }; -#define IMX6Q_CPUFREQ_CLK_NUM 5 -#define IMX6UL_CPUFREQ_CLK_NUM 7 +#define IMX6Q_CPUFREQ_CLK_NUM 8 +#define IMX6UL_CPUFREQ_CLK_NUM 10 static int num_clks; static struct clk_bulk_data clks[] = { @@ -43,6 +60,9 @@ { .id = "step" }, { .id = "pll1_sw" }, { .id = "pll2_pfd2_396m" }, + { .id = "pll1" }, + { .id = "pll1_bypass" }, + { .id = "pll1_bypass_src" }, { .id = "pll2_bus" }, { .id = "secondary_sel" }, }; @@ -55,6 +75,9 @@ static u32 *imx6_soc_volt; static u32 soc_opp_count; +static bool ignore_dc_reg; +static bool low_power_run_support; + static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) { struct dev_pm_opp *opp; @@ -65,7 +88,16 @@ new_freq = freq_table[index].frequency; freq_hz = new_freq * 1000; - old_freq = clk_get_rate(clks[ARM].clk) / 1000; + old_freq = policy->cur; + + /* + * ON i.MX6ULL, the 24MHz setpoint is not seen by cpufreq + * so we neet to prevent the cpufreq change frequency + * from 24MHz to 198Mhz directly. busfreq will handle this + * when exit from low bus mode. + */ + if (old_freq == FREQ_24_MHZ && new_freq == FREQ_198_MHZ) + return 0; opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); if (IS_ERR(opp)) { @@ -82,6 +114,13 @@ old_freq / 1000, volt_old / 1000, new_freq / 1000, volt / 1000); + if (low_power_run_support) { + if (old_freq == freq_table[0].frequency) + request_bus_freq(BUS_FREQ_HIGH); + } else if (old_freq <= FREQ_396_MHZ && new_freq > FREQ_396_MHZ) { + request_bus_freq(BUS_FREQ_HIGH); + } + /* scaling up? scale voltage before frequency */ if (new_freq > old_freq) { if (!IS_ERR(pu_reg)) { @@ -142,11 +181,18 @@ clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) { + /* Ensure that pll1_bypass is set back to + * pll1. We have to do this first so that the + * change rate done to pll1_sys_clk done below + * can propagate up to pll1. + */ + clk_set_parent(clks[PLL1_BYPASS].clk, clks[PLL1].clk); clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); } else { /* pll1_sys needs to be enabled for divider rate change to work. */ pll1_sys_temp_enabled = true; + clk_set_parent(clks[PLL1_BYPASS].clk, clks[PLL1_BYPASS_SRC].clk); clk_prepare_enable(clks[PLL1_SYS].clk); } } @@ -184,15 +230,33 @@ } } + /* + * If CPU is dropped to the lowest level, release the need + * for a high bus frequency. + */ + if (low_power_run_support) { + if (new_freq == freq_table[0].frequency) + release_bus_freq(BUS_FREQ_HIGH); + } else if (old_freq > FREQ_396_MHZ && new_freq <= FREQ_396_MHZ) { + release_bus_freq(BUS_FREQ_HIGH); + } + return 0; } static int imx6q_cpufreq_init(struct cpufreq_policy *policy) { policy->clk = clks[ARM].clk; + policy->cur = clk_get_rate(policy->clk) / 1000; cpufreq_generic_init(policy, freq_table, transition_latency); policy->suspend_freq = max_freq; + if (low_power_run_support && policy->cur > freq_table[0].frequency) { + request_bus_freq(BUS_FREQ_HIGH); + } else if (policy->cur > FREQ_396_MHZ) { + request_bus_freq(BUS_FREQ_HIGH); + } + return 0; } @@ -335,6 +399,43 @@ return ret; } +static int imx6_cpufreq_pm_notify(struct notifier_block *nb, + unsigned long event, void *dummy) +{ + int ret; + + switch (event) { + case PM_SUSPEND_PREPARE: + if (!IS_ERR(dc_reg) && !ignore_dc_reg) { + ret = regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MAX, 0); + if (ret) { + dev_err(cpu_dev, + "failed to scale dc_reg to max: %d\n", ret); + return ret; + } + } + break; + case PM_POST_SUSPEND: + if (!IS_ERR(dc_reg) && !ignore_dc_reg) { + ret = regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); + if (ret) { + dev_err(cpu_dev, + "failed to scale dc_reg to min: %d\n", ret); + return ret; + } + } + break; + default: + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block imx6_cpufreq_pm_notifier = { + .notifier_call = imx6_cpufreq_pm_notify, +}; + static int imx6q_cpufreq_probe(struct platform_device *pdev) { struct device_node *np; @@ -383,6 +484,11 @@ goto put_reg; } + dc_reg = devm_regulator_get_optional(cpu_dev, "dc"); + + /* On i.MX6ULL, check the 24MHz low power run mode support */ + low_power_run_support = of_property_read_bool(np, "fsl,low-power-run"); + ret = dev_pm_opp_of_add_table(cpu_dev); if (ret < 0) { dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); @@ -413,6 +519,21 @@ goto out_free_opp; } + /* + * On i.MX6UL/ULL EVK board, if the SOC is run in overide frequency, + * the dc_regulator voltage should not be touched. + */ + if (freq_table[num - 1].frequency > FREQ_528_MHZ) + ignore_dc_reg = true; + if (!IS_ERR(dc_reg) && !ignore_dc_reg) { + ret = regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); + if (ret) { + dev_err(cpu_dev, + "failed to scale dc_reg to min: %d\n", ret); + return ret; + } + } + /* Make imx6_soc_volt array's size same as arm opp number */ imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt), GFP_KERNEL); @@ -495,6 +616,8 @@ goto free_freq_table; } + register_pm_notifier(&imx6_cpufreq_pm_notifier); + of_node_put(np); return 0; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamalg.c linux-imx-phytec/drivers/crypto/caam/caamalg.c --- linux-6.1.55/drivers/crypto/caam/caamalg.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/caamalg.c 2024-06-19 12:33:59.740217190 +0200 @@ -3,7 +3,7 @@ * caam - Freescale FSL CAAM support for crypto API * * Copyright 2008-2011 Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2020 NXP * * Based on talitos crypto API driver. * @@ -60,6 +60,10 @@ #include #include +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API +#include "tag_object.h" +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ + /* * crypto alg */ @@ -86,6 +90,7 @@ bool rfc3686; bool geniv; bool nodkp; + bool support_tagged_key; }; struct caam_aead_alg { @@ -738,12 +743,19 @@ u32 *desc; const bool is_rfc3686 = alg->caam.rfc3686; - print_hex_dump_debug("key in @"__stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); + /* + * If the algorithm has support for tagged key, + * this is already set in tk_skcipher_setkey(). + * Otherwise, set here the algorithm details. + */ + if (!alg->caam.support_tagged_key) { + ctx->cdata.keylen = keylen; + ctx->cdata.key_virt = key; + ctx->cdata.key_inline = true; + } - ctx->cdata.keylen = keylen; - ctx->cdata.key_virt = key; - ctx->cdata.key_inline = true; + print_hex_dump_debug("key in @" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); /* skcipher_encrypt shared descriptor */ desc = ctx->sh_desc_enc; @@ -815,6 +827,63 @@ return skcipher_setkey(skcipher, key, keylen, ctx1_iv_off); } + +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API +static int tk_skcipher_setkey(struct crypto_skcipher *skcipher, + const u8 *key, unsigned int keylen) +{ + struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher); + struct device *jrdev = ctx->jrdev; + struct header_conf *header; + struct tagged_object *tag_obj; + int ret; + + ctx->cdata.key_inline = true; + + /* Check if one can retrieve the tag object header configuration */ + if (keylen <= TAG_OVERHEAD_SIZE) + return -EINVAL; + + /* Retrieve the tag object */ + tag_obj = (struct tagged_object *)key; + + /* + * Check tag object header configuration + * and retrieve the tag object header configuration + */ + if (is_valid_header_conf(&tag_obj->header)) { + header = &tag_obj->header; + } else { + dev_err(jrdev, + "unable to get tag object header configuration\n"); + return -EINVAL; + } + + /* Check if the tag object header is a black key */ + if (!is_black_key(header)) { + dev_err(jrdev, + "tagged key provided is not a black key\n"); + return -EINVAL; + } + + /* Retrieve the black key configuration */ + get_key_conf(header, + &ctx->cdata.key_real_len, + &ctx->cdata.keylen, + &ctx->cdata.key_cmd_opt); + + /* Retrieve the address of the data of the tagged object */ + ctx->cdata.key_virt = &tag_obj->object; + + /* Validate key length for AES algorithms */ + ret = aes_check_keylen(ctx->cdata.key_real_len); + if (ret) + return ret; + + return skcipher_setkey(skcipher, NULL, 0, 0); +} +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ + static int des_skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key, unsigned int keylen) { @@ -1880,6 +1949,25 @@ }, .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, }, +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API + { + .skcipher = { + .base = { + .cra_name = "tk(cbc(aes))", + .cra_driver_name = "tk-cbc-aes-caam", + .cra_blocksize = AES_BLOCK_SIZE, + }, + .setkey = tk_skcipher_setkey, + .encrypt = skcipher_encrypt, + .decrypt = skcipher_decrypt, + .min_keysize = TAG_MIN_SIZE, + .max_keysize = CAAM_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + }, + .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, + .caam.support_tagged_key = true, + }, +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ { .skcipher = { .base = { @@ -2000,6 +2088,24 @@ }, .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB, }, +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API + { + .skcipher = { + .base = { + .cra_name = "tk(ecb(aes))", + .cra_driver_name = "tk-ecb-aes-caam", + .cra_blocksize = AES_BLOCK_SIZE, + }, + .setkey = tk_skcipher_setkey, + .encrypt = skcipher_encrypt, + .decrypt = skcipher_decrypt, + .min_keysize = TAG_MIN_SIZE, + .max_keysize = CAAM_MAX_KEY_SIZE, + }, + .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB, + .caam.support_tagged_key = true, + }, +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ { .skcipher = { .base = { @@ -3526,13 +3632,14 @@ * First, detect presence and attributes of DES, AES, and MD blocks. */ if (priv->era < 10) { + struct caam_perfmon __iomem *perfmon = &priv->jr[0]->perfmon; u32 cha_vid, cha_inst, aes_rn; - cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls); + cha_vid = rd_reg32(&perfmon->cha_id_ls); aes_vid = cha_vid & CHA_ID_LS_AES_MASK; md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; - cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls); + cha_inst = rd_reg32(&perfmon->cha_num_ls); des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >> CHA_ID_LS_DES_SHIFT; aes_inst = cha_inst & CHA_ID_LS_AES_MASK; @@ -3540,23 +3647,23 @@ ccha_inst = 0; ptha_inst = 0; - aes_rn = rd_reg32(&priv->ctrl->perfmon.cha_rev_ls) & - CHA_ID_LS_AES_MASK; + aes_rn = rd_reg32(&perfmon->cha_rev_ls) & CHA_ID_LS_AES_MASK; gcm_support = !(aes_vid == CHA_VER_VID_AES_LP && aes_rn < 8); } else { + struct version_regs __iomem *vreg = &priv->jr[0]->vreg; u32 aesa, mdha; - aesa = rd_reg32(&priv->ctrl->vreg.aesa); - mdha = rd_reg32(&priv->ctrl->vreg.mdha); + aesa = rd_reg32(&vreg->aesa); + mdha = rd_reg32(&vreg->mdha); aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT; md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT; - des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK; + des_inst = rd_reg32(&vreg->desa) & CHA_VER_NUM_MASK; aes_inst = aesa & CHA_VER_NUM_MASK; md_inst = mdha & CHA_VER_NUM_MASK; - ccha_inst = rd_reg32(&priv->ctrl->vreg.ccha) & CHA_VER_NUM_MASK; - ptha_inst = rd_reg32(&priv->ctrl->vreg.ptha) & CHA_VER_NUM_MASK; + ccha_inst = rd_reg32(&vreg->ccha) & CHA_VER_NUM_MASK; + ptha_inst = rd_reg32(&vreg->ptha) & CHA_VER_NUM_MASK; gcm_support = aesa & CHA_VER_MISC_AES_GCM; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamalg_desc.c linux-imx-phytec/drivers/crypto/caam/caamalg_desc.c --- linux-6.1.55/drivers/crypto/caam/caamalg_desc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/caamalg_desc.c 2024-06-19 12:33:59.740217190 +0200 @@ -623,6 +623,438 @@ EXPORT_SYMBOL(cnstr_shdsc_aead_givencap); /** + * cnstr_shdsc_tls_encap - tls encapsulation shared descriptor + * @desc: pointer to buffer used for descriptor construction + * @cdata: pointer to block cipher transform definitions + * Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed + * with OP_ALG_AAI_CBC + * @adata: pointer to authentication transform definitions. + * A split key is required for SEC Era < 6; the size of the split key + * is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1 + * ANDed with OP_ALG_AAI_HMAC_PRECOMP. + * @assoclen: associated data length + * @ivsize: initialization vector size + * @authsize: authentication data size + * @blocksize: block cipher size + * @era: SEC Era + */ +void cnstr_shdsc_tls_encap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, + unsigned int blocksize, int era) +{ + u32 *key_jump_cmd, *zero_payload_jump_cmd; + u32 genpad, idx_ld_datasz, idx_ld_pad, stidx; + + /* + * Compute the index (in bytes) for the LOAD with destination of + * Class 1 Data Size Register and for the LOAD that generates padding + */ + if (adata->key_inline && cdata->key_inline) { + idx_ld_datasz = DESC_TLS10_ENC_LEN + adata->keylen_pad + + cdata->keylen - 4 * CAAM_CMD_SZ; + idx_ld_pad = DESC_TLS10_ENC_LEN + adata->keylen_pad + + cdata->keylen - 2 * CAAM_CMD_SZ; + } else if (adata->key_inline && !cdata->key_inline) { + idx_ld_datasz = DESC_TLS10_ENC_LEN + adata->keylen_pad + + CAAM_PTR_SZ - 4 * CAAM_CMD_SZ; + idx_ld_pad = DESC_TLS10_ENC_LEN + adata->keylen_pad + + CAAM_PTR_SZ - 2 * CAAM_CMD_SZ; + } else if (adata->key_inline && !cdata->key_inline) { + idx_ld_datasz = DESC_TLS10_ENC_LEN + cdata->keylen + + CAAM_PTR_SZ - 4 * CAAM_CMD_SZ; + idx_ld_pad = DESC_TLS10_ENC_LEN + cdata->keylen + + CAAM_PTR_SZ - 2 * CAAM_CMD_SZ; + } else { + idx_ld_datasz = DESC_TLS10_ENC_LEN + 2 * CAAM_PTR_SZ - + 4 * CAAM_CMD_SZ; + idx_ld_pad = DESC_TLS10_ENC_LEN + 2 * CAAM_PTR_SZ - + 2 * CAAM_CMD_SZ; + } + + stidx = 1 << HDR_START_IDX_SHIFT; + init_sh_desc(desc, HDR_SHARE_SERIAL | stidx); + + /* skip key loading if they are loaded due to sharing */ + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); + + if (era < 6) { + if (adata->key_inline) + append_key_as_imm(desc, adata->key_virt, + adata->keylen_pad, adata->keylen, + CLASS_2 | KEY_DEST_MDHA_SPLIT | + KEY_ENC); + else + append_key(desc, adata->key_dma, adata->keylen, + CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC); + } else { + append_proto_dkp(desc, adata); + } + + if (cdata->key_inline) + append_key_as_imm(desc, cdata->key_virt, cdata->keylen, + cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); + else + append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 | + KEY_DEST_CLASS_REG); + + set_jump_tgt_here(desc, key_jump_cmd); + + /* class 2 operation */ + append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL | + OP_ALG_ENCRYPT); + /* class 1 operation */ + append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL | + OP_ALG_ENCRYPT); + + /* payloadlen = input data length + * - (assoclen + ivsize + xplicit ivsize) + */ + append_math_sub_imm_u32(desc, REG0, SEQINLEN, + IMM, assoclen + 2 * ivsize); + + /* math1 = payloadlen + icvlen + xplicit ivsize */ + append_math_add_imm_u32(desc, REG1, REG0, IMM, authsize + ivsize); + + /* padlen = block_size - math1 % block_size */ + append_math_and_imm_u32(desc, REG3, REG1, IMM, blocksize - 1); + append_math_sub_imm_u32(desc, REG2, IMM, REG3, blocksize); + + /* cryptlen = payloadlen + icvlen + padlen */ + append_math_add(desc, VARSEQOUTLEN, REG1, REG2, 4); + + /* + * update immediate data with the padding length value + * for the LOAD in the class 1 data size register. + */ + append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 | + (idx_ld_datasz << MOVE_OFFSET_SHIFT) | 7); + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF | + (idx_ld_datasz << MOVE_OFFSET_SHIFT) | 8); + + /* overwrite PL field for the padding iNFO FIFO entry */ + append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 | + (idx_ld_pad << MOVE_OFFSET_SHIFT) | 7); + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF | + (idx_ld_pad << MOVE_OFFSET_SHIFT) | 8); + + /* store encrypted payload, icv and padding */ + append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | LDST_VLF); + + /* if payload length is zero, jump to zero-payload commands */ + append_math_add(desc, VARSEQINLEN, ZERO, REG0, 4); + zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL | + JUMP_COND_MATH_Z); + + /* load iv in context1 */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX | + LDST_CLASS_1_CCB | ivsize); + + /* read assoc for authentication */ + append_seq_fifo_load(desc, assoclen, FIFOLD_CLASS_CLASS2 | + FIFOLD_TYPE_MSG); + + /* read xplicit iv in case of >TL10 */ + append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 | + FIFOLD_TYPE_MSG); + + /* insnoop payload */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | FIFOLD_TYPE_MSG | + FIFOLD_TYPE_LAST2 | FIFOLDST_VLF); + + /* jump the zero-payload commands */ + append_jump(desc, JUMP_TEST_ALL | 3); + + /* zero-payload commands */ + set_jump_tgt_here(desc, zero_payload_jump_cmd); + + /* load iv in context1 */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX | + LDST_CLASS_1_CCB | ivsize); + + /* assoc data is the only data for authentication */ + append_seq_fifo_load(desc, assoclen, FIFOLD_CLASS_CLASS2 | + FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST2); + + /* send icv to encryption */ + append_move(desc, MOVE_SRC_CLASS2CTX | MOVE_DEST_CLASS1INFIFO | + authsize); + + /* update class 1 data size register with padding length */ + append_load_imm_u32(desc, 0, LDST_CLASS_1_CCB | + LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM); + + /* generate padding and send it to encryption */ + genpad = NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_LC1 | NFIFOENTRY_FC1 | + NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_PTYPE_N; + append_load_imm_u32(desc, genpad, LDST_CLASS_IND_CCB | + LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM); + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "tls enc shdesc@" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif +} +EXPORT_SYMBOL(cnstr_shdsc_tls_encap); + +/** + * cnstr_shdsc_tls_decap - tls decapsulation shared descriptor + * @desc: pointer to buffer used for descriptor construction + * @cdata: pointer to block cipher transform definitions + * Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed + * with OP_ALG_AAI_CBC + * @adata: pointer to authentication transform definitions. + * A split key is required for SEC Era < 6; the size of the split key + * is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1 + * ANDed with OP_ALG_AAI_HMAC_PRECOMP. + * @assoclen: associated data length + * @ivsize: initialization vector size + * @authsize: authentication data size + * @blocksize: block cipher size + * @era: SEC Era + */ +void cnstr_shdsc_tls_decap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, + unsigned int blocksize, int era) +{ + u32 stidx, jumpback; + u32 *key_jump_cmd, *zero_payload_jump_cmd, *skip_zero_jump_cmd; + /* + * Pointer Size bool determines the size of address pointers. + * false - Pointers fit in one 32-bit word. + * true - Pointers fit in two 32-bit words. + */ + bool ps = (CAAM_PTR_SZ != CAAM_CMD_SZ); + + stidx = 1 << HDR_START_IDX_SHIFT; + init_sh_desc(desc, HDR_SHARE_SERIAL | stidx); + + /* skip key loading if they are loaded due to sharing */ + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); + + if (era < 6) + append_key(desc, adata->key_dma, adata->keylen, CLASS_2 | + KEY_DEST_MDHA_SPLIT | KEY_ENC); + else + append_proto_dkp(desc, adata); + + append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 | + KEY_DEST_CLASS_REG); + + set_jump_tgt_here(desc, key_jump_cmd); + + /* class 2 operation */ + append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL | + OP_ALG_DECRYPT | OP_ALG_ICV_ON); + /* class 1 operation */ + append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL | + OP_ALG_DECRYPT); + + /* VSIL = input data length - 2 * block_size */ + append_math_sub_imm_u32(desc, VARSEQINLEN, SEQINLEN, IMM, 2 * + blocksize); + + /* + * payloadlen + icvlen + padlen = input data length - (assoclen + + * ivsize) + */ + append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, assoclen + ivsize); + + /* skip data to the last but one cipher block */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_SKIP | LDST_VLF); + + /* load iv for the last cipher block */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX | + LDST_CLASS_1_CCB | ivsize); + + /* read last cipher block */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG | + FIFOLD_TYPE_LAST1 | blocksize); + + /* move decrypted block into math0 and math1 */ + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_OUTFIFO | MOVE_DEST_MATH0 | + blocksize); + + /* reset AES CHA */ + append_load_imm_u32(desc, CCTRL_RESET_CHA_AESA, LDST_CLASS_IND_CCB | + LDST_SRCDST_WORD_CHACTRL | LDST_IMM); + + /* rewind input sequence */ + append_seq_in_ptr_intlen(desc, 0, 65535, SQIN_RTO); + + /* key1 is in decryption form */ + append_operation(desc, cdata->algtype | OP_ALG_AAI_DK | + OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT); + + /* load iv in context1 */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_1_CCB | + LDST_SRCDST_WORD_CLASS_CTX | ivsize); + + /* read sequence number */ + append_seq_fifo_load(desc, 8, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG); + /* load Type, Version and Len fields in math0 */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_DECO | + LDST_SRCDST_WORD_DECO_MATH0 | (3 << LDST_OFFSET_SHIFT) | 5); + + /* compute (padlen - 1) */ + append_math_and_imm_u64(desc, REG1, REG1, IMM, 255); + + /* math2 = icvlen + (padlen - 1) + 1 */ + append_math_add_imm_u32(desc, REG2, REG1, IMM, authsize + 1); + + append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1); + + /* VSOL = payloadlen + icvlen + padlen */ + append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, 4); + + if (caam_little_end) + append_moveb(desc, MOVE_WAITCOMP | + MOVE_SRC_MATH0 | MOVE_DEST_MATH0 | 8); + + /* update Len field */ + append_math_sub(desc, REG0, REG0, REG2, 8); + + /* store decrypted payload, icv and padding */ + append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | LDST_VLF); + + /* VSIL = (payloadlen + icvlen + padlen) - (icvlen + padlen)*/ + append_math_sub(desc, VARSEQINLEN, REG3, REG2, 4); + + zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL | + JUMP_COND_MATH_Z); + + /* send Type, Version and Len(pre ICV) fields to authentication */ + append_move(desc, MOVE_WAITCOMP | + MOVE_SRC_MATH0 | MOVE_DEST_CLASS2INFIFO | + (3 << MOVE_OFFSET_SHIFT) | 5); + + /* outsnooping payload */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | + FIFOLD_TYPE_MSG1OUT2 | FIFOLD_TYPE_LAST2 | + FIFOLDST_VLF); + skip_zero_jump_cmd = append_jump(desc, JUMP_TEST_ALL | 2); + + set_jump_tgt_here(desc, zero_payload_jump_cmd); + /* send Type, Version and Len(pre ICV) fields to authentication */ + append_move(desc, MOVE_WAITCOMP | MOVE_AUX_LS | + MOVE_SRC_MATH0 | MOVE_DEST_CLASS2INFIFO | + (3 << MOVE_OFFSET_SHIFT) | 5); + + set_jump_tgt_here(desc, skip_zero_jump_cmd); + append_math_add(desc, VARSEQINLEN, ZERO, REG2, 4); + + /* load icvlen and padlen */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG | + FIFOLD_TYPE_LAST1 | FIFOLDST_VLF); + + /* VSIL = (payloadlen + icvlen + padlen) - icvlen + padlen */ + append_math_sub(desc, VARSEQINLEN, REG3, REG2, 4); + + /* + * Start a new input sequence using the SEQ OUT PTR command options, + * pointer and length used when the current output sequence was defined. + */ + if (ps) { + /* + * Move the lower 32 bits of Shared Descriptor address, the + * SEQ OUT PTR command, Output Pointer (2 words) and + * Output Length into math registers. + */ + if (caam_little_end) + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | + MOVE_DEST_MATH0 | + (55 * 4 << MOVE_OFFSET_SHIFT) | 20); + else + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | + MOVE_DEST_MATH0 | + (54 * 4 << MOVE_OFFSET_SHIFT) | 20); + + /* Transform SEQ OUT PTR command in SEQ IN PTR command */ + append_math_and_imm_u32(desc, REG0, REG0, IMM, + ~(CMD_SEQ_IN_PTR ^ CMD_SEQ_OUT_PTR)); + /* Append a JUMP command after the copied fields */ + jumpback = CMD_JUMP | (char)-9; + append_load_imm_u32(desc, jumpback, LDST_CLASS_DECO | LDST_IMM | + LDST_SRCDST_WORD_DECO_MATH2 | + (4 << LDST_OFFSET_SHIFT)); + append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1); + /* Move the updated fields back to the Job Descriptor */ + if (caam_little_end) + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | + MOVE_DEST_DESCBUF | + (55 * 4 << MOVE_OFFSET_SHIFT) | 24); + else + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | + MOVE_DEST_DESCBUF | + (54 * 4 << MOVE_OFFSET_SHIFT) | 24); + + /* + * Read the new SEQ IN PTR command, Input Pointer, Input Length + * and then jump back to the next command from the + * Shared Descriptor. + */ + append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 6); + } else { + /* + * Move the SEQ OUT PTR command, Output Pointer (1 word) and + * Output Length into math registers. + */ + if (caam_little_end) + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | + MOVE_DEST_MATH0 | + (54 * 4 << MOVE_OFFSET_SHIFT) | 12); + else + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF | + MOVE_DEST_MATH0 | + (53 * 4 << MOVE_OFFSET_SHIFT) | 12); + + /* Transform SEQ OUT PTR command in SEQ IN PTR command */ + append_math_and_imm_u64(desc, REG0, REG0, IMM, + ~(((u64)(CMD_SEQ_IN_PTR ^ + CMD_SEQ_OUT_PTR)) << 32)); + /* Append a JUMP command after the copied fields */ + jumpback = CMD_JUMP | (char)-7; + append_load_imm_u32(desc, jumpback, LDST_CLASS_DECO | LDST_IMM | + LDST_SRCDST_WORD_DECO_MATH1 | + (4 << LDST_OFFSET_SHIFT)); + append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1); + /* Move the updated fields back to the Job Descriptor */ + if (caam_little_end) + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | + MOVE_DEST_DESCBUF | + (54 * 4 << MOVE_OFFSET_SHIFT) | 16); + else + append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 | + MOVE_DEST_DESCBUF | + (53 * 4 << MOVE_OFFSET_SHIFT) | 16); + + /* + * Read the new SEQ IN PTR command, Input Pointer, Input Length + * and then jump back to the next command from the + * Shared Descriptor. + */ + append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 5); + } + + /* skip payload */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_SKIP | FIFOLDST_VLF); + /* check icv */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_ICV | + FIFOLD_TYPE_LAST2 | authsize); + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "tls dec shdesc@" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif +} +EXPORT_SYMBOL(cnstr_shdsc_tls_decap); + +/** * cnstr_shdsc_gcm_encap - gcm encapsulation shared descriptor * @desc: pointer to buffer used for descriptor construction * @cdata: pointer to block cipher transform definitions @@ -1390,8 +1822,18 @@ JUMP_COND_SHRD); /* Load class1 key only */ - append_key_as_imm(desc, cdata->key_virt, cdata->keylen, - cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); + if (IS_ENABLED(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API) && + cdata->key_cmd_opt) + /* + * Black keys can be loaded using only a KEY command + * with ENC=1 and the proper setting of the EKT bit. + */ + append_key_as_imm(desc, cdata->key_virt, cdata->keylen, + cdata->key_real_len, CLASS_1 | + KEY_DEST_CLASS_REG | cdata->key_cmd_opt); + else + append_key_as_imm(desc, cdata->key_virt, cdata->keylen, + cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); /* Load nonce into CONTEXT1 reg */ if (is_rfc3686) { @@ -1465,8 +1907,18 @@ JUMP_COND_SHRD); /* Load class1 key only */ - append_key_as_imm(desc, cdata->key_virt, cdata->keylen, - cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); + if (IS_ENABLED(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API) && + cdata->key_cmd_opt) + /* + * Black keys can be loaded using only a KEY command + * with ENC=1 and the proper setting of the EKT bit. + */ + append_key_as_imm(desc, cdata->key_virt, cdata->keylen, + cdata->key_real_len, CLASS_1 | + KEY_DEST_CLASS_REG | cdata->key_cmd_opt); + else + append_key_as_imm(desc, cdata->key_virt, cdata->keylen, + cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG); /* Load nonce into CONTEXT1 reg */ if (is_rfc3686) { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamalg_desc.h linux-imx-phytec/drivers/crypto/caam/caamalg_desc.h --- linux-6.1.55/drivers/crypto/caam/caamalg_desc.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/caamalg_desc.h 2024-06-19 12:33:59.740217190 +0200 @@ -17,6 +17,9 @@ #define DESC_QI_AEAD_DEC_LEN (DESC_AEAD_DEC_LEN + 3 * CAAM_CMD_SZ) #define DESC_QI_AEAD_GIVENC_LEN (DESC_AEAD_GIVENC_LEN + 3 * CAAM_CMD_SZ) +#define DESC_TLS_BASE (4 * CAAM_CMD_SZ) +#define DESC_TLS10_ENC_LEN (DESC_TLS_BASE + 30 * CAAM_CMD_SZ) + /* Note: Nonce is counted in cdata.keylen */ #define DESC_AEAD_CTR_RFC3686_LEN (4 * CAAM_CMD_SZ) @@ -72,6 +75,16 @@ u32 *nonce, const u32 ctx1_iv_off, const bool is_qi, int era); +void cnstr_shdsc_tls_encap(u32 *const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, + unsigned int blocksize, int era); + +void cnstr_shdsc_tls_decap(u32 *const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, + unsigned int blocksize, int era); + void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata, unsigned int ivsize, unsigned int icvsize, const bool is_qi); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamalg_qi2.c linux-imx-phytec/drivers/crypto/caam/caamalg_qi2.c --- linux-6.1.55/drivers/crypto/caam/caamalg_qi2.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/caamalg_qi2.c 2024-06-19 12:33:59.740217190 +0200 @@ -585,6 +585,254 @@ return edesc; } +static struct tls_edesc *tls_edesc_alloc(struct aead_request *req, + bool encrypt) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + unsigned int blocksize = crypto_aead_blocksize(tls); + unsigned int padsize, authsize; + struct caam_request *req_ctx = aead_request_ctx(req); + struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1]; + struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0]; + struct caam_ctx *ctx = crypto_aead_ctx(tls); + struct caam_aead_alg *alg = container_of(crypto_aead_alg(tls), + typeof(*alg), aead); + struct device *dev = ctx->dev; + gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? + GFP_KERNEL : GFP_ATOMIC; + int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0; + struct tls_edesc *edesc; + dma_addr_t qm_sg_dma, iv_dma = 0; + int ivsize = crypto_aead_ivsize(tls); + u8 *iv; + int qm_sg_index, qm_sg_ents = 0, qm_sg_bytes; + int src_len, dst_len, data_len; + struct dpaa2_sg_entry *sg_table; + struct scatterlist *dst; + + if (encrypt) { + padsize = blocksize - ((req->cryptlen + ctx->authsize) % + blocksize); + authsize = ctx->authsize + padsize; + } else { + authsize = ctx->authsize; + } + + /* allocate space for base edesc, link tables and IV */ + edesc = qi_cache_zalloc(GFP_DMA | flags); + if (unlikely(!edesc)) { + dev_err(dev, "could not allocate extended descriptor\n"); + return ERR_PTR(-ENOMEM); + } + + data_len = req->assoclen + req->cryptlen; + dst_len = req->cryptlen + (encrypt ? authsize : 0); + + if (likely(req->src == req->dst)) { + src_len = req->assoclen + dst_len; + + src_nents = sg_nents_for_len(req->src, src_len); + if (unlikely(src_nents < 0)) { + dev_err(dev, "Insufficient bytes (%d) in src S/G\n", + src_len); + qi_cache_free(edesc); + return ERR_PTR(src_nents); + } + + mapped_src_nents = dma_map_sg(dev, req->src, src_nents, + DMA_BIDIRECTIONAL); + if (unlikely(!mapped_src_nents)) { + dev_err(dev, "unable to map source\n"); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + dst = req->dst; + } else { + src_len = data_len; + + src_nents = sg_nents_for_len(req->src, src_len); + if (unlikely(src_nents < 0)) { + dev_err(dev, "Insufficient bytes (%d) in src S/G\n", + src_len); + qi_cache_free(edesc); + return ERR_PTR(src_nents); + } + + dst = scatterwalk_ffwd(edesc->tmp, req->dst, req->assoclen); + + dst_nents = sg_nents_for_len(dst, dst_len); + if (unlikely(dst_nents < 0)) { + dev_err(dev, "Insufficient bytes (%d) in dst S/G\n", + dst_len); + qi_cache_free(edesc); + return ERR_PTR(dst_nents); + } + + if (src_nents) { + mapped_src_nents = dma_map_sg(dev, req->src, + src_nents, DMA_TO_DEVICE); + if (unlikely(!mapped_src_nents)) { + dev_err(dev, "unable to map source\n"); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + } else { + mapped_src_nents = 0; + } + + mapped_dst_nents = dma_map_sg(dev, dst, dst_nents, + DMA_FROM_DEVICE); + if (unlikely(!mapped_dst_nents)) { + dev_err(dev, "unable to map destination\n"); + dma_unmap_sg(dev, req->src, src_nents, DMA_TO_DEVICE); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + } + + /* + * Create S/G table: IV, src, dst. + * Input is not contiguous. + */ + qm_sg_ents = 1 + mapped_src_nents + + (mapped_dst_nents > 1 ? mapped_dst_nents : 0); + sg_table = &edesc->sgt[0]; + qm_sg_bytes = qm_sg_ents * sizeof(*sg_table); + + iv = (u8 *)(sg_table + qm_sg_ents); + /* Make sure IV is located in a DMAable area */ + memcpy(iv, req->iv, ivsize); + iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE); + if (dma_mapping_error(dev, iv_dma)) { + dev_err(dev, "unable to map IV\n"); + caam_unmap(dev, req->src, dst, src_nents, dst_nents, 0, 0, + DMA_NONE, 0, 0); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + + edesc->src_nents = src_nents; + edesc->dst_nents = dst_nents; + edesc->dst = dst; + edesc->iv_dma = iv_dma; + + dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0); + qm_sg_index = 1; + + sg_to_qm_sg_last(req->src, src_len, sg_table + qm_sg_index, 0); + qm_sg_index += mapped_src_nents; + + if (mapped_dst_nents > 1) + sg_to_qm_sg_last(dst, dst_len, sg_table + qm_sg_index, 0); + + qm_sg_dma = dma_map_single(dev, sg_table, qm_sg_bytes, DMA_TO_DEVICE); + if (dma_mapping_error(dev, qm_sg_dma)) { + dev_err(dev, "unable to map S/G table\n"); + caam_unmap(dev, req->src, dst, src_nents, dst_nents, iv_dma, + ivsize, DMA_TO_DEVICE, 0, 0); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + + edesc->qm_sg_dma = qm_sg_dma; + edesc->qm_sg_bytes = qm_sg_bytes; + + memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt)); + dpaa2_fl_set_final(in_fle, true); + dpaa2_fl_set_format(in_fle, dpaa2_fl_sg); + dpaa2_fl_set_addr(in_fle, qm_sg_dma); + dpaa2_fl_set_len(in_fle, ivsize + data_len); + + if (req->dst == req->src) { + dpaa2_fl_set_format(out_fle, dpaa2_fl_sg); + dpaa2_fl_set_addr(out_fle, qm_sg_dma + + (sg_nents_for_len(req->src, req->assoclen) + + 1) * sizeof(*sg_table)); + } else if (mapped_dst_nents == 1) { + dpaa2_fl_set_format(out_fle, dpaa2_fl_single); + dpaa2_fl_set_addr(out_fle, sg_dma_address(dst)); + } else { + dpaa2_fl_set_format(out_fle, dpaa2_fl_sg); + dpaa2_fl_set_addr(out_fle, qm_sg_dma + qm_sg_index * + sizeof(*sg_table)); + } + + dpaa2_fl_set_len(out_fle, dst_len); + + return edesc; +} + +static int tls_set_sh_desc(struct crypto_aead *tls) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + unsigned int ivsize = crypto_aead_ivsize(tls); + unsigned int blocksize = crypto_aead_blocksize(tls); + struct device *dev = ctx->dev; + struct dpaa2_caam_priv *priv = dev_get_drvdata(dev); + struct caam_flc *flc; + u32 *desc; + unsigned int assoclen = 13; /* always 13 bytes for TLS */ + unsigned int data_len[2]; + u32 inl_mask; + + if (!ctx->cdata.keylen || !ctx->authsize) + return 0; + + /* + * TLS 1.0 encrypt shared descriptor + * Job Descriptor and Shared Descriptor + * must fit into the 64-word Descriptor h/w Buffer + */ + data_len[0] = ctx->adata.keylen_pad; + data_len[1] = ctx->cdata.keylen; + + if (desc_inline_query(DESC_TLS10_ENC_LEN, DESC_JOB_IO_LEN, data_len, + &inl_mask, ARRAY_SIZE(data_len)) < 0) + return -EINVAL; + + if (inl_mask & 1) + ctx->adata.key_virt = ctx->key; + else + ctx->adata.key_dma = ctx->key_dma; + + if (inl_mask & 2) + ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad; + else + ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; + + ctx->adata.key_inline = !!(inl_mask & 1); + ctx->cdata.key_inline = !!(inl_mask & 2); + + flc = &ctx->flc[ENCRYPT]; + desc = flc->sh_desc; + cnstr_shdsc_tls_encap(desc, &ctx->cdata, &ctx->adata, + assoclen, ivsize, ctx->authsize, blocksize, + priv->sec_attr.era); + flc->flc[1] = cpu_to_caam32(desc_len(desc)); + dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT], + sizeof(flc->flc) + desc_bytes(desc), + ctx->dir); + + /* + * TLS 1.0 decrypt shared descriptor + * Keys do not fit inline, regardless of algorithms used + */ + ctx->adata.key_inline = false; + ctx->adata.key_dma = ctx->key_dma; + ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; + + flc = &ctx->flc[DECRYPT]; + desc = flc->sh_desc; + cnstr_shdsc_tls_decap(desc, &ctx->cdata, &ctx->adata, assoclen, ivsize, + ctx->authsize, blocksize, priv->sec_attr.era); + flc->flc[1] = cpu_to_caam32(desc_len(desc)); + dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT], + sizeof(flc->flc) + desc_bytes(desc), + ctx->dir); + + return 0; +} + static int chachapoly_set_sh_desc(struct crypto_aead *aead) { struct caam_ctx *ctx = crypto_aead_ctx(aead); @@ -629,6 +877,60 @@ return chachapoly_set_sh_desc(aead); } +static int tls_setkey(struct crypto_aead *tls, const u8 *key, + unsigned int keylen) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + struct device *dev = ctx->dev; + struct crypto_authenc_keys keys; + + if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) + goto badkey; + +#ifdef DEBUG + dev_err(dev, "keylen %d enckeylen %d authkeylen %d\n", + keys.authkeylen + keys.enckeylen, keys.enckeylen, + keys.authkeylen); + print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); +#endif + + ctx->adata.keylen = keys.authkeylen; + ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & + OP_ALG_ALGSEL_MASK); + + if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE) + goto badkey; + + memcpy(ctx->key, keys.authkey, keys.authkeylen); + memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen); + dma_sync_single_for_device(dev, ctx->key_dma, ctx->adata.keylen_pad + + keys.enckeylen, ctx->dir); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, + ctx->adata.keylen_pad + keys.enckeylen, 1); +#endif + + ctx->cdata.keylen = keys.enckeylen; + + memzero_explicit(&keys, sizeof(keys)); + return tls_set_sh_desc(tls); +badkey: + memzero_explicit(&keys, sizeof(keys)); + return -EINVAL; +} + +static int tls_setauthsize(struct crypto_aead *tls, unsigned int authsize) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + + ctx->authsize = authsize; + tls_set_sh_desc(tls); + + return 0; +} + static int chachapoly_setkey(struct crypto_aead *aead, const u8 *key, unsigned int keylen) { @@ -1267,6 +1569,17 @@ dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE); } +static void tls_unmap(struct device *dev, struct tls_edesc *edesc, + struct aead_request *req) +{ + struct crypto_aead *tls = crypto_aead_reqtfm(req); + int ivsize = crypto_aead_ivsize(tls); + + caam_unmap(dev, req->src, edesc->dst, edesc->src_nents, + edesc->dst_nents, edesc->iv_dma, ivsize, DMA_TO_DEVICE, + edesc->qm_sg_dma, edesc->qm_sg_bytes); +} + static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc, struct skcipher_request *req) { @@ -1278,28 +1591,7 @@ edesc->qm_sg_bytes); } -static void aead_encrypt_done(void *cbk_ctx, u32 status) -{ - struct crypto_async_request *areq = cbk_ctx; - struct aead_request *req = container_of(areq, struct aead_request, - base); - struct caam_request *req_ctx = to_caam_req(areq); - struct aead_edesc *edesc = req_ctx->edesc; - struct crypto_aead *aead = crypto_aead_reqtfm(req); - struct caam_ctx *ctx = crypto_aead_ctx(aead); - int ecode = 0; - - dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); - - if (unlikely(status)) - ecode = caam_qi2_strstatus(ctx->dev, status); - - aead_unmap(ctx->dev, edesc, req); - qi_cache_free(edesc); - aead_request_complete(req, ecode); -} - -static void aead_decrypt_done(void *cbk_ctx, u32 status) +static void aead_crypt_done(void *cbk_ctx, u32 status) { struct crypto_async_request *areq = cbk_ctx; struct aead_request *req = container_of(areq, struct aead_request, @@ -1320,7 +1612,7 @@ aead_request_complete(req, ecode); } -static int aead_encrypt(struct aead_request *req) +static int aead_crypt(struct aead_request *req, enum optype op) { struct aead_edesc *edesc; struct crypto_aead *aead = crypto_aead_reqtfm(req); @@ -1329,13 +1621,13 @@ int ret; /* allocate extended descriptor */ - edesc = aead_edesc_alloc(req, true); + edesc = aead_edesc_alloc(req, op == ENCRYPT); if (IS_ERR(edesc)) return PTR_ERR(edesc); - caam_req->flc = &ctx->flc[ENCRYPT]; - caam_req->flc_dma = ctx->flc_dma[ENCRYPT]; - caam_req->cbk = aead_encrypt_done; + caam_req->flc = &ctx->flc[op]; + caam_req->flc_dma = ctx->flc_dma[op]; + caam_req->cbk = aead_crypt_done; caam_req->ctx = &req->base; caam_req->edesc = edesc; ret = dpaa2_caam_enqueue(ctx->dev, caam_req); @@ -1348,83 +1640,88 @@ return ret; } +static int aead_encrypt(struct aead_request *req) +{ + return aead_crypt(req, ENCRYPT); +} + static int aead_decrypt(struct aead_request *req) { - struct aead_edesc *edesc; - struct crypto_aead *aead = crypto_aead_reqtfm(req); - struct caam_ctx *ctx = crypto_aead_ctx(aead); + return aead_crypt(req, DECRYPT); +} + +static void tls_crypt_done(void *cbk_ctx, u32 status) +{ + struct crypto_async_request *areq = cbk_ctx; + struct aead_request *req = container_of(areq, struct aead_request, + base); + struct caam_request *req_ctx = to_caam_req(areq); + struct tls_edesc *edesc = req_ctx->edesc; + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(tls); + int ecode = 0; + +#ifdef DEBUG + dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); +#endif + + if (unlikely(status)) + ecode = caam_qi2_strstatus(ctx->dev, status); + + tls_unmap(ctx->dev, edesc, req); + qi_cache_free(edesc); + aead_request_complete(req, ecode); +} + +static int tls_crypt(struct aead_request *req, enum optype op) +{ + struct tls_edesc *edesc; + struct crypto_aead *tls = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(tls); struct caam_request *caam_req = aead_request_ctx(req); int ret; /* allocate extended descriptor */ - edesc = aead_edesc_alloc(req, false); + edesc = tls_edesc_alloc(req, op == ENCRYPT); if (IS_ERR(edesc)) return PTR_ERR(edesc); - caam_req->flc = &ctx->flc[DECRYPT]; - caam_req->flc_dma = ctx->flc_dma[DECRYPT]; - caam_req->cbk = aead_decrypt_done; + caam_req->flc = &ctx->flc[op]; + caam_req->flc_dma = ctx->flc_dma[op]; + caam_req->cbk = tls_crypt_done; caam_req->ctx = &req->base; caam_req->edesc = edesc; ret = dpaa2_caam_enqueue(ctx->dev, caam_req); if (ret != -EINPROGRESS && !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { - aead_unmap(ctx->dev, edesc, req); + tls_unmap(ctx->dev, edesc, req); qi_cache_free(edesc); } return ret; } -static int ipsec_gcm_encrypt(struct aead_request *req) +static int tls_encrypt(struct aead_request *req) { - return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_encrypt(req); + return tls_crypt(req, ENCRYPT); } -static int ipsec_gcm_decrypt(struct aead_request *req) +static int tls_decrypt(struct aead_request *req) { - return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_decrypt(req); + return tls_crypt(req, DECRYPT); } -static void skcipher_encrypt_done(void *cbk_ctx, u32 status) +static int ipsec_gcm_encrypt(struct aead_request *req) { - struct crypto_async_request *areq = cbk_ctx; - struct skcipher_request *req = skcipher_request_cast(areq); - struct caam_request *req_ctx = to_caam_req(areq); - struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); - struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher); - struct skcipher_edesc *edesc = req_ctx->edesc; - int ecode = 0; - int ivsize = crypto_skcipher_ivsize(skcipher); - - dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); - - if (unlikely(status)) - ecode = caam_qi2_strstatus(ctx->dev, status); - - print_hex_dump_debug("dstiv @" __stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->iv, - edesc->src_nents > 1 ? 100 : ivsize, 1); - caam_dump_sg("dst @" __stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->dst, - edesc->dst_nents > 1 ? 100 : req->cryptlen, 1); - - skcipher_unmap(ctx->dev, edesc, req); - - /* - * The crypto API expects us to set the IV (req->iv) to the last - * ciphertext block (CBC mode) or last counter (CTR mode). - * This is used e.g. by the CTS mode. - */ - if (!ecode) - memcpy(req->iv, (u8 *)&edesc->sgt[0] + edesc->qm_sg_bytes, - ivsize); + return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_encrypt(req); +} - qi_cache_free(edesc); - skcipher_request_complete(req, ecode); +static int ipsec_gcm_decrypt(struct aead_request *req) +{ + return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_decrypt(req); } -static void skcipher_decrypt_done(void *cbk_ctx, u32 status) +static void skcipher_crypt_done(void *cbk_ctx, u32 status) { struct crypto_async_request *areq = cbk_ctx; struct skcipher_request *req = skcipher_request_cast(areq); @@ -1470,7 +1767,7 @@ return !!get_unaligned((u64 *)(req->iv + (ivsize / 2))); } -static int skcipher_encrypt(struct skcipher_request *req) +static int skcipher_crypt(struct skcipher_request *req, enum optype op) { struct skcipher_edesc *edesc; struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); @@ -1497,7 +1794,9 @@ skcipher_request_set_crypt(&caam_req->fallback_req, req->src, req->dst, req->cryptlen, req->iv); - return crypto_skcipher_encrypt(&caam_req->fallback_req); + return (op == ENCRYPT) ? + crypto_skcipher_encrypt(&caam_req->fallback_req) : + crypto_skcipher_decrypt(&caam_req->fallback_req); } /* allocate extended descriptor */ @@ -1505,9 +1804,9 @@ if (IS_ERR(edesc)) return PTR_ERR(edesc); - caam_req->flc = &ctx->flc[ENCRYPT]; - caam_req->flc_dma = ctx->flc_dma[ENCRYPT]; - caam_req->cbk = skcipher_encrypt_done; + caam_req->flc = &ctx->flc[op]; + caam_req->flc_dma = ctx->flc_dma[op]; + caam_req->cbk = skcipher_crypt_done; caam_req->ctx = &req->base; caam_req->edesc = edesc; ret = dpaa2_caam_enqueue(ctx->dev, caam_req); @@ -1520,54 +1819,14 @@ return ret; } -static int skcipher_decrypt(struct skcipher_request *req) +static int skcipher_encrypt(struct skcipher_request *req) { - struct skcipher_edesc *edesc; - struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); - struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher); - struct caam_request *caam_req = skcipher_request_ctx(req); - struct dpaa2_caam_priv *priv = dev_get_drvdata(ctx->dev); - int ret; - - /* - * XTS is expected to return an error even for input length = 0 - * Note that the case input length < block size will be caught during - * HW offloading and return an error. - */ - if (!req->cryptlen && !ctx->fallback) - return 0; - - if (ctx->fallback && ((priv->sec_attr.era <= 8 && xts_skcipher_ivsize(req)) || - ctx->xts_key_fallback)) { - skcipher_request_set_tfm(&caam_req->fallback_req, ctx->fallback); - skcipher_request_set_callback(&caam_req->fallback_req, - req->base.flags, - req->base.complete, - req->base.data); - skcipher_request_set_crypt(&caam_req->fallback_req, req->src, - req->dst, req->cryptlen, req->iv); - - return crypto_skcipher_decrypt(&caam_req->fallback_req); - } - - /* allocate extended descriptor */ - edesc = skcipher_edesc_alloc(req); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - - caam_req->flc = &ctx->flc[DECRYPT]; - caam_req->flc_dma = ctx->flc_dma[DECRYPT]; - caam_req->cbk = skcipher_decrypt_done; - caam_req->ctx = &req->base; - caam_req->edesc = edesc; - ret = dpaa2_caam_enqueue(ctx->dev, caam_req); - if (ret != -EINPROGRESS && - !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { - skcipher_unmap(ctx->dev, edesc, req); - qi_cache_free(edesc); - } + return skcipher_crypt(req, ENCRYPT); +} - return ret; +static int skcipher_decrypt(struct skcipher_request *req) +{ + return skcipher_crypt(req, DECRYPT); } static int caam_cra_init(struct caam_ctx *ctx, struct caam_alg_entry *caam, @@ -3000,6 +3259,46 @@ .geniv = true, }, }, + { + .aead = { + .base = { + .cra_name = "tls11(hmac(sha1),cbc(aes))", + .cra_driver_name = "tls11-hmac-sha1-cbc-aes-caam-qi2", + .cra_blocksize = AES_BLOCK_SIZE, + }, + .setkey = tls_setkey, + .setauthsize = tls_setauthsize, + .encrypt = tls_encrypt, + .decrypt = tls_decrypt, + .ivsize = AES_BLOCK_SIZE, + .maxauthsize = SHA1_DIGEST_SIZE, + }, + .caam = { + .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA1 | + OP_ALG_AAI_HMAC_PRECOMP, + }, + }, + { + .aead = { + .base = { + .cra_name = "tls12(hmac(sha256),cbc(aes))", + .cra_driver_name = "tls12-hmac-sha256-cbc-aes-caam-qi2", + .cra_blocksize = AES_BLOCK_SIZE, + }, + .setkey = tls_setkey, + .setauthsize = tls_setauthsize, + .encrypt = tls_encrypt, + .decrypt = tls_decrypt, + .ivsize = AES_BLOCK_SIZE, + .maxauthsize = SHA256_DIGEST_SIZE, + }, + .caam = { + .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA256 | + OP_ALG_AAI_HMAC_PRECOMP, + }, + }, }; static void caam_skcipher_alg_init(struct caam_skcipher_alg *t_alg) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamalg_qi2.h linux-imx-phytec/drivers/crypto/caam/caamalg_qi2.h --- linux-6.1.55/drivers/crypto/caam/caamalg_qi2.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/caamalg_qi2.h 2024-06-19 12:33:59.740217190 +0200 @@ -119,6 +119,28 @@ }; /* + * tls_edesc - s/w-extended tls descriptor + * @src_nents: number of segments in input scatterlist + * @dst_nents: number of segments in output scatterlist + * @iv_dma: dma address of iv for checking continuity and link table + * @qm_sg_bytes: length of dma mapped h/w link table + * @qm_sg_dma: bus physical mapped address of h/w link table + * @tmp: array of scatterlists used by 'scatterwalk_ffwd' + * @dst: pointer to output scatterlist, usefull for unmapping + * @sgt: the h/w link table, followed by IV + */ +struct tls_edesc { + int src_nents; + int dst_nents; + dma_addr_t iv_dma; + int qm_sg_bytes; + dma_addr_t qm_sg_dma; + struct scatterlist tmp[2]; + struct scatterlist *dst; + struct dpaa2_sg_entry sgt[0]; +}; + +/* * skcipher_edesc - s/w-extended skcipher descriptor * @src_nents: number of segments in input scatterlist * @dst_nents: number of segments in output scatterlist diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamalg_qi.c linux-imx-phytec/drivers/crypto/caam/caamalg_qi.c --- linux-6.1.55/drivers/crypto/caam/caamalg_qi.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/caamalg_qi.c 2024-06-19 12:33:59.740217190 +0200 @@ -297,6 +297,166 @@ return err; } +static int tls_set_sh_desc(struct crypto_aead *tls) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + unsigned int ivsize = crypto_aead_ivsize(tls); + unsigned int blocksize = crypto_aead_blocksize(tls); + unsigned int assoclen = 13; /* always 13 bytes for TLS */ + unsigned int data_len[2]; + u32 inl_mask; + struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent); + + if (!ctx->cdata.keylen || !ctx->authsize) + return 0; + + /* + * TLS 1.0 encrypt shared descriptor + * Job Descriptor and Shared Descriptor + * must fit into the 64-word Descriptor h/w Buffer + */ + data_len[0] = ctx->adata.keylen_pad; + data_len[1] = ctx->cdata.keylen; + + if (desc_inline_query(DESC_TLS10_ENC_LEN, DESC_JOB_IO_LEN, data_len, + &inl_mask, ARRAY_SIZE(data_len)) < 0) + return -EINVAL; + + if (inl_mask & 1) + ctx->adata.key_virt = ctx->key; + else + ctx->adata.key_dma = ctx->key_dma; + + if (inl_mask & 2) + ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad; + else + ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; + + ctx->adata.key_inline = !!(inl_mask & 1); + ctx->cdata.key_inline = !!(inl_mask & 2); + + cnstr_shdsc_tls_encap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata, + assoclen, ivsize, ctx->authsize, blocksize, + ctrlpriv->era); + + /* + * TLS 1.0 decrypt shared descriptor + * Keys do not fit inline, regardless of algorithms used + */ + ctx->adata.key_inline = false; + ctx->adata.key_dma = ctx->key_dma; + ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; + + cnstr_shdsc_tls_decap(ctx->sh_desc_dec, &ctx->cdata, &ctx->adata, + assoclen, ivsize, ctx->authsize, blocksize, + ctrlpriv->era); + + return 0; +} + +static int tls_setauthsize(struct crypto_aead *tls, unsigned int authsize) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + + ctx->authsize = authsize; + tls_set_sh_desc(tls); + + return 0; +} + +static int tls_setkey(struct crypto_aead *tls, const u8 *key, + unsigned int keylen) +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + struct device *jrdev = ctx->jrdev; + struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent); + struct crypto_authenc_keys keys; + int ret = 0; + + if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) + goto badkey; + +#ifdef DEBUG + dev_err(jrdev, "keylen %d enckeylen %d authkeylen %d\n", + keys.authkeylen + keys.enckeylen, keys.enckeylen, + keys.authkeylen); + print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); +#endif + + /* + * If DKP is supported, use it in the shared descriptor to generate + * the split key. + */ + if (ctrlpriv->era >= 6) { + ctx->adata.keylen = keys.authkeylen; + ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & + OP_ALG_ALGSEL_MASK); + + if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE) + goto badkey; + + memcpy(ctx->key, keys.authkey, keys.authkeylen); + memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, + keys.enckeylen); + dma_sync_single_for_device(jrdev, ctx->key_dma, + ctx->adata.keylen_pad + + keys.enckeylen, ctx->dir); + goto skip_split_key; + } + + ret = gen_split_key(jrdev, ctx->key, &ctx->adata, keys.authkey, + keys.authkeylen, CAAM_MAX_KEY_SIZE - + keys.enckeylen); + if (ret) + goto badkey; + + /* postpend encryption key to auth split key */ + memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen); + dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->adata.keylen_pad + + keys.enckeylen, ctx->dir); + +#ifdef DEBUG + dev_err(jrdev, "split keylen %d split keylen padded %d\n", + ctx->adata.keylen, ctx->adata.keylen_pad); + print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, + ctx->adata.keylen_pad + keys.enckeylen, 1); +#endif + +skip_split_key: + ctx->cdata.keylen = keys.enckeylen; + + ret = tls_set_sh_desc(tls); + if (ret) + goto badkey; + + /* Now update the driver contexts with the new shared descriptor */ + if (ctx->drv_ctx[ENCRYPT]) { + ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT], + ctx->sh_desc_enc); + if (ret) { + dev_err(jrdev, "driver enc context update failed\n"); + goto badkey; + } + } + + if (ctx->drv_ctx[DECRYPT]) { + ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT], + ctx->sh_desc_dec); + if (ret) { + dev_err(jrdev, "driver dec context update failed\n"); + goto badkey; + } + } + + memzero_explicit(&keys, sizeof(keys)); + return ret; +badkey: + memzero_explicit(&keys, sizeof(keys)); + return -EINVAL; +} + static int gcm_set_sh_desc(struct crypto_aead *aead) { struct caam_ctx *ctx = crypto_aead_ctx(aead); @@ -807,6 +967,29 @@ }; /* + * tls_edesc - s/w-extended tls descriptor + * @src_nents: number of segments in input scatterlist + * @dst_nents: number of segments in output scatterlist + * @iv_dma: dma address of iv for checking continuity and link table + * @qm_sg_bytes: length of dma mapped h/w link table + * @tmp: array of scatterlists used by 'scatterwalk_ffwd' + * @qm_sg_dma: bus physical mapped address of h/w link table + * @drv_req: driver-specific request structure + * @sgt: the h/w link table, followed by IV + */ +struct tls_edesc { + int src_nents; + int dst_nents; + dma_addr_t iv_dma; + int qm_sg_bytes; + dma_addr_t qm_sg_dma; + struct scatterlist tmp[2]; + struct scatterlist *dst; + struct caam_drv_req drv_req; + struct qm_sg_entry sgt[0]; +}; + +/* * skcipher_edesc - s/w-extended skcipher descriptor * @src_nents: number of segments in input scatterlist * @dst_nents: number of segments in output scatterlist @@ -898,6 +1081,18 @@ dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE); } +static void tls_unmap(struct device *dev, + struct tls_edesc *edesc, + struct aead_request *req) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + int ivsize = crypto_aead_ivsize(aead); + + caam_unmap(dev, req->src, edesc->dst, edesc->src_nents, + edesc->dst_nents, edesc->iv_dma, ivsize, DMA_TO_DEVICE, + edesc->qm_sg_dma, edesc->qm_sg_bytes); +} + static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc, struct skcipher_request *req) { @@ -1190,6 +1385,238 @@ return aead_crypt(req, false); } +static void tls_done(struct caam_drv_req *drv_req, u32 status) +{ + struct device *qidev; + struct tls_edesc *edesc; + struct aead_request *aead_req = drv_req->app_ctx; + struct crypto_aead *aead = crypto_aead_reqtfm(aead_req); + struct caam_ctx *caam_ctx = crypto_aead_ctx(aead); + int ecode = 0; + + qidev = caam_ctx->qidev; + + if (unlikely(status)) + ecode = caam_jr_strstatus(qidev, status); + + edesc = container_of(drv_req, typeof(*edesc), drv_req); + tls_unmap(qidev, edesc, aead_req); + + aead_request_complete(aead_req, ecode); + qi_cache_free(edesc); +} + +/* + * allocate and map the tls extended descriptor + */ +static struct tls_edesc *tls_edesc_alloc(struct aead_request *req, bool encrypt) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(aead); + unsigned int blocksize = crypto_aead_blocksize(aead); + unsigned int padsize, authsize; + struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead), + typeof(*alg), aead); + struct device *qidev = ctx->qidev; + gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? + GFP_KERNEL : GFP_ATOMIC; + int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0; + struct tls_edesc *edesc; + dma_addr_t qm_sg_dma, iv_dma = 0; + int ivsize = crypto_aead_ivsize(aead); + u8 *iv; + int qm_sg_index, qm_sg_ents = 0, qm_sg_bytes; + int src_len, dst_len, data_len; + struct qm_sg_entry *sg_table, *fd_sgt; + struct caam_drv_ctx *drv_ctx; + struct scatterlist *dst; + + if (encrypt) { + padsize = blocksize - ((req->cryptlen + ctx->authsize) % + blocksize); + authsize = ctx->authsize + padsize; + } else { + authsize = ctx->authsize; + } + + drv_ctx = get_drv_ctx(ctx, encrypt ? ENCRYPT : DECRYPT); + if (unlikely(IS_ERR_OR_NULL(drv_ctx))) + return (struct tls_edesc *)drv_ctx; + + /* allocate space for base edesc, link tables and IV */ + edesc = qi_cache_alloc(GFP_DMA | flags); + if (unlikely(!edesc)) { + dev_err(qidev, "could not allocate extended descriptor\n"); + return ERR_PTR(-ENOMEM); + } + + data_len = req->assoclen + req->cryptlen; + dst_len = req->cryptlen + (encrypt ? authsize : 0); + + if (likely(req->src == req->dst)) { + src_len = req->assoclen + dst_len; + + src_nents = sg_nents_for_len(req->src, src_len); + if (unlikely(src_nents < 0)) { + dev_err(qidev, "Insufficient bytes (%d) in src S/G\n", + src_len); + qi_cache_free(edesc); + return ERR_PTR(src_nents); + } + + mapped_src_nents = dma_map_sg(qidev, req->src, src_nents, + DMA_BIDIRECTIONAL); + if (unlikely(!mapped_src_nents)) { + dev_err(qidev, "unable to map source\n"); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + dst = req->dst; + } else { + src_len = data_len; + + src_nents = sg_nents_for_len(req->src, src_len); + if (unlikely(src_nents < 0)) { + dev_err(qidev, "Insufficient bytes (%d) in src S/G\n", + src_len); + qi_cache_free(edesc); + return ERR_PTR(src_nents); + } + + dst = scatterwalk_ffwd(edesc->tmp, req->dst, req->assoclen); + + dst_nents = sg_nents_for_len(dst, dst_len); + if (unlikely(dst_nents < 0)) { + dev_err(qidev, "Insufficient bytes (%d) in dst S/G\n", + dst_len); + qi_cache_free(edesc); + return ERR_PTR(dst_nents); + } + + if (src_nents) { + mapped_src_nents = dma_map_sg(qidev, req->src, + src_nents, DMA_TO_DEVICE); + if (unlikely(!mapped_src_nents)) { + dev_err(qidev, "unable to map source\n"); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + } else { + mapped_src_nents = 0; + } + + mapped_dst_nents = dma_map_sg(qidev, dst, dst_nents, + DMA_FROM_DEVICE); + if (unlikely(!mapped_dst_nents)) { + dev_err(qidev, "unable to map destination\n"); + dma_unmap_sg(qidev, req->src, src_nents, DMA_TO_DEVICE); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + } + + /* + * Create S/G table: IV, src, dst. + * Input is not contiguous. + */ + qm_sg_ents = 1 + mapped_src_nents + + (mapped_dst_nents > 1 ? mapped_dst_nents : 0); + sg_table = &edesc->sgt[0]; + qm_sg_bytes = qm_sg_ents * sizeof(*sg_table); + + iv = (u8 *)(sg_table + qm_sg_ents); + /* Make sure IV is located in a DMAable area */ + memcpy(iv, req->iv, ivsize); + iv_dma = dma_map_single(qidev, iv, ivsize, DMA_TO_DEVICE); + if (dma_mapping_error(qidev, iv_dma)) { + dev_err(qidev, "unable to map IV\n"); + caam_unmap(qidev, req->src, dst, src_nents, dst_nents, 0, 0, + DMA_NONE, 0, 0); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + + edesc->src_nents = src_nents; + edesc->dst_nents = dst_nents; + edesc->dst = dst; + edesc->iv_dma = iv_dma; + edesc->drv_req.app_ctx = req; + edesc->drv_req.cbk = tls_done; + edesc->drv_req.drv_ctx = drv_ctx; + + dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0); + qm_sg_index = 1; + + sg_to_qm_sg_last(req->src, src_len, sg_table + qm_sg_index, 0); + qm_sg_index += mapped_src_nents; + + if (mapped_dst_nents > 1) + sg_to_qm_sg_last(dst, dst_len, sg_table + qm_sg_index, 0); + + qm_sg_dma = dma_map_single(qidev, sg_table, qm_sg_bytes, DMA_TO_DEVICE); + if (dma_mapping_error(qidev, qm_sg_dma)) { + dev_err(qidev, "unable to map S/G table\n"); + caam_unmap(qidev, req->src, dst, src_nents, dst_nents, iv_dma, + ivsize, DMA_TO_DEVICE, 0, 0); + qi_cache_free(edesc); + return ERR_PTR(-ENOMEM); + } + + edesc->qm_sg_dma = qm_sg_dma; + edesc->qm_sg_bytes = qm_sg_bytes; + + fd_sgt = &edesc->drv_req.fd_sgt[0]; + + dma_to_qm_sg_one_last_ext(&fd_sgt[1], qm_sg_dma, ivsize + data_len, 0); + + if (req->dst == req->src) + dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma + + (sg_nents_for_len(req->src, req->assoclen) + + 1) * sizeof(*sg_table), dst_len, 0); + else if (mapped_dst_nents == 1) + dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(dst), dst_len, 0); + else + dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma + sizeof(*sg_table) * + qm_sg_index, dst_len, 0); + + return edesc; +} + +static int tls_crypt(struct aead_request *req, bool encrypt) +{ + struct tls_edesc *edesc; + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(aead); + int ret; + + if (unlikely(caam_congested)) + return -EAGAIN; + + edesc = tls_edesc_alloc(req, encrypt); + if (IS_ERR_OR_NULL(edesc)) + return PTR_ERR(edesc); + + ret = caam_qi_enqueue(ctx->qidev, &edesc->drv_req); + if (!ret) { + ret = -EINPROGRESS; + } else { + tls_unmap(ctx->qidev, edesc, req); + qi_cache_free(edesc); + } + + return ret; +} + +static int tls_encrypt(struct aead_request *req) +{ + return tls_crypt(req, true); +} + +static int tls_decrypt(struct aead_request *req) +{ + return tls_crypt(req, false); +} + static int ipsec_gcm_encrypt(struct aead_request *req) { return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_crypt(req, @@ -2440,6 +2867,46 @@ .geniv = true, } }, + { + .aead = { + .base = { + .cra_name = "tls11(hmac(sha1),cbc(aes))", + .cra_driver_name = "tls11-hmac-sha1-cbc-aes-caam-qi", + .cra_blocksize = AES_BLOCK_SIZE, + }, + .setkey = tls_setkey, + .setauthsize = tls_setauthsize, + .encrypt = tls_encrypt, + .decrypt = tls_decrypt, + .ivsize = AES_BLOCK_SIZE, + .maxauthsize = SHA1_DIGEST_SIZE, + }, + .caam = { + .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA1 | + OP_ALG_AAI_HMAC_PRECOMP, + }, + }, + { + .aead = { + .base = { + .cra_name = "tls12(hmac(sha256),cbc(aes))", + .cra_driver_name = "tls12-hmac-sha256-cbc-aes-caam-qi", + .cra_blocksize = AES_BLOCK_SIZE, + }, + .setkey = tls_setkey, + .setauthsize = tls_setauthsize, + .encrypt = tls_encrypt, + .decrypt = tls_decrypt, + .ivsize = AES_BLOCK_SIZE, + .maxauthsize = SHA256_DIGEST_SIZE, + }, + .caam = { + .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA256 | + OP_ALG_AAI_HMAC_PRECOMP, + } + } }; static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam, @@ -2447,6 +2914,16 @@ { struct caam_drv_private *priv; struct device *dev; + /* Digest sizes for MD5, SHA1, SHA-224, SHA-256, SHA-384, SHA-512 */ + static const u8 digest_size[] = { + MD5_DIGEST_SIZE, + SHA1_DIGEST_SIZE, + SHA224_DIGEST_SIZE, + SHA256_DIGEST_SIZE, + SHA384_DIGEST_SIZE, + SHA512_DIGEST_SIZE + }; + u8 op_id; /* * distribute tfms across job rings to ensure in-order @@ -2478,6 +2955,21 @@ ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type; ctx->qidev = dev; + if (ctx->adata.algtype) { + op_id = (ctx->adata.algtype & OP_ALG_ALGSEL_SUBMASK) + >> OP_ALG_ALGSEL_SHIFT; + if (op_id < ARRAY_SIZE(digest_size)) { + ctx->authsize = digest_size[op_id]; + } else { + dev_err(ctx->jrdev, + "incorrect op_id %d; must be less than %zu\n", + op_id, ARRAY_SIZE(digest_size)); + caam_jr_free(ctx->jrdev); + return -EINVAL; + } + } else { + ctx->authsize = 0; + } spin_lock_init(&ctx->lock); ctx->drv_ctx[ENCRYPT] = NULL; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamhash.c linux-imx-phytec/drivers/crypto/caam/caamhash.c --- linux-6.1.55/drivers/crypto/caam/caamhash.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/caamhash.c 2024-06-19 12:33:59.740217190 +0200 @@ -1949,12 +1949,14 @@ * presence and attributes of MD block. */ if (priv->era < 10) { - md_vid = (rd_reg32(&priv->ctrl->perfmon.cha_id_ls) & + struct caam_perfmon __iomem *perfmon = &priv->jr[0]->perfmon; + + md_vid = (rd_reg32(&perfmon->cha_id_ls) & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; - md_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & + md_inst = (rd_reg32(&perfmon->cha_num_ls) & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT; } else { - u32 mdha = rd_reg32(&priv->ctrl->vreg.mdha); + u32 mdha = rd_reg32(&priv->jr[0]->vreg.mdha); md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT; md_inst = mdha & CHA_VER_NUM_MASK; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamkeyblob.c linux-imx-phytec/drivers/crypto/caam/caamkeyblob.c --- linux-6.1.55/drivers/crypto/caam/caamkeyblob.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/caamkeyblob.c 2024-06-19 12:33:59.740217190 +0200 @@ -0,0 +1,670 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Black key generation and blob encapsulation/decapsulation for CAAM + * + * Copyright 2018-2020 NXP + */ +#include "caamkeyblob.h" +#include "error.h" + +/* Black key generation and blob encap/decap job completion handler */ +static void caam_key_blob_done(struct device *dev, u32 *desc, u32 err, + void *context) +{ + struct jr_job_result *res = context; + int ecode = 0; + + dev_dbg(dev, "%s %d: err 0x%x\n", __func__, __LINE__, err); + + if (err) + ecode = caam_jr_strstatus(dev, err); + + /* Save the error for post-processing */ + res->error = ecode; + /* Mark job as complete */ + complete(&res->completion); +} + +/** + * map_write_data - Prepare data to be written to CAAM + * + * @dev : struct device of the job ring to be used + * @data : The data to be prepared + * @size : The size of data to be prepared + * @dma_addr : The retrieve DMA address of the input data + * @allocated_data : Pointer to a DMA-able address where the input + * data is copied and synchronized + * + * Return : '0' on success, error code otherwise + */ +static int map_write_data(struct device *dev, const u8 *data, size_t size, + dma_addr_t *dma_addr, u8 **allocated_data) +{ + int ret = 0; + + /* Allocate memory for data and copy it to DMA zone */ + *allocated_data = kmemdup(data, size, GFP_KERNEL | GFP_DMA); + if (!*allocated_data) { + ret = -ENOMEM; + goto exit; + } + + *dma_addr = dma_map_single(dev, *allocated_data, size, DMA_TO_DEVICE); + if (dma_mapping_error(dev, *dma_addr)) { + dev_err(dev, "Unable to map write data\n"); + ret = -ENOMEM; + goto free_alloc; + } + + goto exit; + +free_alloc: + kfree(*allocated_data); + +exit: + return ret; +} + +/** + * map_read_data - Prepare data to be read from CAAM + * + * @dev : struct device of the job ring to be used + * @size : The size of data to be prepared + * @dma_addr : The retrieve DMA address of the data to be read + * @allocated_data : Pointer to a DMA-able address where the data + * to be read will be copied and synchronized + * + * Return : '0' on success, error code otherwise + */ +static int map_read_data(struct device *dev, size_t size, dma_addr_t *dma_addr, + u8 **allocated_data) +{ + int ret = 0; + + /* Allocate memory for data compatible with DMA */ + *allocated_data = kmalloc(size, GFP_KERNEL | GFP_DMA); + if (!*allocated_data) { + ret = -ENOMEM; + goto exit; + } + + *dma_addr = dma_map_single(dev, *allocated_data, size, DMA_FROM_DEVICE); + if (dma_mapping_error(dev, *dma_addr)) { + dev_err(dev, "Unable to map read data\n"); + ret = -ENOMEM; + goto free_alloc; + } + + goto exit; + +free_alloc: + kfree(*allocated_data); + +exit: + return ret; +} + +/** + * read_map_data - Read the data from CAAM + * + * @dev : struct device of the job ring to be used + * @data : The read data from CAAM will be copied here + * @dma_addr : The DMA address of the data to be read + * @allocated_data : Pointer to a DMA-able address where the data + * to be read is + * @size : The size of data to be read + */ +static void read_map_data(struct device *dev, u8 *data, dma_addr_t dma_addr, + u8 *allocated_data, size_t size) +{ + /* Synchronize the DMA and copy the data */ + dma_sync_single_for_cpu(dev, dma_addr, size, DMA_FROM_DEVICE); + memcpy(data, allocated_data, size); +} + +/** + * unmap_read_write_data - Unmap the data needed for or from CAAM + * + * @dev : struct device of the job ring to be used + * @dma_addr : The DMA address of the data used for DMA transfer + * @allocated_data : The data used for DMA transfer + * @size : The size of data + * @dir : The DMA_API direction + */ +static void unmap_read_write_data(struct device *dev, dma_addr_t dma_addr, + u8 *allocated_data, size_t size, + enum dma_data_direction dir) +{ + /* Free the resources and clear the data*/ + dma_unmap_single(dev, dma_addr, size, dir); + kfree_sensitive(allocated_data); +} + +/** + * get_caam_dma_addr - Get the CAAM DMA address of a physical address. + * + * @phy_address : The physical address + * + * Return : The CAAM DMA address + */ +static dma_addr_t get_caam_dma_addr(const void *phy_address) +{ + uintptr_t ptr_conv; + dma_addr_t caam_dma_address = 0; + + /* Check if conversion is possible */ + if (sizeof(caam_dma_address) < sizeof(phy_address)) { + /* + * Check that all bits sets in the phy_address + * can be stored in caam_dma_address + */ + + /* Generate a mask of the representable bits */ + u64 mask = GENMASK_ULL(sizeof(caam_dma_address) * 8 - 1, 0); + + /* + * Check that the bits not representable of + * the physical address are not set + */ + if ((uintptr_t)phy_address & ~mask) + goto exit; + } + + /* Convert address to caam_dma_address */ + ptr_conv = (uintptr_t)phy_address; + caam_dma_address = (dma_addr_t)ptr_conv; + +exit: + return caam_dma_address; +} + +/** + * generate_black_key - Generate a black key from a plaintext or random, + * based on the given input: a size for a random black + * key, or a plaintext (input key). + * + * If the memory type is Secure Memory, the key to cover is read + * directly by CAAM from Secure Memory without intermediate copy. + * The value of the input key (plaintext) must be a physical address + * in Secure Memory. + * + * Notes: + * Limited to Class 1 keys, at the present time. + * The input and output data are copied to temporary arrays + * except for the input key if the memory type is Secure Memory. + * For now, we have support for Black keys, stored in General Memory. + * + * @dev : struct device of the job ring to be used + * @info : keyblob_info structure, will be updated with + * the black key data from CAAM. + * This contains, also, all the data necessary to generate + * a black key from plaintext/random like: key encryption + * key, memory type, input key, etc. + * + * Return : '0' on success, error code otherwise + */ +int generate_black_key(struct device *dev, struct keyblob_info *info) +{ + int ret = 0; + bool not_random = false; + u8 trusted_key, key_enc; + u32 *desc = NULL; + size_t black_key_length_req = 0; + dma_addr_t black_key_dma; + u8 *tmp_black_key = NULL; + + /* Validate device */ + if (!dev) + return -EINVAL; + + /* + * If an input key (plaintext) is given, + * generate a black key from it, not from random + */ + if (info->key) + not_random = true; + + /* Get trusted key and key encryption type from type */ + trusted_key = (info->type >> TAG_OBJ_TK_OFFSET) & 0x1; + key_enc = (info->type >> TAG_OBJ_EKT_OFFSET) & 0x1; + + dev_dbg(dev, "%s input: [key: (%zu) black_key: %p(%zu), key_enc: %x]\n", + __func__, info->key_len, info->black_key, info->black_key_len, + key_enc); + if (not_random) + print_hex_dump_debug("input key @" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, info->key, + info->key_len, 1); + + /* Validate key type - only JDKEK keys are supported */ + if (!is_key_type(info->type) || is_trusted_type(info->type)) + return -EINVAL; + + /* + * Validate key size, expected values are + * between 16 and 64 bytes. + * See TODO from cnstr_desc_black_key(). + */ + if (info->key_len < MIN_KEY_SIZE || info->key_len > MAX_KEY_SIZE) + return -EINVAL; + + /* + * Based on key encryption type (ecb or ccm), + * compute the black key size + */ + if (key_enc == KEY_COVER_ECB) + /* + * ECB-Black Key will be padded with zeros to make it a + * multiple of 16 bytes long before it is encrypted, + * and the resulting Black Key will be this length. + */ + black_key_length_req = ECB_BLACK_KEY_SIZE(info->key_len); + else if (key_enc == KEY_COVER_CCM) + /* + * CCM-Black Key will always be at least 12 bytes longer, + * since the encapsulation uses a 6-byte nonce and adds + * a 6-byte ICV. But first, the key is padded as necessary so + * that CCM-Black Key is a multiple of 8 bytes long. + */ + black_key_length_req = CCM_BLACK_KEY_SIZE(info->key_len); + + /* Check if there is enough space for black key */ + if (info->black_key_len < black_key_length_req) { + info->black_key_len = black_key_length_req; + return -EINVAL; + } + + /* Black key will have at least the same length as the input key */ + info->black_key_len = info->key_len; + + dev_dbg(dev, "%s processing: [key: (%zu) black_key: %p(%zu)", + __func__, info->key_len, info->black_key, info->black_key_len); + dev_dbg(dev, "req:%zu, key_enc: 0x%x]\n", black_key_length_req, key_enc); + + /* Map black key, this will be read from CAAM */ + if (map_read_data(dev, black_key_length_req, + &black_key_dma, &tmp_black_key)) { + dev_err(dev, "Unable to map black key\n"); + ret = -ENOMEM; + goto exit; + } + + /* Construct descriptor for black key */ + if (not_random) + ret = cnstr_desc_black_key(&desc, info->key, info->key_len, + black_key_dma, info->black_key_len, + key_enc, trusted_key); + else + ret = cnstr_desc_random_black_key(&desc, info->key_len, + black_key_dma, + info->black_key_len, + key_enc, trusted_key); + + if (ret) { + dev_err(dev, + "Failed to construct the descriptor for black key\n"); + goto unmap_black_key; + } + + /* Execute descriptor and wait for its completion */ + ret = caam_jr_run_and_wait_for_completion(dev, desc, + caam_key_blob_done); + if (ret) { + dev_err(dev, "Failed to execute black key descriptor\n"); + goto free_desc; + } + + /* Read black key from CAAM */ + read_map_data(dev, info->black_key, black_key_dma, + tmp_black_key, black_key_length_req); + + /* Update black key length with the correct size */ + info->black_key_len = black_key_length_req; + +free_desc: + kfree(desc); + +unmap_black_key: + unmap_read_write_data(dev, black_key_dma, tmp_black_key, + black_key_length_req, DMA_FROM_DEVICE); + +exit: + return ret; +} +EXPORT_SYMBOL(generate_black_key); + +/** + * caam_blob_encap - Encapsulate a black key into a blob + * + * If the memory type is Secure Memory, the key to encapsulate is read + * directly by CAAM from Secure Memory without intermediate copy. + * The value of the key (black key) must be a physical address + * in Secure Memory. + * + * Notes: + * For now, we have support for Black keys, stored in General Memory and + * encapsulated into black blobs. + * + * @dev : struct device of the job ring to be used + * @info : keyblob_info structure, will be updated with + * the blob data from CAAM. + * This contains, also, all the data necessary to + * encapsulate a black key into a blob: key encryption + * key, memory type, color, etc. + * + * Return : '0' on success, error code otherwise + */ +int caam_blob_encap(struct device *dev, struct keyblob_info *info) +{ + int ret = 0; + u32 *desc = NULL; + size_t black_key_real_len = 0; + size_t blob_req_len = 0; + u8 mem_type, color, key_enc, trusted_key; + dma_addr_t black_key_dma, blob_dma; + unsigned char *blob = info->blob; + u8 *tmp_black_key = NULL, *tmp_blob = NULL; + + /* Validate device */ + if (!dev) + return -EINVAL; + + /* + * Get memory type, trusted key, key encryption + * type and color from type + */ + mem_type = (info->type >> TAG_OBJ_MEM_OFFSET) & 0x1; + color = (info->type >> TAG_OBJ_COLOR_OFFSET) & 0x1; + key_enc = (info->type >> TAG_OBJ_EKT_OFFSET) & 0x1; + trusted_key = (info->type >> TAG_OBJ_TK_OFFSET) & 0x1; + + /* Validate input data*/ + if (!info->key_mod || !blob) + return -EINVAL; + + /* Validate object type - only JDKEK keys are supported */ + if (is_trusted_type(info->type)) + return -EINVAL; + + dev_dbg(dev, "%s input:[black_key: %p (%zu) color: %x, key_enc: %x", + __func__, info->black_key, info->black_key_len, color, key_enc); + dev_dbg(dev, ", key_mod: %p (%zu)", info->key_mod, info->key_mod_len); + dev_dbg(dev, "blob: %p (%zu)]\n", blob, info->blob_len); + + /* + * Based on memory type, the key modifier length + * can be 8-byte or 16-byte. + */ + if (mem_type == DATA_SECMEM) + info->key_mod_len = KEYMOD_SIZE_SM; + else + info->key_mod_len = KEYMOD_SIZE_GM; + + /* Adapt the size of the black key */ + black_key_real_len = info->black_key_len; + + blob_req_len = CCM_BLACK_KEY_SIZE(info->key_len); + + /* Check if the blob can be stored */ + if (info->blob_len < (blob_req_len + BLOB_OVERHEAD)) + return -EINVAL; + + /* Update the blob length */ + info->blob_len = blob_req_len + BLOB_OVERHEAD; + + dev_dbg(dev, "%s processing: [black_key: %p (%zu) cnstr: %zu", + __func__, info->black_key, info->black_key_len, + black_key_real_len); + dev_dbg(dev, " color: %x key_enc: %x, mem_type: %x,", + color, key_enc, mem_type); + dev_dbg(dev, ", key_mod: %p (%zu) ", info->key_mod, info->key_mod_len); + dev_dbg(dev, "blob: %p (%zu)]\n", blob, info->blob_len); + + /* Map black key, this will be transferred to CAAM */ + if (mem_type == DATA_GENMEM) { + if (map_write_data(dev, info->black_key, info->black_key_len, + &black_key_dma, &tmp_black_key)) { + dev_err(dev, "Unable to map black key for blob\n"); + ret = -ENOMEM; + goto exit; + } + } else { + black_key_dma = get_caam_dma_addr(info->black_key); + if (!black_key_dma) + return -ENOMEM; + } + + /* Map blob, this will be read to CAAM */ + if (mem_type == DATA_GENMEM) { + if (map_read_data(dev, info->blob_len, &blob_dma, &tmp_blob)) { + dev_err(dev, "Unable to map blob\n"); + ret = -ENOMEM; + goto unmap_black_key; + } + } else { + blob_dma = get_caam_dma_addr(info->blob); + if (!blob_dma) + return -ENOMEM; + } + + /* Construct descriptor for blob encapsulation */ + ret = cnstr_desc_blob_encap(&desc, black_key_dma, info->key_len, + color, key_enc, trusted_key, mem_type, + info->key_mod, info->key_mod_len, + blob_dma, info->blob_len); + if (ret) { + dev_err(dev, + "Failed to construct the descriptor for blob encap\n"); + goto unmap_blob; + } + + /* Execute descriptor and wait for its completion */ + ret = caam_jr_run_and_wait_for_completion(dev, desc, + caam_key_blob_done); + if (ret) { + dev_err(dev, "Failed to execute blob encap descriptor\n"); + goto free_desc; + } + + /* Read blob from CAAM */ + if (mem_type == DATA_GENMEM) + read_map_data(dev, blob, blob_dma, tmp_blob, info->blob_len); + + print_hex_dump_debug("blob @" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, blob, + info->blob_len, 1); +free_desc: + kfree(desc); + +unmap_blob: + if (mem_type == DATA_GENMEM) + unmap_read_write_data(dev, blob_dma, tmp_blob, + info->blob_len, DMA_FROM_DEVICE); + +unmap_black_key: + if (mem_type == DATA_GENMEM) + unmap_read_write_data(dev, black_key_dma, tmp_black_key, + info->black_key_len, DMA_TO_DEVICE); + +exit: + return ret; +} +EXPORT_SYMBOL(caam_blob_encap); + +/** + * caam_blob_decap - Decapsulate a black key from a blob + * + * Notes: + * For now, we have support for Black blob, stored in General Memory and + * can be decapsulated into a black key. + * + * @dev : struct device of the job ring to be used + * @info : keyblob_info structure, will be updated with + * the black key decapsulated from the blob. + * This contains, also, all the data necessary to + * encapsulate a black key into a blob: key encryption + * key, memory type, color, etc. + * + * Return : '0' on success, error code otherwise + */ +int caam_blob_decap(struct device *dev, struct keyblob_info *info) +{ + int ret = 0; + u32 *desc = NULL; + u8 mem_type, color, key_enc, trusted_key; + size_t black_key_real_len; + dma_addr_t black_key_dma, blob_dma; + unsigned char *blob = info->blob + TAG_OVERHEAD_SIZE; + u8 *tmp_black_key = NULL, *tmp_blob = NULL; + + /* Validate device */ + if (!dev) + return -EINVAL; + + /* + * Get memory type, trusted key, key encryption + * type and color from type + */ + mem_type = (info->type >> TAG_OBJ_MEM_OFFSET) & 0x1; + color = (info->type >> TAG_OBJ_COLOR_OFFSET) & 0x1; + key_enc = (info->type >> TAG_OBJ_EKT_OFFSET) & 0x1; + trusted_key = (info->type >> TAG_OBJ_TK_OFFSET) & 0x1; + + /* Validate input data*/ + if (!info->key_mod || !blob) + return -EINVAL; + + dev_dbg(dev, "%s input: [blob: %p (%zu), mem_type: %x, color: %x", + __func__, blob, info->blob_len, mem_type, color); + dev_dbg(dev, " keymod: %p (%zu)", info->key_mod, info->key_mod_len); + dev_dbg(dev, " secret: %p (%zu) key_enc: %x]\n", + info->black_key, info->black_key_len, key_enc); + + /* Validate object type - only JDKEK keys are supported */ + if (is_trusted_type(info->type)) + return -EINVAL; + + print_hex_dump_debug("blob @" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, blob, + info->blob_len, 1); + + /* + * Based on memory type, the key modifier length + * can be 8-byte or 16-byte. + */ + if (mem_type == DATA_SECMEM) + info->key_mod_len = KEYMOD_SIZE_SM; + else + info->key_mod_len = KEYMOD_SIZE_GM; + + /* Check if the blob is valid */ + if (info->blob_len <= BLOB_OVERHEAD) + return -EINVAL; + + /* Initialize black key length */ + black_key_real_len = info->blob_len - BLOB_OVERHEAD; + + /* Check if the black key has enough space to be stored */ + if (info->black_key_len < black_key_real_len) + return -EINVAL; + + /* + * Based on key encryption type (ecb or ccm), + * compute the black key size + */ + if (key_enc == KEY_COVER_ECB) + /* + * ECB-Black Key will be padded with zeros to make it a + * multiple of 16 bytes long before it is encrypted, + * and the resulting Black Key will be this length. + */ + black_key_real_len = ECB_BLACK_KEY_SIZE(info->key_len); + else if (key_enc == KEY_COVER_CCM) + /* + * CCM-Black Key will always be at least 12 bytes longer, + * since the encapsulation uses a 6-byte nonce and adds + * a 6-byte ICV. But first, the key is padded as necessary so + * that CCM-Black Key is a multiple of 8 bytes long. + */ + black_key_real_len = CCM_BLACK_KEY_SIZE(info->key_len); + + /* Check if there is enough space for black key */ + if (info->black_key_len < black_key_real_len) + return -EINVAL; + + /* Update black key length with the one computed based on key_enc */ + info->black_key_len = black_key_real_len; + + dev_dbg(dev, "%s processing: [blob: %p (%zu), mem_type: %x, color: %x,", + __func__, blob, info->blob_len, mem_type, color); + dev_dbg(dev, " key_mod: %p (%zu), black_key: %p (%zu) real_len: %zu]\n", + info->key_mod, info->key_mod_len, info->black_key, + info->black_key_len, black_key_real_len); + + /* Map blob, this will be transferred to CAAM */ + if (mem_type == DATA_GENMEM) { + if (map_write_data(dev, blob, info->blob_len, + &blob_dma, &tmp_blob)) { + dev_err(dev, "Unable to map blob for decap\n"); + ret = -ENOMEM; + goto exit; + } + } else { + blob_dma = get_caam_dma_addr(blob); + if (!blob_dma) + return -ENOMEM; + } + + /* Map black key, this will be read from CAAM */ + if (mem_type == DATA_GENMEM) { + if (map_read_data(dev, info->black_key_len, + &black_key_dma, &tmp_black_key)) { + dev_err(dev, "Unable to map black key for blob decap\n"); + ret = -ENOMEM; + goto unmap_blob; + } + } else { + black_key_dma = get_caam_dma_addr(info->black_key); + if (!black_key_dma) + return -ENOMEM; + } + + ret = cnstr_desc_blob_decap(&desc, blob_dma, info->blob_len, + info->key_mod, info->key_mod_len, + black_key_dma, info->key_len, + color, key_enc, trusted_key, mem_type); + if (ret) { + dev_err(dev, + "Failed to construct the descriptor for blob decap\n"); + goto unmap_black_key; + } + + ret = caam_jr_run_and_wait_for_completion(dev, desc, + caam_key_blob_done); + if (ret) { + dev_err(dev, "Failed to execute blob decap descriptor\n"); + goto free_desc; + } + + /* Read black key from CAAM */ + if (mem_type == DATA_GENMEM) + read_map_data(dev, info->black_key, black_key_dma, + tmp_black_key, info->black_key_len); + +free_desc: + kfree(desc); + +unmap_black_key: + if (mem_type == DATA_GENMEM) + unmap_read_write_data(dev, black_key_dma, tmp_black_key, + info->black_key_len, DMA_FROM_DEVICE); + +unmap_blob: + if (mem_type == DATA_GENMEM) + unmap_read_write_data(dev, blob_dma, tmp_blob, + info->blob_len, DMA_TO_DEVICE); + +exit: + return ret; +} +EXPORT_SYMBOL(caam_blob_decap); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamkeyblob_desc.c linux-imx-phytec/drivers/crypto/caam/caamkeyblob_desc.c --- linux-6.1.55/drivers/crypto/caam/caamkeyblob_desc.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/caamkeyblob_desc.c 2024-06-19 12:33:59.740217190 +0200 @@ -0,0 +1,446 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Shared descriptors for CAAM black key + * and blob encapsulation/decapsulation + * + * Copyright 2018-2020 NXP + */ +#include "caamkeyblob_desc.h" + +/* Size of tmp buffer for descriptor const. */ +#define INITIAL_DESCSZ 64 + +/* + * Construct a black key conversion job descriptor + * + * This function constructs a job descriptor capable of performing + * a key blackening operation on a plaintext secure memory resident object. + * + * @desc : Pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * @key : Pointer to the plaintext, which will also hold + * the result. Since encryption occurs in place, caller must + * ensure that the space is large enough to accommodate the + * blackened key + * @key_len : Size of the plaintext + * @black_key : DMA address of the black key obtained from hardware + * @black_key_len : Size of the black key + * @key_enc : Encrypted Key Type (AES-ECB or AES-CCM) + * @trusted_key : Trusted Key (use Job Descriptor Key Encryption Key (JDKEK) + * or Trusted Descriptor Key Encryption Key (TDKEK) to + * decrypt the key to be loaded into a Key Register). + * + * Return : '0' on success, error code otherwise + */ +int cnstr_desc_black_key(u32 **desc, char *key, size_t key_len, + dma_addr_t black_key, size_t black_key_len, + u8 key_enc, u8 trusted_key) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize; + u32 bk_store; + u32 key_length_for_desc = key_len; + + /* Trusted key not supported */ + if (trusted_key != UNTRUSTED_KEY) + return -EOPNOTSUPP; + + memset(tmpdesc, 0, sizeof(tmpdesc)); + + init_job_desc(tmpdesc, 0); + + /* + * KEY commands seems limited to 32 bytes, so we should use the load + * command instead which can load up to 64 bytes. + * The size must also be loaded. + * + * TODO: The KEY command indicate it should be able to load key bigger + * than 32bytes but it doesn't work in practice + * + * TODO: The LOAD command indicate it should be able to load up to 96 + * byte keys it doesn't work in practice and is limited to 64 bytes + */ + + /* Load key to class 1 key register */ + append_load_as_imm(tmpdesc, (void *)key, key_length_for_desc, + LDST_CLASS_1_CCB | LDST_SRCDST_BYTE_KEY); + + /* Load the size of the key */ + append_load_imm_u32(tmpdesc, key_length_for_desc, LDST_CLASS_1_CCB | + LDST_IMM | LDST_SRCDST_WORD_KEYSZ_REG); + + /* ...and write back out via FIFO store*/ + bk_store = CLASS_1; + if (key_enc == KEY_COVER_ECB) + bk_store |= FIFOST_TYPE_KEY_KEK; + else + bk_store |= FIFOST_TYPE_KEY_CCM_JKEK; + + /* Save the key as black key in memory */ + append_fifo_store(tmpdesc, black_key, black_key_len, bk_store); + + dsize = desc_bytes(&tmpdesc); + + /* Now allocate execution buffer and coat it with executable */ + tdesc = kmemdup(tmpdesc, dsize, GFP_KERNEL | GFP_DMA); + if (!tdesc) + return -ENOMEM; + + *desc = tdesc; + + print_hex_dump_debug("black key desc@" __stringify(__LINE__) ":", + DUMP_PREFIX_ADDRESS, 16, 4, *desc, + desc_bytes(*desc), 1); + + return 0; +} +EXPORT_SYMBOL(cnstr_desc_black_key); + +/* + * Construct a black key using RNG job descriptor + * + * This function constructs a job descriptor capable of performing + * a key blackening operation on RNG generated. + * + * @desc : Pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * @key_len : Size of the random plaintext + * @black_key : DMA address of the black key obtained from hardware + * @black_key_len : Size of the black key + * @key_enc : Encrypted Key Type (AES-ECB or AES-CCM) + * @trusted_key : Trusted Key (use Job Descriptor Key Encryption Key (JDKEK) + * or Trusted Descriptor Key Encryption Key (TDKEK) to + * decrypt the key to be loaded into a Key Register). + * + * Return : '0' on success, error code otherwise + */ +int cnstr_desc_random_black_key(u32 **desc, size_t key_len, + dma_addr_t black_key, size_t black_key_len, + u8 key_enc, u8 trusted_key) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize; + u32 bk_store; + + memset(tmpdesc, 0, sizeof(tmpdesc)); + + init_job_desc(tmpdesc, 0); + + /* Prepare RNG */ + append_operation(tmpdesc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG); + + /* Generate RNG and left it in output data fifo */ + append_cmd(tmpdesc, CMD_FIFO_STORE | FIFOST_TYPE_RNGFIFO | key_len); + + /* Copy RNG from outfifo to class 1 Key register */ + append_move(tmpdesc, MOVE_SRC_OUTFIFO | MOVE_DEST_CLASS1KEY | + MOVE_WAITCOMP | (key_len & MOVE_LEN_MASK)); + + /* Write the size of the key moved */ + append_load_imm_u32(tmpdesc, key_len, LDST_CLASS_1_CCB | + LDST_SRCDST_WORD_KEYSZ_REG | LDST_IMM); + + bk_store = CLASS_1; + if (key_enc == KEY_COVER_ECB) + bk_store |= FIFOST_TYPE_KEY_KEK; + else + bk_store |= FIFOST_TYPE_KEY_CCM_JKEK; + + /* Fifo store to save the key as black key in memory */ + append_fifo_store(tmpdesc, black_key, black_key_len, bk_store); + + dsize = desc_bytes(&tmpdesc); + + /* Now allocate execution buffer and coat it with executable */ + tdesc = kmemdup(tmpdesc, dsize, GFP_KERNEL | GFP_DMA); + if (!tdesc) + return -ENOMEM; + + *desc = tdesc; + + print_hex_dump_debug("black key random desc@" __stringify(__LINE__) ":", + DUMP_PREFIX_ADDRESS, 16, 4, *desc, + desc_bytes(*desc), 1); + + return 0; +} +EXPORT_SYMBOL(cnstr_desc_random_black_key); + +/* + * Construct a blob encapsulation job descriptor + * + * This function dynamically constructs a blob encapsulation job descriptor + * from the following arguments: + * + * @desc : Pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * @black_key : Physical pointer to a secret, normally a black or red key, + * possibly residing within an accessible secure memory page, + * of the secret to be encapsulated to an output blob. + * @black_key_len : Size of input secret, in bytes. This is limited to 65536 + * less the size of blob overhead, since the length embeds + * into DECO pointer in/out instructions. + * @keycolor : Determines if the source data is covered (black key) or + * plaintext (red key). RED_KEY or BLACK_KEY are defined in + * for this purpose. + * @key_enc : If BLACK_KEY source is covered via AES-CCM, specify + * KEY_COVER_CCM, else uses AES-ECB (KEY_COVER_ECB). + * @trusted_key : Trusted Key (use Job Descriptor Key Encryption Key (JDKEK) + * or Trusted Descriptor Key Encryption Key (TDKEK) to + * decrypt the key to be loaded into a Key Register). + * @mem_type : Determine if encapsulated blob should be a secure memory + * blob (DATA_SECMEM), with partition data embedded with key + * material, or a general memory blob (DATA_GENMEM). + * @key_mod : Pointer to a key modifier, which must reside in a + * contiguous piece of memory. Modifier will be assumed to be + * 8 bytes long for a blob of type DATA_SECMEM, or 16 bytes + * long for a blob of type DATA_GENMEM + * @key_mod_len : Modifier length is 8 bytes long for a blob of type + * DATA_SECMEM, or 16 bytes long for a blob of type DATA_GENMEM + * @blob : Physical pointer to the destination buffer to receive the + * encapsulated output. This buffer will need to be 48 bytes + * larger than the input because of the added encapsulation + * data. The generated descriptor will account for the + * increase in size, but the caller must also account for + * this increase in the buffer allocator. + * @blob_len : Size of the destination buffer to receive the + * encapsulated output. + * Return : '0' on success, error code otherwise + * + * Upon completion, desc points to a buffer containing a CAAM job + * descriptor which encapsulates data into an externally-storable blob + * suitable for use across power cycles. + * + * This is an example of a black key encapsulation job into a general memory + * blob. Notice the 16-byte key modifier in the LOAD instruction. Also note + * the output 48 bytes longer than the input: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400010 ld: ccb2-key len=16 offs=0 + * [02] 08144891 ptr->@0x08144891 + * [03] F800003A seqoutptr: len=58 + * [04] 01000000 out_ptr->@0x01000000 + * [05] F000000A seqinptr: len=10 + * [06] 09745090 in_ptr->@0x09745090 + * [07] 870D0004 operation: encap blob reg=memory, black, format=normal + * + * This is an example of a red key encapsulation job for storing a red key + * into a secure memory blob. Note the 8 byte modifier on the 12 byte offset + * in the LOAD instruction; this accounts for blob permission storage: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400C08 ld: ccb2-key len=8 offs=12 + * [02] 087D0784 ptr->@0x087d0784 + * [03] F8000050 seqoutptr: len=80 + * [04] 09251BB2 out_ptr->@0x09251bb2 + * [05] F0000020 seqinptr: len=32 + * [06] 40000F31 in_ptr->@0x40000f31 + * [07] 870D0008 operation: encap blob reg=memory, red, sec_mem, + * format=normal + */ +int cnstr_desc_blob_encap(u32 **desc, dma_addr_t black_key, + size_t key_len, u8 keycolor, u8 key_enc, + u8 trusted_key, u8 mem_type, const void *key_mod, + size_t key_mod_len, dma_addr_t blob, size_t blob_len) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize; + u32 bk_store; + + /* Trusted key not supported */ + if (trusted_key != UNTRUSTED_KEY) + return -EOPNOTSUPP; + + memset(tmpdesc, 0, sizeof(tmpdesc)); + + init_job_desc(tmpdesc, 0); + + /* + * Key modifier works differently for secure/general memory blobs + * This accounts for the permission/protection data encapsulated + * within the blob if a secure memory blob is requested + */ + if (mem_type == DATA_SECMEM) + append_load_as_imm(tmpdesc, key_mod, key_mod_len, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY | + ((12 << LDST_OFFSET_SHIFT) & + LDST_OFFSET_MASK)); + else /* is general memory blob */ + append_load_as_imm(tmpdesc, key_mod, key_mod_len, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); + + /* Input data, should be somewhere in secure memory */ + append_seq_in_ptr_intlen(tmpdesc, black_key, key_len, 0); + + /* + * Encapsulation output must include space for blob key encryption + * key and MAC tag + */ + append_seq_out_ptr_intlen(tmpdesc, blob, CCM_BLACK_KEY_SIZE(key_len) + + BLOB_OVERHEAD, 0); + + bk_store = OP_PCLID_BLOB; + if (mem_type == DATA_SECMEM) + bk_store |= OP_PCL_BLOB_PTXT_SECMEM; + + if (key_enc == KEY_COVER_CCM) + bk_store |= OP_PCL_BLOB_EKT; + + /* An input black key cannot be stored in a red blob */ + if (keycolor == BLACK_KEY) + bk_store |= OP_PCL_BLOB_BLACK; + + /* Set blob encap, then color */ + append_operation(tmpdesc, OP_TYPE_ENCAP_PROTOCOL | bk_store); + + dsize = desc_bytes(&tmpdesc); + + tdesc = kmemdup(tmpdesc, dsize, GFP_KERNEL | GFP_DMA); + if (!tdesc) + return -ENOMEM; + + *desc = tdesc; + + print_hex_dump_debug("blob encap desc@" __stringify(__LINE__) ":", + DUMP_PREFIX_ADDRESS, 16, 4, *desc, + desc_bytes(*desc), 1); + return 0; +} +EXPORT_SYMBOL(cnstr_desc_blob_encap); + +/* + * Construct a blob decapsulation job descriptor + * + * This function dynamically constructs a blob decapsulation job descriptor + * from the following arguments: + * + * @desc : Pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * @blob : Physical pointer (into external memory) of the blob to + * be decapsulated. Blob must reside in a contiguous memory + * segment. + * @blob_len : Size of the blob buffer to be decapsulated. + * @key_mod : Pointer to a key modifier, which must reside in a + * contiguous piece of memory. Modifier will be assumed to be + * 8 bytes long for a blob of type DATA_SECMEM, or 16 bytes + * long for a blob of type DATA_GENMEM + * @key_mod_len : Modifier length is 8 bytes long for a blob of type + * DATA_SECMEM, or 16 bytes long for a blob of type DATA_GENMEM + * @black_key : Physical pointer of the decapsulated output, possibly into + * a location within a secure memory page. Must be contiguous. + * @black_key_len : Size of encapsulated secret in bytes (not the size of the + * input blob). + * @keycolor : Determines if the source data is covered (black key) or + * plaintext (red key). RED_KEY or BLACK_KEY are defined in + * for this purpose. + * @key_enc : If BLACK_KEY source is covered via AES-CCM, specify + * KEY_COVER_CCM, else uses AES-ECB (KEY_COVER_ECB). + * @trusted_key : Trusted Key (use Job Descriptor Key Encryption Key (JDKEK) + * or Trusted Descriptor Key Encryption Key (TDKEK) to + * decrypt the key to be loaded into a Key Register). + * @mem_type : Determine if encapsulated blob should be a secure memory + * blob (DATA_SECMEM), with partition data embedded with key + * material, or a general memory blob (DATA_GENMEM). + * Return : '0' on success, error code otherwise + * + * Upon completion, desc points to a buffer containing a CAAM job descriptor + * that decapsulates a key blob from external memory into a black (encrypted) + * key or red (plaintext) content. + * + * This is an example of a black key decapsulation job from a general memory + * blob. Notice the 16-byte key modifier in the LOAD instruction. + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400010 ld: ccb2-key len=16 offs=0 + * [02] 08A63B7F ptr->@0x08a63b7f + * [03] F8000010 seqoutptr: len=16 + * [04] 01000000 out_ptr->@0x01000000 + * [05] F000003A seqinptr: len=58 + * [06] 01000010 in_ptr->@0x01000010 + * [07] 860D0004 operation: decap blob reg=memory, black, format=normal + * + * This is an example of a red key decapsulation job for restoring a red key + * from a secure memory blob. Note the 8 byte modifier on the 12 byte offset + * in the LOAD instruction: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400C08 ld: ccb2-key len=8 offs=12 + * [02] 01000000 ptr->@0x01000000 + * [03] F8000020 seqoutptr: len=32 + * [04] 400000E6 out_ptr->@0x400000e6 + * [05] F0000050 seqinptr: len=80 + * [06] 08F0C0EA in_ptr->@0x08f0c0ea + * [07] 860D0008 operation: decap blob reg=memory, red, sec_mem, + * format=normal + */ +int cnstr_desc_blob_decap(u32 **desc, dma_addr_t blob, size_t blob_len, + const void *key_mod, size_t key_mod_len, + dma_addr_t black_key, size_t plaintext_len, + u8 keycolor, u8 key_enc, u8 trusted_key, u8 mem_type) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize; + u32 bk_store; + + /* Trusted key not supported */ + if (trusted_key != UNTRUSTED_KEY) + return -EOPNOTSUPP; + + memset(tmpdesc, 0, sizeof(tmpdesc)); + + init_job_desc(tmpdesc, 0); + + /* Load key modifier */ + if (mem_type == DATA_SECMEM) + append_load_as_imm(tmpdesc, key_mod, key_mod_len, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY | + ((12 << LDST_OFFSET_SHIFT) & + LDST_OFFSET_MASK)); + else /* is general memory blob */ + append_load_as_imm(tmpdesc, key_mod, key_mod_len, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); + + /* Compensate blob header + MAC tag over size of encapsulated secret */ + append_seq_in_ptr_intlen(tmpdesc, blob, plaintext_len + BLOB_OVERHEAD, + 0); + + append_seq_out_ptr_intlen(tmpdesc, black_key, plaintext_len, 0); + + /* Decapsulate from secure memory partition to black blob */ + bk_store = OP_PCLID_BLOB; + if (mem_type == DATA_SECMEM) + bk_store |= OP_PCL_BLOB_PTXT_SECMEM; + + if (key_enc == KEY_COVER_CCM) + bk_store |= OP_PCL_BLOB_EKT; + + /* An input black key cannot be stored in a red blob */ + if (keycolor == BLACK_KEY) + bk_store |= OP_PCL_BLOB_BLACK; + + /* Set blob encap, then color */ + append_operation(tmpdesc, OP_TYPE_DECAP_PROTOCOL | bk_store); + + dsize = desc_bytes(&tmpdesc); + + tdesc = kmemdup(tmpdesc, dsize, GFP_KERNEL | GFP_DMA); + if (!tdesc) + return -ENOMEM; + + *desc = tdesc; + + print_hex_dump_debug("blob decap desc@" __stringify(__LINE__) ":", + DUMP_PREFIX_ADDRESS, 16, 4, *desc, + desc_bytes(*desc), 1); + + return 0; +} +EXPORT_SYMBOL(cnstr_desc_blob_decap); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("NXP CAAM Black Key and Blob descriptors"); +MODULE_AUTHOR("NXP Semiconductors"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamkeyblob_desc.h linux-imx-phytec/drivers/crypto/caam/caamkeyblob_desc.h --- linux-6.1.55/drivers/crypto/caam/caamkeyblob_desc.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/caamkeyblob_desc.h 2024-06-19 12:33:59.740217190 +0200 @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Shared descriptors for CAAM black key and blob + * + * Copyright 2018-2020 NXP + */ + +#ifndef _CAAMKEYBLOB_DESC_H_ +#define _CAAMKEYBLOB_DESC_H_ + +#include + +#include "jr.h" +#include "regs.h" +#include "desc.h" + +#include "compat.h" +#include "tag_object.h" +#include "desc_constr.h" + +/* Defines for secure memory and general memory blobs */ +#define DATA_GENMEM 0 +#define DATA_SECMEM 1 + +/* Encrypted key */ +#define BLACK_KEY 1 + +/* Define key encryption/covering options */ +#define KEY_COVER_ECB 0 /* cover key in AES-ECB */ +#define KEY_COVER_CCM 1 /* cover key with AES-CCM */ + +/* Define the trust in the key, to select either JDKEK or TDKEK */ +#define UNTRUSTED_KEY 0 +#define TRUSTED_KEY 1 + +/* Define space required for BKEK + MAC tag storage in any blob */ +#define BLOB_OVERHEAD (32 + 16) + +#define PAD_16_BYTE(_key_size) (roundup(_key_size, 16)) +#define PAD_8_BYTE(_key_size) (roundup(_key_size, 8)) + +/* + * ECB-Black Key will be padded with zeros to make it a + * multiple of 16 bytes long before it is encrypted, + * and the resulting Black Key will be this length. + */ +#define ECB_BLACK_KEY_SIZE(_key_size) (PAD_16_BYTE(_key_size)) + +/* + * CCM-Black Key will always be at least 12 bytes longer, + * since the encapsulation uses a 6-byte nonce and adds + * a 6-byte ICV. But first, the key is padded as necessary so + * that CCM-Black Key is a multiple of 8 bytes long. + */ +#define NONCE_SIZE 6 +#define ICV_SIZE 6 +#define CCM_OVERHEAD (NONCE_SIZE + ICV_SIZE) +#define CCM_BLACK_KEY_SIZE(_key_size) (PAD_8_BYTE(_key_size) \ + + CCM_OVERHEAD) + +static inline int secret_size_in_ccm_black_key(int key_size) +{ + return ((key_size >= CCM_OVERHEAD) ? key_size - CCM_OVERHEAD : 0); +} + +#define SECRET_SIZE_IN_CCM_BLACK_KEY(_key_size) \ + secret_size_in_ccm_black_key(_key_size) + +/* A red key is not encrypted so its size is the same */ +#define RED_KEY_SIZE(_key_size) (_key_size) + +/* + * Based on memory type, the key modifier length + * can be either 8-byte or 16-byte. + */ +#define KEYMOD_SIZE_SM 8 +#define KEYMOD_SIZE_GM 16 + +/* Create job descriptor to cover key */ +int cnstr_desc_black_key(u32 **desc, char *key, size_t key_len, + dma_addr_t black_key, size_t black_key_len, + u8 key_enc, u8 trusted_key); + +/* Create job descriptor to generate a random key and cover it */ +int cnstr_desc_random_black_key(u32 **desc, size_t key_len, + dma_addr_t black_key, size_t black_key_len, + u8 key_enc, u8 trusted_key); + +/* Encapsulate data in a blob */ +int cnstr_desc_blob_encap(u32 **desc, dma_addr_t black_key, + size_t black_key_len, u8 color, u8 key_enc, + u8 trusted_key, u8 mem_type, const void *key_mod, + size_t key_mod_len, dma_addr_t blob, size_t blob_len); + +/* Decapsulate data from a blob */ +int cnstr_desc_blob_decap(u32 **desc, dma_addr_t blob, size_t blob_len, + const void *key_mod, size_t key_mod_len, + dma_addr_t black_key, size_t black_key_len, + u8 keycolor, u8 key_enc, u8 trusted_key, u8 mem_type); + +#endif /* _CAAMKEYBLOB_DESC_H_ */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamkeyblob.h linux-imx-phytec/drivers/crypto/caam/caamkeyblob.h --- linux-6.1.55/drivers/crypto/caam/caamkeyblob.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/caamkeyblob.h 2024-06-19 12:33:59.740217190 +0200 @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Black key generation and blob encapsulation/decapsualtion for CAAM + * + * Copyright 2018-2020 NXP + */ + +#ifndef _CAAMKEYBLOB_H_ +#define _CAAMKEYBLOB_H_ + +#include +#include "caamkeyblob_desc.h" + +/* + * Minimum key size to be used is 16 bytes and maximum key size fixed + * is 64 bytes. + * Blob size to be kept is Maximum key size + tag object header added by CAAM. + */ + +#define MIN_KEY_SIZE 16 +#define MAX_KEY_SIZE 64 + +#define MAX_BLACK_KEY_SIZE (MAX_KEY_SIZE + CCM_OVERHEAD +\ + TAG_OVERHEAD_SIZE) + +/* + * For blobs a randomly-generated, 256-bit blob key is used to + * encrypt the data using the AES-CCM cryptographic algorithm. + * Therefore, blob size is max key size, CCM_OVERHEAD, blob header + * added by CAAM and the tagged object header size. + */ +#define MAX_BLOB_SIZE (MAX_KEY_SIZE + CCM_OVERHEAD +\ + BLOB_OVERHEAD + TAG_OVERHEAD_SIZE) + +/* Key modifier for CAAM blobs, used as a revision number */ +static const char caam_key_modifier[KEYMOD_SIZE_GM] = { + 'C', 'A', 'A', 'M', '_', 'K', 'E', 'Y', + '_', 'T', 'Y', 'P', 'E', '_', 'V', '1', +}; + +/** + * struct keyblob_info - Structure that contains all the data necessary + * to generate a black key and encapsulate it into a blob + * + * @key : The plaintext used as input key + * for black key generation + * @key_len : Size of plaintext or size of key in case of + * black key generated from random + * @type : The type of data contained (e.g. black key, blob, etc.) + * @black_key_len : Length of the generated black key + * @black_key : Black key data obtained from CAAM + * @blob_len : Length of the blob that encapsulates the black key + * @blob : Blob data obtained from CAAM + * @key_modifier_len : 8-byte or 16-byte Key_Modifier based on general or + * secure memory blob type + * @key_modifier : can be either a secret value, or used as a revision + * number, revision date or nonce + * In this case is used as a revision number. + */ +struct keyblob_info { + char *key; + size_t key_len; + + u32 type; + + size_t black_key_len; + unsigned char black_key[MAX_BLACK_KEY_SIZE]; + + size_t blob_len; + unsigned char blob[MAX_BLOB_SIZE]; + + size_t key_mod_len; + const void *key_mod; +}; + +int generate_black_key(struct device *dev, struct keyblob_info *info); + +int caam_blob_encap(struct device *dev, struct keyblob_info *info); + +int caam_blob_decap(struct device *dev, struct keyblob_info *info); + +#endif /* _CAAMKEYBLOB_H_ */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamkeyblob_test.c linux-imx-phytec/drivers/crypto/caam/caamkeyblob_test.c --- linux-6.1.55/drivers/crypto/caam/caamkeyblob_test.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/caamkeyblob_test.c 2024-06-19 12:33:59.740217190 +0200 @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2018-2020 NXP + * + * Test of black key generation from a plaintext (of different size) + * and from random. + * The random black key is encapsulated into a blob. + * Next, the blob is decapsulated and the new obtained black key is + * compared to the random black key. + */ +#include +#include "caamkeyblob.h" + +#define MAX_INPUT_SIZE 64 +#define KEY_ENCRYPTION_ECB 1 +#define KEY_ENCRYPTION_CCM 9 + +static char input[MAX_INPUT_SIZE]; + +static int create_black_key(struct device *dev, struct keyblob_info *info) +{ + int ret; + + ret = generate_black_key(dev, info); + if (ret) + dev_err(dev, "black key of size: %zd, type: %d returned %d", + info->key_len, info->type, ret); + + return (ret) ? 1 : 0; +} + +static int black_key_test(void) +{ + struct device *dev; + struct keyblob_info *info; + int i, ret = 0, nb_errors = 0; + unsigned char tmp_black_key[MAX_BLACK_KEY_SIZE]; + size_t tmp_black_key_len = 0; + + dev = caam_jr_alloc(); + if (!dev) + return -ENOMEM; + + info = kmalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->key = input; + + for (i = 1; i <= MAX_INPUT_SIZE; i++) { + info->key_len = i; + + /* Create a black key encrypted with AES-ECB */ + info->type = KEY_ENCRYPTION_ECB; + info->black_key_len = MAX_INPUT_SIZE; + nb_errors += create_black_key(dev, info); + + /* Create a black key encrypted with AES-CCM */ + info->type = KEY_ENCRYPTION_CCM; + info->black_key_len = MAX_INPUT_SIZE + CCM_OVERHEAD; + nb_errors += create_black_key(dev, info); + } + + /* Create, from random, a black key encrypted with AES-ECB */ + info->key = NULL; + info->type = KEY_ENCRYPTION_ECB; + info->black_key_len = MAX_INPUT_SIZE; + ret = create_black_key(dev, info); + nb_errors += (ret) ? 1 : 0; + + /* Save it for later to compare it */ + tmp_black_key_len = info->black_key_len; + memcpy(tmp_black_key, info->black_key, tmp_black_key_len); + + /* Encapsulate the random black key into a black blob */ + info->key = NULL; + /* Set key modifier, used as revision number, for blob */ + info->key_mod = caam_key_modifier; + info->key_mod_len = ARRAY_SIZE(caam_key_modifier); + /* Black key, encrypted with ECB-AES, in General Memory */ + info->type = KEY_ENCRYPTION_ECB; + info->key_len = MAX_INPUT_SIZE; + info->blob_len = MAX_BLOB_SIZE; + ret = caam_blob_encap(dev, info); + nb_errors += (ret) ? 1 : 0; + + /* Decapsulate the black key from the above black blob */ + ret = caam_blob_decap(dev, info); + nb_errors += (ret) ? 1 : 0; + + /* + * Compare the generated black key with + * the one decapsulated from the blob + */ + if (info->black_key_len == tmp_black_key_len) + ret = memcmp(tmp_black_key, info->black_key, tmp_black_key_len); + else + ret = 1; + nb_errors += ret; + + /* + * Check number of errors. + * If nb_errors > 0, at least one operation failed, success otherwise + */ + pr_info("Nb errors: %d\n", nb_errors); + + caam_jr_free(dev); + kfree(info); + + return nb_errors; +} + +static int black_key_test_init(void) +{ + return black_key_test(); +} + +static void black_key_test_exit(void) +{ +} + +module_init(black_key_test_init); +module_exit(black_key_test_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("NXP CAAM Black Key and Blob Test"); +MODULE_AUTHOR("NXP Semiconductors"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamkeygen.c linux-imx-phytec/drivers/crypto/caam/caamkeygen.c --- linux-6.1.55/drivers/crypto/caam/caamkeygen.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/caamkeygen.c 2024-06-19 12:33:59.740217190 +0200 @@ -0,0 +1,630 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2020, 2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "caamkeyblob.h" +#include "intern.h" +#include + +#define DEVICE_NAME "caam-keygen" + +static long caam_keygen_ioctl(struct file *file, unsigned int cmd, + unsigned long arg); + +/** + * tag_black_obj - Tag a black object (key/blob) with a tag object header. + * + * @info : keyblob_info structure, which contains + * the black key/blob, obtained from CAAM, + * that needs to be tagged + * @black_max_len : The maximum size of the black object (blob/key) + * @blob : Used to determine if it's a blob or key object + * + * Return : '0' on success, error code otherwise + */ +static int tag_black_obj(struct keyblob_info *info, size_t black_max_len, + bool blob) +{ + struct header_conf tag; + u32 type; + int ret; + u32 size_tagged = black_max_len; + + if (!info) + return -EINVAL; + + type = info->type; + + /* Prepare and set the tag */ + if (blob) { + init_tag_object_header(&tag, 0, type, info->key_len, + info->blob_len); + ret = set_tag_object_header_conf(&tag, info->blob, + info->blob_len, + &size_tagged); + } else { + init_tag_object_header(&tag, 0, type, info->key_len, + info->black_key_len); + ret = set_tag_object_header_conf(&tag, info->black_key, + info->black_key_len, + &size_tagged); + } + if (ret) + return ret; + + /* Update the size of the black key tagged */ + if (blob) + info->blob_len = size_tagged; + else + info->black_key_len = size_tagged; + + return ret; +} + +/** + * send_err_msg - Send the error message from kernel to user-space + * + * @msg : The message to be sent + * @output : The output buffer where we want to copy the error msg + * @size : The size of output buffer + */ +static void send_err_msg(char *msg, void __user *output, size_t size) +{ + size_t min_s; + char null_ch = 0; + + /* Not enough space to copy any message */ + if (size <= 1) + return; + + min_s = min(size - 1, strlen(msg)); + /* + * Avoid compile and checkpatch warnings, since we don't + * care about return value from copy_to_user + */ + (void)(copy_to_user(output, msg, min_s) + 1); + /* Copy null terminator */ + (void)(copy_to_user((output + min_s), &null_ch, 1) + 1); +} + +/** + * validate_key_size - Validate the key size from user. + * This can be the exact size given by user when + * generating a black key from random (with -s), + * or the size of the plaintext (with -t). + * + * @key_len : The size of key we want to validate + * @output : The output buffer where we want to copy the error msg + * @size : The size of output buffer + * + *Return : '0' on success, error code otherwise + */ +static int validate_key_size(size_t key_len, void __user *output, size_t size) +{ + char *msg = NULL; + + if (key_len < MIN_KEY_SIZE || key_len > MAX_KEY_SIZE) { + msg = "Invalid key size, expected values are between 16 and 64 bytes.\n"; + send_err_msg(msg, output, size); + return -EINVAL; + } + + return 0; +} + +/** + * validate_input - Validate the input from user and set the + * keyblob_info structure. + * This contains the input key in case of black key + * generated from plaintext or size for random + * black key. + * + * @key_crt : Structure with data from user + * @arg : User-space argument from ioctl call + * @info : keyblob_info structure, will be updated with all the + * data from user-space + * @create_key_op : Used to determine if it's a create or import operation + * + * Return : '0' on success, error code otherwise + */ +static int validate_input(struct caam_keygen_cmd *key_crt, unsigned long arg, + struct keyblob_info *info, bool create_key_op) +{ + char *tmp, *msg; + size_t tmp_size; + bool random = false; + int ret = 0; + u32 tmp_len = 0; + char null_ch = 0; + + /* + * So far, we only support Black keys, encrypted with JDKEK, + * kept in general memory, non-secure state. + * Therefore, default value for type is 1. + */ + u32 type = 1; + + if (copy_from_user(key_crt, (void __user *)arg, + sizeof(struct caam_keygen_cmd))) + return -EFAULT; + + /* Get blob_len from user. */ + info->blob_len = key_crt->blob_len; + /* Get black_key_len from user. */ + info->black_key_len = key_crt->black_key_len; + + /* + * Based on operation type validate a different set of input data. + * + * For key creation, validate the Encrypted Key Type, + * the Key Mode and Key Value + */ + if (create_key_op) { + /* + * Validate arguments received from user. + * These must be at least 1 since + * they have null terminator. + */ + if (key_crt->key_enc_len < 1 || key_crt->key_mode_len < 1 || + key_crt->key_value_len < 1) { + msg = "Invalid arguments.\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + return -EFAULT; + } + /* + * Allocate memory for temporary buffer used to + * get the user arguments from user-space + */ + tmp_size = max_t(size_t, key_crt->key_enc_len, + max_t(size_t, key_crt->key_mode_len, + key_crt->key_value_len)) + 1; + tmp = kmalloc(tmp_size, GFP_KERNEL); + if (!tmp) { + msg = "Unable to allocate memory for temporary buffer.\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + return -ENOMEM; + } + /* Add null terminator */ + tmp[tmp_size - 1] = null_ch; + /* + * Validate and set, in type, the Encrypted Key Type + * given from user-space. + * This must be ecb or ccm. + */ + if (copy_from_user(tmp, u64_to_user_ptr(key_crt->key_enc), + key_crt->key_enc_len)) { + msg = "Unable to copy from user the Encrypted Key Type.\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + ret = -EFAULT; + goto free_resource; + } + if (!strcmp(tmp, "ccm")) { + type |= BIT(TAG_OBJ_EKT_OFFSET); + } else if (strcmp(tmp, "ecb")) { + msg = "Invalid argument for Encrypted Key Type, expected ecb or ccm.\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + ret = -EINVAL; + goto free_resource; + } + /* + * Validate the Key Mode given from user-space. + * This must be -t (text), for a black key generated + * from a plaintext, or -s (size) for a black key + * generated from random. + */ + if (copy_from_user(tmp, u64_to_user_ptr(key_crt->key_mode), + key_crt->key_mode_len)) { + msg = "Unable to copy from user the Key Mode: random (-s) or plaintext (-t).\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + ret = -EFAULT; + goto free_resource; + } + if (!strcmp(tmp, "-s")) { + random = true; /* black key generated from random */ + } else if (strcmp(tmp, "-t")) { + msg = "Invalid argument for Key Mode, expected -s or -t.\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + ret = -EINVAL; + goto free_resource; + } + /* + * Validate and set, into keyblob_info structure, + * the plaintext or key size, based on Key Mode. + */ + if (copy_from_user(tmp, u64_to_user_ptr(key_crt->key_value), + key_crt->key_value_len)) { + msg = "Unable to copy from user the Key Value: size or plaintext.\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + ret = -EFAULT; + goto free_resource; + } + /* Black key generated from random, get its size */ + if (random) { + info->key = NULL; + ret = kstrtou32(tmp, 10, &tmp_len); + if (ret != 0) { + msg = "Invalid key size.\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + goto free_resource; + } + ret = validate_key_size(tmp_len, + u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + if (ret) + goto free_resource; + + info->key_len = tmp_len; + } else { + /* + * Black key generated from plaintext, + * get the plaintext (input key) and its size + */ + ret = validate_key_size(key_crt->key_value_len, + u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + if (ret) + goto free_resource; + + info->key = tmp; + info->key_len = key_crt->key_value_len; + } + info->type = type; + } else { + /* For key import, get the blob from user-space */ + if (copy_from_user(info->blob, u64_to_user_ptr(key_crt->blob), + info->blob_len)) { + msg = "Unable to copy from user the blob.\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->black_key), + key_crt->black_key_len); + return -EFAULT; + } + } + + goto exit; + +free_resource: + kfree(tmp); + +exit: + return ret; +} + +/** + * keygen_create_keyblob - Generate key and blob + * + * @info : keyblob_info structure, will be updated with + * the black key and blob data from CAAM + * + * Return : '0' on success, error code otherwise + */ +static int keygen_create_keyblob(struct keyblob_info *info) +{ + int ret = 0; + struct device *jrdev; + + /* Allocate caam job ring for operation to be performed from CAAM */ + jrdev = caam_jr_alloc(); + if (IS_ERR(jrdev)) { + pr_err("Job Ring Device allocation failed\n"); + return PTR_ERR(jrdev); + } + + /* Create a black key */ + ret = generate_black_key(jrdev, info); + if (ret) { + dev_err(jrdev, "Black key generation failed: (%d)\n", ret); + goto free_jr; + } + + /* Clear the input key, if exists */ + if (info->key) + memset(info->key, 0, info->key_len); + + /* Set key modifier, used as revision number, for blob */ + info->key_mod = caam_key_modifier; + info->key_mod_len = ARRAY_SIZE(caam_key_modifier); + + /* + * Encapsulate the key, into a black blob, in general memory + * (the only memory type supported, right now) + */ + ret = caam_blob_encap(jrdev, info); + if (ret) { + dev_err(jrdev, "Blob encapsulation of black key failed: %d\n", + ret); + goto free_jr; + } + + /* Tag the black key so it can be passed to CAAM Crypto API */ + ret = tag_black_obj(info, sizeof(info->black_key), false); + if (ret) { + dev_err(jrdev, "Black key tagging failed: %d\n", ret); + goto free_jr; + } + + /* Tag the black blob so it can be passed to CAAM Crypto API */ + ret = tag_black_obj(info, sizeof(info->blob), true); + if (ret) { + dev_err(jrdev, "Black blob tagging failed: %d\n", ret); + goto free_jr; + } + +free_jr: + caam_jr_free(jrdev); + + return ret; +} + +/** + * keygen_import_key - Import a black key from a blob + * + * @info : keyblob_info structure, will be updated with + * the black key obtained after blob decapsulation by CAAM + * + * Return : '0' on success, error code otherwise + */ +static int keygen_import_key(struct keyblob_info *info) +{ + int ret = 0; + struct device *jrdev; + struct header_conf *header; + struct tagged_object *tag_obj; + + /* Allocate CAAM Job Ring for operation to be performed from CAAM */ + jrdev = caam_jr_alloc(); + if (IS_ERR(jrdev)) { + pr_err("Job Ring Device allocation failed\n"); + return PTR_ERR(jrdev); + } + + /* Set key modifier, used as revision number, for blob */ + info->key_mod = caam_key_modifier; + info->key_mod_len = ARRAY_SIZE(caam_key_modifier); + + print_hex_dump_debug("input blob @ " __stringify(__LINE__) " : ", + DUMP_PREFIX_ADDRESS, 16, 4, info->blob, + info->blob_len, 1); + + /* Check if one can retrieve the tag object header configuration */ + if (info->blob_len <= TAG_OVERHEAD_SIZE) { + dev_err(jrdev, "Invalid blob length\n"); + ret = -EINVAL; + goto free_jr; + } + + /* Retrieve the tag object */ + tag_obj = (struct tagged_object *)info->blob; + + /* + * Check tag object header configuration + * and retrieve the tag object header configuration + */ + if (is_valid_header_conf(&tag_obj->header)) { + header = &tag_obj->header; + } else { + dev_err(jrdev, + "Unable to get tag object header configuration for blob\n"); + ret = -EINVAL; + goto free_jr; + } + + info->key_len = header->red_key_len; + + /* Validate the red key size extracted from blob */ + if (info->key_len < MIN_KEY_SIZE || info->key_len > MAX_KEY_SIZE) { + dev_err(jrdev, + "Invalid red key length extracted from blob, expected values are between 16 and 64 bytes\n"); + ret = -EINVAL; + goto free_jr; + } + + info->type = header->type; + + /* Update blob length by removing the header size */ + info->blob_len -= TAG_OVERHEAD_SIZE; + + /* + * Check the received, from user, blob length + * with the one from tag header + */ + if (info->blob_len != header->obj_len) { + dev_err(jrdev, "Mismatch between received blob length and the one from tag header\n"); + ret = -EINVAL; + goto free_jr; + } + + /* + * Decapsulate the blob into a black key, + * in general memory (the only memory type supported, right now) + */ + ret = caam_blob_decap(jrdev, info); + if (ret) { + dev_err(jrdev, "Blob decapsulation failed: %d\n", ret); + goto free_jr; + } + + /* Tag the black key so it can be passed to CAAM Crypto API */ + ret = tag_black_obj(info, sizeof(info->black_key), false); + if (ret) + dev_err(jrdev, "Black key tagging failed: %d\n", ret); + +free_jr: + caam_jr_free(jrdev); + + return ret; +} + +/** + * send_output - Send the output data (tagged key and blob) + * from kernel to user-space. + * + * @key_crt : Structure used to transfer data + * from user-space to kernel + * @info : keyblob_info structure, which contains all + * the data obtained from CAAM that needs to + * be transferred to user-space + * @create_key_op : Used to determine if it's a create or import operation + * @err : Error code received from previous operations + * + * Return : '0' on success, error code otherwise + */ +static int send_output(struct caam_keygen_cmd *key_crt, unsigned long arg, + struct keyblob_info *info, bool create_key_op, int err) +{ + int ret = 0; + char *msg; + + /* Free resource used on validate_input */ + kfree(info->key); + + if (err) + return err; + + /* Check if there's enough space to copy black key to user */ + if (key_crt->black_key_len < info->black_key_len) { + msg = "Not enough space for black key.\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + /* Send, to user, the necessary size for key */ + key_crt->black_key_len = info->black_key_len; + + ret = -EINVAL; + goto exit; + } + key_crt->black_key_len = info->black_key_len; + + /* For key import, copy to user only the black key */ + if (copy_to_user(u64_to_user_ptr(key_crt->black_key), + info->black_key, info->black_key_len)) + return -EFAULT; + + /* For key creation, copy to user, also, the blob */ + if (create_key_op) { + /* Check if there's enough space to copy blob user */ + if (key_crt->blob_len < info->blob_len) { + msg = "Not enough space for blob key.\n"; + send_err_msg(msg, u64_to_user_ptr(key_crt->blob), + key_crt->blob_len); + /* Send, to user, the necessary size for blob */ + key_crt->blob_len = info->blob_len; + + ret = -EINVAL; + goto exit; + } + + key_crt->blob_len = info->blob_len; + + if (copy_to_user(u64_to_user_ptr(key_crt->blob), info->blob, + info->blob_len)) + return -EFAULT; + } + +exit: + if (copy_to_user((void __user *)arg, key_crt, + sizeof(struct caam_keygen_cmd))) + return -EFAULT; + + return ret; +} + +static long caam_keygen_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + int ret = 0; + struct keyblob_info info = {.key = NULL}; + struct caam_keygen_cmd key_crt; + /* Used to determine if it's a create or import operation */ + bool create_key_op = false; + + switch (cmd) { + case CAAM_KEYGEN_IOCTL_CREATE: + { + create_key_op = true; + + /* Validate user-space input */ + ret = validate_input(&key_crt, arg, &info, create_key_op); + if (ret) + break; + + /* Create tagged key and blob */ + ret = keygen_create_keyblob(&info); + + /* Send data from kernel to user-space */ + ret = send_output(&key_crt, arg, &info, create_key_op, ret); + + break; + } + case CAAM_KEYGEN_IOCTL_IMPORT: + { + /* Validate user-space input */ + ret = validate_input(&key_crt, arg, &info, create_key_op); + if (ret) + break; + + /* Import tagged key from blob */ + ret = keygen_import_key(&info); + + /* Send data from kernel to user-space */ + ret = send_output(&key_crt, arg, &info, create_key_op, ret); + + break; + } + default: + ret = -ENOTTY; + } + + return ret; +} + +static const struct file_operations fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = caam_keygen_ioctl, + .compat_ioctl = compat_ptr_ioctl, +}; + +static struct miscdevice caam_keygen_dev = { + .minor = MISC_DYNAMIC_MINOR, + .name = DEVICE_NAME, + .fops = &fops +}; + +int caam_keygen_init(void) +{ + int ret; + + ret = misc_register(&caam_keygen_dev); + if (ret) { + pr_err("Failed to register device %s\n", + caam_keygen_dev.name); + return ret; + } + + pr_info("Device %s registered\n", caam_keygen_dev.name); + + return 0; +} + +void caam_keygen_exit(void) +{ + misc_deregister(&caam_keygen_dev); + + pr_info("caam_keygen unregistered\n"); +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caampkc.c linux-imx-phytec/drivers/crypto/caam/caampkc.c --- linux-6.1.55/drivers/crypto/caam/caampkc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/caampkc.c 2024-06-19 12:33:59.740217190 +0200 @@ -1164,10 +1164,10 @@ /* Determine public key hardware accelerator presence. */ if (priv->era < 10) { - pk_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & + pk_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) & CHA_ID_LS_PK_MASK) >> CHA_ID_LS_PK_SHIFT; } else { - pkha = rd_reg32(&priv->ctrl->vreg.pkha); + pkha = rd_reg32(&priv->jr[0]->vreg.pkha); pk_inst = pkha & CHA_VER_NUM_MASK; /* diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/caamrng.c linux-imx-phytec/drivers/crypto/caam/caamrng.c --- linux-6.1.55/drivers/crypto/caam/caamrng.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/caamrng.c 2024-06-19 12:33:59.744217258 +0200 @@ -13,6 +13,7 @@ #include #include #include +#include #include "compat.h" @@ -99,6 +100,7 @@ return -ENOMEM; } + request_bus_freq(BUS_FREQ_HIGH); init_completion(done); err = caam_jr_enqueue(jrdev, caam_init_desc(desc, dst_dma), @@ -108,6 +110,7 @@ err = 0; } + release_bus_freq(BUS_FREQ_HIGH); dma_unmap_single(jrdev, dst_dma, len, DMA_FROM_DEVICE); return err ?: (ret ?: len); @@ -170,6 +173,52 @@ kfifo_free(&ctx->fifo); } +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST +static inline void test_len(struct hwrng *rng, size_t len, bool wait) +{ + u8 *buf; + int real_len; + struct caam_rng_ctx *ctx = to_caam_rng_ctx(rng); + struct device *dev = ctx->ctrldev; + + buf = kzalloc(sizeof(u8) * len, GFP_KERNEL); + real_len = rng->read(rng, buf, len, wait); + dev_info(dev, "wanted %zu bytes, got %d\n", len, real_len); + if (real_len < 0) + dev_err(dev, "READ FAILED\n"); + else if (real_len == 0 && wait) + dev_err(dev, "WAITING FAILED\n"); + if (real_len > 0) + print_hex_dump_debug("random bytes@: ", DUMP_PREFIX_ADDRESS, 16, + 4, buf, real_len, 1); + kfree(buf); +} + +static inline void test_mode_once(struct hwrng *rng, bool wait) +{ + test_len(rng, 32, wait); + test_len(rng, 64, wait); + test_len(rng, 128, wait); +} + +static inline void test_mode(struct hwrng *rng, bool wait) +{ +#define TEST_PASS 1 + int i; + + for (i = 0; i < TEST_PASS; i++) + test_mode_once(rng, wait); +} + +static void self_test(struct hwrng *rng) +{ + pr_info("testing without waiting\n"); + test_mode(rng, false); + pr_info("testing with waiting\n"); + test_mode(rng, true); +} +#endif + static int caam_init(struct hwrng *rng) { struct caam_rng_ctx *ctx = to_caam_rng_ctx(rng); @@ -224,10 +273,10 @@ /* Check for an instantiated RNG before registration */ if (priv->era < 10) - rng_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & + rng_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT; else - rng_inst = rd_reg32(&priv->ctrl->vreg.rng) & CHA_VER_NUM_MASK; + rng_inst = rd_reg32(&priv->jr[0]->vreg.rng) & CHA_VER_NUM_MASK; if (!rng_inst) return 0; @@ -256,6 +305,10 @@ return ret; } +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST + self_test(&ctx->rng); +#endif + devres_close_group(ctrldev, caam_rng_init); return 0; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/ctrl.c linux-imx-phytec/drivers/crypto/caam/ctrl.c --- linux-6.1.55/drivers/crypto/caam/ctrl.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/ctrl.c 2024-06-19 12:33:59.744217258 +0200 @@ -3,10 +3,11 @@ * Controller-level driver, kernel property detection, initialization * * Copyright 2008-2012 Freescale Semiconductor, Inc. - * Copyright 2018-2019 NXP + * Copyright 2018-2022 NXP */ #include +#include #include #include #include @@ -19,6 +20,7 @@ #include "jr.h" #include "desc_constr.h" #include "ctrl.h" +#include "sm.h" bool caam_dpaa2; EXPORT_SYMBOL(caam_dpaa2); @@ -79,6 +81,15 @@ append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); } +static const struct of_device_id imx8m_machine_match[] = { + { .compatible = "fsl,imx8mm", }, + { .compatible = "fsl,imx8mn", }, + { .compatible = "fsl,imx8mp", }, + { .compatible = "fsl,imx8mq", }, + { .compatible = "fsl,imx8ulp", }, + { } +}; + /* * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of * the software (no JR/QI used). @@ -105,10 +116,7 @@ * Apparently on i.MX8M{Q,M,N,P} it doesn't matter if virt_en == 1 * and the following steps should be performed regardless */ - of_machine_is_compatible("fsl,imx8mq") || - of_machine_is_compatible("fsl,imx8mm") || - of_machine_is_compatible("fsl,imx8mn") || - of_machine_is_compatible("fsl,imx8mp")) { + of_match_node(imx8m_machine_match, of_root)) { clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && @@ -344,16 +352,15 @@ /* * kick_trng - sets the various parameters for enabling the initialization * of the RNG4 block in CAAM - * @pdev - pointer to the platform device + * @dev - pointer to the controller device * @ent_delay - Defines the length (in system clocks) of each entropy sample. */ -static void kick_trng(struct platform_device *pdev, int ent_delay) +static void kick_trng(struct device *dev, int ent_delay) { - struct device *ctrldev = &pdev->dev; - struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); struct caam_ctrl __iomem *ctrl; struct rng4tst __iomem *r4tst; - u32 val; + u32 val, rtsdctl; ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; r4tst = &ctrl->r4tst[0]; @@ -369,26 +376,38 @@ * Performance-wise, it does not make sense to * set the delay to a value that is lower * than the last one that worked (i.e. the state handles - * were instantiated properly. Thus, instead of wasting - * time trying to set the values controlling the sample - * frequency, the function simply returns. - */ - val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) - >> RTSDCTL_ENT_DLY_SHIFT; - if (ent_delay <= val) - goto start_rng; - - val = rd_reg32(&r4tst->rtsdctl); - val = (val & ~RTSDCTL_ENT_DLY_MASK) | - (ent_delay << RTSDCTL_ENT_DLY_SHIFT); - wr_reg32(&r4tst->rtsdctl, val); - /* min. freq. count, equal to 1/4 of the entropy sample length */ - wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); - /* disable maximum frequency count */ - wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); - /* read the control register */ - val = rd_reg32(&r4tst->rtmctl); -start_rng: + * were instantiated properly). + */ + rtsdctl = rd_reg32(&r4tst->rtsdctl); + val = (rtsdctl & RTSDCTL_ENT_DLY_MASK) >> RTSDCTL_ENT_DLY_SHIFT; + if (ent_delay > val) { + val = ent_delay; + /* min. freq. count, equal to 1/4 of the entropy sample length */ + wr_reg32(&r4tst->rtfrqmin, val >> 2); + /* max. freq. count, equal to 16 times the entropy sample length */ + wr_reg32(&r4tst->rtfrqmax, val << 4); + } + + wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) | + RTSDCTL_SAMP_SIZE_VAL); + + /* + * To avoid reprogramming the self-test parameters over and over again, + * use RTSDCTL[SAMP_SIZE] as an indicator. + */ + if ((rtsdctl & RTSDCTL_SAMP_SIZE_MASK) != RTSDCTL_SAMP_SIZE_VAL) { + wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32); + wr_reg32(&r4tst->rtpkrrng, 570); + wr_reg32(&r4tst->rtpkrmax, 1600); + wr_reg32(&r4tst->rtscml, (122 << 16) | 317); + wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107); + wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62); + wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39); + wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26); + wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18); + wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17); + } + /* * select raw sampling in both entropy shifter * and statistical checker; ; put RNG4 into run mode @@ -397,7 +416,7 @@ RTMCTL_SAMP_MODE_RAW_ES_SC); } -static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl) +static int caam_get_era_from_hw(struct caam_perfmon __iomem *perfmon) { static const struct { u16 ip_id; @@ -423,12 +442,12 @@ u16 ip_id; int i; - ccbvid = rd_reg32(&ctrl->perfmon.ccb_id); + ccbvid = rd_reg32(&perfmon->ccb_id); era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT; if (era) /* This is '0' prior to CAAM ERA-6 */ return era; - id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms); + id_ms = rd_reg32(&perfmon->caam_id_ms); ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT; maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT; @@ -448,7 +467,7 @@ * * @ctrl: controller region */ -static int caam_get_era(struct caam_ctrl __iomem *ctrl) +static int caam_get_era(struct caam_perfmon __iomem *perfmon) { struct device_node *caam_node; int ret; @@ -461,7 +480,7 @@ if (!ret) return prop; else - return caam_get_era_from_hw(ctrl); + return caam_get_era_from_hw(perfmon); } /* @@ -591,6 +610,241 @@ debugfs_remove_recursive(root); } +static void caam_dma_dev_unregister(void *data) +{ + platform_device_unregister(data); +} + +static bool needs_entropy_delay_adjustment(void) +{ + if (of_machine_is_compatible("fsl,imx6sx")) + return true; + return false; +} + +static int caam_ctrl_rng_init(struct device *dev) +{ + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); + struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; + int ret, gen_sk; + u32 ent_delay = RTSDCTL_ENT_DLY_MIN; + u8 rng_vid; + + if (ctrlpriv->era < 10) { + struct caam_perfmon __iomem *perfmon; + + perfmon = ctrlpriv->total_jobrs ? + (struct caam_perfmon *)&ctrlpriv->jr[0]->perfmon : + (struct caam_perfmon *)&ctrl->perfmon; + + rng_vid = (rd_reg32(&perfmon->cha_id_ls) & + CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT; + } else { + struct version_regs __iomem *vreg; + + vreg = ctrlpriv->total_jobrs ? + (struct version_regs *)&ctrlpriv->jr[0]->vreg : + (struct version_regs *)&ctrl->vreg; + + rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >> + CHA_VER_VID_SHIFT; + } + + /* + * Read entropy-delay property from device tree. If property is not + * available or missing, update the entropy delay value only for imx6sx. + */ + if (device_property_read_u32(dev, "entropy-delay", &ent_delay)) { + dev_dbg(dev, "entropy-delay property missing in DT\n"); + if (needs_entropy_delay_adjustment()) + ent_delay = 12000; + } + + /* + * If SEC has RNG version >= 4 and RNG state handle has not been + * already instantiated, do RNG instantiation + * In case of SoCs with Management Complex, RNG is managed by MC f/w. + */ + if (!(ctrlpriv->mc_en && ctrlpriv->pr_support) && rng_vid >= 4) { + ctrlpriv->rng4_sh_init = + rd_reg32(&ctrl->r4tst[0].rdsta); + /* + * If the secure keys (TDKEK, JDKEK, TDSK), were already + * generated, signal this to the function that is instantiating + * the state handles. An error would occur if RNG4 attempts + * to regenerate these keys before the next POR. + */ + gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; + ctrlpriv->rng4_sh_init &= RDSTA_MASK; + do { + int inst_handles = + rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK; + /* + * If either SH were instantiated by somebody else + * (e.g. u-boot) then it is assumed that the entropy + * parameters are properly set and thus the function + * setting these (kick_trng(...)) is skipped. + * Also, if a handle was instantiated, do not change + * the TRNG parameters. + */ + if (!(ctrlpriv->rng4_sh_init || inst_handles)) { + dev_info(dev, + "Entropy delay = %u\n", + ent_delay); + kick_trng(dev, ent_delay); + ent_delay += 400; + } + /* + * if instantiate_rng(...) fails, the loop will rerun + * and the kick_trng(...) function will modify the + * upper and lower limits of the entropy sampling + * interval, leading to a successful initialization of + * the RNG. + */ + ret = instantiate_rng(dev, inst_handles, + gen_sk); + /* + * Entropy delay is determined via TRNG characterization. + * TRNG characterization is run across different voltages + * and temperatures. + * If worst case value for ent_dly is identified, + * the loop can be skipped for that platform. + */ + if (needs_entropy_delay_adjustment()) + break; + if (ret == -EAGAIN) + /* + * if here, the loop will rerun, + * so don't hog the CPU + */ + cpu_relax(); + } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); + if (ret) { + dev_err(dev, "failed to instantiate RNG"); + return ret; + } + /* + * Set handles initialized by this module as the complement of + * the already initialized ones + */ + ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK; + + /* Enable RDB bit so that RNG works faster */ + clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); + } + + return 0; +} + +#ifdef CONFIG_PM_SLEEP + +/* Indicate if the internal state of the CAAM is lost during PM */ +static int caam_off_during_pm(void) +{ + bool not_off_during_pm = of_machine_is_compatible("fsl,imx6q") || + of_machine_is_compatible("fsl,imx6qp") || + of_machine_is_compatible("fsl,imx6dl"); + + return not_off_during_pm ? 0 : 1; +} + +static void caam_state_save(struct device *dev) +{ + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); + struct caam_ctl_state *state = &ctrlpriv->state; + struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; + u32 deco_inst, jr_inst; + int i; + + state->mcr = rd_reg32(&ctrl->mcr); + state->scfgr = rd_reg32(&ctrl->scfgr); + + deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & + CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT; + for (i = 0; i < deco_inst; i++) { + state->deco_mid[i].liodn_ms = + rd_reg32(&ctrl->deco_mid[i].liodn_ms); + state->deco_mid[i].liodn_ls = + rd_reg32(&ctrl->deco_mid[i].liodn_ls); + } + + jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & + CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT; + for (i = 0; i < jr_inst; i++) { + state->jr_mid[i].liodn_ms = + rd_reg32(&ctrl->jr_mid[i].liodn_ms); + state->jr_mid[i].liodn_ls = + rd_reg32(&ctrl->jr_mid[i].liodn_ls); + } +} + +static void caam_state_restore(const struct device *dev) +{ + const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); + const struct caam_ctl_state *state = &ctrlpriv->state; + struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; + u32 deco_inst, jr_inst; + int i; + + wr_reg32(&ctrl->mcr, state->mcr); + wr_reg32(&ctrl->scfgr, state->scfgr); + + deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & + CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT; + for (i = 0; i < deco_inst; i++) { + wr_reg32(&ctrl->deco_mid[i].liodn_ms, + state->deco_mid[i].liodn_ms); + wr_reg32(&ctrl->deco_mid[i].liodn_ls, + state->deco_mid[i].liodn_ls); + } + + jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & + CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT; + for (i = 0; i < ctrlpriv->total_jobrs; i++) { + wr_reg32(&ctrl->jr_mid[i].liodn_ms, + state->jr_mid[i].liodn_ms); + wr_reg32(&ctrl->jr_mid[i].liodn_ls, + state->jr_mid[i].liodn_ls); + } + + if (ctrlpriv->virt_en == 1) + clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | + JRSTART_JR1_START | JRSTART_JR2_START | + JRSTART_JR3_START); +} + +static int caam_ctrl_suspend(struct device *dev) +{ + const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); + + if (ctrlpriv->caam_off_during_pm && !ctrlpriv->scu_en && + !ctrlpriv->optee_en) + caam_state_save(dev); + + return 0; +} + +static int caam_ctrl_resume(struct device *dev) +{ + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev); + int ret = 0; + + if (ctrlpriv->caam_off_during_pm && !ctrlpriv->scu_en && + !ctrlpriv->optee_en) { + caam_state_restore(dev); + + /* HW and rng will be reset so deinstantiation can be removed */ + devm_remove_action(dev, devm_deinstantiate_rng, dev); + ret = caam_ctrl_rng_init(dev); + } + + return ret; +} + +SIMPLE_DEV_PM_OPS(caam_ctrl_pm_ops, caam_ctrl_suspend, caam_ctrl_resume); + +#endif /* CONFIG_PM_SLEEP */ + #ifdef CONFIG_FSL_MC_BUS static bool check_version(struct fsl_mc_version *mc_version, u32 major, u32 minor, u32 revision) @@ -611,29 +865,28 @@ } #endif -static bool needs_entropy_delay_adjustment(void) -{ - if (of_machine_is_compatible("fsl,imx6sx")) - return true; - return false; -} - /* Probe routine for CAAM top (controller) level */ static int caam_probe(struct platform_device *pdev) { - int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; + int ret, ring; u64 caam_id; const struct soc_device_attribute *imx_soc_match; + static struct platform_device_info caam_dma_pdev_info = { + .name = "caam-dma", + .id = PLATFORM_DEVID_NONE + }; + static struct platform_device *caam_dma_dev; struct device *dev; struct device_node *nprop, *np; + struct resource res_regs; struct caam_ctrl __iomem *ctrl; struct caam_drv_private *ctrlpriv; + struct caam_perfmon __iomem *perfmon; struct dentry *dfs_root; u32 scfgr, comp_params; - u8 rng_vid; int pg_size; int BLOCK_OFFSET = 0; - bool pr_support = false; + bool reg_access = true; ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); if (!ctrlpriv) @@ -644,9 +897,44 @@ nprop = pdev->dev.of_node; imx_soc_match = soc_device_match(caam_imx_soc_table); + if (!imx_soc_match && of_match_node(imx8m_machine_match, of_root)) + return -EPROBE_DEFER; + caam_imx = (bool)imx_soc_match; +#ifdef CONFIG_PM_SLEEP + ctrlpriv->caam_off_during_pm = caam_imx && caam_off_during_pm(); +#endif + if (imx_soc_match) { + np = of_find_compatible_node(NULL, NULL, "fsl,imx-scu"); + + if (!np) + np = of_find_compatible_node(NULL, NULL, "fsl,imx-ele"); + + ctrlpriv->scu_en = !!np; + of_node_put(np); + + reg_access = !ctrlpriv->scu_en; + + /* + * CAAM clocks cannot be controlled from kernel. + * They are automatically turned on by SCU f/w. + */ + if (ctrlpriv->scu_en) + goto iomap_ctrl; + + /* + * Until Layerscape and i.MX OP-TEE get in sync, + * only i.MX OP-TEE use cases disallow access to + * caam page 0 (controller) registers. + */ + np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz"); + ctrlpriv->optee_en = !!np; + of_node_put(np); + + reg_access = reg_access && !ctrlpriv->optee_en; + if (!imx_soc_match->data) { dev_err(dev, "No clock data provided for i.MX SoC"); return -EINVAL; @@ -657,7 +945,7 @@ return ret; } - +iomap_ctrl: /* Get configuration properties from device tree */ /* First, get register page */ ctrl = devm_of_iomap(dev, nprop, 0, NULL); @@ -667,10 +955,38 @@ return ret; } - caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) & + ring = 0; + for_each_available_child_of_node(nprop, np) + if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || + of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { + u32 reg; + + if (of_property_read_u32_index(np, "reg", 0, ®)) { + dev_err(dev, "%s read reg property error\n", + np->full_name); + continue; + } + + ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) + ((__force uint8_t *)ctrl + reg); + + ctrlpriv->total_jobrs++; + ring++; + } + + /* + * Wherever possible, instead of accessing registers from the global page, + * use the alias registers in the first (cf. DT nodes order) + * job ring's page. + */ + perfmon = ring ? (struct caam_perfmon *)&ctrlpriv->jr[0]->perfmon : + (struct caam_perfmon *)&ctrl->perfmon; + + caam_little_end = !(bool)(rd_reg32(&perfmon->status) & (CSTA_PLEND | CSTA_ALT_PLEND)); - comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); - if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR) + comp_params = rd_reg32(&perfmon->comp_parms_ms); + if (reg_access && comp_params & CTPR_MS_PS && + rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR) caam_ptr_sz = sizeof(u64); else caam_ptr_sz = sizeof(u32); @@ -717,8 +1033,6 @@ BLOCK_OFFSET * DECO_BLOCK_NUMBER ); - /* Get the IRQ of the controller (for security violations only) */ - ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc"); ctrlpriv->mc_en = !!np; of_node_put(np); @@ -729,12 +1043,44 @@ mc_version = fsl_mc_get_version(); if (mc_version) - pr_support = check_version(mc_version, 10, 20, 0); + ctrlpriv->pr_support = check_version(mc_version, 10, 20, + 0); else return -EPROBE_DEFER; } #endif + /* Only i.MX SoCs have sm */ + if (!imx_soc_match) + goto mc_fw; + + /* Get CAAM-SM node and of_iomap() and save */ + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm"); + if (!np) + return -ENODEV; + + /* Get CAAM SM registers base address from device tree */ + ret = of_address_to_resource(np, 0, &res_regs); + if (ret) { + dev_err(dev, "failed to retrieve registers base from device tree\n"); + of_node_put(np); + return -ENODEV; + } + + ctrlpriv->sm_phy = res_regs.start; + ctrlpriv->sm_base = devm_ioremap_resource(dev, &res_regs); + if (IS_ERR(ctrlpriv->sm_base)) { + of_node_put(np); + return PTR_ERR(ctrlpriv->sm_base); + } + + ctrlpriv->sm_present = 1; + of_node_put(np); + + if (!reg_access) + goto set_dma_mask; + +mc_fw: /* * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, * long pointers in master configuration register. @@ -774,13 +1120,14 @@ JRSTART_JR1_START | JRSTART_JR2_START | JRSTART_JR3_START); +set_dma_mask: ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev)); if (ret) { dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret); return ret; } - ctrlpriv->era = caam_get_era(ctrl); + ctrlpriv->era = caam_get_era(perfmon); ctrlpriv->domain = iommu_get_domain_for_dev(dev); dfs_root = debugfs_create_dir(dev_name(dev), NULL); @@ -791,7 +1138,7 @@ return ret; } - caam_debugfs_init(ctrlpriv, dfs_root); + caam_debugfs_init(ctrlpriv, perfmon, dfs_root); /* Check to see if (DPAA 1.x) QI present. If so, enable */ if (ctrlpriv->qi_present && !caam_dpaa2) { @@ -810,26 +1157,27 @@ #endif } - ring = 0; - for_each_available_child_of_node(nprop, np) - if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || - of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { - ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) - ((__force uint8_t *)ctrl + - (ring + JR_BLOCK_NUMBER) * - BLOCK_OFFSET - ); - ctrlpriv->total_jobrs++; - ring++; - } - /* If no QI and no rings specified, quit and go home */ if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { dev_err(dev, "no queues configured, terminating\n"); return -ENOMEM; } - comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ls); + caam_dma_pdev_info.parent = dev; + caam_dma_pdev_info.dma_mask = dma_get_mask(dev); + caam_dma_dev = platform_device_register_full(&caam_dma_pdev_info); + if (IS_ERR(caam_dma_dev)) { + dev_err(dev, "Unable to create and register caam-dma dev\n"); + return PTR_ERR(caam_dma_dev); + } else { + set_dma_ops(&caam_dma_dev->dev, get_dma_ops(dev)); + ret = devm_add_action_or_reset(dev, caam_dma_dev_unregister, + caam_dma_dev); + if (ret) + return ret; + } + + comp_params = rd_reg32(&perfmon->comp_parms_ls); ctrlpriv->blob_present = !!(comp_params & CTPR_LS_BLOB); /* @@ -838,97 +1186,27 @@ * check both here. */ if (ctrlpriv->era < 10) { - rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) & - CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT; ctrlpriv->blob_present = ctrlpriv->blob_present && - (rd_reg32(&ctrl->perfmon.cha_num_ls) & CHA_ID_LS_AES_MASK); + (rd_reg32(&perfmon->cha_num_ls) & CHA_ID_LS_AES_MASK); } else { - rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >> - CHA_VER_VID_SHIFT; + struct version_regs __iomem *vreg; + + vreg = ctrlpriv->total_jobrs ? + (struct version_regs *)&ctrlpriv->jr[0]->vreg : + (struct version_regs *)&ctrl->vreg; + ctrlpriv->blob_present = ctrlpriv->blob_present && - (rd_reg32(&ctrl->vreg.aesa) & CHA_VER_MISC_AES_NUM_MASK); + (rd_reg32(&vreg->aesa) & CHA_VER_MISC_AES_NUM_MASK); } - /* - * If SEC has RNG version >= 4 and RNG state handle has not been - * already instantiated, do RNG instantiation - * In case of SoCs with Management Complex, RNG is managed by MC f/w. - */ - if (!(ctrlpriv->mc_en && pr_support) && rng_vid >= 4) { - ctrlpriv->rng4_sh_init = - rd_reg32(&ctrl->r4tst[0].rdsta); - /* - * If the secure keys (TDKEK, JDKEK, TDSK), were already - * generated, signal this to the function that is instantiating - * the state handles. An error would occur if RNG4 attempts - * to regenerate these keys before the next POR. - */ - gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; - ctrlpriv->rng4_sh_init &= RDSTA_MASK; - do { - int inst_handles = - rd_reg32(&ctrl->r4tst[0].rdsta) & - RDSTA_MASK; - /* - * If either SH were instantiated by somebody else - * (e.g. u-boot) then it is assumed that the entropy - * parameters are properly set and thus the function - * setting these (kick_trng(...)) is skipped. - * Also, if a handle was instantiated, do not change - * the TRNG parameters. - */ - if (needs_entropy_delay_adjustment()) - ent_delay = 12000; - if (!(ctrlpriv->rng4_sh_init || inst_handles)) { - dev_info(dev, - "Entropy delay = %u\n", - ent_delay); - kick_trng(pdev, ent_delay); - ent_delay += 400; - } - /* - * if instantiate_rng(...) fails, the loop will rerun - * and the kick_trng(...) function will modify the - * upper and lower limits of the entropy sampling - * interval, leading to a successful initialization of - * the RNG. - */ - ret = instantiate_rng(dev, inst_handles, - gen_sk); - /* - * Entropy delay is determined via TRNG characterization. - * TRNG characterization is run across different voltages - * and temperatures. - * If worst case value for ent_dly is identified, - * the loop can be skipped for that platform. - */ - if (needs_entropy_delay_adjustment()) - break; - if (ret == -EAGAIN) - /* - * if here, the loop will rerun, - * so don't hog the CPU - */ - cpu_relax(); - } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); - if (ret) { - dev_err(dev, "failed to instantiate RNG"); + if (reg_access) { + ret = caam_ctrl_rng_init(dev); + if (ret) return ret; - } - /* - * Set handles initialized by this module as the complement of - * the already initialized ones - */ - ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK; - - /* Enable RDB bit so that RNG works faster */ - clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); } - /* NOTE: RTIC detection ought to go here, around Si time */ - - caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | - (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); + caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 | + (u64)rd_reg32(&perfmon->caam_id_ls); /* Report "alive" for developer to see */ dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, @@ -947,6 +1225,9 @@ .driver = { .name = "caam", .of_match_table = caam_match, +#ifdef CONFIG_PM_SLEEP + .pm = &caam_ctrl_pm_ops, +#endif }, .probe = caam_probe, }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/debugfs.c linux-imx-phytec/drivers/crypto/caam/debugfs.c --- linux-6.1.55/drivers/crypto/caam/debugfs.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/debugfs.c 2024-06-19 12:33:59.744217258 +0200 @@ -42,16 +42,14 @@ } #endif -void caam_debugfs_init(struct caam_drv_private *ctrlpriv, struct dentry *root) +void caam_debugfs_init(struct caam_drv_private *ctrlpriv, + struct caam_perfmon *perfmon, struct dentry *root) { - struct caam_perfmon *perfmon; - /* * FIXME: needs better naming distinction, as some amalgamation of * "caam" and nprop->full_name. The OF name isn't distinctive, * but does separate instances */ - perfmon = (struct caam_perfmon __force *)&ctrlpriv->ctrl->perfmon; ctrlpriv->ctl = debugfs_create_dir("ctl", root); @@ -78,6 +76,9 @@ debugfs_create_file("fault_status", 0444, ctrlpriv->ctl, &perfmon->status, &caam_fops_u32_ro); + if (ctrlpriv->scu_en || ctrlpriv->optee_en) + return; + /* Internal covering keys (useful in non-secure mode only) */ ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0]; ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/debugfs.h linux-imx-phytec/drivers/crypto/caam/debugfs.h --- linux-6.1.55/drivers/crypto/caam/debugfs.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/debugfs.h 2024-06-19 12:33:59.744217258 +0200 @@ -6,11 +6,14 @@ struct dentry; struct caam_drv_private; +struct caam_perfmon; #ifdef CONFIG_DEBUG_FS -void caam_debugfs_init(struct caam_drv_private *ctrlpriv, struct dentry *root); +void caam_debugfs_init(struct caam_drv_private *ctrlpriv, + struct caam_perfmon *perfmon, struct dentry *root); #else static inline void caam_debugfs_init(struct caam_drv_private *ctrlpriv, + struct caam_perfmon *perfmon, struct dentry *root) {} #endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/desc_constr.h linux-imx-phytec/drivers/crypto/caam/desc_constr.h --- linux-6.1.55/drivers/crypto/caam/desc_constr.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/desc_constr.h 2024-06-19 12:33:59.744217258 +0200 @@ -240,6 +240,7 @@ APPEND_CMD_RET(jump, JUMP) APPEND_CMD_RET(move, MOVE) APPEND_CMD_RET(move_len, MOVE_LEN) +APPEND_CMD_RET(moveb, MOVEB) static inline void set_jump_tgt_here(u32 * const desc, u32 *jump_cmd) { @@ -500,6 +501,8 @@ * @key_virt: virtual address where algorithm key resides * @key_inline: true - key can be inlined in the descriptor; false - key is * referenced by the descriptor + * @key_real_len: size of the key to be loaded by the CAAM + * @key_cmd_opt: optional parameters for KEY command */ struct alginfo { u32 algtype; @@ -508,6 +511,8 @@ dma_addr_t key_dma; const void *key_virt; bool key_inline; + u32 key_real_len; + u32 key_cmd_opt; }; /** diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/desc.h linux-imx-phytec/drivers/crypto/caam/desc.h --- linux-6.1.55/drivers/crypto/caam/desc.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/desc.h 2024-06-19 12:33:59.744217258 +0200 @@ -43,6 +43,7 @@ #define CMD_SEQ_LOAD (0x03 << CMD_SHIFT) #define CMD_FIFO_LOAD (0x04 << CMD_SHIFT) #define CMD_SEQ_FIFO_LOAD (0x05 << CMD_SHIFT) +#define CMD_MOVEB (0x07 << CMD_SHIFT) #define CMD_STORE (0x0a << CMD_SHIFT) #define CMD_SEQ_STORE (0x0b << CMD_SHIFT) #define CMD_FIFO_STORE (0x0c << CMD_SHIFT) @@ -152,7 +153,7 @@ * with the TDKEK if TK is set */ #define KEY_ENC 0x00400000 - +#define KEY_ENC_OFFSET 22 /* * No Write Back - Do not allow key to be FIFO STOREd */ @@ -162,11 +163,13 @@ * Enhanced Encryption of Key */ #define KEY_EKT 0x00100000 +#define KEY_EKT_OFFSET 20 /* * Encrypted with Trusted Key */ #define KEY_TK 0x00008000 +#define KEY_TK_OFFSET 15 /* * KDEST - Key Destination: 0 - class key register, @@ -363,6 +366,7 @@ #define FIFOLD_TYPE_PK_N (0x08 << FIFOLD_TYPE_SHIFT) #define FIFOLD_TYPE_PK_A (0x0c << FIFOLD_TYPE_SHIFT) #define FIFOLD_TYPE_PK_B (0x0d << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_IFIFO (0x0f << FIFOLD_TYPE_SHIFT) /* Other types. Need to OR in last/flush bits as desired */ #define FIFOLD_TYPE_MSG_MASK (0x38 << FIFOLD_TYPE_SHIFT) @@ -403,6 +407,10 @@ #define FIFOST_TYPE_PKHA_N (0x08 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_PKHA_A (0x0c << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_PKHA_B (0x0d << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_CCM_JKEK (0x10 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_CCM_TKEK (0x11 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_CCM_JKEK (0x14 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_CCM_TKEK (0x15 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_AF_SBOX_JKEK (0x20 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT) #define FIFOST_TYPE_PKHA_E_JKEK (0x22 << FIFOST_TYPE_SHIFT) @@ -1136,6 +1144,23 @@ #define OP_PCL_PKPROT_ECC 0x0002 #define OP_PCL_PKPROT_F2M 0x0001 +/* Blob protocol protinfo bits */ +#define OP_PCL_BLOB_TK 0x0200 +#define OP_PCL_BLOB_EKT 0x0100 + +#define OP_PCL_BLOB_K2KR_MEM 0x0000 +#define OP_PCL_BLOB_K2KR_C1KR 0x0010 +#define OP_PCL_BLOB_K2KR_C2KR 0x0030 +#define OP_PCL_BLOB_K2KR_AFHAS 0x0050 +#define OP_PCL_BLOB_K2KR_C2KR_SPLIT 0x0070 + +#define OP_PCL_BLOB_PTXT_SECMEM 0x0008 +#define OP_PCL_BLOB_BLACK 0x0004 + +#define OP_PCL_BLOB_FMT_NORMAL 0x0000 +#define OP_PCL_BLOB_FMT_MSTR 0x0002 +#define OP_PCL_BLOB_FMT_TEST 0x0003 + /* For non-protocol/alg-only op commands */ #define OP_ALG_TYPE_SHIFT 24 #define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT) @@ -1502,6 +1527,7 @@ #define MATH_SRC1_INFIFO (0x0a << MATH_SRC1_SHIFT) #define MATH_SRC1_OUTFIFO (0x0b << MATH_SRC1_SHIFT) #define MATH_SRC1_ONE (0x0c << MATH_SRC1_SHIFT) +#define MATH_SRC1_ZERO (0x0f << MATH_SRC1_SHIFT) /* Destination selectors */ #define MATH_DEST_SHIFT 8 @@ -1684,4 +1710,31 @@ /* Frame Descriptor Command for Replacement Job Descriptor */ #define FD_CMD_REPLACE_JOB_DESC 0x20000000 +/* CHA Control Register bits */ +#define CCTRL_RESET_CHA_ALL 0x1 +#define CCTRL_RESET_CHA_AESA 0x2 +#define CCTRL_RESET_CHA_DESA 0x4 +#define CCTRL_RESET_CHA_AFHA 0x8 +#define CCTRL_RESET_CHA_KFHA 0x10 +#define CCTRL_RESET_CHA_SF8A 0x20 +#define CCTRL_RESET_CHA_PKHA 0x40 +#define CCTRL_RESET_CHA_MDHA 0x80 +#define CCTRL_RESET_CHA_CRCA 0x100 +#define CCTRL_RESET_CHA_RNG 0x200 +#define CCTRL_RESET_CHA_SF9A 0x400 +#define CCTRL_RESET_CHA_ZUCE 0x800 +#define CCTRL_RESET_CHA_ZUCA 0x1000 +#define CCTRL_UNLOAD_PK_A0 0x10000 +#define CCTRL_UNLOAD_PK_A1 0x20000 +#define CCTRL_UNLOAD_PK_A2 0x40000 +#define CCTRL_UNLOAD_PK_A3 0x80000 +#define CCTRL_UNLOAD_PK_B0 0x100000 +#define CCTRL_UNLOAD_PK_B1 0x200000 +#define CCTRL_UNLOAD_PK_B2 0x400000 +#define CCTRL_UNLOAD_PK_B3 0x800000 +#define CCTRL_UNLOAD_PK_N 0x1000000 +#define CCTRL_UNLOAD_PK_A 0x4000000 +#define CCTRL_UNLOAD_PK_B 0x8000000 +#define CCTRL_UNLOAD_SBOX 0x10000000 + #endif /* DESC_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/dpseci.c linux-imx-phytec/drivers/crypto/caam/dpseci.c --- linux-6.1.55/drivers/crypto/caam/dpseci.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/dpseci.c 2024-06-19 12:33:59.744217258 +0200 @@ -5,6 +5,7 @@ */ #include +#include #include "dpseci.h" #include "dpseci_cmd.h" @@ -16,8 +17,8 @@ * @token: Returned token; use in subsequent API calls * * This function can be used to open a control session for an already created - * object; an object may have been declared statically in the DPL - * or created dynamically. + * object; an object may have been declared in the DPL or by calling the + * dpseci_create() function. * This function returns a unique authentication token, associated with the * specific object ID and the specific MC portal; this token must be used in all * subsequent commands for this specific object. @@ -67,6 +68,85 @@ } /** + * dpseci_create() - Create the DPSECI object + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: returned object id + * + * Create the DPSECI object, allocate required resources and perform required + * initialization. + * + * The object can be created either by declaring it in the DPL file, or by + * calling this function. + * + * The function accepts an authentication token of a parent container that this + * object should be assigned to. The token can be '0' so the object will be + * assigned to the default container. + * The newly created object can be opened with the returned object id and using + * the container's associated tokens and MC portals. + * + * Return: '0' on success, error code otherwise + */ +int dpseci_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpseci_cfg *cfg, u32 *obj_id) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_create *cmd_params; + int i, err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CREATE, + cmd_flags, + dprc_token); + cmd_params = (struct dpseci_cmd_create *)cmd.params; + for (i = 0; i < 8; i++) + cmd_params->priorities[i] = cfg->priorities[i]; + for (i = 0; i < 8; i++) + cmd_params->priorities2[i] = cfg->priorities[8 + i]; + cmd_params->num_tx_queues = cfg->num_tx_queues; + cmd_params->num_rx_queues = cfg->num_rx_queues; + cmd_params->options = cpu_to_le32(cfg->options); + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + *obj_id = mc_cmd_read_object_id(&cmd); + + return 0; +} + +/** + * dpseci_destroy() - Destroy the DPSECI object and release all its resources + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @object_id: The object id; it must be a valid id within the container that + * created this object + * + * The function accepts the authentication token of the parent container that + * created the object (not the one that currently owns the object). The object + * is searched within parent using the provided 'object_id'. + * All tokens to the object must be closed before calling destroy. + * + * Return: '0' on success, error code otherwise + */ +int dpseci_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_destroy *cmd_params; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_DESTROY, + cmd_flags, + dprc_token); + cmd_params = (struct dpseci_cmd_destroy *)cmd.params; + cmd_params->object_id = cpu_to_le32(object_id); + + return mc_send_command(mc_io, &cmd); +} + +/** * dpseci_enable() - Enable the DPSECI, allow sending and receiving frames * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' @@ -151,6 +231,198 @@ } /** + * dpseci_get_irq_enable() - Get overall interrupt state + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @en: Returned Interrupt state - enable = 1, disable = 0 + * + * Return: '0' on success, error code otherwise + */ +int dpseci_get_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u8 *en) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_enable *cmd_params; + struct dpseci_rsp_get_irq_enable *rsp_params; + int err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_ENABLE, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_enable *)cmd.params; + cmd_params->irq_index = irq_index; + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + rsp_params = (struct dpseci_rsp_get_irq_enable *)cmd.params; + *en = rsp_params->enable_state; + + return 0; +} + +/** + * dpseci_set_irq_enable() - Set overall interrupt state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @en: Interrupt state - enable = 1, disable = 0 + * + * Allows GPP software to control when interrupts are generated. + * Each interrupt can have up to 32 causes. The enable/disable control's the + * overall interrupt state. If the interrupt is disabled no causes will cause + * an interrupt. + * + * Return: '0' on success, error code otherwise + */ +int dpseci_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u8 en) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_enable *cmd_params; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_ENABLE, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_enable *)cmd.params; + cmd_params->irq_index = irq_index; + cmd_params->enable_state = en; + + return mc_send_command(mc_io, &cmd); +} + +/** + * dpseci_get_irq_mask() - Get interrupt mask. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @mask: Returned event mask to trigger interrupt + * + * Every interrupt can have up to 32 causes and the interrupt model supports + * masking/unmasking each cause independently. + * + * Return: '0' on success, error code otherwise + */ +int dpseci_get_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 *mask) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_mask *cmd_params; + int err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_MASK, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_mask *)cmd.params; + cmd_params->irq_index = irq_index; + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + *mask = le32_to_cpu(cmd_params->mask); + + return 0; +} + +/** + * dpseci_set_irq_mask() - Set interrupt mask. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @mask: event mask to trigger interrupt; + * each bit: + * 0 = ignore event + * 1 = consider event for asserting IRQ + * + * Every interrupt can have up to 32 causes and the interrupt model supports + * masking/unmasking each cause independently + * + * Return: '0' on success, error code otherwise + */ +int dpseci_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 mask) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_mask *cmd_params; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_MASK, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_mask *)cmd.params; + cmd_params->mask = cpu_to_le32(mask); + cmd_params->irq_index = irq_index; + + return mc_send_command(mc_io, &cmd); +} + +/** + * dpseci_get_irq_status() - Get the current status of any pending interrupts + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @status: Returned interrupts status - one bit per cause: + * 0 = no interrupt pending + * 1 = interrupt pending + * + * Return: '0' on success, error code otherwise + */ +int dpseci_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 *status) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_status *cmd_params; + int err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_STATUS, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_status *)cmd.params; + cmd_params->status = cpu_to_le32(*status); + cmd_params->irq_index = irq_index; + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + *status = le32_to_cpu(cmd_params->status); + + return 0; +} + +/** + * dpseci_clear_irq_status() - Clear a pending interrupt's status + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @irq_index: The interrupt index to configure + * @status: bits to clear (W1C) - one bit per cause: + * 0 = don't change + * 1 = clear status bit + * + * Return: '0' on success, error code otherwise + */ +int dpseci_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 status) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_irq_status *cmd_params; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CLEAR_IRQ_STATUS, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_irq_status *)cmd.params; + cmd_params->status = cpu_to_le32(status); + cmd_params->irq_index = irq_index; + + return mc_send_command(mc_io, &cmd); +} + +/** * dpseci_get_attributes() - Retrieve DPSECI attributes * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' @@ -340,6 +612,42 @@ } /** + * dpseci_get_sec_counters() - Retrieve SEC accelerator counters + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @counters: Returned SEC counters + * + * Return: '0' on success, error code otherwise + */ +int dpseci_get_sec_counters(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpseci_sec_counters *counters) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_rsp_get_sec_counters *rsp_params; + int err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_SEC_COUNTERS, + cmd_flags, + token); + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + rsp_params = (struct dpseci_rsp_get_sec_counters *)cmd.params; + counters->dequeued_requests = + le64_to_cpu(rsp_params->dequeued_requests); + counters->ob_enc_requests = le64_to_cpu(rsp_params->ob_enc_requests); + counters->ib_dec_requests = le64_to_cpu(rsp_params->ib_dec_requests); + counters->ob_enc_bytes = le64_to_cpu(rsp_params->ob_enc_bytes); + counters->ob_prot_bytes = le64_to_cpu(rsp_params->ob_prot_bytes); + counters->ib_dec_bytes = le64_to_cpu(rsp_params->ib_dec_bytes); + counters->ib_valid_bytes = le64_to_cpu(rsp_params->ib_valid_bytes); + + return 0; +} + +/** * dpseci_get_api_version() - Get Data Path SEC Interface API version * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' @@ -367,6 +675,90 @@ return 0; } + +/** + * dpseci_set_opr() - Set Order Restoration configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @index: The queue index + * @options: Configuration mode options; can be OPR_OPT_CREATE or + * OPR_OPT_RETIRE + * @cfg: Configuration options for the OPR + * + * Return: '0' on success, error code otherwise + */ +int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, + u8 options, struct opr_cfg *cfg) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_opr *cmd_params; + + cmd.header = mc_encode_cmd_header( + DPSECI_CMDID_SET_OPR, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_opr *)cmd.params; + cmd_params->index = index; + cmd_params->options = options; + cmd_params->oloe = cfg->oloe; + cmd_params->oeane = cfg->oeane; + cmd_params->olws = cfg->olws; + cmd_params->oa = cfg->oa; + cmd_params->oprrws = cfg->oprrws; + + return mc_send_command(mc_io, &cmd); +} + +/** + * dpseci_get_opr() - Retrieve Order Restoration config and query + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @index: The queue index + * @cfg: Returned OPR configuration + * @qry: Returned OPR query + * + * Return: '0' on success, error code otherwise + */ +int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, + struct opr_cfg *cfg, struct opr_qry *qry) +{ + struct fsl_mc_command cmd = { 0 }; + struct dpseci_cmd_opr *cmd_params; + struct dpseci_rsp_get_opr *rsp_params; + int err; + + cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_OPR, + cmd_flags, + token); + cmd_params = (struct dpseci_cmd_opr *)cmd.params; + cmd_params->index = index; + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + rsp_params = (struct dpseci_rsp_get_opr *)cmd.params; + qry->rip = dpseci_get_field(rsp_params->flags, OPR_RIP); + qry->enable = dpseci_get_field(rsp_params->flags, OPR_ENABLE); + cfg->oloe = rsp_params->oloe; + cfg->oeane = rsp_params->oeane; + cfg->olws = rsp_params->olws; + cfg->oa = rsp_params->oa; + cfg->oprrws = rsp_params->oprrws; + qry->nesn = le16_to_cpu(rsp_params->nesn); + qry->ndsn = le16_to_cpu(rsp_params->ndsn); + qry->ea_tseq = le16_to_cpu(rsp_params->ea_tseq); + qry->tseq_nlis = dpseci_get_field(rsp_params->tseq_nlis, OPR_TSEQ_NLIS); + qry->ea_hseq = le16_to_cpu(rsp_params->ea_hseq); + qry->hseq_nlis = dpseci_get_field(rsp_params->hseq_nlis, OPR_HSEQ_NLIS); + qry->ea_hptr = le16_to_cpu(rsp_params->ea_hptr); + qry->ea_tptr = le16_to_cpu(rsp_params->ea_tptr); + qry->opr_vid = le16_to_cpu(rsp_params->opr_vid); + qry->opr_id = le16_to_cpu(rsp_params->opr_id); + + return 0; +} /** * dpseci_set_congestion_notification() - Set congestion group diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/dpseci_cmd.h linux-imx-phytec/drivers/crypto/caam/dpseci_cmd.h --- linux-6.1.55/drivers/crypto/caam/dpseci_cmd.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/dpseci_cmd.h 2024-06-19 12:33:59.744217258 +0200 @@ -17,6 +17,7 @@ /* Command versioning */ #define DPSECI_CMD_BASE_VERSION 1 #define DPSECI_CMD_BASE_VERSION_V2 2 +#define DPSECI_CMD_BASE_VERSION_V3 3 #define DPSECI_CMD_ID_OFFSET 4 #define DPSECI_CMD_V1(id) (((id) << DPSECI_CMD_ID_OFFSET) | \ @@ -25,9 +26,14 @@ #define DPSECI_CMD_V2(id) (((id) << DPSECI_CMD_ID_OFFSET) | \ DPSECI_CMD_BASE_VERSION_V2) +#define DPSECI_CMD_V3(id) (((id) << DPSECI_CMD_ID_OFFSET) | \ + DPSECI_CMD_BASE_VERSION_V3) + /* Command IDs */ #define DPSECI_CMDID_CLOSE DPSECI_CMD_V1(0x800) #define DPSECI_CMDID_OPEN DPSECI_CMD_V1(0x809) +#define DPSECI_CMDID_CREATE DPSECI_CMD_V3(0x909) +#define DPSECI_CMDID_DESTROY DPSECI_CMD_V1(0x989) #define DPSECI_CMDID_GET_API_VERSION DPSECI_CMD_V1(0xa09) #define DPSECI_CMDID_ENABLE DPSECI_CMD_V1(0x002) @@ -36,10 +42,20 @@ #define DPSECI_CMDID_RESET DPSECI_CMD_V1(0x005) #define DPSECI_CMDID_IS_ENABLED DPSECI_CMD_V1(0x006) +#define DPSECI_CMDID_SET_IRQ_ENABLE DPSECI_CMD_V1(0x012) +#define DPSECI_CMDID_GET_IRQ_ENABLE DPSECI_CMD_V1(0x013) +#define DPSECI_CMDID_SET_IRQ_MASK DPSECI_CMD_V1(0x014) +#define DPSECI_CMDID_GET_IRQ_MASK DPSECI_CMD_V1(0x015) +#define DPSECI_CMDID_GET_IRQ_STATUS DPSECI_CMD_V1(0x016) +#define DPSECI_CMDID_CLEAR_IRQ_STATUS DPSECI_CMD_V1(0x017) + #define DPSECI_CMDID_SET_RX_QUEUE DPSECI_CMD_V1(0x194) #define DPSECI_CMDID_GET_RX_QUEUE DPSECI_CMD_V1(0x196) #define DPSECI_CMDID_GET_TX_QUEUE DPSECI_CMD_V1(0x197) #define DPSECI_CMDID_GET_SEC_ATTR DPSECI_CMD_V2(0x198) +#define DPSECI_CMDID_GET_SEC_COUNTERS DPSECI_CMD_V1(0x199) +#define DPSECI_CMDID_SET_OPR DPSECI_CMD_V1(0x19A) +#define DPSECI_CMDID_GET_OPR DPSECI_CMD_V1(0x19B) #define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x170) #define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x171) @@ -58,6 +74,20 @@ __le32 dpseci_id; }; +struct dpseci_cmd_create { + u8 priorities[8]; + u8 num_tx_queues; + u8 num_rx_queues; + u8 pad0[6]; + __le32 options; + __le32 pad1; + u8 priorities2[8]; +}; + +struct dpseci_cmd_destroy { + __le32 object_id; +}; + #define DPSECI_ENABLE_SHIFT 0 #define DPSECI_ENABLE_SIZE 1 @@ -65,6 +95,26 @@ u8 is_enabled; }; +struct dpseci_cmd_irq_enable { + u8 enable_state; + u8 pad[3]; + u8 irq_index; +}; + +struct dpseci_rsp_get_irq_enable { + u8 enable_state; +}; + +struct dpseci_cmd_irq_mask { + __le32 mask; + u8 irq_index; +}; + +struct dpseci_cmd_irq_status { + __le32 status; + u8 irq_index; +}; + struct dpseci_rsp_get_attributes { __le32 id; __le32 pad0; @@ -126,11 +176,70 @@ u8 ptha_acc_num; }; +struct dpseci_rsp_get_sec_counters { + __le64 dequeued_requests; + __le64 ob_enc_requests; + __le64 ib_dec_requests; + __le64 ob_enc_bytes; + __le64 ob_prot_bytes; + __le64 ib_dec_bytes; + __le64 ib_valid_bytes; +}; + struct dpseci_rsp_get_api_version { __le16 major; __le16 minor; }; +struct dpseci_cmd_opr { + __le16 pad; + u8 index; + u8 options; + u8 pad1[7]; + u8 oloe; + u8 oeane; + u8 olws; + u8 oa; + u8 oprrws; +}; + +#define DPSECI_OPR_RIP_SHIFT 0 +#define DPSECI_OPR_RIP_SIZE 1 +#define DPSECI_OPR_ENABLE_SHIFT 1 +#define DPSECI_OPR_ENABLE_SIZE 1 +#define DPSECI_OPR_TSEQ_NLIS_SHIFT 0 +#define DPSECI_OPR_TSEQ_NLIS_SIZE 1 +#define DPSECI_OPR_HSEQ_NLIS_SHIFT 0 +#define DPSECI_OPR_HSEQ_NLIS_SIZE 1 + +struct dpseci_rsp_get_opr { + __le64 pad; + u8 flags; + u8 pad0[2]; + u8 oloe; + u8 oeane; + u8 olws; + u8 oa; + u8 oprrws; + __le16 nesn; + __le16 pad1; + __le16 ndsn; + __le16 pad2; + __le16 ea_tseq; + u8 tseq_nlis; + u8 pad3; + __le16 ea_hseq; + u8 hseq_nlis; + u8 pad4; + __le16 ea_hptr; + __le16 pad5; + __le16 ea_tptr; + __le16 pad6; + __le16 opr_vid; + __le16 pad7; + __le16 opr_id; +}; + #define DPSECI_CGN_DEST_TYPE_SHIFT 0 #define DPSECI_CGN_DEST_TYPE_SIZE 4 #define DPSECI_CGN_UNITS_SHIFT 4 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/dpseci.h linux-imx-phytec/drivers/crypto/caam/dpseci.h --- linux-6.1.55/drivers/crypto/caam/dpseci.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/dpseci.h 2024-06-19 12:33:59.744217258 +0200 @@ -12,6 +12,8 @@ */ struct fsl_mc_io; +struct opr_cfg; +struct opr_qry; /** * General DPSECI macros @@ -38,9 +40,21 @@ #define DPSECI_OPT_HAS_CG 0x000020 /** + * Enable the Order Restoration support + */ +#define DPSECI_OPT_HAS_OPR 0x000040 + +/** + * Order Point Records are shared for the entire DPSECI + */ +#define DPSECI_OPT_OPR_SHARED 0x000080 + +/** * struct dpseci_cfg - Structure representing DPSECI configuration - * @options: Any combination of the following flags: + * @options: Any combination of the following options: * DPSECI_OPT_HAS_CG + * DPSECI_OPT_HAS_OPR + * DPSECI_OPT_OPR_SHARED * @num_tx_queues: num of queues towards the SEC * @num_rx_queues: num of queues back from the SEC * @priorities: Priorities for the SEC hardware processing; @@ -55,6 +69,12 @@ u8 priorities[DPSECI_MAX_QUEUE_NUM]; }; +int dpseci_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpseci_cfg *cfg, u32 *obj_id); + +int dpseci_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id); + int dpseci_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); int dpseci_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); @@ -64,13 +84,33 @@ int dpseci_is_enabled(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, int *en); +int dpseci_get_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u8 *en); + +int dpseci_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u8 en); + +int dpseci_get_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 *mask); + +int dpseci_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 mask); + +int dpseci_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 *status); + +int dpseci_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 irq_index, u32 status); + /** * struct dpseci_attr - Structure representing DPSECI attributes * @id: DPSECI object ID * @num_tx_queues: number of queues towards the SEC * @num_rx_queues: number of queues back from the SEC - * @options: any combination of the following flags: + * @options: any combination of the following options: * DPSECI_OPT_HAS_CG + * DPSECI_OPT_HAS_OPR + * DPSECI_OPT_OPR_SHARED */ struct dpseci_attr { int id; @@ -250,9 +290,39 @@ int dpseci_get_sec_attr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpseci_sec_attr *attr); +/** + * struct dpseci_sec_counters - Structure representing global SEC counters and + * not per dpseci counters + * @dequeued_requests: Number of Requests Dequeued + * @ob_enc_requests: Number of Outbound Encrypt Requests + * @ib_dec_requests: Number of Inbound Decrypt Requests + * @ob_enc_bytes: Number of Outbound Bytes Encrypted + * @ob_prot_bytes: Number of Outbound Bytes Protected + * @ib_dec_bytes: Number of Inbound Bytes Decrypted + * @ib_valid_bytes: Number of Inbound Bytes Validated + */ +struct dpseci_sec_counters { + u64 dequeued_requests; + u64 ob_enc_requests; + u64 ib_dec_requests; + u64 ob_enc_bytes; + u64 ob_prot_bytes; + u64 ib_dec_bytes; + u64 ib_valid_bytes; +}; + +int dpseci_get_sec_counters(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpseci_sec_counters *counters); + int dpseci_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 *major_ver, u16 *minor_ver); +int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, + u8 options, struct opr_cfg *cfg); + +int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index, + struct opr_cfg *cfg, struct opr_qry *qry); + /** * enum dpseci_congestion_unit - DPSECI congestion units * @DPSECI_CONGESTION_UNIT_BYTES: bytes units diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/fsl_jr_uio.c linux-imx-phytec/drivers/crypto/caam/fsl_jr_uio.c --- linux-6.1.55/drivers/crypto/caam/fsl_jr_uio.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/fsl_jr_uio.c 2024-06-19 12:33:59.744217258 +0200 @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "regs.h" +#include "fsl_jr_uio.h" + +static const char jr_uio_version[] = "fsl JR UIO driver v1.0"; + +#define NAME_LENGTH 30 +#define JR_INDEX_OFFSET 12 + +static const char uio_device_name[] = "fsl-jr"; +static LIST_HEAD(jr_list); + +struct jr_uio_info { + atomic_t ref; /* exclusive, only one open() at a time */ + struct uio_info uio; + char name[NAME_LENGTH]; +}; + +struct jr_dev { + u32 revision; + u32 index; + u32 irq; + struct caam_job_ring __iomem *global_regs; + struct device *dev; + struct resource *res; + struct jr_uio_info info; + struct list_head node; + struct list_head jr_list; +}; + +static int jr_uio_open(struct uio_info *info, struct inode *inode) +{ + struct jr_uio_info *uio_info = container_of(info, + struct jr_uio_info, uio); + + if (!atomic_dec_and_test(&uio_info->ref)) { + pr_err("%s: failing non-exclusive open()\n", uio_info->name); + atomic_inc(&uio_info->ref); + return -EBUSY; + } + + return 0; +} + +static int jr_uio_release(struct uio_info *info, struct inode *inode) +{ + struct jr_uio_info *uio_info = container_of(info, + struct jr_uio_info, uio); + atomic_inc(&uio_info->ref); + + return 0; +} + +static irqreturn_t jr_uio_irq_handler(int irq, struct uio_info *dev_info) +{ + struct jr_dev *jrdev = dev_info->priv; + u32 irqstate; + + irqstate = rd_reg32(&jrdev->global_regs->jrintstatus); + + if (!irqstate) + return IRQ_NONE; + + if (irqstate & JRINT_JR_ERROR) + dev_info(jrdev->dev, "uio job ring error - irqstate: %08x\n", + irqstate); + + /*mask valid interrupts */ + clrsetbits_32(&jrdev->global_regs->rconfig_lo, 0, JRCFG_IMSK); + + /* Have valid interrupt at this point, just ACK and trigger */ + wr_reg32(&jrdev->global_regs->jrintstatus, irqstate); + + return IRQ_HANDLED; +} + +static int jr_uio_irqcontrol(struct uio_info *dev_info, int irqon) +{ + struct jr_dev *jrdev = dev_info->priv; + + switch (irqon) { + case SEC_UIO_SIMULATE_IRQ_CMD: + uio_event_notify(dev_info); + break; + case SEC_UIO_ENABLE_IRQ_CMD: + /* Enable Job Ring interrupt */ + clrsetbits_32(&jrdev->global_regs->rconfig_lo, JRCFG_IMSK, 0); + break; + case SEC_UIO_DISABLE_IRQ_CMD: + /* Disable Job Ring interrupt */ + clrsetbits_32(&jrdev->global_regs->rconfig_lo, 0, JRCFG_IMSK); + break; + default: + break; + } + return 0; +} + +static int __init jr_uio_init(struct jr_dev *uio_dev) +{ + int ret; + struct jr_uio_info *info; + + info = &uio_dev->info; + atomic_set(&info->ref, 1); + info->uio.version = jr_uio_version; + info->uio.name = uio_dev->info.name; + info->uio.mem[0].name = "JR config space"; + info->uio.mem[0].addr = uio_dev->res->start; + info->uio.mem[0].size = resource_size(uio_dev->res); + info->uio.mem[0].internal_addr = uio_dev->global_regs; + info->uio.mem[0].memtype = UIO_MEM_PHYS; + info->uio.irq = uio_dev->irq; + info->uio.irq_flags = IRQF_SHARED; + info->uio.handler = jr_uio_irq_handler; + info->uio.irqcontrol = jr_uio_irqcontrol; + info->uio.open = jr_uio_open; + info->uio.release = jr_uio_release; + info->uio.priv = uio_dev; + + ret = uio_register_device(uio_dev->dev, &info->uio); + if (ret) { + dev_err(uio_dev->dev, "jr_uio: UIO registration failed\n"); + return ret; + } + + return 0; +} + +static const struct of_device_id jr_ids[] = { + { .compatible = "fsl,sec-v4.0-job-ring", }, + { .compatible = "fsl,sec-v4.4-job-ring", }, + { .compatible = "fsl,sec-v5.0-job-ring", }, + { .compatible = "fsl,sec-v6.0-job-ring", }, + {}, +}; + +static int fsl_jr_probe(struct platform_device *dev) +{ + struct jr_dev *jr_dev; + struct device_node *jr_node; + int ret, count = 0; + struct list_head *p; + + jr_node = dev->dev.of_node; + if (!jr_node) { + dev_err(&dev->dev, "Device OF-Node is NULL\n"); + return -EFAULT; + } + + jr_dev = devm_kzalloc(&dev->dev, sizeof(*jr_dev), GFP_KERNEL); + if (!jr_dev) + return -ENOMEM; + + /* Creat name and index */ + list_for_each(p, &jr_list) { + count++; + } + jr_dev->index = count; + + snprintf(jr_dev->info.name, sizeof(jr_dev->info.name) - 1, + "%s%d", uio_device_name, jr_dev->index); + + jr_dev->dev = &dev->dev; + platform_set_drvdata(dev, jr_dev); + + jr_dev->res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (unlikely(!jr_dev->res)) { + dev_err(jr_dev->dev, "platform_get_resource() failed\n"); + ret = -ENOMEM; + goto abort; + } + + jr_dev->global_regs = + devm_ioremap(&dev->dev, jr_dev->res->start, + resource_size(jr_dev->res)); + if (unlikely(jr_dev->global_regs == 0)) { + dev_err(jr_dev->dev, "devm_ioremap failed\n"); + ret = -EIO; + goto abort; + } + jr_dev->irq = irq_of_parse_and_map(jr_node, 0); + dev_dbg(jr_dev->dev, "errirq: %d\n", jr_dev->irq); + + /* Register UIO */ + ret = jr_uio_init(jr_dev); + if (ret) { + dev_err(&dev->dev, "UIO init Failed\n"); + goto abort; + } + + list_add_tail(&jr_dev->node, &jr_list); + + dev_info(jr_dev->dev, "UIO device full name %s initialized\n", + jr_dev->info.name); + + return 0; + +abort: + return ret; +} + +static int fsl_jr_remove(struct platform_device *dev) +{ + struct jr_dev *jr_dev = platform_get_drvdata(dev); + + if (!jr_dev) + return 0; + + list_del(&jr_dev->node); + uio_unregister_device(&jr_dev->info.uio); + + return 0; +} + +MODULE_DEVICE_TABLE(of, jr_ids); + +static struct platform_driver fsl_jr_driver = { + .driver = { + .name = "fsl-jr-uio", + .of_match_table = jr_ids, + }, + .probe = fsl_jr_probe, + .remove = fsl_jr_remove, +}; + +module_platform_driver(fsl_jr_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("FSL SEC UIO Driver"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/fsl_jr_uio.h linux-imx-phytec/drivers/crypto/caam/fsl_jr_uio.h --- linux-6.1.55/drivers/crypto/caam/fsl_jr_uio.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/fsl_jr_uio.h 2024-06-19 12:33:59.744217258 +0200 @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * CAAM Job RING UIO support header file + * + * Copyright 2013 Freescale Semiconductor, Inc + * Copyright 2018 NXP + */ + +#ifndef FSL_JR_UIO_H +#define FSL_JR_UIO_H + +/** UIO command used by user-space driver to request + * disabling IRQs on a certain job ring + */ +#define SEC_UIO_DISABLE_IRQ_CMD 0 +/** UIO command used by user-space driver to request + * enabling IRQs on a certain job ring + */ +#define SEC_UIO_ENABLE_IRQ_CMD 1 +/** UIO command used by user-space driver to request SEC kernel driver + * to simulate that an IRQ is generated on a certain job ring + */ +#define SEC_UIO_SIMULATE_IRQ_CMD 2 + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/intern.h linux-imx-phytec/drivers/crypto/caam/intern.h --- linux-6.1.55/drivers/crypto/caam/intern.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/intern.h 2024-06-19 12:33:59.744217258 +0200 @@ -47,6 +47,18 @@ u32 desc_size; /* Stored size for postprocessing, header derived */ }; +#ifdef CONFIG_PM_SLEEP +struct caam_jr_state { + dma_addr_t inpbusaddr; + dma_addr_t outbusaddr; +}; +#endif + +struct caam_jr_dequeue_params { + struct device *dev; + int enable_itr; +}; + /* Private sub-storage for a single JobR */ struct caam_drv_private_jr { struct list_head list_node; /* Job Ring device list */ @@ -54,6 +66,7 @@ int ridx; struct caam_job_ring __iomem *rregs; /* JobR's register space */ struct tasklet_struct irqtask; + struct caam_jr_dequeue_params tasklet_params; int irq; /* One per queue */ bool hwrng; @@ -71,18 +84,35 @@ int tail; /* entinfo (s/w ring) tail index */ void *outring; /* Base of output ring, DMA-safe */ struct crypto_engine *engine; + +#ifdef CONFIG_PM_SLEEP + struct caam_jr_state state; /* State of the JR during PM */ +#endif }; +#ifdef CONFIG_PM_SLEEP +struct caam_ctl_state { + struct masterid deco_mid[16]; + struct masterid jr_mid[4]; + u32 mcr; + u32 scfgr; +}; +#endif + /* * Driver-private storage for a single CAAM block instance */ struct caam_drv_private { + struct device *smdev; + /* Physical-presence section */ struct caam_ctrl __iomem *ctrl; /* controller region */ struct caam_deco __iomem *deco; /* DECO/CCB views */ struct caam_assurance __iomem *assure; struct caam_queue_if __iomem *qi; /* QI control region */ struct caam_job_ring __iomem *jr[4]; /* JobR's register space */ + dma_addr_t __iomem *sm_base; /* Secure memory storage base */ + phys_addr_t sm_phy; /* Secure memory storage physical */ struct iommu_domain *domain; @@ -93,8 +123,11 @@ u8 total_jobrs; /* Total Job Rings in device */ u8 qi_present; /* Nonzero if QI present in device */ u8 blob_present; /* Nonzero if BLOB support present in device */ + u8 sm_present; /* Nonzero if Secure Memory is supported */ u8 mc_en; /* Nonzero if MC f/w is active */ - int secvio_irq; /* Security violation interrupt number */ + u8 scu_en; /* Nonzero if SCU f/w is active */ + u8 optee_en; /* Nonzero if OP-TEE f/w is active */ + bool pr_support; /* RNG prediction resistance available */ int virt_en; /* Virtualization enabled in CAAM */ int era; /* CAAM Era (internal HW revision) */ @@ -114,6 +147,11 @@ struct dentry *ctl; /* controller dir */ struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap; #endif + +#ifdef CONFIG_PM_SLEEP + int caam_off_during_pm; /* If the CAAM is reset after suspend */ + struct caam_ctl_state state; /* State of the CTL during PM */ +#endif }; #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API @@ -219,6 +257,42 @@ #endif /* CONFIG_CAAM_QI */ +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_SM + +int caam_sm_startup(struct device *dev); +void caam_sm_shutdown(struct device *dev); + +#else + +static inline int caam_sm_startup(struct device *dev) +{ + return 0; +} + +static inline void caam_sm_shutdown(struct device *dev) +{ +} + +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_SM */ + +#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API + +int caam_keygen_init(void); +void caam_keygen_exit(void); + +#else + +static inline int caam_keygen_init(void) +{ + return 0; +} + +static inline void caam_keygen_exit(void) +{ +} + +#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API */ + static inline u64 caam_get_dma_mask(struct device *dev) { struct device_node *nprop = dev->of_node; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/jr.c linux-imx-phytec/drivers/crypto/caam/jr.c --- linux-6.1.55/drivers/crypto/caam/jr.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/jr.c 2024-06-19 12:33:59.744217258 +0200 @@ -4,7 +4,7 @@ * JobR backend functionality * * Copyright 2008-2012 Freescale Semiconductor, Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ #include @@ -27,8 +27,40 @@ static DEFINE_MUTEX(algs_lock); static unsigned int active_devs; -static void register_algs(struct caam_drv_private_jr *jrpriv, - struct device *dev) +static void init_misc_func(struct caam_drv_private_jr *jrpriv, + struct device *dev) +{ + mutex_lock(&algs_lock); + + if (active_devs != 1) + goto algs_unlock; + + jrpriv->hwrng = !caam_rng_init(dev); + caam_sm_startup(dev); + caam_keygen_init(); + +algs_unlock: + mutex_unlock(&algs_lock); +} + +static void exit_misc_func(struct caam_drv_private_jr *jrpriv, + struct device *dev) +{ + mutex_lock(&algs_lock); + + if (active_devs != 1) + goto algs_unlock; + + caam_keygen_exit(); + caam_sm_shutdown(dev); + if (jrpriv->hwrng) + caam_rng_exit(dev); + +algs_unlock: + mutex_unlock(&algs_lock); +} + +static void register_algs(struct device *dev) { mutex_lock(&algs_lock); @@ -38,7 +70,6 @@ caam_algapi_init(dev); caam_algapi_hash_init(dev); caam_pkc_init(dev); - jrpriv->hwrng = !caam_rng_init(dev); caam_prng_register(dev); caam_qi_algapi_init(dev); @@ -46,7 +77,7 @@ mutex_unlock(&algs_lock); } -static void unregister_algs(void) +static void unregister_algs(struct device *dev) { mutex_lock(&algs_lock); @@ -63,6 +94,14 @@ mutex_unlock(&algs_lock); } +static int jr_driver_probed; + +int caam_jr_driver_probed(void) +{ + return jr_driver_probed; +} +EXPORT_SYMBOL(caam_jr_driver_probed); + static void caam_jr_crypto_engine_exit(void *data) { struct device *jrdev = data; @@ -72,19 +111,27 @@ crypto_engine_exit(jrpriv->engine); } -static int caam_reset_hw_jr(struct device *dev) +/* + * Put the CAAM in quiesce, ie stop + * + * Must be called with itr disabled + */ +static int caam_jr_stop_processing(struct device *dev, u32 jrcr_bits) { struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); unsigned int timeout = 100000; - /* - * mask interrupts since we are going to poll - * for reset completion status - */ - clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JRCFG_IMSK); + /* Check the current status */ + if (rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_INPROGRESS) + goto wait_quiesce_completion; - /* initiate flush (required prior to reset) */ - wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); + /* Reset the field */ + clrsetbits_32(&jrp->rregs->jrintstatus, JRINT_ERR_HALT_MASK, 0); + + /* initiate flush / park (required prior to reset) */ + wr_reg32(&jrp->rregs->jrcommand, jrcr_bits); + +wait_quiesce_completion: while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) == JRINT_ERR_HALT_INPROGRESS) && --timeout) cpu_relax(); @@ -95,8 +142,56 @@ return -EIO; } + return 0; +} + +/* + * Flush the job ring, so the jobs running will be stopped, jobs queued will be + * invalidated and the CAAM will no longer fetch fron input ring. + * + * Must be called with itr disabled + */ +static int caam_jr_flush(struct device *dev) +{ + return caam_jr_stop_processing(dev, JRCR_RESET); +} + +#ifdef CONFIG_PM_SLEEP +/* The resume can be used after a park or a flush if CAAM has not been reset */ +static int caam_jr_restart_processing(struct device *dev) +{ + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); + u32 halt_status = rd_reg32(&jrp->rregs->jrintstatus) & + JRINT_ERR_HALT_MASK; + + /* Check that the flush/park is completed */ + if (halt_status != JRINT_ERR_HALT_COMPLETE) + return -1; + + /* Resume processing of jobs */ + clrsetbits_32(&jrp->rregs->jrintstatus, 0, JRINT_ERR_HALT_COMPLETE); + + return 0; +} +#endif /* CONFIG_PM_SLEEP */ + +static int caam_reset_hw_jr(struct device *dev) +{ + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); + unsigned int timeout = 100000; + int err; + + /* + * mask interrupts since we are going to poll + * for reset completion status + */ + clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JRCFG_IMSK); + + err = caam_jr_flush(dev); + if (err) + return err; + /* initiate reset */ - timeout = 100000; wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout) cpu_relax(); @@ -136,8 +231,7 @@ jrdev = &pdev->dev; jrpriv = dev_get_drvdata(jrdev); - if (jrpriv->hwrng) - caam_rng_exit(jrdev->parent); + exit_misc_func(jrpriv, jrdev->parent); /* * Return EBUSY if job ring already allocated. @@ -148,7 +242,7 @@ } /* Unregister JR-based RNG & crypto algorithms */ - unregister_algs(); + unregister_algs(jrdev->parent); /* Remove the node from Physical JobR list maintained by driver */ spin_lock(&driver_data.jr_alloc_lock); @@ -160,6 +254,8 @@ if (ret) dev_err(jrdev, "Failed to shut down job ring\n"); + jr_driver_probed--; + return ret; } @@ -175,7 +271,7 @@ * tasklet if jobs done. */ irqstate = rd_reg32(&jrp->rregs->jrintstatus); - if (!irqstate) + if (!(irqstate & JRINT_JR_INT)) return IRQ_NONE; /* @@ -205,7 +301,8 @@ static void caam_jr_dequeue(unsigned long devarg) { int hw_idx, sw_idx, i, head, tail; - struct device *dev = (struct device *)devarg; + struct caam_jr_dequeue_params *params = (void *)devarg; + struct device *dev = params->dev; struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); void (*usercall)(struct device *dev, u32 *desc, u32 status, void *arg); u32 *userdesc, userstatus; @@ -279,8 +376,9 @@ outring_used--; } - /* reenable / unmask IRQs */ - clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0); + if (params->enable_itr) + /* reenable / unmask IRQs */ + clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0); } /** @@ -324,6 +422,36 @@ EXPORT_SYMBOL(caam_jr_alloc); /** + * caam_jridx_alloc() - Alloc a specific job ring based on its index. + * + * returns : pointer to the newly allocated physical + * JobR dev can be written to if successful. + **/ +struct device *caam_jridx_alloc(int idx) +{ + struct caam_drv_private_jr *jrpriv; + struct device *dev = ERR_PTR(-ENODEV); + + spin_lock(&driver_data.jr_alloc_lock); + + if (list_empty(&driver_data.jr_list)) + goto end; + + list_for_each_entry(jrpriv, &driver_data.jr_list, list_node) { + if (jrpriv->ridx == idx) { + atomic_inc(&jrpriv->tfm_count); + dev = jrpriv->dev; + break; + } + } + +end: + spin_unlock(&driver_data.jr_alloc_lock); + return dev; +} +EXPORT_SYMBOL(caam_jridx_alloc); + +/** * caam_jr_free() - Free the Job Ring * @rdev: points to the dev that identifies the Job ring to * be released. @@ -405,8 +533,16 @@ * Guarantee that the descriptor's DMA address has been written to * the next slot in the ring before the write index is updated, since * other cores may update this index independently. + * + * Under heavy DDR load, smp_wmb() or dma_wmb() fail to make the input + * ring be updated before the CAAM starts reading it. So, CAAM will + * process, again, an old descriptor address and will put it in the + * output ring. This will make caam_jr_dequeue() to fail, since this + * old descriptor is not in the software ring. + * To fix this, use wmb() which works on the full system instead of + * inner/outer shareable domains. */ - smp_wmb(); + wmb(); jrp->head = (head + 1) & (JOBR_DEPTH - 1); @@ -430,6 +566,80 @@ } EXPORT_SYMBOL(caam_jr_enqueue); +/** + * caam_jr_run_and_wait_for_completion() - Enqueue a job and wait for its + * completion. Returns 0 if OK, -ENOSPC if the queue is full, + * -EIO if it cannot map the caller's descriptor. + * @dev: struct device of the job ring to be used + * @desc: points to a job descriptor that execute our request. All + * descriptors (and all referenced data) must be in a DMAable + * region, and all data references must be physical addresses + * accessible to CAAM (i.e. within a PAMU window granted + * to it). + * @cbk: pointer to a callback function to be invoked upon completion + * of this request. This has the form: + * callback(struct device *dev, u32 *desc, u32 stat, void *arg) + * where: + * @dev: contains the job ring device that processed this + * response. + * @desc: descriptor that initiated the request, same as + * "desc" being argued to caam_jr_enqueue(). + * @status: untranslated status received from CAAM. See the + * reference manual for a detailed description of + * error meaning, or see the JRSTA definitions in the + * register header file + * @areq: optional pointer to an argument passed with the + * original request + **/ +int caam_jr_run_and_wait_for_completion(struct device *dev, u32 *desc, + void (*cbk)(struct device *dev, + u32 *desc, u32 status, + void *areq)) +{ + int ret = 0; + struct jr_job_result jobres = {0}; + + /* Initialize the completion structure */ + init_completion(&jobres.completion); + + /* Enqueue job for execution */ + ret = caam_jr_enqueue(dev, desc, cbk, &jobres); + if (ret != -EINPROGRESS) + return ret; + + /* Wait for job completion */ + wait_for_completion(&jobres.completion); + + /* Get return code processed in cbk */ + ret = jobres.error; + + return ret; +} +EXPORT_SYMBOL(caam_jr_run_and_wait_for_completion); + +static void caam_jr_init_hw(struct device *dev, dma_addr_t inpbusaddr, + dma_addr_t outbusaddr) +{ + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); + + wr_reg64(&jrp->rregs->inpring_base, inpbusaddr); + wr_reg64(&jrp->rregs->outring_base, outbusaddr); + wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH); + wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH); + + /* Select interrupt coalescing parameters */ + clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JOBR_INTC | + (JOBR_INTC_COUNT_THLD << JRCFG_ICDCT_SHIFT) | + (JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT)); +} + +static void caam_jr_reset_index(struct caam_drv_private_jr *jrp) +{ + jrp->out_ring_read_index = 0; + jrp->head = 0; + jrp->tail = 0; +} + /* * Init JobR independent of platform property detection */ @@ -466,25 +676,16 @@ jrp->entinfo[i].desc_addr_dma = !0; /* Setup rings */ - jrp->out_ring_read_index = 0; - jrp->head = 0; - jrp->tail = 0; - - wr_reg64(&jrp->rregs->inpring_base, inpbusaddr); - wr_reg64(&jrp->rregs->outring_base, outbusaddr); - wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH); - wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH); - + caam_jr_reset_index(jrp); jrp->inpring_avail = JOBR_DEPTH; + caam_jr_init_hw(dev, inpbusaddr, outbusaddr); spin_lock_init(&jrp->inplock); - /* Select interrupt coalescing parameters */ - clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JOBR_INTC | - (JOBR_INTC_COUNT_THLD << JRCFG_ICDCT_SHIFT) | - (JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT)); - - tasklet_init(&jrp->irqtask, caam_jr_dequeue, (unsigned long)dev); + jrp->tasklet_params.dev = dev; + jrp->tasklet_params.enable_itr = 1; + tasklet_init(&jrp->irqtask, caam_jr_dequeue, + (unsigned long)&jrp->tasklet_params); /* Connect job ring interrupt handler. */ error = devm_request_irq(dev, jrp->irq, caam_jr_interrupt, IRQF_SHARED, @@ -595,11 +796,138 @@ atomic_set(&jrpriv->tfm_count, 0); - register_algs(jrpriv, jrdev->parent); + device_init_wakeup(&pdev->dev, 1); + device_set_wakeup_enable(&pdev->dev, false); + + register_algs(jrdev->parent); + init_misc_func(jrpriv, jrdev->parent); + jr_driver_probed++; + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static void caam_jr_get_hw_state(struct device *dev) +{ + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); + + jrp->state.inpbusaddr = rd_reg64(&jrp->rregs->inpring_base); + jrp->state.outbusaddr = rd_reg64(&jrp->rregs->outring_base); +} + +static int caam_jr_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev); + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev->parent); + struct caam_jr_dequeue_params suspend_params = { + .dev = dev, + .enable_itr = 0, + }; + + /* Remove the node from Physical JobR list maintained by driver */ + spin_lock(&driver_data.jr_alloc_lock); + list_del(&jrpriv->list_node); + spin_unlock(&driver_data.jr_alloc_lock); + + if (jrpriv->hwrng) + caam_rng_exit(dev->parent); + + if (ctrlpriv->caam_off_during_pm) { + int err; + + tasklet_disable(&jrpriv->irqtask); + + /* mask itr to call flush */ + clrsetbits_32(&jrpriv->rregs->rconfig_lo, 0, JRCFG_IMSK); + + /* Invalid job in process */ + err = caam_jr_flush(dev); + if (err) { + dev_err(dev, "Failed to flush\n"); + return err; + } + + /* Dequeing jobs flushed */ + caam_jr_dequeue((unsigned long)&suspend_params); + + /* Save state */ + caam_jr_get_hw_state(dev); + } else if (device_may_wakeup(&pdev->dev)) { + enable_irq_wake(jrpriv->irq); + } + + return 0; +} + +static int caam_jr_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev); + struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev->parent); + + if (ctrlpriv->caam_off_during_pm) { + u64 inp_addr; + int err; + + /* + * Check if the CAAM has been resetted checking the address of + * the input ring + */ + inp_addr = rd_reg64(&jrpriv->rregs->inpring_base); + if (inp_addr != 0) { + /* JR still has some configuration */ + if (inp_addr == jrpriv->state.inpbusaddr) { + /* JR has not been resetted */ + err = caam_jr_restart_processing(dev); + if (err) { + dev_err(dev, + "Restart processing failed\n"); + return err; + } + + tasklet_enable(&jrpriv->irqtask); + + clrsetbits_32(&jrpriv->rregs->rconfig_lo, + JRCFG_IMSK, 0); + + goto add_jr; + } else if (ctrlpriv->optee_en) { + /* JR has been used by OPTEE, reset it */ + err = caam_reset_hw_jr(dev); + if (err) { + dev_err(dev, "Failed to reset JR\n"); + return err; + } + } else { + /* No explanation, return error */ + return -EIO; + } + } + + caam_jr_reset_index(jrpriv); + caam_jr_init_hw(dev, jrpriv->state.inpbusaddr, + jrpriv->state.outbusaddr); + + tasklet_enable(&jrpriv->irqtask); + } else if (device_may_wakeup(&pdev->dev)) { + disable_irq_wake(jrpriv->irq); + } + +add_jr: + spin_lock(&driver_data.jr_alloc_lock); + list_add_tail(&jrpriv->list_node, &driver_data.jr_list); + spin_unlock(&driver_data.jr_alloc_lock); + + if (jrpriv->hwrng) + jrpriv->hwrng = !caam_rng_init(dev->parent); return 0; } +SIMPLE_DEV_PM_OPS(caam_jr_pm_ops, caam_jr_suspend, caam_jr_resume); +#endif /* CONFIG_PM_SLEEP */ + static const struct of_device_id caam_jr_match[] = { { .compatible = "fsl,sec-v4.0-job-ring", @@ -615,6 +943,9 @@ .driver = { .name = "caam_jr", .of_match_table = caam_jr_match, +#ifdef CONFIG_PM_SLEEP + .pm = &caam_jr_pm_ops, +#endif }, .probe = caam_jr_probe, .remove = caam_jr_remove, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/jr.h linux-imx-phytec/drivers/crypto/caam/jr.h --- linux-6.1.55/drivers/crypto/caam/jr.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/jr.h 2024-06-19 12:33:59.744217258 +0200 @@ -3,17 +3,38 @@ * CAAM public-level include definitions for the JobR backend * * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #ifndef JR_H #define JR_H +#include + + /** + * struct jr_job_result - Job Ring result structure, used for requests + * that need to run and wait for their completion + * + * @error : The result returned after request was executed + * @completion : Structure used to maintain state for a "completion" + */ +struct jr_job_result { + int error; + struct completion completion; +}; + /* Prototypes for backend-level services exposed to APIs */ +int caam_jr_driver_probed(void); struct device *caam_jr_alloc(void); +struct device *caam_jridx_alloc(int idx); void caam_jr_free(struct device *rdev); int caam_jr_enqueue(struct device *dev, u32 *desc, void (*cbk)(struct device *dev, u32 *desc, u32 status, void *areq), void *areq); +int caam_jr_run_and_wait_for_completion(struct device *dev, u32 *desc, + void (*cbk)(struct device *dev, + u32 *desc, u32 status, + void *areq)); #endif /* JR_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/Kconfig linux-imx-phytec/drivers/crypto/caam/Kconfig --- linux-6.1.55/drivers/crypto/caam/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/Kconfig 2024-06-19 12:33:59.736217122 +0200 @@ -8,6 +8,17 @@ config CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC tristate +config CRYPTO_DEV_FSL_CAAM_KEYBLOB_API_DESC + tristate + +config CRYPTO_DEV_FSL_CAAM_SECVIO + tristate "CAAM/SNVS Security Violation Handler" + depends on ARCH_MXC + help + Enables installation of an interrupt handler with registrable + handler functions which can be specified to act on the consequences + of a security violation. + config CRYPTO_DEV_FSL_CAAM tristate "Freescale CAAM-Multicore platform driver backend" depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE @@ -109,7 +120,7 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI bool "Queue Interface as Crypto API backend" - depends on FSL_DPAA && NET + depends on FSL_SDK_DPA && NET default y select CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC select CRYPTO_AUTHENC @@ -162,6 +173,79 @@ config CRYPTO_DEV_FSL_CAAM_BLOB_GEN bool +config CRYPTO_DEV_FSL_CAAM_TK_API + bool "Register tagged key cryptography implementations with Crypto API" + default y + select CRYPTO_DEV_FSL_CAAM_CRYPTO_API + select CRYPTO_DEV_FSL_CAAM_KEYBLOB_API_DESC + help + Selecting this will register algorithms supporting tagged key and + generate black keys and encapsulate them into black blobs. + + Tagged keys are black keys that contain metadata indicating what + they are and how to handle them. + CAAM protects data in a data structure called a Blob, which provides + both confidentiality and integrity protection. + +config CRYPTO_DEV_FSL_CAAM_TK_API_TEST + tristate "CAAM keys and blobs test" + depends on CRYPTO_DEV_FSL_CAAM_TK_API + depends on m + help + Test to exercise black key generation and blob encapsulation and + decapsulation. + +config CRYPTO_DEV_FSL_CAAM_RNG_TEST + bool "Test caam rng" + depends on CRYPTO_DEV_FSL_CAAM_RNG_API + help + Selecting this will enable a self-test to run for the + caam RNG. This test is several minutes long and executes + just before the RNG is registered with the hw_random API. + +config CRYPTO_DEV_FSL_CAAM_SM + bool "CAAM Secure Memory / Keystore API" + default y + help + Enables use of a prototype kernel-level Keystore API with CAAM + Secure Memory for insertion/extraction of bus-protected secrets. + +config CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE + int "Size of each keystore slot in Secure Memory" + depends on CRYPTO_DEV_FSL_CAAM_SM + range 5 9 + default 7 + help + Select size of allocation units to divide Secure Memory pages into + (the size of a "slot" as referenced inside the API code). + Established as powers of two. + Examples: + 5 => 32 bytes + 6 => 64 bytes + 7 => 128 bytes + 8 => 256 bytes + 9 => 512 bytes + +config CRYPTO_DEV_FSL_CAAM_SM_TEST + tristate "CAAM Secure Memory - Keystore Test/Example" + depends on CRYPTO_DEV_FSL_CAAM_SM + depends on m + help + Example thread to exercise the Keystore API and to verify that + stored and recovered secrets can be used for general purpose + encryption/decryption. + +config CRYPTO_DEV_FSL_CAAM_JR_UIO + tristate "Freescale Job Ring UIO support" + depends on UIO + default m + help + Selecting this will allow job ring UIO support for + Userspace drivers + + To compile this as a module, choose M here: the module + will be called fsl_jr_uio. + endif # CRYPTO_DEV_FSL_CAAM_JR endif # CRYPTO_DEV_FSL_CAAM diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/Makefile linux-imx-phytec/drivers/crypto/caam/Makefile --- linux-6.1.55/drivers/crypto/caam/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/Makefile 2024-06-19 12:33:59.736217122 +0200 @@ -13,9 +13,12 @@ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC) += caamalg_desc.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC) += caamhash_desc.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_KEYBLOB_API_DESC) += caamkeyblob_desc.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR_UIO) += fsl_jr_uio.o caam-y := ctrl.o caam_jr-y := jr.o key_gen.o +caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API) += tag_object.o caamkeyblob.o caamkeygen.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o @@ -23,6 +26,10 @@ caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API) += caamprng.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caampkc.o pkc_desc.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_BLOB_GEN) += blob_gen.o +caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM) += sm_store.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST) += sm_test.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO) += secvio.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_TK_API_TEST) += caamkeyblob_test.o caam-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += qi.o ifneq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI),) diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/qi.c linux-imx-phytec/drivers/crypto/caam/qi.c --- linux-6.1.55/drivers/crypto/caam/qi.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/qi.c 2024-06-19 12:33:59.744217258 +0200 @@ -9,7 +9,7 @@ #include #include -#include +#include #include "debugfs.h" #include "regs.h" @@ -99,23 +99,21 @@ int caam_qi_enqueue(struct device *qidev, struct caam_drv_req *req) { struct qm_fd fd; - dma_addr_t addr; int ret; int num_retries = 0; - qm_fd_clear_fd(&fd); - qm_fd_set_compound(&fd, qm_sg_entry_get_len(&req->fd_sgt[1])); - - addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt), + fd.cmd = 0; + fd.format = qm_fd_compound; + fd.cong_weight = caam32_to_cpu(req->fd_sgt[1].length); + fd.addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt), DMA_BIDIRECTIONAL); - if (dma_mapping_error(qidev, addr)) { + if (dma_mapping_error(qidev, fd.addr)) { dev_err(qidev, "DMA mapping error for QI enqueue request\n"); return -EIO; } - qm_fd_addr_set64(&fd, addr); do { - ret = qman_enqueue(req->drv_ctx->req_fq, &fd); + ret = qman_enqueue(req->drv_ctx->req_fq, &fd, 0); if (likely(!ret)) { refcount_inc(&req->drv_ctx->refcnt); return 0; @@ -133,7 +131,7 @@ EXPORT_SYMBOL(caam_qi_enqueue); static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq, - const union qm_mr_entry *msg) + const struct qm_mr_entry *msg) { const struct qm_fd *fd; struct caam_drv_req *drv_req; @@ -151,7 +149,7 @@ refcount_dec(&drv_req->drv_ctx->refcnt); - if (qm_fd_get_format(fd) != qm_fd_compound) { + if (fd->format != qm_fd_compound) { dev_err(qidev, "Non-compound FD from CAAM\n"); return; } @@ -182,20 +180,22 @@ req_fq->cb.fqs = NULL; ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | - QMAN_FQ_FLAG_TO_DCPORTAL, req_fq); + QMAN_FQ_FLAG_TO_DCPORTAL | QMAN_FQ_FLAG_LOCKED, + req_fq); if (ret) { dev_err(qidev, "Failed to create session req FQ\n"); goto create_req_fq_fail; } - memset(&opts, 0, sizeof(opts)); - opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | - QM_INITFQ_WE_CONTEXTB | - QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID); - opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE); - qm_fqd_set_destwq(&opts.fqd, qm_channel_caam, 2); - opts.fqd.context_b = cpu_to_be32(qman_fq_fqid(rsp_fq)); - qm_fqd_context_a_set64(&opts.fqd, hwdesc); + opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | + QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA | + QM_INITFQ_WE_CGID; + opts.fqd.fq_ctrl = QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE; + opts.fqd.dest.channel = qm_channel_caam; + opts.fqd.dest.wq = 2; + opts.fqd.context_b = qman_fq_fqid(rsp_fq); + opts.fqd.context_a.hi = upper_32_bits(hwdesc); + opts.fqd.context_a.lo = lower_32_bits(hwdesc); opts.fqd.cgid = qipriv.cgr.cgrid; ret = qman_init_fq(req_fq, fq_sched_flag, &opts); @@ -209,7 +209,7 @@ return req_fq; init_req_fq_fail: - qman_destroy_fq(req_fq); + qman_destroy_fq(req_fq, 0); create_req_fq_fail: kfree(req_fq); return ERR_PTR(ret); @@ -277,7 +277,7 @@ if (ret) dev_err(qidev, "OOS of FQID: %u failed\n", fq->fqid); - qman_destroy_fq(fq); + qman_destroy_fq(fq, 0); kfree(fq); return ret; @@ -295,7 +295,7 @@ if (ret) return ret; - if (!qm_mcr_np_get(&np, frm_cnt)) + if (!np.frm_cnt) break; msleep(20); @@ -545,10 +545,14 @@ } } -static int caam_qi_napi_schedule(struct qman_portal *p, struct caam_napi *np, - bool sched_napi) +static int caam_qi_napi_schedule(struct qman_portal *p, struct caam_napi *np) { - if (sched_napi) { + /* + * In case of threaded ISR, for RT kernels in_irq() does not return + * appropriate value, so use in_serving_softirq to distinguish between + * softirq and irq contexts. + */ + if (unlikely(in_irq() || !in_serving_softirq())) { /* Disable QMan IRQ source and invoke NAPI */ qman_p_irqsource_remove(p, QM_PIRQ_DQRI); np->p = p; @@ -560,22 +564,20 @@ static enum qman_cb_dqrr_result caam_rsp_fq_dqrr_cb(struct qman_portal *p, struct qman_fq *rsp_fq, - const struct qm_dqrr_entry *dqrr, - bool sched_napi) + const struct qm_dqrr_entry *dqrr) { struct caam_napi *caam_napi = raw_cpu_ptr(&pcpu_qipriv.caam_napi); struct caam_drv_req *drv_req; const struct qm_fd *fd; struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev); struct caam_drv_private *priv = dev_get_drvdata(qidev); - u32 status; - if (caam_qi_napi_schedule(p, caam_napi, sched_napi)) + if (caam_qi_napi_schedule(p, caam_napi)) return qman_cb_dqrr_stop; fd = &dqrr->fd; - drv_req = caam_iova_to_virt(priv->domain, qm_fd_addr_get64(fd)); + drv_req = caam_iova_to_virt(priv->domain, fd->addr); if (unlikely(!drv_req)) { dev_err(qidev, "Can't find original request for caam response\n"); @@ -584,19 +586,18 @@ refcount_dec(&drv_req->drv_ctx->refcnt); - status = be32_to_cpu(fd->status); - if (unlikely(status)) { - u32 ssrc = status & JRSTA_SSRC_MASK; - u8 err_id = status & JRSTA_CCBERR_ERRID_MASK; + if (unlikely(fd->status)) { + u32 ssrc = fd->status & JRSTA_SSRC_MASK; + u8 err_id = fd->status & JRSTA_CCBERR_ERRID_MASK; if (ssrc != JRSTA_SSRC_CCB_ERROR || err_id != JRSTA_CCBERR_ERRID_ICVCHK) dev_err_ratelimited(qidev, "Error: %#x in CAAM response FD\n", - status); + fd->status); } - if (unlikely(qm_fd_get_format(fd) != qm_fd_compound)) { + if (unlikely(fd->format != qm_fd_compound)) { dev_err(qidev, "Non-compound FD from CAAM\n"); return qman_cb_dqrr_consume; } @@ -604,7 +605,7 @@ dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd), sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL); - drv_req->cbk(drv_req, status); + drv_req->cbk(drv_req, fd->status); return qman_cb_dqrr_consume; } @@ -628,17 +629,18 @@ return -ENODEV; } - memset(&opts, 0, sizeof(opts)); - opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | - QM_INITFQ_WE_CONTEXTB | - QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID); - opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CTXASTASHING | - QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE); - qm_fqd_set_destwq(&opts.fqd, qman_affine_channel(cpu), 3); + opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | + QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA | + QM_INITFQ_WE_CGID; + opts.fqd.fq_ctrl = QM_FQCTRL_CTXASTASHING | QM_FQCTRL_CPCSTASH | + QM_FQCTRL_CGE; + opts.fqd.dest.channel = qman_affine_channel(cpu); + opts.fqd.dest.wq = 3; opts.fqd.cgid = qipriv.cgr.cgrid; opts.fqd.context_a.stashing.exclusive = QM_STASHING_EXCL_CTX | QM_STASHING_EXCL_DATA; - qm_fqd_set_stashing(&opts.fqd, 0, 1, 1); + opts.fqd.context_a.stashing.data_cl = 1; + opts.fqd.context_a.stashing.context_cl = 1; ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); if (ret) { @@ -668,8 +670,7 @@ qipriv.cgr.cb = cgr_cb; memset(&opts, 0, sizeof(opts)); - opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES | - QM_CGR_WE_MODE); + opts.we_mask = QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES | QM_CGR_WE_MODE; opts.cgr.cscn_en = QM_CGR_EN; opts.cgr.mode = QMAN_CGR_MODE_FRAME; qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, val, 1); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/qi.h linux-imx-phytec/drivers/crypto/caam/qi.h --- linux-6.1.55/drivers/crypto/caam/qi.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/qi.h 2024-06-19 12:33:59.744217258 +0200 @@ -9,7 +9,7 @@ #ifndef __QI_H__ #define __QI_H__ -#include +#include #include "compat.h" #include "desc.h" #include "desc_constr.h" diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/regs.h linux-imx-phytec/drivers/crypto/caam/regs.h --- linux-6.1.55/drivers/crypto/caam/regs.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/regs.h 2024-06-19 12:33:59.744217258 +0200 @@ -386,6 +386,12 @@ #define CHA_VER_VID_MD_LP512 0x1ull #define CHA_VER_VID_MD_HP 0x2ull +/* + * caam_perfmon - Performance Monitor/Secure Memory Status/ + * CAAM Global Status/Component Version IDs + * + * Spans f00-fff wherever instantiated + */ struct sec_vid { u16 ip_id; u8 maj_rev; @@ -417,17 +423,22 @@ u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ #define CTPR_LS_BLOB BIT(1) u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ - u64 rsvd1[2]; + /* Secure Memory State Visibility */ + u32 rsvd1; + u32 smstatus; /* Secure memory status */ + u32 rsvd2; + u32 smpartown; /* Secure memory partition owner */ /* CAAM Global Status fc0-fdf */ u64 faultaddr; /* FAR - Fault Address */ u32 faultliodn; /* FALR - Fault Address LIODN */ u32 faultdetail; /* FADR - Fault Addr Detail */ - u32 rsvd2; #define CSTA_PLEND BIT(10) #define CSTA_ALT_PLEND BIT(18) + u32 rsvd3; u32 status; /* CSTA - CAAM Status */ - u64 rsvd3; + u32 smpart; /* Secure Memory Partition Parameters */ + u32 smvid; /* Secure Memory Version ID */ /* Component Instantiation Parameters fe0-fff */ u32 rtic_id; /* RVID - RTIC Version ID */ @@ -446,6 +457,62 @@ u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ }; +#define SMSTATUS_PART_SHIFT 28 +#define SMSTATUS_PART_MASK (0xf << SMSTATUS_PART_SHIFT) +#define SMSTATUS_PAGE_SHIFT 16 +#define SMSTATUS_PAGE_MASK (0x7ff << SMSTATUS_PAGE_SHIFT) +#define SMSTATUS_MID_SHIFT 8 +#define SMSTATUS_MID_MASK (0x3f << SMSTATUS_MID_SHIFT) +#define SMSTATUS_ACCERR_SHIFT 4 +#define SMSTATUS_ACCERR_MASK (0xf << SMSTATUS_ACCERR_SHIFT) +#define SMSTATUS_ACCERR_NONE 0 +#define SMSTATUS_ACCERR_ALLOC 1 /* Page not allocated */ +#define SMSTATUS_ACCESS_ID 2 /* Not granted by ID */ +#define SMSTATUS_ACCESS_WRITE 3 /* Writes not allowed */ +#define SMSTATUS_ACCESS_READ 4 /* Reads not allowed */ +#define SMSTATUS_ACCESS_NONKEY 6 /* Non-key reads not allowed */ +#define SMSTATUS_ACCESS_BLOB 9 /* Blob access not allowed */ +#define SMSTATUS_ACCESS_DESCB 10 /* Descriptor Blob access spans pages */ +#define SMSTATUS_ACCESS_NON_SM 11 /* Outside Secure Memory range */ +#define SMSTATUS_ACCESS_XPAGE 12 /* Access crosses pages */ +#define SMSTATUS_ACCESS_INITPG 13 /* Page still initializing */ +#define SMSTATUS_STATE_SHIFT 0 +#define SMSTATUS_STATE_MASK (0xf << SMSTATUS_STATE_SHIFT) +#define SMSTATUS_STATE_RESET 0 +#define SMSTATUS_STATE_INIT 1 +#define SMSTATUS_STATE_NORMAL 2 +#define SMSTATUS_STATE_FAIL 3 + +/* up to 15 rings, 2 bits shifted by ring number */ +#define SMPARTOWN_RING_SHIFT 2 +#define SMPARTOWN_RING_MASK 3 +#define SMPARTOWN_AVAILABLE 0 +#define SMPARTOWN_NOEXIST 1 +#define SMPARTOWN_UNAVAILABLE 2 +#define SMPARTOWN_OURS 3 + +/* Maximum number of pages possible */ +#define SMPART_MAX_NUMPG_SHIFT 16 +#define SMPART_MAX_NUMPG_MASK (0x3f << SMPART_MAX_NUMPG_SHIFT) + +/* Maximum partition number */ +#define SMPART_MAX_PNUM_SHIFT 12 +#define SMPART_MAX_PNUM_MASK (0xf << SMPART_MAX_PNUM_SHIFT) + +/* Highest possible page number */ +#define SMPART_MAX_PG_SHIFT 0 +#define SMPART_MAX_PG_MASK (0x3f << SMPART_MAX_PG_SHIFT) + +/* Max size of a page */ +#define SMVID_PG_SIZE_SHIFT 16 +#define SMVID_PG_SIZE_MASK (0x7 << SMVID_PG_SIZE_SHIFT) + +/* Major/Minor Version ID */ +#define SMVID_MAJ_VERS_SHIFT 8 +#define SMVID_MAJ_VERS (0xf << SMVID_MAJ_VERS_SHIFT) +#define SMVID_MIN_VERS_SHIFT 0 +#define SMVID_MIN_VERS (0xf << SMVID_MIN_VERS_SHIFT) + /* LIODN programming for DMA configuration */ #define MSTRID_LOCK_LIODN 0x80000000 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ @@ -456,12 +523,6 @@ u32 liodn_ls; /* LIODN for non-sequence and seq access */ }; -/* Partition ID for DMA configuration */ -struct partid { - u32 rsvd1; - u32 pidr; /* partition ID, DECO */ -}; - /* RNGB test mode (replicated twice in some configurations) */ /* Padded out to 0x100 */ struct rngtst { @@ -520,6 +581,8 @@ #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) #define RTSDCTL_ENT_DLY_MIN 3200 #define RTSDCTL_ENT_DLY_MAX 12800 +#define RTSDCTL_SAMP_SIZE_MASK 0xffff +#define RTSDCTL_SAMP_SIZE_VAL 512 u32 rtsdctl; /* seed control register */ union { u32 rtsblim; /* PRGM=1: sparse bit limit register */ @@ -531,7 +594,15 @@ u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ u32 rtfrqcnt; /* PRGM=0: freq. count register */ }; - u32 rsvd1[40]; + union { + u32 rtscmc; /* statistical check run monobit count */ + u32 rtscml; /* statistical check run monobit limit */ + }; + union { + u32 rtscrc[6]; /* statistical check run length count */ + u32 rtscrl[6]; /* statistical check run length limit */ + }; + u32 rsvd1[33]; #define RDSTA_SKVT 0x80000000 #define RDSTA_SKVN 0x40000000 #define RDSTA_PR0 BIT(4) @@ -577,8 +648,7 @@ u32 deco_rsr; /* DECORSR - Deco Request Source */ u32 rsvd11; u32 deco_rq; /* DECORR - DECO Request */ - struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ - u32 rsvd5[22]; + struct masterid deco_mid[16]; /* DECOxLIODNR - 1 per DECO */ /* DECO Availability/Reset Section 120-3ff */ u32 deco_avail; /* DAR - DECO availability */ @@ -652,6 +722,35 @@ #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ +/* Secure Memory Configuration - if you have it */ +/* Secure Memory Register Offset from JR Base Reg*/ +#define SM_V1_OFFSET 0x0f4 +#define SM_V2_OFFSET 0xa00 + +/* Minimum SM Version ID requiring v2 SM register mapping */ +#define SMVID_V2 0x20105 + +struct caam_secure_mem_v1 { + u32 sm_cmd; /* SMCJRx - Secure memory command */ + u32 rsvd1; + u32 sm_status; /* SMCSJRx - Secure memory status */ + u32 rsvd2; + + u32 sm_perm; /* SMAPJRx - Secure memory access perms */ + u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */ + u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */ +}; + +struct caam_secure_mem_v2 { + u32 sm_perm; /* SMAPJRx - Secure memory access perms */ + u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */ + u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */ + u32 rsvd1[118]; + u32 sm_cmd; /* SMCJRx - Secure memory command */ + u32 rsvd2; + u32 sm_status; /* SMCSJRx - Secure memory status */ +}; + /* * caam_job_ring - direct job ring setup * 1-4 possible per instantiation, base + 1000/2000/3000/4000 @@ -822,6 +921,62 @@ #define JRCR_RESET 0x01 +/* secure memory command */ +#define SMC_PAGE_SHIFT 16 +#define SMC_PAGE_MASK (0xffff << SMC_PAGE_SHIFT) +#define SMC_PART_SHIFT 8 +#define SMC_PART_MASK (0x0f << SMC_PART_SHIFT) +#define SMC_CMD_SHIFT 0 +#define SMC_CMD_MASK (0x0f << SMC_CMD_SHIFT) + +#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */ +#define SMC_CMD_DEALLOC_PAGE 0x02 /* deallocate page from partition */ +#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */ +#define SMC_CMD_PAGE_INQUIRY 0x05 /* find partition associate with page */ + +/* secure memory (command) status */ +#define SMCS_PAGE_SHIFT 16 +#define SMCS_PAGE_MASK (0x0fff << SMCS_PAGE_SHIFT) +#define SMCS_CMDERR_SHIFT 14 +#define SMCS_CMDERR_MASK (3 << SMCS_CMDERR_SHIFT) +#define SMCS_ALCERR_SHIFT 12 +#define SMCS_ALCERR_MASK (3 << SMCS_ALCERR_SHIFT) +#define SMCS_PGOWN_SHIFT 6 +#define SMCS_PGWON_MASK (3 << SMCS_PGOWN_SHIFT) +#define SMCS_PART_SHIFT 0 +#define SMCS_PART_MASK (0xf << SMCS_PART_SHIFT) + +#define SMCS_CMDERR_NONE 0 +#define SMCS_CMDERR_INCOMP 1 /* Command not yet complete */ +#define SMCS_CMDERR_SECFAIL 2 /* Security failure occurred */ +#define SMCS_CMDERR_OVERFLOW 3 /* Command overflow */ + +#define SMCS_ALCERR_NONE 0 +#define SMCS_ALCERR_PSPERR 1 /* Partion marked PSP (dealloc only) */ +#define SMCS_ALCERR_PAGEAVAIL 2 /* Page not available */ +#define SMCS_ALCERR_PARTOWN 3 /* Partition ownership error */ + +#define SMCS_PGOWN_AVAIL 0 /* Page is available */ +#define SMCS_PGOWN_NOEXIST 1 /* Page initializing or nonexistent */ +#define SMCS_PGOWN_NOOWN 2 /* Page owned by another processor */ +#define SMCS_PGOWN_OWNED 3 /* Page belongs to this processor */ + +/* secure memory access permissions */ +#define SMCS_PERM_KEYMOD_SHIFT 16 +#define SMCA_PERM_KEYMOD_MASK (0xff << SMCS_PERM_KEYMOD_SHIFT) +#define SMCA_PERM_CSP_ZERO 0x8000 /* Zero when deallocated or released */ +#define SMCA_PERM_PSP_LOCK 0x4000 /* Part./pages can't be deallocated */ +#define SMCA_PERM_PERM_LOCK 0x2000 /* Lock permissions */ +#define SMCA_PERM_GRP_LOCK 0x1000 /* Lock access groups */ +#define SMCA_PERM_RINGID_SHIFT 10 +#define SMCA_PERM_RINGID_MASK (3 << SMCA_PERM_RINGID_SHIFT) +#define SMCA_PERM_G2_BLOB 0x0080 /* Group 2 blob import/export */ +#define SMCA_PERM_G2_WRITE 0x0020 /* Group 2 write */ +#define SMCA_PERM_G2_READ 0x0010 /* Group 2 read */ +#define SMCA_PERM_G1_BLOB 0x0008 /* Group 1... */ +#define SMCA_PERM_G1_WRITE 0x0002 +#define SMCA_PERM_G1_READ 0x0001 + /* * caam_assurance - Assurance Controller View * base + 0x6000 padded out to 0x1000 diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/secvio.c linux-imx-phytec/drivers/crypto/caam/secvio.c --- linux-6.1.55/drivers/crypto/caam/secvio.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/secvio.c 2024-06-19 12:33:59.744217258 +0200 @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * SNVS Security Violation Handler + * + * Copyright 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019, 2023 NXP + */ + +#include "compat.h" +#include "secvio.h" +#include "regs.h" +#include "intern.h" +#include +#include +#include + +/* The driver is matched with node caam_snvs to get regmap + * It will then retrieve interruption and tamper alarm configuration from + * node caam-secvio searching for the compat string "fsl,imx6q-caam-secvio" + */ +#define DRIVER_NAME "caam-snvs" + +/* + * These names are associated with each violation handler. + * The source names were taken from MX6, and are based on recommendations + * for most common SoCs. + */ +static const u8 *violation_src_name[] = { + "CAAM Internal Security Violation", + "JTAG Alarm", + "Watchdog", + "(reserved)", + "External Boot", + "External Tamper Detect", +}; + +/* These names help describe security monitor state for the console */ +static const u8 *snvs_ssm_state_name[] = { + "init", + "hard fail", + "(undef:2)", + "soft fail", + "(undef:4)", + "(undef:5)", + "(undef:6)", + "(undef:7)", + "transition", + "check", + "(undef:10)", + "non-secure", + "(undef:12)", + "trusted", + "(undef:14)", + "secure", +}; + +static DEFINE_STATIC_KEY_TRUE(snvs_little_end); + +static inline u32 secvio_read(void __iomem *reg) +{ + if (static_branch_likely(&snvs_little_end)) + return ioread32(reg); + else + return ioread32be(reg); +} + +static inline void secvio_write(void __iomem *reg, u32 data) +{ + if (static_branch_likely(&snvs_little_end)) + iowrite32(data, reg); + else + iowrite32be(data, reg); +} + +/* Top-level security violation interrupt */ +static irqreturn_t snvs_secvio_interrupt(int irq, void *snvsdev) +{ + struct device *dev = snvsdev; + struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); + + clk_enable(svpriv->clk); + /* Check the HP secvio status register */ + svpriv->irqcause = secvio_read(&svpriv->svregs->hp.secvio_status) & + HP_SECVIOST_SECVIOMASK; + + if (!svpriv->irqcause) { + clk_disable(svpriv->clk); + return IRQ_NONE; + } + + /* Now ACK cause */ + clrsetbits_32(&svpriv->svregs->hp.secvio_status, 0, svpriv->irqcause); + + /* And run deferred service */ + preempt_disable(); + tasklet_schedule(&svpriv->irqtask[smp_processor_id()]); + preempt_enable(); + + clk_disable(svpriv->clk); + + return IRQ_HANDLED; +} + +/* Deferred service handler. Tasklet arg is simply the SNVS dev */ +static void snvs_secvio_dispatch(unsigned long indev) +{ + struct device *dev = (struct device *)indev; + struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); + unsigned long flags; + int i; + + + /* Look through stored causes, call each handler if exists */ + for (i = 0; i < MAX_SECVIO_SOURCES; i++) + if (svpriv->irqcause & (1 << i)) { + spin_lock_irqsave(&svpriv->svlock, flags); + svpriv->intsrc[i].handler(dev, i, + svpriv->intsrc[i].ext); + spin_unlock_irqrestore(&svpriv->svlock, flags); + }; + + /* Re-enable now-serviced interrupts */ + clrsetbits_32(&svpriv->svregs->hp.secvio_intcfg, 0, svpriv->irqcause); +} + +/* + * Default cause handler, used in lieu of an application-defined handler. + * All it does at this time is print a console message. It could force a halt. + */ +static void snvs_secvio_default(struct device *dev, u32 cause, void *ext) +{ + struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); + + dev_err(dev, "Unhandled Security Violation Interrupt %d = %s\n", + cause, svpriv->intsrc[cause].intname); +} + +/* + * Install an application-defined handler for a specified cause + * Arguments: + * - dev points to SNVS-owning device + * - cause interrupt source cause + * - handler application-defined handler, gets called with dev + * source cause, and locally-defined handler argument + * - cause_description points to a string to override the default cause + * name, this can be used as an alternate for error + * messages and such. If left NULL, the default + * description string is used. + * - ext pointer to any extra data needed by the handler. + */ +int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause, + void (*handler)(struct device *dev, u32 cause, + void *ext), + u8 *cause_description, void *ext) +{ + unsigned long flags; + struct snvs_secvio_drv_private *svpriv; + + svpriv = dev_get_drvdata(dev); + + if ((handler == NULL) || (cause > SECVIO_CAUSE_SOURCE_5)) + return -EINVAL; + + spin_lock_irqsave(&svpriv->svlock, flags); + svpriv->intsrc[cause].handler = handler; + if (cause_description != NULL) + svpriv->intsrc[cause].intname = cause_description; + if (ext != NULL) + svpriv->intsrc[cause].ext = ext; + spin_unlock_irqrestore(&svpriv->svlock, flags); + + return 0; +} +EXPORT_SYMBOL(snvs_secvio_install_handler); + +/* + * Remove an application-defined handler for a specified cause (and, by + * implication, restore the "default". + * Arguments: + * - dev points to SNVS-owning device + * - cause interrupt source cause + */ +int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause) +{ + unsigned long flags; + struct snvs_secvio_drv_private *svpriv; + + svpriv = dev_get_drvdata(dev); + + if (cause > SECVIO_CAUSE_SOURCE_5) + return -EINVAL; + + spin_lock_irqsave(&svpriv->svlock, flags); + svpriv->intsrc[cause].intname = violation_src_name[cause]; + svpriv->intsrc[cause].handler = snvs_secvio_default; + svpriv->intsrc[cause].ext = NULL; + spin_unlock_irqrestore(&svpriv->svlock, flags); + return 0; +} +EXPORT_SYMBOL(snvs_secvio_remove_handler); + +static int snvs_secvio_remove(struct platform_device *pdev) +{ + struct device *svdev; + struct snvs_secvio_drv_private *svpriv; + int i; + + svdev = &pdev->dev; + svpriv = dev_get_drvdata(svdev); + + clk_enable(svpriv->clk); + /* Set all sources to nonfatal */ + secvio_write(&svpriv->svregs->hp.secvio_intcfg, 0); + + /* Remove tasklets and release interrupt */ + for_each_possible_cpu(i) + tasklet_kill(&svpriv->irqtask[i]); + + clk_disable_unprepare(svpriv->clk); + free_irq(svpriv->irq, svdev); + iounmap(svpriv->svregs); + kfree(svpriv); + + return 0; +} + +static int snvs_secvio_probe(struct platform_device *pdev) +{ + struct device *svdev; + struct snvs_secvio_drv_private *svpriv; + struct device_node *np, *npirq; + struct snvs_full __iomem *snvsregs; + int i, error; + u32 hpstate; + const void *jtd, *wtd, *itd, *etd; + u32 td_en; + u32 ipidr, ipid; + + svpriv = kzalloc(sizeof(struct snvs_secvio_drv_private), GFP_KERNEL); + if (!svpriv) + return -ENOMEM; + + svdev = &pdev->dev; + dev_set_drvdata(svdev, svpriv); + svpriv->pdev = pdev; + spin_lock_init(&svpriv->svlock); + np = pdev->dev.of_node; + + npirq = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-secvio"); + if (!npirq) { + dev_err(svdev, "can't find secvio node\n"); + kfree(svpriv); + return -EINVAL; + } + svpriv->irq = irq_of_parse_and_map(npirq, 0); + if (svpriv->irq <= 0) { + dev_err(svdev, "can't identify secvio interrupt\n"); + kfree(svpriv); + return -EINVAL; + } + + jtd = of_get_property(npirq, "jtag-tamper", NULL); + wtd = of_get_property(npirq, "watchdog-tamper", NULL); + itd = of_get_property(npirq, "internal-boot-tamper", NULL); + etd = of_get_property(npirq, "external-pin-tamper", NULL); + if (!jtd | !wtd | !itd | !etd ) { + dev_err(svdev, "can't identify all tamper alarm configuration\n"); + kfree(svpriv); + return -EINVAL; + } + + /* + * Configure all sources according to device tree property. + * If the property is enabled then the source is ser as + * fatal violations except LP section, + * source #5 (typically used as an external tamper detect), and + * source #3 (typically unused). Whenever the transition to + * secure mode has occurred, these will now be "fatal" violations + */ + td_en = HP_SECVIO_INTEN_SRC0; + if (!strcmp(jtd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC1; + if (!strcmp(wtd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC2; + if (!strcmp(itd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC4; + if (!strcmp(etd, "enabled")) + td_en |= HP_SECVIO_INTEN_SRC5; + + snvsregs = of_iomap(np, 0); + if (!snvsregs) { + dev_err(svdev, "register mapping failed\n"); + return -ENOMEM; + } + svpriv->svregs = (struct snvs_full __force *)snvsregs; + + svpriv->clk = devm_clk_get_optional(&pdev->dev, "ipg"); + if (IS_ERR(svpriv->clk)) + return PTR_ERR(svpriv->clk); + + clk_prepare_enable(svpriv->clk); + + /* + * Reading SNVS version ID register HPVIDR1 to identify the endianness + * of the device which contain non-zero constants including 16-bit field + * called IP_ID[Bit 31-16] having one of the four values 0x003A, 0x003C, + * 0x003E, 0x003F. + */ + ipidr = secvio_read(&svpriv->svregs->vid); + ipid = ipidr >> SNVS_HPVIDR_BLOCK_ID; + if (ipid == SNVS_ID1 || ipid == SNVS_ID2 || ipid == SNVS_ID3 || ipid == SNVS_ID4) { + dev_info(svdev, "ipid matched - 0x%x\n", ipid); + } else { + /* + * Device endianness is not LE.Reading again SNVS version ID + * register value to identify the endianness of device is BE. + */ + ipid = (ipidr & (u32)0x0000FF00) >> 8; + if (ipid == SNVS_ID1 || ipid == SNVS_ID2 || ipid == SNVS_ID3 || ipid == SNVS_ID4) { + dev_info(svdev, "ipid matched - 0x%x\n", ipid); + static_branch_disable(&snvs_little_end); + } else { + dev_err(svdev, "unable to identify secvio endianness\n"); + iounmap(svpriv->svregs); + kfree(svpriv); + return -EINVAL; + } + } + + /* Write the Secvio Enable Config the SVCR */ + secvio_write(&svpriv->svregs->hp.secvio_ctl, td_en); + secvio_write(&svpriv->svregs->hp.secvio_intcfg, td_en); + + /* Device data set up. Now init interrupt source descriptions */ + for (i = 0; i < MAX_SECVIO_SOURCES; i++) { + svpriv->intsrc[i].intname = violation_src_name[i]; + svpriv->intsrc[i].handler = snvs_secvio_default; + } + /* Connect main handler */ + for_each_possible_cpu(i) + tasklet_init(&svpriv->irqtask[i], snvs_secvio_dispatch, + (unsigned long)svdev); + + error = request_irq(svpriv->irq, snvs_secvio_interrupt, + IRQF_SHARED, DRIVER_NAME, svdev); + if (error) { + dev_err(svdev, "can't connect secvio interrupt\n"); + irq_dispose_mapping(svpriv->irq); + svpriv->irq = 0; + iounmap(svpriv->svregs); + kfree(svpriv); + return -EINVAL; + } + + hpstate = (secvio_read(&svpriv->svregs->hp.status) & + HP_STATUS_SSM_ST_MASK) >> HP_STATUS_SSM_ST_SHIFT; + dev_info(svdev, "violation handlers armed - %s state\n", + snvs_ssm_state_name[hpstate]); + + clk_disable(svpriv->clk); + + return 0; +} + +static struct of_device_id snvs_secvio_match[] = { + { + .compatible = "fsl,imx6q-caam-snvs", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, snvs_secvio_match); + +static struct platform_driver snvs_secvio_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = snvs_secvio_match, + }, + .probe = snvs_secvio_probe, + .remove = snvs_secvio_remove, +}; + +module_platform_driver(snvs_secvio_driver); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("FSL SNVS Security Violation Handler"); +MODULE_AUTHOR("Freescale Semiconductor - MCU"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/secvio.h linux-imx-phytec/drivers/crypto/caam/secvio.h --- linux-6.1.55/drivers/crypto/caam/secvio.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/secvio.h 2024-06-19 12:33:59.748217327 +0200 @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * CAAM Security Violation Handler + * + * Copyright 2012-2015 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + */ + +#ifndef SECVIO_H +#define SECVIO_H + +#include "snvsregs.h" + + +/* + * Defines the published interfaces to install/remove application-specified + * handlers for catching violations + */ + +#define MAX_SECVIO_SOURCES 6 + +/* these are the untranslated causes */ +enum secvio_cause { + SECVIO_CAUSE_SOURCE_0, + SECVIO_CAUSE_SOURCE_1, + SECVIO_CAUSE_SOURCE_2, + SECVIO_CAUSE_SOURCE_3, + SECVIO_CAUSE_SOURCE_4, + SECVIO_CAUSE_SOURCE_5 +}; + +/* These are common "recommended" cause definitions for most devices */ +#define SECVIO_CAUSE_CAAM_VIOLATION SECVIO_CAUSE_SOURCE_0 +#define SECVIO_CAUSE_JTAG_ALARM SECVIO_CAUSE_SOURCE_1 +#define SECVIO_CAUSE_WATCHDOG SECVIO_CAUSE_SOURCE_2 +#define SECVIO_CAUSE_EXTERNAL_BOOT SECVIO_CAUSE_SOURCE_4 +#define SECVIO_CAUSE_TAMPER_DETECT SECVIO_CAUSE_SOURCE_5 + +int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause, + void (*handler)(struct device *dev, u32 cause, + void *ext), + u8 *cause_description, void *ext); +int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause); + +/* + * Private data definitions for the secvio "driver" + */ + +struct secvio_int_src { + const u8 *intname; /* Points to a descriptive name for source */ + void *ext; /* Extended data to pass to the handler */ + void (*handler)(struct device *dev, u32 cause, void *ext); +}; + +struct snvs_secvio_drv_private { + struct platform_device *pdev; + spinlock_t svlock ____cacheline_aligned; + struct tasklet_struct irqtask[NR_CPUS]; + struct snvs_full __iomem *svregs; /* both HP and LP domains */ + struct clk *clk; + int irq; + u32 irqcause; /* stashed cause of violation interrupt */ + + /* Registered handlers for each violation */ + struct secvio_int_src intsrc[MAX_SECVIO_SOURCES]; + +}; + +#endif /* SECVIO_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/sg_sw_qm.h linux-imx-phytec/drivers/crypto/caam/sg_sw_qm.h --- linux-6.1.55/drivers/crypto/caam/sg_sw_qm.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/caam/sg_sw_qm.h 2024-06-19 12:33:59.748217327 +0200 @@ -7,46 +7,61 @@ #ifndef __SG_SW_QM_H #define __SG_SW_QM_H -#include +#include #include "regs.h" +static inline void cpu_to_hw_sg(struct qm_sg_entry *qm_sg_ptr) +{ + dma_addr_t addr = qm_sg_ptr->opaque; + + qm_sg_ptr->opaque = cpu_to_caam64(addr); + qm_sg_ptr->sgt_efl = cpu_to_caam32(qm_sg_ptr->sgt_efl); +} + static inline void __dma_to_qm_sg(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma, - u16 offset) + u32 len, u16 offset) { - qm_sg_entry_set64(qm_sg_ptr, dma); + qm_sg_ptr->addr = dma; + qm_sg_ptr->length = len; qm_sg_ptr->__reserved2 = 0; qm_sg_ptr->bpid = 0; - qm_sg_ptr->offset = cpu_to_be16(offset & QM_SG_OFF_MASK); + qm_sg_ptr->__reserved3 = 0; + qm_sg_ptr->offset = offset & QM_SG_OFFSET_MASK; + + cpu_to_hw_sg(qm_sg_ptr); } static inline void dma_to_qm_sg_one(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma, u32 len, u16 offset) { - __dma_to_qm_sg(qm_sg_ptr, dma, offset); - qm_sg_entry_set_len(qm_sg_ptr, len); + qm_sg_ptr->extension = 0; + qm_sg_ptr->final = 0; + __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); } static inline void dma_to_qm_sg_one_last(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma, u32 len, u16 offset) { - __dma_to_qm_sg(qm_sg_ptr, dma, offset); - qm_sg_entry_set_f(qm_sg_ptr, len); + qm_sg_ptr->extension = 0; + qm_sg_ptr->final = 1; + __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); } static inline void dma_to_qm_sg_one_ext(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma, u32 len, u16 offset) { - __dma_to_qm_sg(qm_sg_ptr, dma, offset); - qm_sg_ptr->cfg = cpu_to_be32(QM_SG_EXT | (len & QM_SG_LEN_MASK)); + qm_sg_ptr->extension = 1; + qm_sg_ptr->final = 0; + __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); } static inline void dma_to_qm_sg_one_last_ext(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma, u32 len, u16 offset) { - __dma_to_qm_sg(qm_sg_ptr, dma, offset); - qm_sg_ptr->cfg = cpu_to_be32(QM_SG_EXT | QM_SG_FIN | - (len & QM_SG_LEN_MASK)); + qm_sg_ptr->extension = 1; + qm_sg_ptr->final = 1; + __dma_to_qm_sg(qm_sg_ptr, dma, len, offset); } /* @@ -79,7 +94,10 @@ struct qm_sg_entry *qm_sg_ptr, u16 offset) { qm_sg_ptr = sg_to_qm_sg(sg, len, qm_sg_ptr, offset); - qm_sg_entry_set_f(qm_sg_ptr, qm_sg_entry_get_len(qm_sg_ptr)); + + qm_sg_ptr->sgt_efl = caam32_to_cpu(qm_sg_ptr->sgt_efl); + qm_sg_ptr->final = 1; + qm_sg_ptr->sgt_efl = cpu_to_caam32(qm_sg_ptr->sgt_efl); } #endif /* __SG_SW_QM_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/sm.h linux-imx-phytec/drivers/crypto/caam/sm.h --- linux-6.1.55/drivers/crypto/caam/sm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/sm.h 2024-06-19 12:33:59.748217327 +0200 @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * CAAM Secure Memory/Keywrap API Definitions + * + * Copyright 2008-2015 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + */ + +#ifndef SM_H +#define SM_H + + +/* Storage access permissions */ +#define SM_PERM_READ 0x01 +#define SM_PERM_WRITE 0x02 +#define SM_PERM_BLOB 0x03 + +/* Define treatment of secure memory vs. general memory blobs */ +#define SM_SECMEM 0 +#define SM_GENMEM 1 + +/* Define treatment of red/black keys */ +#define RED_KEY 0 +#define BLACK_KEY 1 + +/* Define key encryption/covering options */ +#define KEY_COVER_ECB 0 /* cover key in AES-ECB */ +#define KEY_COVER_CCM 1 /* cover key with AES-CCM */ + +/* + * Round a key size up to an AES blocksize boundary so to allow for + * padding out to a full block + */ +#define AES_BLOCK_PAD(x) ((x % 16) ? ((x >> 4) + 1) << 4 : x) + +/* Define space required for BKEK + MAC tag storage in any blob */ +#define BLOB_OVERHEAD (32 + 16) + +/* Keystore maintenance functions */ +void sm_init_keystore(struct device *dev); +u32 sm_detect_keystore_units(struct device *dev); +int sm_establish_keystore(struct device *dev, u32 unit); +void sm_release_keystore(struct device *dev, u32 unit); +int caam_sm_example_init(struct platform_device *pdev); + +/* Keystore accessor functions */ +extern int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, + u32 *slot); +extern int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot); +extern int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot, + const u8 *key_data, u32 key_length); +extern int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot, + u32 key_length, u8 *key_data); +extern int sm_keystore_cover_key(struct device *dev, u32 unit, u32 slot, + u16 key_length, u8 keyauth); +extern int sm_keystore_slot_export(struct device *dev, u32 unit, u32 slot, + u8 keycolor, u8 keyauth, u8 *outbuf, + u16 keylen, u8 *keymod); +extern int sm_keystore_slot_import(struct device *dev, u32 unit, u32 slot, + u8 keycolor, u8 keyauth, u8 *inbuf, + u16 keylen, u8 *keymod); + +/* Prior functions from legacy API, deprecated */ +extern int sm_keystore_slot_encapsulate(struct device *dev, u32 unit, + u32 inslot, u32 outslot, u16 secretlen, + u8 *keymod, u16 keymodlen); +extern int sm_keystore_slot_decapsulate(struct device *dev, u32 unit, + u32 inslot, u32 outslot, u16 secretlen, + u8 *keymod, u16 keymodlen); + +/* Data structure to hold per-slot information */ +struct keystore_data_slot_info { + u8 allocated; /* Track slot assignments */ + u32 key_length; /* Size of the key */ +}; + +/* Data structure to hold keystore information */ +struct keystore_data { + void *base_address; /* Virtual base of secure memory pages */ + void *phys_address; /* Physical base of secure memory pages */ + u32 slot_count; /* Number of slots in the keystore */ + struct keystore_data_slot_info *slot; /* Per-slot information */ +}; + +/* store the detected attributes of a secure memory page */ +struct sm_page_descriptor { + u16 phys_pagenum; /* may be discontiguous */ + u16 own_part; /* Owning partition */ + void *pg_base; /* Calculated virtual address */ + void *pg_phys; /* Calculated physical address */ + struct keystore_data *ksdata; +}; + +struct caam_drv_private_sm { + struct device *parentdev; /* this ends up as the controller */ + struct device *smringdev; /* ring that owns this instance */ + struct platform_device *sm_pdev; /* Secure Memory platform device */ + spinlock_t kslock ____cacheline_aligned; + + /* SM Register offset from JR base address */ + u32 sm_reg_offset; + + /* Default parameters for geometry */ + u32 max_pages; /* maximum pages this instance can support */ + u32 top_partition; /* highest partition number in this instance */ + u32 top_page; /* highest page number in this instance */ + u32 page_size; /* page size */ + u32 slot_size; /* selected size of each storage block */ + + /* Partition/Page Allocation Map */ + u32 localpages; /* Number of pages we can access */ + struct sm_page_descriptor *pagedesc; /* Allocated per-page */ + + /* Installed handlers for keystore access */ + int (*data_init)(struct device *dev, u32 unit); + void (*data_cleanup)(struct device *dev, u32 unit); + int (*slot_alloc)(struct device *dev, u32 unit, u32 size, u32 *slot); + int (*slot_dealloc)(struct device *dev, u32 unit, u32 slot); + void *(*slot_get_address)(struct device *dev, u32 unit, u32 handle); + void *(*slot_get_physical)(struct device *dev, u32 unit, u32 handle); + u32 (*slot_get_base)(struct device *dev, u32 unit, u32 handle); + u32 (*slot_get_offset)(struct device *dev, u32 unit, u32 handle); + u32 (*slot_get_slot_size)(struct device *dev, u32 unit, u32 handle); +}; + +#endif /* SM_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/sm_store.c linux-imx-phytec/drivers/crypto/caam/sm_store.c --- linux-6.1.55/drivers/crypto/caam/sm_store.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/sm_store.c 2024-06-19 12:33:59.748217327 +0200 @@ -0,0 +1,1270 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * CAAM Secure Memory Storage Interface + * + * Copyright 2008-2015 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * + * Loosely based on the SHW Keystore API for SCC/SCC2 + * Experimental implementation and NOT intended for upstream use. Expect + * this interface to be amended significantly in the future once it becomes + * integrated into live applications. + * + * Known issues: + * + * - Executes one instance of an secure memory "driver". This is tied to the + * fact that job rings can't run as standalone instances in the present + * configuration. + * + * - It does not expose a userspace interface. The value of a userspace + * interface for access to secrets is a point for further architectural + * discussion. + * + * - Partition/permission management is not part of this interface. It + * depends on some level of "knowledge" agreed upon between bootloader, + * provisioning applications, and OS-hosted software (which uses this + * driver). + * + * - No means of identifying the location or purpose of secrets managed by + * this interface exists; "slot location" and format of a given secret + * needs to be agreed upon between bootloader, provisioner, and OS-hosted + * application. + */ + +#include "compat.h" +#include "regs.h" +#include "jr.h" +#include "desc.h" +#include "intern.h" +#include "error.h" +#include "sm.h" +#include + +#define SECMEM_KEYMOD_LEN 8 +#define GENMEM_KEYMOD_LEN 16 + +#ifdef SM_DEBUG_CONT +void sm_show_page(struct device *dev, struct sm_page_descriptor *pgdesc) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + u32 i, *smdata; + + dev_info(dev, "physical page %d content at 0x%08x\n", + pgdesc->phys_pagenum, pgdesc->pg_base); + smdata = pgdesc->pg_base; + for (i = 0; i < (smpriv->page_size / sizeof(u32)); i += 4) + dev_info(dev, "[0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n", + (u32)&smdata[i], smdata[i], smdata[i+1], smdata[i+2], + smdata[i+3]); +} +#endif + +#define INITIAL_DESCSZ 16 /* size of tmp buffer for descriptor const. */ + +static __always_inline u32 sm_send_cmd(struct caam_drv_private_sm *smpriv, + struct caam_drv_private_jr *jrpriv, + u32 cmd, u32 *status) +{ + void __iomem *write_address; + void __iomem *read_address; + + if (smpriv->sm_reg_offset == SM_V1_OFFSET) { + struct caam_secure_mem_v1 *sm_regs_v1; + + sm_regs_v1 = (struct caam_secure_mem_v1 *) + ((void *)jrpriv->rregs + SM_V1_OFFSET); + write_address = &sm_regs_v1->sm_cmd; + read_address = &sm_regs_v1->sm_status; + + } else if (smpriv->sm_reg_offset == SM_V2_OFFSET) { + struct caam_secure_mem_v2 *sm_regs_v2; + + sm_regs_v2 = (struct caam_secure_mem_v2 *) + ((void *)jrpriv->rregs + SM_V2_OFFSET); + write_address = &sm_regs_v2->sm_cmd; + read_address = &sm_regs_v2->sm_status; + + } else { + return -EINVAL; + } + + wr_reg32(write_address, cmd); + + udelay(10); + + /* Read until the command has terminated and the status is correct */ + do { + *status = rd_reg32(read_address); + } while (((*status & SMCS_CMDERR_MASK) >> SMCS_CMDERR_SHIFT) + == SMCS_CMDERR_INCOMP); + + return 0; +} + +/* + * Construct a black key conversion job descriptor + * + * This function constructs a job descriptor capable of performing + * a key blackening operation on a plaintext secure memory resident object. + * + * - desc pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * - key physical pointer to the plaintext, which will also hold + * the result. Since encryption occurs in place, caller must + * ensure that the space is large enough to accommodate the + * blackened key + * - keysz size of the plaintext + * - auth if a CCM-covered key is required, use KEY_COVER_CCM, else + * use KEY_COVER_ECB. + * + * KEY to key1 from @key_addr LENGTH 16 BYTES; + * FIFO STORE from key1[ecb] TO @key_addr LENGTH 16 BYTES; + * + * Note that this variant uses the JDKEK only; it does not accommodate the + * trusted key encryption key at this time. + * + */ +static int blacken_key_jobdesc(u32 **desc, void *key, u16 keysz, bool auth) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize, idx; + + memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); + idx = 1; + + /* Load key to class 1 key register */ + tmpdesc[idx++] = CMD_KEY | CLASS_1 | (keysz & KEY_LENGTH_MASK); + tmpdesc[idx++] = (uintptr_t)key; + + /* ...and write back out via FIFO store*/ + tmpdesc[idx] = CMD_FIFO_STORE | CLASS_1 | (keysz & KEY_LENGTH_MASK); + + /* plus account for ECB/CCM option in FIFO_STORE */ + if (auth == KEY_COVER_ECB) + tmpdesc[idx] |= FIFOST_TYPE_KEY_KEK; + else + tmpdesc[idx] |= FIFOST_TYPE_KEY_CCM_JKEK; + + idx++; + tmpdesc[idx++] = (uintptr_t)key; + + /* finish off the job header */ + tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); + dsize = idx * sizeof(u32); + + /* now allocate execution buffer and coat it with executable */ + tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); + if (tdesc == NULL) + return 0; + + memcpy(tdesc, tmpdesc, dsize); + *desc = tdesc; + + return dsize; +} + +/* + * Construct a blob encapsulation job descriptor + * + * This function dynamically constructs a blob encapsulation job descriptor + * from the following arguments: + * + * - desc pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * - keymod Physical pointer to a key modifier, which must reside in a + * contiguous piece of memory. Modifier will be assumed to be + * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long + * for a blob of type SM_GENMEM (see blobtype argument). + * - secretbuf Physical pointer to a secret, normally a black or red key, + * possibly residing within an accessible secure memory page, + * of the secret to be encapsulated to an output blob. + * - outbuf Physical pointer to the destination buffer to receive the + * encapsulated output. This buffer will need to be 48 bytes + * larger than the input because of the added encapsulation data. + * The generated descriptor will account for the increase in size, + * but the caller must also account for this increase in the + * buffer allocator. + * - secretsz Size of input secret, in bytes. This is limited to 65536 + * less the size of blob overhead, since the length embeds into + * DECO pointer in/out instructions. + * - keycolor Determines if the source data is covered (black key) or + * plaintext (red key). RED_KEY or BLACK_KEY are defined in + * for this purpose. + * - blobtype Determine if encapsulated blob should be a secure memory + * blob (SM_SECMEM), with partition data embedded with key + * material, or a general memory blob (SM_GENMEM). + * - auth If BLACK_KEY source is covered via AES-CCM, specify + * KEY_COVER_CCM, else uses AES-ECB (KEY_COVER_ECB). + * + * Upon completion, desc points to a buffer containing a CAAM job + * descriptor which encapsulates data into an externally-storable blob + * suitable for use across power cycles. + * + * This is an example of a black key encapsulation job into a general memory + * blob. Notice the 16-byte key modifier in the LOAD instruction. Also note + * the output 48 bytes longer than the input: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400010 ld: ccb2-key len=16 offs=0 + * [02] 08144891 ptr->@0x08144891 + * [03] F800003A seqoutptr: len=58 + * [04] 01000000 out_ptr->@0x01000000 + * [05] F000000A seqinptr: len=10 + * [06] 09745090 in_ptr->@0x09745090 + * [07] 870D0004 operation: encap blob reg=memory, black, format=normal + * + * This is an example of a red key encapsulation job for storing a red key + * into a secure memory blob. Note the 8 byte modifier on the 12 byte offset + * in the LOAD instruction; this accounts for blob permission storage: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400C08 ld: ccb2-key len=8 offs=12 + * [02] 087D0784 ptr->@0x087d0784 + * [03] F8000050 seqoutptr: len=80 + * [04] 09251BB2 out_ptr->@0x09251bb2 + * [05] F0000020 seqinptr: len=32 + * [06] 40000F31 in_ptr->@0x40000f31 + * [07] 870D0008 operation: encap blob reg=memory, red, sec_mem, + * format=normal + * + * Note: this function only generates 32-bit pointers at present, and should + * be refactored using a scheme that allows both 32 and 64 bit addressing + */ + +static int blob_encap_jobdesc(u32 **desc, dma_addr_t keymod, + void *secretbuf, dma_addr_t outbuf, + u16 secretsz, u8 keycolor, u8 blobtype, u8 auth) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize, idx; + + memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); + idx = 1; + + /* + * Key modifier works differently for secure/general memory blobs + * This accounts for the permission/protection data encapsulated + * within the blob if a secure memory blob is requested + */ + if (blobtype == SM_SECMEM) + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | + ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) + | (8 & LDST_LEN_MASK); + else /* is general memory blob */ + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK); + + tmpdesc[idx++] = (u32)keymod; + + /* + * Encapsulation output must include space for blob key encryption + * key and MAC tag + */ + tmpdesc[idx++] = CMD_SEQ_OUT_PTR | (secretsz + BLOB_OVERHEAD); + tmpdesc[idx++] = (u32)outbuf; + + /* Input data, should be somewhere in secure memory */ + tmpdesc[idx++] = CMD_SEQ_IN_PTR | secretsz; + tmpdesc[idx++] = (uintptr_t)secretbuf; + + /* Set blob encap, then color */ + tmpdesc[idx] = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB; + + if (blobtype == SM_SECMEM) + tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; + + if (auth == KEY_COVER_CCM) + tmpdesc[idx] |= OP_PCL_BLOB_EKT; + + if (keycolor == BLACK_KEY) + tmpdesc[idx] |= OP_PCL_BLOB_BLACK; + + idx++; + tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); + dsize = idx * sizeof(u32); + + tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); + if (tdesc == NULL) + return 0; + + memcpy(tdesc, tmpdesc, dsize); + *desc = tdesc; + return dsize; +} + +/* + * Construct a blob decapsulation job descriptor + * + * This function dynamically constructs a blob decapsulation job descriptor + * from the following arguments: + * + * - desc pointer to a pointer to the descriptor generated by this + * function. Caller will be responsible to kfree() this + * descriptor after execution. + * - keymod Physical pointer to a key modifier, which must reside in a + * contiguous piece of memory. Modifier will be assumed to be + * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long + * for a blob of type SM_GENMEM (see blobtype argument). + * - blobbuf Physical pointer (into external memory) of the blob to + * be decapsulated. Blob must reside in a contiguous memory + * segment. + * - outbuf Physical pointer of the decapsulated output, possibly into + * a location within a secure memory page. Must be contiguous. + * - secretsz Size of encapsulated secret in bytes (not the size of the + * input blob). + * - keycolor Determines if decapsulated content is encrypted (BLACK_KEY) + * or left as plaintext (RED_KEY). + * - blobtype Determine if encapsulated blob should be a secure memory + * blob (SM_SECMEM), with partition data embedded with key + * material, or a general memory blob (SM_GENMEM). + * - auth If decapsulation path is specified by BLACK_KEY, then if + * AES-CCM is requested for key covering use KEY_COVER_CCM, else + * use AES-ECB (KEY_COVER_ECB). + * + * Upon completion, desc points to a buffer containing a CAAM job descriptor + * that decapsulates a key blob from external memory into a black (encrypted) + * key or red (plaintext) content. + * + * This is an example of a black key decapsulation job from a general memory + * blob. Notice the 16-byte key modifier in the LOAD instruction. + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400010 ld: ccb2-key len=16 offs=0 + * [02] 08A63B7F ptr->@0x08a63b7f + * [03] F8000010 seqoutptr: len=16 + * [04] 01000000 out_ptr->@0x01000000 + * [05] F000003A seqinptr: len=58 + * [06] 01000010 in_ptr->@0x01000010 + * [07] 860D0004 operation: decap blob reg=memory, black, format=normal + * + * This is an example of a red key decapsulation job for restoring a red key + * from a secure memory blob. Note the 8 byte modifier on the 12 byte offset + * in the LOAD instruction: + * + * [00] B0800008 jobhdr: stidx=0 len=8 + * [01] 14400C08 ld: ccb2-key len=8 offs=12 + * [02] 01000000 ptr->@0x01000000 + * [03] F8000020 seqoutptr: len=32 + * [04] 400000E6 out_ptr->@0x400000e6 + * [05] F0000050 seqinptr: len=80 + * [06] 08F0C0EA in_ptr->@0x08f0c0ea + * [07] 860D0008 operation: decap blob reg=memory, red, sec_mem, + * format=normal + * + * Note: this function only generates 32-bit pointers at present, and should + * be refactored using a scheme that allows both 32 and 64 bit addressing + */ + +static int blob_decap_jobdesc(u32 **desc, dma_addr_t keymod, dma_addr_t blobbuf, + u8 *outbuf, u16 secretsz, u8 keycolor, + u8 blobtype, u8 auth) +{ + u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; + u16 dsize, idx; + + memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); + idx = 1; + + /* Load key modifier */ + if (blobtype == SM_SECMEM) + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | + ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) + | (8 & LDST_LEN_MASK); + else /* is general memory blob */ + tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK); + + tmpdesc[idx++] = (u32)keymod; + + /* Compensate BKEK + MAC tag over size of encapsulated secret */ + tmpdesc[idx++] = CMD_SEQ_IN_PTR | (secretsz + BLOB_OVERHEAD); + tmpdesc[idx++] = (u32)blobbuf; + tmpdesc[idx++] = CMD_SEQ_OUT_PTR | secretsz; + tmpdesc[idx++] = (uintptr_t)outbuf; + + /* Decapsulate from secure memory partition to black blob */ + tmpdesc[idx] = CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB; + + if (blobtype == SM_SECMEM) + tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; + + if (auth == KEY_COVER_CCM) + tmpdesc[idx] |= OP_PCL_BLOB_EKT; + + if (keycolor == BLACK_KEY) + tmpdesc[idx] |= OP_PCL_BLOB_BLACK; + + idx++; + tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); + dsize = idx * sizeof(u32); + + tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); + if (tdesc == NULL) + return 0; + + memcpy(tdesc, tmpdesc, dsize); + *desc = tdesc; + return dsize; +} + +/* + * Pseudo-synchronous ring access functions for carrying out key + * encapsulation and decapsulation + */ + +struct sm_key_job_result { + int error; + struct completion completion; +}; + +void sm_key_job_done(struct device *dev, u32 *desc, u32 err, void *context) +{ + struct sm_key_job_result *res = context; + + if (err) + caam_jr_strstatus(dev, err); + + res->error = err; /* save off the error for postprocessing */ + + complete(&res->completion); /* mark us complete */ +} + +static int sm_key_job(struct device *ksdev, u32 *jobdesc) +{ + struct sm_key_job_result testres = {0}; + struct caam_drv_private_sm *kspriv; + int rtn = 0; + + kspriv = dev_get_drvdata(ksdev); + + init_completion(&testres.completion); + + rtn = caam_jr_enqueue(kspriv->smringdev, jobdesc, sm_key_job_done, + &testres); + if (rtn != -EINPROGRESS) + goto exit; + + wait_for_completion(&testres.completion); + rtn = testres.error; + +exit: + return rtn; +} + +/* + * Following section establishes the default methods for keystore access + * They are NOT intended for use external to this module + * + * In the present version, these are the only means for the higher-level + * interface to deal with the mechanics of accessing the phyiscal keystore + */ + + +int slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + u32 i; +#ifdef SM_DEBUG + dev_info(dev, "slot_alloc(): requesting slot for %d bytes\n", size); +#endif + + if (size > smpriv->slot_size) + return -EKEYREJECTED; + + for (i = 0; i < ksdata->slot_count; i++) { + if (ksdata->slot[i].allocated == 0) { + ksdata->slot[i].allocated = 1; + (*slot) = i; +#ifdef SM_DEBUG + dev_info(dev, "slot_alloc(): new slot %d allocated\n", + *slot); +#endif + return 0; + } + } + + return -ENOSPC; +} +EXPORT_SYMBOL(slot_alloc); + +int slot_dealloc(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + u8 __iomem *slotdata; + +#ifdef SM_DEBUG + dev_info(dev, "slot_dealloc(): releasing slot %d\n", slot); +#endif + if (slot >= ksdata->slot_count) + return -EINVAL; + slotdata = ksdata->base_address + slot * smpriv->slot_size; + + if (ksdata->slot[slot].allocated == 1) { + /* Forcibly overwrite the data from the keystore */ + memset_io(ksdata->base_address + slot * smpriv->slot_size, 0, + smpriv->slot_size); + + ksdata->slot[slot].allocated = 0; +#ifdef SM_DEBUG + dev_info(dev, "slot_dealloc(): slot %d released\n", slot); +#endif + return 0; + } + + return -EINVAL; +} +EXPORT_SYMBOL(slot_dealloc); + +void *slot_get_address(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + if (slot >= ksdata->slot_count) + return NULL; + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_address(): slot %d is 0x%08x\n", slot, + (u32)ksdata->base_address + slot * smpriv->slot_size); +#endif + + return ksdata->base_address + slot * smpriv->slot_size; +} + +void *slot_get_physical(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + if (slot >= ksdata->slot_count) + return NULL; + +#ifdef SM_DEBUG + dev_info(dev, "%s: slot %d is 0x%08x\n", __func__, slot, + (u32)ksdata->phys_address + slot * smpriv->slot_size); +#endif + + return ksdata->phys_address + slot * smpriv->slot_size; +} + +u32 slot_get_base(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + /* + * There could potentially be more than one secure partition object + * associated with this keystore. For now, there is just one. + */ + + (void)slot; + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_base(): slot %d = 0x%08x\n", + slot, (u32)ksdata->base_address); +#endif + + return (uintptr_t)(ksdata->base_address); +} + +u32 slot_get_offset(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; + + if (slot >= ksdata->slot_count) + return -EINVAL; + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_offset(): slot %d = %d\n", slot, + slot * smpriv->slot_size); +#endif + + return slot * smpriv->slot_size; +} + +u32 slot_get_slot_size(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + + +#ifdef SM_DEBUG + dev_info(dev, "slot_get_slot_size(): slot %d = %d\n", slot, + smpriv->slot_size); +#endif + /* All slots are the same size in the default implementation */ + return smpriv->slot_size; +} + + + +int kso_init_data(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *keystore_data = NULL; + u32 slot_count; + u32 keystore_data_size; + + /* + * Calculate the required size of the keystore data structure, based + * on the number of keys that can fit in the partition. + */ + slot_count = smpriv->page_size / smpriv->slot_size; +#ifdef SM_DEBUG + dev_info(dev, "kso_init_data: %d slots initializing\n", slot_count); +#endif + + keystore_data_size = sizeof(struct keystore_data) + + slot_count * + sizeof(struct keystore_data_slot_info); + + keystore_data = kzalloc(keystore_data_size, GFP_KERNEL); + + if (!keystore_data) + return -ENOMEM; + +#ifdef SM_DEBUG + dev_info(dev, "kso_init_data: keystore data size = %d\n", + keystore_data_size); +#endif + + /* + * Place the slot information structure directly after the keystore data + * structure. + */ + keystore_data->slot = (struct keystore_data_slot_info *) + (keystore_data + 1); + keystore_data->slot_count = slot_count; + + smpriv->pagedesc[unit].ksdata = keystore_data; + smpriv->pagedesc[unit].ksdata->base_address = + smpriv->pagedesc[unit].pg_base; + smpriv->pagedesc[unit].ksdata->phys_address = + smpriv->pagedesc[unit].pg_phys; + + return 0; +} + +void kso_cleanup_data(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + struct keystore_data *keystore_data = NULL; + + if (smpriv->pagedesc[unit].ksdata != NULL) + keystore_data = smpriv->pagedesc[unit].ksdata; + + /* Release the allocated keystore management data */ + kfree(smpriv->pagedesc[unit].ksdata); + + return; +} + + + +/* + * Keystore management section + */ + +void sm_init_keystore(struct device *dev) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + + smpriv->data_init = kso_init_data; + smpriv->data_cleanup = kso_cleanup_data; + smpriv->slot_alloc = slot_alloc; + smpriv->slot_dealloc = slot_dealloc; + smpriv->slot_get_address = slot_get_address; + smpriv->slot_get_physical = slot_get_physical; + smpriv->slot_get_base = slot_get_base; + smpriv->slot_get_offset = slot_get_offset; + smpriv->slot_get_slot_size = slot_get_slot_size; +#ifdef SM_DEBUG + dev_info(dev, "sm_init_keystore(): handlers installed\n"); +#endif +} +EXPORT_SYMBOL(sm_init_keystore); + +/* Return available pages/units */ +u32 sm_detect_keystore_units(struct device *dev) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + + return smpriv->localpages; +} +EXPORT_SYMBOL(sm_detect_keystore_units); + +/* + * Do any keystore specific initializations + */ +int sm_establish_keystore(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + +#ifdef SM_DEBUG + dev_info(dev, "sm_establish_keystore(): unit %d initializing\n", unit); +#endif + + if (smpriv->data_init == NULL) + return -EINVAL; + + /* Call the data_init function for any user setup */ + return smpriv->data_init(dev, unit); +} +EXPORT_SYMBOL(sm_establish_keystore); + +void sm_release_keystore(struct device *dev, u32 unit) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + +#ifdef SM_DEBUG + dev_info(dev, "sm_establish_keystore(): unit %d releasing\n", unit); +#endif + if ((smpriv != NULL) && (smpriv->data_cleanup != NULL)) + smpriv->data_cleanup(dev, unit); + + return; +} +EXPORT_SYMBOL(sm_release_keystore); + +/* + * Subsequent interfacce (sm_keystore_*) forms the accessor interfacce to + * the keystore + */ +int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + + spin_lock(&smpriv->kslock); + + if ((smpriv->slot_alloc == NULL) || + (smpriv->pagedesc[unit].ksdata == NULL)) + goto out; + + retval = smpriv->slot_alloc(dev, unit, size, slot); + +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_alloc); + +int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + + spin_lock(&smpriv->kslock); + + if ((smpriv->slot_alloc == NULL) || + (smpriv->pagedesc[unit].ksdata == NULL)) + goto out; + + retval = smpriv->slot_dealloc(dev, unit, slot); +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_dealloc); + +int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot, + const u8 *key_data, u32 key_length) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + u32 slot_size; + u8 __iomem *slot_location; + + spin_lock(&smpriv->kslock); + + slot_size = smpriv->slot_get_slot_size(dev, unit, slot); + + if (key_length > slot_size) { + retval = -EFBIG; + goto out; + } + + slot_location = smpriv->slot_get_address(dev, unit, slot); + + memcpy_toio(slot_location, key_data, key_length); + + retval = 0; + +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_load); + +int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot, + u32 key_length, u8 *key_data) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = -EINVAL; + u8 __iomem *slot_addr; + u32 slot_size; + + spin_lock(&smpriv->kslock); + + slot_addr = smpriv->slot_get_address(dev, unit, slot); + slot_size = smpriv->slot_get_slot_size(dev, unit, slot); + + if (key_length > slot_size) { + retval = -EKEYREJECTED; + goto out; + } + + memcpy_fromio(key_data, slot_addr, key_length); + retval = 0; + +out: + spin_unlock(&smpriv->kslock); + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_read); + +/* + * Blacken a clear key in a slot. Operates "in place". + * Limited to class 1 keys at the present time + */ +int sm_keystore_cover_key(struct device *dev, u32 unit, u32 slot, + u16 key_length, u8 keyauth) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = 0; + u8 __iomem *slotaddr; + void *slotphys; + u32 dsize, jstat; + u32 __iomem *coverdesc = NULL; + + /* Get the address of the object in the slot */ + slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); + slotphys = (u8 *)smpriv->slot_get_physical(dev, unit, slot); + + dsize = blacken_key_jobdesc(&coverdesc, slotphys, key_length, keyauth); + if (!dsize) + return -ENOMEM; + jstat = sm_key_job(dev, coverdesc); + if (jstat) + retval = -EIO; + + kfree(coverdesc); + return retval; +} +EXPORT_SYMBOL(sm_keystore_cover_key); + +/* Export a black/red key to a blob in external memory */ +int sm_keystore_slot_export(struct device *dev, u32 unit, u32 slot, u8 keycolor, + u8 keyauth, u8 *outbuf, u16 keylen, u8 *keymod) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = 0; + u8 __iomem *slotaddr, *lkeymod; + u8 __iomem *slotphys; + dma_addr_t keymod_dma, outbuf_dma; + u32 dsize, jstat; + u32 __iomem *encapdesc = NULL; + struct device *dev_for_dma_op; + + /* Use the ring as device for DMA operations */ + dev_for_dma_op = smpriv->smringdev; + + /* Get the base address(es) of the specified slot */ + slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); + slotphys = smpriv->slot_get_physical(dev, unit, slot); + + /* Allocate memory for key modifier compatible with DMA */ + lkeymod = kmalloc(SECMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA); + if (!lkeymod) { + retval = (-ENOMEM); + goto exit; + } + + /* Get DMA address for the key modifier */ + keymod_dma = dma_map_single(dev_for_dma_op, lkeymod, + SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); + if (dma_mapping_error(dev_for_dma_op, keymod_dma)) { + dev_err(dev, "unable to map keymod: %p\n", lkeymod); + retval = (-ENOMEM); + goto free_keymod; + } + + /* Copy the keymod and synchronize the DMA */ + memcpy(lkeymod, keymod, SECMEM_KEYMOD_LEN); + dma_sync_single_for_device(dev_for_dma_op, keymod_dma, + SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); + + /* Get DMA address for the destination */ + outbuf_dma = dma_map_single(dev_for_dma_op, outbuf, + keylen + BLOB_OVERHEAD, DMA_FROM_DEVICE); + if (dma_mapping_error(dev_for_dma_op, outbuf_dma)) { + dev_err(dev, "unable to map outbuf: %p\n", outbuf); + retval = (-ENOMEM); + goto unmap_keymod; + } + + /* Build the encapsulation job descriptor */ + dsize = blob_encap_jobdesc(&encapdesc, keymod_dma, slotphys, outbuf_dma, + keylen, keycolor, SM_SECMEM, keyauth); + if (!dsize) { + dev_err(dev, "can't alloc an encapsulation descriptor\n"); + retval = -ENOMEM; + goto unmap_outbuf; + } + + /* Run the job */ + jstat = sm_key_job(dev, encapdesc); + if (jstat) { + retval = (-EIO); + goto free_desc; + } + + /* Synchronize the data received */ + dma_sync_single_for_cpu(dev_for_dma_op, outbuf_dma, + keylen + BLOB_OVERHEAD, DMA_FROM_DEVICE); + +free_desc: + kfree(encapdesc); + +unmap_outbuf: + dma_unmap_single(dev_for_dma_op, outbuf_dma, keylen + BLOB_OVERHEAD, + DMA_FROM_DEVICE); + +unmap_keymod: + dma_unmap_single(dev_for_dma_op, keymod_dma, SECMEM_KEYMOD_LEN, + DMA_TO_DEVICE); + +free_keymod: + kfree(lkeymod); + +exit: + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_export); + +/* Import a black/red key from a blob residing in external memory */ +int sm_keystore_slot_import(struct device *dev, u32 unit, u32 slot, u8 keycolor, + u8 keyauth, u8 *inbuf, u16 keylen, u8 *keymod) +{ + struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); + int retval = 0; + u8 __iomem *slotaddr, *lkeymod; + u8 __iomem *slotphys; + dma_addr_t keymod_dma, inbuf_dma; + u32 dsize, jstat; + u32 __iomem *decapdesc = NULL; + struct device *dev_for_dma_op; + + /* Use the ring as device for DMA operations */ + dev_for_dma_op = smpriv->smringdev; + + /* Get the base address(es) of the specified slot */ + slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot); + slotphys = smpriv->slot_get_physical(dev, unit, slot); + + /* Allocate memory for key modifier compatible with DMA */ + lkeymod = kmalloc(SECMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA); + if (!lkeymod) { + retval = (-ENOMEM); + goto exit; + } + + /* Get DMA address for the key modifier */ + keymod_dma = dma_map_single(dev_for_dma_op, lkeymod, + SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); + if (dma_mapping_error(dev_for_dma_op, keymod_dma)) { + dev_err(dev, "unable to map keymod: %p\n", lkeymod); + retval = (-ENOMEM); + goto free_keymod; + } + + /* Copy the keymod and synchronize the DMA */ + memcpy(lkeymod, keymod, SECMEM_KEYMOD_LEN); + dma_sync_single_for_device(dev_for_dma_op, keymod_dma, + SECMEM_KEYMOD_LEN, DMA_TO_DEVICE); + + /* Get DMA address for the input */ + inbuf_dma = dma_map_single(dev_for_dma_op, inbuf, + keylen + BLOB_OVERHEAD, DMA_TO_DEVICE); + if (dma_mapping_error(dev_for_dma_op, inbuf_dma)) { + dev_err(dev, "unable to map inbuf: %p\n", inbuf); + retval = (-ENOMEM); + goto unmap_keymod; + } + + /* synchronize the DMA */ + dma_sync_single_for_device(dev_for_dma_op, inbuf_dma, + keylen + BLOB_OVERHEAD, DMA_TO_DEVICE); + + /* Build the encapsulation job descriptor */ + dsize = blob_decap_jobdesc(&decapdesc, keymod_dma, inbuf_dma, slotphys, + keylen, keycolor, SM_SECMEM, keyauth); + if (!dsize) { + dev_err(dev, "can't alloc a decapsulation descriptor\n"); + retval = -ENOMEM; + goto unmap_inbuf; + } + + /* Run the job */ + jstat = sm_key_job(dev, decapdesc); + + /* + * May want to expand upon error meanings a bit. Any CAAM status + * is reported as EIO, but we might want to look for something more + * meaningful for something like an ICV error on restore, otherwise + * the caller is left guessing. + */ + if (jstat) { + retval = (-EIO); + goto free_desc; + } + +free_desc: + kfree(decapdesc); + +unmap_inbuf: + dma_unmap_single(dev_for_dma_op, inbuf_dma, keylen + BLOB_OVERHEAD, + DMA_TO_DEVICE); + +unmap_keymod: + dma_unmap_single(dev_for_dma_op, keymod_dma, SECMEM_KEYMOD_LEN, + DMA_TO_DEVICE); + +free_keymod: + kfree(lkeymod); + +exit: + return retval; +} +EXPORT_SYMBOL(sm_keystore_slot_import); + +/* + * Initialization/shutdown subsystem + * Assumes statically-invoked startup/shutdown from the controller driver + * for the present time, to be reworked when a device tree becomes + * available. This code will not modularize in present form. + * + * Also, simply uses ring 0 for execution at the present + */ + +int caam_sm_startup(struct device *ctrldev) +{ + struct device *smdev; + struct caam_drv_private *ctrlpriv; + struct caam_drv_private_sm *smpriv; + struct caam_drv_private_jr *jrpriv; /* need this for reg page */ + struct platform_device *sm_pdev; + struct sm_page_descriptor *lpagedesc; + u32 page, pgstat, lpagect, detectedpage, smvid, smpart; + int ret = 0; + + struct device_node *np; + ctrlpriv = dev_get_drvdata(ctrldev); + + if (!ctrlpriv->sm_present) + return 0; + + /* + * Set up the private block for secure memory + * Only one instance is possible + */ + smpriv = kzalloc(sizeof(struct caam_drv_private_sm), GFP_KERNEL); + if (smpriv == NULL) { + dev_err(ctrldev, "can't alloc private mem for secure memory\n"); + ret = -ENOMEM; + goto exit; + } + smpriv->parentdev = ctrldev; /* copy of parent dev is handy */ + spin_lock_init(&smpriv->kslock); + + /* Create the dev */ + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm"); + if (np) + of_node_clear_flag(np, OF_POPULATED); + sm_pdev = of_platform_device_create(np, "caam_sm", ctrldev); + + if (sm_pdev == NULL) { + ret = -EINVAL; + goto free_smpriv; + } + + /* Save a pointer to the platform device for Secure Memory */ + smpriv->sm_pdev = sm_pdev; + smdev = &sm_pdev->dev; + dev_set_drvdata(smdev, smpriv); + ctrlpriv->smdev = smdev; + + /* Set the Secure Memory Register Map Version */ + smvid = rd_reg32(&ctrlpriv->jr[0]->perfmon.smvid); + smpart = rd_reg32(&ctrlpriv->jr[0]->perfmon.smpart); + + if (smvid < SMVID_V2) + smpriv->sm_reg_offset = SM_V1_OFFSET; + else + smpriv->sm_reg_offset = SM_V2_OFFSET; + + /* + * Collect configuration limit data for reference + * This batch comes from the partition data/vid registers in perfmon + */ + smpriv->max_pages = ((smpart & SMPART_MAX_NUMPG_MASK) >> + SMPART_MAX_NUMPG_SHIFT) + 1; + smpriv->top_partition = ((smpart & SMPART_MAX_PNUM_MASK) >> + SMPART_MAX_PNUM_SHIFT) + 1; + smpriv->top_page = ((smpart & SMPART_MAX_PG_MASK) >> + SMPART_MAX_PG_SHIFT) + 1; + smpriv->page_size = 1024 << ((smvid & SMVID_PG_SIZE_MASK) >> + SMVID_PG_SIZE_SHIFT); + smpriv->slot_size = 1 << CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE; + +#ifdef SM_DEBUG + dev_info(smdev, "max pages = %d, top partition = %d\n", + smpriv->max_pages, smpriv->top_partition); + dev_info(smdev, "top page = %d, page size = %d (total = %d)\n", + smpriv->top_page, smpriv->page_size, + smpriv->top_page * smpriv->page_size); + dev_info(smdev, "selected slot size = %d\n", smpriv->slot_size); +#endif + + /* + * Now probe for partitions/pages to which we have access. Note that + * these have likely been set up by a bootloader or platform + * provisioning application, so we have to assume that we "inherit" + * a configuration and work within the constraints of what it might be. + * + * Assume use of the zeroth ring in the present iteration (until + * we can divorce the controller and ring drivers, and then assign + * an SM instance to any ring instance). + */ + smpriv->smringdev = caam_jr_alloc(); + if (!smpriv->smringdev) { + dev_err(smdev, "Device for job ring not created\n"); + ret = -ENODEV; + goto unregister_smpdev; + } + + jrpriv = dev_get_drvdata(smpriv->smringdev); + lpagect = 0; + pgstat = 0; + lpagedesc = kzalloc(sizeof(struct sm_page_descriptor) + * smpriv->max_pages, GFP_KERNEL); + if (lpagedesc == NULL) { + ret = -ENOMEM; + goto free_smringdev; + } + + for (page = 0; page < smpriv->max_pages; page++) { + u32 page_ownership; + + if (sm_send_cmd(smpriv, jrpriv, + ((page << SMC_PAGE_SHIFT) & SMC_PAGE_MASK) | + (SMC_CMD_PAGE_INQUIRY & SMC_CMD_MASK), + &pgstat)) { + ret = -EINVAL; + goto free_lpagedesc; + } + + page_ownership = (pgstat & SMCS_PGWON_MASK) >> SMCS_PGOWN_SHIFT; + if ((page_ownership == SMCS_PGOWN_OWNED) + || (page_ownership == SMCS_PGOWN_NOOWN)) { + /* page allocated */ + lpagedesc[page].phys_pagenum = + (pgstat & SMCS_PAGE_MASK) >> SMCS_PAGE_SHIFT; + lpagedesc[page].own_part = + (pgstat & SMCS_PART_SHIFT) >> SMCS_PART_MASK; + lpagedesc[page].pg_base = (u8 *)ctrlpriv->sm_base + + (smpriv->page_size * page); + if (ctrlpriv->scu_en) { +/* FIXME: get different addresses viewed by CPU and CAAM from + * platform property + */ + lpagedesc[page].pg_phys = (u8 *)0x20800000 + + (smpriv->page_size * page); + } else { + lpagedesc[page].pg_phys = + (u8 *) ctrlpriv->sm_phy + + (smpriv->page_size * page); + } + lpagect++; +#ifdef SM_DEBUG + dev_info(smdev, + "physical page %d, owning partition = %d\n", + lpagedesc[page].phys_pagenum, + lpagedesc[page].own_part); +#endif + } + } + + smpriv->pagedesc = kzalloc(sizeof(struct sm_page_descriptor) * lpagect, + GFP_KERNEL); + if (smpriv->pagedesc == NULL) { + ret = -ENOMEM; + goto free_lpagedesc; + } + smpriv->localpages = lpagect; + + detectedpage = 0; + for (page = 0; page < smpriv->max_pages; page++) { + if (lpagedesc[page].pg_base != NULL) { /* e.g. live entry */ + memcpy(&smpriv->pagedesc[detectedpage], + &lpagedesc[page], + sizeof(struct sm_page_descriptor)); +#ifdef SM_DEBUG_CONT + sm_show_page(smdev, &smpriv->pagedesc[detectedpage]); +#endif + detectedpage++; + } + } + + kfree(lpagedesc); + + sm_init_keystore(smdev); + + goto exit; + +free_lpagedesc: + kfree(lpagedesc); +free_smringdev: + caam_jr_free(smpriv->smringdev); +unregister_smpdev: + of_device_unregister(smpriv->sm_pdev); +free_smpriv: + kfree(smpriv); + +exit: + return ret; +} + +void caam_sm_shutdown(struct device *ctrldev) +{ + struct device *smdev; + struct caam_drv_private *priv; + struct caam_drv_private_sm *smpriv; + + priv = dev_get_drvdata(ctrldev); + if (!priv->sm_present) + return; + + smdev = priv->smdev; + + /* Return if resource not initialized by startup */ + if (smdev == NULL) + return; + + smpriv = dev_get_drvdata(smdev); + + caam_jr_free(smpriv->smringdev); + + /* Remove Secure Memory Platform Device */ + of_device_unregister(smpriv->sm_pdev); + + kfree(smpriv->pagedesc); + kfree(smpriv); +} +EXPORT_SYMBOL(caam_sm_shutdown); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/sm_test.c linux-imx-phytec/drivers/crypto/caam/sm_test.c --- linux-6.1.55/drivers/crypto/caam/sm_test.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/sm_test.c 2024-06-19 12:33:59.748217327 +0200 @@ -0,0 +1,586 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Secure Memory / Keystore Exemplification Module + * + * Copyright 2012-2015 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * + * This module has been overloaded as an example to show: + * - Secure memory subsystem initialization/shutdown + * - Allocation/deallocation of "slots" in a secure memory page + * - Loading and unloading of key material into slots + * - Covering of secure memory objects into "black keys" (ECB only at present) + * - Verification of key covering (by differentiation only) + * - Exportation of keys into secure memory blobs (with display of result) + * - Importation of keys from secure memory blobs (with display of result) + * - Verification of re-imported keys where possible. + * + * The module does not show the use of key objects as working key register + * source material at this time. + * + * This module can use a substantial amount of refactoring, which may occur + * after the API gets some mileage. Furthermore, expect this module to + * eventually disappear once the API is integrated into "real" software. + */ + +#include "compat.h" +#include "regs.h" +#include "intern.h" +#include "desc.h" +#include "error.h" +#include "jr.h" +#include "sm.h" + +/* Fixed known pattern for a key modifier */ +static u8 skeymod[] = { + 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, + 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 +}; + +/* Fixed known pattern for a key */ +static u8 clrkey[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x0f, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff +}; + +static void key_display(struct device *dev, const char *label, u16 size, + u8 *key) +{ + unsigned i; + + dev_dbg(dev, "%s", label); + for (i = 0; i < size; i += 8) + dev_dbg(dev, + "[%04d] %02x %02x %02x %02x %02x %02x %02x %02x\n", + i, key[i], key[i + 1], key[i + 2], key[i + 3], + key[i + 4], key[i + 5], key[i + 6], key[i + 7]); +} + +int caam_sm_example_init(struct platform_device *pdev) +{ + struct device *ctrldev, *ksdev; + struct caam_drv_private *ctrlpriv; + struct caam_drv_private_sm *kspriv; + u32 unit, units; + int rtnval; + u8 clrkey8[8], clrkey16[16], clrkey24[24], clrkey32[32]; + u8 blkkey8[AES_BLOCK_PAD(8)], blkkey16[AES_BLOCK_PAD(16)]; + u8 blkkey24[AES_BLOCK_PAD(24)], blkkey32[AES_BLOCK_PAD(32)]; + u8 rstkey8[AES_BLOCK_PAD(8)], rstkey16[AES_BLOCK_PAD(16)]; + u8 rstkey24[AES_BLOCK_PAD(24)], rstkey32[AES_BLOCK_PAD(32)]; + u8 __iomem *blob8, *blob16, *blob24, *blob32; + u32 keyslot8, keyslot16, keyslot24, keyslot32 = 0; + + blob8 = blob16 = blob24 = blob32 = NULL; + + /* + * 3.5.x and later revs for MX6 should be able to ditch this + * and detect via dts property + */ + ctrldev = &pdev->dev; + ctrlpriv = dev_get_drvdata(ctrldev); + + /* + * If ctrlpriv is NULL, it's probably because the caam driver wasn't + * properly initialized (e.g. RNG4 init failed). Thus, bail out here. + */ + if (!ctrlpriv) + return -ENODEV; + + ksdev = ctrlpriv->smdev; + kspriv = dev_get_drvdata(ksdev); + if (kspriv == NULL) + return -ENODEV; + + /* What keystores are available ? */ + units = sm_detect_keystore_units(ksdev); + if (!units) + dev_err(ksdev, "blkkey_ex: no keystore units available\n"); + + /* + * MX6 bootloader stores some stuff in unit 0, so let's + * use 1 or above + */ + if (units < 2) { + dev_err(ksdev, "blkkey_ex: insufficient keystore units\n"); + return -ENODEV; + } + unit = 1; + + dev_info(ksdev, "blkkey_ex: %d keystore units available\n", units); + + /* Initialize/Establish Keystore */ + sm_establish_keystore(ksdev, unit); /* Initalize store in #1 */ + + /* + * Now let's set up buffers for blobs in DMA-able memory. All are + * larger than need to be so that blob size can be seen. + */ + blob8 = kzalloc(128, GFP_KERNEL | GFP_DMA); + blob16 = kzalloc(128, GFP_KERNEL | GFP_DMA); + blob24 = kzalloc(128, GFP_KERNEL | GFP_DMA); + blob32 = kzalloc(128, GFP_KERNEL | GFP_DMA); + + if ((blob8 == NULL) || (blob16 == NULL) || (blob24 == NULL) || + (blob32 == NULL)) { + rtnval = -ENOMEM; + dev_err(ksdev, "blkkey_ex: can't get blob buffers\n"); + goto freemem; + } + + /* Initialize clear keys with a known and recognizable pattern */ + memcpy(clrkey8, clrkey, 8); + memcpy(clrkey16, clrkey, 16); + memcpy(clrkey24, clrkey, 24); + memcpy(clrkey32, clrkey, 32); + + memset(blkkey8, 0, AES_BLOCK_PAD(8)); + memset(blkkey16, 0, AES_BLOCK_PAD(16)); + memset(blkkey24, 0, AES_BLOCK_PAD(24)); + memset(blkkey32, 0, AES_BLOCK_PAD(32)); + + memset(rstkey8, 0, AES_BLOCK_PAD(8)); + memset(rstkey16, 0, AES_BLOCK_PAD(16)); + memset(rstkey24, 0, AES_BLOCK_PAD(24)); + memset(rstkey32, 0, AES_BLOCK_PAD(32)); + + /* + * Allocate keyslots. Since we're going to blacken keys in-place, + * we want slots big enough to pad out to the next larger AES blocksize + * so pad them out. + */ + rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(8), + &keyslot8); + if (rtnval) + goto freemem; + + rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(16), + &keyslot16); + if (rtnval) + goto dealloc_slot8; + + rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(24), + &keyslot24); + if (rtnval) + goto dealloc_slot16; + + rtnval = sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(32), + &keyslot32); + if (rtnval) + goto dealloc_slot24; + + + /* Now load clear key data into the newly allocated slots */ + rtnval = sm_keystore_slot_load(ksdev, unit, keyslot8, clrkey8, 8); + if (rtnval) + goto dealloc; + + rtnval = sm_keystore_slot_load(ksdev, unit, keyslot16, clrkey16, 16); + if (rtnval) + goto dealloc; + + rtnval = sm_keystore_slot_load(ksdev, unit, keyslot24, clrkey24, 24); + if (rtnval) + goto dealloc; + + rtnval = sm_keystore_slot_load(ksdev, unit, keyslot32, clrkey32, 32); + if (rtnval) + goto dealloc; + + /* + * All cleartext keys are loaded into slots (in an unprotected + * partition at this time) + * + * Cover keys in-place + */ + rtnval = sm_keystore_cover_key(ksdev, unit, keyslot8, 8, KEY_COVER_ECB); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't cover 64-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_cover_key(ksdev, unit, keyslot16, 16, + KEY_COVER_ECB); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't cover 128-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_cover_key(ksdev, unit, keyslot24, 24, + KEY_COVER_ECB); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't cover 192-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_cover_key(ksdev, unit, keyslot32, 32, + KEY_COVER_ECB); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't cover 256-bit key\n"); + goto dealloc; + } + + /* + * Keys should be covered and appear sufficiently "random" + * as a result of the covering (blackening) process. Assuming + * non-secure mode, read them back out for examination; they should + * appear as random data, completely differing from the clear + * inputs. So, this will read them back from secure memory and + * compare them. If they match the clear key, then the covering + * operation didn't occur. + */ + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot8, AES_BLOCK_PAD(8), + blkkey8); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't read 64-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot16, + AES_BLOCK_PAD(16), blkkey16); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't read 128-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot24, + AES_BLOCK_PAD(24), blkkey24); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't read 192-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot32, + AES_BLOCK_PAD(32), blkkey32); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't read 256-bit black key\n"); + goto dealloc; + } + + rtnval = -EINVAL; + if (!memcmp(blkkey8, clrkey8, 8)) { + dev_err(ksdev, "blkkey_ex: 64-bit key cover failed\n"); + goto dealloc; + } + + if (!memcmp(blkkey16, clrkey16, 16)) { + dev_err(ksdev, "blkkey_ex: 128-bit key cover failed\n"); + goto dealloc; + } + + if (!memcmp(blkkey24, clrkey24, 24)) { + dev_err(ksdev, "blkkey_ex: 192-bit key cover failed\n"); + goto dealloc; + } + + if (!memcmp(blkkey32, clrkey32, 32)) { + dev_err(ksdev, "blkkey_ex: 256-bit key cover failed\n"); + goto dealloc; + } + + + key_display(ksdev, "64-bit clear key:", 8, clrkey8); + key_display(ksdev, "64-bit black key:", AES_BLOCK_PAD(8), blkkey8); + + key_display(ksdev, "128-bit clear key:", 16, clrkey16); + key_display(ksdev, "128-bit black key:", AES_BLOCK_PAD(16), blkkey16); + + key_display(ksdev, "192-bit clear key:", 24, clrkey24); + key_display(ksdev, "192-bit black key:", AES_BLOCK_PAD(24), blkkey24); + + key_display(ksdev, "256-bit clear key:", 32, clrkey32); + key_display(ksdev, "256-bit black key:", AES_BLOCK_PAD(32), blkkey32); + + /* + * Now encapsulate all keys as SM blobs out to external memory + * Blobs will appear as random-looking blocks of data different + * from the original source key, and 48 bytes longer than the + * original key, to account for the extra data encapsulated within. + */ + key_display(ksdev, "64-bit unwritten blob:", 96, blob8); + key_display(ksdev, "128-bit unwritten blob:", 96, blob16); + key_display(ksdev, "196-bit unwritten blob:", 96, blob24); + key_display(ksdev, "256-bit unwritten blob:", 96, blob32); + + rtnval = sm_keystore_slot_export(ksdev, unit, keyslot8, BLACK_KEY, + KEY_COVER_ECB, blob8, 8, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't encapsulate 64-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_export(ksdev, unit, keyslot16, BLACK_KEY, + KEY_COVER_ECB, blob16, 16, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't encapsulate 128-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_export(ksdev, unit, keyslot24, BLACK_KEY, + KEY_COVER_ECB, blob24, 24, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't encapsulate 192-bit key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_export(ksdev, unit, keyslot32, BLACK_KEY, + KEY_COVER_ECB, blob32, 32, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't encapsulate 256-bit key\n"); + goto dealloc; + } + + key_display(ksdev, "64-bit black key in blob:", 96, blob8); + key_display(ksdev, "128-bit black key in blob:", 96, blob16); + key_display(ksdev, "192-bit black key in blob:", 96, blob24); + key_display(ksdev, "256-bit black key in blob:", 96, blob32); + + /* + * Now re-import black keys from secure-memory blobs stored + * in general memory from the previous operation. Since we are + * working with black keys, and since power has not cycled, the + * restored black keys should match the original blackened keys + * (this would not be true if the blobs were save in some non-volatile + * store, and power was cycled between the save and restore) + */ + rtnval = sm_keystore_slot_import(ksdev, unit, keyslot8, BLACK_KEY, + KEY_COVER_ECB, blob8, 8, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't decapsulate 64-bit blob\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_import(ksdev, unit, keyslot16, BLACK_KEY, + KEY_COVER_ECB, blob16, 16, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't decapsulate 128-bit blob\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_import(ksdev, unit, keyslot24, BLACK_KEY, + KEY_COVER_ECB, blob24, 24, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't decapsulate 196-bit blob\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_import(ksdev, unit, keyslot32, BLACK_KEY, + KEY_COVER_ECB, blob32, 32, skeymod); + if (rtnval) { + dev_err(ksdev, "blkkey_ex: can't decapsulate 256-bit blob\n"); + goto dealloc; + } + + + /* + * Blobs are now restored as black keys. Read those black keys back + * for a comparison with the original black key, they should match + */ + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot8, AES_BLOCK_PAD(8), + rstkey8); + if (rtnval) { + dev_err(ksdev, + "blkkey_ex: can't read restored 64-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot16, + AES_BLOCK_PAD(16), rstkey16); + if (rtnval) { + dev_err(ksdev, + "blkkey_ex: can't read restored 128-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot24, + AES_BLOCK_PAD(24), rstkey24); + if (rtnval) { + dev_err(ksdev, + "blkkey_ex: can't read restored 196-bit black key\n"); + goto dealloc; + } + + rtnval = sm_keystore_slot_read(ksdev, unit, keyslot32, + AES_BLOCK_PAD(32), rstkey32); + if (rtnval) { + dev_err(ksdev, + "blkkey_ex: can't read restored 256-bit black key\n"); + goto dealloc; + } + + key_display(ksdev, "restored 64-bit black key:", AES_BLOCK_PAD(8), + rstkey8); + key_display(ksdev, "restored 128-bit black key:", AES_BLOCK_PAD(16), + rstkey16); + key_display(ksdev, "restored 192-bit black key:", AES_BLOCK_PAD(24), + rstkey24); + key_display(ksdev, "restored 256-bit black key:", AES_BLOCK_PAD(32), + rstkey32); + + /* + * Compare the restored black keys with the original blackened keys + * As long as we're operating within the same power cycle, a black key + * restored from a blob should match the original black key IF the + * key happens to be of a size that matches a multiple of the AES + * blocksize. Any key that is padded to fill the block size will not + * match, excepting a key that exceeds a block; only the first full + * blocks will match (assuming ECB). + * + * Therefore, compare the 16 and 32 bit keys, they should match. + * The 24 bit key can only match within the first 16 byte block. + */ + + if (memcmp(rstkey16, blkkey16, AES_BLOCK_PAD(16))) { + dev_err(ksdev, "blkkey_ex: 128-bit restored key mismatch\n"); + rtnval = -EINVAL; + } + + /* Only first AES block will match, remainder subject to padding */ + if (memcmp(rstkey24, blkkey24, 16)) { + dev_err(ksdev, "blkkey_ex: 192-bit restored key mismatch\n"); + rtnval = -EINVAL; + } + + if (memcmp(rstkey32, blkkey32, AES_BLOCK_PAD(32))) { + dev_err(ksdev, "blkkey_ex: 256-bit restored key mismatch\n"); + rtnval = -EINVAL; + } + + + /* Remove keys from keystore */ +dealloc: + sm_keystore_slot_dealloc(ksdev, unit, keyslot32); +dealloc_slot24: + sm_keystore_slot_dealloc(ksdev, unit, keyslot24); +dealloc_slot16: + sm_keystore_slot_dealloc(ksdev, unit, keyslot16); +dealloc_slot8: + sm_keystore_slot_dealloc(ksdev, unit, keyslot8); + + /* Free resources */ +freemem: + kfree(blob8); + kfree(blob16); + kfree(blob24); + kfree(blob32); + + /* Disconnect from keystore and leave */ + sm_release_keystore(ksdev, unit); + + return rtnval; +} +EXPORT_SYMBOL(caam_sm_example_init); + +void caam_sm_example_shutdown(void) +{ + /* unused in present version */ + struct device_node *dev_node; + struct platform_device *pdev; + + /* + * Do of_find_compatible_node() then of_find_device_by_node() + * once a functional device tree is available + */ + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + if (!dev_node) { + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); + if (!dev_node) + return; + } + + pdev = of_find_device_by_node(dev_node); + if (!pdev) + return; + + of_node_get(dev_node); + +} + +static int __init caam_sm_test_init(void) +{ + struct device_node *dev_node; + struct platform_device *pdev; + struct caam_drv_private *priv; + int ret; + + /* + * Do of_find_compatible_node() then of_find_device_by_node() + * once a functional device tree is available + */ + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + if (!dev_node) { + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); + if (!dev_node) + return -ENODEV; + } + + pdev = of_find_device_by_node(dev_node); + if (!pdev) + return -ENODEV; + + of_node_put(dev_node); + + priv = dev_get_drvdata(&pdev->dev); + if (!priv) { + dev_info(&pdev->dev, "SM driver not ready, aborting tests\n"); + return -ENODEV; + } + if (!priv->sm_present) { + dev_info(&pdev->dev, "No SM support, skipping tests\n"); + return -ENODEV; + } + if (!priv->smdev) { + dev_info(&pdev->dev, "SM not initialized (no job rings?) skipping tests\n"); + return -ENODEV; + } + + ret = caam_sm_example_init(pdev); + if (ret) + dev_err(&pdev->dev, "SM test failed: %d\n", ret); + else + dev_info(&pdev->dev, "SM test passed\n"); + + return ret; +} + + +/* Module-based initialization needs to wait for dev tree */ +#ifdef CONFIG_OF +module_init(caam_sm_test_init); +module_exit(caam_sm_example_shutdown); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("FSL CAAM Black Key Usage Example"); +MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD"); +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/snvsregs.h linux-imx-phytec/drivers/crypto/caam/snvsregs.h --- linux-6.1.55/drivers/crypto/caam/snvsregs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/snvsregs.h 2024-06-19 12:33:59.748217327 +0200 @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * SNVS hardware register-level view + * + * Copyright 2012-2015 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + */ + +#ifndef SNVSREGS_H +#define SNVSREGS_H + +#include +#include + +/* + * SNVS High Power Domain + * Includes security violations, HA counter, RTC, alarm + */ +struct snvs_hp { + u32 lock; /* HPLR - HP Lock */ + u32 cmd; /* HPCOMR - HP Command */ + u32 ctl; /* HPCR - HP Control */ + u32 secvio_intcfg; /* HPSICR - Security Violation Int Config */ + u32 secvio_ctl; /* HPSVCR - Security Violation Control */ + u32 status; /* HPSR - HP Status */ + u32 secvio_status; /* HPSVSR - Security Violation Status */ + u32 ha_counteriv; /* High Assurance Counter IV */ + u32 ha_counter; /* High Assurance Counter */ + u32 rtc_msb; /* Real Time Clock/Counter MSB */ + u32 rtc_lsb; /* Real Time Counter LSB */ + u32 time_alarm_msb; /* Time Alarm MSB */ + u32 time_alarm_lsb; /* Time Alarm LSB */ +}; + +#define HP_LOCK_HAC_LCK 0x00040000 +#define HP_LOCK_HPSICR_LCK 0x00020000 +#define HP_LOCK_HPSVCR_LCK 0x00010000 +#define HP_LOCK_MKEYSEL_LCK 0x00000200 +#define HP_LOCK_TAMPCFG_LCK 0x00000100 +#define HP_LOCK_TAMPFLT_LCK 0x00000080 +#define HP_LOCK_SECVIO_LCK 0x00000040 +#define HP_LOCK_GENP_LCK 0x00000020 +#define HP_LOCK_MONOCTR_LCK 0x00000010 +#define HP_LOCK_CALIB_LCK 0x00000008 +#define HP_LOCK_SRTC_LCK 0x00000004 +#define HP_LOCK_ZMK_RD_LCK 0x00000002 +#define HP_LOCK_ZMK_WT_LCK 0x00000001 + +#define HP_CMD_NONPRIV_AXS 0x80000000 +#define HP_CMD_HAC_STOP 0x00080000 +#define HP_CMD_HAC_CLEAR 0x00040000 +#define HP_CMD_HAC_LOAD 0x00020000 +#define HP_CMD_HAC_CFG_EN 0x00010000 +#define HP_CMD_SNVS_MSTR_KEY 0x00002000 +#define HP_CMD_PROG_ZMK 0x00001000 +#define HP_CMD_SW_LPSV 0x00000400 +#define HP_CMD_SW_FSV 0x00000200 +#define HP_CMD_SW_SV 0x00000100 +#define HP_CMD_LP_SWR_DIS 0x00000020 +#define HP_CMD_LP_SWR 0x00000010 +#define HP_CMD_SSM_SFNS_DIS 0x00000004 +#define HP_CMD_SSM_ST_DIS 0x00000002 +#define HP_CMD_SMM_ST 0x00000001 + +#define HP_CTL_TIME_SYNC 0x00010000 +#define HP_CTL_CAL_VAL_SHIFT 10 +#define HP_CTL_CAL_VAL_MASK (0x1f << HP_CTL_CALIB_SHIFT) +#define HP_CTL_CALIB_EN 0x00000100 +#define HP_CTL_PI_FREQ_SHIFT 4 +#define HP_CTL_PI_FREQ_MASK (0xf << HP_CTL_PI_FREQ_SHIFT) +#define HP_CTL_PI_EN 0x00000008 +#define HP_CTL_TIMEALARM_EN 0x00000002 +#define HP_CTL_RTC_EN 0x00000001 + +#define HP_SECVIO_INTEN_EN 0x10000000 +#define HP_SECVIO_INTEN_SRC5 0x00000020 +#define HP_SECVIO_INTEN_SRC4 0x00000010 +#define HP_SECVIO_INTEN_SRC3 0x00000008 +#define HP_SECVIO_INTEN_SRC2 0x00000004 +#define HP_SECVIO_INTEN_SRC1 0x00000002 +#define HP_SECVIO_INTEN_SRC0 0x00000001 +#define HP_SECVIO_INTEN_ALL 0x8000003f + +#define HP_SECVIO_ICTL_CFG_SHIFT 30 +#define HP_SECVIO_ICTL_CFG_MASK (0x3 << HP_SECVIO_ICTL_CFG_SHIFT) +#define HP_SECVIO_ICTL_CFG5_SHIFT 5 +#define HP_SECVIO_ICTL_CFG5_MASK (0x3 << HP_SECVIO_ICTL_CFG5_SHIFT) +#define HP_SECVIO_ICTL_CFG_DISABLE 0 +#define HP_SECVIO_ICTL_CFG_NONFATAL 1 +#define HP_SECVIO_ICTL_CFG_FATAL 2 +#define HP_SECVIO_ICTL_CFG4_FATAL 0x00000010 +#define HP_SECVIO_ICTL_CFG3_FATAL 0x00000008 +#define HP_SECVIO_ICTL_CFG2_FATAL 0x00000004 +#define HP_SECVIO_ICTL_CFG1_FATAL 0x00000002 +#define HP_SECVIO_ICTL_CFG0_FATAL 0x00000001 + +#define HP_STATUS_ZMK_ZERO 0x80000000 +#define HP_STATUS_OTPMK_ZERO 0x08000000 +#define HP_STATUS_OTPMK_SYN_SHIFT 16 +#define HP_STATUS_OTPMK_SYN_MASK (0x1ff << HP_STATUS_OTPMK_SYN_SHIFT) +#define HP_STATUS_SSM_ST_SHIFT 8 +#define HP_STATUS_SSM_ST_MASK (0xf << HP_STATUS_SSM_ST_SHIFT) +#define HP_STATUS_SSM_ST_INIT 0 +#define HP_STATUS_SSM_ST_HARDFAIL 1 +#define HP_STATUS_SSM_ST_SOFTFAIL 3 +#define HP_STATUS_SSM_ST_INITINT 8 +#define HP_STATUS_SSM_ST_CHECK 9 +#define HP_STATUS_SSM_ST_NONSECURE 11 +#define HP_STATUS_SSM_ST_TRUSTED 13 +#define HP_STATUS_SSM_ST_SECURE 15 + +#define HP_SECVIOST_ZMK_ECC_FAIL 0x08000000 /* write to clear */ +#define HP_SECVIOST_ZMK_SYN_SHIFT 16 +#define HP_SECVIOST_ZMK_SYN_MASK (0x1ff << HP_SECVIOST_ZMK_SYN_SHIFT) +#define HP_SECVIOST_SECVIO5 0x00000020 +#define HP_SECVIOST_SECVIO4 0x00000010 +#define HP_SECVIOST_SECVIO3 0x00000008 +#define HP_SECVIOST_SECVIO2 0x00000004 +#define HP_SECVIOST_SECVIO1 0x00000002 +#define HP_SECVIOST_SECVIO0 0x00000001 +#define HP_SECVIOST_SECVIOMASK 0x0000003f + +/* + * SNVS Low Power Domain + * Includes glitch detector, SRTC, alarm, monotonic counter, ZMK + */ +struct snvs_lp { + u32 lock; + u32 ctl; + u32 mstr_key_ctl; /* Master Key Control */ + u32 secvio_ctl; /* Security Violation Control */ + u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration */ + u32 tamper_det_cfg; /* Tamper Detectors Configuration */ + u32 status; + u32 srtc_msb; /* Secure Real Time Clock/Counter MSB */ + u32 srtc_lsb; /* Secure Real Time Clock/Counter LSB */ + u32 time_alarm; /* Time Alarm */ + u32 smc_msb; /* Secure Monotonic Counter MSB */ + u32 smc_lsb; /* Secure Monotonic Counter LSB */ + u32 pwr_glitch_det; /* Power Glitch Detector */ + u32 gen_purpose; + u32 zmk[8]; /* Zeroizable Master Key */ +}; + +#define LP_LOCK_MKEYSEL_LCK 0x00000200 +#define LP_LOCK_TAMPDET_LCK 0x00000100 +#define LP_LOCK_TAMPFLT_LCK 0x00000080 +#define LP_LOCK_SECVIO_LCK 0x00000040 +#define LP_LOCK_GENP_LCK 0x00000020 +#define LP_LOCK_MONOCTR_LCK 0x00000010 +#define LP_LOCK_CALIB_LCK 0x00000008 +#define LP_LOCK_SRTC_LCK 0x00000004 +#define LP_LOCK_ZMK_RD_LCK 0x00000002 +#define LP_LOCK_ZMK_WT_LCK 0x00000001 + +#define LP_CTL_CAL_VAL_SHIFT 10 +#define LP_CTL_CAL_VAL_MASK (0x1f << LP_CTL_CAL_VAL_SHIFT) +#define LP_CTL_CALIB_EN 0x00000100 +#define LP_CTL_SRTC_INVAL_EN 0x00000010 +#define LP_CTL_WAKE_INT_EN 0x00000008 +#define LP_CTL_MONOCTR_EN 0x00000004 +#define LP_CTL_TIMEALARM_EN 0x00000002 +#define LP_CTL_SRTC_EN 0x00000001 + +#define LP_MKEYCTL_ZMKECC_SHIFT 8 +#define LP_MKEYCTL_ZMKECC_MASK (0xff << LP_MKEYCTL_ZMKECC_SHIFT) +#define LP_MKEYCTL_ZMKECC_EN 0x00000010 +#define LP_MKEYCTL_ZMKECC_VAL 0x00000008 +#define LP_MKEYCTL_ZMKECC_PROG 0x00000004 +#define LP_MKEYCTL_MKSEL_SHIFT 0 +#define LP_MKEYCTL_MKSEL_MASK (3 << LP_MKEYCTL_MKSEL_SHIFT) +#define LP_MKEYCTL_MK_OTP 0 +#define LP_MKEYCTL_MK_ZMK 2 +#define LP_MKEYCTL_MK_COMB 3 + +#define LP_SECVIO_CTL_SRC5 0x20 +#define LP_SECVIO_CTL_SRC4 0x10 +#define LP_SECVIO_CTL_SRC3 0x08 +#define LP_SECVIO_CTL_SRC2 0x04 +#define LP_SECVIO_CTL_SRC1 0x02 +#define LP_SECVIO_CTL_SRC0 0x01 + +#define LP_TAMPFILT_EXT2_EN 0x80000000 +#define LP_TAMPFILT_EXT2_SHIFT 24 +#define LP_TAMPFILT_EXT2_MASK (0x1f << LP_TAMPFILT_EXT2_SHIFT) +#define LP_TAMPFILT_EXT1_EN 0x00800000 +#define LP_TAMPFILT_EXT1_SHIFT 16 +#define LP_TAMPFILT_EXT1_MASK (0x1f << LP_TAMPFILT_EXT1_SHIFT) +#define LP_TAMPFILT_WM_EN 0x00000080 +#define LP_TAMPFILT_WM_SHIFT 0 +#define LP_TAMPFILT_WM_MASK (0x1f << LP_TAMPFILT_WM_SHIFT) + +#define LP_TAMPDET_OSC_BPS 0x10000000 +#define LP_TAMPDET_VRC_SHIFT 24 +#define LP_TAMPDET_VRC_MASK (3 << LP_TAMPFILT_VRC_SHIFT) +#define LP_TAMPDET_HTDC_SHIFT 20 +#define LP_TAMPDET_HTDC_MASK (3 << LP_TAMPFILT_HTDC_SHIFT) +#define LP_TAMPDET_LTDC_SHIFT 16 +#define LP_TAMPDET_LTDC_MASK (3 << LP_TAMPFILT_LTDC_SHIFT) +#define LP_TAMPDET_POR_OBS 0x00008000 +#define LP_TAMPDET_PFD_OBS 0x00004000 +#define LP_TAMPDET_ET2_EN 0x00000400 +#define LP_TAMPDET_ET1_EN 0x00000200 +#define LP_TAMPDET_WMT2_EN 0x00000100 +#define LP_TAMPDET_WMT1_EN 0x00000080 +#define LP_TAMPDET_VT_EN 0x00000040 +#define LP_TAMPDET_TT_EN 0x00000020 +#define LP_TAMPDET_CT_EN 0x00000010 +#define LP_TAMPDET_MCR_EN 0x00000004 +#define LP_TAMPDET_SRTCR_EN 0x00000002 + +#define LP_STATUS_SECURE +#define LP_STATUS_NONSECURE +#define LP_STATUS_SCANEXIT 0x00100000 /* all write 1 clear here on */ +#define LP_STATUS_EXT_SECVIO 0x00010000 +#define LP_STATUS_ET2 0x00000400 +#define LP_STATUS_ET1 0x00000200 +#define LP_STATUS_WMT2 0x00000100 +#define LP_STATUS_WMT1 0x00000080 +#define LP_STATUS_VTD 0x00000040 +#define LP_STATUS_TTD 0x00000020 +#define LP_STATUS_CTD 0x00000010 +#define LP_STATUS_PGD 0x00000008 +#define LP_STATUS_MCR 0x00000004 +#define LP_STATUS_SRTCR 0x00000002 +#define LP_STATUS_LPTA 0x00000001 + +/* Full SNVS register page, including version/options */ +struct snvs_full { + struct snvs_hp hp; + struct snvs_lp lp; + u32 rsvd[731]; /* deadspace 0x08c-0xbf7 */ + + /* Version / Revision / Option ID space - end of register page */ + u32 vid; /* 0xbf8 HP Version ID (VID 1) */ + u32 opt_rev; /* 0xbfc HP Options / Revision (VID 2) */ +}; + +#define SNVS_HPVIDR_BLOCK_ID 16 /* SNVS Block ID 31-16 bit */ +#define SNVS_ID1 58 /* SNVS Block ID 0x3A */ +#define SNVS_ID2 60 /* SNVS Block ID 0x3C */ +#define SNVS_ID3 62 /* SNVS Block ID 0x3E */ +#define SNVS_ID4 63 /* SNVS Block ID 0x3F */ + +#endif /* SNVSREGS_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/tag_object.c linux-imx-phytec/drivers/crypto/caam/tag_object.c --- linux-6.1.55/drivers/crypto/caam/tag_object.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/tag_object.c 2024-06-19 12:33:59.748217327 +0200 @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2018-2020 NXP + */ + +#include +#include +#include + +#include "tag_object.h" +#include "desc.h" + +/** + * is_key_type - Check if the object is a key + * + * @type: The object type + * + * Return: True if the object is a key (of black or red color), + * false otherwise + */ +bool is_key_type(u32 type) +{ + /* Check type bitfield from object type */ + return ((type >> TAG_OBJ_TYPE_OFFSET) & TAG_OBJ_TYPE_MASK) == 0; +} +EXPORT_SYMBOL(is_key_type); + +/** + * is_trusted_type - Check if the object is a trusted key + * Trusted Descriptor Key Encryption Key (TDKEK) + * + * @type: The object type + * + * Return: True if the object is a trusted key, + * false otherwise + */ +bool is_trusted_type(u32 type) +{ + /* Check type bitfield from object type */ + return ((type >> TAG_OBJ_TK_OFFSET) & TAG_OBJ_TK_MASK) == 1; +} +EXPORT_SYMBOL(is_trusted_type); + +/** + * is_black_key - Check if the tag object header is a black key + * @header: The tag object header configuration + * + * Return: True if is a black key, false otherwise + */ +bool is_black_key(const struct header_conf *header) +{ + u32 type = header->type; + /* Check type and color bitfields from tag object type */ + return (type & (BIT(TAG_OBJ_COLOR_OFFSET) | + BIT(TAG_OBJ_TYPE_OFFSET))) == BIT(TAG_OBJ_COLOR_OFFSET); +} +EXPORT_SYMBOL(is_black_key); + +/** + * is_valid_header_conf - Check if the header configuration is valid + * @header: The header configuration + * + * Return: True if the header of the tag object configuration, + * has the TAG_OBJECT_MAGIC number and a valid type, + * false otherwise + */ +bool is_valid_header_conf(const struct header_conf *header) +{ + return (header->_magic_number == TAG_OBJECT_MAGIC); +} +EXPORT_SYMBOL(is_valid_header_conf); + +/** + * get_key_conf - Retrieve the key configuration, + * meaning the length of the black key and + * the KEY command parameters needed for CAAM + * @header: The tag object header configuration + * @red_key_len: Red key length + * @obj_len: Black/Red key/blob length + * @load_param: Load parameters for KEY command: + * - indicator for encrypted keys: plaintext or black + * - indicator for encryption mode: AES-ECB or AES-CCM + * - indicator for encryption keys: JDKEK or TDKEK + */ +void get_key_conf(const struct header_conf *header, + u32 *red_key_len, u32 *obj_len, u32 *load_param) +{ + *red_key_len = header->red_key_len; + *obj_len = header->obj_len; + /* Based on the color of the key, set key encryption bit (ENC) */ + *load_param = ((header->type >> TAG_OBJ_COLOR_OFFSET) & + TAG_OBJ_COLOR_MASK) << KEY_ENC_OFFSET; + /* + * For red keys, the TK and EKT bits are ignored. + * So we set them anyway, to be valid when the key is black. + */ + *load_param |= ((header->type >> TAG_OBJ_TK_OFFSET) & + TAG_OBJ_TK_MASK) << KEY_TK_OFFSET; + *load_param |= ((header->type >> TAG_OBJ_EKT_OFFSET) & + TAG_OBJ_EKT_MASK) << KEY_EKT_OFFSET; +} +EXPORT_SYMBOL(get_key_conf); + +/** + * init_tag_object_header - Initialize the tag object header by setting up + * the TAG_OBJECT_MAGIC number, tag object version, + * a valid type and the object's length + * @header: The header configuration to initialize + * @version: The tag object version + * @type: The tag object type + * @red_key_len: The red key length + * @obj_len: The object (actual data) length + */ +void init_tag_object_header(struct header_conf *header, u32 version, + u32 type, size_t red_key_len, size_t obj_len) +{ + header->_magic_number = TAG_OBJECT_MAGIC; + header->version = version; + header->type = type; + header->red_key_len = red_key_len; + header->obj_len = obj_len; +} +EXPORT_SYMBOL(init_tag_object_header); + +/** + * set_tag_object_header_conf - Set tag object header configuration + * @header: The tag object header configuration to set + * @buffer: The buffer needed to be tagged + * @buf_size: The buffer size + * @tag_obj_size: The tagged object size + * + * Return: '0' on success, error code otherwise + */ +int set_tag_object_header_conf(const struct header_conf *header, + void *buffer, size_t buf_size, u32 *tag_obj_size) +{ + /* Retrieve the tag object */ + struct tagged_object *tag_obj = (struct tagged_object *)buffer; + /* + * Requested size for the tagged object is the buffer size + * and the header configuration size (TAG_OVERHEAD_SIZE) + */ + size_t req_size = buf_size + TAG_OVERHEAD_SIZE; + + /* + * Check if the configuration can be set, + * based on the size of the tagged object + */ + if (*tag_obj_size < req_size) + return -EINVAL; + + /* + * Buffers might overlap, use memmove to + * copy the buffer into the tagged object + */ + memmove(&tag_obj->object, buffer, buf_size); + /* Copy the tag object header configuration into the tagged object */ + memcpy(&tag_obj->header, header, TAG_OVERHEAD_SIZE); + /* Set tagged object size */ + *tag_obj_size = req_size; + + return 0; +} +EXPORT_SYMBOL(set_tag_object_header_conf); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/caam/tag_object.h linux-imx-phytec/drivers/crypto/caam/tag_object.h --- linux-6.1.55/drivers/crypto/caam/tag_object.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/crypto/caam/tag_object.h 2024-06-19 12:33:59.748217327 +0200 @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright 2018-2020 NXP + */ + +#ifndef _TAG_OBJECT_H_ +#define _TAG_OBJECT_H_ + +#include +#include + +/** + * Magic number to identify the tag object structure + * 0x54 = 'T' + * 0x61 = 'a' + * 0x67 = 'g' + * 0x4f = 'O' + */ +#define TAG_OBJECT_MAGIC 0x5461674f +#define TAG_OVERHEAD_SIZE sizeof(struct header_conf) +#define MIN_KEY_SIZE 16 +#define TAG_MIN_SIZE (MIN_KEY_SIZE + TAG_OVERHEAD_SIZE) +/* + * Tag object type is a bitfield: + * + * EKT: Encrypted Key Type (AES-ECB or AES-CCM) + * TK: Trusted Key (use Job Descriptor Key Encryption Key (JDKEK) + * or Trusted Descriptor Key Encryption Key (TDKEK) to + * decrypt the key to be loaded into a Key Register). + * + *| Denomination | Security state | Memory | EKT | TK | Type | Color | + *| ------------ | -------------- | ------- | --- | ----- | ---- | ----- | + *| bit(s) | 5-6 | 4 | 3 | 2 | 1 | 0 | + *| option 0 | non-secure | general | ECB | JDKEK | key | red | + *| option 1 | secure | secure | CCM | TDKEK | blob | black | + *| option 2 | trusted | | | | | | + * + * CAAM supports two different Black Key encapsulation schemes, + * one intended for quick decryption (uses AES-ECB encryption), + * and another intended for high assurance (uses AES-CCM encryption). + * + * CAAM implements both Trusted and normal (non-Trusted) Black Keys, + * which are encrypted with different key-encryption keys. + * Both Trusted and normal Descriptors are allowed to encrypt or decrypt + * normal Black Keys, but only Trusted Descriptors are allowed to + * encrypt or decrypt Trusted Black Keys. + */ +#define TAG_OBJ_COLOR_OFFSET 0 +#define TAG_OBJ_COLOR_MASK 0x1 +#define TAG_OBJ_TYPE_OFFSET 1 +#define TAG_OBJ_TYPE_MASK 0x1 +#define TAG_OBJ_TK_OFFSET 2 +#define TAG_OBJ_TK_MASK 0x1 +#define TAG_OBJ_EKT_OFFSET 3 +#define TAG_OBJ_EKT_MASK 0x1 +#define TAG_OBJ_MEM_OFFSET 4 +#define TAG_OBJ_MEM_MASK 0x1 +#define TAG_OBJ_SEC_STATE_OFFSET 5 + +/** + * struct header_conf - Header configuration structure, which represents + * the metadata (or simply a header) applied to the + * actual data (e.g. black key) + * @_magic_number : A magic number to identify the structure + * @version : The version of the data contained (e.g. tag object) + * @type : The type of data contained (e.g. black key, blob, etc.) + * @red_key_len : Length of the red key to be loaded by CAAM (for key + * generation or blob encapsulation) + * @obj_len : The total length of the (black/red) object (key/blob), + * after encryption/encapsulation + */ +struct header_conf { + u32 _magic_number; + u32 version; + u32 type; + u32 red_key_len; + u32 obj_len; +}; + +/** + * struct tagged_object - Tag object structure, which represents the metadata + * (or simply a header) and the actual data + * (e.g. black key) obtained from hardware + * @tag : The configuration of the data (e.g. header) + * @object : The actual data (e.g. black key) + */ +struct tagged_object { + struct header_conf header; + char object; +}; + +bool is_key_type(u32 type); + +bool is_trusted_type(u32 type); + +bool is_black_key(const struct header_conf * const header); + +bool is_black_key(const struct header_conf * const header); + +bool is_valid_header_conf(const struct header_conf *header); + +void get_key_conf(const struct header_conf *header, + u32 *red_key_len, u32 *obj_len, u32 *load_param); + +void init_tag_object_header(struct header_conf *header, u32 version, + u32 type, size_t red_key_len, size_t obj_len); + +int set_tag_object_header_conf(const struct header_conf *header, + void *buffer, size_t obj_size, u32 *to_size); + +#endif /* _TAG_OBJECT_H_ */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/crypto/mxs-dcp.c linux-imx-phytec/drivers/crypto/mxs-dcp.c --- linux-6.1.55/drivers/crypto/mxs-dcp.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/crypto/mxs-dcp.c 2024-06-19 12:33:59.776217805 +0200 @@ -3,6 +3,7 @@ * Freescale i.MX23/i.MX28 Data Co-Processor driver * * Copyright (C) 2013 Marek Vasut + * Copyright 2022 NXP */ #include @@ -15,6 +16,13 @@ #include #include #include +#include +#include +#include + +#ifdef CONFIG_PM_SLEEP +#include +#endif #include #include @@ -124,7 +132,10 @@ * design of Linux Crypto API. */ static struct dcp *global_sdcp; - +#ifdef CONFIG_PM_SLEEP +static uint32_t ctrl_bak; +static int dcp_vmi_irq_bak, dcp_irq_bak; +#endif /* DCP register layout. */ #define MXS_DCP_CTRL 0x00 #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23) @@ -155,6 +166,7 @@ #define MXS_DCP_CONTROL0_HASH_TERM (1 << 13) #define MXS_DCP_CONTROL0_HASH_INIT (1 << 12) #define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11) +#define MXS_DCP_CONTROL0_OTP_KEY (1 << 10) #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT (1 << 8) #define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9) #define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6) @@ -164,6 +176,8 @@ #define MXS_DCP_CONTROL1_HASH_SELECT_SHA256 (2 << 16) #define MXS_DCP_CONTROL1_HASH_SELECT_SHA1 (0 << 16) +#define MXS_DCP_CONTROL1_AES_OTP_CRYPTO_KEY (0xff << 8) +#define MXS_DCP_CONTROL1_AES_OTP_UNIQUE_KEY (0xfe << 8) #define MXS_DCP_CONTROL1_CIPHER_MODE_CBC (1 << 4) #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4) #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128 (0 << 0) @@ -224,7 +238,14 @@ struct dcp *sdcp = global_sdcp; struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req); - int ret; + int ret, len_crypto_hdl, len_unique_hdl; + const struct fdt_property *prop_crypto, *prop_unique; + int nodeoff = fdt_node_offset_by_compatible(initial_boot_params, -1, "fsl,imx28-dcp"); + + if (nodeoff < 0) { + pr_info("node to update the SoC serial number is not found.\n"); + return nodeoff; + } key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key, 2 * AES_KEYSIZE_128, DMA_TO_DEVICE); @@ -249,36 +270,51 @@ ret = -EINVAL; goto aes_done_run; } - /* Fill in the DMA descriptor. */ desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE | - MXS_DCP_CONTROL0_INTERRUPT | - MXS_DCP_CONTROL0_ENABLE_CIPHER; - - /* Payload contains the key. */ - desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY; - + MXS_DCP_CONTROL0_INTERRUPT | + MXS_DCP_CONTROL0_ENABLE_CIPHER; if (rctx->enc) desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT; - if (init) - desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT; desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128; - if (rctx->ecb) desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB; else desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC; + if (init) + desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT; + /*Read device property*/ + prop_crypto = fdt_get_property(initial_boot_params, nodeoff, + "otp_crypto_key", &len_crypto_hdl); + prop_unique = fdt_get_property(initial_boot_params, nodeoff, + "otp_unique_key", &len_unique_hdl); + + if (len_crypto_hdl > 0 && !memcmp(sdcp->coh->aes_key, + prop_crypto->data, AES_KEYSIZE_128)) { + /* Use AES_OTP CRYPTO_KEY. */ + desc->control0 |= MXS_DCP_CONTROL0_OTP_KEY; + /* Use AES_OTP crypto key. */ + desc->control1 |= MXS_DCP_CONTROL1_AES_OTP_CRYPTO_KEY; + desc->payload = 0; + } else if (len_unique_hdl > 0 && (!memcmp(sdcp->coh->aes_key, + prop_unique->data, AES_KEYSIZE_128))) { + /* Use AES_OTP unique key. */ + desc->control1 |= MXS_DCP_CONTROL1_AES_OTP_UNIQUE_KEY; + desc->payload = 0; + } else { + /* Payload contains the key. */ + desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY; + desc->payload = key_phys; + } desc->next_cmd_addr = 0; desc->source = src_phys; desc->destination = dst_phys; desc->size = actx->fill; - desc->payload = key_phys; desc->status = 0; ret = mxs_dcp_start_dma(actx); - aes_done_run: dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE); err_dst: @@ -317,6 +353,9 @@ int init = 0; bool limit_hit = false; + if (!req->cryptlen) + return 0; + actx->fill = 0; /* Copy the key from the temporary location. */ @@ -397,9 +436,15 @@ int ret; +#ifdef CONFIG_PM_SLEEP + set_freezable(); +#endif while (!kthread_should_stop()) { set_current_state(TASK_INTERRUPTIBLE); +#ifdef CONFIG_PM_SLEEP + try_to_freeze(); +#endif spin_lock(&sdcp->lock[chan]); backlog = crypto_get_backlog(&sdcp->queue[chan]); arq = crypto_dequeue_request(&sdcp->queue[chan]); @@ -437,6 +482,10 @@ skcipher_request_set_crypt(&rctx->fallback_req, req->src, req->dst, req->cryptlen, req->iv); +#ifdef CONFIG_PM_SLEEP +set_freezable(); +try_to_freeze(); +#endif if (enc) ret = crypto_skcipher_encrypt(&rctx->fallback_req); else @@ -693,9 +742,15 @@ struct crypto_async_request *arq; int ret; +#ifdef CONFIG_PM_SLEEP + set_freezable(); +#endif while (!kthread_should_stop()) { set_current_state(TASK_INTERRUPTIBLE); +#ifdef CONFIG_PM_SLEEP + try_to_freeze(); +#endif spin_lock(&sdcp->lock[chan]); backlog = crypto_get_backlog(&sdcp->queue[chan]); arq = crypto_dequeue_request(&sdcp->queue[chan]); @@ -968,6 +1023,49 @@ return IRQ_HANDLED; } +#ifdef CONFIG_PM_SLEEP +static int mxs_dcp_resume(struct device *dev) +{ + struct dcp *sdcp = global_sdcp; + int ret; + + /* Restart the DCP block */ + ret = stmp_reset_block(sdcp->base); + if (ret) { + dev_err(dev, "Failed reset\n"); + clk_disable_unprepare(sdcp->dcp_clk); + return ret; + } + + /* Restore control register */ + writel(ctrl_bak, sdcp->base + MXS_DCP_CTRL); + /* Enable all DCP DMA channels */ + writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK, + sdcp->base + MXS_DCP_CHANNELCTRL); + + /* Re-enable DCP interrupts */ + enable_irq(dcp_irq_bak); + enable_irq(dcp_vmi_irq_bak); + + return 0; +} + +static int mxs_dcp_suspend(struct device *dev) +{ + struct dcp *sdcp = global_sdcp; + + /* Backup control register */ + ctrl_bak = readl(sdcp->base + MXS_DCP_CTRL); + /* Temporarily disable DCP interrupts */ + disable_irq(dcp_irq_bak); + disable_irq(dcp_vmi_irq_bak); + + return 0; +} + +SIMPLE_DEV_PM_OPS(mxs_dcp_pm_ops, mxs_dcp_suspend, mxs_dcp_resume); +#endif + static int mxs_dcp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -987,7 +1085,10 @@ dcp_irq = platform_get_irq(pdev, 1); if (dcp_irq < 0) return dcp_irq; - +#ifdef CONFIG_PM_SLEEP + dcp_vmi_irq_bak = dcp_vmi_irq; + dcp_irq_bak = dcp_irq; +#endif sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL); if (!sdcp) return -ENOMEM; @@ -1165,6 +1266,36 @@ return 0; } +/* + * mxs_dcp_blob_to_key transfers content of hardware blob to key. + * Returns -EINVAL, if user wants to add hardware key other than + * otp_crypto_key & otp_unique_key. + * Returns 0, in case of success. + */ +int mxs_dcp_blob_to_key(struct dcp_key_payload *p) +{ + int len_crypto_hdl, len_unique_hdl; + const struct fdt_property *prop_crypto, *prop_unique; + int nodeoff = fdt_node_offset_by_compatible(initial_boot_params, -1, "fsl,imx28-dcp"); + + if (nodeoff < 0) { + pr_info("node to update the SoC serial number is not found.\n"); + return nodeoff; + } + + prop_crypto = fdt_get_property(initial_boot_params, nodeoff, + "otp_crypto_key", &len_crypto_hdl); + prop_unique = fdt_get_property(initial_boot_params, nodeoff, + "otp_unique_key", &len_unique_hdl); + memcpy(p->key, p->blob, p->blob_len); + p->key_len = p->blob_len; + if (memcmp(prop_crypto->data, p->blob, AES_KEYSIZE_128) && + memcmp(prop_unique->data, p->blob, AES_KEYSIZE_128)) + return -EINVAL; + + return 0; +} +EXPORT_SYMBOL_GPL(mxs_dcp_blob_to_key); static const struct of_device_id mxs_dcp_dt_ids[] = { { .compatible = "fsl,imx23-dcp", .data = NULL, }, { .compatible = "fsl,imx28-dcp", .data = NULL, }, @@ -1179,6 +1310,9 @@ .driver = { .name = "mxs-dcp", .of_match_table = mxs_dcp_dt_ids, +#ifdef CONFIG_PM_SLEEP + .pm = &mxs_dcp_pm_ops +#endif }, }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/caam_dma.c linux-imx-phytec/drivers/dma/caam_dma.c --- linux-6.1.55/drivers/dma/caam_dma.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/dma/caam_dma.c 2024-06-19 12:33:59.812218421 +0200 @@ -0,0 +1,463 @@ +/* + * caam support for SG DMA + * + * Copyright 2016 Freescale Semiconductor, Inc + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +#include "../crypto/caam/regs.h" +#include "../crypto/caam/jr.h" +#include "../crypto/caam/error.h" +#include "../crypto/caam/desc_constr.h" + +#define DESC_DMA_MEMCPY_LEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN_MIN) / \ + CAAM_CMD_SZ) + +/* + * This is max chunk size of a DMA transfer. If a buffer is larger than this + * value it is internally broken into chunks of max CAAM_DMA_CHUNK_SIZE bytes + * and for each chunk a DMA transfer request is issued. + * This value is the largest number on 16 bits that is a multiple of 256 bytes + * (the largest configurable CAAM DMA burst size). + */ +#define CAAM_DMA_CHUNK_SIZE 65280 + +struct caam_dma_sh_desc { + u32 desc[DESC_DMA_MEMCPY_LEN] ____cacheline_aligned; + dma_addr_t desc_dma; +}; + +/* caam dma extended descriptor */ +struct caam_dma_edesc { + struct dma_async_tx_descriptor async_tx; + struct list_head node; + struct caam_dma_ctx *ctx; + dma_addr_t src_dma; + dma_addr_t dst_dma; + unsigned int src_len; + unsigned int dst_len; + u32 jd[] ____cacheline_aligned; +}; + +/* + * caam_dma_ctx - per jr/channel context + * @chan: dma channel used by async_tx API + * @node: list_head used to attach to the global dma_ctx_list + * @jrdev: Job Ring device + * @pending_q: queue of pending (submitted, but not enqueued) jobs + * @done_not_acked: jobs that have been completed by jr, but maybe not acked + * @edesc_lock: protects extended descriptor + */ +struct caam_dma_ctx { + struct dma_chan chan; + struct list_head node; + struct device *jrdev; + struct list_head pending_q; + struct list_head done_not_acked; + spinlock_t edesc_lock; +}; + +static struct dma_device *dma_dev; +static struct caam_dma_sh_desc *dma_sh_desc; +static LIST_HEAD(dma_ctx_list); + +static dma_cookie_t caam_dma_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct caam_dma_edesc *edesc = NULL; + struct caam_dma_ctx *ctx = NULL; + dma_cookie_t cookie; + + edesc = container_of(tx, struct caam_dma_edesc, async_tx); + ctx = container_of(tx->chan, struct caam_dma_ctx, chan); + + spin_lock_bh(&ctx->edesc_lock); + + cookie = dma_cookie_assign(tx); + list_add_tail(&edesc->node, &ctx->pending_q); + + spin_unlock_bh(&ctx->edesc_lock); + + return cookie; +} + +static void caam_jr_chan_free_edesc(struct caam_dma_edesc *edesc) +{ + struct caam_dma_ctx *ctx = edesc->ctx; + struct caam_dma_edesc *_edesc = NULL; + + spin_lock_bh(&ctx->edesc_lock); + + list_add_tail(&edesc->node, &ctx->done_not_acked); + list_for_each_entry_safe(edesc, _edesc, &ctx->done_not_acked, node) { + if (async_tx_test_ack(&edesc->async_tx)) { + list_del(&edesc->node); + kfree(edesc); + } + } + + spin_unlock_bh(&ctx->edesc_lock); +} + +static void caam_dma_done(struct device *dev, u32 *hwdesc, u32 err, + void *context) +{ + struct caam_dma_edesc *edesc = context; + struct caam_dma_ctx *ctx = edesc->ctx; + dma_async_tx_callback callback; + void *callback_param; + + if (err) + caam_jr_strstatus(ctx->jrdev, err); + + dma_run_dependencies(&edesc->async_tx); + + spin_lock_bh(&ctx->edesc_lock); + dma_cookie_complete(&edesc->async_tx); + spin_unlock_bh(&ctx->edesc_lock); + + callback = edesc->async_tx.callback; + callback_param = edesc->async_tx.callback_param; + + dma_descriptor_unmap(&edesc->async_tx); + + caam_jr_chan_free_edesc(edesc); + + if (callback) + callback(callback_param); +} + +static void caam_dma_memcpy_init_job_desc(struct caam_dma_edesc *edesc) +{ + u32 *jd = edesc->jd; + u32 *sh_desc = dma_sh_desc->desc; + dma_addr_t desc_dma = dma_sh_desc->desc_dma; + + /* init the job descriptor */ + init_job_desc_shared(jd, desc_dma, desc_len(sh_desc), HDR_REVERSE); + + /* set SEQIN PTR */ + append_seq_in_ptr(jd, edesc->src_dma, edesc->src_len, 0); + + /* set SEQOUT PTR */ + append_seq_out_ptr(jd, edesc->dst_dma, edesc->dst_len, 0); + + print_hex_dump_debug("caam dma desc@" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, jd, desc_bytes(jd), 1); +} + +static struct dma_async_tx_descriptor * +caam_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, + size_t len, unsigned long flags) +{ + struct caam_dma_edesc *edesc; + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + + edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN, GFP_DMA | GFP_NOWAIT); + if (!edesc) + return ERR_PTR(-ENOMEM); + + dma_async_tx_descriptor_init(&edesc->async_tx, chan); + edesc->async_tx.tx_submit = caam_dma_tx_submit; + edesc->async_tx.flags = flags; + edesc->async_tx.cookie = -EBUSY; + + edesc->src_dma = src; + edesc->src_len = len; + edesc->dst_dma = dst; + edesc->dst_len = len; + edesc->ctx = ctx; + + caam_dma_memcpy_init_job_desc(edesc); + + return &edesc->async_tx; +} + +/* This function can be called in an interrupt context */ +static void caam_dma_issue_pending(struct dma_chan *chan) +{ + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + struct caam_dma_edesc *edesc, *_edesc; + + spin_lock_bh(&ctx->edesc_lock); + list_for_each_entry_safe(edesc, _edesc, &ctx->pending_q, node) { + int ret = caam_jr_enqueue(ctx->jrdev, edesc->jd, + caam_dma_done, edesc); + if (ret != -EINPROGRESS) + break; + list_del(&edesc->node); + } + spin_unlock_bh(&ctx->edesc_lock); +} + +static void caam_dma_free_chan_resources(struct dma_chan *chan) +{ + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + struct caam_dma_edesc *edesc, *_edesc; + + spin_lock_bh(&ctx->edesc_lock); + list_for_each_entry_safe(edesc, _edesc, &ctx->pending_q, node) { + list_del(&edesc->node); + kfree(edesc); + } + list_for_each_entry_safe(edesc, _edesc, &ctx->done_not_acked, node) { + list_del(&edesc->node); + kfree(edesc); + } + spin_unlock_bh(&ctx->edesc_lock); +} + +static int caam_dma_jr_chan_bind(void) +{ + struct device *jrdev; + struct caam_dma_ctx *ctx; + int bonds = 0; + int i; + + for (i = 0; i < caam_jr_driver_probed(); i++) { + jrdev = caam_jridx_alloc(i); + if (IS_ERR(jrdev)) { + pr_err("job ring device %d allocation failed\n", i); + continue; + } + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + caam_jr_free(jrdev); + continue; + } + + ctx->chan.device = dma_dev; + ctx->chan.private = ctx; + + ctx->jrdev = jrdev; + + INIT_LIST_HEAD(&ctx->pending_q); + INIT_LIST_HEAD(&ctx->done_not_acked); + INIT_LIST_HEAD(&ctx->node); + spin_lock_init(&ctx->edesc_lock); + + dma_cookie_init(&ctx->chan); + + /* add the context of this channel to the context list */ + list_add_tail(&ctx->node, &dma_ctx_list); + + /* add this channel to the device chan list */ + list_add_tail(&ctx->chan.device_node, &dma_dev->channels); + + bonds++; + } + + return bonds; +} + +static inline void caam_jr_dma_free(struct dma_chan *chan) +{ + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + + list_del(&ctx->node); + list_del(&chan->device_node); + caam_jr_free(ctx->jrdev); + kfree(ctx); +} + +static void set_caam_dma_desc(u32 *desc) +{ + u32 *jmp_cmd; + + /* dma shared descriptor */ + init_sh_desc(desc, HDR_SHARE_NEVER | (1 << HDR_START_IDX_SHIFT)); + + /* REG1 = CAAM_DMA_CHUNK_SIZE */ + append_math_add_imm_u32(desc, REG1, ZERO, IMM, CAAM_DMA_CHUNK_SIZE); + + /* REG0 = SEQINLEN - CAAM_DMA_CHUNK_SIZE */ + append_math_sub_imm_u32(desc, REG0, SEQINLEN, IMM, CAAM_DMA_CHUNK_SIZE); + + /* + * if (REG0 > 0) + * jmp to LABEL1 + */ + jmp_cmd = append_jump(desc, JUMP_TEST_INVALL | JUMP_COND_MATH_N | + JUMP_COND_MATH_Z); + + /* REG1 = SEQINLEN */ + append_math_sub(desc, REG1, SEQINLEN, ZERO, CAAM_CMD_SZ); + + /* LABEL1 */ + set_jump_tgt_here(desc, jmp_cmd); + + /* VARSEQINLEN = REG1 */ + append_math_add(desc, VARSEQINLEN, REG1, ZERO, CAAM_CMD_SZ); + + /* VARSEQOUTLEN = REG1 */ + append_math_add(desc, VARSEQOUTLEN, REG1, ZERO, CAAM_CMD_SZ); + + /* do FIFO STORE */ + append_seq_fifo_store(desc, 0, FIFOST_TYPE_METADATA | LDST_VLF); + + /* do FIFO LOAD */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | + FIFOLD_TYPE_IFIFO | LDST_VLF); + + /* + * if (REG0 > 0) + * jmp 0xF8 (after shared desc header) + */ + append_jump(desc, JUMP_TEST_INVALL | JUMP_COND_MATH_N | + JUMP_COND_MATH_Z | 0xF8); + + print_hex_dump_debug("caam dma shdesc@" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), + 1); +} + +static int caam_dma_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device *ctrldev = dev->parent; + struct dma_chan *chan, *_chan; + u32 *sh_desc; + int err = -ENOMEM; + int bonds; + + if (!caam_jr_driver_probed()) { + dev_info(dev, "Defer probing after JR driver probing\n"); + return -EPROBE_DEFER; + } + + dma_dev = kzalloc(sizeof(*dma_dev), GFP_KERNEL); + if (!dma_dev) + return -ENOMEM; + + dma_sh_desc = kzalloc(sizeof(*dma_sh_desc), GFP_KERNEL | GFP_DMA); + if (!dma_sh_desc) + goto desc_err; + + sh_desc = dma_sh_desc->desc; + set_caam_dma_desc(sh_desc); + dma_sh_desc->desc_dma = dma_map_single(ctrldev, sh_desc, + desc_bytes(sh_desc), + DMA_TO_DEVICE); + if (dma_mapping_error(ctrldev, dma_sh_desc->desc_dma)) { + dev_err(dev, "unable to map dma descriptor\n"); + goto map_err; + } + + INIT_LIST_HEAD(&dma_dev->channels); + + bonds = caam_dma_jr_chan_bind(); + if (!bonds) { + err = -ENODEV; + goto jr_bind_err; + } + + dma_dev->dev = dev; + dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; + dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); + dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask); + dma_dev->device_tx_status = dma_cookie_status; + dma_dev->device_issue_pending = caam_dma_issue_pending; + dma_dev->device_prep_dma_memcpy = caam_dma_prep_memcpy; + dma_dev->device_free_chan_resources = caam_dma_free_chan_resources; + + err = dma_async_device_register(dma_dev); + if (err) { + dev_err(dev, "Failed to register CAAM DMA engine\n"); + goto jr_bind_err; + } + + dev_info(dev, "caam dma support with %d job rings\n", bonds); + + return err; + +jr_bind_err: + list_for_each_entry_safe(chan, _chan, &dma_dev->channels, device_node) + caam_jr_dma_free(chan); + + dma_unmap_single(ctrldev, dma_sh_desc->desc_dma, desc_bytes(sh_desc), + DMA_TO_DEVICE); +map_err: + kfree(dma_sh_desc); +desc_err: + kfree(dma_dev); + return err; +} + +static int caam_dma_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device *ctrldev = dev->parent; + struct caam_dma_ctx *ctx, *_ctx; + + dma_async_device_unregister(dma_dev); + + list_for_each_entry_safe(ctx, _ctx, &dma_ctx_list, node) { + list_del(&ctx->node); + caam_jr_free(ctx->jrdev); + kfree(ctx); + } + + dma_unmap_single(ctrldev, dma_sh_desc->desc_dma, + desc_bytes(dma_sh_desc->desc), DMA_TO_DEVICE); + + kfree(dma_sh_desc); + kfree(dma_dev); + + dev_info(dev, "caam dma support disabled\n"); + return 0; +} + +static struct platform_driver caam_dma_driver = { + .driver = { + .name = "caam-dma", + }, + .probe = caam_dma_probe, + .remove = caam_dma_remove, +}; +module_platform_driver(caam_dma_driver); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("NXP CAAM support for DMA engine"); +MODULE_AUTHOR("NXP Semiconductors"); +MODULE_ALIAS("platform:caam-dma"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/dw-edma/dw-edma-core.c linux-imx-phytec/drivers/dma/dw-edma/dw-edma-core.c --- linux-6.1.55/drivers/dma/dw-edma/dw-edma-core.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/dw-edma/dw-edma-core.c 2024-06-19 12:33:59.816218490 +0200 @@ -39,6 +39,17 @@ return container_of(vd, struct dw_edma_desc, vd); } +static inline +u64 dw_edma_get_pci_address(struct dw_edma_chan *chan, phys_addr_t cpu_addr) +{ + struct dw_edma_chip *chip = chan->dw->chip; + + if (chip->ops->pci_address) + return chip->ops->pci_address(chip->dev, cpu_addr); + + return cpu_addr; +} + static struct dw_edma_burst *dw_edma_alloc_burst(struct dw_edma_chunk *chunk) { struct dw_edma_burst *burst; @@ -199,6 +210,24 @@ return 1; } +static void dw_edma_device_caps(struct dma_chan *dchan, + struct dma_slave_caps *caps) +{ + struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan); + + if (chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) { + if (chan->dir == EDMA_DIR_READ) + caps->directions = BIT(DMA_DEV_TO_MEM); + else + caps->directions = BIT(DMA_MEM_TO_DEV); + } else { + if (chan->dir == EDMA_DIR_WRITE) + caps->directions = BIT(DMA_DEV_TO_MEM); + else + caps->directions = BIT(DMA_MEM_TO_DEV); + } +} + static int dw_edma_device_config(struct dma_chan *dchan, struct dma_slave_config *config) { @@ -332,11 +361,12 @@ { struct dw_edma_chan *chan = dchan2dw_edma_chan(xfer->dchan); enum dma_transfer_direction dir = xfer->direction; - phys_addr_t src_addr, dst_addr; struct scatterlist *sg = NULL; struct dw_edma_chunk *chunk; struct dw_edma_burst *burst; struct dw_edma_desc *desc; + u64 src_addr, dst_addr; + size_t fsz = 0; u32 cnt = 0; int i; @@ -386,9 +416,9 @@ if (xfer->xfer.sg.len < 1) return NULL; } else if (xfer->type == EDMA_XFER_INTERLEAVED) { - if (!xfer->xfer.il->numf) + if (!xfer->xfer.il->numf || xfer->xfer.il->frame_size < 1) return NULL; - if (xfer->xfer.il->numf > 0 && xfer->xfer.il->frame_size > 0) + if (!xfer->xfer.il->src_inc || !xfer->xfer.il->dst_inc) return NULL; } else { return NULL; @@ -410,16 +440,19 @@ dst_addr = chan->config.dst_addr; } + if (dir == DMA_DEV_TO_MEM) + src_addr = dw_edma_get_pci_address(chan, (phys_addr_t)src_addr); + else + dst_addr = dw_edma_get_pci_address(chan, (phys_addr_t)dst_addr); + if (xfer->type == EDMA_XFER_CYCLIC) { cnt = xfer->xfer.cyclic.cnt; } else if (xfer->type == EDMA_XFER_SCATTER_GATHER) { cnt = xfer->xfer.sg.len; sg = xfer->xfer.sg.sgl; } else if (xfer->type == EDMA_XFER_INTERLEAVED) { - if (xfer->xfer.il->numf > 0) - cnt = xfer->xfer.il->numf; - else - cnt = xfer->xfer.il->frame_size; + cnt = xfer->xfer.il->numf * xfer->xfer.il->frame_size; + fsz = xfer->xfer.il->frame_size; } for (i = 0; i < cnt; i++) { @@ -441,7 +474,7 @@ else if (xfer->type == EDMA_XFER_SCATTER_GATHER) burst->sz = sg_dma_len(sg); else if (xfer->type == EDMA_XFER_INTERLEAVED) - burst->sz = xfer->xfer.il->sgl[i].size; + burst->sz = xfer->xfer.il->sgl[i % fsz].size; chunk->ll_region.sz += burst->sz; desc->alloc_sz += burst->sz; @@ -484,20 +517,17 @@ if (xfer->type == EDMA_XFER_SCATTER_GATHER) { sg = sg_next(sg); - } else if (xfer->type == EDMA_XFER_INTERLEAVED && - xfer->xfer.il->frame_size > 0) { + } else if (xfer->type == EDMA_XFER_INTERLEAVED) { struct dma_interleaved_template *il = xfer->xfer.il; - struct data_chunk *dc = &il->sgl[i]; + struct data_chunk *dc = &il->sgl[i % fsz]; - if (il->src_sgl) { - src_addr += burst->sz; + src_addr += burst->sz; + if (il->src_sgl) src_addr += dmaengine_get_src_icg(il, dc); - } - if (il->dst_sgl) { - dst_addr += burst->sz; + dst_addr += burst->sz; + if (il->dst_sgl) dst_addr += dmaengine_get_dst_icg(il, dc); - } } } @@ -710,92 +740,76 @@ } } -static int dw_edma_channel_setup(struct dw_edma *dw, bool write, - u32 wr_alloc, u32 rd_alloc) +static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc) { struct dw_edma_chip *chip = dw->chip; - struct dw_edma_region *dt_region; struct device *dev = chip->dev; struct dw_edma_chan *chan; struct dw_edma_irq *irq; struct dma_device *dma; - u32 alloc, off_alloc; - u32 i, j, cnt; - int err = 0; + u32 i, ch_cnt; u32 pos; - if (write) { - i = 0; - cnt = dw->wr_ch_cnt; - dma = &dw->wr_edma; - alloc = wr_alloc; - off_alloc = 0; - } else { - i = dw->wr_ch_cnt; - cnt = dw->rd_ch_cnt; - dma = &dw->rd_edma; - alloc = rd_alloc; - off_alloc = wr_alloc; - } + ch_cnt = dw->wr_ch_cnt + dw->rd_ch_cnt; + dma = &dw->dma; INIT_LIST_HEAD(&dma->channels); - for (j = 0; (alloc || dw->nr_irqs == 1) && j < cnt; j++, i++) { + + for (i = 0; i < ch_cnt; i++) { chan = &dw->chan[i]; - dt_region = devm_kzalloc(dev, sizeof(*dt_region), GFP_KERNEL); - if (!dt_region) - return -ENOMEM; + chan->dw = dw; - chan->vc.chan.private = dt_region; + if (i < dw->wr_ch_cnt) { + chan->id = i; + chan->dir = EDMA_DIR_WRITE; + } else { + chan->id = i - dw->wr_ch_cnt; + chan->dir = EDMA_DIR_READ; + } - chan->dw = dw; - chan->id = j; - chan->dir = write ? EDMA_DIR_WRITE : EDMA_DIR_READ; chan->configured = false; chan->request = EDMA_REQ_NONE; chan->status = EDMA_ST_IDLE; - if (write) - chan->ll_max = (chip->ll_region_wr[j].sz / EDMA_LL_SZ); + if (chan->dir == EDMA_DIR_WRITE) + chan->ll_max = (chip->ll_region_wr[chan->id].sz / EDMA_LL_SZ); else - chan->ll_max = (chip->ll_region_rd[j].sz / EDMA_LL_SZ); + chan->ll_max = (chip->ll_region_rd[chan->id].sz / EDMA_LL_SZ); chan->ll_max -= 1; dev_vdbg(dev, "L. List:\tChannel %s[%u] max_cnt=%u\n", - write ? "write" : "read", j, chan->ll_max); + chan->dir == EDMA_DIR_WRITE ? "write" : "read", + chan->id, chan->ll_max); if (dw->nr_irqs == 1) pos = 0; + else if (chan->dir == EDMA_DIR_WRITE) + pos = chan->id % wr_alloc; else - pos = off_alloc + (j % alloc); + pos = wr_alloc + chan->id % rd_alloc; irq = &dw->irq[pos]; - if (write) - irq->wr_mask |= BIT(j); + if (chan->dir == EDMA_DIR_WRITE) + irq->wr_mask |= BIT(chan->id); else - irq->rd_mask |= BIT(j); + irq->rd_mask |= BIT(chan->id); irq->dw = dw; memcpy(&chan->msi, &irq->msi, sizeof(chan->msi)); dev_vdbg(dev, "MSI:\t\tChannel %s[%u] addr=0x%.8x%.8x, data=0x%.8x\n", - write ? "write" : "read", j, + chan->dir == EDMA_DIR_WRITE ? "write" : "read", chan->id, chan->msi.address_hi, chan->msi.address_lo, chan->msi.data); chan->vc.desc_free = vchan_free_desc; - vchan_init(&chan->vc, dma); + chan->vc.chan.private = chan->dir == EDMA_DIR_WRITE ? + &dw->chip->dt_region_wr[chan->id] : + &dw->chip->dt_region_rd[chan->id]; - if (write) { - dt_region->paddr = chip->dt_region_wr[j].paddr; - dt_region->vaddr = chip->dt_region_wr[j].vaddr; - dt_region->sz = chip->dt_region_wr[j].sz; - } else { - dt_region->paddr = chip->dt_region_rd[j].paddr; - dt_region->vaddr = chip->dt_region_rd[j].vaddr; - dt_region->sz = chip->dt_region_rd[j].sz; - } + vchan_init(&chan->vc, dma); dw_edma_v0_core_device_config(chan); } @@ -806,16 +820,16 @@ dma_cap_set(DMA_CYCLIC, dma->cap_mask); dma_cap_set(DMA_PRIVATE, dma->cap_mask); dma_cap_set(DMA_INTERLEAVE, dma->cap_mask); - dma->directions = BIT(write ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV); + dma->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); dma->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); dma->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); dma->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; - dma->chancnt = cnt; /* Set DMA channel callbacks */ dma->dev = chip->dev; dma->device_alloc_chan_resources = dw_edma_alloc_chan_resources; dma->device_free_chan_resources = dw_edma_free_chan_resources; + dma->device_caps = dw_edma_device_caps; dma->device_config = dw_edma_device_config; dma->device_pause = dw_edma_device_pause; dma->device_resume = dw_edma_device_resume; @@ -829,9 +843,7 @@ dma_set_max_seg_size(dma->dev, U32_MAX); /* Register DMA device */ - err = dma_async_device_register(dma); - - return err; + return dma_async_device_register(dma); } static inline void dw_edma_dec_irq_alloc(int *nr_irqs, u32 *alloc, u16 cnt) @@ -902,10 +914,8 @@ dw_edma_interrupt_read, IRQF_SHARED, dw->name, &dw->irq[i]); - if (err) { - dw->nr_irqs = i; - return err; - } + if (err) + goto err_irq_free; if (irq_get_msi_desc(irq)) get_cached_msi_msg(irq, &dw->irq[i].msi); @@ -914,6 +924,14 @@ dw->nr_irqs = i; } + return 0; + +err_irq_free: + for (i--; i >= 0; i--) { + irq = chip->ops->irq_vector(dev, i); + free_irq(irq, &dw->irq[i]); + } + return err; } @@ -960,7 +978,8 @@ if (!dw->chan) return -ENOMEM; - snprintf(dw->name, sizeof(dw->name), "dw-edma-core:%d", chip->id); + snprintf(dw->name, sizeof(dw->name), "dw-edma-core:%s", + dev_name(chip->dev)); /* Disable eDMA, only to establish the ideal initial conditions */ dw_edma_v0_core_off(dw); @@ -970,13 +989,8 @@ if (err) return err; - /* Setup write channels */ - err = dw_edma_channel_setup(dw, true, wr_alloc, rd_alloc); - if (err) - goto err_irq_free; - - /* Setup read channels */ - err = dw_edma_channel_setup(dw, false, wr_alloc, rd_alloc); + /* Setup write/read channels */ + err = dw_edma_channel_setup(dw, wr_alloc, rd_alloc); if (err) goto err_irq_free; @@ -1002,6 +1016,10 @@ struct dw_edma *dw = chip->dw; int i; + /* Skip removal if no private data found */ + if (!dw) + return -ENODEV; + /* Disable eDMA */ dw_edma_v0_core_off(dw); @@ -1010,23 +1028,13 @@ free_irq(chip->ops->irq_vector(dev, i), &dw->irq[i]); /* Deregister eDMA device */ - dma_async_device_unregister(&dw->wr_edma); - list_for_each_entry_safe(chan, _chan, &dw->wr_edma.channels, + dma_async_device_unregister(&dw->dma); + list_for_each_entry_safe(chan, _chan, &dw->dma.channels, vc.chan.device_node) { tasklet_kill(&chan->vc.task); list_del(&chan->vc.chan.device_node); } - dma_async_device_unregister(&dw->rd_edma); - list_for_each_entry_safe(chan, _chan, &dw->rd_edma.channels, - vc.chan.device_node) { - tasklet_kill(&chan->vc.task); - list_del(&chan->vc.chan.device_node); - } - - /* Turn debugfs off */ - dw_edma_v0_core_debugfs_off(dw); - return 0; } EXPORT_SYMBOL_GPL(dw_edma_remove); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/dw-edma/dw-edma-core.h linux-imx-phytec/drivers/dma/dw-edma/dw-edma-core.h --- linux-6.1.55/drivers/dma/dw-edma/dw-edma-core.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/dw-edma/dw-edma-core.h 2024-06-19 12:33:59.816218490 +0200 @@ -96,12 +96,11 @@ }; struct dw_edma { - char name[20]; + char name[32]; - struct dma_device wr_edma; - u16 wr_ch_cnt; + struct dma_device dma; - struct dma_device rd_edma; + u16 wr_ch_cnt; u16 rd_ch_cnt; struct dw_edma_irq *irq; @@ -112,9 +111,6 @@ raw_spinlock_t lock; /* Only for legacy */ struct dw_edma_chip *chip; -#ifdef CONFIG_DEBUG_FS - struct dentry *debugfs; -#endif /* CONFIG_DEBUG_FS */ }; struct dw_edma_sg { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/dw-edma/dw-edma-pcie.c linux-imx-phytec/drivers/dma/dw-edma/dw-edma-pcie.c --- linux-6.1.55/drivers/dma/dw-edma/dw-edma-pcie.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/dw-edma/dw-edma-pcie.c 2024-06-19 12:33:59.816218490 +0200 @@ -95,8 +95,23 @@ return pci_irq_vector(to_pci_dev(dev), nr); } +static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct pci_bus_region region; + struct resource res = { + .flags = IORESOURCE_MEM, + .start = cpu_addr, + .end = cpu_addr, + }; + + pcibios_resource_to_bus(pdev->bus, ®ion, &res); + return region.start; +} + static const struct dw_edma_core_ops dw_edma_pcie_core_ops = { .irq_vector = dw_edma_pcie_irq_vector, + .pci_address = dw_edma_pcie_address, }; static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev, @@ -207,7 +222,6 @@ /* Data structure initialization */ chip->dev = dev; - chip->id = pdev->devfn; chip->mf = vsec_data.mf; chip->nr_irqs = nr_irqs; @@ -226,21 +240,21 @@ struct dw_edma_block *ll_block = &vsec_data.ll_wr[i]; struct dw_edma_block *dt_block = &vsec_data.dt_wr[i]; - ll_region->vaddr = pcim_iomap_table(pdev)[ll_block->bar]; - if (!ll_region->vaddr) + ll_region->vaddr.io = pcim_iomap_table(pdev)[ll_block->bar]; + if (!ll_region->vaddr.io) return -ENOMEM; - ll_region->vaddr += ll_block->off; - ll_region->paddr = pdev->resource[ll_block->bar].start; + ll_region->vaddr.io += ll_block->off; + ll_region->paddr = pci_bus_address(pdev, ll_block->bar); ll_region->paddr += ll_block->off; ll_region->sz = ll_block->sz; - dt_region->vaddr = pcim_iomap_table(pdev)[dt_block->bar]; - if (!dt_region->vaddr) + dt_region->vaddr.io = pcim_iomap_table(pdev)[dt_block->bar]; + if (!dt_region->vaddr.io) return -ENOMEM; - dt_region->vaddr += dt_block->off; - dt_region->paddr = pdev->resource[dt_block->bar].start; + dt_region->vaddr.io += dt_block->off; + dt_region->paddr = pci_bus_address(pdev, dt_block->bar); dt_region->paddr += dt_block->off; dt_region->sz = dt_block->sz; } @@ -251,21 +265,21 @@ struct dw_edma_block *ll_block = &vsec_data.ll_rd[i]; struct dw_edma_block *dt_block = &vsec_data.dt_rd[i]; - ll_region->vaddr = pcim_iomap_table(pdev)[ll_block->bar]; - if (!ll_region->vaddr) + ll_region->vaddr.io = pcim_iomap_table(pdev)[ll_block->bar]; + if (!ll_region->vaddr.io) return -ENOMEM; - ll_region->vaddr += ll_block->off; - ll_region->paddr = pdev->resource[ll_block->bar].start; + ll_region->vaddr.io += ll_block->off; + ll_region->paddr = pci_bus_address(pdev, ll_block->bar); ll_region->paddr += ll_block->off; ll_region->sz = ll_block->sz; - dt_region->vaddr = pcim_iomap_table(pdev)[dt_block->bar]; - if (!dt_region->vaddr) + dt_region->vaddr.io = pcim_iomap_table(pdev)[dt_block->bar]; + if (!dt_region->vaddr.io) return -ENOMEM; - dt_region->vaddr += dt_block->off; - dt_region->paddr = pdev->resource[dt_block->bar].start; + dt_region->vaddr.io += dt_block->off; + dt_region->paddr = pci_bus_address(pdev, dt_block->bar); dt_region->paddr += dt_block->off; dt_region->sz = dt_block->sz; } @@ -289,24 +303,24 @@ pci_dbg(pdev, "L. List:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", i, vsec_data.ll_wr[i].bar, vsec_data.ll_wr[i].off, chip->ll_region_wr[i].sz, - chip->ll_region_wr[i].vaddr, &chip->ll_region_wr[i].paddr); + chip->ll_region_wr[i].vaddr.io, &chip->ll_region_wr[i].paddr); pci_dbg(pdev, "Data:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", i, vsec_data.dt_wr[i].bar, vsec_data.dt_wr[i].off, chip->dt_region_wr[i].sz, - chip->dt_region_wr[i].vaddr, &chip->dt_region_wr[i].paddr); + chip->dt_region_wr[i].vaddr.io, &chip->dt_region_wr[i].paddr); } for (i = 0; i < chip->ll_rd_cnt; i++) { pci_dbg(pdev, "L. List:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", i, vsec_data.ll_rd[i].bar, vsec_data.ll_rd[i].off, chip->ll_region_rd[i].sz, - chip->ll_region_rd[i].vaddr, &chip->ll_region_rd[i].paddr); + chip->ll_region_rd[i].vaddr.io, &chip->ll_region_rd[i].paddr); pci_dbg(pdev, "Data:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", i, vsec_data.dt_rd[i].bar, vsec_data.dt_rd[i].off, chip->dt_region_rd[i].sz, - chip->dt_region_rd[i].vaddr, &chip->dt_region_rd[i].paddr); + chip->dt_region_rd[i].vaddr.io, &chip->dt_region_rd[i].paddr); } pci_dbg(pdev, "Nr. IRQs:\t%u\n", chip->nr_irqs); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/dw-edma/dw-edma-v0-core.c linux-imx-phytec/drivers/dma/dw-edma/dw-edma-v0-core.c --- linux-6.1.55/drivers/dma/dw-edma/dw-edma-v0-core.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/dw-edma/dw-edma-v0-core.c 2024-06-19 12:33:59.816218490 +0200 @@ -8,6 +8,8 @@ #include +#include + #include "dw-edma-core.h" #include "dw-edma-v0-core.h" #include "dw-edma-v0-regs.h" @@ -53,8 +55,6 @@ SET_32(dw, rd_##name, value); \ } while (0) -#ifdef CONFIG_64BIT - #define SET_64(dw, name, value) \ writeq(value, &(__dw_regs(dw)->name)) @@ -80,8 +80,6 @@ SET_64(dw, rd_##name, value); \ } while (0) -#endif /* CONFIG_64BIT */ - #define SET_COMPAT(dw, name, value) \ writel(value, &(__dw_regs(dw)->type.unroll.name)) @@ -161,11 +159,6 @@ #define GET_CH_32(dw, dir, ch, name) \ readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name)) -#define SET_LL_32(ll, value) \ - writel(value, ll) - -#ifdef CONFIG_64BIT - static inline void writeq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, u64 value, void __iomem *addr) { @@ -222,11 +215,6 @@ #define GET_CH_64(dw, dir, ch, name) \ readq_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name)) -#define SET_LL_64(ll, value) \ - writeq(value, ll) - -#endif /* CONFIG_64BIT */ - /* eDMA management callbacks */ void dw_edma_v0_core_off(struct dw_edma *dw) { @@ -298,17 +286,53 @@ GET_RW_32(dw, dir, int_status)); } +static void dw_edma_v0_write_ll_data(struct dw_edma_chunk *chunk, int i, + u32 control, u32 size, u64 sar, u64 dar) +{ + ptrdiff_t ofs = i * sizeof(struct dw_edma_v0_lli); + + if (chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) { + struct dw_edma_v0_lli *lli = chunk->ll_region.vaddr.mem + ofs; + + lli->control = control; + lli->transfer_size = size; + lli->sar.reg = sar; + lli->dar.reg = dar; + } else { + struct dw_edma_v0_lli __iomem *lli = chunk->ll_region.vaddr.io + ofs; + + writel(control, &lli->control); + writel(size, &lli->transfer_size); + writeq(sar, &lli->sar.reg); + writeq(dar, &lli->dar.reg); + } +} + +static void dw_edma_v0_write_ll_link(struct dw_edma_chunk *chunk, + int i, u32 control, u64 pointer) +{ + ptrdiff_t ofs = i * sizeof(struct dw_edma_v0_lli); + + if (chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) { + struct dw_edma_v0_llp *llp = chunk->ll_region.vaddr.mem + ofs; + + llp->control = control; + llp->llp.reg = pointer; + } else { + struct dw_edma_v0_llp __iomem *llp = chunk->ll_region.vaddr.io + ofs; + + writel(control, &llp->control); + writeq(pointer, &llp->llp.reg); + } +} + static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) { struct dw_edma_burst *child; struct dw_edma_chan *chan = chunk->chan; - struct dw_edma_v0_lli __iomem *lli; - struct dw_edma_v0_llp __iomem *llp; u32 control = 0, i = 0; int j; - lli = chunk->ll_region.vaddr; - if (chunk->cb) control = DW_EDMA_V0_CB; @@ -320,41 +344,16 @@ if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) control |= DW_EDMA_V0_RIE; } - /* Channel control */ - SET_LL_32(&lli[i].control, control); - /* Transfer size */ - SET_LL_32(&lli[i].transfer_size, child->sz); - /* SAR */ - #ifdef CONFIG_64BIT - SET_LL_64(&lli[i].sar.reg, child->sar); - #else /* CONFIG_64BIT */ - SET_LL_32(&lli[i].sar.lsb, lower_32_bits(child->sar)); - SET_LL_32(&lli[i].sar.msb, upper_32_bits(child->sar)); - #endif /* CONFIG_64BIT */ - /* DAR */ - #ifdef CONFIG_64BIT - SET_LL_64(&lli[i].dar.reg, child->dar); - #else /* CONFIG_64BIT */ - SET_LL_32(&lli[i].dar.lsb, lower_32_bits(child->dar)); - SET_LL_32(&lli[i].dar.msb, upper_32_bits(child->dar)); - #endif /* CONFIG_64BIT */ - i++; + + dw_edma_v0_write_ll_data(chunk, i++, control, child->sz, + child->sar, child->dar); } - llp = (void __iomem *)&lli[i]; control = DW_EDMA_V0_LLP | DW_EDMA_V0_TCB; if (!chunk->cb) control |= DW_EDMA_V0_CB; - /* Channel control */ - SET_LL_32(&llp->control, control); - /* Linked list */ - #ifdef CONFIG_64BIT - SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr); - #else /* CONFIG_64BIT */ - SET_LL_32(&llp->llp.lsb, lower_32_bits(chunk->ll_region.paddr)); - SET_LL_32(&llp->llp.msb, upper_32_bits(chunk->ll_region.paddr)); - #endif /* CONFIG_64BIT */ + dw_edma_v0_write_ll_link(chunk, i, control, chunk->ll_region.paddr); } void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) @@ -504,8 +503,3 @@ { dw_edma_v0_debugfs_on(dw); } - -void dw_edma_v0_core_debugfs_off(struct dw_edma *dw) -{ - dw_edma_v0_debugfs_off(dw); -} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/dw-edma/dw-edma-v0-core.h linux-imx-phytec/drivers/dma/dw-edma/dw-edma-v0-core.h --- linux-6.1.55/drivers/dma/dw-edma/dw-edma-v0-core.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/dw-edma/dw-edma-v0-core.h 2024-06-19 12:33:59.816218490 +0200 @@ -23,6 +23,5 @@ int dw_edma_v0_core_device_config(struct dw_edma_chan *chan); /* eDMA debug fs callbacks */ void dw_edma_v0_core_debugfs_on(struct dw_edma *dw); -void dw_edma_v0_core_debugfs_off(struct dw_edma *dw); #endif /* _DW_EDMA_V0_CORE_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/dw-edma/dw-edma-v0-debugfs.c linux-imx-phytec/drivers/dma/dw-edma/dw-edma-v0-debugfs.c --- linux-6.1.55/drivers/dma/dw-edma/dw-edma-v0-debugfs.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/dw-edma/dw-edma-v0-debugfs.c 2024-06-19 12:33:59.816218490 +0200 @@ -13,76 +13,79 @@ #include "dw-edma-v0-regs.h" #include "dw-edma-core.h" -#define REGS_ADDR(name) \ - ((void __force *)®s->name) -#define REGISTER(name) \ - { #name, REGS_ADDR(name) } - -#define WR_REGISTER(name) \ - { #name, REGS_ADDR(wr_##name) } -#define RD_REGISTER(name) \ - { #name, REGS_ADDR(rd_##name) } +#define REGS_ADDR(dw, name) \ + ({ \ + struct dw_edma_v0_regs __iomem *__regs = (dw)->chip->reg_base; \ + \ + (void __iomem *)&__regs->name; \ + }) + +#define REGS_CH_ADDR(dw, name, _dir, _ch) \ + ({ \ + struct dw_edma_v0_ch_regs __iomem *__ch_regs; \ + \ + if ((dw)->chip->mf == EDMA_MF_EDMA_LEGACY) \ + __ch_regs = REGS_ADDR(dw, type.legacy.ch); \ + else if (_dir == EDMA_DIR_READ) \ + __ch_regs = REGS_ADDR(dw, type.unroll.ch[_ch].rd); \ + else \ + __ch_regs = REGS_ADDR(dw, type.unroll.ch[_ch].wr); \ + \ + (void __iomem *)&__ch_regs->name; \ + }) + +#define REGISTER(dw, name) \ + { dw, #name, REGS_ADDR(dw, name) } + +#define CTX_REGISTER(dw, name, dir, ch) \ + { dw, #name, REGS_CH_ADDR(dw, name, dir, ch), dir, ch } + +#define WR_REGISTER(dw, name) \ + { dw, #name, REGS_ADDR(dw, wr_##name) } +#define RD_REGISTER(dw, name) \ + { dw, #name, REGS_ADDR(dw, rd_##name) } -#define WR_REGISTER_LEGACY(name) \ - { #name, REGS_ADDR(type.legacy.wr_##name) } +#define WR_REGISTER_LEGACY(dw, name) \ + { dw, #name, REGS_ADDR(dw, type.legacy.wr_##name) } #define RD_REGISTER_LEGACY(name) \ - { #name, REGS_ADDR(type.legacy.rd_##name) } + { dw, #name, REGS_ADDR(dw, type.legacy.rd_##name) } -#define WR_REGISTER_UNROLL(name) \ - { #name, REGS_ADDR(type.unroll.wr_##name) } -#define RD_REGISTER_UNROLL(name) \ - { #name, REGS_ADDR(type.unroll.rd_##name) } +#define WR_REGISTER_UNROLL(dw, name) \ + { dw, #name, REGS_ADDR(dw, type.unroll.wr_##name) } +#define RD_REGISTER_UNROLL(dw, name) \ + { dw, #name, REGS_ADDR(dw, type.unroll.rd_##name) } #define WRITE_STR "write" #define READ_STR "read" #define CHANNEL_STR "channel" #define REGISTERS_STR "registers" -static struct dw_edma *dw; -static struct dw_edma_v0_regs __iomem *regs; - -static struct { - void __iomem *start; - void __iomem *end; -} lim[2][EDMA_V0_MAX_NR_CH]; - -struct debugfs_entries { +struct dw_edma_debugfs_entry { + struct dw_edma *dw; const char *name; - dma_addr_t *reg; + void __iomem *reg; + enum dw_edma_dir dir; + u16 ch; }; static int dw_edma_debugfs_u32_get(void *data, u64 *val) { - void __iomem *reg = (void __force __iomem *)data; + struct dw_edma_debugfs_entry *entry = data; + struct dw_edma *dw = entry->dw; + void __iomem *reg = entry->reg; + if (dw->chip->mf == EDMA_MF_EDMA_LEGACY && - reg >= (void __iomem *)®s->type.legacy.ch) { - void __iomem *ptr = ®s->type.legacy.ch; - u32 viewport_sel = 0; + reg >= REGS_ADDR(dw, type.legacy.ch)) { unsigned long flags; - u16 ch; + u32 viewport_sel; - for (ch = 0; ch < dw->wr_ch_cnt; ch++) - if (lim[0][ch].start >= reg && reg < lim[0][ch].end) { - ptr += (reg - lim[0][ch].start); - goto legacy_sel_wr; - } - - for (ch = 0; ch < dw->rd_ch_cnt; ch++) - if (lim[1][ch].start >= reg && reg < lim[1][ch].end) { - ptr += (reg - lim[1][ch].start); - goto legacy_sel_rd; - } - - return 0; -legacy_sel_rd: - viewport_sel = BIT(31); -legacy_sel_wr: - viewport_sel |= FIELD_PREP(EDMA_V0_VIEWPORT_MASK, ch); + viewport_sel = entry->dir == EDMA_DIR_READ ? BIT(31) : 0; + viewport_sel |= FIELD_PREP(EDMA_V0_VIEWPORT_MASK, entry->ch); raw_spin_lock_irqsave(&dw->lock, flags); - writel(viewport_sel, ®s->type.legacy.viewport_sel); - *val = readl(ptr); + writel(viewport_sel, REGS_ADDR(dw, type.legacy.viewport_sel)); + *val = readl(reg); raw_spin_unlock_irqrestore(&dw->lock, flags); } else { @@ -93,222 +96,195 @@ } DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_edma_debugfs_u32_get, NULL, "0x%08llx\n"); -static void dw_edma_debugfs_create_x32(const struct debugfs_entries entries[], - int nr_entries, struct dentry *dir) +static void dw_edma_debugfs_create_x32(struct dw_edma *dw, + const struct dw_edma_debugfs_entry ini[], + int nr_entries, struct dentry *dent) { + struct dw_edma_debugfs_entry *entries; int i; + entries = devm_kcalloc(dw->chip->dev, nr_entries, sizeof(*entries), + GFP_KERNEL); + if (!entries) + return; + for (i = 0; i < nr_entries; i++) { - if (!debugfs_create_file_unsafe(entries[i].name, 0444, dir, - entries[i].reg, &fops_x32)) - break; + entries[i] = ini[i]; + + debugfs_create_file_unsafe(entries[i].name, 0444, dent, + &entries[i], &fops_x32); } } -static void dw_edma_debugfs_regs_ch(struct dw_edma_v0_ch_regs __iomem *regs, - struct dentry *dir) +static void dw_edma_debugfs_regs_ch(struct dw_edma *dw, enum dw_edma_dir dir, + u16 ch, struct dentry *dent) { - int nr_entries; - const struct debugfs_entries debugfs_regs[] = { - REGISTER(ch_control1), - REGISTER(ch_control2), - REGISTER(transfer_size), - REGISTER(sar.lsb), - REGISTER(sar.msb), - REGISTER(dar.lsb), - REGISTER(dar.msb), - REGISTER(llp.lsb), - REGISTER(llp.msb), + struct dw_edma_debugfs_entry debugfs_regs[] = { + CTX_REGISTER(dw, ch_control1, dir, ch), + CTX_REGISTER(dw, ch_control2, dir, ch), + CTX_REGISTER(dw, transfer_size, dir, ch), + CTX_REGISTER(dw, sar.lsb, dir, ch), + CTX_REGISTER(dw, sar.msb, dir, ch), + CTX_REGISTER(dw, dar.lsb, dir, ch), + CTX_REGISTER(dw, dar.msb, dir, ch), + CTX_REGISTER(dw, llp.lsb, dir, ch), + CTX_REGISTER(dw, llp.msb, dir, ch), }; + int nr_entries; nr_entries = ARRAY_SIZE(debugfs_regs); - dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, dir); + dw_edma_debugfs_create_x32(dw, debugfs_regs, nr_entries, dent); } -static void dw_edma_debugfs_regs_wr(struct dentry *dir) +static void dw_edma_debugfs_regs_wr(struct dw_edma *dw, struct dentry *dent) { - const struct debugfs_entries debugfs_regs[] = { + const struct dw_edma_debugfs_entry debugfs_regs[] = { /* eDMA global registers */ - WR_REGISTER(engine_en), - WR_REGISTER(doorbell), - WR_REGISTER(ch_arb_weight.lsb), - WR_REGISTER(ch_arb_weight.msb), + WR_REGISTER(dw, engine_en), + WR_REGISTER(dw, doorbell), + WR_REGISTER(dw, ch_arb_weight.lsb), + WR_REGISTER(dw, ch_arb_weight.msb), /* eDMA interrupts registers */ - WR_REGISTER(int_status), - WR_REGISTER(int_mask), - WR_REGISTER(int_clear), - WR_REGISTER(err_status), - WR_REGISTER(done_imwr.lsb), - WR_REGISTER(done_imwr.msb), - WR_REGISTER(abort_imwr.lsb), - WR_REGISTER(abort_imwr.msb), - WR_REGISTER(ch01_imwr_data), - WR_REGISTER(ch23_imwr_data), - WR_REGISTER(ch45_imwr_data), - WR_REGISTER(ch67_imwr_data), - WR_REGISTER(linked_list_err_en), + WR_REGISTER(dw, int_status), + WR_REGISTER(dw, int_mask), + WR_REGISTER(dw, int_clear), + WR_REGISTER(dw, err_status), + WR_REGISTER(dw, done_imwr.lsb), + WR_REGISTER(dw, done_imwr.msb), + WR_REGISTER(dw, abort_imwr.lsb), + WR_REGISTER(dw, abort_imwr.msb), + WR_REGISTER(dw, ch01_imwr_data), + WR_REGISTER(dw, ch23_imwr_data), + WR_REGISTER(dw, ch45_imwr_data), + WR_REGISTER(dw, ch67_imwr_data), + WR_REGISTER(dw, linked_list_err_en), }; - const struct debugfs_entries debugfs_unroll_regs[] = { + const struct dw_edma_debugfs_entry debugfs_unroll_regs[] = { /* eDMA channel context grouping */ - WR_REGISTER_UNROLL(engine_chgroup), - WR_REGISTER_UNROLL(engine_hshake_cnt.lsb), - WR_REGISTER_UNROLL(engine_hshake_cnt.msb), - WR_REGISTER_UNROLL(ch0_pwr_en), - WR_REGISTER_UNROLL(ch1_pwr_en), - WR_REGISTER_UNROLL(ch2_pwr_en), - WR_REGISTER_UNROLL(ch3_pwr_en), - WR_REGISTER_UNROLL(ch4_pwr_en), - WR_REGISTER_UNROLL(ch5_pwr_en), - WR_REGISTER_UNROLL(ch6_pwr_en), - WR_REGISTER_UNROLL(ch7_pwr_en), + WR_REGISTER_UNROLL(dw, engine_chgroup), + WR_REGISTER_UNROLL(dw, engine_hshake_cnt.lsb), + WR_REGISTER_UNROLL(dw, engine_hshake_cnt.msb), + WR_REGISTER_UNROLL(dw, ch0_pwr_en), + WR_REGISTER_UNROLL(dw, ch1_pwr_en), + WR_REGISTER_UNROLL(dw, ch2_pwr_en), + WR_REGISTER_UNROLL(dw, ch3_pwr_en), + WR_REGISTER_UNROLL(dw, ch4_pwr_en), + WR_REGISTER_UNROLL(dw, ch5_pwr_en), + WR_REGISTER_UNROLL(dw, ch6_pwr_en), + WR_REGISTER_UNROLL(dw, ch7_pwr_en), }; - struct dentry *regs_dir, *ch_dir; + struct dentry *regs_dent, *ch_dent; int nr_entries, i; char name[16]; - regs_dir = debugfs_create_dir(WRITE_STR, dir); - if (!regs_dir) - return; + regs_dent = debugfs_create_dir(WRITE_STR, dent); nr_entries = ARRAY_SIZE(debugfs_regs); - dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, regs_dir); + dw_edma_debugfs_create_x32(dw, debugfs_regs, nr_entries, regs_dent); if (dw->chip->mf == EDMA_MF_HDMA_COMPAT) { nr_entries = ARRAY_SIZE(debugfs_unroll_regs); - dw_edma_debugfs_create_x32(debugfs_unroll_regs, nr_entries, - regs_dir); + dw_edma_debugfs_create_x32(dw, debugfs_unroll_regs, nr_entries, + regs_dent); } for (i = 0; i < dw->wr_ch_cnt; i++) { snprintf(name, sizeof(name), "%s:%d", CHANNEL_STR, i); - ch_dir = debugfs_create_dir(name, regs_dir); - if (!ch_dir) - return; - - dw_edma_debugfs_regs_ch(®s->type.unroll.ch[i].wr, ch_dir); + ch_dent = debugfs_create_dir(name, regs_dent); - lim[0][i].start = ®s->type.unroll.ch[i].wr; - lim[0][i].end = ®s->type.unroll.ch[i].padding_1[0]; + dw_edma_debugfs_regs_ch(dw, EDMA_DIR_WRITE, i, ch_dent); } } -static void dw_edma_debugfs_regs_rd(struct dentry *dir) +static void dw_edma_debugfs_regs_rd(struct dw_edma *dw, struct dentry *dent) { - const struct debugfs_entries debugfs_regs[] = { + const struct dw_edma_debugfs_entry debugfs_regs[] = { /* eDMA global registers */ - RD_REGISTER(engine_en), - RD_REGISTER(doorbell), - RD_REGISTER(ch_arb_weight.lsb), - RD_REGISTER(ch_arb_weight.msb), + RD_REGISTER(dw, engine_en), + RD_REGISTER(dw, doorbell), + RD_REGISTER(dw, ch_arb_weight.lsb), + RD_REGISTER(dw, ch_arb_weight.msb), /* eDMA interrupts registers */ - RD_REGISTER(int_status), - RD_REGISTER(int_mask), - RD_REGISTER(int_clear), - RD_REGISTER(err_status.lsb), - RD_REGISTER(err_status.msb), - RD_REGISTER(linked_list_err_en), - RD_REGISTER(done_imwr.lsb), - RD_REGISTER(done_imwr.msb), - RD_REGISTER(abort_imwr.lsb), - RD_REGISTER(abort_imwr.msb), - RD_REGISTER(ch01_imwr_data), - RD_REGISTER(ch23_imwr_data), - RD_REGISTER(ch45_imwr_data), - RD_REGISTER(ch67_imwr_data), + RD_REGISTER(dw, int_status), + RD_REGISTER(dw, int_mask), + RD_REGISTER(dw, int_clear), + RD_REGISTER(dw, err_status.lsb), + RD_REGISTER(dw, err_status.msb), + RD_REGISTER(dw, linked_list_err_en), + RD_REGISTER(dw, done_imwr.lsb), + RD_REGISTER(dw, done_imwr.msb), + RD_REGISTER(dw, abort_imwr.lsb), + RD_REGISTER(dw, abort_imwr.msb), + RD_REGISTER(dw, ch01_imwr_data), + RD_REGISTER(dw, ch23_imwr_data), + RD_REGISTER(dw, ch45_imwr_data), + RD_REGISTER(dw, ch67_imwr_data), }; - const struct debugfs_entries debugfs_unroll_regs[] = { + const struct dw_edma_debugfs_entry debugfs_unroll_regs[] = { /* eDMA channel context grouping */ - RD_REGISTER_UNROLL(engine_chgroup), - RD_REGISTER_UNROLL(engine_hshake_cnt.lsb), - RD_REGISTER_UNROLL(engine_hshake_cnt.msb), - RD_REGISTER_UNROLL(ch0_pwr_en), - RD_REGISTER_UNROLL(ch1_pwr_en), - RD_REGISTER_UNROLL(ch2_pwr_en), - RD_REGISTER_UNROLL(ch3_pwr_en), - RD_REGISTER_UNROLL(ch4_pwr_en), - RD_REGISTER_UNROLL(ch5_pwr_en), - RD_REGISTER_UNROLL(ch6_pwr_en), - RD_REGISTER_UNROLL(ch7_pwr_en), + RD_REGISTER_UNROLL(dw, engine_chgroup), + RD_REGISTER_UNROLL(dw, engine_hshake_cnt.lsb), + RD_REGISTER_UNROLL(dw, engine_hshake_cnt.msb), + RD_REGISTER_UNROLL(dw, ch0_pwr_en), + RD_REGISTER_UNROLL(dw, ch1_pwr_en), + RD_REGISTER_UNROLL(dw, ch2_pwr_en), + RD_REGISTER_UNROLL(dw, ch3_pwr_en), + RD_REGISTER_UNROLL(dw, ch4_pwr_en), + RD_REGISTER_UNROLL(dw, ch5_pwr_en), + RD_REGISTER_UNROLL(dw, ch6_pwr_en), + RD_REGISTER_UNROLL(dw, ch7_pwr_en), }; - struct dentry *regs_dir, *ch_dir; + struct dentry *regs_dent, *ch_dent; int nr_entries, i; char name[16]; - regs_dir = debugfs_create_dir(READ_STR, dir); - if (!regs_dir) - return; + regs_dent = debugfs_create_dir(READ_STR, dent); nr_entries = ARRAY_SIZE(debugfs_regs); - dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, regs_dir); + dw_edma_debugfs_create_x32(dw, debugfs_regs, nr_entries, regs_dent); if (dw->chip->mf == EDMA_MF_HDMA_COMPAT) { nr_entries = ARRAY_SIZE(debugfs_unroll_regs); - dw_edma_debugfs_create_x32(debugfs_unroll_regs, nr_entries, - regs_dir); + dw_edma_debugfs_create_x32(dw, debugfs_unroll_regs, nr_entries, + regs_dent); } for (i = 0; i < dw->rd_ch_cnt; i++) { snprintf(name, sizeof(name), "%s:%d", CHANNEL_STR, i); - ch_dir = debugfs_create_dir(name, regs_dir); - if (!ch_dir) - return; + ch_dent = debugfs_create_dir(name, regs_dent); - dw_edma_debugfs_regs_ch(®s->type.unroll.ch[i].rd, ch_dir); - - lim[1][i].start = ®s->type.unroll.ch[i].rd; - lim[1][i].end = ®s->type.unroll.ch[i].padding_2[0]; + dw_edma_debugfs_regs_ch(dw, EDMA_DIR_READ, i, ch_dent); } } -static void dw_edma_debugfs_regs(void) +static void dw_edma_debugfs_regs(struct dw_edma *dw) { - const struct debugfs_entries debugfs_regs[] = { - REGISTER(ctrl_data_arb_prior), - REGISTER(ctrl), + const struct dw_edma_debugfs_entry debugfs_regs[] = { + REGISTER(dw, ctrl_data_arb_prior), + REGISTER(dw, ctrl), }; - struct dentry *regs_dir; + struct dentry *regs_dent; int nr_entries; - regs_dir = debugfs_create_dir(REGISTERS_STR, dw->debugfs); - if (!regs_dir) - return; + regs_dent = debugfs_create_dir(REGISTERS_STR, dw->dma.dbg_dev_root); nr_entries = ARRAY_SIZE(debugfs_regs); - dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, regs_dir); + dw_edma_debugfs_create_x32(dw, debugfs_regs, nr_entries, regs_dent); - dw_edma_debugfs_regs_wr(regs_dir); - dw_edma_debugfs_regs_rd(regs_dir); + dw_edma_debugfs_regs_wr(dw, regs_dent); + dw_edma_debugfs_regs_rd(dw, regs_dent); } -void dw_edma_v0_debugfs_on(struct dw_edma *_dw) +void dw_edma_v0_debugfs_on(struct dw_edma *dw) { - dw = _dw; - if (!dw) - return; - - regs = dw->chip->reg_base; - if (!regs) - return; - - dw->debugfs = debugfs_create_dir(dw->name, NULL); - if (!dw->debugfs) + if (!debugfs_initialized()) return; - debugfs_create_u32("mf", 0444, dw->debugfs, &dw->chip->mf); - debugfs_create_u16("wr_ch_cnt", 0444, dw->debugfs, &dw->wr_ch_cnt); - debugfs_create_u16("rd_ch_cnt", 0444, dw->debugfs, &dw->rd_ch_cnt); - - dw_edma_debugfs_regs(); -} - -void dw_edma_v0_debugfs_off(struct dw_edma *_dw) -{ - dw = _dw; - if (!dw) - return; + debugfs_create_u32("mf", 0444, dw->dma.dbg_dev_root, &dw->chip->mf); + debugfs_create_u16("wr_ch_cnt", 0444, dw->dma.dbg_dev_root, &dw->wr_ch_cnt); + debugfs_create_u16("rd_ch_cnt", 0444, dw->dma.dbg_dev_root, &dw->rd_ch_cnt); - debugfs_remove_recursive(dw->debugfs); - dw->debugfs = NULL; + dw_edma_debugfs_regs(dw); } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/dw-edma/dw-edma-v0-debugfs.h linux-imx-phytec/drivers/dma/dw-edma/dw-edma-v0-debugfs.h --- linux-6.1.55/drivers/dma/dw-edma/dw-edma-v0-debugfs.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/dw-edma/dw-edma-v0-debugfs.h 2024-06-19 12:33:59.816218490 +0200 @@ -13,15 +13,10 @@ #ifdef CONFIG_DEBUG_FS void dw_edma_v0_debugfs_on(struct dw_edma *dw); -void dw_edma_v0_debugfs_off(struct dw_edma *dw); #else static inline void dw_edma_v0_debugfs_on(struct dw_edma *dw) { } - -static inline void dw_edma_v0_debugfs_off(struct dw_edma *dw) -{ -} #endif /* CONFIG_DEBUG_FS */ #endif /* _DW_EDMA_V0_DEBUG_FS_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/dw-edma/Kconfig linux-imx-phytec/drivers/dma/dw-edma/Kconfig --- linux-6.1.55/drivers/dma/dw-edma/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/dw-edma/Kconfig 2024-06-19 12:33:59.816218490 +0200 @@ -9,11 +9,14 @@ Support the Synopsys DesignWare eDMA controller, normally implemented on endpoints SoCs. +if DW_EDMA + config DW_EDMA_PCIE tristate "Synopsys DesignWare eDMA PCIe driver" depends on PCI && PCI_MSI - select DW_EDMA help Provides a glue-logic between the Synopsys DesignWare eDMA controller and an endpoint PCIe device. This also serves as a reference design to whom desires to use this IP. + +endif # DW_EDMA diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c linux-imx-phytec/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c --- linux-6.1.55/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c 2024-06-19 12:33:59.820218558 +0200 @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright 2019 NXP +// Copyright 2019-2021 NXP #include #include @@ -38,15 +38,17 @@ if (!dpaa2_chan->fd_pool) goto err; - dpaa2_chan->fl_pool = dma_pool_create("fl_pool", dev, - sizeof(struct dpaa2_fl_entry), - sizeof(struct dpaa2_fl_entry), 0); + dpaa2_chan->fl_pool = + dma_pool_create("fl_pool", dev, + sizeof(struct dpaa2_fl_entry) * 3, + sizeof(struct dpaa2_fl_entry), 0); + if (!dpaa2_chan->fl_pool) goto err_fd; dpaa2_chan->sdd_pool = dma_pool_create("sdd_pool", dev, - sizeof(struct dpaa2_qdma_sd_d), + sizeof(struct dpaa2_qdma_sd_d) * 2, sizeof(struct dpaa2_qdma_sd_d), 0); if (!dpaa2_chan->sdd_pool) goto err_fl; @@ -330,26 +332,6 @@ goto exit; } - if (priv->dpdmai_attr.version.major > DPDMAI_VER_MAJOR) { - err = -EINVAL; - dev_err(dev, "DPDMAI major version mismatch\n" - "Found %u.%u, supported version is %u.%u\n", - priv->dpdmai_attr.version.major, - priv->dpdmai_attr.version.minor, - DPDMAI_VER_MAJOR, DPDMAI_VER_MINOR); - goto exit; - } - - if (priv->dpdmai_attr.version.minor > DPDMAI_VER_MINOR) { - err = -EINVAL; - dev_err(dev, "DPDMAI minor version mismatch\n" - "Found %u.%u, supported version is %u.%u\n", - priv->dpdmai_attr.version.major, - priv->dpdmai_attr.version.minor, - DPDMAI_VER_MAJOR, DPDMAI_VER_MINOR); - goto exit; - } - priv->num_pairs = min(priv->dpdmai_attr.num_of_priorities, prio_def); ppriv = kcalloc(priv->num_pairs, sizeof(*ppriv), GFP_KERNEL); if (!ppriv) { @@ -360,7 +342,7 @@ for (i = 0; i < priv->num_pairs; i++) { err = dpdmai_get_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, - i, &priv->rx_queue_attr[i]); + i, 0, &priv->rx_queue_attr[i]); if (err) { dev_err(dev, "dpdmai_get_rx_queue() failed\n"); goto exit; @@ -368,13 +350,13 @@ ppriv->rsp_fqid = priv->rx_queue_attr[i].fqid; err = dpdmai_get_tx_queue(priv->mc_io, 0, ls_dev->mc_handle, - i, &priv->tx_fqid[i]); + i, 0, &priv->tx_queue_attr[i]); if (err) { dev_err(dev, "dpdmai_get_tx_queue() failed\n"); goto exit; } - ppriv->req_fqid = priv->tx_fqid[i]; - ppriv->prio = i; + ppriv->req_fqid = priv->tx_queue_attr[i].fqid; + ppriv->prio = DPAA2_QDMA_DEFAULT_PRIORITY; ppriv->priv = priv; ppriv++; } @@ -540,8 +522,7 @@ rx_queue_cfg.dest_cfg.dest_id = ppriv->nctx.dpio_id; rx_queue_cfg.dest_cfg.priority = ppriv->prio; err = dpdmai_set_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, - rx_queue_cfg.dest_cfg.priority, - &rx_queue_cfg); + i, 0, &rx_queue_cfg); if (err) { dev_err(dev, "dpdmai_set_rx_queue() failed\n"); return err; @@ -603,6 +584,7 @@ static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma) { struct dpaa2_qdma_chan *qchan; + struct dma_chan *chan; int num, i; num = dpaa2_qdma->n_chans; @@ -613,6 +595,9 @@ dma_pool_destroy(qchan->fd_pool); dma_pool_destroy(qchan->fl_pool); dma_pool_destroy(qchan->sdd_pool); + chan = &qchan->vchan.chan; + if (chan->client_count) + chan->client_count--; } } @@ -640,7 +625,7 @@ for (i = 0; i < dpaa2_qdma->n_chans; i++) { dpaa2_chan = &dpaa2_qdma->chans[i]; dpaa2_chan->qdma = dpaa2_qdma; - dpaa2_chan->fqid = priv->tx_fqid[i % num]; + dpaa2_chan->fqid = priv->tx_queue_attr[i % num].fqid; dpaa2_chan->vchan.desc_free = dpaa2_qdma_free_desc; vchan_init(&dpaa2_chan->vchan, &dpaa2_qdma->dma_dev); spin_lock_init(&dpaa2_chan->queue_lock); @@ -802,7 +787,7 @@ dpdmai_disable(priv->mc_io, 0, ls_dev->mc_handle); dpaa2_dpdmai_dpio_unbind(priv); dpdmai_close(priv->mc_io, 0, ls_dev->mc_handle); - dpdmai_destroy(priv->mc_io, 0, ls_dev->mc_handle); + dpdmai_destroy(priv->mc_io, 0, priv->dpqdma_id, ls_dev->mc_handle); } static const struct fsl_mc_device_id dpaa2_qdma_id_table[] = { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h linux-imx-phytec/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h --- linux-6.1.55/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h 2024-06-19 12:33:59.820218558 +0200 @@ -6,6 +6,7 @@ #define DPAA2_QDMA_STORE_SIZE 16 #define NUM_CH 8 +#define DPAA2_QDMA_DEFAULT_PRIORITY 0 struct dpaa2_qdma_sd_d { u32 rsv:32; @@ -122,8 +123,8 @@ struct dpaa2_qdma_engine *dpaa2_qdma; struct dpaa2_qdma_priv_per_prio *ppriv; - struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_PRIO_NUM]; - u32 tx_fqid[DPDMAI_PRIO_NUM]; + struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_MAX_QUEUE_NUM]; + struct dpdmai_tx_queue_attr tx_queue_attr[DPDMAI_MAX_QUEUE_NUM]; }; struct dpaa2_qdma_priv_per_prio { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/fsl-dpaa2-qdma/dpdmai.c linux-imx-phytec/drivers/dma/fsl-dpaa2-qdma/dpdmai.c --- linux-6.1.55/drivers/dma/fsl-dpaa2-qdma/dpdmai.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/fsl-dpaa2-qdma/dpdmai.c 2024-06-19 12:33:59.820218558 +0200 @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright 2019 NXP +// Copyright 2019-2021 NXP #include #include @@ -7,47 +7,6 @@ #include #include "dpdmai.h" -struct dpdmai_rsp_get_attributes { - __le32 id; - u8 num_of_priorities; - u8 pad0[3]; - __le16 major; - __le16 minor; -}; - -struct dpdmai_cmd_queue { - __le32 dest_id; - u8 priority; - u8 queue; - u8 dest_type; - u8 pad; - __le64 user_ctx; - union { - __le32 options; - __le32 fqid; - }; -}; - -struct dpdmai_rsp_get_tx_queue { - __le64 pad; - __le32 fqid; -}; - -#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ - ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg)) - -/* cmd, param, offset, width, type, arg_name */ -#define DPDMAI_CMD_CREATE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 8, 8, u8, (cfg)->priorities[0]);\ - MC_CMD_OP(cmd, 0, 16, 8, u8, (cfg)->priorities[1]);\ -} while (0) - -static inline u64 mc_enc(int lsoffset, int width, u64 val) -{ - return (val & MAKE_UMASK64(width)) << lsoffset; -} - /** * dpdmai_open() - Open a control session for the specified object * @mc_io: Pointer to MC portal's I/O object @@ -68,16 +27,16 @@ int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpdmai_id, u16 *token) { + struct dpdmai_cmd_open *cmd_params; struct fsl_mc_command cmd = { 0 }; - __le64 *cmd_dpdmai_id; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN, cmd_flags, 0); - cmd_dpdmai_id = cmd.params; - *cmd_dpdmai_id = cpu_to_le32(dpdmai_id); + cmd_params = (struct dpdmai_cmd_open *)cmd.params; + cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -138,15 +97,20 @@ * Return: '0' on Success; Error code otherwise. */ int dpdmai_create(struct fsl_mc_io *mc_io, u32 cmd_flags, - const struct dpdmai_cfg *cfg, u16 *token) + const struct dpdmai_cfg *cfg, u16 token, + u32 *dpdmai_id) { + struct dpdmai_cmd_create *cmd_params; struct fsl_mc_command cmd = { 0 }; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CREATE, - cmd_flags, 0); - DPDMAI_CMD_CREATE(cmd, cfg); + cmd_flags, token); + cmd_params = (struct dpdmai_cmd_create *)cmd.params; + cmd_params->num_queues = cfg->num_queues; + cmd_params->priorities[0] = cfg->priorities[0]; + cmd_params->priorities[1] = cfg->priorities[1]; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -154,26 +118,38 @@ return err; /* retrieve response parameters */ - *token = mc_cmd_hdr_read_token(&cmd); + *dpdmai_id = mc_cmd_read_object_id(&cmd); return 0; } +EXPORT_SYMBOL_GPL(dpdmai_create); /** * dpdmai_destroy() - Destroy the DPDMAI object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPDMAI object + * @mc_io: Pointer to MC portal's I/O object + * @token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @object_id: The object id; it must be a valid id within the container that + * created this object; * - * Return: '0' on Success; error code otherwise. + * The function accepts the authentication token of the parent container that + * created the object (not the one that currently owns the object). The object + * is searched within parent using the provided 'object_id'. + * All tokens to the object must be closed before calling destroy. + * + * Return: '0' on Success; error code otherwise. */ -int dpdmai_destroy(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) +int dpdmai_destroy(struct fsl_mc_io *mc_io, u32 cmd_flags, + u32 dpdmai_id, u16 token) { + struct dpdmai_cmd_destroy *cmd_params; struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_DESTROY, cmd_flags, token); + cmd_params = (struct dpdmai_cmd_destroy *)cmd.params; + cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); @@ -223,6 +199,40 @@ EXPORT_SYMBOL_GPL(dpdmai_disable); /** + * dpdmai_is_enabled() - Check if the DPDMAI is enabled. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * @en: Returns '1' if object is enabled; '0' otherwise + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_is_enabled(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, int *en) +{ + struct dpdmai_rsp_is_enabled *rsp_params; + struct fsl_mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_IS_ENABLED, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dpdmai_rsp_is_enabled *)cmd.params; + *en = dpdmai_get_field(rsp_params->en, ENABLE); + + return 0; +} +EXPORT_SYMBOL_GPL(dpdmai_is_enabled); + +/** * dpdmai_reset() - Reset the DPDMAI, returns the object to initial state. * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' @@ -271,9 +281,8 @@ /* retrieve response parameters */ rsp_params = (struct dpdmai_rsp_get_attributes *)cmd.params; attr->id = le32_to_cpu(rsp_params->id); - attr->version.major = le16_to_cpu(rsp_params->major); - attr->version.minor = le16_to_cpu(rsp_params->minor); attr->num_of_priorities = rsp_params->num_of_priorities; + attr->num_of_queues = rsp_params->num_of_queues; return 0; } @@ -290,23 +299,27 @@ * * Return: '0' on Success; Error code otherwise. */ -int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, - u8 priority, const struct dpdmai_rx_queue_cfg *cfg) +int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, u8 queue_idx, u8 priority, + const struct dpdmai_rx_queue_cfg *cfg) { - struct dpdmai_cmd_queue *cmd_params; + struct dpdmai_cmd_set_rx_queue *cmd_params; struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_RX_QUEUE, cmd_flags, token); - cmd_params = (struct dpdmai_cmd_queue *)cmd.params; + cmd_params = (struct dpdmai_cmd_set_rx_queue *)cmd.params; cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id); - cmd_params->priority = cfg->dest_cfg.priority; - cmd_params->queue = priority; - cmd_params->dest_type = cfg->dest_cfg.dest_type; + cmd_params->dest_priority = cfg->dest_cfg.priority; + cmd_params->priority = priority; + cmd_params->queue_idx = queue_idx; cmd_params->user_ctx = cpu_to_le64(cfg->user_ctx); cmd_params->options = cpu_to_le32(cfg->options); + dpdmai_set_field(cmd_params->dest_type, + DEST_TYPE, + cfg->dest_cfg.dest_type); /* send command to mc*/ return mc_send_command(mc_io, &cmd); @@ -324,10 +337,12 @@ * * Return: '0' on Success; Error code otherwise. */ -int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, - u8 priority, struct dpdmai_rx_queue_attr *attr) +int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, u8 queue_idx, u8 priority, + struct dpdmai_rx_queue_attr *attr) { - struct dpdmai_cmd_queue *cmd_params; + struct dpdmai_cmd_get_queue *cmd_params; + struct dpdmai_rsp_get_rx_queue *rsp_params; struct fsl_mc_command cmd = { 0 }; int err; @@ -335,8 +350,9 @@ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_RX_QUEUE, cmd_flags, token); - cmd_params = (struct dpdmai_cmd_queue *)cmd.params; - cmd_params->queue = priority; + cmd_params = (struct dpdmai_cmd_get_queue *)cmd.params; + cmd_params->priority = priority; + cmd_params->queue_idx = queue_idx; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -344,11 +360,13 @@ return err; /* retrieve response parameters */ - attr->dest_cfg.dest_id = le32_to_cpu(cmd_params->dest_id); - attr->dest_cfg.priority = cmd_params->priority; - attr->dest_cfg.dest_type = cmd_params->dest_type; - attr->user_ctx = le64_to_cpu(cmd_params->user_ctx); - attr->fqid = le32_to_cpu(cmd_params->fqid); + rsp_params = (struct dpdmai_rsp_get_rx_queue *)cmd.params; + attr->user_ctx = le64_to_cpu(rsp_params->user_ctx); + attr->fqid = le32_to_cpu(rsp_params->fqid); + attr->dest_cfg.dest_id = le32_to_cpu(rsp_params->dest_id); + attr->dest_cfg.priority = le32_to_cpu(rsp_params->dest_priority); + attr->dest_cfg.dest_type = dpdmai_get_field(rsp_params->dest_type, + DEST_TYPE); return 0; } @@ -366,10 +384,11 @@ * Return: '0' on Success; Error code otherwise. */ int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, - u16 token, u8 priority, u32 *fqid) + u16 token, u8 queue_idx, u8 priority, + struct dpdmai_tx_queue_attr *attr) { + struct dpdmai_cmd_get_queue *cmd_params; struct dpdmai_rsp_get_tx_queue *rsp_params; - struct dpdmai_cmd_queue *cmd_params; struct fsl_mc_command cmd = { 0 }; int err; @@ -377,8 +396,9 @@ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_TX_QUEUE, cmd_flags, token); - cmd_params = (struct dpdmai_cmd_queue *)cmd.params; - cmd_params->queue = priority; + cmd_params = (struct dpdmai_cmd_get_queue *)cmd.params; + cmd_params->priority = priority; + cmd_params->queue_idx = queue_idx; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -388,7 +408,7 @@ /* retrieve response parameters */ rsp_params = (struct dpdmai_rsp_get_tx_queue *)cmd.params; - *fqid = le32_to_cpu(rsp_params->fqid); + attr->fqid = le32_to_cpu(rsp_params->fqid); return 0; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/fsl-dpaa2-qdma/dpdmai.h linux-imx-phytec/drivers/dma/fsl-dpaa2-qdma/dpdmai.h --- linux-6.1.55/drivers/dma/fsl-dpaa2-qdma/dpdmai.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/fsl-dpaa2-qdma/dpdmai.h 2024-06-19 12:33:59.820218558 +0200 @@ -1,43 +1,45 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright 2019 NXP */ +/* Copyright 2019-2021 NXP */ #ifndef __FSL_DPDMAI_H #define __FSL_DPDMAI_H /* DPDMAI Version */ -#define DPDMAI_VER_MAJOR 2 -#define DPDMAI_VER_MINOR 2 +#define DPDMAI_VER_MAJOR 3 +#define DPDMAI_VER_MINOR 3 -#define DPDMAI_CMD_BASE_VERSION 0 +#define DPDMAI_CMD_BASE_VERSION 1 +#define DPDMAI_CMD_VERSION_2 2 #define DPDMAI_CMD_ID_OFFSET 4 -#define DPDMAI_CMDID_FORMAT(x) (((x) << DPDMAI_CMD_ID_OFFSET) | \ - DPDMAI_CMD_BASE_VERSION) +#define DPDMAI_CMD(id) ((id << DPDMAI_CMD_ID_OFFSET) | DPDMAI_CMD_BASE_VERSION) +#define DPDMAI_CMD_V2(id) ((id << DPDMAI_CMD_ID_OFFSET) | DPDMAI_CMD_VERSION_2) /* Command IDs */ -#define DPDMAI_CMDID_CLOSE DPDMAI_CMDID_FORMAT(0x800) -#define DPDMAI_CMDID_OPEN DPDMAI_CMDID_FORMAT(0x80E) -#define DPDMAI_CMDID_CREATE DPDMAI_CMDID_FORMAT(0x90E) -#define DPDMAI_CMDID_DESTROY DPDMAI_CMDID_FORMAT(0x900) - -#define DPDMAI_CMDID_ENABLE DPDMAI_CMDID_FORMAT(0x002) -#define DPDMAI_CMDID_DISABLE DPDMAI_CMDID_FORMAT(0x003) -#define DPDMAI_CMDID_GET_ATTR DPDMAI_CMDID_FORMAT(0x004) -#define DPDMAI_CMDID_RESET DPDMAI_CMDID_FORMAT(0x005) -#define DPDMAI_CMDID_IS_ENABLED DPDMAI_CMDID_FORMAT(0x006) - -#define DPDMAI_CMDID_SET_IRQ DPDMAI_CMDID_FORMAT(0x010) -#define DPDMAI_CMDID_GET_IRQ DPDMAI_CMDID_FORMAT(0x011) -#define DPDMAI_CMDID_SET_IRQ_ENABLE DPDMAI_CMDID_FORMAT(0x012) -#define DPDMAI_CMDID_GET_IRQ_ENABLE DPDMAI_CMDID_FORMAT(0x013) -#define DPDMAI_CMDID_SET_IRQ_MASK DPDMAI_CMDID_FORMAT(0x014) -#define DPDMAI_CMDID_GET_IRQ_MASK DPDMAI_CMDID_FORMAT(0x015) -#define DPDMAI_CMDID_GET_IRQ_STATUS DPDMAI_CMDID_FORMAT(0x016) -#define DPDMAI_CMDID_CLEAR_IRQ_STATUS DPDMAI_CMDID_FORMAT(0x017) - -#define DPDMAI_CMDID_SET_RX_QUEUE DPDMAI_CMDID_FORMAT(0x1A0) -#define DPDMAI_CMDID_GET_RX_QUEUE DPDMAI_CMDID_FORMAT(0x1A1) -#define DPDMAI_CMDID_GET_TX_QUEUE DPDMAI_CMDID_FORMAT(0x1A2) +#define DPDMAI_CMDID_CLOSE DPDMAI_CMD(0x800) +#define DPDMAI_CMDID_OPEN DPDMAI_CMD(0x80E) +#define DPDMAI_CMDID_CREATE DPDMAI_CMD_V2(0x90E) +#define DPDMAI_CMDID_DESTROY DPDMAI_CMD(0x98E) +#define DPDMAI_CMDID_GET_API_VERSION DPDMAI_CMD(0xa0E) + +#define DPDMAI_CMDID_ENABLE DPDMAI_CMD(0x002) +#define DPDMAI_CMDID_DISABLE DPDMAI_CMD(0x003) +#define DPDMAI_CMDID_GET_ATTR DPDMAI_CMD_V2(0x004) +#define DPDMAI_CMDID_RESET DPDMAI_CMD(0x005) +#define DPDMAI_CMDID_IS_ENABLED DPDMAI_CMD(0x006) + +#define DPDMAI_CMDID_SET_RX_QUEUE DPDMAI_CMD_V2(0x1A0) +#define DPDMAI_CMDID_GET_RX_QUEUE DPDMAI_CMD_V2(0x1A1) +#define DPDMAI_CMDID_GET_TX_QUEUE DPDMAI_CMD_V2(0x1A2) + +/* Macros for accessing command fields smaller than 1byte */ +#define DPDMAI_MASK(field) \ + GENMASK(DPDMAI_##field##_SHIFT + DPDMAI_##field##_SIZE - 1, \ + DPDMAI_##field##_SHIFT) +#define dpdmai_set_field(var, field, val) \ + ((var) |= (((val) << DPDMAI_##field##_SHIFT) & DPDMAI_MASK(field))) +#define dpdmai_get_field(var, field) \ + (((var) & DPDMAI_MASK(field)) >> DPDMAI_##field##_SHIFT) #define MC_CMD_HDR_TOKEN_O 32 /* Token field offset */ #define MC_CMD_HDR_TOKEN_S 16 /* Token field size */ @@ -49,11 +51,21 @@ * Contains initialization APIs and runtime control APIs for DPDMAI */ +/* + * Maximum number of Tx/Rx queues per DPDMAI object + */ +#define DPDMAI_MAX_QUEUE_NUM 8 + /** * Maximum number of Tx/Rx priorities per DPDMAI object */ #define DPDMAI_PRIO_NUM 2 +/** + * All queues considered; see dpdmai_set_rx_queue() + */ +#define DPDMAI_ALL_QUEUES ((uint8_t)(-1)) + /* DPDMAI queue modification options */ /** @@ -66,6 +78,69 @@ */ #define DPDMAI_QUEUE_OPT_DEST 0x2 +struct dpdmai_cmd_open { + u32 dpdmai_id; +}; + +struct dpdmai_cmd_create { + u8 num_queues; + u8 priorities[2]; +}; + +struct dpdmai_cmd_destroy { + u32 dpdmai_id; +}; + +#define DPDMAI_ENABLE_SHIFT 0 +#define DPDMAI_ENABLE_SIZE 1 + +struct dpdmai_rsp_is_enabled { + /* only the LSB bit */ + u8 en; +}; + +struct dpdmai_rsp_get_attributes { + u32 id; + u8 num_of_priorities; + u8 num_of_queues; +}; + +#define DPDMAI_DEST_TYPE_SHIFT 0 +#define DPDMAI_DEST_TYPE_SIZE 4 + +struct dpdmai_cmd_set_rx_queue { + u32 dest_id; + u8 dest_priority; + u8 priority; + /* from LSB: dest_type:4 */ + u8 dest_type; + u8 queue_idx; + u64 user_ctx; + u32 options; +}; + +struct dpdmai_cmd_get_queue { + u8 pad[5]; + u8 priority; + u8 queue_idx; +}; + +struct dpdmai_rsp_get_rx_queue { + u32 dest_id; + u8 dest_priority; + u8 pad1; + /* from LSB: dest_type:4 */ + u8 dest_type; + u8 pad2; + u64 user_ctx; + u32 fqid; +}; + +struct dpdmai_rsp_get_tx_queue { + u64 pad; + u32 fqid; +}; + /** * struct dpdmai_cfg - Structure representing DPDMAI configuration * @priorities: Priorities for the DMA hardware processing; valid priorities are @@ -73,6 +148,7 @@ * should be configured with 0 */ struct dpdmai_cfg { + u8 num_queues; u8 priorities[DPDMAI_PRIO_NUM]; }; @@ -83,17 +159,14 @@ * @num_of_priorities: number of priorities */ struct dpdmai_attr { - int id; + int id; /** * struct version - DPDMAI version * @major: DPDMAI major version * @minor: DPDMAI minor version */ - struct { - u16 major; - u16 minor; - } version; u8 num_of_priorities; + u8 num_of_queues; }; /** @@ -158,22 +231,33 @@ u32 fqid; }; +struct dpdmai_tx_queue_attr { + u32 fqid; +}; + int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpdmai_id, u16 *token); int dpdmai_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -int dpdmai_destroy(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); int dpdmai_create(struct fsl_mc_io *mc_io, u32 cmd_flags, - const struct dpdmai_cfg *cfg, u16 *token); + const struct dpdmai_cfg *cfg, u16 token, + u32 *dpdmai_id); +int dpdmai_destroy(struct fsl_mc_io *mc_io, u32 cmd_flags, + u32 dpdmai_id, u16 token); int dpdmai_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); int dpdmai_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpdmai_is_enabled(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, int *en); int dpdmai_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); int dpdmai_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpdmai_attr *attr); -int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, - u8 priority, const struct dpdmai_rx_queue_cfg *cfg); -int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, - u8 priority, struct dpdmai_rx_queue_attr *attr); +int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, u8 queue_idx, u8 priority, + const struct dpdmai_rx_queue_cfg *cfg); +int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, u8 queue_idx, u8 priority, + struct dpdmai_rx_queue_attr *attr); int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, - u16 token, u8 priority, u32 *fqid); + u16 token, u8 queue_idx, u8 priority, + struct dpdmai_tx_queue_attr *attr); #endif /* __FSL_DPDMAI_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/fsl-edma.c linux-imx-phytec/drivers/dma/fsl-edma.c --- linux-6.1.55/drivers/dma/fsl-edma.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/fsl-edma.c 2024-06-19 12:33:59.820218558 +0200 @@ -2,11 +2,12 @@ /* * drivers/dma/fsl-edma.c * - * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2020 NXP * * Driver for the Freescale eDMA engine with flexible channel multiplexing * capability for DMA request sources. The eDMA block can be found on some - * Vybrid and Layerscape SoCs. + * Vybrid, Layerscape and S32V234 SoCs. */ #include @@ -54,6 +55,7 @@ } if (!fsl_chan->edesc->iscyclic) { + fsl_edma_get_realcnt(fsl_chan); list_del(&fsl_chan->edesc->vdesc.node); vchan_cookie_complete(&fsl_chan->edesc->vdesc); fsl_chan->edesc = NULL; @@ -139,23 +141,23 @@ { int ret; - fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); - if (fsl_edma->txirq < 0) - return fsl_edma->txirq; + *fsl_edma->txirqs = platform_get_irq_byname(pdev, "edma-tx"); + if (*fsl_edma->txirqs < 0) + return *fsl_edma->txirqs; fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); if (fsl_edma->errirq < 0) return fsl_edma->errirq; - if (fsl_edma->txirq == fsl_edma->errirq) { - ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, + if (*fsl_edma->txirqs == fsl_edma->errirq) { + ret = devm_request_irq(&pdev->dev, *fsl_edma->txirqs, fsl_edma_irq_handler, 0, "eDMA", fsl_edma); if (ret) { dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); return ret; } } else { - ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, + ret = devm_request_irq(&pdev->dev, *fsl_edma->txirqs, fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); if (ret) { dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); @@ -178,14 +180,7 @@ struct fsl_edma_engine *fsl_edma) { int i, ret, irq; - int count; - - count = platform_irq_count(pdev); - dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); - if (count <= 2) { - dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); - return -EINVAL; - } + int count = fsl_edma->drvdata->txirq_count + 1; /* * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17... @@ -200,15 +195,18 @@ sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i); /* The last IRQ is for eDMA err */ - if (i == count - 1) + if (i == count - 1) { + fsl_edma->errirq = irq; ret = devm_request_irq(&pdev->dev, irq, fsl_edma_err_handler, 0, "eDMA2-ERR", fsl_edma); - else + } else { + fsl_edma->txirqs[i] = irq; ret = devm_request_irq(&pdev->dev, irq, fsl_edma_tx_handler, 0, fsl_edma->chans[i].chan_name, fsl_edma); + } if (ret) return ret; } @@ -216,15 +214,59 @@ return 0; } +static int fsl_edma_irq_init_s32(struct platform_device *pdev, + struct fsl_edma_engine *fsl_edma) +{ + int i, ret, irq, txirq_count = fsl_edma->drvdata->txirq_count; + static const char * const names[] = {"edma-tx_0-15", "edma-tx_16-31", + "edma-err"}; + + for (i = 0; i <= txirq_count; i++) { + irq = platform_get_irq_byname(pdev, names[i]); + if (irq < 0) { + dev_err(&pdev->dev, "Can't get %s IRQ.\n", + names[i]); + return irq; + } + + if (i == txirq_count) { + fsl_edma->errirq = irq; + ret = devm_request_irq(&pdev->dev, irq, + fsl_edma_err_handler, 0, + names[i], fsl_edma); + } else { + fsl_edma->txirqs[i] = irq; + ret = devm_request_irq(&pdev->dev, irq, + fsl_edma_tx_handler, 0, + names[i], fsl_edma); + } + + if (ret) { + dev_err(&pdev->dev, + "Can't register %s IRQ.\n", + names[i]); + return ret; + } + } + + return 0; +} + static void fsl_edma_irq_exit( struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) { - if (fsl_edma->txirq == fsl_edma->errirq) { - devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); - } else { - devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); - devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); + int i; + bool free_errirq = true; + u8 count = fsl_edma->drvdata->txirq_count; + + for (i = 0; i < count; i++) { + devm_free_irq(&pdev->dev, fsl_edma->txirqs[i], fsl_edma); + if (fsl_edma->txirqs[i] == fsl_edma->errirq) + free_errirq = false; } + + if (free_errirq) + devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); } static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) @@ -239,6 +281,7 @@ .version = v1, .dmamuxs = DMAMUX_NR, .setup_irq = fsl_edma_irq_init, + .txirq_count = 1, }; static struct fsl_edma_drvdata ls1028a_data = { @@ -246,6 +289,7 @@ .dmamuxs = DMAMUX_NR, .mux_swap = true, .setup_irq = fsl_edma_irq_init, + .txirq_count = 1, }; static struct fsl_edma_drvdata imx7ulp_data = { @@ -253,12 +297,22 @@ .dmamuxs = 1, .has_dmaclk = true, .setup_irq = fsl_edma2_irq_init, + .txirq_count = 16, +}; + +static struct fsl_edma_drvdata s32v234_data = { + .version = v1, + .dmamuxs = DMAMUX_NR, + .mux_swap = true, + .setup_irq = fsl_edma_irq_init_s32, + .txirq_count = 2, }; static const struct of_device_id fsl_edma_dt_ids[] = { { .compatible = "fsl,vf610-edma", .data = &vf610_data}, { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, + { .compatible = "fsl,s32v234-edma", .data = &s32v234_data}, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); @@ -366,6 +420,12 @@ } edma_writel(fsl_edma, ~0, regs->intl); + + fsl_edma->txirqs = devm_kzalloc(&pdev->dev, + drvdata->txirq_count * sizeof(*fsl_edma->txirqs), GFP_KERNEL); + if (!fsl_edma->txirqs) + return -ENOMEM; + ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); if (ret) return ret; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/fsl-edma-common.c linux-imx-phytec/drivers/dma/fsl-edma-common.c --- linux-6.1.55/drivers/dma/fsl-edma-common.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/fsl-edma-common.c 2024-06-19 12:33:59.820218558 +0200 @@ -4,6 +4,7 @@ // Copyright (c) 2017 Sysam, Angelo Dureghello #include +#include #include #include #include @@ -160,11 +161,24 @@ int fsl_edma_terminate_all(struct dma_chan *chan) { struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); + struct edma_regs *regs = &fsl_chan->edma->regs; + u32 ch = fsl_chan->vchan.chan.chan_id; unsigned long flags; + int count = 0; LIST_HEAD(head); - spin_lock_irqsave(&fsl_chan->vchan.lock, flags); fsl_edma_disable_request(fsl_chan); + + /* + * Checking ACTIVE to ensure minor loop stop indeed to prevent the + * potential illegal memory write if channel not stopped with buffer + * freed. + */ + while (count++ < EDMA_MINOR_LOOP_TIMEOUT && (EDMA_TCD_CSR_ACTIVE & + edma_readw(fsl_chan->edma, ®s->tcd[ch].csr))) + udelay(1); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); fsl_chan->edesc = NULL; fsl_chan->idle = true; vchan_get_all_descriptors(&fsl_chan->vchan, &head); @@ -310,6 +324,11 @@ return len; } +void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan) +{ + fsl_chan->chn_real_count = fsl_edma_desc_residue(fsl_chan, NULL, true); +} + enum dma_status fsl_edma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { @@ -319,8 +338,12 @@ unsigned long flags; status = dma_cookie_status(chan, cookie, txstate); - if (status == DMA_COMPLETE) + if (status == DMA_COMPLETE) { + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + txstate->residue = fsl_chan->chn_real_count; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); return status; + } if (!txstate) return fsl_chan->status; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/fsl-edma-common.h linux-imx-phytec/drivers/dma/fsl-edma-common.h --- linux-6.1.55/drivers/dma/fsl-edma-common.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/fsl-edma-common.h 2024-06-19 12:33:59.820218558 +0200 @@ -2,6 +2,7 @@ /* * Copyright 2013-2014 Freescale Semiconductor, Inc. * Copyright 2018 Angelo Dureghello + * Copyright 2020 NXP */ #ifndef _FSL_EDMA_COMMON_H_ #define _FSL_EDMA_COMMON_H_ @@ -58,6 +59,8 @@ #define DMAMUX_NR 2 +#define EDMA_MINOR_LOOP_TIMEOUT 500 /* us */ + #define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ @@ -127,6 +130,7 @@ u32 dma_dev_size; enum dma_data_direction dma_dir; char chan_name[16]; + u32 chn_real_count; }; struct fsl_edma_desc { @@ -151,6 +155,7 @@ bool mux_swap; int (*setup_irq)(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma); + u8 txirq_count; }; struct fsl_edma_engine { @@ -162,7 +167,7 @@ struct mutex fsl_edma_mutex; const struct fsl_edma_drvdata *drvdata; u32 n_chans; - int txirq; + int *txirqs; int errirq; bool big_endian; struct edma_regs regs; @@ -183,6 +188,14 @@ return ioread32(addr); } +static inline u32 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr) +{ + if (edma->big_endian) + return ioread16be(addr); + else + return ioread16(addr); +} + static inline void edma_writeb(struct fsl_edma_engine *edma, u8 val, void __iomem *addr) { @@ -231,6 +244,7 @@ int fsl_edma_resume(struct dma_chan *chan); int fsl_edma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg); +void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan); enum dma_status fsl_edma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate); struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/fsl-edma-v3.c linux-imx-phytec/drivers/dma/fsl-edma-v3.c --- linux-6.1.55/drivers/dma/fsl-edma-v3.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/dma/fsl-edma-v3.c 2024-06-19 12:33:59.820218558 +0200 @@ -0,0 +1,1429 @@ +/* + * drivers/dma/fsl-edma3-v3.c + * + * Copyright 2017-2018 NXP . + * + * Driver for the Freescale eDMA engine v3. This driver based on fsl-edma3.c + * but changed to meet the IP change on i.MX8QM: every dma channel is specific + * to hardware. For example, channel 14 for LPUART1 receive request and channel + * 13 for transmit requesst. The eDMA block can be found on i.MX8QM + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "virt-dma.h" + +#define EDMA_CH_CSR 0x00 +#define EDMA_CH_ES 0x04 +#define EDMA_CH_INT 0x08 +#define EDMA_CH_SBR 0x0C +#define EDMA_CH_PRI 0x10 +#define EDMA_CH_MUX 0x14 +#define EDMA_TCD_SADDR 0x20 +#define EDMA_TCD_SOFF 0x24 +#define EDMA_TCD_ATTR 0x26 +#define EDMA_TCD_NBYTES 0x28 +#define EDMA_TCD_SLAST 0x2C +#define EDMA_TCD_DADDR 0x30 +#define EDMA_TCD_DOFF 0x34 +#define EDMA_TCD_CITER_ELINK 0x36 +#define EDMA_TCD_CITER 0x36 +#define EDMA_TCD_DLAST_SGA 0x38 +#define EDMA_TCD_CSR 0x3C +#define EDMA_TCD_BITER_ELINK 0x3E +#define EDMA_TCD_BITER 0x3E + +#define EDMA_CH_SBR_RD BIT(22) +#define EDMA_CH_SBR_WR BIT(21) +#define EDMA_CH_CSR_ERQ BIT(0) +#define EDMA_CH_CSR_EARQ BIT(1) +#define EDMA_CH_CSR_EEI BIT(2) +#define EDMA_CH_CSR_DONE BIT(30) +#define EDMA_CH_CSR_ACTIVE BIT(31) + +#define EDMA_TCD_ATTR_DSIZE(x) (((x) & 0x0007)) +#define EDMA_TCD_ATTR_DMOD(x) (((x) & 0x001F) << 3) +#define EDMA_TCD_ATTR_SSIZE(x) (((x) & 0x0007) << 8) +#define EDMA_TCD_ATTR_SMOD(x) (((x) & 0x001F) << 11) +#define EDMA_TCD_ATTR_SSIZE_8BIT (0x0000) +#define EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) +#define EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) +#define EDMA_TCD_ATTR_SSIZE_64BIT (0x0300) +#define EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400) +#define EDMA_TCD_ATTR_SSIZE_32BYTE (0x0500) +#define EDMA_TCD_ATTR_SSIZE_64BYTE (0x0600) +#define EDMA_TCD_ATTR_DSIZE_8BIT (0x0000) +#define EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) +#define EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) +#define EDMA_TCD_ATTR_DSIZE_64BIT (0x0003) +#define EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004) +#define EDMA_TCD_ATTR_DSIZE_32BYTE (0x0005) +#define EDMA_TCD_ATTR_DSIZE_64BYTE (0x0006) + +#define EDMA_TCD_SOFF_SOFF(x) (x) +#define EDMA_TCD_NBYTES_NBYTES(x) (x) +#define EDMA_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0)) +#define EDMA_TCD_NBYTES_MLOFF(x) (x << 10) +#define EDMA_TCD_NBYTES_DMLOE (1 << 30) +#define EDMA_TCD_NBYTES_SMLOE (1 << 31) +#define EDMA_TCD_SLAST_SLAST(x) (x) +#define EDMA_TCD_DADDR_DADDR(x) (x) +#define EDMA_TCD_CITER_CITER(x) ((x) & 0x7FFF) +#define EDMA_TCD_DOFF_DOFF(x) (x) +#define EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x) +#define EDMA_TCD_BITER_BITER(x) ((x) & 0x7FFF) + +#define EDMA_TCD_CSR_START BIT(0) +#define EDMA_TCD_CSR_INT_MAJOR BIT(1) +#define EDMA_TCD_CSR_INT_HALF BIT(2) +#define EDMA_TCD_CSR_D_REQ BIT(3) +#define EDMA_TCD_CSR_E_SG BIT(4) +#define EDMA_TCD_CSR_E_LINK BIT(5) +#define EDMA_TCD_CSR_ACTIVE BIT(6) +#define EDMA_TCD_CSR_DONE BIT(7) + +#define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_16_BYTES)) + +#define ARGS_RX BIT(0) +#define ARGS_REMOTE BIT(1) +#define ARGS_MULTI_FIFO BIT(2) + +/* channel name template define in dts */ +#define CHAN_PREFIX "edma0-chan" +#define CHAN_POSFIX "-tx" +#define CLK_POSFIX "-clk" + +#define EDMA_MINOR_LOOP_TIMEOUT 500 /* us */ + +struct fsl_edma3_hw_tcd { + __le32 saddr; + __le16 soff; + __le16 attr; + __le32 nbytes; + __le32 slast; + __le32 daddr; + __le16 doff; + __le16 citer; + __le32 dlast_sga; + __le16 csr; + __le16 biter; +}; + +struct fsl_edma3_sw_tcd { + dma_addr_t ptcd; + struct fsl_edma3_hw_tcd *vtcd; +}; + +struct fsl_edma3_slave_config { + enum dma_transfer_direction dir; + enum dma_slave_buswidth addr_width; + u32 dev_addr; + u32 dev2_addr; /* source addr for dev2dev */ + u32 burst; + u32 attr; +}; + +struct fsl_edma3_chan { + struct virt_dma_chan vchan; + enum dma_status status; + bool idle; + struct fsl_edma3_engine *edma3; + struct fsl_edma3_desc *edesc; + struct fsl_edma3_slave_config fsc; + void __iomem *membase; + int txirq; + int hw_chanid; + int priority; + int is_rxchan; + int is_remote; + int is_multi_fifo; + bool is_sw; + struct dma_pool *tcd_pool; + u32 chn_real_count; + char txirq_name[32]; + struct platform_device *pdev; + struct device *dev; + struct work_struct issue_worker; + u32 srcid; + struct clk *clk; +}; + +struct fsl_edma3_drvdata { + bool has_pd; + u32 dmamuxs; + bool has_chclk; + bool has_chmux; +}; + +struct fsl_edma3_desc { + struct virt_dma_desc vdesc; + struct fsl_edma3_chan *echan; + bool iscyclic; + unsigned int n_tcds; + struct fsl_edma3_sw_tcd tcd[]; +}; + +struct fsl_edma3_reg_save { + u32 csr; + u32 sbr; +}; + +struct fsl_edma3_engine { + struct dma_device dma_dev; + unsigned long irqflag; + struct mutex fsl_edma3_mutex; + u32 n_chans; + int errirq; + #define MAX_CHAN_NUM 64 + struct fsl_edma3_reg_save edma_regs[MAX_CHAN_NUM]; + bool swap; /* remote/local swapped on Audio edma */ + bool bus_axi; + const struct fsl_edma3_drvdata *drvdata; + struct clk *clk_mp; + struct clk *dmaclk; + struct fsl_edma3_chan chans[]; +}; + + +static struct fsl_edma3_drvdata fsl_edma_imx8q = { + .has_pd = true, + .dmamuxs = 0, + .has_chclk = false, + .has_chmux = true, +}; + +static struct fsl_edma3_drvdata fsl_edma_imx8ulp = { + .has_pd = false, + .dmamuxs = 1, + .has_chclk = true, + .has_chmux = true, +}; + +static struct fsl_edma3_drvdata fsl_edma_imx93 = { + .has_pd = false, + .dmamuxs = 0, + .has_chclk = false, + .has_chmux = false, +}; + +static struct fsl_edma3_chan *to_fsl_edma3_chan(struct dma_chan *chan) +{ + return container_of(chan, struct fsl_edma3_chan, vchan.chan); +} + +static struct fsl_edma3_desc *to_fsl_edma3_desc(struct virt_dma_desc *vd) +{ + return container_of(vd, struct fsl_edma3_desc, vdesc); +} + +static bool is_srcid_in_use(struct fsl_edma3_engine *fsl_edma3, u32 srcid) +{ + struct fsl_edma3_chan *fsl_chan; + int i; + + for (i = 0; i < fsl_edma3->n_chans; i++) { + fsl_chan = &fsl_edma3->chans[i]; + + if (fsl_chan->srcid && srcid == fsl_chan->srcid) { + dev_err(&fsl_chan->pdev->dev, "The srcid is using! Can't use repeatly."); + return true; + } + } + return false; +} + +static void fsl_edma3_enable_request(struct fsl_edma3_chan *fsl_chan) +{ + void __iomem *addr = fsl_chan->membase; + u32 val; + + val = readl(addr + EDMA_CH_SBR); + /* Remote/local swapped wrongly on iMX8 QM Audio edma */ + if (fsl_chan->edma3->swap) { + if (!fsl_chan->is_rxchan) + val |= EDMA_CH_SBR_RD; + else + val |= EDMA_CH_SBR_WR; + } else { + if (fsl_chan->is_rxchan) + val |= EDMA_CH_SBR_RD; + else + val |= EDMA_CH_SBR_WR; + } + + if (fsl_chan->is_remote) + val &= ~(EDMA_CH_SBR_RD | EDMA_CH_SBR_WR); + + writel(val, addr + EDMA_CH_SBR); + + if ((fsl_chan->edma3->drvdata->has_chmux || fsl_chan->edma3->bus_axi) && + fsl_chan->srcid && !readl(addr + EDMA_CH_MUX)) + writel(fsl_chan->srcid, addr + EDMA_CH_MUX); + + val = readl(addr + EDMA_CH_CSR); + + val |= EDMA_CH_CSR_ERQ; + writel(val, addr + EDMA_CH_CSR); +} + +static void fsl_edma3_disable_request(struct fsl_edma3_chan *fsl_chan) +{ + void __iomem *addr = fsl_chan->membase; + u32 val = readl(addr + EDMA_CH_CSR); + + if ((fsl_chan->edma3->drvdata->has_chmux || fsl_chan->edma3->bus_axi) && + fsl_chan->srcid) + writel(0, addr + EDMA_CH_MUX); + + val &= ~EDMA_CH_CSR_ERQ; + writel(val, addr + EDMA_CH_CSR); +} + +static unsigned int fsl_edma3_get_tcd_attr(enum dma_slave_buswidth addr_width) +{ + switch (addr_width) { + case 1: + return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT; + case 2: + return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT; + case 4: + return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; + case 8: + return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT; + case 16: + return EDMA_TCD_ATTR_SSIZE_16BYTE | EDMA_TCD_ATTR_DSIZE_16BYTE; + case 32: + return EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE; + case 64: + return EDMA_TCD_ATTR_SSIZE_64BYTE | EDMA_TCD_ATTR_DSIZE_64BYTE; + default: + return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; + } +} + +static void fsl_edma3_free_desc(struct virt_dma_desc *vdesc) +{ + struct fsl_edma3_desc *fsl_desc; + int i; + + fsl_desc = to_fsl_edma3_desc(vdesc); + for (i = 0; i < fsl_desc->n_tcds; i++) + dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, + fsl_desc->tcd[i].ptcd); + kfree(fsl_desc); +} + +static int fsl_edma3_terminate_all(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + LIST_HEAD(head); + u32 val; + + fsl_edma3_disable_request(fsl_chan); + + /* + * Checking ACTIVE to ensure minor loop stop indeed to prevent the + * potential illegal memory write if channel not stopped with buffer + * freed. Ignore tx channel since no such risk. + */ + if (fsl_chan->is_rxchan) + readl_poll_timeout_atomic(fsl_chan->membase + EDMA_CH_CSR, val, + !(val & EDMA_CH_CSR_ACTIVE), 2, + EDMA_MINOR_LOOP_TIMEOUT); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_chan->edesc = NULL; + fsl_chan->idle = true; + fsl_chan->vchan.cyclic = NULL; + vchan_get_all_descriptors(&fsl_chan->vchan, &head); + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + vchan_dma_desc_free_list(&fsl_chan->vchan, &head); + + if (fsl_chan->edma3->drvdata->has_pd) + pm_runtime_allow(fsl_chan->dev); + + return 0; +} + +static int fsl_edma3_pause(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + if (fsl_chan->edesc) { + fsl_edma3_disable_request(fsl_chan); + fsl_chan->status = DMA_PAUSED; + fsl_chan->idle = true; + } + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + return 0; +} + +static int fsl_edma3_resume(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + if (fsl_chan->edesc) { + fsl_edma3_enable_request(fsl_chan); + fsl_chan->status = DMA_IN_PROGRESS; + fsl_chan->idle = false; + } + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + return 0; +} + +static int fsl_edma3_slave_config(struct dma_chan *chan, + struct dma_slave_config *cfg) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + + fsl_chan->fsc.dir = cfg->direction; + if (cfg->direction == DMA_DEV_TO_MEM) { + fsl_chan->fsc.dev_addr = cfg->src_addr; + fsl_chan->fsc.addr_width = cfg->src_addr_width; + fsl_chan->fsc.burst = cfg->src_maxburst; + fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr + (cfg->src_addr_width); + } else if (cfg->direction == DMA_MEM_TO_DEV) { + fsl_chan->fsc.dev_addr = cfg->dst_addr; + fsl_chan->fsc.addr_width = cfg->dst_addr_width; + fsl_chan->fsc.burst = cfg->dst_maxburst; + fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr + (cfg->dst_addr_width); + } else if (cfg->direction == DMA_DEV_TO_DEV) { + fsl_chan->fsc.dev2_addr = cfg->src_addr; + fsl_chan->fsc.dev_addr = cfg->dst_addr; + fsl_chan->fsc.addr_width = cfg->dst_addr_width; + fsl_chan->fsc.burst = cfg->dst_maxburst; + fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr + (cfg->dst_addr_width); + } else { + return -EINVAL; + } + return 0; +} + +static size_t fsl_edma3_desc_residue(struct fsl_edma3_chan *fsl_chan, + struct virt_dma_desc *vdesc, bool in_progress) +{ + struct fsl_edma3_desc *edesc = fsl_chan->edesc; + void __iomem *addr = fsl_chan->membase; + enum dma_transfer_direction dir = fsl_chan->fsc.dir; + dma_addr_t cur_addr, dma_addr; + size_t len, size; + u32 nbytes = 0; + int i; + + /* calculate the total size in this desc */ + for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) { + if ((edesc->tcd[i].vtcd->nbytes & EDMA_TCD_NBYTES_DMLOE) || + (edesc->tcd[i].vtcd->nbytes & EDMA_TCD_NBYTES_SMLOE)) + nbytes = EDMA_TCD_NBYTES_MLOFF_NBYTES(edesc->tcd[i].vtcd->nbytes); + else + nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes); + + len += nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter); + } + + if (!in_progress) + return len; + + if (dir == DMA_MEM_TO_DEV) + cur_addr = readl(addr + EDMA_TCD_SADDR); + else + cur_addr = readl(addr + EDMA_TCD_DADDR); + + /* figure out the finished and calculate the residue */ + for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { + if ((edesc->tcd[i].vtcd->nbytes & EDMA_TCD_NBYTES_DMLOE) || + (edesc->tcd[i].vtcd->nbytes & EDMA_TCD_NBYTES_SMLOE)) + nbytes = EDMA_TCD_NBYTES_MLOFF_NBYTES(edesc->tcd[i].vtcd->nbytes); + else + nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes); + + size = nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter); + + if (dir == DMA_MEM_TO_DEV) + dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); + else + dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); + + len -= size; + if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { + len += dma_addr + size - cur_addr; + break; + } + } + + return len; +} + +static enum dma_status fsl_edma3_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, struct dma_tx_state *txstate) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct virt_dma_desc *vdesc; + enum dma_status status; + unsigned long flags; + + status = dma_cookie_status(chan, cookie, txstate); + if (status == DMA_COMPLETE) { + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + txstate->residue = fsl_chan->chn_real_count; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + return status; + } + + if (!txstate) + return fsl_chan->status; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); + if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) + txstate->residue = fsl_edma3_desc_residue(fsl_chan, vdesc, + true); + else if (fsl_chan->edesc && vdesc) + txstate->residue = fsl_edma3_desc_residue(fsl_chan, vdesc, + false); + else + txstate->residue = 0; + + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + return fsl_chan->status; +} + +static void fsl_edma3_set_tcd_regs(struct fsl_edma3_chan *fsl_chan, + struct fsl_edma3_hw_tcd *tcd) +{ + void __iomem *addr = fsl_chan->membase; + /* + * TCD parameters are stored in struct fsl_edma3_hw_tcd in little + * endian format. However, we need to load the TCD registers in + * big- or little-endian obeying the eDMA engine model endian. + */ + writew(0, addr + EDMA_TCD_CSR); + writel(le32_to_cpu(tcd->saddr), addr + EDMA_TCD_SADDR); + writel(le32_to_cpu(tcd->daddr), addr + EDMA_TCD_DADDR); + + writew(le16_to_cpu(tcd->attr), addr + EDMA_TCD_ATTR); + writew(le16_to_cpu(tcd->soff), addr + EDMA_TCD_SOFF); + + writel(le32_to_cpu(tcd->nbytes), addr + EDMA_TCD_NBYTES); + writel(le32_to_cpu(tcd->slast), addr + EDMA_TCD_SLAST); + + writew(le16_to_cpu(tcd->citer), addr + EDMA_TCD_CITER); + writew(le16_to_cpu(tcd->biter), addr + EDMA_TCD_BITER); + writew(le16_to_cpu(tcd->doff), addr + EDMA_TCD_DOFF); + + writel(le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA); + + /* Must clear CHa_CSR[DONE] bit before enable TCDa_CSR[ESG] */ + writel(readl(addr + EDMA_CH_CSR), addr + EDMA_CH_CSR); + + writew(le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR); +} + +static inline +void fsl_edma3_fill_tcd(struct fsl_edma3_chan *fsl_chan, + struct fsl_edma3_hw_tcd *tcd, u32 src, u32 dst, + u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, + u16 biter, u16 doff, u32 dlast_sga, bool major_int, + bool disable_req, bool enable_sg) +{ + u16 csr = 0; + + /* + * eDMA hardware SGs require the TCDs to be stored in little + * endian format irrespective of the register endian model. + * So we put the value in little endian in memory, waiting + * for fsl_edma3_set_tcd_regs doing the swap. + */ + tcd->saddr = cpu_to_le32(src); + tcd->daddr = cpu_to_le32(dst); + + tcd->attr = cpu_to_le16(attr); + + tcd->soff = cpu_to_le16(EDMA_TCD_SOFF_SOFF(soff)); + + if (fsl_chan->is_multi_fifo) { + /* set mloff to support multiple fifo */ + nbytes |= EDMA_TCD_NBYTES_MLOFF(-(fsl_chan->fsc.burst * 4)); + /* enable DMLOE/SMLOE */ + if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { + nbytes |= EDMA_TCD_NBYTES_DMLOE; + nbytes &= ~EDMA_TCD_NBYTES_SMLOE; + } else { + nbytes |= EDMA_TCD_NBYTES_SMLOE; + nbytes &= ~EDMA_TCD_NBYTES_DMLOE; + } + } + + tcd->nbytes = cpu_to_le32(EDMA_TCD_NBYTES_NBYTES(nbytes)); + tcd->slast = cpu_to_le32(EDMA_TCD_SLAST_SLAST(slast)); + + tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); + tcd->doff = cpu_to_le16(EDMA_TCD_DOFF_DOFF(doff)); + + tcd->dlast_sga = cpu_to_le32(EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga)); + + tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); + if (major_int) + csr |= EDMA_TCD_CSR_INT_MAJOR; + + if (disable_req) + csr |= EDMA_TCD_CSR_D_REQ; + + if (enable_sg) + csr |= EDMA_TCD_CSR_E_SG; + + if (fsl_chan->is_rxchan) + csr |= EDMA_TCD_CSR_ACTIVE; + + if (fsl_chan->is_sw) + csr |= EDMA_TCD_CSR_START; + + tcd->csr = cpu_to_le16(csr); +} + +static struct fsl_edma3_desc *fsl_edma3_alloc_desc(struct fsl_edma3_chan + *fsl_chan, int sg_len) +{ + struct fsl_edma3_desc *fsl_desc; + int i; + + fsl_desc = kzalloc(sizeof(*fsl_desc) + sizeof(struct fsl_edma3_sw_tcd) + * sg_len, GFP_ATOMIC); + if (!fsl_desc) + return NULL; + + fsl_desc->echan = fsl_chan; + fsl_desc->n_tcds = sg_len; + for (i = 0; i < sg_len; i++) { + fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, + GFP_ATOMIC, &fsl_desc->tcd[i].ptcd); + if (!fsl_desc->tcd[i].vtcd) + goto err; + } + return fsl_desc; + +err: + while (--i >= 0) + dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, + fsl_desc->tcd[i].ptcd); + kfree(fsl_desc); + return NULL; +} + +static struct dma_async_tx_descriptor *fsl_edma3_prep_dma_cyclic( + struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, + size_t period_len, enum dma_transfer_direction direction, + unsigned long flags) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct fsl_edma3_desc *fsl_desc; + dma_addr_t dma_buf_next; + int sg_len, i; + u32 src_addr, dst_addr, last_sg, nbytes; + u16 soff, doff, iter; + bool major_int = true; + + sg_len = buf_len / period_len; + fsl_desc = fsl_edma3_alloc_desc(fsl_chan, sg_len); + if (!fsl_desc) + return NULL; + fsl_desc->iscyclic = true; + + dma_buf_next = dma_addr; + nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; + + /* + * Choose the suitable burst length if period_len is not multiple of + * burst length so that the whole transfer length is multiple of minor + * loop(burst length). + */ + if (period_len % nbytes) { + u32 width = fsl_chan->fsc.addr_width; + + for (i = fsl_chan->fsc.burst; i > 1; i--) { + if (!(period_len % (i * width))) { + nbytes = i * width; + break; + } + } + /* if no chance to get suitable burst size, use it as 1 */ + if (i == 1) + nbytes = width; + } + + iter = period_len / nbytes; + + for (i = 0; i < sg_len; i++) { + if (dma_buf_next >= dma_addr + buf_len) + dma_buf_next = dma_addr; + + /* get next sg's physical address */ + last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; + + if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { + src_addr = dma_buf_next; + dst_addr = fsl_chan->fsc.dev_addr; + soff = fsl_chan->fsc.addr_width; + if (fsl_chan->is_multi_fifo) + doff = 4; + else + doff = 0; + } else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) { + src_addr = fsl_chan->fsc.dev_addr; + dst_addr = dma_buf_next; + if (fsl_chan->is_multi_fifo) + soff = 4; + else + soff = 0; + doff = fsl_chan->fsc.addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr = fsl_chan->fsc.dev2_addr; + dst_addr = fsl_chan->fsc.dev_addr; + soff = 0; + doff = 0; + major_int = false; + } + + fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->fsc.attr, soff, nbytes, 0, + iter, iter, doff, last_sg, major_int, false, true); + dma_buf_next += period_len; + } + + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); +} + +static struct dma_async_tx_descriptor *fsl_edma3_prep_slave_sg( + struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct fsl_edma3_desc *fsl_desc; + struct scatterlist *sg; + u32 src_addr, dst_addr, last_sg, nbytes; + u16 soff, doff, iter; + int i; + + if (!is_slave_direction(fsl_chan->fsc.dir)) + return NULL; + + fsl_desc = fsl_edma3_alloc_desc(fsl_chan, sg_len); + if (!fsl_desc) + return NULL; + fsl_desc->iscyclic = false; + + nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; + for_each_sg(sgl, sg, sg_len, i) { + /* get next sg's physical address */ + last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; + + if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { + src_addr = sg_dma_address(sg); + dst_addr = fsl_chan->fsc.dev_addr; + soff = fsl_chan->fsc.addr_width; + doff = 0; + } else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) { + src_addr = fsl_chan->fsc.dev_addr; + dst_addr = sg_dma_address(sg); + soff = 0; + doff = fsl_chan->fsc.addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr = fsl_chan->fsc.dev2_addr; + dst_addr = fsl_chan->fsc.dev_addr; + soff = 0; + doff = 0; + } + + /* + * Choose the suitable burst length if sg_dma_len is not + * multiple of burst length so that the whole transfer length is + * multiple of minor loop(burst length). + */ + if (sg_dma_len(sg) % nbytes) { + u32 width = fsl_chan->fsc.addr_width; + int j; + + for (j = fsl_chan->fsc.burst; j > 1; j--) { + if (!(sg_dma_len(sg) % (j * width))) { + nbytes = j * width; + break; + } + } + /* Set burst size as 1 if there's no suitable one */ + if (j == 1) + nbytes = width; + } + + iter = sg_dma_len(sg) / nbytes; + if (i < sg_len - 1) { + last_sg = fsl_desc->tcd[(i + 1)].ptcd; + fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, + src_addr, dst_addr, fsl_chan->fsc.attr, + soff, nbytes, 0, iter, iter, doff, + last_sg, false, false, true); + } else { + last_sg = 0; + fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, + src_addr, dst_addr, fsl_chan->fsc.attr, + soff, nbytes, 0, iter, iter, doff, + last_sg, true, true, false); + } + } + + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); +} + +static void fsl_edma3_xfer_desc(struct fsl_edma3_chan *fsl_chan) +{ + struct virt_dma_desc *vdesc; + + vdesc = vchan_next_desc(&fsl_chan->vchan); + if (!vdesc) + return; + fsl_chan->edesc = to_fsl_edma3_desc(vdesc); + + fsl_edma3_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); + fsl_edma3_enable_request(fsl_chan); + fsl_chan->status = DMA_IN_PROGRESS; + fsl_chan->idle = false; +} + +static struct dma_async_tx_descriptor *fsl_edma3_prep_memcpy( + struct dma_chan *chan, dma_addr_t dma_dst, + dma_addr_t dma_src, size_t len, unsigned long flags) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct fsl_edma3_desc *fsl_desc; + + fsl_desc = fsl_edma3_alloc_desc(fsl_chan, 1); + if (!fsl_desc) + return NULL; + fsl_desc->iscyclic = false; + + fsl_chan->is_sw = true; + + /* To match with copy_align and max_seg_size so 1 tcd is enough */ + fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[0].vtcd, dma_src, dma_dst, + EDMA_TCD_ATTR_SSIZE_64BYTE | EDMA_TCD_ATTR_DSIZE_64BYTE, + 64, len, 0, 1, 1, 64, 0, true, true, false); + + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); +} + +static size_t fsl_edma3_desc_residue(struct fsl_edma3_chan *fsl_chan, + struct virt_dma_desc *vdesc, bool in_progress); + +static void fsl_edma3_get_realcnt(struct fsl_edma3_chan *fsl_chan) +{ + fsl_chan->chn_real_count = fsl_edma3_desc_residue(fsl_chan, NULL, true); +} + +static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) +{ + struct fsl_edma3_chan *fsl_chan = dev_id; + unsigned int intr; + void __iomem *base_addr; + + spin_lock(&fsl_chan->vchan.lock); + + /* Ignore this interrupt since channel has been freeed with power off */ + if (!fsl_chan->edesc && !fsl_chan->tcd_pool) + goto irq_handled; + + base_addr = fsl_chan->membase; + + intr = readl(base_addr + EDMA_CH_INT); + if (!intr) + goto irq_handled; + + writel(1, base_addr + EDMA_CH_INT); + + /* Ignore this interrupt since channel has been disabled already */ + if (!fsl_chan->edesc) + goto irq_handled; + + if (!fsl_chan->edesc->iscyclic) { + fsl_edma3_get_realcnt(fsl_chan); + list_del(&fsl_chan->edesc->vdesc.node); + vchan_cookie_complete(&fsl_chan->edesc->vdesc); + fsl_chan->edesc = NULL; + fsl_chan->status = DMA_COMPLETE; + fsl_chan->idle = true; + } else { + vchan_cyclic_callback(&fsl_chan->edesc->vdesc); + } + + if (!fsl_chan->edesc) + fsl_edma3_xfer_desc(fsl_chan); +irq_handled: + spin_unlock(&fsl_chan->vchan.lock); + + return IRQ_HANDLED; +} + +static void fsl_edma3_issue_pending(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + + schedule_work(&fsl_chan->issue_worker); +} + +static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct fsl_edma3_engine *fsl_edma3 = ofdma->of_dma_data; + struct dma_chan *chan, *_chan; + struct fsl_edma3_chan *fsl_chan; + bool srcid_used = false; + + if (dma_spec->args_count != 3) + return NULL; + + mutex_lock(&fsl_edma3->fsl_edma3_mutex); + list_for_each_entry_safe(chan, _chan, &fsl_edma3->dma_dev.channels, + device_node) { + if (chan->client_count) + continue; + + fsl_chan = to_fsl_edma3_chan(chan); + srcid_used = is_srcid_in_use(fsl_edma3, dma_spec->args[0]); + if (srcid_used) { + dev_err(&fsl_chan->pdev->dev, "The srcid %d has been used. Please check srcid config!", + dma_spec->args[0]); + return NULL; + } + + if (fsl_edma3->drvdata->dmamuxs == 0 && + fsl_chan->hw_chanid == dma_spec->args[0]) { + chan = dma_get_slave_channel(chan); + chan->device->privatecnt++; + fsl_chan->priority = dma_spec->args[1]; + fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; + fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; + fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO; + mutex_unlock(&fsl_edma3->fsl_edma3_mutex); + return chan; + } else if ((fsl_edma3->drvdata->dmamuxs || fsl_edma3->bus_axi) && + !fsl_chan->srcid) { + chan = dma_get_slave_channel(chan); + chan->device->privatecnt++; + fsl_chan->priority = dma_spec->args[1]; + fsl_chan->srcid = dma_spec->args[0]; + fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; + fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; + fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO; + mutex_unlock(&fsl_edma3->fsl_edma3_mutex); + return chan; + } + } + mutex_unlock(&fsl_edma3->fsl_edma3_mutex); + return NULL; +} + +static int fsl_edma3_alloc_chan_resources(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct platform_device *pdev = fsl_chan->pdev; + int ret; + + if (fsl_chan->edma3->drvdata->has_chclk) + clk_prepare_enable(fsl_chan->clk); + + fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, + sizeof(struct fsl_edma3_hw_tcd), + 32, 0); + + if (fsl_chan->edma3->drvdata->has_pd) { + pm_runtime_get_sync(fsl_chan->dev); + /* clear meaningless pending irq anyway */ + if (readl(fsl_chan->membase + EDMA_CH_INT)) + writel(1, fsl_chan->membase + EDMA_CH_INT); + } + + ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, + fsl_edma3_tx_handler, fsl_chan->edma3->irqflag, + fsl_chan->txirq_name, fsl_chan); + if (ret) { + dev_err(&pdev->dev, "Can't register %s IRQ.\n", + fsl_chan->txirq_name); + if (fsl_chan->edma3->drvdata->has_pd) + pm_runtime_put_sync_suspend(fsl_chan->dev); + + return ret; + } + + if (fsl_chan->edma3->drvdata->has_pd) { + pm_runtime_mark_last_busy(fsl_chan->dev); + pm_runtime_put_autosuspend(fsl_chan->dev); + } + + return 0; +} + +static void fsl_edma3_free_chan_resources(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + LIST_HEAD(head); + + if (fsl_chan->edma3->drvdata->has_pd) + pm_runtime_get_sync(fsl_chan->dev); + + devm_free_irq(&fsl_chan->pdev->dev, fsl_chan->txirq, fsl_chan); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_edma3_disable_request(fsl_chan); + fsl_chan->edesc = NULL; + vchan_get_all_descriptors(&fsl_chan->vchan, &head); + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + vchan_dma_desc_free_list(&fsl_chan->vchan, &head); + dma_pool_destroy(fsl_chan->tcd_pool); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_chan->tcd_pool = NULL; + fsl_chan->srcid = 0; + /* Clear interrupt before power off */ + if (readl(fsl_chan->membase + EDMA_CH_INT)) + writel(1, fsl_chan->membase + EDMA_CH_INT); + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + if (fsl_chan->edma3->drvdata->has_pd) + pm_runtime_put_sync_suspend(fsl_chan->dev); + + if (fsl_chan->edma3->drvdata->has_chclk) + clk_disable_unprepare(fsl_chan->clk); + + fsl_chan->is_sw = false; +} + +static void fsl_edma3_synchronize(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + + if (fsl_chan->status == DMA_PAUSED) + fsl_edma3_terminate_all(chan); + + vchan_synchronize(&fsl_chan->vchan); +} + +static struct device *fsl_edma3_attach_pd(struct device *dev, + struct device_node *np, int index) +{ + const char *domn = "edma0-chan01"; + struct device *pd_chan; + struct device_link *link; + int ret; + + ret = of_property_read_string_index(np, "power-domain-names", index, + &domn); + if (ret) { + dev_err(dev, "parse power-domain-names error.(%d)\n", ret); + return NULL; + } + + pd_chan = dev_pm_domain_attach_by_name(dev, domn); + if (IS_ERR_OR_NULL(pd_chan)) + return NULL; + + link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (IS_ERR(link)) { + dev_err(dev, "Failed to add device_link to %s: %ld\n", domn, + PTR_ERR(link)); + return NULL; + } + + return pd_chan; +} + +static void fsl_edma3_issue_work(struct work_struct *work) +{ + struct fsl_edma3_chan *fsl_chan = container_of(work, + struct fsl_edma3_chan, + issue_worker); + unsigned long flags; + + if (fsl_chan->edma3->drvdata->has_pd) + pm_runtime_forbid(fsl_chan->dev); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + + if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) + fsl_edma3_xfer_desc(fsl_chan); + + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); +} + +static const struct of_device_id fsl_edma3_dt_ids[] = { + { .compatible = "fsl,imx8qm-edma", .data = &fsl_edma_imx8q}, + { .compatible = "fsl,imx8qm-adma", .data = &fsl_edma_imx8q}, + { .compatible = "fsl,imx8ulp-edma", .data = &fsl_edma_imx8ulp}, + { .compatible = "fsl,imx93-edma", .data = &fsl_edma_imx93}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, fsl_edma3_dt_ids); + +static int fsl_edma3_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *of_id = + of_match_device(fsl_edma3_dt_ids, &pdev->dev); + struct fsl_edma3_engine *fsl_edma3; + struct fsl_edma3_chan *fsl_chan; + struct resource *res_mp; + struct resource *res; + int len, chans; + int ret, i; + + if (!of_id) + return -EINVAL; + + ret = of_property_read_u32(np, "dma-channels", &chans); + if (ret) { + dev_err(&pdev->dev, "Can't get dma-channels.\n"); + return ret; + } + + len = sizeof(*fsl_edma3) + sizeof(*fsl_chan) * chans; + fsl_edma3 = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!fsl_edma3) + return -ENOMEM; + + /* Audio edma rx/tx channel shared interrupt */ + if (of_property_read_bool(np, "shared-interrupt")) + fsl_edma3->irqflag = IRQF_SHARED; + + fsl_edma3->swap = of_device_is_compatible(np, "fsl,imx8qm-adma"); + fsl_edma3->n_chans = chans; + fsl_edma3->drvdata = (const struct fsl_edma3_drvdata *)of_id->data; + + INIT_LIST_HEAD(&fsl_edma3->dma_dev.channels); + + res_mp = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (of_property_read_bool(np, "fsl,edma-axi")) + fsl_edma3->bus_axi = true; + + if (fsl_edma3->drvdata->has_chclk) { + fsl_edma3->clk_mp = devm_clk_get(&pdev->dev, "edma-mp-clk"); + if (IS_ERR(fsl_edma3->clk_mp)) { + dev_err(&pdev->dev, "Can't get mp clk.\n"); + return PTR_ERR(fsl_edma3->clk_mp); + } + clk_prepare_enable(fsl_edma3->clk_mp); + } else { + fsl_edma3->dmaclk = devm_clk_get_optional(&pdev->dev, "edma"); + if (IS_ERR(fsl_edma3->dmaclk)) { + dev_err(&pdev->dev, "Missing DMA block clock.\n"); + return PTR_ERR(fsl_edma3->dmaclk); + } + clk_prepare_enable(fsl_edma3->dmaclk); + } + for (i = 0; i < fsl_edma3->n_chans; i++) { + struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i]; + const char *txirq_name; + char chanid[3], id_len = 0; + char clk_name[18]; + char *p = chanid; + unsigned long val; + + fsl_chan->edma3 = fsl_edma3; + fsl_chan->pdev = pdev; + fsl_chan->idle = true; + fsl_chan->srcid = 0; + /* Get per channel membase */ + res = platform_get_resource(pdev, IORESOURCE_MEM, i + 1); + fsl_chan->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(fsl_chan->membase)) + return PTR_ERR(fsl_chan->membase); + + if (fsl_edma3->bus_axi) { + fsl_chan->hw_chanid = ((res->start - res_mp->start) >> 15) & 0x7f; + fsl_chan->hw_chanid = fsl_chan->hw_chanid - 2; + } else { + /* Get the hardware chanel id by the channel membase + * channel0:0x10000, channel1:0x20000... total 32 channels + * Note: skip first res_mp which we don't care. + */ + fsl_chan->hw_chanid = ((res->start - res_mp->start) >> 16) & 0x3f; + fsl_chan->hw_chanid--; + } + + ret = of_property_read_string_index(np, "interrupt-names", i, + &txirq_name); + if (ret) { + dev_err(&pdev->dev, "read interrupt-names fail.\n"); + return ret; + } + /* Get channel id length from dts, one-digit or double-digit */ + id_len = strlen(txirq_name) - strlen(CHAN_PREFIX) - + strlen(CHAN_POSFIX); + if (id_len > 2) { + dev_err(&pdev->dev, "%s is edmaX-chanX-tx in dts?\n", + res->name); + return -EINVAL; + } + /* Grab channel id from txirq_name */ + strncpy(p, txirq_name + strlen(CHAN_PREFIX), id_len); + *(p + id_len) = '\0'; + + /* check if the channel id match well with hw_chanid */ + ret = kstrtoul(chanid, 0, &val); + if (ret || val != fsl_chan->hw_chanid) { + dev_err(&pdev->dev, "%s,wrong id?\n", txirq_name); + return -EINVAL; + } + + /* request channel irq */ + fsl_chan->txirq = platform_get_irq_byname(pdev, txirq_name); + if (fsl_chan->txirq < 0) { + dev_err(&pdev->dev, "Can't get %s irq.\n", txirq_name); + return fsl_chan->txirq; + } + + memcpy(fsl_chan->txirq_name, txirq_name, strlen(txirq_name)); + + if (fsl_edma3->drvdata->has_chclk) { + strncpy(clk_name, txirq_name, strlen(CHAN_PREFIX) + id_len); + strcpy(clk_name + strlen(CHAN_PREFIX) + id_len, CLK_POSFIX); + fsl_chan->clk = devm_clk_get(&pdev->dev, + (const char *)clk_name); + + if (IS_ERR(fsl_chan->clk)) + return PTR_ERR(fsl_chan->clk); + } + + fsl_chan->vchan.desc_free = fsl_edma3_free_desc; + vchan_init(&fsl_chan->vchan, &fsl_edma3->dma_dev); + + INIT_WORK(&fsl_chan->issue_worker, + fsl_edma3_issue_work); + } + + mutex_init(&fsl_edma3->fsl_edma3_mutex); + + dma_cap_set(DMA_PRIVATE, fsl_edma3->dma_dev.cap_mask); + dma_cap_set(DMA_SLAVE, fsl_edma3->dma_dev.cap_mask); + dma_cap_set(DMA_CYCLIC, fsl_edma3->dma_dev.cap_mask); + dma_cap_set(DMA_MEMCPY, fsl_edma3->dma_dev.cap_mask); + + fsl_edma3->dma_dev.dev = &pdev->dev; + fsl_edma3->dma_dev.device_alloc_chan_resources + = fsl_edma3_alloc_chan_resources; + fsl_edma3->dma_dev.device_free_chan_resources + = fsl_edma3_free_chan_resources; + fsl_edma3->dma_dev.device_tx_status = fsl_edma3_tx_status; + fsl_edma3->dma_dev.device_prep_slave_sg = fsl_edma3_prep_slave_sg; + fsl_edma3->dma_dev.device_prep_dma_memcpy = fsl_edma3_prep_memcpy; + fsl_edma3->dma_dev.device_prep_dma_cyclic = fsl_edma3_prep_dma_cyclic; + fsl_edma3->dma_dev.device_config = fsl_edma3_slave_config; + fsl_edma3->dma_dev.device_pause = fsl_edma3_pause; + fsl_edma3->dma_dev.device_resume = fsl_edma3_resume; + fsl_edma3->dma_dev.device_terminate_all = fsl_edma3_terminate_all; + fsl_edma3->dma_dev.device_issue_pending = fsl_edma3_issue_pending; + fsl_edma3->dma_dev.device_synchronize = fsl_edma3_synchronize; + fsl_edma3->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; + + fsl_edma3->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; + fsl_edma3->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; + fsl_edma3->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | + BIT(DMA_MEM_TO_DEV) | + BIT(DMA_DEV_TO_DEV); + + fsl_edma3->dma_dev.copy_align = DMAENGINE_ALIGN_64_BYTES; + /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ + dma_set_max_seg_size(fsl_edma3->dma_dev.dev, 0x7fff); + + platform_set_drvdata(pdev, fsl_edma3); + + ret = dma_async_device_register(&fsl_edma3->dma_dev); + if (ret) { + dev_err(&pdev->dev, "Can't register Freescale eDMA engine.\n"); + return ret; + } + /* Attach power domains from dts for each dma chanel device */ + if (fsl_edma3->drvdata->has_pd) { + for (i = 0; i < fsl_edma3->n_chans; i++) { + struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i]; + struct device *dev; + + dev = fsl_edma3_attach_pd(&pdev->dev, np, i); + if (!dev) { + dev_err(dev, "edma channel attach failed.\n"); + return -EINVAL; + } + + fsl_chan->dev = dev; + /* clear meaningless pending irq anyway */ + writel(1, fsl_chan->membase + EDMA_CH_INT); + + pm_runtime_use_autosuspend(fsl_chan->dev); + pm_runtime_set_autosuspend_delay(fsl_chan->dev, 200); + pm_runtime_set_active(fsl_chan->dev); + pm_runtime_put_sync_suspend(fsl_chan->dev); + } + } + + ret = of_dma_controller_register(np, fsl_edma3_xlate, fsl_edma3); + if (ret) { + dev_err(&pdev->dev, "Can't register Freescale eDMA of_dma.\n"); + dma_async_device_unregister(&fsl_edma3->dma_dev); + return ret; + } + + return 0; +} + +static int fsl_edma3_remove(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct fsl_edma3_engine *fsl_edma3 = platform_get_drvdata(pdev); + + of_dma_controller_free(np); + dma_async_device_unregister(&fsl_edma3->dma_dev); + + if (fsl_edma3->drvdata->has_chclk) + clk_disable_unprepare(fsl_edma3->clk_mp); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int fsl_edma3_suspend_late(struct device *dev) +{ + struct fsl_edma3_engine *fsl_edma = dev_get_drvdata(dev); + struct fsl_edma3_chan *fsl_chan; + unsigned long flags; + void __iomem *addr; + int i; + + for (i = 0; i < fsl_edma->n_chans; i++) { + fsl_chan = &fsl_edma->chans[i]; + addr = fsl_chan->membase; + + if ((fsl_chan->edma3->drvdata->has_pd && + pm_runtime_status_suspended(fsl_chan->dev)) || + (!fsl_chan->edma3->drvdata->has_pd && !fsl_chan->srcid)) + continue; + + if (fsl_chan->edma3->drvdata->has_pd) + pm_runtime_get_sync(fsl_chan->dev); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_edma->edma_regs[i].csr = readl(addr + EDMA_CH_CSR); + fsl_edma->edma_regs[i].sbr = readl(addr + EDMA_CH_SBR); + /* Make sure chan is idle or will force disable. */ + if (unlikely(!fsl_chan->idle)) { + dev_warn(dev, "WARN: There is non-idle channel."); + fsl_edma3_disable_request(fsl_chan); + } + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + if (fsl_chan->edma3->drvdata->has_pd) + pm_runtime_put_sync_suspend(fsl_chan->dev); + } + + return 0; +} + +static int fsl_edma3_resume_early(struct device *dev) +{ + struct fsl_edma3_engine *fsl_edma = dev_get_drvdata(dev); + struct fsl_edma3_chan *fsl_chan; + void __iomem *addr; + unsigned long flags; + int i; + + for (i = 0; i < fsl_edma->n_chans; i++) { + fsl_chan = &fsl_edma->chans[i]; + addr = fsl_chan->membase; + + if ((fsl_chan->edma3->drvdata->has_pd && + pm_runtime_status_suspended(fsl_chan->dev)) || + (!fsl_chan->edma3->drvdata->has_pd && !fsl_chan->srcid)) + continue; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + writel(fsl_edma->edma_regs[i].csr, addr + EDMA_CH_CSR); + writel(fsl_edma->edma_regs[i].sbr, addr + EDMA_CH_SBR); + /* restore tcd if this channel not terminated before suspend */ + if (fsl_chan->edesc) + fsl_edma3_set_tcd_regs(fsl_chan, + fsl_chan->edesc->tcd[0].vtcd); + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + } + + return 0; +} +#endif + +static const struct dev_pm_ops fsl_edma3_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(fsl_edma3_suspend_late, + fsl_edma3_resume_early) +}; + +static struct platform_driver fsl_edma3_driver = { + .driver = { + .name = "fsl-edma-v3", + .of_match_table = fsl_edma3_dt_ids, + .pm = &fsl_edma3_pm_ops, + }, + .probe = fsl_edma3_probe, + .remove = fsl_edma3_remove, +}; + +static int __init fsl_edma3_init(void) +{ + return platform_driver_register(&fsl_edma3_driver); +} +fs_initcall(fsl_edma3_init); + +static void __exit fsl_edma3_exit(void) +{ + platform_driver_unregister(&fsl_edma3_driver); +} +module_exit(fsl_edma3_exit); + +MODULE_ALIAS("platform:fsl-edma3"); +MODULE_DESCRIPTION("Freescale eDMA-V3 engine driver"); +MODULE_LICENSE("GPL v2"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/fsl-qdma.c linux-imx-phytec/drivers/dma/fsl-qdma.c --- linux-6.1.55/drivers/dma/fsl-qdma.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/fsl-qdma.c 2024-06-19 12:33:59.820218558 +0200 @@ -109,6 +109,7 @@ #define FSL_QDMA_CMD_WTHROTL_OFFSET 20 #define FSL_QDMA_CMD_DSEN_OFFSET 19 #define FSL_QDMA_CMD_LWC_OFFSET 16 +#define FSL_QDMA_CMD_PF BIT(17) /* Field definition for Descriptor status */ #define QDMA_CCDF_STATUS_RTE BIT(5) @@ -316,7 +317,7 @@ vchan_dma_desc_free_list(&fsl_chan->vchan, &head); - if (!fsl_queue->comp_pool && !fsl_queue->desc_pool) + if (!fsl_queue->comp_pool || !fsl_queue->desc_pool) return; list_for_each_entry_safe(comp_temp, _comp_temp, @@ -384,7 +385,8 @@ qdma_csgf_set_f(csgf_dest, len); /* Descriptor Buffer */ cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE << - FSL_QDMA_CMD_RWTTYPE_OFFSET); + FSL_QDMA_CMD_RWTTYPE_OFFSET) | + FSL_QDMA_CMD_PF; sdf->data = QDMA_SDDF_CMD(cmd); cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE << @@ -1201,10 +1203,6 @@ if (!fsl_qdma->queue) return -ENOMEM; - ret = fsl_qdma_irq_init(pdev, fsl_qdma); - if (ret) - return ret; - fsl_qdma->irq_base = platform_get_irq_byname(pdev, "qdma-queue0"); if (fsl_qdma->irq_base < 0) return fsl_qdma->irq_base; @@ -1243,16 +1241,20 @@ platform_set_drvdata(pdev, fsl_qdma); - ret = dma_async_device_register(&fsl_qdma->dma_dev); + ret = fsl_qdma_reg_init(fsl_qdma); if (ret) { - dev_err(&pdev->dev, - "Can't register NXP Layerscape qDMA engine.\n"); + dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n"); return ret; } - ret = fsl_qdma_reg_init(fsl_qdma); + ret = fsl_qdma_irq_init(pdev, fsl_qdma); + if (ret) + return ret; + + ret = dma_async_device_register(&fsl_qdma->dma_dev); if (ret) { - dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n"); + dev_err(&pdev->dev, + "Can't register NXP Layerscape qDMA engine.\n"); return ret; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/imx-sdma.c linux-imx-phytec/drivers/dma/imx-sdma.c --- linux-6.1.55/drivers/dma/imx-sdma.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/imx-sdma.c 2024-06-19 12:33:59.824218627 +0200 @@ -24,10 +24,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -169,6 +171,8 @@ #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) #define SDMA_WATERMARK_LEVEL_SP BIT(11) #define SDMA_WATERMARK_LEVEL_DP BIT(12) +#define SDMA_WATERMARK_LEVEL_SD BIT(13) +#define SDMA_WATERMARK_LEVEL_DD BIT(14) #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) #define SDMA_WATERMARK_LEVEL_LWE BIT(28) #define SDMA_WATERMARK_LEVEL_HWE BIT(29) @@ -176,6 +180,7 @@ #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \ @@ -186,11 +191,12 @@ #define SDMA_WATERMARK_LEVEL_OFF_FIFOS GENMASK(19, 16) #define SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO GENMASK(31, 28) #define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23) +#define SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF 24 -#define SDMA_DONE0_CONFIG_DONE_SEL BIT(7) -#define SDMA_DONE0_CONFIG_DONE_DIS BIT(6) +#define SDMA_DONE0_CONFIG_DONE_SEL 0x7 +#define SDMA_DONE0_CONFIG_DONE_DIS 0x6 -/* +/** * struct sdma_script_start_addrs - SDMA script start pointers * * start addresses of the different functions in the physical @@ -244,6 +250,8 @@ s32 sai_2_mcu_addr; s32 uart_2_mcu_rom_addr; s32 uartsh_2_mcu_rom_addr; + s32 i2c_2_mcu_addr; + s32 mcu_2_i2c_addr; /* End of v3 array */ s32 mcu_2_zqspi_addr; /* End of v4 array */ @@ -430,18 +438,19 @@ * @is_ram_script: flag for script in ram * @n_fifos_src: number of source device fifos * @n_fifos_dst: number of destination device fifos - * @sw_done: software done flag * @stride_fifos_src: stride for source device FIFOs * @stride_fifos_dst: stride for destination device FIFOs * @words_per_fifo: copy number of words one time for one FIFO + * @sw_done: software done flag */ struct sdma_channel { struct virt_dma_chan vc; struct sdma_desc *desc; struct sdma_engine *sdma; unsigned int channel; - enum dma_transfer_direction direction; + enum dma_transfer_direction direction; struct dma_slave_config slave_config; + struct sdma_peripheral_config *audio_config; enum sdma_peripheral_type peripheral_type; unsigned int event_id0; unsigned int event_id1; @@ -459,12 +468,13 @@ struct work_struct terminate_worker; struct list_head terminated; bool is_ram_script; - unsigned int n_fifos_src; - unsigned int n_fifos_dst; - unsigned int stride_fifos_src; - unsigned int stride_fifos_dst; - unsigned int words_per_fifo; - bool sw_done; + int prio; + unsigned int n_fifos_src; + unsigned int n_fifos_dst; + unsigned int stride_fifos_src; + unsigned int stride_fifos_dst; + unsigned int words_per_fifo; + bool sw_done; }; #define IMX_DMA_SG_LOOP BIT(0) @@ -474,6 +484,15 @@ #define MXC_SDMA_MIN_PRIORITY 1 #define MXC_SDMA_MAX_PRIORITY 7 +/* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are reserved and + * can't be accessed. Skip these register touch in suspend/resume. Also below + * two macros are only used on i.mx6sx. + */ +#define MXC_SDMA_RESERVED_REG (SDMA_CHNPRI_0 - SDMA_XTRIG_CONF2 - 4) +#define MXC_SDMA_SAVED_REG_NUM (((SDMA_CHNENBL0_IMX35 + 4 * 48) - \ + MXC_SDMA_RESERVED_REG) / 4) + #define SDMA_FIRMWARE_MAGIC 0x414d4453 /** @@ -512,15 +531,22 @@ * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf */ bool ecspi_fixed; + bool has_done0; + bool pm_runtime; }; struct sdma_engine { struct device *dev; struct sdma_channel channel[MAX_DMA_CHANNELS]; struct sdma_channel_control *channel_control; + u32 save_regs[MXC_SDMA_SAVED_REG_NUM]; + u32 save_done0_regs[2]; + const char *fw_name; void __iomem *regs; struct sdma_context_data *context; dma_addr_t context_phys; + dma_addr_t ccb_phys; + bool is_on; struct dma_device dma_device; struct clk *clk_ipg; struct clk *clk_ahb; @@ -536,6 +562,10 @@ /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/ bool clk_ratio; bool fw_loaded; + struct gen_pool *iram_pool; + u32 fw_fail; + u8 *fw_data; + unsigned short ram_code_start; }; static int sdma_config_write(struct dma_chan *chan, @@ -632,6 +662,12 @@ .script_addrs = &sdma_script_imx6q, }; +static struct sdma_driver_data sdma_imx6sx = { + .chnenbl0 = SDMA_CHNENBL0_IMX35, + .num_events = 48, + .script_addrs = &sdma_script_imx6q, +}; + static struct sdma_driver_data sdma_imx6ul = { .chnenbl0 = SDMA_CHNENBL0_IMX35, .num_events = 48, @@ -664,6 +700,16 @@ .check_ratio = 1, }; +static struct sdma_driver_data sdma_imx8mp = { + .chnenbl0 = SDMA_CHNENBL0_IMX35, + .num_events = 48, + .script_addrs = &sdma_script_imx7d, + .check_ratio = 1, + .ecspi_fixed = true, + .has_done0 = true, + .pm_runtime = true, +}; + static const struct of_device_id sdma_dt_ids[] = { { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, @@ -672,8 +718,10 @@ { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, }, + { .compatible = "fsl,imx6sx-sdma", .data = &sdma_imx6sx, }, { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, }, { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, }, + { .compatible = "fsl,imx8mp-sdma", .data = &sdma_imx8mp, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sdma_dt_ids); @@ -683,6 +731,30 @@ #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ +static void sdma_pm_clk_enable(struct sdma_engine *sdma, bool direct, bool enable) +{ + if (enable) { + if (sdma->drvdata->pm_runtime) + pm_runtime_get_sync(sdma->dev); + else { + clk_enable(sdma->clk_ipg); + clk_enable(sdma->clk_ahb); + } + } else { + if (sdma->drvdata->pm_runtime) { + if (direct) { + pm_runtime_put_sync_suspend(sdma->dev); + } else { + pm_runtime_mark_last_busy(sdma->dev); + pm_runtime_put_autosuspend(sdma->dev); + } + } else { + clk_disable(sdma->clk_ipg); + clk_disable(sdma->clk_ahb); + } + } +} + static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) { u32 chnenbl0 = sdma->drvdata->chnenbl0; @@ -744,9 +816,11 @@ u32 reg; sdma_enable_channel(sdma, 0); - + /* enlarge timeout to 5ms for safe since many highest channel + * also may run at the same time like asrc/easrc tough test. + */ ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, - reg, !(reg & 1), 1, 500); + reg, !(reg & 1), 1, 5000); if (ret) dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); @@ -760,16 +834,68 @@ return ret; } -static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, - u32 address) + +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 47 +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 48 + +static void sdma_add_scripts(struct sdma_engine *sdma, + const struct sdma_script_start_addrs *addr) +{ + s32 *addr_arr = (u32 *)addr; + s32 *saddr_arr = (u32 *)sdma->script_addrs; + int i; + + /* use the default firmware in ROM if missing external firmware */ + if (!sdma->script_number) + sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; + + if (sdma->script_number > sizeof(struct sdma_script_start_addrs) + / sizeof(s32)) { + dev_err(sdma->dev, + "SDMA script number %d not match with firmware.\n", + sdma->script_number); + return; + } + + for (i = 0; i < sdma->script_number; i++) + if (addr_arr[i] > 0) + saddr_arr[i] = addr_arr[i]; + + /* + * For compatibility with NXP internal legacy kernel before 4.19 which + * is based on uart ram script and mainline kernel based on uart rom + * script, both uart ram/rom scripts are present in newer sdma + * firmware. Use the rom versions if they are present (V3 or newer). + */ + if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) { + if (addr->uart_2_mcu_rom_addr) + sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr; + if (addr->uartsh_2_mcu_rom_addr) + sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr; + } +} + +static int sdma_load_script(struct sdma_engine *sdma) { struct sdma_buffer_descriptor *bd0 = sdma->bd0; + const struct sdma_script_start_addrs *addr; + struct sdma_firmware_header *header; + unsigned short *ram_code; void *buf_virt; dma_addr_t buf_phys; int ret; unsigned long flags; - buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); + header = (struct sdma_firmware_header *)sdma->fw_data; + + addr = (void *)header + header->script_addrs_start; + ram_code = (void *)header + header->ram_code_start; + sdma->ram_code_start = header->ram_code_start; + + buf_virt = dma_alloc_coherent(sdma->dev, header->ram_code_size, + &buf_phys, GFP_KERNEL); if (!buf_virt) return -ENOMEM; @@ -777,18 +903,25 @@ bd0->mode.command = C0_SETPM; bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; - bd0->mode.count = size / 2; + bd0->mode.count = header->ram_code_size / 2; bd0->buffer_addr = buf_phys; - bd0->ext_buffer_addr = address; + bd0->ext_buffer_addr = addr->ram_code_start_addr; - memcpy(buf_virt, buf, size); + memcpy(buf_virt, ram_code, header->ram_code_size); ret = sdma_run_channel0(sdma); spin_unlock_irqrestore(&sdma->channel_0_lock, flags); - dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); + dma_free_coherent(sdma->dev, header->ram_code_size, buf_virt, buf_phys); + + sdma_add_scripts(sdma, addr); + sdma->fw_loaded = true; + + dev_info_once(sdma->dev, "loaded firmware %d.%d\n", + header->version_major, + header->version_minor); return ret; } @@ -804,12 +937,37 @@ writel_relaxed(val, sdma->regs + chnenbl); /* Set SDMA_DONEx_CONFIG is sw_done enabled */ - if (sdmac->sw_done) { - val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG); - val |= SDMA_DONE0_CONFIG_DONE_SEL; - val &= ~SDMA_DONE0_CONFIG_DONE_DIS; - writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG); + if (sdmac->audio_config && (sdmac->audio_config->sw_done_sel & BIT(31) || + sdmac->sw_done)) { + u32 sw_done_sel = sdmac->audio_config->sw_done_sel & 0xff; + u32 offset = SDMA_DONE0_CONFIG + sw_done_sel / 4; + u32 done_sel = SDMA_DONE0_CONFIG_DONE_SEL + + ((sw_done_sel % 4) << 3); + u32 sw_done_dis = SDMA_DONE0_CONFIG_DONE_DIS + + ((sw_done_sel % 4) << 3); + + val = readl_relaxed(sdma->regs + offset); + __set_bit(done_sel, &val); + __clear_bit(sw_done_dis, &val); + writel_relaxed(val, sdma->regs + offset); } + +} + +static int sdma_set_channel_priority(struct sdma_channel *sdmac, + unsigned int priority) +{ + struct sdma_engine *sdma = sdmac->sdma; + int channel = sdmac->channel; + + if (priority < MXC_SDMA_MIN_PRIORITY + || priority > MXC_SDMA_MAX_PRIORITY) { + return -EINVAL; + } + + writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); + + return 0; } static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) @@ -876,9 +1034,16 @@ /* * We use bd->mode.count to calculate the residue, since contains * the number of bytes present in the current buffer descriptor. + * Note: in IMX_DMATYPE_MULTI_SAI case, bd->mode.count used as + * remaining bytes instead so that one register could be saved. + * so chn_real_count = desc->period_len - bd->mode.count. */ + if (sdmac->peripheral_type == IMX_DMATYPE_MULTI_SAI) + desc->chn_real_count = desc->period_len - bd->mode.count; + else + desc->chn_real_count = bd->mode.count; - desc->chn_real_count = bd->mode.count; + bd->mode.status |= BD_DONE; bd->mode.count = desc->period_len; desc->buf_ptail = desc->buf_tail; desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; @@ -940,6 +1105,7 @@ struct sdma_engine *sdma = dev_id; unsigned long stat; + sdma_pm_clk_enable(sdma, false, true); stat = readl_relaxed(sdma->regs + SDMA_H_INTR); writel_relaxed(stat, sdma->regs + SDMA_H_INTR); /* channel 0 is special and not handled here, see run_channel0() */ @@ -954,7 +1120,10 @@ desc = sdmac->desc; if (desc) { if (sdmac->flags & IMX_DMA_SG_LOOP) { - sdma_update_channel_loop(sdmac); + if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) + sdma_update_channel_loop(sdmac); + else + vchan_cyclic_callback(&desc->vd); } else { mxc_sdma_handle_channel_normal(sdmac); vchan_cookie_complete(&desc->vd); @@ -966,6 +1135,8 @@ __clear_bit(channel, &stat); } + sdma_pm_clk_enable(sdma, false, false); + return IRQ_HANDLED; } @@ -1073,6 +1244,16 @@ case IMX_DMATYPE_MULTI_SAI: per_2_emi = sdma->script_addrs->sai_2_mcu_addr; emi_2_per = sdma->script_addrs->mcu_2_sai_addr; + sdmac->is_ram_script = true; + break; + case IMX_DMATYPE_I2C: + per_2_emi = sdma->script_addrs->i2c_2_mcu_addr; + emi_2_per = sdma->script_addrs->mcu_2_i2c_addr; + sdmac->is_ram_script = true; + break; + case IMX_DMATYPE_HDMI: + emi_2_per = sdma->script_addrs->hdmi_dma_addr; + sdmac->is_ram_script = true; break; default: dev_err(sdma->dev, "Unsupported transfer type %d\n", @@ -1085,6 +1266,13 @@ sdmac->device_to_device = per_2_per; sdmac->pc_to_pc = emi_2_emi; + if (sdma->ram_code_start && + ((sdmac->pc_from_device >= sdma->ram_code_start) || + (sdmac->pc_to_device >= sdma->ram_code_start) || + (sdmac->device_to_device >= sdma->ram_code_start || + (sdmac->pc_to_pc >= sdma->ram_code_start)))) + sdmac->is_ram_script = true; + return 0; } @@ -1125,11 +1313,16 @@ /* Send by context the event mask,base address for peripheral * and watermark level */ - context->gReg[0] = sdmac->event_mask[1]; - context->gReg[1] = sdmac->event_mask[0]; - context->gReg[2] = sdmac->per_addr; - context->gReg[6] = sdmac->shp_addr; - context->gReg[7] = sdmac->watermark_level; + if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { + context->gReg[4] = sdmac->per_addr; + context->gReg[6] = sdmac->shp_addr; + } else { + context->gReg[0] = sdmac->event_mask[1]; + context->gReg[1] = sdmac->event_mask[0]; + context->gReg[2] = sdmac->per_addr; + context->gReg[6] = sdmac->shp_addr; + context->gReg[7] = sdmac->watermark_level; + } bd0->mode.command = C0_SETDM; bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; @@ -1143,6 +1336,31 @@ return ret; } +static int sdma_save_restore_context(struct sdma_engine *sdma, bool save) +{ + struct sdma_context_data *context = sdma->context; + struct sdma_buffer_descriptor *bd0 = sdma->bd0; + unsigned long flags; + int ret; + + spin_lock_irqsave(&sdma->channel_0_lock, flags); + + if (save) + bd0->mode.command = C0_GETDM; + else + bd0->mode.command = C0_SETDM; + + bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; + bd0->mode.count = MAX_DMA_CHANNELS * sizeof(*context) / 4; + bd0->buffer_addr = sdma->context_phys; + bd0->ext_buffer_addr = 2048; + ret = sdma_run_channel0(sdma); + + spin_unlock_irqrestore(&sdma->channel_0_lock, flags); + + return ret; +} + static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) { return container_of(chan, struct sdma_channel, vc.chan); @@ -1179,6 +1397,7 @@ struct sdma_channel *sdmac = to_sdma_chan(chan); unsigned long flags; + sdma_pm_clk_enable(sdmac->sdma, false, true); spin_lock_irqsave(&sdmac->vc.lock, flags); sdma_disable_channel(chan); @@ -1198,6 +1417,8 @@ spin_unlock_irqrestore(&sdmac->vc.lock, flags); + sdma_pm_clk_enable(sdmac->sdma, false, false); + return 0; } @@ -1248,6 +1469,11 @@ sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; + + if (sdmac->n_fifos_src > 1) + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SD; + if (sdmac->n_fifos_dst > 1) + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DD; } static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac) @@ -1256,8 +1482,11 @@ unsigned int stride_fifos; unsigned int words_per_fifo; - if (sdmac->sw_done) - sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE; + if (sdmac->audio_config && (sdmac->audio_config->sw_done_sel & BIT(31) || + sdmac->sw_done)) + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE | + (sdmac->audio_config->sw_done_sel & 0xff) << + SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF; if (sdmac->direction == DMA_DEV_TO_MEM) { n_fifos = sdmac->n_fifos_src; @@ -1271,8 +1500,10 @@ sdmac->watermark_level |= FIELD_PREP(SDMA_WATERMARK_LEVEL_N_FIFOS, n_fifos); + sdmac->watermark_level |= FIELD_PREP(SDMA_WATERMARK_LEVEL_OFF_FIFOS, stride_fifos); + if (words_per_fifo) sdmac->watermark_level |= FIELD_PREP(SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO, (words_per_fifo - 1)); @@ -1305,6 +1536,11 @@ ret = sdma_get_pc(sdmac, sdmac->peripheral_type); if (ret) return ret; + sdma_set_channel_priority(sdmac, sdmac->prio); + + sdma_event_enable(sdmac, sdmac->event_id0); + if (sdmac->event_id1) + sdma_event_enable(sdmac, sdmac->event_id1); if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { @@ -1314,8 +1550,7 @@ sdmac->peripheral_type == IMX_DMATYPE_ASRC) sdma_set_watermarklevel_for_p2p(sdmac); } else { - if (sdmac->peripheral_type == - IMX_DMATYPE_MULTI_SAI) + if (sdmac->peripheral_type == IMX_DMATYPE_MULTI_SAI) sdma_set_watermarklevel_for_sais(sdmac); __set_bit(sdmac->event_id0, sdmac->event_mask); @@ -1331,28 +1566,18 @@ return 0; } -static int sdma_set_channel_priority(struct sdma_channel *sdmac, - unsigned int priority) -{ - struct sdma_engine *sdma = sdmac->sdma; - int channel = sdmac->channel; - - if (priority < MXC_SDMA_MIN_PRIORITY - || priority > MXC_SDMA_MAX_PRIORITY) { - return -EINVAL; - } - - writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); - - return 0; -} - static int sdma_request_channel0(struct sdma_engine *sdma) { int ret = -EBUSY; - sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, - GFP_NOWAIT); + if (sdma->iram_pool) + sdma->bd0 = gen_pool_dma_alloc(sdma->iram_pool, + sizeof(struct sdma_buffer_descriptor), + &sdma->bd0_phys); + else + sdma->bd0 = dma_alloc_coherent(sdma->dev, + sizeof(struct sdma_buffer_descriptor), + &sdma->bd0_phys, GFP_NOWAIT); if (!sdma->bd0) { ret = -ENOMEM; goto out; @@ -1372,10 +1597,15 @@ static int sdma_alloc_bd(struct sdma_desc *desc) { u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); + struct sdma_engine *sdma = desc->sdmac->sdma; int ret = 0; - desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, - &desc->bd_phys, GFP_NOWAIT); + if (sdma->iram_pool) + desc->bd = gen_pool_dma_alloc(sdma->iram_pool, bd_size, + &desc->bd_phys); + else + desc->bd = dma_alloc_coherent(sdma->dev, bd_size, + &desc->bd_phys, GFP_NOWAIT); if (!desc->bd) { ret = -ENOMEM; goto out; @@ -1387,9 +1617,14 @@ static void sdma_free_bd(struct sdma_desc *desc) { u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); + struct sdma_engine *sdma = desc->sdmac->sdma; - dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, - desc->bd_phys); + if (sdma->iram_pool) + gen_pool_free(sdma->iram_pool, (unsigned long)desc->bd, + bd_size); + else + dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, + desc->bd_phys); } static void sdma_desc_free(struct virt_dma_desc *vd) @@ -1400,6 +1635,116 @@ kfree(desc); } +static int sdma_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + + if (!sdma->is_on) + return 0; + + sdma->fw_loaded = false; + sdma->is_on = false; + + clk_disable(sdma->clk_ipg); + clk_disable(sdma->clk_ahb); + + /* free channel0 bd */ + if (sdma->iram_pool) + gen_pool_free(sdma->iram_pool, (unsigned long)sdma->bd0, + sizeof(struct sdma_buffer_descriptor)); + else + dma_free_coherent(sdma->dev, + sizeof(struct sdma_buffer_descriptor), + sdma->bd0, sdma->bd0_phys); + + return 0; +} + +static int sdma_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + int i, ret = 0; + + ret = clk_enable(sdma->clk_ipg); + if (ret) + return ret; + ret = clk_enable(sdma->clk_ahb); + if (ret) + goto disable_clk_ipg; + + /* Do nothing at HW level if audiomix which shared with audio driver + * not off indeed. + */ + if (readl_relaxed(sdma->regs + SDMA_H_C0PTR)) { + if (sdma->iram_pool) + sdma->bd0 = gen_pool_dma_alloc(sdma->iram_pool, + sizeof(struct sdma_buffer_descriptor), + &sdma->bd0_phys); + else + sdma->bd0 = dma_alloc_coherent(sdma->dev, + sizeof(struct sdma_buffer_descriptor), + &sdma->bd0_phys, GFP_NOWAIT); + if (!sdma->bd0) + ret = -ENOMEM; + + sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; + sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; + + sdma->is_on = true; + sdma->fw_loaded = true; + + return ret; + } + + /* Be sure SDMA has not started yet */ + writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); + + /* disable all channels */ + for (i = 0; i < sdma->drvdata->num_events; i++) + writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); + + /* All channels have priority 0 */ + for (i = 0; i < MAX_DMA_CHANNELS; i++) + writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); + + ret = sdma_request_channel0(sdma); + if (ret) + return ret; + + sdma_config_ownership(&sdma->channel[0], false, true, false); + + /* Set Command Channel (Channel Zero) */ + writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); + + /* Set bits of CONFIG register but with static context switching */ + if (sdma->clk_ratio) + writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); + else + writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); + + writel_relaxed(sdma->ccb_phys, sdma->regs + SDMA_H_C0PTR); + + /* Initializes channel's priorities */ + sdma_set_channel_priority(&sdma->channel[0], 7); + + if (!sdma->fw_data) + dev_dbg(sdma->dev, "firmware not ready.\n"); + else if (sdma_load_script(sdma)) + dev_warn(sdma->dev, "failed to load script.\n"); + + sdma->is_on = true; + + return 0; + +disable_clk_ipg: + clk_disable(sdma->clk_ipg); + dev_err(sdma->dev, "initialisation failed with %d\n", ret); + + return ret; +} + static int sdma_alloc_chan_resources(struct dma_chan *chan) { struct sdma_channel *sdmac = to_sdma_chan(chan); @@ -1445,32 +1790,30 @@ sdmac->peripheral_type = data->peripheral_type; sdmac->event_id0 = data->dma_request; sdmac->event_id1 = data->dma_request2; - - ret = clk_enable(sdmac->sdma->clk_ipg); - if (ret) - return ret; - ret = clk_enable(sdmac->sdma->clk_ahb); - if (ret) - goto disable_clk_ipg; - - ret = sdma_set_channel_priority(sdmac, prio); - if (ret) - goto disable_clk_ahb; + sdmac->prio = prio; return 0; - -disable_clk_ahb: - clk_disable(sdmac->sdma->clk_ahb); -disable_clk_ipg: - clk_disable(sdmac->sdma->clk_ipg); - return ret; } static void sdma_free_chan_resources(struct dma_chan *chan) { struct sdma_channel *sdmac = to_sdma_chan(chan); - struct sdma_engine *sdma = sdmac->sdma; + /* + * Per fw_data is null which means firmware not loaded and sdma + * not initialized, directly return. This happens in below case: + * + * -- driver request dma chan in probe phase, after that driver + * fall into -EPROBE_DEFER and free channel again without + * anything else about dma, so just return directly, otherwise + * kernel could hang since dma hardware not ready if drvdata-> + * pm_runtime is false. + * + */ + if (unlikely(!sdmac->sdma->fw_data)) + return; + + sdma_pm_clk_enable(sdmac->sdma, false, true); sdma_terminate_all(chan); sdma_channel_synchronize(chan); @@ -1484,8 +1827,9 @@ sdma_set_channel_priority(sdmac, 0); - clk_disable(sdma->clk_ipg); - clk_disable(sdma->clk_ahb); + kfree(sdmac->audio_config); + sdmac->audio_config = NULL; + sdma_pm_clk_enable(sdmac->sdma, false, false); } static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, @@ -1493,11 +1837,6 @@ { struct sdma_desc *desc; - if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) { - dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n"); - goto err_out; - } - desc = kzalloc((sizeof(*desc)), GFP_NOWAIT); if (!desc) goto err_out; @@ -1513,12 +1852,14 @@ desc->sdmac = sdmac; desc->num_bd = bds; - if (sdma_alloc_bd(desc)) + if (bds && sdma_alloc_bd(desc)) goto err_desc_out; /* No slave_config called in MEMCPY case, so do here */ - if (direction == DMA_MEM_TO_MEM) + if (direction == DMA_MEM_TO_MEM) { sdma_config_ownership(sdmac, false, true, false); + sdma_set_channel_priority(sdmac, sdmac->prio); + } if (sdma_load_context(sdmac)) goto err_bd_out; @@ -1551,10 +1892,13 @@ dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", &dma_src, &dma_dst, len, channel); + sdma_pm_clk_enable(sdmac->sdma, false, true); desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM, len / SDMA_BD_MAX_CNT + 1); - if (!desc) + if (!desc) { + sdma_pm_clk_enable(sdmac->sdma, true, false); return NULL; + } do { count = min_t(size_t, len, SDMA_BD_MAX_CNT); @@ -1586,6 +1930,8 @@ bd->mode.status = param; } while (len); + sdma_pm_clk_enable(sdmac->sdma, false, false); + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); } @@ -1600,8 +1946,12 @@ int channel = sdmac->channel; struct scatterlist *sg; struct sdma_desc *desc; + int ret; - sdma_config_write(chan, &sdmac->slave_config, direction); + sdma_pm_clk_enable(sdmac->sdma, false, true); + ret = sdma_config_write(chan, &sdmac->slave_config, direction); + if (ret) + goto err_out; desc = sdma_transfer_init(sdmac, direction, sg_len); if (!desc) @@ -1636,6 +1986,9 @@ if (count & 3 || sg->dma_address & 3) goto err_bd_out; break; + case DMA_SLAVE_BUSWIDTH_3_BYTES: + bd->mode.command = 3; + break; case DMA_SLAVE_BUSWIDTH_2_BYTES: bd->mode.command = 2; if (count & 1 || sg->dma_address & 1) @@ -1664,12 +2017,16 @@ bd->mode.status = param; } + sdma_pm_clk_enable(sdmac->sdma, false, false); + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); err_bd_out: sdma_free_bd(desc); kfree(desc); err_out: sdmac->status = DMA_ERROR; + sdma_pm_clk_enable(sdmac->sdma, true, false); + return NULL; } @@ -1680,14 +2037,22 @@ { struct sdma_channel *sdmac = to_sdma_chan(chan); struct sdma_engine *sdma = sdmac->sdma; - int num_periods = buf_len / period_len; + int num_periods = 0; int channel = sdmac->channel; int i = 0, buf = 0; struct sdma_desc *desc; + int ret; dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); - sdma_config_write(chan, &sdmac->slave_config, direction); + sdma_pm_clk_enable(sdmac->sdma, false, true); + + if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) + num_periods = buf_len / period_len; + + ret = sdma_config_write(chan, &sdmac->slave_config, direction); + if (ret) + goto err_out; desc = sdma_transfer_init(sdmac, direction, num_periods); if (!desc) @@ -1703,6 +2068,9 @@ goto err_bd_out; } + if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); + while (buf < buf_len) { struct sdma_buffer_descriptor *bd = &desc->bd[i]; int param; @@ -1735,12 +2103,16 @@ i++; } + sdma_pm_clk_enable(sdmac->sdma, false, false); + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); err_bd_out: sdma_free_bd(desc); kfree(desc); err_out: sdmac->status = DMA_ERROR; + sdma_pm_clk_enable(sdmac->sdma, true, false); + return NULL; } @@ -1750,6 +2122,14 @@ { struct sdma_channel *sdmac = to_sdma_chan(chan); + sdmac->watermark_level = 0; + sdma_get_pc(sdmac, sdmac->peripheral_type); + + if (!sdmac->sdma->is_on || (!sdmac->sdma->fw_loaded && sdmac->is_ram_script)) { + dev_warn_once(sdmac->sdma->dev, "sdma or sdma firmware not ready!\n"); + return -EPERM; + } + if (direction == DMA_DEV_TO_MEM) { sdmac->per_address = dmaengine_cfg->src_addr; sdmac->watermark_level = dmaengine_cfg->src_maxburst * @@ -1763,6 +2143,10 @@ sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & SDMA_WATERMARK_LEVEL_HWML; sdmac->word_size = dmaengine_cfg->dst_addr_width; + } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { + sdmac->per_address = dmaengine_cfg->dst_addr; + sdmac->per_address2 = dmaengine_cfg->src_addr; + sdmac->watermark_level = 0; } else { sdmac->per_address = dmaengine_cfg->dst_addr; sdmac->watermark_level = dmaengine_cfg->dst_maxburst * @@ -1778,6 +2162,7 @@ { struct sdma_channel *sdmac = to_sdma_chan(chan); struct sdma_engine *sdma = sdmac->sdma; + void *tmp; memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); @@ -1789,6 +2174,14 @@ sizeof(struct sdma_peripheral_config)); return -EINVAL; } + + tmp = krealloc(sdmac->audio_config, dmaengine_cfg->peripheral_size, GFP_NOWAIT); + if (!tmp) + return -ENOMEM; + + sdmac->audio_config = (struct sdma_peripheral_config *)tmp; + memcpy(tmp, sdmacfg, dmaengine_cfg->peripheral_size); + sdmac->n_fifos_src = sdmacfg->n_fifos_src; sdmac->n_fifos_dst = sdmacfg->n_fifos_dst; sdmac->stride_fifos_src = sdmacfg->stride_fifos_src; @@ -1800,13 +2193,11 @@ /* Set ENBLn earlier to make sure dma request triggered after that */ if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) return -EINVAL; - sdma_event_enable(sdmac, sdmac->event_id0); - if (sdmac->event_id1) { - if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) - return -EINVAL; - sdma_event_enable(sdmac, sdmac->event_id1); - } + + if (sdmac->event_id1 && + sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) + return -EINVAL; return 0; } @@ -1857,68 +2248,38 @@ struct sdma_channel *sdmac = to_sdma_chan(chan); unsigned long flags; + sdma_pm_clk_enable(sdmac->sdma, false, true); spin_lock_irqsave(&sdmac->vc.lock, flags); if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) sdma_start_desc(sdmac); spin_unlock_irqrestore(&sdmac->vc.lock, flags); -} - -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 45 -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 46 - -static void sdma_add_scripts(struct sdma_engine *sdma, - const struct sdma_script_start_addrs *addr) -{ - s32 *addr_arr = (u32 *)addr; - s32 *saddr_arr = (u32 *)sdma->script_addrs; - int i; - - /* use the default firmware in ROM if missing external firmware */ - if (!sdma->script_number) - sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; - - if (sdma->script_number > sizeof(struct sdma_script_start_addrs) - / sizeof(s32)) { - dev_err(sdma->dev, - "SDMA script number %d not match with firmware.\n", - sdma->script_number); - return; - } - - for (i = 0; i < sdma->script_number; i++) - if (addr_arr[i] > 0) - saddr_arr[i] = addr_arr[i]; - /* - * For compatibility with NXP internal legacy kernel before 4.19 which - * is based on uart ram script and mainline kernel based on uart rom - * script, both uart ram/rom scripts are present in newer sdma - * firmware. Use the rom versions if they are present (V3 or newer). - */ - if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) { - if (addr->uart_2_mcu_rom_addr) - sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr; - if (addr->uartsh_2_mcu_rom_addr) - sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr; - } + sdma_pm_clk_enable(sdmac->sdma, false, false); } static void sdma_load_firmware(const struct firmware *fw, void *context) { struct sdma_engine *sdma = context; const struct sdma_firmware_header *header; - const struct sdma_script_start_addrs *addr; - unsigned short *ram_code; if (!fw) { - dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); - /* In this case we just use the ROM firmware. */ + /* Load firmware once more time if timeout */ + if (sdma->fw_fail) + dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); + else { + /*add a bit delay to wait for firmware priv released */ + msleep(20); + request_firmware_nowait(THIS_MODULE, + FW_ACTION_UEVENT, sdma->fw_name, + sdma->dev, GFP_KERNEL, sdma, + sdma_load_firmware); + sdma->fw_fail++; + } + return; } - if (fw->size < sizeof(*header)) + if (fw->size < sizeof(*header) || sdma->fw_loaded) goto err_firmware; header = (struct sdma_firmware_header *)fw->data; @@ -1945,25 +2306,18 @@ goto err_firmware; } - addr = (void *)header + header->script_addrs_start; - ram_code = (void *)header + header->ram_code_start; - - clk_enable(sdma->clk_ipg); - clk_enable(sdma->clk_ahb); - /* download the RAM image for SDMA */ - sdma_load_script(sdma, ram_code, - header->ram_code_size, - addr->ram_code_start_addr); - clk_disable(sdma->clk_ipg); - clk_disable(sdma->clk_ahb); + dev_info(sdma->dev, "firmware found.\n"); - sdma_add_scripts(sdma, addr); + if (!sdma->fw_data) { + sdma->fw_data = kmalloc(fw->size, GFP_KERNEL); + if (!sdma->fw_data) + goto err_firmware; - sdma->fw_loaded = true; + memcpy(sdma->fw_data, fw->data, fw->size); - dev_info(sdma->dev, "loaded firmware %d.%d\n", - header->version_major, - header->version_minor); + if (!sdma->drvdata->pm_runtime) + sdma_runtime_resume(sdma->dev); + } err_firmware: release_firmware(fw); @@ -2047,79 +2401,34 @@ return ret; } -static int sdma_init(struct sdma_engine *sdma) +static int sdma_init_sw(struct sdma_engine *sdma) { - int i, ret; - dma_addr_t ccb_phys; - - ret = clk_enable(sdma->clk_ipg); - if (ret) - return ret; - ret = clk_enable(sdma->clk_ahb); - if (ret) - goto disable_clk_ipg; + int ret, ccbsize; if (sdma->drvdata->check_ratio && (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) sdma->clk_ratio = 1; - /* Be sure SDMA has not started yet */ - writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); - - sdma->channel_control = dma_alloc_coherent(sdma->dev, - MAX_DMA_CHANNELS * sizeof(struct sdma_channel_control) + - sizeof(struct sdma_context_data), - &ccb_phys, GFP_KERNEL); + ccbsize = MAX_DMA_CHANNELS * (sizeof(struct sdma_channel_control) + + sizeof(struct sdma_context_data)); + if (sdma->iram_pool) + sdma->channel_control = gen_pool_dma_alloc(sdma->iram_pool, + ccbsize, &sdma->ccb_phys); + else + sdma->channel_control = dma_alloc_coherent(sdma->dev, ccbsize, + &sdma->ccb_phys, GFP_KERNEL); if (!sdma->channel_control) { ret = -ENOMEM; - goto err_dma_alloc; + return ret; } sdma->context = (void *)sdma->channel_control + MAX_DMA_CHANNELS * sizeof(struct sdma_channel_control); - sdma->context_phys = ccb_phys + + sdma->context_phys = sdma->ccb_phys + MAX_DMA_CHANNELS * sizeof(struct sdma_channel_control); - /* disable all channels */ - for (i = 0; i < sdma->drvdata->num_events; i++) - writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); - - /* All channels have priority 0 */ - for (i = 0; i < MAX_DMA_CHANNELS; i++) - writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); - - ret = sdma_request_channel0(sdma); - if (ret) - goto err_dma_alloc; - - sdma_config_ownership(&sdma->channel[0], false, true, false); - - /* Set Command Channel (Channel Zero) */ - writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); - - /* Set bits of CONFIG register but with static context switching */ - if (sdma->clk_ratio) - writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); - else - writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); - - writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); - - /* Initializes channel's priorities */ - sdma_set_channel_priority(&sdma->channel[0], 7); - - clk_disable(sdma->clk_ipg); - clk_disable(sdma->clk_ahb); - return 0; - -err_dma_alloc: - clk_disable(sdma->clk_ahb); -disable_clk_ipg: - clk_disable(sdma->clk_ipg); - dev_err(sdma->dev, "initialisation failed with %d\n", ret); - return ret; } static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) @@ -2146,9 +2455,11 @@ if (dma_spec->args_count != 3) return NULL; + memset(&data, 0, sizeof(data)); + data.dma_request = dma_spec->args[0]; data.peripheral_type = dma_spec->args[1]; - data.priority = dma_spec->args[2]; + data.priority = dma_spec->args[2] & 0xff; /* * init dma_request2 to zero, which is not used by the dts. * For P2P, dma_request2 is init from dma_request_channel(), @@ -2256,7 +2567,13 @@ vchan_init(&sdmac->vc, &sdma->dma_device); } - ret = sdma_init(sdma); + if (np) { + sdma->iram_pool = of_gen_pool_get(np, "iram", 0); + if (sdma->iram_pool) + dev_info(&pdev->dev, "alloc bd from iram.\n"); + } + + ret = sdma_init_sw(sdma); if (ret) goto err_init; @@ -2317,12 +2634,25 @@ */ ret = of_property_read_string(np, "fsl,sdma-ram-script-name", &fw_name); - if (ret) { + if (ret) dev_warn(&pdev->dev, "failed to get firmware name\n"); - } else { - ret = sdma_get_firmware(sdma, fw_name); - if (ret) - dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); + else + sdma->fw_name = fw_name; + + ret = sdma_get_firmware(sdma, sdma->fw_name); + if (ret) + dev_warn(sdma->dev, "failed to get firmware.\n"); + + /* enable autosuspend for pm_runtime */ + if (sdma->drvdata->pm_runtime) { + /* For the largest period size 64KB, the dma transfer time + * is about 8 sec. + */ + pm_runtime_set_autosuspend_delay(&pdev->dev, 8000); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + pm_runtime_enable(&pdev->dev); } return 0; @@ -2346,6 +2676,7 @@ devm_free_irq(&pdev->dev, sdma->irq, sdma); dma_async_device_unregister(&sdma->dma_device); kfree(sdma->script_addrs); + kfree(sdma->fw_data); clk_unprepare(sdma->clk_ahb); clk_unprepare(sdma->clk_ipg); /* Kill the tasklet */ @@ -2356,14 +2687,130 @@ sdma_free_chan_resources(&sdmac->vc.chan); } + if (sdma->drvdata->pm_runtime) { + pm_runtime_disable(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); + } else { + sdma_runtime_suspend(&pdev->dev); + } + platform_set_drvdata(pdev, NULL); return 0; } +#ifdef CONFIG_PM_SLEEP +static int sdma_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + int i, ret = 0; + + /* Do nothing if not i.MX6SX/6UL or i.MX7D, i.MX8MP */ + if (sdma->drvdata != &sdma_imx6sx && sdma->drvdata != &sdma_imx7d + && sdma->drvdata != &sdma_imx6ul && sdma->drvdata != &sdma_imx8mp) + return 0; + + if (!sdma->is_on) + return 0; + + ret = sdma_save_restore_context(sdma, true); + if (ret) { + dev_err(sdma->dev, "save context error!\n"); + return ret; + } + + /* save regs */ + for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) { + /* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are + * reserved and can't be touched. Skip these regs. + */ + if (i > SDMA_XTRIG_CONF2 / 4) + sdma->save_regs[i] = readl_relaxed(sdma->regs + + MXC_SDMA_RESERVED_REG + + 4 * i); + else + sdma->save_regs[i] = readl_relaxed(sdma->regs + 4 * i); + } + + if (sdma->drvdata->has_done0) { + for (i = 0; i < 2; i++) + sdma->save_done0_regs[i] = + readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG + 4 * i); + } + + return 0; +} + +static int sdma_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + int i, ret; + + /* Do nothing if not i.MX6SX/6UL or i.MX7D, i.MX8MP */ + if (sdma->drvdata != &sdma_imx6sx && sdma->drvdata != &sdma_imx7d + && sdma->drvdata != &sdma_imx6ul && sdma->drvdata != &sdma_imx8mp) + return 0; + + if (!sdma->is_on) + return 0; + + /* Do nothing if mega/fast mix not turned off */ + if (readl_relaxed(sdma->regs + SDMA_H_C0PTR)) + return 0; + + /* Firmware was lost, mark as "not ready" */ + sdma->fw_loaded = false; + + /* restore regs and load firmware */ + for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) { + /* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are + * reserved and can't be touched. Skip these regs. + */ + if (i > SDMA_XTRIG_CONF2 / 4) + writel_relaxed(sdma->save_regs[i], sdma->regs + + MXC_SDMA_RESERVED_REG + 4 * i); + /* set static context switch mode before channel0 running */ + else if (i == SDMA_H_CONFIG / 4) + writel_relaxed(sdma->save_regs[i] & ~SDMA_H_CONFIG_CSM, + sdma->regs + SDMA_H_CONFIG); + else + writel_relaxed(sdma->save_regs[i], sdma->regs + 4 * i); + } + + /* restore SDMA_DONEx_CONFIG */ + if (sdma->drvdata->has_done0) { + for (i = 0; i < 2; i++) + writel_relaxed(sdma->save_done0_regs[i], + sdma->regs + SDMA_DONE0_CONFIG + 4 * i); + } + + /* prepare priority for channel0 to start */ + sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_MAX_PRIORITY); + + if (sdma_load_script(sdma)) + dev_warn(sdma->dev, "failed to load firmware.\n"); + + ret = sdma_save_restore_context(sdma, false); + if (ret) + dev_err(sdma->dev, "restore context error!\n"); + + return ret; +} +#endif + +static const struct dev_pm_ops sdma_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(sdma_suspend, sdma_resume) + SET_RUNTIME_PM_OPS(sdma_runtime_suspend, sdma_runtime_resume, NULL) +}; + static struct platform_driver sdma_driver = { .driver = { .name = "imx-sdma", .of_match_table = sdma_dt_ids, + .pm = &sdma_pm_ops, }, .remove = sdma_remove, .probe = sdma_probe, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/Kconfig linux-imx-phytec/drivers/dma/Kconfig --- linux-6.1.55/drivers/dma/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/Kconfig 2024-06-19 12:33:59.808218353 +0200 @@ -133,6 +133,24 @@ has the capability to offload memcpy, xor and pq computation for raid5/6. +config CRYPTO_DEV_FSL_CAAM_DMA + tristate "CAAM DMA engine support" + depends on CRYPTO_DEV_FSL_CAAM_JR + default n + select DMA_ENGINE + select ASYNC_CORE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Selecting this will offload the DMA operations for users of + the scatter gather memcopy API to the CAAM via job rings. The + CAAM is a hardware module that provides hardware acceleration to + cryptographic operations. It has a built-in DMA controller that can + be programmed to read/write cryptographic data. This module defines + a DMA driver that uses the DMA capabilities of the CAAM. + + To compile this as a module, choose M here: the module + will be called caam_dma. + config DMA_BCM2835 tristate "BCM2835 DMA engine support" depends on ARCH_BCM2835 @@ -231,6 +249,17 @@ or dequeuing DMA jobs from, different work queues. This module can be found on NXP Layerscape SoCs. The qdma driver only work on SoCs with a DPAA hardware block. +config FSL_EDMA_V3 + tristate "Freescale eDMA v3 engine support" + depends on OF + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + help + Support the Freescale eDMA v3 engine with programmable channel. + This driver is based on FSL_EDMA but big changes come such as + different interrupt for different channel, different register + scope for different channel. + This module can be found on Freescale i.MX8QM. config FSL_RAID tristate "Freescale RAID engine Support" @@ -473,7 +502,7 @@ platforms. config MXS_DMA - bool "MXS DMA support" + tristate "MXS DMA support" depends on ARCH_MXS || ARCH_MXC || COMPILE_TEST select STMP_DEVICE select DMA_ENGINE @@ -481,6 +510,8 @@ Support the MXS DMA engine. This engine including APBH-DMA and APBX-DMA is integrated into some Freescale chips. +source "drivers/dma/pxp/Kconfig" + config MX3_IPU bool "MX3x Image Processing Unit support" depends on ARCH_MXC diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/Makefile linux-imx-phytec/drivers/dma/Makefile --- linux-6.1.55/drivers/dma/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/Makefile 2024-06-19 12:33:59.808218353 +0200 @@ -33,6 +33,7 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o +obj-$(CONFIG_FSL_EDMA_V3) += fsl-edma-v3.o obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o @@ -64,6 +65,8 @@ obj-$(CONFIG_PLX_DMA) += plx_dma.o obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ obj-$(CONFIG_PXA_DMA) += pxa_dma.o +obj-$(CONFIG_MXC_PXP_V2) += pxp/ +obj-$(CONFIG_MXC_PXP_V3) += pxp/ obj-$(CONFIG_RENESAS_DMA) += sh/ obj-$(CONFIG_SF_PDMA) += sf-pdma/ obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o @@ -81,6 +84,7 @@ obj-$(CONFIG_UNIPHIER_XDMAC) += uniphier-xdmac.o obj-$(CONFIG_XGENE_DMA) += xgene-dma.o obj-$(CONFIG_ST_FDMA) += st_fdma.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_DMA) += caam_dma.o obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/ obj-$(CONFIG_INTEL_LDMA) += lgm/ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/mxs-dma.c linux-imx-phytec/drivers/dma/mxs-dma.c --- linux-6.1.55/drivers/dma/mxs-dma.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma/mxs-dma.c 2024-06-19 12:33:59.832218763 +0200 @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include @@ -39,6 +41,8 @@ #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH) #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA) +#define MXS_DMA_RPM_TIMEOUT 50 /* ms */ + #define HW_APBHX_CTRL0 0x000 #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) @@ -118,6 +122,7 @@ enum dma_status status; unsigned int flags; bool reset; + struct dma_pool *ccw_pool; #define MXS_DMA_SG_LOOP (1 << 0) #define MXS_DMA_USE_SEMAPHORE (1 << 1) }; @@ -397,11 +402,13 @@ { struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; + struct device *dev = &mxs_dma->pdev->dev; int ret; - mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, - CCW_BLOCK_SIZE, - &mxs_chan->ccw_phys, GFP_KERNEL); + mxs_chan->ccw = dma_pool_zalloc(mxs_chan->ccw_pool, + GFP_ATOMIC, + &mxs_chan->ccw_phys); + if (!mxs_chan->ccw) { ret = -ENOMEM; goto err_alloc; @@ -412,9 +419,11 @@ if (ret) goto err_irq; - ret = clk_prepare_enable(mxs_dma->clk); - if (ret) + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable clock\n"); goto err_clk; + } mxs_dma_reset_chan(chan); @@ -429,8 +438,8 @@ err_clk: free_irq(mxs_chan->chan_irq, mxs_dma); err_irq: - dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, - mxs_chan->ccw, mxs_chan->ccw_phys); + dma_pool_free(mxs_chan->ccw_pool, mxs_chan->ccw, + mxs_chan->ccw_phys); err_alloc: return ret; } @@ -439,15 +448,18 @@ { struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; + struct device *dev = &mxs_dma->pdev->dev; mxs_dma_disable_chan(chan); free_irq(mxs_chan->chan_irq, mxs_dma); - dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, - mxs_chan->ccw, mxs_chan->ccw_phys); + dma_pool_free(mxs_chan->ccw_pool, mxs_chan->ccw, + mxs_chan->ccw_phys); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); - clk_disable_unprepare(mxs_dma->clk); } /* @@ -670,14 +682,32 @@ return mxs_chan->status; } +static int mxs_dma_init_rpm(struct mxs_dma_engine *mxs_dma) +{ + struct device *dev = &mxs_dma->pdev->dev; + + pm_runtime_enable(dev); + pm_runtime_set_autosuspend_delay(dev, MXS_DMA_RPM_TIMEOUT); + pm_runtime_use_autosuspend(dev); + + return 0; +} + static int mxs_dma_init(struct mxs_dma_engine *mxs_dma) { + struct device *dev = &mxs_dma->pdev->dev; int ret; - ret = clk_prepare_enable(mxs_dma->clk); + ret = mxs_dma_init_rpm(mxs_dma); if (ret) return ret; + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable clock\n"); + return ret; + } + ret = stmp_reset_block(mxs_dma->base); if (ret) goto err_out; @@ -695,7 +725,8 @@ mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); err_out: - clk_disable_unprepare(mxs_dma->clk); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); return ret; } @@ -710,6 +741,12 @@ struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; int chan_irq; + if (strcmp(chan->device->dev->driver->name, "mxs-dma")) + return false; + + if (!mxs_dma) + return false; + if (chan->chan_id != param->chan_id) return false; @@ -747,6 +784,7 @@ const struct mxs_dma_type *dma_type; struct mxs_dma_engine *mxs_dma; struct resource *iores; + struct dma_pool *ccw_pool; int ret, i; mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL); @@ -787,19 +825,31 @@ tasklet_setup(&mxs_chan->tasklet, mxs_dma_tasklet); - /* Add the channel to mxs_chan list */ list_add_tail(&mxs_chan->chan.device_node, &mxs_dma->dma_device.channels); } + platform_set_drvdata(pdev, mxs_dma); + mxs_dma->pdev = pdev; + ret = mxs_dma_init(mxs_dma); if (ret) return ret; - mxs_dma->pdev = pdev; mxs_dma->dma_device.dev = &pdev->dev; + /* create the dma pool */ + ccw_pool = dma_pool_create("ccw_pool", + mxs_dma->dma_device.dev, + CCW_BLOCK_SIZE, 32, 0); + + for (i = 0; i < MXS_DMA_CHANNELS; i++) { + struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; + + mxs_chan->ccw_pool = ccw_pool; + } + /* mxs_dma gets 65535 bytes maximum sg size */ dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); @@ -834,12 +884,86 @@ return 0; } +static int mxs_dma_remove(struct platform_device *pdev) +{ + struct mxs_dma_engine *mxs_dma = platform_get_drvdata(pdev); + int i; + + dma_async_device_unregister(&mxs_dma->dma_device); + dma_pool_destroy(mxs_dma->mxs_chans[0].ccw_pool); + + for (i = 0; i < MXS_DMA_CHANNELS; i++) { + struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; + + tasklet_kill(&mxs_chan->tasklet); + mxs_chan->ccw_pool = NULL; + } + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int mxs_dma_pm_suspend(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_suspend(dev); + + return ret; +} + +static int mxs_dma_pm_resume(struct device *dev) +{ + struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); + int ret; + + ret = mxs_dma_init(mxs_dma); + if (ret) + return ret; + + return 0; +} +#endif + +int mxs_dma_runtime_suspend(struct device *dev) +{ + struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); + + clk_disable_unprepare(mxs_dma->clk); + + return 0; +} + +int mxs_dma_runtime_resume(struct device *dev) +{ + struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(mxs_dma->clk); + if (ret) { + dev_err(&mxs_dma->pdev->dev, "failed to enable the clock\n"); + return ret; + } + + return 0; +} + +static const struct dev_pm_ops mxs_dma_pm_ops = { + SET_RUNTIME_PM_OPS(mxs_dma_runtime_suspend, mxs_dma_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(mxs_dma_pm_suspend, mxs_dma_pm_resume) +}; + static struct platform_driver mxs_dma_driver = { .driver = { .name = "mxs-dma", + .pm = &mxs_dma_pm_ops, .of_match_table = mxs_dma_dt_ids, }, + .remove = mxs_dma_remove, .probe = mxs_dma_probe, }; builtin_platform_driver(mxs_dma_driver); + +MODULE_DESCRIPTION("MXS DMA driver"); +MODULE_LICENSE("GPL"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/pxp/Kconfig linux-imx-phytec/drivers/dma/pxp/Kconfig --- linux-6.1.55/drivers/dma/pxp/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/dma/pxp/Kconfig 2024-06-19 12:33:59.832218763 +0200 @@ -0,0 +1,21 @@ +config MXC_PXP_V2 + bool "MXC PxP V2 support" + depends on ARM + select DMA_ENGINE + help + Support the PxP (Pixel Pipeline) on i.MX6 DualLite and i.MX6 SoloLite. + If unsure, select N. + +config MXC_PXP_V3 + bool "MXC PxP V3 support" + select DMA_ENGINE + help + Support the PxP V3(Pixel Pipeline) on i.MX7D. The PxP V3 supports + more functions than PxP V2, dithering, reagl/-D and etc. + If unsure, select N. + +config MXC_PXP_CLIENT_DEVICE + bool "MXC PxP Client Device" + default y + depends on MXC_PXP_V2 || MXC_PXP_V3 + diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/pxp/Makefile linux-imx-phytec/drivers/dma/pxp/Makefile --- linux-6.1.55/drivers/dma/pxp/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/dma/pxp/Makefile 2024-06-19 12:33:59.832218763 +0200 @@ -0,0 +1,3 @@ +obj-$(CONFIG_MXC_PXP_V2) += pxp_dma_v2.o +obj-$(CONFIG_MXC_PXP_V3) += pxp_dma_v3.o +obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/pxp/pxp_device.c linux-imx-phytec/drivers/dma/pxp/pxp_device.c --- linux-6.1.55/drivers/dma/pxp/pxp_device.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/dma/pxp/pxp_device.c 2024-06-19 12:33:59.832218763 +0200 @@ -0,0 +1,1164 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BUFFER_HASH_ORDER 4 + +static struct pxp_buffer_hash bufhash; +static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL]; +static int major; +static struct class *pxp_class; +static struct device *pxp_dev; + +static int pxp_ht_create(struct pxp_buffer_hash *hash, int order) +{ + unsigned long i; + unsigned long table_size; + + table_size = 1U << order; + + hash->order = order; + hash->hash_table = kmalloc(sizeof(*hash->hash_table) * table_size, GFP_KERNEL); + + if (!hash->hash_table) { + pr_err("%s: Out of memory for hash table\n", __func__); + return -ENOMEM; + } + + for (i = 0; i < table_size; i++) + INIT_HLIST_HEAD(&hash->hash_table[i]); + + return 0; +} + +static int pxp_ht_insert_item(struct pxp_buffer_hash *hash, + struct pxp_buf_obj *new) +{ + unsigned long hashkey; + struct hlist_head *h_list; + + hashkey = hash_long(new->offset >> PAGE_SHIFT, hash->order); + h_list = &hash->hash_table[hashkey]; + + spin_lock(&hash->hash_lock); + hlist_add_head_rcu(&new->item, h_list); + spin_unlock(&hash->hash_lock); + + return 0; +} + +static int pxp_ht_remove_item(struct pxp_buffer_hash *hash, + struct pxp_buf_obj *obj) +{ + spin_lock(&hash->hash_lock); + hlist_del_init_rcu(&obj->item); + spin_unlock(&hash->hash_lock); + return 0; +} + +static struct hlist_node *pxp_ht_find_key(struct pxp_buffer_hash *hash, + unsigned long key) +{ + struct pxp_buf_obj *entry; + struct hlist_head *h_list; + unsigned long hashkey; + + hashkey = hash_long(key, hash->order); + h_list = &hash->hash_table[hashkey]; + + hlist_for_each_entry_rcu(entry, h_list, item) { + if (entry->offset >> PAGE_SHIFT == key) + return &entry->item; + } + + return NULL; +} + +static void pxp_ht_destroy(struct pxp_buffer_hash *hash) +{ + kfree(hash->hash_table); + hash->hash_table = NULL; +} + +static int pxp_buffer_handle_create(struct pxp_file *file_priv, + struct pxp_buf_obj *obj, + uint32_t *handlep) +{ + int ret; + + idr_preload(GFP_KERNEL); + spin_lock(&file_priv->buffer_lock); + + ret = idr_alloc(&file_priv->buffer_idr, obj, 1, 0, GFP_NOWAIT); + + spin_unlock(&file_priv->buffer_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handlep = ret; + + return 0; +} + +static struct pxp_buf_obj * +pxp_buffer_object_lookup(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_buf_obj *obj; + + spin_lock(&file_priv->buffer_lock); + + obj = idr_find(&file_priv->buffer_idr, handle); + if (!obj) { + spin_unlock(&file_priv->buffer_lock); + return NULL; + } + + spin_unlock(&file_priv->buffer_lock); + + return obj; +} + +static int pxp_buffer_handle_delete(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_buf_obj *obj; + + spin_lock(&file_priv->buffer_lock); + + obj = idr_find(&file_priv->buffer_idr, handle); + if (!obj) { + spin_unlock(&file_priv->buffer_lock); + return -EINVAL; + } + + idr_remove(&file_priv->buffer_idr, handle); + spin_unlock(&file_priv->buffer_lock); + + return 0; +} + +static int pxp_channel_handle_create(struct pxp_file *file_priv, + struct pxp_chan_obj *obj, + uint32_t *handlep) +{ + int ret; + + idr_preload(GFP_KERNEL); + spin_lock(&file_priv->channel_lock); + + ret = idr_alloc(&file_priv->channel_idr, obj, 0, 0, GFP_NOWAIT); + + spin_unlock(&file_priv->channel_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handlep = ret; + + return 0; +} + +static struct pxp_chan_obj * +pxp_channel_object_lookup(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_chan_obj *obj; + + spin_lock(&file_priv->channel_lock); + + obj = idr_find(&file_priv->channel_idr, handle); + if (!obj) { + spin_unlock(&file_priv->channel_lock); + return NULL; + } + + spin_unlock(&file_priv->channel_lock); + + return obj; +} + +static int pxp_channel_handle_delete(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_chan_obj *obj; + + spin_lock(&file_priv->channel_lock); + + obj = idr_find(&file_priv->channel_idr, handle); + if (!obj) { + spin_unlock(&file_priv->channel_lock); + return -EINVAL; + } + + idr_remove(&file_priv->channel_idr, handle); + spin_unlock(&file_priv->channel_lock); + + return 0; +} + +static int pxp_alloc_dma_buffer(struct pxp_buf_obj *obj) +{ + obj->virtual = dma_alloc_coherent(pxp_dev, PAGE_ALIGN(obj->size), + (dma_addr_t *) (&obj->offset), + GFP_DMA | GFP_KERNEL); + pr_debug("[ALLOC] mem alloc phys_addr = 0x%lx\n", obj->offset); + + if (obj->virtual == NULL) { + printk(KERN_ERR "Physical memory allocation error!\n"); + return -1; + } + + return 0; +} + +static void pxp_free_dma_buffer(struct pxp_buf_obj *obj) +{ + if (obj->virtual != NULL) { + dma_free_coherent(pxp_dev, PAGE_ALIGN(obj->size), + obj->virtual, (dma_addr_t)obj->offset); + } +} + +static int +pxp_buffer_object_free(int id, void *ptr, void *data) +{ + struct pxp_file *file_priv = data; + struct pxp_buf_obj *obj = ptr; + int ret; + + ret = pxp_buffer_handle_delete(file_priv, obj->handle); + if (ret < 0) + return ret; + + pxp_ht_remove_item(&bufhash, obj); + pxp_free_dma_buffer(obj); + kfree(obj); + + return 0; +} + +static int +pxp_channel_object_free(int id, void *ptr, void *data) +{ + struct pxp_file *file_priv = data; + struct pxp_chan_obj *obj = ptr; + int chan_id; + + chan_id = obj->chan->chan_id; + wait_event(irq_info[chan_id].waitq, + atomic_read(&irq_info[chan_id].irq_pending) == 0); + + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(obj->chan); + kfree(obj); + + return 0; +} + +static void pxp_free_buffers(struct pxp_file *file_priv) +{ + idr_for_each(&file_priv->buffer_idr, + &pxp_buffer_object_free, file_priv); + idr_destroy(&file_priv->buffer_idr); +} + +static void pxp_free_channels(struct pxp_file *file_priv) +{ + idr_for_each(&file_priv->channel_idr, + &pxp_channel_object_free, file_priv); + idr_destroy(&file_priv->channel_idr); +} + +/* Callback function triggered after PxP receives an EOF interrupt */ +static void pxp_dma_done(void *arg) +{ + struct pxp_tx_desc *tx_desc = to_tx_desc(arg); + struct dma_chan *chan = tx_desc->txd.chan; + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + int chan_id = pxp_chan->dma_chan.chan_id; + + pr_debug("DMA Done ISR, chan_id %d\n", chan_id); + + atomic_dec(&irq_info[chan_id].irq_pending); + irq_info[chan_id].hist_status = tx_desc->hist_status; + + wake_up(&(irq_info[chan_id].waitq)); +} + +static int pxp_ioc_config_chan(struct pxp_file *priv, unsigned long arg) +{ + struct scatterlist *sg; + struct pxp_tx_desc *desc; + struct dma_async_tx_descriptor *txd; + struct pxp_config_data *pxp_conf; + dma_cookie_t cookie; + int handle, chan_id; + struct dma_chan *chan; + struct pxp_chan_obj *obj; + int i = 0, j = 0, k = 0, m = 0, length, ret, sg_len; + + pxp_conf = kzalloc(sizeof(*pxp_conf), GFP_KERNEL); + if (!pxp_conf) + return -ENOMEM; + + ret = copy_from_user(pxp_conf, + (struct pxp_config_data *)arg, + sizeof(struct pxp_config_data)); + if (ret) { + kfree(pxp_conf); + return -EFAULT; + } + + handle = pxp_conf->handle; + obj = pxp_channel_object_lookup(priv, handle); + if (!obj) { + kfree(pxp_conf); + return -EINVAL; + } + chan = obj->chan; + chan_id = chan->chan_id; + + sg_len = 3; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_A) + sg_len += 4; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_B) + sg_len += 4; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_DITHER) + sg_len += 4; + + sg = kmalloc(sizeof(*sg) * sg_len, GFP_KERNEL); + if (!sg) { + kfree(pxp_conf); + return -ENOMEM; + } + + sg_init_table(sg, sg_len); + + txd = chan->device->device_prep_slave_sg(chan, + sg, sg_len, + DMA_MEM_TO_DEV, + DMA_PREP_INTERRUPT, + NULL); + if (!txd) { + pr_err("Error preparing a DMA transaction descriptor.\n"); + kfree(pxp_conf); + kfree(sg); + return -EIO; + } + + txd->callback_param = txd; + txd->callback = pxp_dma_done; + + desc = to_tx_desc(txd); + + length = desc->len; + for (i = 0; i < length; i++) { + if (i == 0) { /* S0 */ + memcpy(&desc->proc_data, + &pxp_conf->proc_data, + sizeof(struct pxp_proc_data)); + memcpy(&desc->layer_param.s0_param, + &pxp_conf->s0_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if (i == 1) { /* Output */ + memcpy(&desc->layer_param.out_param, + &pxp_conf->out_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if (i == 2) { + /* OverLay */ + memcpy(&desc->layer_param.ol_param, + &pxp_conf->ol_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_A) && (j < 4)) { + for (j = 0; j < 4; j++) { + if (j == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_FETCH0; + } else if (j == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_FETCH1; + } else if (j == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_STORE0; + } else if (j == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_STORE1; + } + + desc = desc->next; + } + + i += 4; + + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_B) && (m < 4)) { + for (m = 0; m < 4; m++) { + if (m == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_FETCH0; + } else if (m == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_FETCH1; + } else if (m == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_STORE0; + } else if (m == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_STORE1; + } + + desc = desc->next; + } + + i += 4; + + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_DITHER) && (k < 4)) { + for (k = 0; k < 4; k++) { + if (k == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_FETCH0; + } else if (k == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_FETCH1; + } else if (k == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_STORE0; + } else if (k == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_STORE1; + } + + desc = desc->next; + } + + i += 4; + } + } + + cookie = txd->tx_submit(txd); + if (cookie < 0) { + pr_err("Error tx_submit\n"); + kfree(pxp_conf); + kfree(sg); + return -EIO; + } + + atomic_inc(&irq_info[chan_id].irq_pending); + + kfree(pxp_conf); + kfree(sg); + + return 0; +} + +static int pxp_device_open(struct inode *inode, struct file *filp) +{ + struct pxp_file *priv; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + + if (!priv) + return -ENOMEM; + + filp->private_data = priv; + priv->filp = filp; + + idr_init(&priv->buffer_idr); + spin_lock_init(&priv->buffer_lock); + + idr_init(&priv->channel_idr); + spin_lock_init(&priv->channel_lock); + + return 0; +} + +static int pxp_device_release(struct inode *inode, struct file *filp) +{ + struct pxp_file *priv = filp->private_data; + + if (priv) { + pxp_free_channels(priv); + pxp_free_buffers(priv); + kfree(priv); + filp->private_data = NULL; + } + + return 0; +} + +static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma) +{ + int request_size; + struct hlist_node *node; + struct pxp_buf_obj *obj; + + request_size = vma->vm_end - vma->vm_start; + + pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n", + (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff), + request_size); + + node = pxp_ht_find_key(&bufhash, vma->vm_pgoff); + if (!node) + return -EINVAL; + + obj = list_entry(node, struct pxp_buf_obj, item); + if (obj->offset + (obj->size >> PAGE_SHIFT) < + (vma->vm_pgoff + vma_pages(vma))) + return -ENOMEM; + + switch (obj->mem_type) { + case MEMORY_TYPE_UNCACHED: + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + break; + case MEMORY_TYPE_WC: + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + break; + case MEMORY_TYPE_CACHED: + break; + default: + pr_err("%s: invalid memory type!\n", __func__); + return -EINVAL; + } + + return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + request_size, vma->vm_page_prot) ? -EAGAIN : 0; +} + +static bool chan_filter(struct dma_chan *chan, void *arg) +{ + if (imx_dma_is_pxp(chan)) + return true; + else + return false; +} + +/*********************************************/ +/* DMABUF ops for exporters */ +/*********************************************/ + +static struct sg_table *pxp_get_base_sgt(struct pxp_buf_obj *obj) +{ + int ret; + struct sg_table *sgt; + + sgt = kmalloc(sizeof(*sgt), GFP_KERNEL); + if (!sgt) { + dev_err(pxp_dev, "failed to alloc sg table\n"); + return NULL; + } + + ret = dma_get_sgtable_attrs(pxp_dev, sgt, obj->virtual, + (dma_addr_t)obj->offset, + PAGE_ALIGN(obj->size), obj->attrs); + if (ret < 0) { + dev_err(pxp_dev, "failed to get scatterlist from DMA API\n"); + kfree(sgt); + return NULL; + } + + return sgt; +} + + +static int pxp_dmabuf_ops_attach(struct dma_buf *dbuf, + struct dma_buf_attachment *dbuf_attach) +{ + struct pxp_attachment *attach; + struct sg_table *sgt; + struct scatterlist *rd, *wr; + struct pxp_buf_obj *obj = dbuf->priv; + int ret, i; + + attach = kzalloc(sizeof(*attach), GFP_KERNEL); + if (!attach) + return -ENOMEM; + + sgt = &attach->sgt; + ret = sg_alloc_table(sgt, obj->sgt_base->orig_nents, GFP_KERNEL); + if (ret) { + kfree(attach); + return -ENOMEM; + } + + rd = obj->sgt_base->sgl; + wr = sgt->sgl; + for (i = 0; i < sgt->orig_nents; ++i) { + sg_set_page(wr, sg_page(rd), rd->length, rd->offset); + rd = sg_next(rd); + wr = sg_next(wr); + } + + attach->dma_dir = DMA_NONE; + dbuf_attach->priv = attach; + + return 0; +} + +static void pxp_dmabuf_ops_detach(struct dma_buf *dbuf, + struct dma_buf_attachment *db_attach) +{ + struct pxp_attachment *attach = db_attach->priv; + struct sg_table *sgt; + + if (!attach) + return; + + sgt = &attach->sgt; + + if (attach->dma_dir != DMA_NONE) + dma_unmap_sgtable(db_attach->dev, sgt, attach->dma_dir, + DMA_ATTR_SKIP_CPU_SYNC); + sg_free_table(sgt); + kfree(attach); + db_attach->priv = NULL; +} + +static struct sg_table *pxp_dmabuf_ops_map( + struct dma_buf_attachment *db_attach, enum dma_data_direction dma_dir) +{ + struct pxp_attachment *attach = db_attach->priv; + struct mutex *lock = &db_attach->dmabuf->lock; + struct sg_table *sgt; + + mutex_lock(lock); + + sgt = &attach->sgt; + /* return previously mapped sg table */ + if (attach->dma_dir == dma_dir) { + mutex_unlock(lock); + return sgt; + } + + /* release any previous cache */ + if (attach->dma_dir != DMA_NONE) { + dma_unmap_sgtable(db_attach->dev, sgt, attach->dma_dir, + DMA_ATTR_SKIP_CPU_SYNC); + attach->dma_dir = DMA_NONE; + } + + /* + * mapping to the client with new direction, no cache sync + * required see comment in vb2_dc_dmabuf_ops_detach() + */ + if (dma_map_sgtable(db_attach->dev, sgt, dma_dir, + DMA_ATTR_SKIP_CPU_SYNC)) { + pr_err("failed to map scatterlist\n"); + mutex_unlock(lock); + return ERR_PTR(-EIO); + } + + attach->dma_dir = dma_dir; + + mutex_unlock(lock); + + return sgt; +} + +static void pxp_dmabuf_ops_unmap(struct dma_buf_attachment *db_attach, + struct sg_table *sgt, + enum dma_data_direction dma_dir) +{ + /* nothing to be done here */ +} + +static void pxp_dmabuf_ops_release(struct dma_buf *dbuf) +{ + /* nothing to be done here */ +} + +static int +pxp_dmabuf_ops_begin_cpu_access(struct dma_buf *dbuf, + enum dma_data_direction direction) +{ + return 0; +} + +static int +pxp_dmabuf_ops_end_cpu_access(struct dma_buf *dbuf, + enum dma_data_direction direction) +{ + return 0; +} + +static int pxp_dmabuf_ops_vmap(struct dma_buf *dbuf, struct iosys_map *map) +{ + struct pxp_buf_obj *obj = dbuf->priv; + + iosys_map_set_vaddr(map, obj->virtual); + + return 0; +} + +static int pxp_dmabuf_ops_mmap(struct dma_buf *dbuf, + struct vm_area_struct *vma) +{ + /* Don't support so far */ + return 0; +} + +static const struct dma_buf_ops pxp_dmabuf_ops = { + .attach = pxp_dmabuf_ops_attach, + .detach = pxp_dmabuf_ops_detach, + .map_dma_buf = pxp_dmabuf_ops_map, + .unmap_dma_buf = pxp_dmabuf_ops_unmap, + .begin_cpu_access = pxp_dmabuf_ops_begin_cpu_access, + .end_cpu_access = pxp_dmabuf_ops_end_cpu_access, + .vmap = pxp_dmabuf_ops_vmap, + .mmap = pxp_dmabuf_ops_mmap, + .release = pxp_dmabuf_ops_release, +}; + +static long pxp_device_ioctl(struct file *filp, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + struct pxp_file *file_priv = filp->private_data; + + switch (cmd) { + case PXP_IOC_GET_CHAN: + { + int ret; + struct dma_chan *chan = NULL; + dma_cap_mask_t mask; + struct pxp_chan_obj *obj = NULL; + + pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__); + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_cap_set(DMA_PRIVATE, mask); + + chan = dma_request_channel(mask, chan_filter, NULL); + if (!chan) { + pr_err("Unsccessfully received channel!\n"); + return -EBUSY; + } + + pr_debug("Successfully received channel." + "chan_id %d\n", chan->chan_id); + + obj = kzalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) { + dma_release_channel(chan); + return -ENOMEM; + } + obj->chan = chan; + + ret = pxp_channel_handle_create(file_priv, obj, + &obj->handle); + if (ret) { + dma_release_channel(chan); + kfree(obj); + return ret; + } + + init_waitqueue_head(&(irq_info[chan->chan_id].waitq)); + if (put_user(obj->handle, (u32 __user *) arg)) { + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(chan); + kfree(obj); + return -EFAULT; + } + + break; + } + case PXP_IOC_PUT_CHAN: + { + int handle; + struct pxp_chan_obj *obj; + + if (get_user(handle, (u32 __user *) arg)) + return -EFAULT; + + pr_debug("%d release handle %d\n", __LINE__, handle); + + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(obj->chan); + kfree(obj); + + break; + } + case PXP_IOC_CONFIG_CHAN: + { + int ret; + + ret = pxp_ioc_config_chan(file_priv, arg); + if (ret) + return ret; + + break; + } + case PXP_IOC_START_CHAN: + { + int handle; + struct pxp_chan_obj *obj = NULL; + + if (get_user(handle, (u32 __user *) arg)) + return -EFAULT; + + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + + dma_async_issue_pending(obj->chan); + + break; + } + case PXP_IOC_GET_PHYMEM: + { + struct pxp_mem_desc buffer; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&buffer, + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EFAULT; + + pr_debug("[ALLOC] mem alloc size = 0x%x\n", + buffer.size); + + obj = kzalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) + return -ENOMEM; + obj->size = buffer.size; + obj->mem_type = buffer.mtype; + + ret = pxp_alloc_dma_buffer(obj); + if (ret == -1) { + printk(KERN_ERR + "Physical memory allocation error!\n"); + kfree(obj); + return ret; + } + + ret = pxp_buffer_handle_create(file_priv, obj, &obj->handle); + if (ret) { + pxp_free_dma_buffer(obj); + kfree(obj); + return ret; + } + buffer.handle = obj->handle; + buffer.phys_addr = obj->offset; + + ret = copy_to_user((void __user *)arg, &buffer, + sizeof(struct pxp_mem_desc)); + if (ret) { + pxp_buffer_handle_delete(file_priv, buffer.handle); + pxp_free_dma_buffer(obj); + kfree(obj); + return -EFAULT; + } + + pxp_ht_insert_item(&bufhash, obj); + + break; + } + case PXP_IOC_PUT_PHYMEM: + { + struct pxp_mem_desc pxp_mem; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&pxp_mem, + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EACCES; + + obj = pxp_buffer_object_lookup(file_priv, pxp_mem.handle); + if (!obj) + return -EINVAL; + + if (obj->sgt_base) { + sg_free_table(obj->sgt_base); + kfree(obj->sgt_base); + } + + ret = pxp_buffer_handle_delete(file_priv, obj->handle); + if (ret) + return ret; + + pxp_ht_remove_item(&bufhash, obj); + pxp_free_dma_buffer(obj); + kfree(obj); + + break; + } + case PXP_IOC_FLUSH_PHYMEM: + { + int ret; + struct pxp_mem_flush flush; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&flush, + (struct pxp_mem_flush *)arg, + sizeof(struct pxp_mem_flush)); + if (ret) + return -EACCES; + + if (flush.handle) { + obj = pxp_buffer_object_lookup(file_priv, flush.handle); + if (!obj) + return -EINVAL; + + switch (flush.type) { + case CACHE_CLEAN: + dma_sync_single_for_device(pxp_dev, obj->offset, + obj->size, DMA_TO_DEVICE); + break; + case CACHE_INVALIDATE: + dma_sync_single_for_device(pxp_dev, obj->offset, + obj->size, DMA_FROM_DEVICE); + break; + case CACHE_FLUSH: + dma_sync_single_for_device(pxp_dev, obj->offset, + obj->size, DMA_TO_DEVICE); + dma_sync_single_for_device(pxp_dev, obj->offset, + obj->size, DMA_FROM_DEVICE); + break; + default: + pr_err("%s: invalid cache flush type\n", __func__); + return -EINVAL; + } + } else { + struct dma_buf *dmabuf; + struct dma_buf_attachment *attachment; + struct sg_table *sgt; + int direction; + + if (flush.type == CACHE_CLEAN) + direction = DMA_TO_DEVICE; + else if (flush.type == CACHE_INVALIDATE) + direction = DMA_FROM_DEVICE; + else if (flush.type == CACHE_FLUSH) + direction = DMA_BIDIRECTIONAL; + else + direction = DMA_NONE; + + ret = 0; + dmabuf = dma_buf_get(flush.dmabuf_fd); + if (IS_ERR(dmabuf)) { + dev_err(pxp_dev, "failed to get dmabuf\n"); + return PTR_ERR(dmabuf); + } + attachment = dma_buf_attach(dmabuf, pxp_dev); + if (IS_ERR(attachment)) { + ret = PTR_ERR(attachment); + dev_err(pxp_dev, "failed to attach dmabuf\n"); + goto err_put; + } + sgt = dma_buf_map_attachment(attachment, direction); + if (IS_ERR(sgt)) { + ret = PTR_ERR(sgt); + dev_err(pxp_dev, "failed to get dmabuf sg_table\n"); + goto err_detach; + } + dma_buf_unmap_attachment(attachment, sgt, direction); +err_detach: + dma_buf_detach(dmabuf, attachment); +err_put: + dma_buf_put(dmabuf); + if (ret) + return ret; + } + + break; + } + case PXP_IOC_WAIT4CMPLT: + { + struct pxp_chan_handle chan_handle; + int ret, chan_id, handle; + struct pxp_chan_obj *obj = NULL; + + ret = copy_from_user(&chan_handle, + (struct pxp_chan_handle *)arg, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + + handle = chan_handle.handle; + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + chan_id = obj->chan->chan_id; + + ret = wait_event_interruptible + (irq_info[chan_id].waitq, + (atomic_read(&irq_info[chan_id].irq_pending) == 0)); + if (ret < 0) + return -ERESTARTSYS; + + chan_handle.hist_status = irq_info[chan_id].hist_status; + ret = copy_to_user((struct pxp_chan_handle *)arg, + &chan_handle, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + break; + } + case PXP_IOC_EXPBUF: + { + struct pxp_mem_desc buffer; + struct dma_buf *dbuf; + struct pxp_buf_obj *obj; + DEFINE_DMA_BUF_EXPORT_INFO(pxp_exp_info); + + ret = copy_from_user(&buffer, (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EFAULT; + + obj = pxp_buffer_object_lookup(file_priv, buffer.handle); + if (!obj) + return -EINVAL; + + if (!obj->sgt_base) + obj->sgt_base = pxp_get_base_sgt(obj); + + if (WARN_ON(!obj->sgt_base)) + return -EINVAL; + + pxp_exp_info.ops = &pxp_dmabuf_ops; + pxp_exp_info.flags = buffer.flags; + pxp_exp_info.size = obj->size; + pxp_exp_info.priv = obj; + + dbuf = dma_buf_export(&pxp_exp_info); + if (IS_ERR(dbuf)) + return PTR_ERR(dbuf); + + /* need to check buffer.flags */ + ret = dma_buf_fd(dbuf, buffer.flags & ~O_ACCMODE); + if (ret < 0) + return ret; + buffer.fd = ret; + + ret = copy_to_user((void __user *)arg, &buffer, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EFAULT; + break; + } + default: + break; + } + + return 0; +} + +static const struct file_operations pxp_device_fops = { + .open = pxp_device_open, + .release = pxp_device_release, + .unlocked_ioctl = pxp_device_ioctl, + .mmap = pxp_device_mmap, +}; + +int register_pxp_device(void) +{ + int ret; + + if (!major) { + major = register_chrdev(0, "pxp_device", &pxp_device_fops); + if (major < 0) { + printk(KERN_ERR "Unable to register pxp device\n"); + ret = major; + goto register_cdev_fail; + } + + pxp_class = class_create(THIS_MODULE, "pxp_device"); + if (IS_ERR(pxp_class)) { + ret = PTR_ERR(pxp_class); + goto pxp_class_fail; + } + + pxp_dev = device_create(pxp_class, NULL, MKDEV(major, 0), + NULL, "pxp_device"); + if (IS_ERR(pxp_dev)) { + ret = PTR_ERR(pxp_dev); + goto dev_create_fail; + } + pxp_dev->dma_mask = kmalloc(sizeof(*pxp_dev->dma_mask), + GFP_KERNEL); + *pxp_dev->dma_mask = DMA_BIT_MASK(32); + pxp_dev->coherent_dma_mask = DMA_BIT_MASK(32); + } + + ret = pxp_ht_create(&bufhash, BUFFER_HASH_ORDER); + if (ret) { + goto ht_create_fail; + } + spin_lock_init(&(bufhash.hash_lock)); + + pr_debug("PxP_Device registered Successfully\n"); + return 0; + +ht_create_fail: + device_destroy(pxp_class, MKDEV(major, 0)); +dev_create_fail: + class_destroy(pxp_class); +pxp_class_fail: + unregister_chrdev(major, "pxp_device"); +register_cdev_fail: + return ret; +} + +void unregister_pxp_device(void) +{ + pxp_ht_destroy(&bufhash); + if (major) { + device_destroy(pxp_class, MKDEV(major, 0)); + class_destroy(pxp_class); + unregister_chrdev(major, "pxp_device"); + major = 0; + } +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/pxp/pxp_dma_v2.c linux-imx-phytec/drivers/dma/pxp/pxp_dma_v2.c --- linux-6.1.55/drivers/dma/pxp/pxp_dma_v2.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/dma/pxp/pxp_dma_v2.c 2024-06-19 12:33:59.836218832 +0200 @@ -0,0 +1,1849 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regs-pxp_v2.h" + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +static LIST_HEAD(head); +static int timeout_in_ms = 600; +static unsigned int block_size; +static struct kmem_cache *tx_desc_cache; + +struct pxp_dma { + struct dma_device dma; +}; + +struct pxps { + struct platform_device *pdev; + struct clk *clk; + struct clk *clk_disp_axi; /* may exist on some SoC for gating */ + void __iomem *base; + int irq; /* PXP IRQ to the CPU */ + + spinlock_t lock; + struct mutex clk_mutex; + int clk_stat; +#define CLK_STAT_OFF 0 +#define CLK_STAT_ON 1 + int pxp_ongoing; + int lut_state; + + struct device *dev; + struct pxp_dma pxp_dma; + struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; + struct work_struct work; + + /* describes most recent processing configuration */ + struct pxp_config_data pxp_conf_state; + + /* to turn clock off when pxp is inactive */ + struct timer_list clk_timer; + + /* for pxp config dispatch asynchronously*/ + struct task_struct *dispatch; + wait_queue_head_t thread_waitq; + struct completion complete; +}; + +#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) +#define to_pxp(id) container_of(id, struct pxps, pxp_dma) + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +/* + * PXP common functions + */ +static void dump_pxp_reg(struct pxps *pxp) +{ + dev_dbg(pxp->dev, "PXP_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CTRL)); + dev_dbg(pxp->dev, "PXP_STAT 0x%x", + __raw_readl(pxp->base + HW_PXP_STAT)); + dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_CTRL)); + dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF)); + dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF2)); + dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PITCH)); + dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC)); + dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CTRL)); + dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BUF)); + dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_UBUF)); + dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_VBUF)); + dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_PITCH)); + dev_dbg(pxp->dev, "PXP_PS_BACKGROUND 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND)); + dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_SCALE)); + dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_OFFSET)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH)); + dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CTRL)); + dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_BUF)); + dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_PITCH)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_CTRL)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF3)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF4)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF5)); + dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_CTRL)); + dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_ADDR)); + dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_DATA)); + dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM)); + dev_dbg(pxp->dev, "PXP_CFA 0x%x", + __raw_readl(pxp->base + HW_PXP_CFA)); + dev_dbg(pxp->dev, "PXP_HIST_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST_CTRL)); + dev_dbg(pxp->dev, "PXP_HIST2_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST2_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST4_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST4_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM2 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM2)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM3 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM3)); + dev_dbg(pxp->dev, "PXP_POWER 0x%x", + __raw_readl(pxp->base + HW_PXP_POWER)); + dev_dbg(pxp->dev, "PXP_NEXT 0x%x", + __raw_readl(pxp->base + HW_PXP_NEXT)); + dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUGCTRL)); + dev_dbg(pxp->dev, "PXP_DEBUG 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUG)); + dev_dbg(pxp->dev, "PXP_VERSION 0x%x", + __raw_readl(pxp->base + HW_PXP_VERSION)); +} + +static bool is_yuv(u32 pix_fmt) +{ + switch (pix_fmt) { + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_Y41P: + case PXP_PIX_FMT_VUY444: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_YVU410P: + case PXP_PIX_FMT_YUV410P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YUV420P2: + case PXP_PIX_FMT_YVU422P: + case PXP_PIX_FMT_YUV422P: + return true; + default: + return false; + } +} + +static void pxp_soft_reset(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_SET); + while (!(__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_CLKGATE)) + dev_dbg(pxp->dev, "%s: wait for clock gate off", __func__); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); +} + +static void pxp_set_ctrl(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 ctrl; + u32 fmt_ctrl; + int need_swap = 0; /* to support YUYV and YVYU formats */ + + /* Configure S0 input format */ + switch (pxp_conf->s0_param.pixel_fmt) { + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_YVU420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_VUY444: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_YUYV: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + need_swap = 1; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_YVYU: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + need_swap = 1; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_PS_CTRL_FORMAT(fmt_ctrl) | BF_PXP_PS_CTRL_SWAP(need_swap); + __raw_writel(ctrl, pxp->base + HW_PXP_PS_CTRL_SET); + + /* Configure output format based on out_channel format */ + switch (pxp_conf->out_param.pixel_fmt) { + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_BGRA32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_OUT_CTRL_FORMAT(fmt_ctrl); + __raw_writel(ctrl, pxp->base + HW_PXP_OUT_CTRL); + + ctrl = 0; + if (proc_data->scaling) + ; + if (proc_data->vflip) + ctrl |= BM_PXP_CTRL_VFLIP; + if (proc_data->hflip) + ctrl |= BM_PXP_CTRL_HFLIP; + if (proc_data->rotate) + ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90); + + /* In default, the block size is set to 8x8 + * But block size can be set to 16x16 due to + * blocksize variable modification + */ + ctrl |= block_size << 23; + + __raw_writel(ctrl, pxp->base + HW_PXP_CTRL); +} + +static int pxp_start(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET); + __raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET); + dump_pxp_reg(pxp); + + return 0; +} + +static void pxp_set_outbuf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + __raw_writel(out_params->paddr, pxp->base + HW_PXP_OUT_BUF); + + if ((out_params->pixel_fmt == PXP_PIX_FMT_NV12) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV21) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV61)) { + dma_addr_t Y, U; + + Y = out_params->paddr; + U = Y + (out_params->width * out_params->height); + + __raw_writel(U, pxp->base + HW_PXP_OUT_BUF2); + } + + if (proc_data->rotate == 90 || proc_data->rotate == 270) + __raw_writel(BF_PXP_OUT_LRC_X(out_params->height - 1) | + BF_PXP_OUT_LRC_Y(out_params->width - 1), + pxp->base + HW_PXP_OUT_LRC); + else + __raw_writel(BF_PXP_OUT_LRC_X(out_params->width - 1) | + BF_PXP_OUT_LRC_Y(out_params->height - 1), + pxp->base + HW_PXP_OUT_LRC); + + if (out_params->pixel_fmt == PXP_PIX_FMT_RGB24) { + __raw_writel(out_params->stride * 3, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_BGRA32 || + out_params->pixel_fmt == PXP_PIX_FMT_XRGB32) { + __raw_writel(out_params->stride << 2, + pxp->base + HW_PXP_OUT_PITCH); + } else if ((out_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (out_params->pixel_fmt == PXP_PIX_FMT_RGB555)) { + __raw_writel(out_params->stride << 1, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_UYVY || + (out_params->pixel_fmt == PXP_PIX_FMT_VYUY)) { + __raw_writel(out_params->stride << 1, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_GREY || + out_params->pixel_fmt == PXP_PIX_FMT_NV12 || + out_params->pixel_fmt == PXP_PIX_FMT_NV21 || + out_params->pixel_fmt == PXP_PIX_FMT_NV16 || + out_params->pixel_fmt == PXP_PIX_FMT_NV61) { + __raw_writel(out_params->stride, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_GY04) { + __raw_writel(out_params->stride >> 1, + pxp->base + HW_PXP_OUT_PITCH); + } else { + __raw_writel(0, pxp->base + HW_PXP_OUT_PITCH); + } + + /* set global alpha if necessary */ + if (out_params->global_alpha_enable) { + __raw_writel(out_params->global_alpha << 24, + pxp->base + HW_PXP_OUT_CTRL_SET); + __raw_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT, + pxp->base + HW_PXP_OUT_CTRL_SET); + } +} + +static void pxp_set_s0colorkey(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_PS_CLRKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_PS_CLRKEYHIGH); + } else { + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_PS_CLRKEYLOW); + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_PS_CLRKEYHIGH); + } +} + +static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no]; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_AS_CLRKEYLOW); + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_AS_CLRKEYHIGH); + } else { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_AS_CLRKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_AS_CLRKEYHIGH); + } +} + +static void pxp_set_oln(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + dma_addr_t phys_addr = olparams_data->paddr; + u32 pitch = olparams_data->stride ? olparams_data->stride : + olparams_data->width; + + __raw_writel(phys_addr, pxp->base + HW_PXP_AS_BUF); + + /* Fixme */ + if (olparams_data->width == 0 && olparams_data->height == 0) { + __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_AS_ULC); + __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_LRC); + } else { + __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_ULC); + __raw_writel(BF_PXP_OUT_AS_LRC_X(olparams_data->width - 1) | + BF_PXP_OUT_AS_LRC_Y(olparams_data->height - 1), + pxp->base + HW_PXP_OUT_AS_LRC); + } + + if ((olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) || + (olparams_data->pixel_fmt == PXP_PIX_FMT_XRGB32)) { + __raw_writel(pitch << 2, + pxp->base + HW_PXP_AS_PITCH); + } else if ((olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) || + (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB555)) { + __raw_writel(pitch << 1, + pxp->base + HW_PXP_AS_PITCH); + } else { + __raw_writel(0, pxp->base + HW_PXP_AS_PITCH); + } +} + +static void pxp_set_olparam(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + u32 olparam; + + olparam = BF_PXP_AS_CTRL_ALPHA(olparams_data->global_alpha); + if (olparams_data->pixel_fmt == PXP_PIX_FMT_XRGB32) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB888); + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__ARGB8888); + if (!olparams_data->combine_enable) { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs); + olparam |= 0x3 << 16; + } + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB565); + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB555) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB555); + } + + if (olparams_data->global_alpha_enable) { + if (olparams_data->global_override) { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__Override); + } else { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply); + } + if (olparams_data->alpha_invert) + olparam |= BM_PXP_AS_CTRL_ALPHA_INVERT; + } + if (olparams_data->color_key_enable) + olparam |= BM_PXP_AS_CTRL_ENABLE_COLORKEY; + + __raw_writel(olparam, pxp->base + HW_PXP_AS_CTRL); +} + +static void pxp_set_s0param(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + u32 s0param_ulc, s0param_lrc; + + /* contains the coordinate for the PS in the OUTPUT buffer. */ + if ((pxp_conf->s0_param).width == 0 && + (pxp_conf->s0_param).height == 0) { + __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_PS_ULC); + __raw_writel(0x0, pxp->base + HW_PXP_OUT_PS_LRC); + } else { + switch (proc_data->rotate) { + case 0: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(proc_data->drect.left); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.top); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1); + break; + case 90: + s0param_ulc = BF_PXP_OUT_PS_ULC_Y(out_params->width - (proc_data->drect.left + proc_data->drect.width)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_X(proc_data->drect.top); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1); + break; + case 180: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->width - (proc_data->drect.left + proc_data->drect.width)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(out_params->height - (proc_data->drect.top + proc_data->drect.height)); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1); + break; + case 270: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->height - (proc_data->drect.top + proc_data->drect.height)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.left); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1); + break; + default: + return; + } + __raw_writel(s0param_ulc, pxp->base + HW_PXP_OUT_PS_ULC); + __raw_writel(s0param_lrc, pxp->base + HW_PXP_OUT_PS_LRC); + } + + /* Since user apps always pass the rotated drect + * to this driver, we need to first swap the width + * and height which is used to calculate the scale + * factors later. + */ + if (proc_data->rotate == 90 || proc_data->rotate == 270) { + int temp; + temp = proc_data->drect.width; + proc_data->drect.width = proc_data->drect.height; + proc_data->drect.height = temp; + } +} + +/* crop behavior is re-designed in h/w. */ +static void pxp_set_s0crop(struct pxps *pxp) +{ + /* + * place-holder, it's implemented in other functions in this driver. + * Refer to "Clipping source images" section in RM for detail. + */ +} + +static int pxp_set_scaling(struct pxps *pxp) +{ + int ret = 0; + u32 xscale, yscale, s0scale; + u32 decx, decy, xdec = 0, ydec = 0; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + proc_data->scaling = 1; + + if (!proc_data->drect.width || !proc_data->drect.height) { + pr_err("Invalid drect width and height passed in\n"); + return -EINVAL; + } + + decx = proc_data->srect.width / proc_data->drect.width; + decy = proc_data->srect.height / proc_data->drect.height; + if (decx > 1) { + if (decx >= 2 && decx < 4) { + decx = 2; + xdec = 1; + } else if (decx >= 4 && decx < 8) { + decx = 4; + xdec = 2; + } else if (decx >= 8) { + decx = 8; + xdec = 3; + } + xscale = proc_data->srect.width * 0x1000 / + (proc_data->drect.width * decx); + } else { + if (!is_yuv(s0_params->pixel_fmt) || + (is_yuv(s0_params->pixel_fmt) == + is_yuv(out_params->pixel_fmt)) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) || + (s0_params->pixel_fmt == PXP_PIX_FMT_VUY444)) { + if ((proc_data->srect.width > 1) && + (proc_data->drect.width > 1)) + xscale = (proc_data->srect.width - 1) * 0x1000 / + (proc_data->drect.width - 1); + else + xscale = proc_data->srect.width * 0x1000 / + proc_data->drect.width; + } else { + if ((proc_data->srect.width > 2) && + (proc_data->drect.width > 1)) + xscale = (proc_data->srect.width - 2) * 0x1000 / + (proc_data->drect.width - 1); + else + xscale = proc_data->srect.width * 0x1000 / + proc_data->drect.width; + } + } + if (decy > 1) { + if (decy >= 2 && decy < 4) { + decy = 2; + ydec = 1; + } else if (decy >= 4 && decy < 8) { + decy = 4; + ydec = 2; + } else if (decy >= 8) { + decy = 8; + ydec = 3; + } + yscale = proc_data->srect.height * 0x1000 / + (proc_data->drect.height * decy); + } else { + if ((proc_data->srect.height > 1) && + (proc_data->drect.height > 1)) + yscale = (proc_data->srect.height - 1) * 0x1000 / + (proc_data->drect.height - 1); + else + yscale = proc_data->srect.height * 0x1000 / + proc_data->drect.height; + } + + __raw_writel((xdec << 10) | (ydec << 8), pxp->base + HW_PXP_PS_CTRL); + + if (xscale > PXP_DOWNSCALE_THRESHOLD) + xscale = PXP_DOWNSCALE_THRESHOLD; + if (yscale > PXP_DOWNSCALE_THRESHOLD) + yscale = PXP_DOWNSCALE_THRESHOLD; + s0scale = BF_PXP_PS_SCALE_YSCALE(yscale) | + BF_PXP_PS_SCALE_XSCALE(xscale); + __raw_writel(s0scale, pxp->base + HW_PXP_PS_SCALE); + + pxp_set_ctrl(pxp); + + return ret; +} + +static void pxp_set_bg(struct pxps *pxp) +{ + __raw_writel(pxp->pxp_conf_state.proc_data.bgcolor, + pxp->base + HW_PXP_PS_BACKGROUND); +} + +static void pxp_set_lut(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + int lut_op = pxp_conf->proc_data.lut_transform; + u32 reg_val; + int i; + bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false; + u8 *cmap = pxp_conf->proc_data.lut_map; + u32 entry_src; + u32 pix_val; + u8 entry[4]; + + /* + * If LUT already configured as needed, return... + * Unless CMAP is needed and it has been updated. + */ + if ((pxp->lut_state == lut_op) && + !(use_cmap && pxp_conf->proc_data.lut_map_updated)) + return; + + if (lut_op == PXP_LUT_NONE) { + __raw_writel(BM_PXP_LUT_CTRL_BYPASS, + pxp->base + HW_PXP_LUT_CTRL); + } else if (((lut_op & PXP_LUT_INVERT) != 0) + && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) { + /* Fill out LUT table with inverted monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0xFF : 0x00; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_INVERT) != 0) { + /* Fill out LUT table with 8-bit inverted values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = ~entry_src & 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) { + /* Fill out LUT table with 8-bit monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if (use_cmap) { + /* Fill out LUT table using colormap values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) + entry[i] = cmap[pix_val + i]; + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } + + pxp->lut_state = lut_op; +} + +static void pxp_set_csc(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + bool input_is_YUV = is_yuv(s0_params->pixel_fmt); + bool output_is_YUV = is_yuv(out_params->pixel_fmt); + + if (input_is_YUV && output_is_YUV) { + /* + * Input = YUV, Output = YUV + * No CSC unless we need to do combining + */ + if (ol_params->combine_enable) { + /* Must convert to RGB for combining with RGB overlay */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x04030000, pxp->base + HW_PXP_CSC1_COEF0); + __raw_writel(0x01230208, pxp->base + HW_PXP_CSC1_COEF1); + __raw_writel(0x076b079c, pxp->base + HW_PXP_CSC1_COEF2); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5); + } else { + /* Input & Output both YUV, so bypass both CSCs */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } + } else if (input_is_YUV && !output_is_YUV) { + /* + * Input = YUV, Output = RGB + * Use CSC1 to convert to RGB + */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x84ab01f0, pxp->base + HW_PXP_CSC1_COEF0); + __raw_writel(0x01980204, pxp->base + HW_PXP_CSC1_COEF1); + __raw_writel(0x0730079c, pxp->base + HW_PXP_CSC1_COEF2); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } else if (!input_is_YUV && output_is_YUV) { + /* + * Input = RGB, Output = YUV + * Use CSC2 to convert to YUV + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5); + } else { + /* + * Input = RGB, Output = RGB + * Input & Output both RGB, so bypass both CSCs + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } + + /* YCrCb colorspace */ + /* Not sure when we use this...no YCrCb formats are defined for PxP */ + /* + __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR); + __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR); + __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR); + */ + +} + +static void pxp_set_s0buf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + dma_addr_t Y, U, V; + dma_addr_t Y1, U1, V1; + u32 offset, bpp = 1; + u32 pitch = s0_params->stride ? s0_params->stride : + s0_params->width; + + Y = s0_params->paddr; + + if ((s0_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (s0_params->pixel_fmt == PXP_PIX_FMT_RGB555)) + bpp = 2; + else if (s0_params->pixel_fmt == PXP_PIX_FMT_XRGB32) + bpp = 4; + offset = (proc_data->srect.top * s0_params->width + + proc_data->srect.left) * bpp; + /* clipping or cropping */ + Y1 = Y + offset; + __raw_writel(Y1, pxp->base + HW_PXP_PS_BUF); + if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) || + (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P)) { + /* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */ + int s = 2; + if (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) + s = 1; + + offset = proc_data->srect.top * s0_params->width / 4 + + proc_data->srect.left / 2; + U = Y + (s0_params->width * s0_params->height); + U1 = U + offset; + V = U + ((s0_params->width * s0_params->height) >> s); + V1 = V + offset; + if (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) { + __raw_writel(V1, pxp->base + HW_PXP_PS_UBUF); + __raw_writel(U1, pxp->base + HW_PXP_PS_VBUF); + } else { + __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF); + __raw_writel(V1, pxp->base + HW_PXP_PS_VBUF); + } + } else if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV12) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV21) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) { + int s = 2; + if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) + s = 1; + + offset = (proc_data->srect.top * s0_params->width + + proc_data->srect.left) / s; + U = Y + (s0_params->width * s0_params->height); + U1 = U + offset; + + __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF); + } + + /* TODO: only support RGB565, Y8, Y4, YUV420 */ + if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY || + s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P || + s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P || + s0_params->pixel_fmt == PXP_PIX_FMT_NV12 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV21 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV16 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV61 || + s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) { + __raw_writel(pitch, pxp->base + HW_PXP_PS_PITCH); + } + else if (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) + __raw_writel(pitch >> 1, + pxp->base + HW_PXP_PS_PITCH); + else if (s0_params->pixel_fmt == PXP_PIX_FMT_XRGB32 || + s0_params->pixel_fmt == PXP_PIX_FMT_VUY444) + __raw_writel(pitch << 2, + pxp->base + HW_PXP_PS_PITCH); + else if (s0_params->pixel_fmt == PXP_PIX_FMT_UYVY || + s0_params->pixel_fmt == PXP_PIX_FMT_YUYV || + s0_params->pixel_fmt == PXP_PIX_FMT_VYUY || + s0_params->pixel_fmt == PXP_PIX_FMT_YVYU) + __raw_writel(pitch << 1, + pxp->base + HW_PXP_PS_PITCH); + else if ((s0_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (s0_params->pixel_fmt == PXP_PIX_FMT_RGB555)) + __raw_writel(pitch << 1, + pxp->base + HW_PXP_PS_PITCH); + else + __raw_writel(0, pxp->base + HW_PXP_PS_PITCH); +} + +/** + * pxp_config() - configure PxP for a processing task + * @pxps: PXP context. + * @pxp_chan: PXP channel. + * @return: 0 on success or negative error code on failure. + */ +static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) +{ + /* Configure PxP regs */ + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + pxp_set_s0colorkey(pxp); + + pxp_set_oln(0, pxp); + pxp_set_olparam(0, pxp); + pxp_set_olcolorkey(0, pxp); + + pxp_set_csc(pxp); + pxp_set_bg(pxp); + pxp_set_lut(pxp); + + pxp_set_s0buf(pxp); + pxp_set_outbuf(pxp); + + return 0; +} + +static void pxp_clk_enable(struct pxps *pxp) +{ + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_ON) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + pm_runtime_get_sync(pxp->dev); + + if (pxp->clk_disp_axi) + clk_prepare_enable(pxp->clk_disp_axi); + clk_prepare_enable(pxp->clk); + pxp->clk_stat = CLK_STAT_ON; + + mutex_unlock(&pxp->clk_mutex); +} + +static void pxp_clk_disable(struct pxps *pxp) +{ + unsigned long flags; + + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_OFF) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + spin_lock_irqsave(&pxp->lock, flags); + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) { + spin_unlock_irqrestore(&pxp->lock, flags); + clk_disable_unprepare(pxp->clk); + if (pxp->clk_disp_axi) + clk_disable_unprepare(pxp->clk_disp_axi); + pxp->clk_stat = CLK_STAT_OFF; + pm_runtime_put_sync_suspend(pxp->dev); + } else + spin_unlock_irqrestore(&pxp->lock, flags); + + mutex_unlock(&pxp->clk_mutex); +} + +static inline void clkoff_callback(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + + pxp_clk_disable(pxp); +} + +static void pxp_clkoff_timer(struct timer_list *t) +{ + struct pxps *pxp = from_timer(pxp, t, clk_timer); + + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) + schedule_work(&pxp->work); + else + mod_timer(&pxp->clk_timer, + jiffies + msecs_to_jiffies(timeout_in_ms)); +} + +static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); +} + +/* called with pxp_chan->lock held */ +static void __pxpdma_dostart(struct pxp_channel *pxp_chan) +{ + struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child; + int i = 0; + + memset(&pxp->pxp_conf_state.s0_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.out_param, 0, sizeof(struct pxp_layer_param)); + memset(pxp->pxp_conf_state.ol_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.proc_data, 0, sizeof(struct pxp_proc_data)); + /* S0 */ + desc = list_first_entry(&head, struct pxp_tx_desc, list); + memcpy(&pxp->pxp_conf_state.s0_param, + &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); + memcpy(&pxp->pxp_conf_state.proc_data, + &desc->proc_data, sizeof(struct pxp_proc_data)); + + /* Save PxP configuration */ + list_for_each_entry(child, &desc->tx_list, list) { + if (i == 0) { /* Output */ + memcpy(&pxp->pxp_conf_state.out_param, + &child->layer_param.out_param, + sizeof(struct pxp_layer_param)); + } else { /* Overlay */ + memcpy(&pxp->pxp_conf_state.ol_param[i - 1], + &child->layer_param.ol_param, + sizeof(struct pxp_layer_param)); + } + + i++; + } + pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.s0_param.width, + pxp->pxp_conf_state.s0_param.height, + pxp->pxp_conf_state.s0_param.paddr); + pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.out_param.width, + pxp->pxp_conf_state.out_param.height, + pxp->pxp_conf_state.out_param.paddr); +} + +static void pxpdma_dostart_work(struct pxps *pxp) +{ + struct pxp_channel *pxp_chan = NULL; + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + spin_lock_irqsave(&pxp->lock, flags); + + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + __pxpdma_dostart(pxp_chan); + + /* Configure PxP */ + pxp_config(pxp, pxp_chan); + + pxp_start(pxp); + + spin_unlock_irqrestore(&pxp->lock, flags); +} + +static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct pxps *pxp) +{ + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + do { + desc = pxpdma_first_queued(pxp_chan); + spin_lock_irqsave(&pxp->lock, flags); + list_move_tail(&desc->list, &head); + spin_unlock_irqrestore(&pxp->lock, flags); + } while (!list_empty(&pxp_chan->queue)); +} + +static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct pxp_tx_desc *desc = to_tx_desc(tx); + struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); + dma_cookie_t cookie; + + dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); + + /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ + spin_lock(&pxp_chan->lock); + + cookie = pxp_chan->dma_chan.cookie; + + if (++cookie < 0) + cookie = 1; + + /* from dmaengine.h: "last cookie value returned to client" */ + pxp_chan->dma_chan.cookie = cookie; + tx->cookie = cookie; + + /* Here we add the tx descriptor to our PxP task queue. */ + list_add_tail(&desc->list, &pxp_chan->queue); + + spin_unlock(&pxp_chan->lock); + + dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); + + return cookie; +} + +/** + * pxp_init_channel() - initialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_init_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + int ret = 0; + + /* + * We are using _virtual_ channel here. + * Each channel contains all parameters of corresponding layers + * for one transaction; each layer is represented as one descriptor + * (i.e., pxp_tx_desc) here. + */ + + INIT_LIST_HEAD(&pxp_chan->queue); + + return ret; +} + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = dev_id; + struct pxp_channel *pxp_chan; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child, *_child; + dma_async_tx_callback callback; + void *callback_param; + unsigned long flags; + u32 hist_status; + + dump_pxp_reg(pxp); + + hist_status = + __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS; + + __raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR); + + /* set the SFTRST bit to be 1 to reset + * the PXP block to its default state. + */ + pxp_soft_reset(pxp); + + spin_lock_irqsave(&pxp->lock, flags); + + if (list_empty(&head)) { + pxp->pxp_ongoing = 0; + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + /* Get descriptor and call callback */ + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + pxp_chan->completed = desc->txd.cookie; + + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + /* Send histogram status back to caller */ + desc->hist_status = hist_status; + + if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) + callback(callback_param); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + complete(&pxp->complete); + pxp->pxp_ongoing = 0; + mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms)); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +/* allocate/free dma tx descriptor dynamically*/ +static struct pxp_tx_desc *pxpdma_desc_alloc(struct pxp_channel *pxp_chan) +{ + struct pxp_tx_desc *desc = NULL; + struct dma_async_tx_descriptor *txd = NULL; + + desc = kmem_cache_alloc(tx_desc_cache, GFP_KERNEL | __GFP_ZERO); + if (desc == NULL) + return NULL; + + INIT_LIST_HEAD(&desc->list); + INIT_LIST_HEAD(&desc->tx_list); + txd = &desc->txd; + dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); + txd->tx_submit = pxp_tx_submit; + + return desc; +} + +/* Allocate and initialise a transfer descriptor. */ +static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, + struct scatterlist + *sgl, + unsigned int sg_len, + enum + dma_transfer_direction + direction, + unsigned long tx_flags, + void *context) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *pos = NULL, *next = NULL; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *first = NULL, *prev = NULL; + struct scatterlist *sg; + dma_addr_t phys_addr; + int i; + + if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) { + dev_err(chan->device->dev, "Invalid DMA direction %d!\n", + direction); + return NULL; + } + + if (unlikely(sg_len < 2)) + return NULL; + + for_each_sg(sgl, sg, sg_len, i) { + desc = pxpdma_desc_alloc(pxp_chan); + if (!desc) { + dev_err(chan->device->dev, "no enough memory to allocate tx descriptor\n"); + + if (first) { + list_for_each_entry_safe(pos, next, &first->tx_list, list) { + list_del_init(&pos->list); + kmem_cache_free(tx_desc_cache, (void*)pos); + } + list_del_init(&first->list); + kmem_cache_free(tx_desc_cache, (void*)first); + } + + return NULL; + } + + phys_addr = sg_dma_address(sg); + + if (!first) { + first = desc; + + desc->layer_param.s0_param.paddr = phys_addr; + } else { + list_add_tail(&desc->list, &first->tx_list); + prev->next = desc; + desc->next = NULL; + + if (i == 1) + desc->layer_param.out_param.paddr = phys_addr; + else + desc->layer_param.ol_param.paddr = phys_addr; + } + + prev = desc; + } + + pxp->pxp_conf_state.layer_nr = sg_len; + first->txd.flags = tx_flags; + first->len = sg_len; + pr_debug("%s:%d first %p, first->len %d, flags %08x\n", + __func__, __LINE__, first, first->len, first->txd.flags); + + return &first->txd; +} + +static void pxp_issue_pending(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + + spin_lock(&pxp_chan->lock); + + if (list_empty(&pxp_chan->queue)) { + spin_unlock(&pxp_chan->lock); + return; + } + + pxpdma_dequeue(pxp_chan, pxp); + pxp_chan->status = PXP_CHANNEL_READY; + + spin_unlock(&pxp_chan->lock); + + pxp_clk_enable(pxp); + wake_up_interruptible(&pxp->thread_waitq); +} + +static void __pxp_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; +} + +static int pxp_device_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + __pxp_terminate_all(chan); + spin_unlock(&pxp_chan->lock); + + return 0; +} + +static int pxp_alloc_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + int ret; + + /* dmaengine.c now guarantees to only offer free channels */ + BUG_ON(chan->client_count > 1); + WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); + + chan->cookie = 1; + pxp_chan->completed = -ENXIO; + + pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); + ret = pxp_init_channel(pxp_dma, pxp_chan); + if (ret < 0) + goto err_chan; + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", + chan->chan_id, pxp_chan->eof_irq); + + return ret; + +err_chan: + return ret; +} + +static void pxp_free_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + + __pxp_terminate_all(chan); + + pxp_chan->status = PXP_CHANNEL_FREE; + + spin_unlock(&pxp_chan->lock); +} + +static enum dma_status pxp_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + if (cookie != chan->cookie) + return DMA_ERROR; + + if (txstate) { + txstate->last = pxp_chan->completed; + txstate->used = chan->cookie; + txstate->residue = 0; + } + return DMA_COMPLETE; +} + +static int pxp_dma_init(struct pxps *pxp) +{ + struct pxp_dma *pxp_dma = &pxp->pxp_dma; + struct dma_device *dma = &pxp_dma->dma; + int i; + + dma_cap_set(DMA_SLAVE, dma->cap_mask); + dma_cap_set(DMA_PRIVATE, dma->cap_mask); + + /* Compulsory common fields */ + dma->dev = pxp->dev; + dma->device_alloc_chan_resources = pxp_alloc_chan_resources; + dma->device_free_chan_resources = pxp_free_chan_resources; + dma->device_tx_status = pxp_tx_status; + dma->device_issue_pending = pxp_issue_pending; + + /* Compulsory for DMA_SLAVE fields */ + dma->device_prep_slave_sg = pxp_prep_slave_sg; + dma->device_terminate_all = pxp_device_terminate_all; + + /* Initialize PxP Channels */ + INIT_LIST_HEAD(&dma->channels); + for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { + struct pxp_channel *pxp_chan = pxp->channel + i; + struct dma_chan *dma_chan = &pxp_chan->dma_chan; + + spin_lock_init(&pxp_chan->lock); + + /* Only one EOF IRQ for PxP, shared by all channels */ + pxp_chan->eof_irq = pxp->irq; + pxp_chan->status = PXP_CHANNEL_FREE; + pxp_chan->completed = -ENXIO; + snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), + "PXP EOF %d", i); + + dma_chan->device = &pxp_dma->dma; + dma_chan->cookie = 1; + dma_chan->chan_id = i; + list_add_tail(&dma_chan->device_node, &dma->channels); + } + + return dma_async_device_register(&pxp_dma->dma); +} + +static ssize_t clk_off_timeout_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", timeout_in_ms); +} + +static ssize_t clk_off_timeout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int val; + if (sscanf(buf, "%d", &val) > 0) { + timeout_in_ms = val; + return count; + } + return -EINVAL; +} + +static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show, + clk_off_timeout_store); + +static ssize_t block_size_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", block_size); +} + +static ssize_t block_size_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char **last = NULL; + + block_size = simple_strtoul(buf, last, 0); + if (block_size > 1) + block_size = 1; + + return count; +} +static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO, + block_size_show, block_size_store); + +static const struct of_device_id imx_pxpdma_dt_ids[] = { + { .compatible = "fsl,imx6dl-pxp-dma", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids); + +static int has_pending_task(struct pxps *pxp, struct pxp_channel *task) +{ + int found; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + found = !list_empty(&head); + spin_unlock_irqrestore(&pxp->lock, flags); + + return found; +} + +static int pxp_dispatch_thread(void *argv) +{ + struct pxps *pxp = (struct pxps *)argv; + struct pxp_channel *pending = NULL; + unsigned long flags; + + set_freezable(); + + while (!kthread_should_stop()) { + int ret; + ret = wait_event_freezable(pxp->thread_waitq, + has_pending_task(pxp, pending) || + kthread_should_stop()); + if (ret < 0) + continue; + + if (kthread_should_stop()) + break; + + spin_lock_irqsave(&pxp->lock, flags); + pxp->pxp_ongoing = 1; + spin_unlock_irqrestore(&pxp->lock, flags); + init_completion(&pxp->complete); + pxpdma_dostart_work(pxp); + ret = wait_for_completion_timeout(&pxp->complete, 2 * HZ); + if (ret == 0) { + printk(KERN_EMERG "%s: task is timeout\n\n", __func__); + break; + } + } + + return 0; +} + +static int pxp_probe(struct platform_device *pdev) +{ + struct pxps *pxp; + struct resource *res; + int irq; + int err = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0); + if (!res || irq < 0) { + err = -ENODEV; + goto exit; + } + + pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + pxp->dev = &pdev->dev; + + platform_set_drvdata(pdev, pxp); + pxp->irq = irq; + + spin_lock_init(&pxp->lock); + mutex_init(&pxp->clk_mutex); + + pxp->base = devm_ioremap_resource(&pdev->dev, res); + if (pxp->base == NULL) { + dev_err(&pdev->dev, "Couldn't ioremap regs\n"); + err = -ENODEV; + goto exit; + } + + pxp->pdev = pdev; + + pxp->clk_disp_axi = devm_clk_get(&pdev->dev, "disp-axi"); + if (IS_ERR(pxp->clk_disp_axi)) + pxp->clk_disp_axi = NULL; + pxp->clk = devm_clk_get(&pdev->dev, "pxp-axi"); + + err = devm_request_irq(&pdev->dev, pxp->irq, pxp_irq, 0, + "pxp-dmaengine", pxp); + if (err) + goto exit; + /* Initialize DMA engine */ + err = pxp_dma_init(pxp); + if (err < 0) + goto exit; + + if (device_create_file(&pdev->dev, &dev_attr_clk_off_timeout)) { + dev_err(&pdev->dev, + "Unable to create file from clk_off_timeout\n"); + goto exit; + } + + device_create_file(&pdev->dev, &dev_attr_block_size); + pxp_clk_enable(pxp); + dump_pxp_reg(pxp); + pxp_clk_disable(pxp); + + INIT_WORK(&pxp->work, clkoff_callback); + timer_setup(&pxp->clk_timer, pxp_clkoff_timer, 0); + + init_waitqueue_head(&pxp->thread_waitq); + /* allocate a kernel thread to dispatch pxp conf */ + pxp->dispatch = kthread_run(pxp_dispatch_thread, pxp, "pxp_dispatch"); + if (IS_ERR(pxp->dispatch)) { + err = PTR_ERR(pxp->dispatch); + goto exit; + } + tx_desc_cache = kmem_cache_create("tx_desc", sizeof(struct pxp_tx_desc), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!tx_desc_cache) { + err = -ENOMEM; + goto exit; + } + + register_pxp_device(); + + pm_runtime_enable(pxp->dev); + +exit: + if (err) + dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n"); + return err; +} + +static int pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + unregister_pxp_device(); + kmem_cache_destroy(tx_desc_cache); + kthread_stop(pxp->dispatch); + cancel_work_sync(&pxp->work); + del_timer_sync(&pxp->clk_timer); + clk_disable_unprepare(pxp->clk); + if (pxp->clk_disp_axi) + clk_disable_unprepare(pxp->clk_disp_axi); + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + device_remove_file(&pdev->dev, &dev_attr_block_size); + dma_async_device_unregister(&(pxp->pxp_dma.dma)); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pxp_suspend(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} + +static int pxp_resume(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + /* Pull PxP out of reset */ + __raw_writel(0, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +#ifdef CONFIG_PM +static int pxp_runtime_suspend(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high release.\n"); + return 0; +} + +static int pxp_runtime_resume(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high request.\n"); + return 0; +} +#else +#define pxp_runtime_suspend NULL +#define pxp_runtime_resume NULL +#endif + +static const struct dev_pm_ops pxp_pm_ops = { + SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume) +}; + +static struct platform_driver pxp_driver = { + .driver = { + .name = "imx-pxp", + .of_match_table = of_match_ptr(imx_pxpdma_dt_ids), + .pm = &pxp_pm_ops, + }, + .probe = pxp_probe, + .remove = pxp_remove, +}; + +module_platform_driver(pxp_driver); + + +MODULE_DESCRIPTION("i.MX PxP driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/pxp/pxp_dma_v3.c linux-imx-phytec/drivers/dma/pxp/pxp_dma_v3.c --- linux-6.1.55/drivers/dma/pxp/pxp_dma_v3.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/dma/pxp/pxp_dma_v3.c 2024-06-19 12:33:59.836218832 +0200 @@ -0,0 +1,8352 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * + * Copyright 2017-2019 NXP + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regs-pxp_v3.h" +#include "reg_bitfields.h" + +#ifdef CONFIG_MXC_FPGA_M4_TEST +#include "cm4_image.c" +#define FPGA_TCML_ADDR 0x0C7F8000 +#define PINCTRL 0x0C018000 +#define PIN_DOUT 0x700 +void __iomem *fpga_tcml_base; +void __iomem *pinctrl_base; +#endif + +#define PXP_FILL_TIMEOUT 3000 +#define busy_wait(cond) \ + ({ \ + unsigned long end_jiffies = jiffies + \ + msecs_to_jiffies(PXP_FILL_TIMEOUT); \ + bool succeeded = false; \ + do { \ + if (cond) { \ + succeeded = true; \ + break; \ + } \ + cpu_relax(); \ + } while (time_after(end_jiffies, jiffies)); \ + succeeded; \ + }) + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +#define CONFIG_FB_MXC_EINK_FPGA + +/* define all the pxp 2d nodes */ +#define PXP_2D_PS 0 +#define PXP_2D_AS 1 +#define PXP_2D_INPUT_FETCH0 2 +#define PXP_2D_INPUT_FETCH1 3 +#define PXP_2D_CSC1 4 +#define PXP_2D_ROTATION1 5 +#define PXP_2D_ALPHA0_S0 6 +#define PXP_2D_ALPHA0_S1 7 +#define PXP_2D_ALPHA1_S0 8 +#define PXP_2D_ALPHA1_S1 9 +#define PXP_2D_CSC2 10 +#define PXP_2D_LUT 11 +#define PXP_2D_ROTATION0 12 +#define PXP_2D_OUT 13 +#define PXP_2D_INPUT_STORE0 14 +#define PXP_2D_INPUT_STORE1 15 +#define PXP_2D_NUM 16 + +#define PXP_2D_ALPHA0_S0_S1 0xaa +#define PXP_2D_ALPHA1_S0_S1 0xbb + +#define PXP_2D_MUX_BASE 50 +#define PXP_2D_MUX_MUX0 (PXP_2D_MUX_BASE + 0) +#define PXP_2D_MUX_MUX1 (PXP_2D_MUX_BASE + 1) +#define PXP_2D_MUX_MUX2 (PXP_2D_MUX_BASE + 2) +#define PXP_2D_MUX_MUX3 (PXP_2D_MUX_BASE + 3) +#define PXP_2D_MUX_MUX4 (PXP_2D_MUX_BASE + 4) +#define PXP_2D_MUX_MUX5 (PXP_2D_MUX_BASE + 5) +#define PXP_2D_MUX_MUX6 (PXP_2D_MUX_BASE + 6) +#define PXP_2D_MUX_MUX7 (PXP_2D_MUX_BASE + 7) +#define PXP_2D_MUX_MUX8 (PXP_2D_MUX_BASE + 8) +#define PXP_2D_MUX_MUX9 (PXP_2D_MUX_BASE + 9) +#define PXP_2D_MUX_MUX10 (PXP_2D_MUX_BASE + 10) +#define PXP_2D_MUX_MUX11 (PXP_2D_MUX_BASE + 11) +#define PXP_2D_MUX_MUX12 (PXP_2D_MUX_BASE + 12) +#define PXP_2D_MUX_MUX13 (PXP_2D_MUX_BASE + 13) +#define PXP_2D_MUX_MUX14 (PXP_2D_MUX_BASE + 14) +#define PXP_2D_MUX_MUX15 (PXP_2D_MUX_BASE + 15) + +/* define pxp 2d node types */ +#define PXP_2D_TYPE_INPUT 1 +#define PXP_2D_TYPE_ALU 2 +#define PXP_2D_TYPE_OUTPUT 3 + +#define DISTANCE_INFINITY 0xffff +#define NO_PATH_NODE 0xffffffff + +#define PXP_MAX_INPUT_NUM 2 +#define PXP_MAX_OUTPUT_NUM 2 + +#define FETCH_NOOP 0x01 +#define FETCH_EXPAND 0x02 +#define FETCH_SHIFT 0x04 + +#define STORE_NOOP 0x01 +#define STORE_SHIFT 0x02 +#define STORE_SHRINK 0x04 + +#define NEED_YUV_SWAP 0x02 + +#define IN_NEED_COMPOSITE (0x01 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_CSC (0x02 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_SCALE (0x04 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_ROTATE_FLIP (0x08 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_FMT_UNIFIED 0x10 +#define IN_NEED_SHIFT 0x20 +#define IN_NEED_LUT (0x40 | IN_NEED_UNIFIED) + +#define OUT_NEED_SHRINK 0x100 +#define OUT_NEED_SHIFT 0x200 + +#define PXP_ROTATE_0 0 +#define PXP_ROTATE_90 1 +#define PXP_ROTATE_180 2 +#define PXP_ROTATE_270 3 + +#define PXP_H_FLIP 1 +#define PXP_V_FLIP 2 + +#define PXP_OP_TYPE_2D 0x001 +#define PXP_OP_TYPE_DITHER 0x002 +#define PXP_OP_TYPE_WFE_A 0x004 +#define PXP_OP_TYPE_WFE_B 0x008 + +/* define store engine output mode */ +#define STORE_MODE_NORMAL 1 +#define STORE_MODE_BYPASS 2 +#define STORE_MODE_DUAL 3 +#define STORE_MODE_HANDSHAKE 4 + +/* define fetch engine input mode */ +#define FETCH_MODE_NORMAL 1 +#define FETCH_MODE_BYPASS 2 +#define FETCH_MODE_HANDSHAKE 3 + +#define COMMON_FMT_BPP 32 + +#define R_COMP 0 +#define G_COMP 1 +#define B_COMP 2 +#define A_COMP 3 + +#define Y_COMP 0 +#define U_COMP 1 +#define V_COMP 2 +#define Y1_COMP 4 + +static LIST_HEAD(head); +static int timeout_in_ms = 600; +static unsigned int block_size; +static struct kmem_cache *tx_desc_cache; +static struct kmem_cache *edge_node_cache; +static struct pxp_collision_info col_info; +static bool v3p_flag; +static int alpha_blending_version; +static bool pxp_legacy; + +struct pxp_dma { + struct dma_device dma; +}; + +enum pxp_alpha_blending_version { + PXP_ALPHA_BLENDING_NONE = 0x0, + PXP_ALPHA_BLENDING_V1 = 0x1, + PXP_ALPHA_BLENDING_V2 = 0x2, +}; + +struct pxp_alpha_global { + unsigned int color_key_enable; + bool combine_enable; + bool global_alpha_enable; + bool global_override; + bool alpha_invert; + bool local_alpha_enable; + unsigned char global_alpha; + int comp_mask; +}; + +struct rectangle { + uint16_t x; + uint16_t y; + uint16_t width; + uint16_t height; +}; + +struct pxp_alpha_info { + uint8_t alpha_mode; + uint8_t rop_type; + + struct pxp_alpha s0_alpha; + struct pxp_alpha s1_alpha; +}; + +struct pxp_op_info{ + uint16_t op_type; + uint16_t rotation; + uint8_t flip; + uint8_t fill_en; + uint32_t fill_data; + uint8_t alpha_blending; + struct pxp_alpha_info alpha_info; + + /* Dithering specific data */ + uint32_t dither_mode; + uint32_t quant_bit; + + /* + * partial: + * 0 - full update + * 1 - partial update + * alpha_en: + * 0 - upd is {Y4[3:0],4'b0000} format + * 1 - upd is {Y4[3:0],3'b000,alpha} format + * reagl_en: + * 0 - use normal waveform algorithm + * 1 - enable reagl/-d waveform algorithm + * detection_only: + * 0 - write working buffer + * 1 - do no write working buffer, detection only + * lut: + * valid value 0-63 + * set to the lut used for next update + */ + bool partial_update; + bool alpha_en; + bool lut_update; + bool reagl_en; /* enable reagl/-d */ + bool reagl_d_en; /* enable reagl or reagl-d */ + bool detection_only; + int lut; + uint32_t lut_status_1; + uint32_t lut_status_2; +}; + +struct pxp_pixmap { + uint8_t channel_id; + uint8_t bpp; + int32_t pitch; + uint16_t width; + uint16_t height; + struct rectangle crop; + uint32_t rotate; + uint8_t flip; + uint32_t format; /* fourcc pixmap format */ + uint32_t flags; + bool valid; + dma_addr_t paddr; + dma_addr_t paddr_u; + dma_addr_t paddr_v; + struct pxp_alpha_global g_alpha; +}; + +struct pxp_task_info { + uint8_t input_num; + uint8_t output_num; + struct pxp_pixmap input[PXP_MAX_INPUT_NUM]; + struct pxp_pixmap output[PXP_MAX_OUTPUT_NUM]; + struct pxp_op_info op_info; + uint32_t pxp_2d_flags; +}; + +struct pxps { + struct platform_device *pdev; + struct clk *ipg_clk; + struct clk *axi_clk; + void __iomem *base; + int irq; /* PXP IRQ to the CPU */ + + spinlock_t lock; + struct mutex clk_mutex; + int clk_stat; +#define CLK_STAT_OFF 0 +#define CLK_STAT_ON 1 + int pxp_ongoing; + int lut_state; + + struct device *dev; + struct pxp_dma pxp_dma; + struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; + struct work_struct work; + + const struct pxp_devdata *devdata; + struct pxp_task_info task; + + /* describes most recent processing configuration */ + struct pxp_config_data pxp_conf_state; + + /* to turn clock off when pxp is inactive */ + struct timer_list clk_timer; + + /* for pxp config dispatch asynchronously*/ + struct task_struct *dispatch; + wait_queue_head_t thread_waitq; + struct completion complete; + + struct regmap *gpr; +}; + +#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) +#define to_pxp(id) container_of(id, struct pxps, pxp_dma) + +#define to_pxp_task_info(op) container_of((op), struct pxp_task_info, op_info) +#define to_pxp_from_task(task) container_of((task), struct pxps, task) + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +static uint8_t active_bpp(uint8_t bpp) +{ + switch(bpp) { + case 8: + return 0x0; + case 16: + return 0x1; + case 32: + return 0x2; + case 64: + return 0x3; + default: + return 0xff; + } +} + +static uint8_t rotate_map(uint32_t degree) +{ + switch (degree) { + case 0: + return PXP_ROTATE_0; + case 90: + return PXP_ROTATE_90; + case 180: + return PXP_ROTATE_180; + case 270: + return PXP_ROTATE_270; + default: + return 0; + } +} + +static uint8_t expand_format(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_BGR565: + return 0x0; + case PXP_PIX_FMT_RGB555: + return 0x1; + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_YVYU: + return 0x5; + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + return 0x6; + case PXP_PIX_FMT_NV16: + return 0x7; + default: + return 0xff; + } +} + +struct color_component { + uint8_t id; + uint8_t offset; + uint8_t length; + uint8_t mask; +}; + +struct color { + uint32_t format; + struct color_component comp[4]; +}; + +struct color rgb_colors[] = { + { + .format = PXP_PIX_FMT_RGB565, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 6, .mask = 0x3f, }, + { .id = R_COMP, .offset = 11, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_BGR565, + .comp = { + { .id = R_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 6, .mask = 0x3f, }, + { .id = B_COMP, .offset = 11, .length = 6, .mask = 0x3f, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_RGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA555, + .comp = { + { .id = A_COMP, .offset = 0, .length = 1, .mask = 0x1, }, + { .id = B_COMP, .offset = 1, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 6, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 11, .length = 5, .mask = 0x1f, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB444, + .comp = { + { .id = B_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = A_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB444, + .comp = { + { .id = B_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = A_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA444, + .comp = { + { .id = A_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = B_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_RGB24, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_BGR24, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB32, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_RGBX32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_XBGR32, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_BGRX32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB32, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_ABGR32, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_BGRA32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, +}; + +/* only one plane yuv formats */ +struct color yuv_colors[] = { + { + .format = PXP_PIX_FMT_GREY, + .comp = { + { .id = Y_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 0, .mask = 0x00, }, + { .id = V_COMP, .offset = 16, .length = 0, .mask = 0x00, }, + { .id = A_COMP, .offset = 24, .length = 0, .mask = 0x00, }, + }, + }, { + .format = PXP_PIX_FMT_YUYV, + .comp = { + { .id = V_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = Y1_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_UYVY, + .comp = { + { .id = Y1_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YVYU, + .comp = { + { .id = U_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = Y1_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_VYUY, + .comp = { + { .id = Y1_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YUV444, + .comp = { + { .id = V_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YVU444, + .comp = { + { .id = U_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, +}; + +/* 4 to 1 mux */ +struct mux { + uint32_t id; + uint8_t mux_inputs[4]; + uint8_t mux_outputs[2]; +}; + +/* Adjacent list structure */ +struct edge_node { + uint32_t adjvex; + uint32_t prev_vnode; + struct edge_node *next; + unsigned long mux_used; + struct mux_config muxes; +}; + +struct vetex_node { + uint8_t type; + struct edge_node *first; +}; + +struct path_node { + struct list_head node; + uint32_t id; + uint32_t distance; + uint32_t prev_node; +}; + +static struct vetex_node adj_list[PXP_2D_NUM]; +static struct path_node path_table[PXP_2D_NUM][PXP_2D_NUM]; + +static bool adj_array_v3[PXP_2D_NUM][PXP_2D_NUM] = { + /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ + {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 0 */ + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1 */ + {0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0}, /* 2 */ + {0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1}, /* 3 */ + {0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 4 */ + {0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0}, /* 5 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 6 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 7 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0}, /* 8 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0}, /* 9 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0}, /* 10 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0}, /* 11 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0}, /* 12 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 13 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 14 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 15 */ +}; + + +static struct mux muxes_v3[16] = { + { + /* mux0 */ + .id = 0, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_INPUT_FETCH0, PXP_2D_INPUT_FETCH1, 0xff}, + .mux_outputs = {PXP_2D_ROTATION1, 0xff}, + }, { + /* mux1 */ + .id = 1, + .mux_inputs = {PXP_2D_INPUT_FETCH0, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA1_S1, PXP_2D_MUX_MUX5}, + }, { + /* mux2 */ + .id = 2, + .mux_inputs = {PXP_2D_INPUT_FETCH1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA1_S0, 0xff}, + }, { + /* mux3 */ + .id = 3, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA0_S0, 0xff}, + }, { + /* mux4 is not used in ULT1 */ + .id = 4, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux5 */ + .id = 5, + .mux_inputs = {PXP_2D_MUX_MUX1, PXP_2D_ALPHA1_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX7, 0xff}, + }, { + /* mux6 */ + .id = 6, + .mux_inputs = {PXP_2D_ALPHA1_S0_S1, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_CSC2, 0xff}, + }, { + /* mux7 */ + .id = 7, + .mux_inputs = {PXP_2D_MUX_MUX5, PXP_2D_CSC2, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX10}, + }, { + /* mux8 */ + .id = 8, + .mux_inputs = {PXP_2D_CSC2, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX11}, + }, { + /* mux9 */ + .id = 9, + .mux_inputs = {PXP_2D_MUX_MUX7, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_LUT, 0xff}, + }, { + /* mux10 */ + .id = 10, + .mux_inputs = {PXP_2D_MUX_MUX7, PXP_2D_LUT, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_MUX_MUX15}, + }, { + /* mux11 */ + .id = 11, + .mux_inputs = {PXP_2D_LUT, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_MUX_MUX14}, + }, { + /* mux12 */ + .id = 12, + .mux_inputs = {PXP_2D_MUX_MUX10, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ROTATION0, 0xff}, + }, { + /* mux13 */ + .id = 13, + .mux_inputs = {PXP_2D_INPUT_FETCH1, 0xff, 0xff, 0xff}, + .mux_outputs = {PXP_2D_INPUT_STORE1, 0xff}, + }, { + /* mux14 */ + .id = 14, + .mux_inputs = {PXP_2D_ROTATION0, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_OUT, 0xff}, + }, { + /* mux15 */ + .id = 15, + .mux_inputs = {PXP_2D_INPUT_FETCH0, PXP_2D_MUX_MUX10, 0xff, 0xff}, + .mux_outputs = {PXP_2D_INPUT_STORE0, 0xff}, + }, +}; + +static bool adj_array_v3p[PXP_2D_NUM][PXP_2D_NUM] = { + /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ + {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 0 */ + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 3 */ + {0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 4 */ + {0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 5 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 6 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 7 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 8 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 9 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0}, /* 10 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0}, /* 11 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0}, /* 12 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 13 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 14 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 15 */ +}; + +static struct mux muxes_v3p[16] = { + { + /* mux0 */ + .id = 0, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux1 */ + .id = 1, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux2 */ + .id = 2, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux3 */ + .id = 3, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA0_S0, 0xff}, + }, { + /* mux4 is not used in ULT1 */ + .id = 4, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux5 */ + .id = 5, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux6 */ + .id = 6, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux7 */ + .id = 7, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux8 */ + .id = 8, + .mux_inputs = {PXP_2D_CSC2, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX11}, + }, { + /* mux9 */ + .id = 9, + .mux_inputs = {0xff, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_LUT, 0xff}, + }, { + /* mux10 */ + .id = 10, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux11 */ + .id = 11, + .mux_inputs = {PXP_2D_LUT, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_ROTATION0}, + }, { + /* mux12 */ + .id = 12, + .mux_inputs = {PXP_2D_ROTATION0, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX14, 0xff}, + }, { + /* mux13 */ + .id = 13, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux14 */ + .id = 14, + .mux_inputs = {0xff, PXP_2D_MUX_MUX12, 0xff, 0xff}, + .mux_outputs = {PXP_2D_OUT, 0xff}, + }, { + /* mux15 */ + .id = 15, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, +}; + +static void __iomem *pxp_reg_base; + +#define pxp_writel(val, reg) writel(val, pxp_reg_base + (reg)) + +static __attribute__((aligned (1024*4))) unsigned int active_matrix_data_8x8[64]={ + 0x06050100, 0x04030207, 0x06050100, 0x04030207, + 0x00040302, 0x07060501, 0x00040302, 0x07060501, + 0x02070605, 0x01000403, 0x02070605, 0x01000403, + 0x05010004, 0x03020706, 0x05010004, 0x03020706, + 0x04030207, 0x06050100, 0x04030207, 0x06050100, + 0x07060501, 0x00040302, 0x07060501, 0x00040302, + 0x01000403, 0x02070605, 0x01000403, 0x02070605, + 0x03020706, 0x05010004, 0x03020706, 0x05010004, + 0x06050100, 0x04030207, 0x06050100, 0x04030207, + 0x00040302, 0x07060501, 0x00040302, 0x07060501, + 0x02070605, 0x01000403, 0x02070605, 0x01000403, + 0x05010004, 0x03020706, 0x05010004, 0x03020706, + 0x04030207, 0x06050100, 0x04030207, 0x06050100, + 0x07060501, 0x00040302, 0x07060501, 0x00040302, + 0x01000403, 0x02070605, 0x01000403, 0x02070605, + 0x03020706, 0x05010004, 0x03020706, 0x05010004 + }; + +static __attribute__((aligned (1024*4))) unsigned int bit1_dither_data_8x8[64] = { + + 1, 49*2, 13*2, 61*2, 4*2, 52*2, 16*2, 64*2, + 33*2, 17*2, 45*2, 29*2, 36*2, 20*2, 48*2, 32*2, + 9*2, 57*2, 5*2, 53*2, 12*2, 60*2, 8*2, 56*2, + 41*2, 25*2, 37*2, 21*2, 44*2, 28*2, 40*2, 24*2, + 3*2, 51*2, 15*2, 63*2, 2*2, 50*2, 14*2, 62*2, + 35*2, 19*2, 47*2, 31*2, 34*2, 18*2, 46*2, 30*2, + 11*2, 59*2, 7*2, 55*2, 10*2, 58*2, 6*2, 54*2, + 43*2, 27*2, 39*2, 23*2, 42*2, 26*2, 38*2, 22*2 +}; + +static __attribute__((aligned (1024*4))) unsigned int bit2_dither_data_8x8[64] = { + + 1, 49, 13, 61, 4, 52, 16, 64, + 33, 17, 45, 29, 36, 20, 48, 32, + 9, 57, 5, 53, 12, 60, 8, 56, + 41, 25, 37, 21, 44, 28, 40, 24, + 3, 51, 15, 63, 2, 50, 14, 62, + 35, 19, 47, 31, 34, 18, 46, 30, + 11, 59, 7, 55, 10, 58, 6, 54, + 43, 27, 39, 23, 42, 26, 38, 22 +}; + +static __attribute__((aligned (1024*4))) unsigned int bit4_dither_data_8x8[64] = { + + 1, 49/4, 13/4, 61/4, 4/4, 52/4, 16/4, 64/4, + 33/4, 17/4, 45/4, 29/4, 36/4, 20/4, 48/4, 32/4, + 9/4, 57/4, 5/4, 53/4, 12/4, 60/4, 8/4, 56/4, + 41/4, 25/4, 37/4, 21/4, 44/4, 28/4, 40/4, 24/4, + 3/4, 51/4, 15/4, 63/4, 2/4, 50/4, 14/4, 62/4, + 35/4, 19/4, 47/4, 31/4, 34/4, 18/4, 46/4, 30/4, + 11/4, 59/4, 7/4, 55/4, 10/4, 58/4, 6/4, 54/4, + 43/4, 27/4, 39/4, 23/4, 42/4, 26/4, 38/4, 22/4 +}; + +static void pxp_dithering_configure(struct pxps *pxp); +static void pxp_dithering_configure_v3p(struct pxps *pxp); +static void pxp_dithering_process(struct pxps *pxp); +static void pxp_wfe_a_process(struct pxps *pxp); +static void pxp_wfe_a_process_v3p(struct pxps *pxp); +static void pxp_wfe_a_configure(struct pxps *pxp); +static void pxp_wfe_a_configure_v3p(struct pxps *pxp); +static void pxp_wfe_b_process(struct pxps *pxp); +static void pxp_wfe_b_configure(struct pxps *pxp); +static void pxp_lut_status_set(struct pxps *pxp, unsigned int lut); +static void pxp_lut_status_set_v3p(struct pxps *pxp, unsigned int lut); +static void pxp_lut_status_clr(unsigned int lut); +static void pxp_lut_status_clr_v3p(unsigned int lut); +static void pxp_start2(struct pxps *pxp); +static void pxp_data_path_config_v3p(struct pxps *pxp); +static void pxp_soft_reset(struct pxps *pxp); +static void pxp_collision_detection_disable(struct pxps *pxp); +static void pxp_collision_detection_enable(struct pxps *pxp, + unsigned int width, + unsigned int height); +static void pxp_luts_activate(struct pxps *pxp, u64 lut_status); +static bool pxp_collision_status_report(struct pxps *pxp, struct pxp_collision_info *info); +static void pxp_histogram_status_report(struct pxps *pxp, u32 *hist_status); +static void pxp_histogram_enable(struct pxps *pxp, + unsigned int width, + unsigned int height); +static void pxp_histogram_disable(struct pxps *pxp); +static void pxp_lut_cleanup_multiple(struct pxps *pxp, u64 lut, bool set); +static void pxp_lut_cleanup_multiple_v3p(struct pxps *pxp, u64 lut, bool set); +static void pxp_luts_deactivate(struct pxps *pxp, u64 lut_status); +static void pxp_set_colorkey(struct pxps *pxp); +static void pxp_software_restart(struct pxps *pxp); +static void imx93_pxp_software_restart(struct pxps *pxp); + +enum { + DITHER0_LUT = 0x0, /* Select the LUT memory for access */ + DITHER0_ERR0 = 0x1, /* Select the ERR0 memory for access */ + DITHER0_ERR1 = 0x2, /* Select the ERR1 memory for access */ + DITHER1_LUT = 0x3, /* Select the LUT memory for access */ + DITHER2_LUT = 0x4, /* Select the LUT memory for access */ + ALU_A = 0x5, /* Select the ALU instr memory for access */ + ALU_B = 0x6, /* Select the ALU instr memory for access */ + WFE_A = 0x7, /* Select the WFE_A instr memory for access */ + WFE_B = 0x8, /* Select the WFE_B instr memory for access */ + RESERVED = 0x15, +}; + +enum pxp_devtype { + PXP_V3 = 0, + PXP_V3P, /* minor changes over V3, use WFE_B to replace WFE_A */ + PXP_V3_8ULP, /* PXP V3 version for iMX8ULP */ + PXP_V3_IMX93, /* PXP V3 version for iMX93 */ +}; + +#define pxp_is_v3(pxp) ((pxp->devdata->version == PXP_V3) || \ + (pxp->devdata->version == PXP_V3_8ULP)) +#define pxp_is_v3p(pxp) (pxp->devdata->version == PXP_V3P) + +struct pxp_devdata { + void (*pxp_wfe_a_configure)(struct pxps *pxp); + void (*pxp_wfe_a_process)(struct pxps *pxp); + void (*pxp_lut_status_set)(struct pxps *pxp, unsigned int lut); + void (*pxp_lut_status_clr)(unsigned int lut); + void (*pxp_dithering_configure)(struct pxps *pxp); + void (*pxp_lut_cleanup_multiple)(struct pxps *pxp, u64 lut, bool set); + void (*pxp_data_path_config)(struct pxps *pxp); + void (*pxp_restart)(struct pxps *pxp); + unsigned int version; + bool input_fetch_arbit_en; +}; + +static const struct pxp_devdata pxp_devdata[] = { + [PXP_V3] = { + .pxp_wfe_a_configure = pxp_wfe_a_configure, + .pxp_wfe_a_process = pxp_wfe_a_process, + .pxp_lut_status_set = pxp_lut_status_set, + .pxp_lut_status_clr = pxp_lut_status_clr, + .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple, + .pxp_dithering_configure = pxp_dithering_configure, + .pxp_data_path_config = NULL, + .pxp_restart = NULL, + .version = PXP_V3, + .input_fetch_arbit_en = false, + }, + [PXP_V3P] = { + .pxp_wfe_a_configure = pxp_wfe_a_configure_v3p, + .pxp_wfe_a_process = pxp_wfe_a_process_v3p, + .pxp_lut_status_set = pxp_lut_status_set_v3p, + .pxp_lut_status_clr = pxp_lut_status_clr_v3p, + .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple_v3p, + .pxp_dithering_configure = pxp_dithering_configure_v3p, + .pxp_data_path_config = pxp_data_path_config_v3p, + .pxp_restart = NULL, + .version = PXP_V3P, + .input_fetch_arbit_en = false, + }, + [PXP_V3_8ULP] = { + .pxp_wfe_a_configure = pxp_wfe_a_configure, + .pxp_wfe_a_process = pxp_wfe_a_process, + .pxp_lut_status_set = pxp_lut_status_set, + .pxp_lut_status_clr = pxp_lut_status_clr, + .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple, + .pxp_dithering_configure = pxp_dithering_configure, + .pxp_data_path_config = NULL, + .pxp_restart = pxp_software_restart, + .version = PXP_V3_8ULP, + .input_fetch_arbit_en = false, + }, + [PXP_V3_IMX93] = { + .pxp_wfe_a_configure = NULL, + .pxp_wfe_a_process = NULL, + .pxp_lut_status_set = NULL, + .pxp_lut_status_clr = NULL, + .pxp_lut_cleanup_multiple = NULL, + .pxp_dithering_configure = NULL, + .pxp_data_path_config = NULL, + .pxp_restart = imx93_pxp_software_restart, + .version = PXP_V3_IMX93, + /* + * Due to iMX93 only connect one AXI bus to PXP, so need to + * enable arbitration when use two PXP input fetch channels + */ + .input_fetch_arbit_en = true, + }, +}; + +/* + * PXP common functions + */ +static void dump_pxp_reg(struct pxps *pxp) +{ + struct pxp_register { + u32 offset; + const char * const name; + bool opt; + } regs[] = { + { 0x00, "HW_PXP_CTRL", false }, + { 0x10, "HW_PXP_STAT", false }, + { 0x20, "HW_PXP_OUT_CTRL", false }, + { 0x30, "HW_PXP_OUT_BUF", false }, + { 0x40, "HW_PXP_OUT_BUF2", false }, + { 0x50, "HW_PXP_OUT_PITCH", false }, + { 0x60, "HW_PXP_OUT_LRC", false }, + { 0x70, "HW_PXP_OUT_PS_ULC", false }, + { 0x80, "HW_PXP_OUT_PS_LRC", false }, + { 0x90, "HW_PXP_OUT_AS_ULC", false }, + { 0xa0, "HW_PXP_OUT_AS_LRC", false }, + { 0xb0, "HW_PXP_PS_CTRL", false }, + { 0xc0, "HW_PXP_PS_BUF", false }, + { 0xd0, "HW_PXP_PS_UBUF", false }, + { 0xe0, "HW_PXP_PS_VBUF", false }, + { 0xf0, "HW_PXP_PS_PITCH", false }, + { 0x100, "HW_PXP_PS_BACKGROUND_0", false }, + { 0x110, "HW_PXP_PS_SCALE", false }, + { 0x120, "HW_PXP_PS_OFFSET", false }, + { 0x130, "HW_PXP_PS_CLRKEYLOW_0", false }, + { 0x140, "HW_PXP_PS_CLRKEYHIGH_0", false }, + { 0x150, "HW_PXP_AS_CTRL", false }, + { 0x160, "HW_PXP_AS_BUF", false }, + { 0x170, "HW_PXP_AS_PITCH", false }, + { 0x180, "HW_PXP_AS_CLRKEYLOW_0", false }, + { 0x190, "HW_PXP_AS_CLRKEYHIGH_0", false }, + { 0x1A0, "HW_PXP_CSC1_COEF0", false }, + { 0x1B0, "HW_PXP_CSC1_COEF1", false }, + { 0x1C0, "HW_PXP_CSC1_COEF2", false }, + { 0x1D0, "HW_PXP_CSC2_CTRL", false }, + { 0x1E0, "HW_PXP_CSC2_COEF0", false }, + { 0x1F0, "HW_PXP_CSC2_COEF1", false }, + { 0x200, "HW_PXP_CSC2_COEF2", false }, + { 0x210, "HW_PXP_CSC2_COEF3", false }, + { 0x220, "HW_PXP_CSC2_COEF4", false }, + { 0x230, "HW_PXP_CSC2_COEF5", false }, + { 0x240, "HW_PXP_LUT_CTRL", true }, + { 0x250, "HW_PXP_LUT_ADDR", true }, + { 0x260, "HW_PXP_LUT_DATA", true }, + { 0x270, "HW_PXP_LUT_EXTMEM", true }, + { 0x280, "HW_PXP_CFA", true }, + { 0x290, "HW_PXP_ALPHA_A_CTRL", false }, + { 0x2a0, "HW_PXP_ALPHA_B_CTRL", false }, + { 0x320, "HW_PXP_POWER_REG0", false }, + { 0x400, "HW_PXP_NEXT", false }, + { 0x410, "HW_PXP_DEBUGCTRL", false }, + { 0x420, "HW_PXP_DEBUG", false }, + { 0x430, "HW_PXP_VERSION", false }, + }; + u32 val; + int i; + + for (i = 0; i < ARRAY_SIZE(regs); i++) { + if (pxp->devdata && + pxp->devdata->version == PXP_V3_IMX93 && + regs[i].opt) + continue; + + val = __raw_readl(pxp->base + regs[i].offset); + dev_dbg(pxp->dev, "%20s[0x%x]: 0x%.8x\n", regs[i].name, regs[i].offset, val); + } +} + +static void dump_pxp_reg2(struct pxps *pxp) +{ +#ifdef DEBUG + int i = 0; + + for (i=0; i< ((0x33C0/0x10) + 1);i++) { + printk("0x%08x: 0x%08x\n", 0x10*i, __raw_readl(pxp->base + 0x10*i)); + } +#endif +} + +static void print_param(struct pxp_layer_param *p, char *s) +{ + pr_debug("%s: t/l/w/h/s %d/%d/%d/%d/%d, addr %p\n", s, + p->top, p->left, p->width, p->height, p->stride, (void *)p->paddr); +} + +/* when it is, return yuv plane number */ +static uint8_t is_yuv(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_YVU444: + case PXP_PIX_FMT_VUY444: + return 1; + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + return 2; + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_YVU422P: + return 3; + default: + return 0; + } +} + +static u32 get_bpp_from_fmt(u32 pix_fmt) +{ + unsigned int bpp = 0; + + switch (pix_fmt) { + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YVU422P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YVU420P: + bpp = 8; + break; + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_XRGB555: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_XRGB444: + case PXP_PIX_FMT_RGBA444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_BGR565: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + bpp = 16; + break; + case PXP_PIX_FMT_RGB24: + case PXP_PIX_FMT_BGR24: + bpp = 24; + break; + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_YVU444: + case PXP_PIX_FMT_VUY444: + bpp = 32; + break; + default: + pr_err("%s: pix_fmt unsupport yet: 0x%x\n", __func__, pix_fmt); + break; + } + + return bpp; +} + +static uint32_t pxp_parse_ps_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_YVU420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_VUY444: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_YUYV: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_YVYU: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422; + break; + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGBA888; + break; + default: + pr_debug("PS doesn't support this format\n"); + fmt_ctrl = 0; + } + + return fmt_ctrl; +} + +static void pxp_set_colorkey(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) { + /* disable color key */ + pxp_writel(0xFFFFFF, HW_PXP_PS_CLRKEYLOW_0); + pxp_writel(0, HW_PXP_PS_CLRKEYHIGH_0); + } else { + pxp_writel(s0_params->color_key, HW_PXP_PS_CLRKEYLOW_0); + pxp_writel(s0_params->color_key, HW_PXP_PS_CLRKEYHIGH_0); + } + + if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { + pxp_writel(ol_params->color_key, HW_PXP_AS_CLRKEYLOW_0); + pxp_writel(ol_params->color_key, HW_PXP_AS_CLRKEYHIGH_0); + } else { + /* disable color key */ + pxp_writel(0xFFFFFF, HW_PXP_AS_CLRKEYLOW_0); + pxp_writel(0, HW_PXP_AS_CLRKEYHIGH_0); + } +} + +static void pxp_software_restart(struct pxps *pxp) +{ + pxp_soft_reset(pxp); + pxp_writel(0x0, HW_PXP_CTRL); + + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); +} + +static void imx93_pxp_software_restart(struct pxps *pxp) +{ + pxp_software_restart(pxp); + + /* config mediamix for PXP, keep default so far */ +} + +static uint32_t pxp_parse_as_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_RGBA32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA8888; + break; + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_ARGB555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB1555; + break; + case PXP_PIX_FMT_ARGB444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB4444; + break; + case PXP_PIX_FMT_RGBA555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA5551; + break; + case PXP_PIX_FMT_RGBA444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA4444; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_RGB444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB444; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB565; + break; + default: + pr_debug("AS doesn't support this format\n"); + fmt_ctrl = 0xf; + break; + } + + return fmt_ctrl; +} + +static uint32_t pxp_parse_out_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422; + break; + default: + pr_debug("OUT doesn't support this format\n"); + fmt_ctrl = 0; + } + + return fmt_ctrl; +} + +static void set_mux(struct mux_config *path_ctrl) +{ + struct mux_config *mux = path_ctrl; + + *(uint32_t *)path_ctrl = 0xFFFFFFFF; + + mux->mux0_sel = 0; + mux->mux3_sel = 1; + mux->mux6_sel = 1; + mux->mux8_sel = 0; + mux->mux9_sel = 1; + mux->mux11_sel = 0; + mux->mux12_sel = 1; + mux->mux14_sel = 0; +} + +static void set_mux_val(struct mux_config *muxes, + uint32_t mux_id, + uint32_t mux_val) +{ + BUG_ON(!muxes); + BUG_ON(mux_id > 15); + + switch (mux_id) { + case 0: + muxes->mux0_sel = mux_val; + break; + case 1: + muxes->mux1_sel = mux_val; + break; + case 2: + muxes->mux2_sel = mux_val; + break; + case 3: + muxes->mux3_sel = mux_val; + break; + case 4: + muxes->mux4_sel = mux_val; + break; + case 5: + muxes->mux5_sel = mux_val; + break; + case 6: + muxes->mux6_sel = mux_val; + break; + case 7: + muxes->mux7_sel = mux_val; + break; + case 8: + muxes->mux8_sel = mux_val; + break; + case 9: + muxes->mux9_sel = mux_val; + break; + case 10: + muxes->mux10_sel = mux_val; + break; + case 11: + muxes->mux11_sel = mux_val; + break; + case 12: + muxes->mux12_sel = mux_val; + break; + case 13: + muxes->mux13_sel = mux_val; + break; + case 14: + muxes->mux14_sel = mux_val; + break; + case 15: + muxes->mux15_sel = mux_val; + break; + default: + break; + } +} + +static uint32_t get_mux_val(struct mux_config *muxes, + uint32_t mux_id) +{ + BUG_ON(!muxes); + BUG_ON(mux_id > 15); + + switch (mux_id) { + case 0: + return muxes->mux0_sel; + case 1: + return muxes->mux1_sel; + case 2: + return muxes->mux2_sel; + case 3: + return muxes->mux3_sel; + case 4: + return muxes->mux4_sel; + case 5: + return muxes->mux5_sel; + case 6: + return muxes->mux6_sel; + case 7: + return muxes->mux7_sel; + case 8: + return muxes->mux8_sel; + case 9: + return muxes->mux9_sel; + case 10: + return muxes->mux10_sel; + case 11: + return muxes->mux11_sel; + case 12: + return muxes->mux12_sel; + case 13: + return muxes->mux13_sel; + case 14: + return muxes->mux14_sel; + case 15: + return muxes->mux15_sel; + default: + return -EINVAL; + } +} + +static uint32_t pxp_store_ctrl_config(struct pxp_pixmap *out, uint8_t mode, + uint8_t fill_en, uint8_t combine_2ch) +{ + struct store_ctrl ctrl; + uint8_t output_active_bpp; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + if (combine_2ch) { + ctrl.combine_2channel = 1; + if (out) { + output_active_bpp = active_bpp(out->bpp); + ctrl.pack_in_sel = (output_active_bpp < 0x3) ? 1 : 0; + ctrl.store_memory_en = 1; + } + } else { + if (fill_en) + ctrl.fill_data_en = 1; + + ctrl.store_memory_en = 1; + } + + if (out && (out->rotate || out->flip)) + ctrl.block_en = 1; + + ctrl.ch_en = 1; + ctrl.block_16 = 1; + ctrl.wr_num_bytes = 3; + + return *(uint32_t *)&ctrl; +} + +static uint32_t pxp_store_size_config(struct pxp_pixmap *out) +{ + struct store_size size; + + memset((void*)&size, 0x0, sizeof(size)); + + size.out_height = out->height - 1; + size.out_width = out->width - 1; + + return *(uint32_t *)&size; +} + +static uint32_t pxp_store_pitch_config(struct pxp_pixmap *out0, + struct pxp_pixmap *out1) +{ + struct store_pitch pitch; + + memset((void*)&pitch, 0x0, sizeof(pitch)); + + pitch.ch0_out_pitch = out0->pitch; + pitch.ch1_out_pitch = out1 ? out1->pitch : 0; + + return *(uint32_t *)&pitch; +} + +static struct color *pxp_find_rgb_color(uint32_t format) +{ + int i; + + for (i = 0; i < sizeof(rgb_colors) / sizeof(struct color); i++) { + if (rgb_colors[i].format == format) + return &rgb_colors[i]; + } + + return NULL; +} + +static struct color_component *pxp_find_comp(struct color *color, uint8_t id) +{ + int i; + + for (i = 0; i < 4; i++) { + if (id == color->comp[i].id) + return &color->comp[i]; + } + + return NULL; +} + +static struct color *pxp_find_yuv_color(uint32_t format) +{ + int i; + + for (i = 0; i < sizeof(yuv_colors) / sizeof(struct color); i++) { + if (yuv_colors[i].format == format) + return &yuv_colors[i]; + } + + return NULL; +} + +static uint64_t pxp_store_d_shift_calc(uint32_t in_fmt, uint32_t out_fmt, + struct store_d_mask *d_mask) +{ + int i, shift_width, shift_flag, drop = 0; + struct store_d_shift d_shift; + struct color *input_color, *output_color; + struct color_component *input_comp, *output_comp; + + BUG_ON((in_fmt == out_fmt)); + memset((void*)&d_shift, 0x0, sizeof(d_shift)); + memset((void*)d_mask, 0x0, sizeof(*d_mask) * 8); + + if (!is_yuv(in_fmt)) { + input_color = pxp_find_rgb_color(in_fmt); + output_color = pxp_find_rgb_color(out_fmt); + } else { + input_color = pxp_find_yuv_color(in_fmt); + output_color = pxp_find_yuv_color(out_fmt); + } + + for (i = 0; i < 4; i++) { + input_comp = &input_color->comp[i]; + if (!input_comp->length) + continue; + + output_comp = pxp_find_comp(output_color, input_comp->id); + if (!output_comp->length) + continue; + + /* only rgb format can drop color bits */ + if (input_comp->length > output_comp->length) { + drop = input_comp->length - output_comp->length; + input_comp->offset += drop; + } + d_mask[i].d_mask_l = output_comp->mask << input_comp->offset; + + shift_width = input_comp->offset - output_comp->offset; + if (shift_width > 0) + shift_flag = 0; /* right shift */ + else if (shift_width < 0) { + shift_flag = 1; /* left shift */ + shift_width = -shift_width; + } else + shift_width = shift_flag = 0; /* no shift require */ + + switch (i) { + case 0: + d_shift.d_shift_width0 = shift_width; + d_shift.d_shift_flag0 = shift_flag; + break; + case 1: + d_shift.d_shift_width1 = shift_width; + d_shift.d_shift_flag1 = shift_flag; + break; + case 2: + d_shift.d_shift_width2 = shift_width; + d_shift.d_shift_flag2 = shift_flag; + break; + case 3: + d_shift.d_shift_width3 = shift_width; + d_shift.d_shift_flag3 = shift_flag; + break; + default: + printk(KERN_ERR "unsupport d shift\n"); + break; + } + + input_comp->offset -= drop; + } + + return *(uint64_t *)&d_shift; +} + +static uint32_t pxp_store_shift_ctrl_config(struct pxp_pixmap *out, + uint8_t shift_bypass) +{ + struct store_shift_ctrl shift_ctrl; + + memset((void*)&shift_ctrl, 0x0, sizeof(shift_ctrl)); + + shift_ctrl.output_active_bpp = active_bpp(out->bpp); + /* Not general data */ + if (!shift_bypass) { + switch(out->format) { + case PXP_PIX_FMT_YUYV: + shift_bypass = 1; + fallthrough; + case PXP_PIX_FMT_YVYU: + shift_ctrl.out_yuv422_1p_en = 1; + break; + case PXP_PIX_FMT_NV16: + shift_bypass = 1; + fallthrough; + case PXP_PIX_FMT_NV61: + shift_ctrl.out_yuv422_2p_en = 1; + break; + default: + break; + } + } + shift_ctrl.shift_bypass = shift_bypass; + + return *(uint32_t *)&shift_ctrl; +} + +static uint32_t pxp_fetch_ctrl_config(struct pxp_pixmap *in, + uint8_t mode) +{ + struct fetch_ctrl ctrl; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + if (mode == FETCH_MODE_NORMAL) + ctrl.bypass_pixel_en = 0; + + if (in->flip == PXP_H_FLIP) + ctrl.hflip = 1; + else if (in->flip == PXP_V_FLIP) + ctrl.vflip = 1; + + ctrl.rotation_angle = rotate_map(in->rotate); + + if (in->rotate || in->flip) + ctrl.block_en = 1; + + ctrl.block_16 = 1; + ctrl.ch_en = 1; + ctrl.rd_num_bytes = 3; + + return *(uint32_t *)&ctrl; +} + +static uint32_t pxp_fetch_active_size_ulc(struct pxp_pixmap *in) +{ + struct fetch_active_size_ulc size_ulc; + + memset((void*)&size_ulc, 0x0, sizeof(size_ulc)); + + size_ulc.active_size_ulc_x = 0; + size_ulc.active_size_ulc_y = 0; + + return *(uint32_t *)&size_ulc; +} + +static uint32_t pxp_fetch_active_size_lrc(struct pxp_pixmap *in) +{ + struct fetch_active_size_lrc size_lrc; + + memset((void*)&size_lrc, 0x0, sizeof(size_lrc)); + + if (in->crop.width > 0 && in->crop.height > 0) { + size_lrc.active_size_lrc_x = in->crop.width - 1; + size_lrc.active_size_lrc_y = in->crop.height - 1; + } else { + size_lrc.active_size_lrc_x = in->width - 1; + size_lrc.active_size_lrc_y = in->height - 1; + } + + return *(uint32_t *)&size_lrc; +} + +static uint32_t pxp_fetch_pitch_config(struct pxp_pixmap *in0, + struct pxp_pixmap *in1) +{ + struct fetch_pitch pitch; + + memset((void*)&pitch, 0x0, sizeof(pitch)); + + if (in0) + pitch.ch0_input_pitch = in0->pitch; + if (in1) + pitch.ch1_input_pitch = in1->pitch; + + return *(uint32_t *)&pitch; +} + +static uint32_t pxp_fetch_shift_ctrl_config(struct pxp_pixmap *in, + uint8_t shift_bypass, + uint8_t need_expand) +{ + uint8_t input_expand_format; + struct fetch_shift_ctrl shift_ctrl; + + memset((void*)&shift_ctrl, 0x0, sizeof(shift_ctrl)); + + shift_ctrl.input_active_bpp = active_bpp(in->bpp); + shift_ctrl.shift_bypass = shift_bypass; + + if (in->bpp == 32) + need_expand = 0; + + if (need_expand) { + input_expand_format = expand_format(in->format); + + if (input_expand_format <= 0x7) { + shift_ctrl.expand_en = 1; + shift_ctrl.expand_format = input_expand_format; + } + } + + return *(uint32_t *)&shift_ctrl; +} + +static uint32_t pxp_fetch_shift_calc(uint32_t in_fmt, uint32_t out_fmt, + struct fetch_shift_width *shift_width) +{ + int i; + struct fetch_shift_offset shift_offset; + struct color *input_color, *output_color; + struct color_component *input_comp, *output_comp; + + memset((void*)&shift_offset, 0x0, sizeof(shift_offset)); + memset((void*)shift_width, 0x0, sizeof(*shift_width)); + + if (!is_yuv(in_fmt)) { + input_color = pxp_find_rgb_color(in_fmt); + output_color = pxp_find_rgb_color(out_fmt); + } else { + input_color = pxp_find_yuv_color(in_fmt); + output_color = pxp_find_yuv_color(out_fmt); + } + + for(i = 0; i < 4; i++) { + output_comp = &output_color->comp[i]; + if (!output_comp->length) + continue; + + input_comp = pxp_find_comp(input_color, output_comp->id); + switch (i) { + case 0: + shift_offset.offset0 = input_comp->offset; + shift_width->width0 = input_comp->length; + break; + case 1: + shift_offset.offset1 = input_comp->offset; + shift_width->width1 = input_comp->length; + break; + case 2: + shift_offset.offset2 = input_comp->offset; + shift_width->width2 = input_comp->length; + break; + case 3: + shift_offset.offset3 = input_comp->offset; + shift_width->width3 = input_comp->length; + break; + } + } + + return *(uint32_t *)&shift_offset; +} + +static int pxp_start(struct pxps *pxp) +{ + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + u32 val; + + if (pxp->devdata && pxp->devdata->input_fetch_arbit_en) + __raw_writel(BF_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN(1), + pxp->base + HW_PXP_INPUT_FETCH_CTRL_CH0_SET); + + val = (BM_PXP_CTRL_ENABLE | BM_PXP_CTRL_BLOCK_SIZE); + + if (pxp->devdata && + pxp_is_v3(pxp) && + proc_data->lut_transform) { + val |= (BM_PXP_CTRL_ENABLE_CSC2 | + BM_PXP_CTRL_ENABLE_ROTATE0 | + BM_PXP_CTRL_ENABLE_ROTATE1); + } + + if (pxp->devdata && pxp->devdata->version <= PXP_V3_8ULP) { + val |= BM_PXP_CTRL_ENABLE_LUT; + val &= ~(BM_PXP_CTRL_BLOCK_SIZE); + } + + __raw_writel(val, pxp->base + HW_PXP_CTRL_SET); + dump_pxp_reg(pxp); + + return 0; +} + +static bool fmt_ps_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_XRGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_XRGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VUY444: + /* need word byte swap */ + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_VYUY: + /* need word byte swap */ + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_RGBA444: + return true; + default: + return false; + } +} + +static bool fmt_as_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_RGBA444: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_RGB565: + return true; + default: + return false; + } +} + +static bool fmt_out_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_RGB24: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV21: + return true; + default: + return false; + } +} + +/* common means 'ARGB32/XRGB32/YUV444' */ +static uint8_t fmt_fetch_to_common(uint32_t in) +{ + switch (in) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_YUV444: + return FETCH_NOOP; + + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_NV16: + return FETCH_EXPAND; + + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_YVU444: + return FETCH_SHIFT; + + case PXP_PIX_FMT_BGR565: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + return FETCH_EXPAND | FETCH_SHIFT; + + default: + return 0; + } +} + +static uint8_t fmt_store_from_common(uint32_t out) +{ + switch (out) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_YUV444: + return STORE_NOOP; + + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_NV16: + return STORE_SHRINK; + + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_YVU444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_GREY: + return STORE_SHIFT; + + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_NV61: + return STORE_SHIFT | STORE_SHRINK; + + default: + return 0; + } +} + +static void filter_possible_inputs(struct pxp_pixmap *input, + size_t *possible) +{ + uint8_t clear = 0xff; + uint8_t position = 0; + + do { + position = find_next_bit((unsigned long *)possible, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_PS: + if (!fmt_ps_support(input->format)) + clear = PXP_2D_PS; + break; + case PXP_2D_AS: + if (!fmt_as_support(input->format)) + clear = PXP_2D_AS; + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + if ((is_yuv(input->format) == 3)) { + clear = position; + break; + } + if ((input->flags & IN_NEED_FMT_UNIFIED) || + is_yuv(input->format) == 2) + if (!fmt_fetch_to_common(input->format)) + clear = position; + break; + default: + pr_err("invalid input node: %d\n", position); + clear = position; + break; + } + + if (clear != 0xff) { + clear_bit(clear, (unsigned long*)possible); + clear = 0xff; + } + + position++; + } while (1); +} + +static void filter_possible_outputs(struct pxp_pixmap *output, + size_t *possible) +{ + uint8_t clear = 0xff; + uint8_t position = 0; + + do { + position = find_next_bit((unsigned long *)possible, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_OUT: + if (!fmt_out_support(output->format)) + clear = PXP_2D_OUT; + break; + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + if (output->flags) { + if (!fmt_store_from_common(output->format)) + clear = position; + } + break; + default: + pr_err("invalid output node: %d\n", position); + clear = position; + break; + } + + if (clear != 0xff) { + clear_bit(clear, (unsigned long*)possible); + clear = 0xff; + } + + position++; + } while (1); +} + +/* + * PXP support PS/AS -> OUT, INPUT FETCH -> STORE data path + * don't support cross them, such as PS/AS -> STORE and ROTATION2 + * (or ROTATION1 in some IMX platform reference manul) + * engine only can be used to rotate data from input fetch engine. + * So replace ROTATION1 with ROTATION0 when AS/PS engine are used + */ +static void filter_nodes_by_inputs_outputs(size_t *nodes_in_path, + size_t *nodes_used) +{ + bool ps_as_engine_used; + + ps_as_engine_used = (((*nodes_in_path) & (1 << PXP_2D_PS)) | + ((*nodes_in_path) & (1 << PXP_2D_AS)) | + ((*nodes_used) & (1 << PXP_2D_PS)) | + ((*nodes_used) & (1 << PXP_2D_AS))) ? true : false; + + if (ps_as_engine_used) { + if (*nodes_in_path & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)nodes_in_path); + set_bit(PXP_2D_ROTATION0, (unsigned long *)nodes_in_path); + } + + if (*nodes_used & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)nodes_used); + set_bit(PXP_2D_ROTATION0, (unsigned long *)nodes_used); + } + } +} + +static uint32_t calc_shortest_path(size_t *nodes_used) +{ + uint32_t distance = 0; + uint32_t from = 0, to = 0, bypass, end; + + do { + from = find_next_bit((unsigned long *)nodes_used, 32, from); + if (from >= sizeof(uint32_t) * 8) + break; + + if (to != 0) { + if (path_table[to][from].distance == DISTANCE_INFINITY) + return DISTANCE_INFINITY; + + distance += path_table[to][from].distance; + /* backtrace */ + end = from; + while (1) { + bypass = path_table[to][end].prev_node; + if (bypass == to) + break; + set_bit(bypass, (unsigned long*)nodes_used); + end = bypass; + } + } + + to = find_next_bit((unsigned long *)nodes_used, 32, from + 1); + if (to >= sizeof(uint32_t) * 8) + break; + + if (path_table[from][to].distance == DISTANCE_INFINITY) + return DISTANCE_INFINITY; + + distance += path_table[from][to].distance; + /* backtrace */ + end = to; + while (1) { + bypass = path_table[from][end].prev_node; + if (bypass == from) + break; + set_bit(bypass, (unsigned long*)nodes_used); + end = bypass; + } + + from = to + 1; + } while (1); + + return distance; +} + +static uint32_t find_best_path(size_t inputs, + size_t outputs, + struct pxp_pixmap *in, + size_t *nodes_used) +{ + size_t outs; + size_t nodes_add, best_nodes_used = 0; + uint8_t in_pos = 0, out_pos = 0; + size_t nodes_in_path, best_nodes_in_path = 0; + uint32_t best_distance = DISTANCE_INFINITY, distance; + + do { + outs = outputs; + in_pos = find_next_bit((unsigned long *)&inputs, 32, in_pos); + if (in_pos >= sizeof(uint32_t) * 8) + break; + nodes_add = 0; + set_bit(in_pos, (unsigned long *)&nodes_add); + + switch (in_pos) { + case PXP_2D_PS: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) { + if (is_yuv(in->format)) + set_bit(PXP_2D_CSC1, + (unsigned long *)&nodes_add); + else + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + } + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION1, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_INPUT_STORE0, (unsigned long *)&outs); + break; + case PXP_2D_AS: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_INPUT_STORE0, (unsigned long *)&outs); + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_OUT, (unsigned long *)&outs); + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION1, + (unsigned long *)&nodes_add); + break; + default: + /* alph0_s0/s1, alpha1_s0/s1 */ + break; + } + + nodes_add |= *nodes_used; + + do { + out_pos = find_next_bit((unsigned long *)&outs, 32, out_pos); + if (out_pos >= sizeof(uint32_t) * 8) + break; + set_bit(out_pos, (unsigned long *)&nodes_add); + + switch(out_pos) { + case PXP_2D_ALPHA0_S0: + case PXP_2D_ALPHA0_S1: + case PXP_2D_ALPHA1_S0: + case PXP_2D_ALPHA1_S1: + clear_bit(PXP_2D_CSC2, (unsigned long *)&nodes_add); + clear_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_add); + clear_bit(PXP_2D_LUT, (unsigned long *)&nodes_add); + break; + default: + break; + } + + nodes_in_path = nodes_add; + distance = calc_shortest_path(&nodes_in_path); + if (best_distance > distance) { + best_distance = distance; + best_nodes_used = nodes_add; + best_nodes_in_path = nodes_in_path; + } + pr_debug("%s: out_pos = %d, nodes_in_path = 0x%x, nodes_add = 0x%x, distance = 0x%x\n", + __func__, out_pos, (u32)nodes_in_path, (u32)nodes_add, distance); + + clear_bit(out_pos, (unsigned long *)&nodes_add); + + out_pos++; + } while (1); + + in_pos++; + } while (1); + + *nodes_used = best_nodes_used; + + return best_nodes_in_path; +} + +static uint32_t ps_calc_scaling(struct pxp_pixmap *input, + struct pxp_pixmap *output, + struct ps_ctrl *ctrl) +{ + struct ps_scale scale; + uint32_t decx, decy; + + memset((void*)&scale, 0x0, sizeof(scale)); + + if (!output->crop.width || !output->crop.height) { + pr_err("Invalid drect width and height passed in\n"); + return 0; + } + + if ((input->rotate == 90) || (input->rotate == 270)) + swap(output->crop.width, output->crop.height); + + decx = input->crop.width / output->crop.width; + decy = input->crop.height / output->crop.height; + + if (decx > 1) { + if (decx >= 2 && decx < 4) { + decx = 2; + ctrl->decx = 1; + } else if (decx >= 4 && decx < 8) { + decx = 4; + ctrl->decx = 2; + } else if (decx >= 8) { + decx = 8; + ctrl->decx = 3; + } + scale.xscale = input->crop.width * 0x1000 / + (output->crop.width * decx); + + /* A factor greater than 2 is not supported + * with the bilinear filter, so correct it in + * driver + */ + if (((scale.xscale >> BP_PXP_PS_SCALE_OFFSET) & 0x3) > 2) { + scale.xscale &= (~(0x3 << BP_PXP_PS_SCALE_OFFSET)); + scale.xscale |= (0x2 << BP_PXP_PS_SCALE_OFFSET); + pr_warn("%s: scale.xscale is larger than 2, forcing to 2" + "input w/h=(%d,%d), output w/h=(%d, %d)\n", + __func__, input->crop.width, input->crop.height, + output->crop.width, output->crop.height); + } + } else { + if (!is_yuv(input->format) || + (is_yuv(input->format) == is_yuv(output->format)) || + (input->format == PXP_PIX_FMT_GREY) || + (input->format == PXP_PIX_FMT_GY04) || + (input->format == PXP_PIX_FMT_VUY444)) { + if ((input->crop.width > 1) && + (output->crop.width > 1)) + scale.xscale = (input->crop.width - 1) * 0x1000 / + (output->crop.width - 1); + else + scale.xscale = input->crop.width * 0x1000 / + output->crop.width; + } else { + if ((input->crop.width > 2) && + (output->crop.width > 1)) + scale.xscale = (input->crop.width - 2) * 0x1000 / + (output->crop.width - 1); + else + scale.xscale = input->crop.width * 0x1000 / + output->crop.width; + } + } + + if (decy > 1) { + if (decy >= 2 && decy < 4) { + decy = 2; + ctrl->decy = 1; + } else if (decy >= 4 && decy < 8) { + decy = 4; + ctrl->decy = 2; + } else if (decy >= 8) { + decy = 8; + ctrl->decy = 3; + } + scale.yscale = input->crop.height * 0x1000 / + (output->crop.height * decy); + + /* A factor greater than 2 is not supported + * with the bilinear filter, so correct it in + * driver + */ + if (((scale.yscale >> BP_PXP_PS_SCALE_OFFSET) & 0x3) > 2) { + scale.yscale &= (~(0x3 << BP_PXP_PS_SCALE_OFFSET)); + scale.yscale |= (0x2 << BP_PXP_PS_SCALE_OFFSET); + pr_warn("%s: scale.yscale is larger than 2, forcing to 2" + "input w/h=(%d,%d), output w/h=(%d, %d)\n", + __func__, input->crop.width, input->crop.height, + output->crop.width, output->crop.height); + } + } else { + if ((input->crop.height > 1) && (output->crop.height > 1)) + scale.yscale = (input->crop.height - 1) * 0x1000 / + (output->crop.height - 1); + else + scale.yscale = input->crop.height * 0x1000 / + output->crop.height; + } + + return *(uint32_t *)&scale; +} + +static int pxp_ps_config(struct pxp_pixmap *input, + struct pxp_pixmap *output) +{ + uint32_t offset, U, V; + struct ps_ctrl ctrl; + struct coordinate out_ps_ulc, out_ps_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_ps_fmt(input->format); + + switch (output->rotate) { + case 0: + out_ps_ulc.x = output->crop.x; + out_ps_ulc.y = output->crop.y; + out_ps_lrc.x = out_ps_ulc.x + output->crop.width - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.height - 1; + break; + case 90: + out_ps_ulc.x = output->crop.y; + out_ps_ulc.y = output->width - (output->crop.x + output->crop.width); + out_ps_lrc.x = out_ps_ulc.x + output->crop.height - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.width - 1; + break; + case 180: + out_ps_ulc.x = output->width - (output->crop.x + output->crop.width); + out_ps_ulc.y = output->height - (output->crop.y + output->crop.height); + out_ps_lrc.x = out_ps_ulc.x + output->crop.width - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.height - 1; + break; + case 270: + out_ps_ulc.x = output->height - (output->crop.y + output->crop.height); + out_ps_ulc.y = output->crop.x; + out_ps_lrc.x = out_ps_ulc.x + output->crop.height - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.width - 1; + break; + default: + pr_err("PxP only support rotate 0 90 180 270\n"); + return -EINVAL; + break; + } + + if ((input->format == PXP_PIX_FMT_YUYV) || + (input->format == PXP_PIX_FMT_YVYU)) + ctrl.wb_swap = 1; + + pxp_writel(ps_calc_scaling(input, output, &ctrl), + HW_PXP_PS_SCALE); + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_PS_CTRL); + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + + pxp_writel(input->paddr + offset, HW_PXP_PS_BUF); + + switch (is_yuv(input->format)) { + case 0: /* RGB */ + case 1: + /* + * 1 Plane YUV. + * Refer to PXP manual, in monochrome modes Y8 and Y4, + * the low 16 bits of PS_VBUF register are used as the + * U/V data in the datapath instead of sourcing U/V data + * from external buffers. + */ + if (input->format == PXP_PIX_FMT_GY04 || + input->format == PXP_PIX_FMT_GREY) + pxp_writel(0x8080, HW_PXP_PS_VBUF); + break; + case 2: /* NV16,NV61,NV12,NV21 */ + U = (input->paddr_u) ? input->paddr_u : + input->paddr + input->width * input->height; + if ((input->format == PXP_PIX_FMT_NV16) || + (input->format == PXP_PIX_FMT_NV61)) { + pxp_writel(U + offset, HW_PXP_PS_UBUF); + } else { + offset = input->crop.y * input->pitch >> 1; + offset += input->crop.x; + pxp_writel(U + offset, HW_PXP_PS_UBUF); + } + break; + case 3: /* YUV422P, YUV420P */ + U = (input->paddr_u) ? input->paddr_u : + input->paddr + input->width * input->height; + if (input->format == PXP_PIX_FMT_YUV422P) { + pxp_writel(U + (offset >> 1), HW_PXP_PS_UBUF); + V = (input->paddr_v) ? input->paddr_v : + U + (input->width * input->height >> 1); + pxp_writel(V + (offset >> 1), HW_PXP_PS_VBUF); + } else if (input->format == PXP_PIX_FMT_YUV420P) { + offset = input->crop.y * input->pitch >> 2; + offset += input->crop.x >> 1; + pxp_writel(U + offset, HW_PXP_PS_UBUF); + V = (input->paddr_v) ? input->paddr_v : + U + (input->width * input->height >> 2); + pxp_writel(V + offset, HW_PXP_PS_VBUF); + } else if (input->format == PXP_PIX_FMT_YVU420P) { + V = (input->paddr_v) ? input->paddr_v : + U + (input->width * input->height >> 2); + offset = input->crop.y * input->pitch >> 2; + offset += input->crop.x >> 1; + pxp_writel(U + offset, HW_PXP_PS_VBUF); + pxp_writel(V + offset, HW_PXP_PS_UBUF); + } + + break; + default: + break; + } + + pxp_writel(input->pitch, HW_PXP_PS_PITCH); + pxp_writel(*(uint32_t *)&out_ps_ulc, HW_PXP_OUT_PS_ULC); + pxp_writel(*(uint32_t *)&out_ps_lrc, HW_PXP_OUT_PS_LRC); + + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_as_config(struct pxp_pixmap *input, + struct pxp_pixmap *output) +{ + uint32_t offset; + struct as_ctrl ctrl; + struct coordinate out_as_ulc, out_as_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_as_fmt(input->format); + + if (alpha_blending_version == PXP_ALPHA_BLENDING_V1) { + if (input->format == PXP_PIX_FMT_BGRA32) { + if (!input->g_alpha.combine_enable) { + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs; + ctrl.rop = 0x3; + } + } + + if (input->g_alpha.global_alpha_enable) { + if (input->g_alpha.global_override) + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__Override; + else + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply; + + if (input->g_alpha.alpha_invert) + ctrl.alpha0_invert = 0x1; + } + + if (input->g_alpha.color_key_enable) { + ctrl.enable_colorkey = 1; + } + + ctrl.alpha = input->g_alpha.global_alpha; + } + + out_as_ulc.x = out_as_ulc.y = 0; + if (input->g_alpha.combine_enable) { + out_as_lrc.x = input->width - 1; + out_as_lrc.y = input->height - 1; + } else { + out_as_lrc.x = output->crop.width - 1; + out_as_lrc.y = output->crop.height - 1; + } + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + pxp_writel(input->paddr + offset, HW_PXP_AS_BUF); + + pxp_writel(input->pitch, HW_PXP_AS_PITCH); + pxp_writel(*(uint32_t *)&out_as_ulc, HW_PXP_OUT_AS_ULC); + pxp_writel(*(uint32_t *)&out_as_lrc, HW_PXP_OUT_AS_LRC); + + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_AS_CTRL); + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static uint32_t pxp_fetch_size_config(struct pxp_pixmap *input) +{ + struct fetch_size total_size; + + memset((void*)&total_size, 0x0, sizeof(total_size)); + + total_size.input_total_width = input->width - 1; + total_size.input_total_height = input->height - 1; + + return *(uint32_t *)&total_size; +} + +static int pxp_fetch_config(struct pxp_pixmap *input, + uint32_t fetch_index) +{ + uint8_t shift_bypass = 1, expand_en = 0; + uint32_t flags, pitch = 0, offset, UV = 0; + uint32_t in_fmt, out_fmt; + uint32_t size_ulc, size_lrc; + uint32_t fetch_ctrl, total_size; + uint32_t shift_ctrl, shift_offset = 0; + struct fetch_shift_width shift_width; + + memset((unsigned int *)&shift_width, 0x0, sizeof(shift_width)); + fetch_ctrl = pxp_fetch_ctrl_config(input, FETCH_MODE_NORMAL); + size_ulc = pxp_fetch_active_size_ulc(input); + size_lrc = pxp_fetch_active_size_lrc(input); + total_size = pxp_fetch_size_config(input); + + if (input->flags) { + flags = fmt_fetch_to_common(input->format); + shift_bypass = (flags & FETCH_SHIFT) ? 0 : 1; + expand_en = (flags & FETCH_EXPAND) ? 1 : 0; + + if (!shift_bypass) { + if (expand_en) { + if (is_yuv(input->format)) { + in_fmt = PXP_PIX_FMT_YVU444; + out_fmt = PXP_PIX_FMT_YUV444; + } else { + in_fmt = PXP_PIX_FMT_ABGR32; + out_fmt = PXP_PIX_FMT_ARGB32; + } + } else { + in_fmt = input->format; + out_fmt = is_yuv(input->format) ? + PXP_PIX_FMT_YUV444 : + PXP_PIX_FMT_ARGB32; + } + + shift_offset = pxp_fetch_shift_calc(in_fmt, out_fmt, + &shift_width); + } + } + shift_ctrl = pxp_fetch_shift_ctrl_config(input, shift_bypass, expand_en); + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + if (is_yuv(input->format) == 2) + UV = input->paddr + input->width * input->height; + + switch (fetch_index) { + case PXP_2D_INPUT_FETCH0: + pitch = __raw_readl(pxp_reg_base + HW_PXP_INPUT_FETCH_PITCH); + pitch |= pxp_fetch_pitch_config(input, NULL); + pxp_writel(fetch_ctrl, HW_PXP_INPUT_FETCH_CTRL_CH0); + pxp_writel(size_ulc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0); + pxp_writel(size_lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0); + pxp_writel(total_size, HW_PXP_INPUT_FETCH_SIZE_CH0); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0); + pxp_writel(input->paddr + offset, HW_PXP_INPUT_FETCH_ADDR_0_CH0); + if (UV) + pxp_writel(UV + offset, HW_PXP_INPUT_FETCH_ADDR_1_CH0); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0); + if (shift_offset) + pxp_writel(*(uint32_t *)&shift_offset, HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0); + pxp_writel(*(uint32_t *)&shift_width, HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0); + break; + case PXP_2D_INPUT_FETCH1: + pitch = __raw_readl(pxp_reg_base + HW_PXP_INPUT_FETCH_PITCH); + pitch |= pxp_fetch_pitch_config(NULL, input); + pxp_writel(fetch_ctrl, HW_PXP_INPUT_FETCH_CTRL_CH1); + pxp_writel(size_ulc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1); + pxp_writel(size_lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1); + pxp_writel(total_size, HW_PXP_INPUT_FETCH_SIZE_CH1); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1); + pxp_writel(input->paddr + offset, HW_PXP_INPUT_FETCH_ADDR_0_CH1); + if (UV) + pxp_writel(UV + offset, HW_PXP_INPUT_FETCH_ADDR_1_CH1); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1); + if (shift_offset) + pxp_writel(*(uint32_t *)&shift_offset, HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1); + pxp_writel(*(uint32_t *)&shift_width, HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1); + break; + default: + break; + } + + pxp_writel(pitch, HW_PXP_INPUT_FETCH_PITCH); + pxp_writel(BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_csc1_config(struct pxp_pixmap *input, + bool is_ycbcr) +{ + BUG_ON(!is_yuv(input->format)); + + if (!is_ycbcr) { + /* YUV -> RGB */ + pxp_writel(0x04030000, HW_PXP_CSC1_COEF0); + pxp_writel(0x01230208, HW_PXP_CSC1_COEF1); + pxp_writel(0x076b079c, HW_PXP_CSC1_COEF2); + + return 0; + } + + /* YCbCr -> RGB */ + pxp_writel(0x84ab01f0, HW_PXP_CSC1_COEF0); + pxp_writel(0x01980204, HW_PXP_CSC1_COEF1); + pxp_writel(0x0730079c, HW_PXP_CSC1_COEF2); + + return 0; +} + +static int pxp_rotation1_config(struct pxp_pixmap *input) +{ + uint8_t rotate; + + if (input->flip == PXP_H_FLIP) + pxp_writel(BF_PXP_CTRL_HFLIP1(1), HW_PXP_CTRL_SET); + else if (input->flip == PXP_V_FLIP) + pxp_writel(BF_PXP_CTRL_VFLIP1(1), HW_PXP_CTRL_SET); + + rotate = rotate_map(input->rotate); + pxp_writel(BF_PXP_CTRL_ROTATE1(rotate), HW_PXP_CTRL_SET); + + pxp_writel(BF_PXP_CTRL_ENABLE_ROTATE1(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_rotation0_config(struct pxp_pixmap *input) +{ + uint8_t rotate; + + if (input->flip == PXP_H_FLIP) + pxp_writel(BF_PXP_CTRL_HFLIP0(1), HW_PXP_CTRL_SET); + else if (input->flip == PXP_V_FLIP) + pxp_writel(BF_PXP_CTRL_VFLIP0(1), HW_PXP_CTRL_SET); + + rotate = rotate_map(input->rotate); + pxp_writel(BF_PXP_CTRL_ROTATE0(rotate), HW_PXP_CTRL_SET); + + pxp_writel(BF_PXP_CTRL_ENABLE_ROTATE0(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_csc2_config(struct pxp_pixmap *output) +{ + u32 coeffs[2][6] = { + { 0x00810042, 0x07DA0019, 0x007007B6, + 0x07A20070, 0x001007EE, 0x00800080 }, + { 0x0096004D, 0x05DA001D, 0x007005B6, + 0x057C009E, 0x000005E6, 0x00000000 }, + }; + u32 legacy_mode = 0; + + if (output->format == PXP_PIX_FMT_GREY || + output->format == PXP_PIX_FMT_GY04) { + pxp_writel(0x4, HW_PXP_CSC2_CTRL); + legacy_mode = 1; + } else if (is_yuv(output->format)) { + pxp_writel(0x6, HW_PXP_CSC2_CTRL); + legacy_mode = 0; + } + + if (is_yuv(output->format)) { + pxp_writel(coeffs[legacy_mode][0], HW_PXP_CSC2_COEF0); + pxp_writel(coeffs[legacy_mode][1], HW_PXP_CSC2_COEF1); + pxp_writel(coeffs[legacy_mode][2], HW_PXP_CSC2_COEF2); + pxp_writel(coeffs[legacy_mode][3], HW_PXP_CSC2_COEF3); + pxp_writel(coeffs[legacy_mode][4], HW_PXP_CSC2_COEF4); + pxp_writel(coeffs[legacy_mode][5], HW_PXP_CSC2_COEF5); + } + + pxp_writel(BF_PXP_CTRL_ENABLE_CSC2(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_out_config(struct pxp_pixmap *output) +{ + uint32_t offset, UV; + struct out_ctrl ctrl; + struct coordinate out_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_out_fmt(output->format); + offset = output->crop.y * output->pitch + + output->crop.x * (output->bpp >> 3); + + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_OUT_CTRL); + + pxp_writel(output->paddr, HW_PXP_OUT_BUF); + if (is_yuv(output->format) == 2) { + UV = (output->paddr_u) ? output->paddr_u : + output->paddr + output->width * output->height; + if ((output->format == PXP_PIX_FMT_NV16) || + (output->format == PXP_PIX_FMT_NV61)) + pxp_writel(UV + offset, HW_PXP_OUT_BUF2); + else + pxp_writel(UV + (offset >> 1), HW_PXP_OUT_BUF2); + } + + if (output->rotate == 90 || output->rotate == 270) { + out_lrc.y = output->width - 1; + out_lrc.x = output->height - 1; + } else { + out_lrc.x = output->width - 1; + out_lrc.y = output->height - 1; + } + + pxp_writel(*(uint32_t *)&out_lrc, HW_PXP_OUT_LRC); + + pxp_writel(output->pitch, HW_PXP_OUT_PITCH); + + /* set global alpha if necessary */ + if (output->g_alpha.global_alpha_enable) { + pxp_writel(output->g_alpha.global_alpha << 24, HW_PXP_OUT_CTRL_SET); + pxp_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT, HW_PXP_OUT_CTRL_SET); + } + + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_store_config(struct pxp_pixmap *output, + struct pxp_op_info *op) +{ + uint8_t combine_2ch, flags; + uint32_t in_fmt, out_fmt, offset, UV = 0; + uint64_t d_shift = 0; + struct store_d_mask d_mask[8]; + uint32_t store_ctrl, store_size, store_pitch, shift_ctrl; + + memset((void*)d_mask, 0x0, sizeof(*d_mask) * 8); + combine_2ch = (output->bpp == 64) ? 1 : 0; + store_ctrl = pxp_store_ctrl_config(output, STORE_MODE_NORMAL, + op->fill_en, combine_2ch); + store_size = pxp_store_size_config(output); + store_pitch = pxp_store_pitch_config(output, NULL); + + pxp_writel(store_ctrl, HW_PXP_INPUT_STORE_CTRL_CH0); + + if (output->flags) { + flags = fmt_store_from_common(output->format); + if (flags == STORE_NOOP) + shift_ctrl = pxp_store_shift_ctrl_config(output, 1); + else if (flags & STORE_SHIFT) { + in_fmt = is_yuv(output->format) ? PXP_PIX_FMT_YUV444 : + PXP_PIX_FMT_ARGB32; + out_fmt = (flags & STORE_SHRINK) ? PXP_PIX_FMT_YVU444 : + output->format; + d_shift = pxp_store_d_shift_calc(in_fmt, out_fmt, d_mask); + shift_ctrl = pxp_store_shift_ctrl_config(output, 0); + } else + shift_ctrl = pxp_store_shift_ctrl_config(output, 0); + + if (flags & STORE_SHIFT) { + pxp_writel((uint32_t)d_shift, HW_PXP_INPUT_STORE_D_SHIFT_L_CH0); + /* TODO use only 4 masks */ + pxp_writel(d_mask[0].d_mask_l, HW_PXP_INPUT_STORE_D_MASK0_L_CH0); + pxp_writel(d_mask[0].d_mask_h, HW_PXP_INPUT_STORE_D_MASK0_H_CH0); + pxp_writel(d_mask[1].d_mask_l, HW_PXP_INPUT_STORE_D_MASK1_L_CH0); + pxp_writel(d_mask[1].d_mask_h, HW_PXP_INPUT_STORE_D_MASK1_H_CH0); + pxp_writel(d_mask[2].d_mask_l, HW_PXP_INPUT_STORE_D_MASK2_L_CH0); + pxp_writel(d_mask[2].d_mask_h, HW_PXP_INPUT_STORE_D_MASK2_H_CH0); + pxp_writel(d_mask[3].d_mask_l, HW_PXP_INPUT_STORE_D_MASK3_L_CH0); + pxp_writel(d_mask[3].d_mask_h, HW_PXP_INPUT_STORE_D_MASK3_H_CH0); + } + } else + shift_ctrl = pxp_store_shift_ctrl_config(output, 1); + + pxp_writel(shift_ctrl, HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0); + pxp_writel(store_size, HW_PXP_INPUT_STORE_SIZE_CH0); + pxp_writel(store_pitch, HW_PXP_INPUT_STORE_PITCH); + if (op->fill_en) { + uint32_t lrc; + + lrc = (output->width - 1) | ((output->height - 1) << 16); + pxp_writel(op->fill_data, HW_PXP_INPUT_STORE_FILL_DATA_CH0); + + pxp_writel(0x1, HW_PXP_INPUT_FETCH_CTRL_CH0); + pxp_writel(0, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0); + pxp_writel(lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0); + } + + offset = output->crop.y * output->pitch + + output->crop.x * (output->bpp >> 3); + if (is_yuv(output->format == 2)) { + UV = output->paddr + output->width * output->height; + pxp_writel(UV + offset, HW_PXP_INPUT_STORE_ADDR_1_CH0); + } + pxp_writel(output->paddr + offset, HW_PXP_INPUT_STORE_ADDR_0_CH0); + + pxp_writel(BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_alpha_config(struct pxp_op_info *op, + uint8_t alpha_node) +{ + uint32_t as_ctrl; + struct pxp_alpha_ctrl alpha_ctrl; + struct pxp_alpha_info *alpha = &op->alpha_info; + struct pxp_alpha *s0_alpha, *s1_alpha; + + memset((void*)&alpha_ctrl, 0x0, sizeof(alpha_ctrl)); + + if (alpha_blending_version != PXP_ALPHA_BLENDING_V1) { + if (alpha->alpha_mode == ALPHA_MODE_ROP) { + switch (alpha_node) { + case PXP_2D_ALPHA0_S0: + as_ctrl = __raw_readl(pxp_reg_base + HW_PXP_AS_CTRL); + as_ctrl |= BF_PXP_AS_CTRL_ALPHA_CTRL(BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs); + as_ctrl |= BF_PXP_AS_CTRL_ROP(alpha->rop_type); + pxp_writel(as_ctrl, HW_PXP_AS_CTRL); + break; + case PXP_2D_ALPHA1_S0: + pxp_writel(BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE | + BF_PXP_ALPHA_B_CTRL_1_ROP(alpha->rop_type), + HW_PXP_ALPHA_B_CTRL_1); + pxp_writel(BF_PXP_CTRL_ENABLE_ALPHA_B(1), HW_PXP_CTRL_SET); + break; + default: + break; + } + + return 0; + } + + s0_alpha = &alpha->s0_alpha; + s1_alpha = &alpha->s1_alpha; + + alpha_ctrl.poter_duff_enable = 1; + + alpha_ctrl.s0_s1_factor_mode = s1_alpha->factor_mode; + alpha_ctrl.s0_global_alpha_mode = s0_alpha->global_alpha_mode; + alpha_ctrl.s0_alpha_mode = s0_alpha->alpha_mode; + alpha_ctrl.s0_color_mode = s0_alpha->color_mode; + + alpha_ctrl.s1_s0_factor_mode = s0_alpha->factor_mode; + alpha_ctrl.s1_global_alpha_mode = s1_alpha->global_alpha_mode; + alpha_ctrl.s1_alpha_mode = s1_alpha->alpha_mode; + alpha_ctrl.s1_color_mode = s1_alpha->color_mode; + + alpha_ctrl.s0_global_alpha = s0_alpha->global_alpha_value; + alpha_ctrl.s1_global_alpha = s1_alpha->global_alpha_value; + + switch (alpha_node) { + case PXP_2D_ALPHA0_S0: + pxp_writel(*(uint32_t *)&alpha_ctrl, HW_PXP_ALPHA_A_CTRL); + break; + case PXP_2D_ALPHA1_S0: + pxp_writel(*(uint32_t *)&alpha_ctrl, HW_PXP_ALPHA_B_CTRL); + pxp_writel(BF_PXP_CTRL_ENABLE_ALPHA_B(1), HW_PXP_CTRL_SET); + break; + default: + break; + } + } + + return 0; +} + +static void pxp_lut_config(struct pxp_op_info *op) +{ + struct pxp_task_info *task = to_pxp_task_info(op); + struct pxps *pxp = to_pxp_from_task(task); + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + int lut_op = proc_data->lut_transform; + u32 reg_val; + int i; + bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false; + u8 *cmap = proc_data->lut_map; + u32 entry_src; + u32 pix_val; + u8 entry[4]; + + /* + * If LUT already configured as needed, return... + * Unless CMAP is needed and it has been updated. + */ + if ((pxp->lut_state == lut_op) && + !(use_cmap && proc_data->lut_map_updated)) + return; + + if (lut_op == PXP_LUT_NONE) { + __raw_writel(BM_PXP_LUT_CTRL_BYPASS, + pxp->base + HW_PXP_LUT_CTRL); + } else if (((lut_op & PXP_LUT_INVERT) != 0) + && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) { + /* Fill out LUT table with inverted monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0xFF : 0x00; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_INVERT) != 0) { + /* Fill out LUT table with 8-bit inverted values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = ~entry_src & 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) { + /* Fill out LUT table with 8-bit monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if (use_cmap) { + /* Fill out LUT table using colormap values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) + entry[i] = cmap[pix_val + i]; + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } + + pxp_writel(BM_PXP_CTRL_ENABLE_ROTATE1 | BM_PXP_CTRL_ENABLE_ROTATE0 | + BM_PXP_CTRL_ENABLE_CSC2 | BM_PXP_CTRL_ENABLE_LUT, + HW_PXP_CTRL_SET); + + pxp->lut_state = lut_op; +} + +static int pxp_2d_task_config(struct pxp_pixmap *input, + struct pxp_pixmap *output, + struct pxp_op_info *op, + size_t nodes_used) +{ + uint8_t position = 0; + + + do { + position = find_next_bit((unsigned long *)&nodes_used, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_PS: + pxp_ps_config(input, output); + break; + case PXP_2D_AS: + pxp_as_config(input, output); + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + pxp_fetch_config(input, position); + break; + case PXP_2D_CSC1: + pxp_csc1_config(input, true); + break; + case PXP_2D_ROTATION1: + pxp_rotation1_config(input); + break; + case PXP_2D_ALPHA0_S0: + case PXP_2D_ALPHA1_S0: + pxp_alpha_config(op, position); + break; + case PXP_2D_ALPHA0_S1: + case PXP_2D_ALPHA1_S1: + break; + case PXP_2D_CSC2: + pxp_csc2_config(output); + break; + case PXP_2D_LUT: + pxp_lut_config(op); + break; + case PXP_2D_ROTATION0: + pxp_rotation0_config(input); + break; + case PXP_2D_OUT: + pxp_out_config(output); + break; + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + pxp_store_config(output, op); + break; + default: + break; + } + + position++; + } while (1); + + return 0; +} + +static void mux_config_helper(struct mux_config *path_ctrl, + struct edge_node *enode) +{ + uint32_t mux_val, mux_pos = 0; + + if (enode->mux_used) { + do { + mux_pos = find_next_bit(&enode->mux_used, + 32, mux_pos); + if (mux_pos >= 16) + break; + + mux_val = get_mux_val(&enode->muxes, mux_pos); + pr_debug("%s: mux_pos = %d, mux_val = %d\n", + __func__, mux_pos, mux_val); + set_mux_val(path_ctrl, mux_pos, mux_val); + + mux_pos++; + } while (1); + } +} + +static void pxp_2d_calc_mux(size_t nodes, struct mux_config *path_ctrl) +{ + struct edge_node *enode; + uint8_t from = 0, to = 0; + + do { + from = find_next_bit((unsigned long *)&nodes, 32, from); + if (from >= sizeof(uint32_t) * 8) + break; + + if (to != 0) { + enode = adj_list[to].first; + while (enode) { + if (enode->adjvex == from) { + mux_config_helper(path_ctrl, enode); + break; + } + enode = enode->next; + } + } + + to = find_next_bit((unsigned long *)&nodes, 32, from + 1); + if (to >= sizeof(uint32_t) * 8) + break; + + enode = adj_list[from].first; + while (enode) { + if (enode->adjvex == to) { + mux_config_helper(path_ctrl, enode); + break; + } + enode = enode->next; + } + + from = to + 1; + } while (1); +} + +/* + * Workaround to support RGB with alpha channel of PS engine + */ +static void pxp_config_alpha(struct pxp_pixmap *input) +{ + struct pxp_alpha_ctrl alpha_ctrl; + + memset((void*)&alpha_ctrl, 0x0, sizeof(alpha_ctrl)); + + switch (input->format) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_RGBA444: + alpha_ctrl.poter_duff_enable = 1; + alpha_ctrl.s0_s1_factor_mode = 1; + alpha_ctrl.s0_global_alpha_mode = 1; + break; + default: + break; + } + pxp_writel(*(uint32_t *)&alpha_ctrl, HW_PXP_ALPHA_A_CTRL); +} + +/* + * Workaround to support data copy when only use AS engine + * It will use MERGEAS raster operation and only remain pixel + * data from As engine + */ +static void pxp_as_alpha_config(struct pxp_pixmap *input) +{ + if (alpha_blending_version != PXP_ALPHA_BLENDING_NONE) + return; + + if (input->g_alpha.global_alpha_enable) + return; + + alpha_blending_version = PXP_ALPHA_BLENDING_V1; +} + +static int pxp_2d_op_handler(struct pxps *pxp) +{ + struct mux_config path_ctrl0; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_pixmap *input, *output, *input_s0, *input_s1; + size_t possible_inputs, possible_outputs; + size_t possible_inputs_s0, possible_inputs_s1; + size_t inputs_filter_s0, inputs_filter_s1; + size_t nodes_used = 0, nodes_in_path; + size_t partial_nodes_used = 0; + size_t nodes_used_s0 = 0, nodes_used_s1 = 0; + size_t nodes_in_path_s0, nodes_in_path_s1; + uint32_t val; + + output = &task->output[0]; + if (!output->pitch) + return -EINVAL; + + *(unsigned int*)&path_ctrl0 = 0xffffffff; + +reparse: + switch (task->input_num) { + case 0: + /* Fill operation: use input store engine */ + if (is_yuv(output->format) > 1) + return -EINVAL; + + if (output->bpp > 32) + return -EINVAL; + + nodes_used = 1 << PXP_2D_INPUT_STORE0; + pxp_2d_task_config(NULL, output, op, nodes_used); + break; + case 1: + /* No Composite */ + possible_inputs = (1 << PXP_2D_PS) | + (1 << PXP_2D_AS) | + (1 << PXP_2D_INPUT_FETCH0); + possible_outputs = (1 << PXP_2D_OUT) | + (1 << PXP_2D_INPUT_STORE0); + + input = &task->input[0]; + if (!input->pitch) + return -EINVAL; + + if (input->rotate || input->flip) { + input->flags |= IN_NEED_ROTATE_FLIP; + output->rotate = input->rotate; + output->flip = input->flip; + } + + if (!is_yuv(input->format) != !is_yuv(output->format)) + input->flags |= IN_NEED_CSC; + else if (input->format != output->format) + input->flags |= IN_NEED_FMT_UNIFIED; + + if ((input->rotate == 90) || (input->rotate == 270)) { + if ((input->crop.width != output->crop.height) || + (input->crop.height != output->crop.width)) + input->flags |= IN_NEED_SCALE; + } else { + if ((input->crop.width != output->crop.width) || + (input->crop.height != output->crop.height)) + input->flags |= IN_NEED_SCALE; + } + + if (input->flags) { + /* only ps has scaling function */ + if ((input->flags & IN_NEED_SCALE) == IN_NEED_SCALE) + possible_inputs = 1 << PXP_2D_PS; + output->flags |= (output->bpp < 32) ? OUT_NEED_SHRINK : + OUT_NEED_SHIFT; + } + + filter_possible_inputs(input, &possible_inputs); + filter_possible_outputs(output, &possible_outputs); + + if (!possible_inputs || !possible_outputs) { + dev_err(&pxp->pdev->dev, "unsupport 2d operation\n"); + return -EINVAL; + } + + if (proc_data->lut_transform) + nodes_used |= (1 << PXP_2D_LUT); + + nodes_in_path = find_best_path(possible_inputs, + possible_outputs, + input, &nodes_used); + + filter_nodes_by_inputs_outputs(&nodes_in_path, &nodes_used); + + pr_debug("%s: nodes_in_path = 0x%x, nodes_used = 0x%x\n", + __func__, (u32)nodes_in_path, (u32)nodes_used); + if (!nodes_used) { + dev_err(&pxp->pdev->dev, "unsupport 2d operation\n"); + return -EINVAL; + } + + /* If use input fetch0, should use + * alpha b instead of alpha a */ + if (nodes_in_path & (1 << PXP_2D_ALPHA0_S0)) { + if (nodes_in_path & (1 << PXP_2D_INPUT_FETCH0)) { + clear_bit(PXP_2D_ALPHA0_S0, + (unsigned long *)&nodes_in_path); + set_bit(PXP_2D_ALPHA1_S1, + (unsigned long *)&nodes_in_path); + } + } + + /* In this case input read in + * by input fetch engine + */ + if ((nodes_in_path & (1 << PXP_2D_ALPHA1_S1)) || + (nodes_in_path & (1 << PXP_2D_ALPHA1_S0))) { + memcpy(&task->input[1], input, sizeof(*input)); + if (input->rotate == 90 || input->rotate == 270) { + uint32_t temp; + + input = &task->input[1]; + input->rotate = 0; + input->flags = 0; + temp = input->width; + input->width = input->height; + input->height = temp; + input->pitch = input->width * (input->bpp >> 3); + temp = input->crop.width; + input->crop.width = input->crop.height; + input->crop.height = temp; + } + + op->alpha_info.alpha_mode = ALPHA_MODE_ROP; + /* s0 AND s1 */ + op->alpha_info.rop_type = 0x0; + task->input_num = 2; + goto reparse; + } + + if (nodes_used & (1 << PXP_2D_PS)) + pxp_config_alpha(input); + + if (nodes_used & (1 << PXP_2D_AS)) { + /* Need to select mux3 port 0 when use AS engine */ + path_ctrl0.mux3_sel = 0; + pxp_as_alpha_config(input); + } + + pxp_2d_calc_mux(nodes_in_path, &path_ctrl0); + pr_debug("%s: path_ctrl0 = 0x%x\n", + __func__, *(uint32_t *)&path_ctrl0); + pxp_2d_task_config(input, output, op, nodes_used); + + if (is_yuv(input->format) && is_yuv(output->format)) { + val = readl(pxp_reg_base + HW_PXP_CSC1_COEF0); + val |= (BF_PXP_CSC1_COEF0_YCBCR_MODE(1) | + BF_PXP_CSC1_COEF0_BYPASS(1)); + pxp_writel(val, HW_PXP_CSC1_COEF0); + } + break; + case 2: + /* Composite */ + input_s0 = &task->input[0]; + input_s1 = &task->input[1]; + if (!input_s0->pitch || !input_s1->pitch) + return -EINVAL; + + possible_inputs_s0 = (1 << PXP_2D_PS) | + (1 << PXP_2D_INPUT_FETCH0) | + (1 << PXP_2D_INPUT_FETCH1); + possible_inputs_s1 = (1 << PXP_2D_AS) | + (1 << PXP_2D_INPUT_FETCH0); + possible_outputs = (1 << PXP_2D_OUT) | + (1 << PXP_2D_INPUT_STORE0); + + if (input_s0->rotate || input_s0->flip) { + input_s0->flags |= IN_NEED_ROTATE_FLIP; + output->rotate = input_s0->rotate; + output->flip = input_s0->flip; + } + if (input_s1->rotate || input_s1->flip) { + input_s1->flags |= IN_NEED_ROTATE_FLIP; + clear_bit(PXP_2D_AS, + (unsigned long *)&possible_inputs_s1); + } + + if (is_yuv(input_s0->format) && is_yuv(input_s1->format)) + return -EINVAL; + + if (is_yuv(input_s0->format)){ + /* need do yuv -> rgb conversion by csc1 */ + possible_inputs_s0 = 1 << PXP_2D_PS; + input_s0->flags |= IN_NEED_CSC; + } else if (is_yuv(input_s1->format)) { + possible_inputs_s1 = 1 << PXP_2D_PS; + input_s1->flags |= IN_NEED_CSC; + } + + filter_possible_inputs(input_s0, &possible_inputs_s0); + filter_possible_inputs(input_s1, &possible_inputs_s1); + + if (!possible_inputs_s0 || !possible_inputs_s1) + return -EINVAL; + + filter_possible_outputs(output, &possible_outputs); + if (!possible_outputs) + return -EINVAL; + + pr_debug("%s: poss_s0 = 0x%x, poss_s1 = 0x%x, poss_out = 0x%x\n", + __func__, (u32)possible_inputs_s0, (u32)possible_inputs_s1, (u32)possible_outputs); + + inputs_filter_s0 = possible_inputs_s0; + inputs_filter_s1 = possible_inputs_s1; + + /* Using alpha0, possible cases: + * 1. PS --> S0, AS --> S1; + */ + if (possible_inputs_s1 & (1 << PXP_2D_AS)) { + clear_bit(PXP_2D_INPUT_FETCH0, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_FETCH1, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_STORE0, + (unsigned long *)&possible_outputs); + + if (!possible_inputs_s0 || !possible_outputs) + goto alpha1; + + nodes_in_path_s0 = find_best_path(possible_inputs_s0, + 1 << PXP_2D_ALPHA0_S0, + input_s0, + &partial_nodes_used); + if (!nodes_in_path_s0) + goto alpha1; + + nodes_used_s0 |= partial_nodes_used; + partial_nodes_used = 0; + + if (is_yuv(output->format)) + set_bit(PXP_2D_CSC2, + (unsigned long *)&partial_nodes_used); + if (output->rotate || output->flip) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&partial_nodes_used); + + nodes_in_path_s0 |= find_best_path(1 << PXP_2D_ALPHA0_S0, + possible_outputs, + input_s0, + &partial_nodes_used); + if (!(nodes_in_path_s0 & possible_outputs)) + goto alpha1; + nodes_used_s0 |= partial_nodes_used; + + possible_inputs_s1 = (1 << PXP_2D_AS); + nodes_in_path_s1 = find_best_path(possible_inputs_s1, + 1 << PXP_2D_ALPHA0_S1, + input_s1, + &nodes_used_s1); + if (!nodes_in_path_s1) + goto alpha1; + + goto config; + } +alpha1: + partial_nodes_used = 0; + possible_inputs_s0 = inputs_filter_s0; + possible_inputs_s1 = inputs_filter_s1; + + /* Using alpha1, possible cases: + * 1. FETCH1 --> S0, FETCH0 --> S1; + */ + clear_bit(PXP_2D_PS, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_FETCH0, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_OUT, + (unsigned long *)&possible_outputs); + + if (!possible_inputs_s0 || !possible_outputs) + return -EINVAL; + + nodes_in_path_s0 = find_best_path(possible_inputs_s0, + 1 << PXP_2D_ALPHA1_S0, + input_s0, + &partial_nodes_used); + pr_debug("%s: nodes_in_path_s0 = 0x%x\n", __func__, (u32)nodes_in_path_s0); + BUG_ON(!nodes_in_path_s0); + + nodes_used_s0 |= partial_nodes_used; + if ((nodes_used_s0 & (1 << PXP_2D_INPUT_FETCH0)) || + (nodes_used_s0 & (1 << PXP_2D_INPUT_FETCH1))) + clear_bit(PXP_2D_OUT, (unsigned long *)&possible_outputs); + else + clear_bit(PXP_2D_INPUT_STORE0, + (unsigned long *)&possible_outputs); + partial_nodes_used = 0; + + if (is_yuv(output->format)) + set_bit(PXP_2D_CSC2, + (unsigned long *)&partial_nodes_used); + if (output->rotate || output->flip) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&partial_nodes_used); + + nodes_in_path_s0 |= find_best_path(1 << PXP_2D_ALPHA1_S0, + possible_outputs, + input_s0, + &partial_nodes_used); + BUG_ON(!(nodes_in_path_s0 & possible_outputs)); + nodes_used_s0 |= partial_nodes_used; + pr_debug("%s: nodes_in_path_s0 = 0x%x, nodes_used_s0 = 0x%x\n", + __func__, (u32)nodes_in_path_s0, (u32)nodes_used_s0); + + clear_bit(PXP_2D_AS, + (unsigned long *)&possible_inputs_s1); + BUG_ON(!possible_inputs_s1); + + nodes_in_path_s1 = find_best_path(possible_inputs_s1, + 1 << PXP_2D_ALPHA1_S1, + input_s1, + &nodes_used_s1); + pr_debug("%s: poss_s1 = 0x%x, nodes_used_s1 = 0x%x\n", + __func__, (u32)possible_inputs_s1, (u32)nodes_used_s1); + BUG_ON(!nodes_in_path_s1); + /* To workaround an IC bug */ + path_ctrl0.mux4_sel = 0x0; +config: + if (nodes_in_path_s0 & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_in_path_s0); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_in_path_s0); + } + + pr_debug("%s: nodes_in_path_s0 = 0x%x, nodes_used_s0 = 0x%x, nodes_in_path_s1 = 0x%x, nodes_used_s1 = 0x%x\n", + __func__, (u32)nodes_in_path_s0, (u32)nodes_used_s0, (u32)nodes_in_path_s1, (u32)nodes_used_s1); + pxp_2d_calc_mux(nodes_in_path_s0, &path_ctrl0); + pxp_2d_calc_mux(nodes_in_path_s1, &path_ctrl0); + + pr_debug("%s: s0 paddr = 0x%p, s1 paddr = 0x%p, out paddr = 0x%p\n", + __func__, (void *)input_s0->paddr, (void *)input_s1->paddr, (void *)output->paddr); + + if (nodes_used_s0 & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_used_s0); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_used_s0); + } + + pxp_2d_task_config(input_s0, output, op, nodes_used_s0); + pxp_2d_task_config(input_s1, output, op, nodes_used_s1); + break; + default: + break; + } + + __raw_writel(proc_data->bgcolor, + pxp->base + HW_PXP_PS_BACKGROUND_0); + pxp_set_colorkey(pxp); + + if (proc_data->lut_transform && pxp_is_v3(pxp)) + set_mux(&path_ctrl0); + + pr_debug("%s: path_ctrl0 = 0x%x\n", + __func__, *(uint32_t *)&path_ctrl0); + pxp_writel(*(uint32_t *)&path_ctrl0, HW_PXP_DATA_PATH_CTRL0); + + return 0; +} + +/** + * pxp_config() - configure PxP for a processing task + * @pxps: PXP context. + * @pxp_chan: PXP channel. + * @return: 0 on success or negative error code on failure. + */ +static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) +{ + int ret = 0; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf_data->proc_data; + + switch (op->op_type) { + case PXP_OP_TYPE_2D: + pxp_writel(0xffffffff, HW_PXP_OUT_AS_ULC); + pxp_writel(0x0, HW_PXP_OUT_AS_LRC); + pxp_writel(0xffffffff, HW_PXP_OUT_PS_ULC); + pxp_writel(0x0, HW_PXP_OUT_PS_LRC); + pxp_writel(0x0, HW_PXP_INPUT_FETCH_PITCH); + pxp_writel(0x40000000, HW_PXP_CSC1_COEF0); + ret = pxp_2d_op_handler(pxp); + break; + case PXP_OP_TYPE_DITHER: + pxp_dithering_process(pxp); + if (pxp_is_v3p(pxp)) { + __raw_writel( + BM_PXP_CTRL_ENABLE | + BM_PXP_CTRL_ENABLE_DITHER | + BM_PXP_CTRL_ENABLE_CSC2 | + BM_PXP_CTRL_ENABLE_LUT | + BM_PXP_CTRL_ENABLE_ROTATE0 | + BM_PXP_CTRL_ENABLE_PS_AS_OUT, + pxp->base + HW_PXP_CTRL_SET); + return 0; + } + break; + case PXP_OP_TYPE_WFE_A: + pxp_luts_deactivate(pxp, proc_data->lut_sels); + + if (proc_data->lut_cleanup == 0) { + /* We should enable histogram in standard mode + * in wfe_a processing for waveform mode selection + */ + pxp_histogram_enable(pxp, pxp_conf_data->wfe_a_fetch_param[0].width, + pxp_conf_data->wfe_a_fetch_param[0].height); + + pxp_luts_activate(pxp, (u64)proc_data->lut_status_1 | + ((u64)proc_data->lut_status_2 << 32)); + + /* collision detection should be always enable in standard mode */ + pxp_collision_detection_enable(pxp, pxp_conf_data->wfe_a_fetch_param[0].width, + pxp_conf_data->wfe_a_fetch_param[0].height); + } + + if (pxp->devdata && pxp->devdata->pxp_wfe_a_configure) + pxp->devdata->pxp_wfe_a_configure(pxp); + if (pxp->devdata && pxp->devdata->pxp_wfe_a_process) + pxp->devdata->pxp_wfe_a_process(pxp); + break; + case PXP_OP_TYPE_WFE_B: + pxp_wfe_b_configure(pxp); + pxp_wfe_b_process(pxp); + break; + default: + /* Unsupport */ + ret = -EINVAL; + pr_err("Invalid pxp operation type passed\n"); + break; + } + + return ret; +} + +static void pxp_clk_enable(struct pxps *pxp) +{ + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_ON) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + pm_runtime_get_sync(pxp->dev); + clk_prepare_enable(pxp->ipg_clk); + clk_prepare_enable(pxp->axi_clk); + + if (pxp->devdata && pxp->devdata->pxp_restart) + pxp->devdata->pxp_restart(pxp); + + pxp->clk_stat = CLK_STAT_ON; + + mutex_unlock(&pxp->clk_mutex); +} + +static void pxp_clk_disable(struct pxps *pxp) +{ + unsigned long flags; + + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_OFF) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + spin_lock_irqsave(&pxp->lock, flags); + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) { + pxp->clk_stat = CLK_STAT_OFF; + spin_unlock_irqrestore(&pxp->lock, flags); + clk_disable_unprepare(pxp->ipg_clk); + clk_disable_unprepare(pxp->axi_clk); + pm_runtime_put_sync_suspend(pxp->dev); + } else + spin_unlock_irqrestore(&pxp->lock, flags); + + mutex_unlock(&pxp->clk_mutex); +} + +static inline void clkoff_callback(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + + pxp_clk_disable(pxp); +} + +static void pxp_clkoff_timer(struct timer_list *t) +{ + struct pxps *pxp = from_timer(pxp, t, clk_timer); + + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) + schedule_work(&pxp->work); + else + mod_timer(&pxp->clk_timer, + jiffies + msecs_to_jiffies(timeout_in_ms)); +} + +static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); +} + +static int convert_param_to_pixmap(struct pxp_pixmap *pixmap, + struct pxp_layer_param *param) +{ + if (!param->width || !param->height) + return -EINVAL; + + pixmap->width = param->width; + pixmap->height = param->height; + pixmap->format = param->pixel_fmt; + pixmap->bpp = get_bpp_from_fmt(pixmap->format); + pixmap->paddr = param->paddr; + pixmap->paddr_u = param->paddr_u; + pixmap->paddr_v = param->paddr_v; + + if (pxp_legacy) { + pixmap->pitch = (param->stride) ? (param->stride * pixmap->bpp >> 3) : + (param->width * pixmap->bpp >> 3); + } else { + if (!param->stride || (param->stride == param->width)) + pixmap->pitch = param->width * pixmap->bpp >> 3; + else + pixmap->pitch = param->stride; + } + + pixmap->crop.x = param->crop.left; + pixmap->crop.y = param->crop.top; + pixmap->crop.width = param->crop.width; + pixmap->crop.height = param->crop.height; + + pixmap->g_alpha.color_key_enable = param->color_key_enable; + pixmap->g_alpha.combine_enable = param->combine_enable; + pixmap->g_alpha.global_alpha_enable = param->global_alpha_enable; + pixmap->g_alpha.global_override = param->global_override; + pixmap->g_alpha.global_alpha = param->global_alpha; + pixmap->g_alpha.alpha_invert = param->alpha_invert; + pixmap->g_alpha.local_alpha_enable = param->local_alpha_enable; + pixmap->g_alpha.comp_mask = param->comp_mask; + + return 0; +} + +/* called with pxp_chan->lock held */ +static void __pxpdma_dostart(struct pxp_channel *pxp_chan) +{ + struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_alpha_info *alpha = &op->alpha_info; + struct pxp_layer_param *param = NULL; + struct pxp_pixmap *input, *output; + int i = 0, ret; + bool combine_enable = false; + int delta_x, delta_y; + + memset(&pxp->pxp_conf_state.s0_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.out_param, 0, sizeof(struct pxp_layer_param)); + memset(pxp->pxp_conf_state.ol_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.proc_data, 0, sizeof(struct pxp_proc_data)); + + memset(task, 0, sizeof(*task)); + /* S0 */ + desc = list_first_entry(&head, struct pxp_tx_desc, list); + memcpy(&pxp->pxp_conf_state.s0_param, + &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); + memcpy(&pxp->pxp_conf_state.proc_data, + &desc->proc_data, sizeof(struct pxp_proc_data)); + + if (proc_data->combine_enable) + alpha_blending_version = PXP_ALPHA_BLENDING_V2; + else + alpha_blending_version = PXP_ALPHA_BLENDING_NONE; + + pxp_legacy = (proc_data->pxp_legacy) ? true : false; + + param = &pxp->pxp_conf_state.s0_param; + if (param->pixel_fmt == PXP_PIX_FMT_YUV420P || + param->pixel_fmt == PXP_PIX_FMT_YVU420P) { + delta_x = proc_data->srect.left - ALIGN_DOWN(proc_data->srect.left, 2); + delta_y = proc_data->srect.top - ALIGN_DOWN(proc_data->srect.top, 2); + + proc_data->srect.left = ALIGN_DOWN(proc_data->srect.left, 2); + proc_data->srect.top = ALIGN_DOWN(proc_data->srect.top, 2); + + proc_data->srect.width = proc_data->srect.width + delta_x; + proc_data->srect.height = proc_data->srect.height + delta_y; + } + + /* Save PxP configuration */ + list_for_each_entry(child, &desc->tx_list, list) { + if (i == 0) { /* Output */ + memcpy(&pxp->pxp_conf_state.out_param, + &child->layer_param.out_param, + sizeof(struct pxp_layer_param)); + } else if (i == 1) { /* Overlay */ + memcpy(&pxp->pxp_conf_state.ol_param[i - 1], + &child->layer_param.ol_param, + sizeof(struct pxp_layer_param)); + if (pxp->pxp_conf_state.ol_param[i - 1].width != 0 && + pxp->pxp_conf_state.ol_param[i - 1].height != 0) { + if (pxp->pxp_conf_state.ol_param[i - 1].combine_enable) + alpha_blending_version = PXP_ALPHA_BLENDING_V1; + } + } + + if (proc_data->engine_enable & PXP_ENABLE_DITHER) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_FETCH0) + memcpy(&pxp->pxp_conf_state.dither_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_FETCH1) + memcpy(&pxp->pxp_conf_state.dither_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_STORE0) + memcpy(&pxp->pxp_conf_state.dither_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_STORE1) + memcpy(&pxp->pxp_conf_state.dither_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_DITHER; + } + + if (proc_data->engine_enable & PXP_ENABLE_WFE_A) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_FETCH0) + memcpy(&pxp->pxp_conf_state.wfe_a_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_FETCH1) + memcpy(&pxp->pxp_conf_state.wfe_a_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_STORE0) + memcpy(&pxp->pxp_conf_state.wfe_a_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_STORE1) + memcpy(&pxp->pxp_conf_state.wfe_a_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_WFE_A; + } + + if (proc_data->engine_enable & PXP_ENABLE_WFE_B) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_FETCH0) + memcpy(&pxp->pxp_conf_state.wfe_b_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_FETCH1) + memcpy(&pxp->pxp_conf_state.wfe_b_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_STORE0) + memcpy(&pxp->pxp_conf_state.wfe_b_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_STORE1) + memcpy(&pxp->pxp_conf_state.wfe_b_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_WFE_B; + } + + i++; + } + + if (!op->op_type) { + op->op_type = PXP_OP_TYPE_2D; + + if ((alpha_blending_version == PXP_ALPHA_BLENDING_V1) || + (alpha_blending_version == PXP_ALPHA_BLENDING_V2)) + combine_enable = true; + + if (combine_enable) + task->input_num = 2; + else if (proc_data->fill_en) + task->input_num = 0; + else + task->input_num = 1; + + output = &task->output[0]; + switch (task->input_num) { + case 0: + op->fill_en = 1; + op->fill_data = proc_data->bgcolor; + break; + case 1: + param = &pxp->pxp_conf_state.s0_param; + input = &task->input[0]; + + ret = convert_param_to_pixmap(input, param); + if (ret < 0) { + param = &pxp->pxp_conf_state.ol_param[0]; + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + } else { + input->crop.x = proc_data->srect.left; + input->crop.y = proc_data->srect.top; + input->crop.width = proc_data->srect.width; + input->crop.height = proc_data->srect.height; + } + + input->rotate = proc_data->rotate; + input->flip = (proc_data->hflip) ? PXP_H_FLIP : + (proc_data->vflip) ? PXP_V_FLIP : 0; + break; + case 2: + /* s0 */ + param = &pxp->pxp_conf_state.s0_param; + input = &task->input[0]; + + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + input->crop.x = proc_data->srect.left; + input->crop.y = proc_data->srect.top; + input->crop.width = proc_data->srect.width; + input->crop.height = proc_data->srect.height; + alpha->s0_alpha = param->alpha; + + input->rotate = proc_data->rotate; + input->flip = (proc_data->hflip) ? PXP_H_FLIP : + (proc_data->vflip) ? PXP_V_FLIP : 0; + + /* overlay */ + param = &pxp->pxp_conf_state.ol_param[0]; + input = &task->input[1]; + + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + alpha->s1_alpha = param->alpha; + alpha->alpha_mode = proc_data->alpha_mode; + break; + } + + param = &pxp->pxp_conf_state.out_param; + ret = convert_param_to_pixmap(output, param); + BUG_ON(ret < 0); + + output->crop.x = proc_data->drect.left; + output->crop.y = proc_data->drect.top; + output->crop.width = proc_data->drect.width; + output->crop.height = proc_data->drect.height; + } + + pr_debug("%s:%d S0 w/h %d/%d paddr %p\n", __func__, __LINE__, + pxp->pxp_conf_state.s0_param.width, + pxp->pxp_conf_state.s0_param.height, + (void *)pxp->pxp_conf_state.s0_param.paddr); + pr_debug("%s:%d S0 crop (top, left)=(%d, %d), (width, height)=(%d, %d)\n", + __func__, __LINE__, + pxp->pxp_conf_state.s0_param.crop.top, + pxp->pxp_conf_state.s0_param.crop.left, + pxp->pxp_conf_state.s0_param.crop.width, + pxp->pxp_conf_state.s0_param.crop.height); + pr_debug("%s:%d OUT w/h %d/%d paddr %p\n", __func__, __LINE__, + pxp->pxp_conf_state.out_param.width, + pxp->pxp_conf_state.out_param.height, + (void *)pxp->pxp_conf_state.out_param.paddr); +} + +static int pxpdma_dostart_work(struct pxps *pxp) +{ + int ret; + struct pxp_channel *pxp_chan = NULL; + unsigned long flags; + dma_async_tx_callback callback; + void *callback_param; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *child, *_child; + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + + spin_lock_irqsave(&pxp->lock, flags); + + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + __pxpdma_dostart(pxp_chan); + + /* Configure PxP */ + ret = pxp_config(pxp, pxp_chan); + if (ret) { + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + callback(callback_param); + + /* Unsupport operation */ + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + spin_unlock_irqrestore(&pxp->lock, flags); + return -EINVAL; + } + + if (proc_data->working_mode & PXP_MODE_STANDARD) { + if(!pxp_is_v3p(pxp) || !(proc_data->engine_enable & PXP_ENABLE_DITHER)) + pxp_start2(pxp); + } else + pxp_start(pxp); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return 0; +} + +static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct pxps *pxp) +{ + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + do { + desc = pxpdma_first_queued(pxp_chan); + spin_lock_irqsave(&pxp->lock, flags); + list_move_tail(&desc->list, &head); + spin_unlock_irqrestore(&pxp->lock, flags); + } while (!list_empty(&pxp_chan->queue)); +} + +static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct pxp_tx_desc *desc = to_tx_desc(tx); + struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); + dma_cookie_t cookie; + + dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); + + /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ + spin_lock(&pxp_chan->lock); + + cookie = pxp_chan->dma_chan.cookie; + + if (++cookie < 0) + cookie = 1; + + /* from dmaengine.h: "last cookie value returned to client" */ + pxp_chan->dma_chan.cookie = cookie; + tx->cookie = cookie; + + /* Here we add the tx descriptor to our PxP task queue. */ + list_add_tail(&desc->list, &pxp_chan->queue); + + spin_unlock(&pxp_chan->lock); + + dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); + + return cookie; +} + +/** + * pxp_init_channel() - initialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_init_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + int ret = 0; + + /* + * We are using _virtual_ channel here. + * Each channel contains all parameters of corresponding layers + * for one transaction; each layer is represented as one descriptor + * (i.e., pxp_tx_desc) here. + */ + + INIT_LIST_HEAD(&pxp_chan->queue); + + return ret; +} + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = dev_id; + struct pxp_channel *pxp_chan; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child, *_child; + dma_async_tx_callback callback; + void *callback_param; + unsigned long flags; + u32 hist_status = 0; + int pxp_irq_status = 0; + + dump_pxp_reg(pxp); + + if (__raw_readl(pxp->base + HW_PXP_STAT) & BM_PXP_STAT_IRQ0) + __raw_writel(BM_PXP_STAT_IRQ0, pxp->base + HW_PXP_STAT_CLR); + else { + int irq_clr = 0; + + pxp_irq_status = __raw_readl(pxp->base + HW_PXP_IRQ); + BUG_ON(!pxp_irq_status); + + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH1_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH1_STORE_IRQ; + /*XXX other irqs status clear should be added below */ + + __raw_writel(irq_clr, pxp->base + HW_PXP_IRQ_CLR); + + pxp_writel(BM_PXP_CTRL_ENABLE, HW_PXP_CTRL_CLR); + } + + if (pxp->devdata && pxp->devdata->version < PXP_V3_IMX93) { + pxp_collision_status_report(pxp, &col_info); + pxp_histogram_status_report(pxp, &hist_status); + /*XXX before a new update operation, we should + * always clear all the collision information + */ + pxp_collision_detection_disable(pxp); + pxp_histogram_disable(pxp); + } + + pxp_writel(0x0, HW_PXP_CTRL); + pxp_soft_reset(pxp); + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + + spin_lock_irqsave(&pxp->lock, flags); + if (list_empty(&head)) { + pxp->pxp_ongoing = 0; + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + /* Get descriptor and call callback */ + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + pxp_chan->completed = desc->txd.cookie; + + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + /* Send histogram status back to caller */ + desc->hist_status = hist_status; + + if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) + callback(callback_param); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + complete(&pxp->complete); + pxp->pxp_ongoing = 0; + mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms)); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +/* allocate/free dma tx descriptor dynamically*/ +static struct pxp_tx_desc *pxpdma_desc_alloc(struct pxp_channel *pxp_chan) +{ + struct pxp_tx_desc *desc = NULL; + struct dma_async_tx_descriptor *txd = NULL; + + desc = kmem_cache_alloc(tx_desc_cache, GFP_KERNEL | __GFP_ZERO); + if (desc == NULL) + return NULL; + + INIT_LIST_HEAD(&desc->list); + INIT_LIST_HEAD(&desc->tx_list); + txd = &desc->txd; + dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); + txd->tx_submit = pxp_tx_submit; + + return desc; +} + + +/* Allocate and initialise a transfer descriptor. */ +static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, + struct scatterlist + *sgl, + unsigned int sg_len, + enum + dma_transfer_direction + direction, + unsigned long tx_flags, + void *context) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *pos = NULL, *next = NULL; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *first = NULL, *prev = NULL; + struct scatterlist *sg; + dma_addr_t phys_addr; + int i; + + if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) { + dev_err(chan->device->dev, "Invalid DMA direction %d!\n", + direction); + return NULL; + } + + if (unlikely(sg_len < 2)) + return NULL; + + for_each_sg(sgl, sg, sg_len, i) { + desc = pxpdma_desc_alloc(pxp_chan); + if (!desc) { + dev_err(chan->device->dev, "no enough memory to allocate tx descriptor\n"); + + if (first) { + list_for_each_entry_safe(pos, next, &first->tx_list, list) { + list_del_init(&pos->list); + kmem_cache_free(tx_desc_cache, (void*)pos); + } + list_del_init(&first->list); + kmem_cache_free(tx_desc_cache, (void*)first); + } + + return NULL; + } + + phys_addr = sg_dma_address(sg); + + if (!first) { + first = desc; + + desc->layer_param.s0_param.paddr = phys_addr; + } else { + list_add_tail(&desc->list, &first->tx_list); + prev->next = desc; + desc->next = NULL; + + if (i == 1) + desc->layer_param.out_param.paddr = phys_addr; + else + desc->layer_param.ol_param.paddr = phys_addr; + } + + prev = desc; + } + + pxp->pxp_conf_state.layer_nr = sg_len; + first->txd.flags = tx_flags; + first->len = sg_len; + pr_debug("%s:%d first %p, first->len %d, flags %08x\n", + __func__, __LINE__, first, first->len, first->txd.flags); + + return &first->txd; +} + +static void pxp_issue_pending(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + + spin_lock(&pxp_chan->lock); + + if (list_empty(&pxp_chan->queue)) { + spin_unlock(&pxp_chan->lock); + return; + } + + pxpdma_dequeue(pxp_chan, pxp); + pxp_chan->status = PXP_CHANNEL_READY; + + spin_unlock(&pxp_chan->lock); + + pxp_clk_enable(pxp); + wake_up_interruptible(&pxp->thread_waitq); +} + +static void __pxp_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + pxp_chan->status = PXP_CHANNEL_INITIALIZED; +} + +static int pxp_device_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + __pxp_terminate_all(chan); + spin_unlock(&pxp_chan->lock); + + return 0; +} + +static int pxp_alloc_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + int ret; + + /* dmaengine.c now guarantees to only offer free channels */ + BUG_ON(chan->client_count > 1); + WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); + + chan->cookie = 1; + pxp_chan->completed = -ENXIO; + + pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); + ret = pxp_init_channel(pxp_dma, pxp_chan); + if (ret < 0) + goto err_chan; + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", + chan->chan_id, pxp_chan->eof_irq); + + return ret; + +err_chan: + return ret; +} + +static void pxp_free_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + + __pxp_terminate_all(chan); + + pxp_chan->status = PXP_CHANNEL_FREE; + + spin_unlock(&pxp_chan->lock); +} + +static enum dma_status pxp_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + if (cookie != chan->cookie) + return DMA_ERROR; + + if (txstate) { + txstate->last = pxp_chan->completed; + txstate->used = chan->cookie; + txstate->residue = 0; + } + return DMA_COMPLETE; +} + +static void pxp_data_path_config_v3p(struct pxps *pxp) +{ + u32 val = 0; + + __raw_writel( + BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1)| + BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(1)| + BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(0), + pxp->base + HW_PXP_DATA_PATH_CTRL0); + + /* + * MUX17: HIST_B as histogram: 0: output buffer, 1: wfe_store + * MUX16: HIST_A as collision: 0: output buffer, 1: wfe_store + */ + if (pxp_is_v3(pxp)) + val = BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1)| + BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1)| + BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(1); + __raw_writel(val, pxp->base + HW_PXP_DATA_PATH_CTRL1); +} + +static void pxp_soft_reset(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_SET); + while (!(__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_CLKGATE)) + dev_dbg(pxp->dev, "%s: wait for clock gate off", __func__); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); +} + +static void pxp_sram_init(struct pxps *pxp, u32 select, + void *buffer_addr, u32 length) +{ + u32 i; + + __raw_writel( + BF_PXP_INIT_MEM_CTRL_ADDR(0) | + BF_PXP_INIT_MEM_CTRL_SELECT(select) | + BF_PXP_INIT_MEM_CTRL_START(1), + pxp->base + HW_PXP_INIT_MEM_CTRL); + + if ((select == WFE_A) || (select == WFE_B)) { + for (i = 0; i < length / 2; i++) { + __raw_writel(*(((u32*)buffer_addr) + 2 * i + 1), + pxp->base + HW_PXP_INIT_MEM_DATA_HIGH); + + __raw_writel(*(((u32*)buffer_addr) + 2 * i), + pxp->base + HW_PXP_INIT_MEM_DATA); + } + } else { + for (i = 0; i < length; i++) { + __raw_writel(*(((u32*) buffer_addr) + i), + pxp->base + HW_PXP_INIT_MEM_DATA); + } + } + + __raw_writel( + BF_PXP_INIT_MEM_CTRL_ADDR(0) | + BF_PXP_INIT_MEM_CTRL_SELECT(select) | + BF_PXP_INIT_MEM_CTRL_START(0), + pxp->base + HW_PXP_INIT_MEM_CTRL); +} + +/* + * wfe a configuration + * configure wfe a engine for waveform processing + * including its fetch and store module + */ +static void pxp_wfe_a_configure(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + /* FETCH */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(3), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS(4) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS(7), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS(8) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS(9), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS(10) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS(15), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS(4) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS(7), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL4_MASK); + + __raw_writel(1, pxp->base + HW_PXP_WFA_ARRAY_REG2); + + /* STORE */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES(8)| + BF_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0); + + + __raw_writel( + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_A_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xf), /* fetch CP */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00), /* fetch NP */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x00000), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK2_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK3_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000), /* fetch LUT */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK3_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xf), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK4_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(0x0), /* fetch Y4 */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK4_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_A_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0), + pxp->base + HW_PXP_WFE_A_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32+6)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32+6)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_A_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7(0), + pxp->base + HW_PXP_WFE_A_STORE_F_MASK_H_CH0); + + + __raw_writel( + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(0x1) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(0x2) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(0x4) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(0x8), + pxp->base + HW_PXP_WFE_A_STORE_F_MASK_L_CH0); + + /* ALU */ + __raw_writel(BF_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_A_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_A_PARAM_PARAM0(0) | + BF_PXP_ALU_A_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_A_PARAM); + + __raw_writel(BF_PXP_ALU_A_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_A_CONFIG); + + __raw_writel(BF_PXP_ALU_A_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_A_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_A_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_A_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_A_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_A_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_A_LUT_DATA1); + + __raw_writel(BF_PXP_ALU_A_CTRL_BYPASS (1) | + BF_PXP_ALU_A_CTRL_ENABLE (1) | + BF_PXP_ALU_A_CTRL_START (0) | + BF_PXP_ALU_A_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_A_CTRL); + + /* WFE A */ + __raw_writel(0x3F3F0303, pxp->base + HW_PXP_WFE_A_STAGE1_MUX0); + __raw_writel(0x0C00000C, pxp->base + HW_PXP_WFE_A_STAGE1_MUX1); + __raw_writel(0x01040000, pxp->base + HW_PXP_WFE_A_STAGE1_MUX2); + __raw_writel(0x0A0A0904, pxp->base + HW_PXP_WFE_A_STAGE1_MUX3); + __raw_writel(0x00000B0B, pxp->base + HW_PXP_WFE_A_STAGE1_MUX4); + + __raw_writel(0x1800280E, pxp->base + HW_PXP_WFE_A_STAGE2_MUX0); + __raw_writel(0x00280E01, pxp->base + HW_PXP_WFE_A_STAGE2_MUX1); + __raw_writel(0x280E0118, pxp->base + HW_PXP_WFE_A_STAGE2_MUX2); + __raw_writel(0x00011800, pxp->base + HW_PXP_WFE_A_STAGE2_MUX3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX4); + __raw_writel(0x1800280E, pxp->base + HW_PXP_WFE_A_STAGE2_MUX5); + __raw_writel(0x00280E01, pxp->base + HW_PXP_WFE_A_STAGE2_MUX6); + __raw_writel(0x1A0E0118, pxp->base + HW_PXP_WFE_A_STAGE2_MUX7); + __raw_writel(0x1B012911, pxp->base + HW_PXP_WFE_A_STAGE2_MUX8); + __raw_writel(0x00002911, pxp->base + HW_PXP_WFE_A_STAGE2_MUX9); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX10); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX11); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX12); + + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_A_STAGE3_MUX0); + __raw_writel(0x3F3F3F08, pxp->base + HW_PXP_WFE_A_STAGE3_MUX1); + __raw_writel(0x03020100, pxp->base + HW_PXP_WFE_A_STAGE3_MUX2); + __raw_writel(0x3F3F3F3F, pxp->base + HW_PXP_WFE_A_STAGE3_MUX3); + + __raw_writel(0x001F1F1F, pxp->base + HW_PXP_WFE_A_STAGE2_5X6_MASKS_0); + __raw_writel(0x3f030100, pxp->base + HW_PXP_WFE_A_STAGE2_5X6_ADDR_0); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT0); + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT1); + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT2); + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT3); + __raw_writel(0x071F1F1F, pxp->base + HW_PXP_WFE_A_STG2_5X1_MASKS); + + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_2); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_3); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_4); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_5); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_6); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_7); + + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_0); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_1); + __raw_writel(0x04050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_2); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_3); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_4); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_5); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_6); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_7); + + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_0); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_1); + __raw_writel(0x05080808, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_2); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_3); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_4); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_5); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_6); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_7); + + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_0); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_1); + __raw_writel(0x070C0C0C, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_2); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_3); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_4); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_5); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_6); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_7); + + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, + proc_data->lut_sels, 1); +} + +static void pxp_wfe_a_configure_v3p(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + /* FETCH */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(3), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(4) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(10) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(15), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(4) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL4_MASK); + + __raw_writel(1, pxp->base + HW_PXP_WFB_ARRAY_REG2); + + /* STORE */ + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(8)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xf), /* fetch CP */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00), /* fetch NP */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x00000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK3_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000), /* fetch LUT */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK3_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xf), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK4_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(0x0), /* fetch Y4 */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK4_L_CH0); + + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK5_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK5_L_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK6_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK6_L_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK7_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK7_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32+6)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32+6)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(0x1) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0x2) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0x4) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0x8), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(0x0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_H_CH0); + + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_B_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_B_PARAM_PARAM0(0) | + BF_PXP_ALU_B_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_B_PARAM); + + __raw_writel(BF_PXP_ALU_B_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_B_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_B_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_B_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA1); + + __raw_writel(BF_PXP_ALU_B_CTRL_BYPASS (1) | + BF_PXP_ALU_B_CTRL_ENABLE (1) | + BF_PXP_ALU_B_CTRL_START (0) | + BF_PXP_ALU_B_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_B_CTRL); + + /* WFE A */ + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX2); + __raw_writel(0x03000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX3); + __raw_writel(0x00000003, pxp->base + HW_PXP_WFE_B_STAGE1_MUX4); + __raw_writel(0x04000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX5); + __raw_writel(0x0A090401, pxp->base + HW_PXP_WFE_B_STAGE1_MUX6); + __raw_writel(0x000B0B0A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX7); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX8); + + __raw_writel(0x1901290C, pxp->base + HW_PXP_WFE_B_STAGE2_MUX0); + __raw_writel(0x01290C02, pxp->base + HW_PXP_WFE_B_STAGE2_MUX1); + __raw_writel(0x290C0219, pxp->base + HW_PXP_WFE_B_STAGE2_MUX2); + __raw_writel(0x00021901, pxp->base + HW_PXP_WFE_B_STAGE2_MUX3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX4); + __raw_writel(0x1901290C, pxp->base + HW_PXP_WFE_B_STAGE2_MUX5); + __raw_writel(0x01290C02, pxp->base + HW_PXP_WFE_B_STAGE2_MUX6); + __raw_writel(0x1B0C0219, pxp->base + HW_PXP_WFE_B_STAGE2_MUX7); + __raw_writel(0x1C022A0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX8); + __raw_writel(0x02002A0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX9); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX10); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX11); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX12); + + __raw_writel(0x2a123a1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX0); + __raw_writel(0x00000013, pxp->base + HW_PXP_WFE_B_STAGE3_MUX1); + __raw_writel(0x2a123a1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX2); + __raw_writel(0x00000013, pxp->base + HW_PXP_WFE_B_STAGE3_MUX3); + __raw_writel(0x3b202c1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX5); + __raw_writel(0x003b202d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX7); + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_B_STAGE3_MUX8); + __raw_writel(0x00000008, pxp->base + HW_PXP_WFE_B_STAGE3_MUX9); + __raw_writel(0x03020100, pxp->base + HW_PXP_WFE_B_STAGE3_MUX10); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_7); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_7); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_5X8_MASKS_0); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_OUT0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_MASKS); + + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_2); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_3); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_4); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_5); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_6); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_7); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT0); + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT1); + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT2); + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT3); + __raw_writel(0x070F1F1F, pxp->base + HW_PXP_WFE_B_STG2_5X1_MASKS); + + __raw_writel(0x001F1F1F, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_MASKS_0); + __raw_writel(0x3f232120, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_ADDR_0); + + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_0); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_1); + __raw_writel(0x04050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_2); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_3); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_4); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_5); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_6); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_7); + + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_0); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_1); + __raw_writel(0x05080808, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_2); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_3); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_4); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_5); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_6); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_7); + + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_0); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_1); + __raw_writel(0x070C0C0C, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_2); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_3); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_4); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_5); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_6); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_7); + + __raw_writel(0x070F1F1F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_MASKS); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_7); + + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_7); + + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_7); + + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_7); + + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, + proc_data->lut_sels, 1); +} + +/* + * wfe a processing + * use wfe a to process an update + * x,y,width,height: + * coordinate and size of the update region + * wb: + * working buffer, 16bpp + * upd: + * update buffer, in Y4 with or without alpha, 8bpp + * twb: + * temp working buffer, 16bpp + * only used when reagl_en is 1 + * y4c: + * y4c buffer, {Y4[3:0],3'b000,collision}, 8bpp + * lut: + * valid value 0-63 + * set to the lut used for next update + * partial: + * 0 - full update + * 1 - partial update + * reagl_en: + * 0 - use normal waveform algorithm + * 1 - enable reagl/-d waveform algorithm + * detection_only: + * 0 - write working buffer + * 1 - do no write working buffer, detection only + * alpha_en: + * 0 - upd is {Y4[3:0],4'b0000} format + * 1 - upd is {Y4[3:0],3'b000,alpha} format + */ +static void pxp_wfe_a_process(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_a_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_a_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_a_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_a_store_param[1]; + int v; + + if (fetch_ch0->width != fetch_ch1->width || + fetch_ch0->height != fetch_ch1->height) { + dev_err(pxp->dev, "width/height should be same for two fetch " + "channels\n"); + } + + print_param(fetch_ch0, "wfe_a fetch_ch0"); + print_param(fetch_ch1, "wfe_a fetch_ch1"); + print_param(store_ch0, "wfe_a store_ch0"); + print_param(store_ch1, "wfe_a store_ch1"); + + /* Fetch */ + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFA_FETCH_BUF1_ADDR); + + __raw_writel(BF_PXP_WFA_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFA_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFA_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_WFA_FETCH_BUF1_PITCH); + + __raw_writel(BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height - 1) | + BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width - 1), + pxp->base + HW_PXP_WFA_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFA_FETCH_BUF2_ADDR); + + __raw_writel(BF_PXP_WFA_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFA_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFA_FETCH_BUF2_CORD); + + __raw_writel(fetch_ch1->stride * 2, pxp->base + HW_PXP_WFA_FETCH_BUF2_PITCH); + + __raw_writel(BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height - 1) | + BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width - 1), + pxp->base + HW_PXP_WFA_FETCH_BUF2_SIZE); + + /* Store */ + __raw_writel(BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_WFE_A_STORE_SIZE_CH0); + + + __raw_writel(BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_WFE_A_STORE_SIZE_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_A_STORE_PITCH); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_0_CH0); + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( + store_ch1->paddr + (store_ch1->left + store_ch1->top * + store_ch1->stride) * 2), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_1_CH1); + + /* ALU */ + __raw_writel(BF_PXP_ALU_A_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_A_BUF_SIZE); + + /* WFE */ + __raw_writel(BF_PXP_WFE_A_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_A_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_A_DIMENSIONS); + + /* Here it should be fetch_ch1 */ + __raw_writel(BF_PXP_WFE_A_OFFSET_X_OFFSET(fetch_ch1->left) | + BF_PXP_WFE_A_OFFSET_Y_OFFSET(fetch_ch1->top), + pxp->base + HW_PXP_WFE_A_OFFSET); + + __raw_writel((proc_data->lut & 0x000000FF) | 0x00000F00, + pxp->base + HW_PXP_WFE_A_SW_DATA_REGS); + __raw_writel((proc_data->partial_update | (proc_data->reagl_en << 1)), + pxp->base + HW_PXP_WFE_A_SW_FLAG_REGS); + + __raw_writel( + BF_PXP_WFE_A_CTRL_ENABLE(1) | + BF_PXP_WFE_A_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_A_CTRL); + + if (proc_data->alpha_en) { + __raw_writel(BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFA_ARRAY_FLAG0_MASK); + } else { + __raw_writel(BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(2) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFA_ARRAY_FLAG0_MASK); + } + + /* disable CH1 when only doing detection */ + v = __raw_readl(pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + if (proc_data->detection_only) { + v &= ~BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1); + printk(KERN_EMERG "%s: detection only happens\n", __func__); + } else + v |= BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1); + __raw_writel(v, pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); +} + +static void pxp_wfe_a_process_v3p(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_a_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_a_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_a_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_a_store_param[1]; + int v; + + if (fetch_ch0->width != fetch_ch1->width || + fetch_ch0->height != fetch_ch1->height) { + dev_err(pxp->dev, "width/height should be same for two fetch " + "channels\n"); + } + + print_param(fetch_ch0, "wfe_a fetch_ch0"); + print_param(fetch_ch1, "wfe_a fetch_ch1"); + print_param(store_ch0, "wfe_a store_ch0"); + print_param(store_ch1, "wfe_a store_ch1"); + + /* Fetch */ + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF1_ADDR); + + __raw_writel(BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFB_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_WFB_FETCH_BUF1_PITCH); + + __raw_writel(BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height - 1) | + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width - 1), + pxp->base + HW_PXP_WFB_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF2_ADDR); + + __raw_writel(BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFB_FETCH_BUF2_CORD); + + __raw_writel(fetch_ch1->stride * 2, pxp->base + HW_PXP_WFB_FETCH_BUF2_PITCH); + + __raw_writel(BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height - 1) | + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width - 1), + pxp->base + HW_PXP_WFB_FETCH_BUF2_SIZE); + + /* Store */ + __raw_writel(BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + + __raw_writel(BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( + store_ch1->paddr + (store_ch1->left + store_ch1->top * + store_ch1->stride) * 2), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_B_BUF_SIZE); + + /* WFE */ + __raw_writel(BF_PXP_WFE_B_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_B_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_B_DIMENSIONS); + + /* Here it should be fetch_ch1 */ + __raw_writel(BF_PXP_WFE_B_OFFSET_X_OFFSET(fetch_ch1->left) | + BF_PXP_WFE_B_OFFSET_Y_OFFSET(fetch_ch1->top), + pxp->base + HW_PXP_WFE_B_OFFSET); + + __raw_writel((proc_data->lut & 0x000000FF) | 0x00000F00, + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + __raw_writel((proc_data->partial_update | (proc_data->reagl_en << 1)), + pxp->base + HW_PXP_WFE_B_SW_FLAG_REGS); + + __raw_writel( + BF_PXP_WFE_B_CTRL_ENABLE(1) | + BF_PXP_WFE_B_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_B_CTRL); + + if (proc_data->alpha_en) { + __raw_writel(BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + } else { + __raw_writel(BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(2) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + } + + /* disable CH1 when only doing detection */ + v = __raw_readl(pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + if (proc_data->detection_only) { + v &= ~BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1); + printk(KERN_EMERG "%s: detection only happens\n", __func__); + } else + v |= BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1); + __raw_writel(v, pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); +} + +/* + * wfe b configuration + * + * configure wfe b engnine for reagl/-d waveform processing + */ +static void pxp_wfe_b_configure(struct pxps *pxp) +{ + /* Fetch */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(10) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(15), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(2) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL4_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL5_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL6_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL7_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG4_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG5_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG6_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG7_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG8_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG9_MASK); + + pxp_sram_init(pxp, WFE_B, active_matrix_data_8x8, 64); + + /* Store */ + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(32), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x00000000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xff), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x3f00), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(2)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(6)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(8)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_H_CH0); + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_B_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_B_PARAM_PARAM0(0) | + BF_PXP_ALU_B_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_B_PARAM); + + __raw_writel(BF_PXP_ALU_B_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_B_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_B_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_B_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA1); + + __raw_writel( + BF_PXP_ALU_B_CTRL_BYPASS (1) | + BF_PXP_ALU_B_CTRL_ENABLE (1) | + BF_PXP_ALU_B_CTRL_START (0) | + BF_PXP_ALU_B_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_B_CTRL); + + /* WFE */ + __raw_writel(0x00000402, pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + + __raw_writel(0x02040608, pxp->base + HW_PXP_WFE_B_STAGE1_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX4); + __raw_writel(0x03000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX5); + __raw_writel(0x050A040A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX6); + __raw_writel(0x070A060A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX7); + __raw_writel(0x0000000A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX8); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX4); + __raw_writel(0x1C1E2022, pxp->base + HW_PXP_WFE_B_STAGE2_MUX5); + __raw_writel(0x1215181A, pxp->base + HW_PXP_WFE_B_STAGE2_MUX6); + __raw_writel(0x00000C0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX7); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX8); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX9); + __raw_writel(0x01000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX10); + __raw_writel(0x000C010B, pxp->base + HW_PXP_WFE_B_STAGE2_MUX11); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX12); + + __raw_writel(0x09000C01, pxp->base + HW_PXP_WFE_B_STAGE3_MUX0); + __raw_writel(0x003A2A1D, pxp->base + HW_PXP_WFE_B_STAGE3_MUX1); + __raw_writel(0x09000C01, pxp->base + HW_PXP_WFE_B_STAGE3_MUX2); + __raw_writel(0x003A2A1D, pxp->base + HW_PXP_WFE_B_STAGE3_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX7); + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_B_STAGE3_MUX8); + __raw_writel(0x00000008, pxp->base + HW_PXP_WFE_B_STAGE3_MUX9); + __raw_writel(0x00001211, pxp->base + HW_PXP_WFE_B_STAGE3_MUX10); + + __raw_writel(0x02010100, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_0); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_1); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_2); + __raw_writel(0x04030302, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_7); + + __raw_writel(0x02010100, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_0); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_1); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_2); + __raw_writel(0x04030302, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_7); + + __raw_writel(0x0000000F, pxp->base + HW_PXP_WFE_B_STAGE1_5X8_MASKS_0); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_OUT0); + __raw_writel(0x0000000F, pxp->base + HW_PXP_WFE_B_STG1_5X1_MASKS); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_MASKS_0); + __raw_writel(0x3F3F3F3F, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_ADDR_0); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_7); + + __raw_writel(0x00008000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT0); + __raw_writel(0x0000FFFE, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT3); + __raw_writel(0x00000F0F, pxp->base + HW_PXP_WFE_B_STG2_5X1_MASKS); + + __raw_writel(0x00007F7F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_MASKS); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_0); + __raw_writel(0x00FF00FF, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_2); + __raw_writel(0x000000FF, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_0); + __raw_writel(0xFF3FFF3F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_2); + __raw_writel(0xFFFFFF1F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_7); + + __raw_writel( + BF_PXP_WFE_B_CTRL_ENABLE(1) | + BF_PXP_WFE_B_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_B_CTRL); +} + +/* wfe b processing + * use wfe b to process an update + * call this function only after pxp_wfe_a_processing + * x,y,width,height: + * coordinate and size of the update region + * twb: + * temp working buffer, 16bpp + * only used when reagl_en is 1 + * wb: + * working buffer, 16bpp + * lut: + * lut buffer, 8bpp + * lut_update: + * 0 - wfe_b is used for reagl/reagl-d operation + * 1 - wfe_b is used for lut update operation + * reagl_d_en: + * 0 - use reagl waveform algorithm + * 1 - use reagl/-d waveform algorithm + */ +static void pxp_wfe_b_process(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_b_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_b_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_b_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_b_store_param[1]; + static int comp_mask; + /* Fetch */ + + print_param(fetch_ch0, "wfe_b fetch_ch0"); + print_param(fetch_ch1, "wfe_b fetch_ch1"); + print_param(store_ch0, "wfe_b store_ch0"); + print_param(store_ch1, "wfe_b store_ch1"); + + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF1_ADDR); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFB_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, + pxp->base + HW_PXP_WFB_FETCH_BUF1_PITCH); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height-1) | + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width-1), + pxp->base + HW_PXP_WFB_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF2_ADDR); + + __raw_writel(fetch_ch1->stride * 2, + pxp->base + HW_PXP_WFB_FETCH_BUF2_PITCH); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFB_FETCH_BUF2_CORD); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height-1) | + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width-1), + pxp->base + HW_PXP_WFB_FETCH_BUF2_SIZE); + + if (!proc_data->lut_update) { + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } else { + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } + +#ifdef CONFIG_REAGLD_ALGO_CHECK + __raw_writel( + (__raw_readl(pxp->base + HW_PXP_WFE_B_SW_DATA_REGS) & 0x0000FFFF) | ((fetch_ch0->comp_mask&0x000000FF)<<16), + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); +#else + __raw_writel( + (__raw_readl(pxp->base + HW_PXP_WFE_B_SW_DATA_REGS) & 0x0000FFFF) | ((comp_mask&0x000000FF)<<16), + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + + /* comp_mask only need to be updated upon REAGL-D, 0,1,...7, 0,1,... */ + if (proc_data->reagl_d_en) { + comp_mask++; + if (comp_mask>7) + comp_mask = 0; + } +#endif + + /* Store */ + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height-1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height-1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride * 2)| + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr + + (store_ch0->left + store_ch0->top * store_ch0->stride) * 2), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + + if (proc_data->lut_update) { + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x3f0000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(0x30)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(4)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + } else { + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x3f00), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(3)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(8)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + } + + /* ALU */ + __raw_writel( + BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_B_BUF_SIZE); + + /* WFE */ + __raw_writel( + BF_PXP_WFE_B_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_B_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_B_DIMENSIONS); + + __raw_writel( /*TODO check*/ + BF_PXP_WFE_B_OFFSET_X_OFFSET(fetch_ch0->left) | + BF_PXP_WFE_B_OFFSET_Y_OFFSET(fetch_ch0->top), + pxp->base + HW_PXP_WFE_B_OFFSET); + + __raw_writel(proc_data->reagl_d_en, pxp->base + HW_PXP_WFE_B_SW_FLAG_REGS); +} + +void pxp_fill( + u32 bpp, + u32 value, + u32 width, + u32 height, + u32 output_buffer, + u32 output_pitch) +{ + u32 active_bpp; + u32 pitch; + + if (bpp == 8) { + active_bpp = 0; + pitch = output_pitch; + } else if(bpp == 16) { + active_bpp = 1; + pitch = output_pitch * 2; + } else { + active_bpp = 2; + pitch = output_pitch * 4; + } + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp_reg_base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(height-1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(height-1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(pitch)| + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(pitch), + pxp_reg_base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(active_bpp)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(active_bpp)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(output_buffer), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(output_buffer), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(value), + pxp_reg_base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(32)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(40)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_CTRL2_ENABLE (1) | + BF_PXP_CTRL2_ROTATE0 (0) | + BF_PXP_CTRL2_HFLIP0 (0) | + BF_PXP_CTRL2_VFLIP0 (0) | + BF_PXP_CTRL2_ROTATE1 (0) | + BF_PXP_CTRL2_HFLIP1 (0) | + BF_PXP_CTRL2_VFLIP1 (0) | + BF_PXP_CTRL2_ENABLE_DITHER (0) | + BF_PXP_CTRL2_ENABLE_WFE_A (0) | + BF_PXP_CTRL2_ENABLE_WFE_B (1) | + BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE (0) | + BF_PXP_CTRL2_ENABLE_ALPHA_B (0) | + BF_PXP_CTRL2_BLOCK_SIZE (0) | + BF_PXP_CTRL2_ENABLE_CSC2 (0) | + BF_PXP_CTRL2_ENABLE_LUT (0) | + BF_PXP_CTRL2_ENABLE_ROTATE0 (0) | + BF_PXP_CTRL2_ENABLE_ROTATE1 (0), + pxp_reg_base + HW_PXP_CTRL2); + + if (busy_wait(BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ & + __raw_readl(pxp_reg_base + HW_PXP_IRQ)) == false) + printk("%s: wait for completion timeout\n", __func__); +} +EXPORT_SYMBOL(pxp_fill); + +static void pxp_lut_cleanup_multiple(struct pxps *pxp, u64 lut, bool set) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + u32 val; + + if (proc_data->lut_cleanup == 1) { + if (set) { + val = __raw_readl(pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); + val |= (u32)lut; + __raw_writel(val, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); + val = __raw_readl(pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); + val |= (u32)(lut >> 32); + __raw_writel(val, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); + } else { + pxp_luts_deactivate(pxp, lut); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); + } + } +} + +static void pxp_lut_cleanup_multiple_v3p(struct pxps *pxp, u64 lut, bool set) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + if (proc_data->lut_cleanup == 1) { + if (set) { + __raw_writel((u32)lut, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0 + 0x4); + __raw_writel((u32)(lut>>32), pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1 + 0x4); + } else { + pxp_luts_deactivate(pxp, lut); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + } + } +} + +#ifdef CONFIG_MXC_FPGA_M4_TEST +void m4_process(void) +{ + __raw_writel(0x7, pinctrl_base + PIN_DOUT); /* M4 Start */ + + while (!(__raw_readl(pxp_reg_base + HW_PXP_HANDSHAKE_CPU_STORE) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY)); + + __raw_writel(0x3, pinctrl_base + PIN_DOUT); /* M4 Stop */ + + +} +#else +void m4_process(void) {} +#endif +EXPORT_SYMBOL(m4_process); + +static void pxp_lut_status_set(struct pxps *pxp, unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0) | (1 << lut), + pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_0); + else { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1) | (1 << lut), + pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_1); + } +} + +static void pxp_lut_status_set_v3p(struct pxps *pxp, unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0) | (1 << lut), + pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + else { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1) | (1 << lut), + pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + } +} + +static void pxp_luts_activate(struct pxps *pxp, u64 lut_status) +{ + int i = 0; + + if (!lut_status) + return; + + for (i = 0; i < 64; i++) { + if (lut_status & (1ULL << i)) + if (pxp->devdata && pxp->devdata->pxp_lut_status_set) + pxp->devdata->pxp_lut_status_set(pxp, i); + } +} + +static void pxp_lut_status_clr(unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0); + else + { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1); + } +} + +static void pxp_lut_status_clr_v3p(unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + else + { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + } +} + +/* this function should be called in the epdc + * driver explicitly when some epdc lut becomes + * idle. So it should be exported. + */ +static void pxp_luts_deactivate(struct pxps *pxp, u64 lut_status) +{ + int i = 0; + + if (!lut_status) + return; + + for (i = 0; i < 64; i++) { + if (lut_status & (1ULL << i)) + if (pxp->devdata && pxp->devdata->pxp_lut_status_clr) + pxp->devdata->pxp_lut_status_clr(i); + } +} + +/* use histogram_B engine to calculate histogram status */ +static void pxp_histogram_enable(struct pxps *pxp, + unsigned int width, + unsigned int height) +{ + u32 val = 0; + + __raw_writel( + BF_PXP_HIST_B_BUF_SIZE_HEIGHT(height)| + BF_PXP_HIST_B_BUF_SIZE_WIDTH(width), + pxp->base + HW_PXP_HIST_B_BUF_SIZE); + + if (pxp_is_v3(pxp)) + val = 64; + else if (pxp_is_v3p(pxp)) + val = 64 + 4; + + __raw_writel( + BF_PXP_HIST_B_MASK_MASK_EN(1)| + BF_PXP_HIST_B_MASK_MASK_MODE(0)| + BF_PXP_HIST_B_MASK_MASK_OFFSET(val)| + BF_PXP_HIST_B_MASK_MASK_WIDTH(0)| + BF_PXP_HIST_B_MASK_MASK_VALUE0(1) | + BF_PXP_HIST_B_MASK_MASK_VALUE1(0), + pxp->base + HW_PXP_HIST_B_MASK); + + __raw_writel( + BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(3)| + BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(8)| + BF_PXP_HIST_B_CTRL_CLEAR(0)| + BF_PXP_HIST_B_CTRL_ENABLE(1), + pxp->base + HW_PXP_HIST_B_CTRL); +} + +static void pxp_histogram_status_report(struct pxps *pxp, u32 *hist_status) +{ + BUG_ON(!hist_status); + + *hist_status = (__raw_readl(pxp->base + HW_PXP_HIST_B_CTRL) & BM_PXP_HIST_B_CTRL_STATUS) + >> BP_PXP_HIST_B_CTRL_STATUS; + dev_dbg(pxp->dev, "%d pixels are used to calculate histogram status %d\n", + __raw_readl(pxp->base + HW_PXP_HIST_B_TOTAL_PIXEL), *hist_status); +} + +static void pxp_histogram_disable(struct pxps *pxp) +{ + __raw_writel( + BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(3)| + BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(4)| + BF_PXP_HIST_B_CTRL_CLEAR(1)| + BF_PXP_HIST_B_CTRL_ENABLE(0), + pxp->base + HW_PXP_HIST_B_CTRL); +} + +/* the collision detection function will be + * called by epdc driver when required + */ +static void pxp_collision_detection_enable(struct pxps *pxp, + unsigned int width, + unsigned int height) +{ + u32 val = 0; + + __raw_writel( + BF_PXP_HIST_A_BUF_SIZE_HEIGHT(height)| + BF_PXP_HIST_A_BUF_SIZE_WIDTH(width), + pxp_reg_base + HW_PXP_HIST_A_BUF_SIZE); + + if (pxp_is_v3(pxp)) + val = 65; + else if (pxp_is_v3p(pxp)) + val = 65 + 4; + + __raw_writel( + BF_PXP_HIST_A_MASK_MASK_EN(1)| + BF_PXP_HIST_A_MASK_MASK_MODE(0)| + BF_PXP_HIST_A_MASK_MASK_OFFSET(val)| + BF_PXP_HIST_A_MASK_MASK_WIDTH(0)| + BF_PXP_HIST_A_MASK_MASK_VALUE0(1) | + BF_PXP_HIST_A_MASK_MASK_VALUE1(0), + pxp_reg_base + HW_PXP_HIST_A_MASK); + + __raw_writel( + BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(6)| + BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(24)| + BF_PXP_HIST_A_CTRL_CLEAR(0)| + BF_PXP_HIST_A_CTRL_ENABLE(1), + pxp_reg_base + HW_PXP_HIST_A_CTRL); +} + +static void pxp_collision_detection_disable(struct pxps *pxp) +{ + __raw_writel( + BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(6)| + BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(24)| + BF_PXP_HIST_A_CTRL_CLEAR(1)| + BF_PXP_HIST_A_CTRL_ENABLE(0), + pxp_reg_base + HW_PXP_HIST_A_CTRL); +} + +/* this function can be called in the epdc callback + * function in the pxp_irq() to let the epdc know + * the collision information for the previous working + * buffer update. + */ +static bool pxp_collision_status_report(struct pxps *pxp, struct pxp_collision_info *info) +{ + unsigned int count; + + BUG_ON(!info); + memset(info, 0x0, sizeof(*info)); + + info->pixel_cnt = count = __raw_readl(pxp->base + HW_PXP_HIST_A_TOTAL_PIXEL); + if (!count) + return false; + + dev_dbg(pxp->dev, "%s: pixel_cnt = %d\n", __func__, info->pixel_cnt); + info->rect_min_x = __raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_X) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_min_x = %d\n", __func__, info->rect_min_x); + info->rect_max_x = (__raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_X) >> 16) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_max_x = %d\n", __func__, info->rect_max_x); + info->rect_min_y = __raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_Y) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_min_y = %d\n", __func__, info->rect_min_y); + info->rect_max_y = (__raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_Y) >> 16) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_max_y = %d\n", __func__, info->rect_max_y); + + info->victim_luts[0] = __raw_readl(pxp->base + HW_PXP_HIST_A_RAW_STAT0); + dev_dbg(pxp->dev, "%s: victim_luts[0] = 0x%x\n", __func__, info->victim_luts[0]); + info->victim_luts[1] = __raw_readl(pxp->base + HW_PXP_HIST_A_RAW_STAT1); + dev_dbg(pxp->dev, "%s: victim_luts[1] = 0x%x\n", __func__, info->victim_luts[1]); + + return true; +} + +void pxp_get_collision_info(struct pxp_collision_info *info) +{ + BUG_ON(!info); + + memcpy(info, &col_info, sizeof(struct pxp_collision_info)); +} +EXPORT_SYMBOL(pxp_get_collision_info); + +static void dither_prefetch_config(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *fetch_ch0 = &config_data->dither_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->dither_fetch_param[1]; + + print_param(fetch_ch0, "dither fetch_ch0"); + print_param(fetch_ch1, "dither fetch_ch1"); + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(1) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(32) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH1_CH_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(2) | + BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(0) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(0), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0); + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(fetch_ch0->width - 1) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(fetch_ch0->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(0) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(0), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1); + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(fetch_ch1->width - 1) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(fetch_ch1->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1); + __raw_writel( + BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(fetch_ch0->width - 1) | + BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(fetch_ch0->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_SIZE_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(fetch_ch1->width - 1) | + BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(fetch_ch1->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_SIZE_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(fetch_ch0->stride) | + BF_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(fetch_ch1->stride), + pxp->base + HW_PXP_DITHER_FETCH_PITCH); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(0), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(0), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(7), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(7), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(fetch_ch0->paddr), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_0_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_1_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(fetch_ch1->paddr), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_0_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_1_CH1); +} + +static void dither_store_config(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *store_ch0 = &config_data->dither_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->dither_store_param[1]; + + print_param(store_ch0, "dither store_ch0"); + print_param(store_ch1, "dither store_ch1"); + + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(32), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride), + pxp->base + HW_PXP_DITHER_STORE_PITCH); + + __raw_writel( + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_DITHER_STORE_ADDR_0_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_STORE_ADDR_1_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(store_ch1->paddr), + pxp->base + HW_PXP_DITHER_STORE_ADDR_0_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_STORE_ADDR_1_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_DITHER_STORE_FILL_DATA_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0xffffff), + pxp->base + HW_PXP_DITHER_STORE_D_MASK0_H_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0x0), + pxp->base + HW_PXP_DITHER_STORE_D_MASK0_L_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_DITHER_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xff), + pxp->base + HW_PXP_DITHER_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(32)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp->base + HW_PXP_DITHER_STORE_D_SHIFT_L_CH0); +} + +static void pxp_set_final_lut_data(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + if (proc_data->quant_bit < 2) { + pxp_sram_init(pxp, DITHER0_LUT, bit1_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xf0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } else if (proc_data->quant_bit < 4) { + pxp_sram_init(pxp, DITHER0_LUT, bit2_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x50), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0xa0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0xa0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xa0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xa0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } else { + pxp_sram_init(pxp, DITHER0_LUT, bit4_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x10) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x20) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x30), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x40) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x60) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x70), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0x80) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0x90) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xa0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xb0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xc0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xd0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xe0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } +} + +static void pxp_dithering_process(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 val = 0; + + if (pxp->devdata && pxp->devdata->pxp_dithering_configure) + pxp->devdata->pxp_dithering_configure(pxp); + + if (pxp->devdata && pxp_is_v3(pxp)) + val = BF_PXP_DITHER_CTRL_ENABLE0 (1) | + BF_PXP_DITHER_CTRL_ENABLE1 (0) | + BF_PXP_DITHER_CTRL_ENABLE2 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE2 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE1 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE0(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_LUT_MODE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE (0) | + BF_PXP_DITHER_CTRL_BUSY2 (0) | + BF_PXP_DITHER_CTRL_BUSY1 (0) | + BF_PXP_DITHER_CTRL_BUSY0 (0); + else if (pxp->devdata && pxp_is_v3p(pxp)) { + if (proc_data->dither_mode != 0 && + proc_data->dither_mode != 3) { + dev_err(pxp->dev, "Not supported dithering mode. " + "Forced to be Orderred mode!\n"); + proc_data->dither_mode = 3; + } + + val = BF_PXP_DITHER_CTRL_ENABLE0 (1) | + BF_PXP_DITHER_CTRL_ENABLE1 (1) | + BF_PXP_DITHER_CTRL_ENABLE2 (1) | + BF_PXP_DITHER_CTRL_DITHER_MODE2(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_DITHER_MODE1(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_DITHER_MODE0(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_LUT_MODE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE (1) | + BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE (0) | + BF_PXP_DITHER_CTRL_BUSY2 (0) | + BF_PXP_DITHER_CTRL_BUSY1 (0) | + BF_PXP_DITHER_CTRL_BUSY0 (0); + } + __raw_writel(val, pxp->base + HW_PXP_DITHER_CTRL); + + switch(proc_data->dither_mode) { + case PXP_DITHER_PASS_THROUGH: + /* no more settings required */ + break; + case PXP_DITHER_FLOYD: + case PXP_DITHER_ATKINSON: + case PXP_DITHER_ORDERED: + if(!proc_data->quant_bit || proc_data->quant_bit > 7) { + dev_err(pxp->dev, "unsupported quantization bit number!\n"); + return; + } + __raw_writel( + BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE(1) | + BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(proc_data->quant_bit), + pxp->base + HW_PXP_DITHER_CTRL_SET); + pxp_set_final_lut_data(pxp); + + break; + case PXP_DITHER_QUANT_ONLY: + if(!proc_data->quant_bit || proc_data->quant_bit > 7) { + dev_err(pxp->dev, "unsupported quantization bit number!\n"); + return; + } + __raw_writel( + BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(proc_data->quant_bit), + pxp->base + HW_PXP_DITHER_CTRL_SET); + break; + default: + /* unknown mode */ + dev_err(pxp->dev, "unknown dithering mode passed!\n"); + __raw_writel(0x0, pxp->base + HW_PXP_DITHER_CTRL); + return; + } +} + +static void pxp_dithering_configure(struct pxps *pxp) +{ + dither_prefetch_config(pxp); + dither_store_config(pxp); +} + +static void pxp_dithering_configure_v3p(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *fetch_ch0 = &config_data->dither_fetch_param[0]; + struct pxp_layer_param *store_ch0 = &config_data->dither_store_param[0]; + + __raw_writel(BF_PXP_CTRL_BLOCK_SIZE(BV_PXP_CTRL_BLOCK_SIZE__8X8) | + BF_PXP_CTRL_ROTATE0(BV_PXP_CTRL_ROTATE0__ROT_0) | + BM_PXP_CTRL_IRQ_ENABLE, + pxp->base + HW_PXP_CTRL); + + __raw_writel(BF_PXP_PS_CTRL_DECX(BV_PXP_PS_CTRL_DECX__DISABLE) | + BF_PXP_PS_CTRL_DECY(BV_PXP_PS_CTRL_DECY__DISABLE) | + BF_PXP_PS_CTRL_FORMAT(BV_PXP_PS_CTRL_FORMAT__Y8), + pxp->base + HW_PXP_PS_CTRL); + + __raw_writel(BF_PXP_OUT_CTRL_FORMAT(BV_PXP_OUT_CTRL_FORMAT__Y8), + pxp->base + HW_PXP_OUT_CTRL); + + __raw_writel(BF_PXP_PS_SCALE_YSCALE(4096) | + BF_PXP_PS_SCALE_XSCALE(4096), + pxp->base + HW_PXP_PS_SCALE); + + __raw_writel(store_ch0->paddr, pxp->base + HW_PXP_OUT_BUF); + + __raw_writel(store_ch0->stride, pxp->base + HW_PXP_OUT_PITCH); + + __raw_writel(BF_PXP_OUT_LRC_X(store_ch0->width - 1) | + BF_PXP_OUT_LRC_Y(store_ch0->height - 1), + pxp->base + HW_PXP_OUT_LRC); + + __raw_writel(BF_PXP_OUT_AS_ULC_X(1) | + BF_PXP_OUT_AS_ULC_Y(1), + pxp->base + HW_PXP_OUT_AS_ULC); + + __raw_writel(BF_PXP_OUT_AS_LRC_X(0) | + BF_PXP_OUT_AS_LRC_Y(0), + pxp->base + HW_PXP_OUT_AS_LRC); + + __raw_writel(BF_PXP_OUT_PS_ULC_X(0) | + BF_PXP_OUT_PS_ULC_Y(0), + pxp->base + HW_PXP_OUT_PS_ULC); + + __raw_writel(BF_PXP_OUT_PS_LRC_X(fetch_ch0->width - 1) | + BF_PXP_OUT_PS_LRC_Y(fetch_ch0->height - 1), + pxp->base + HW_PXP_OUT_PS_LRC); + + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_PS_BUF); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_PS_PITCH); + + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + __raw_writel(BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width-1)| + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height-1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH0); + + __raw_writel(BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1), + pxp->base + HW_PXP_DATA_PATH_CTRL0_CLR); +} + +static void pxp_start2(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + int dither_wfe_a_handshake = 0; + int wfe_a_b_handshake = 0; + int count = 0; + + int wfe_a_enable = ((proc_data->engine_enable & PXP_ENABLE_WFE_A) == PXP_ENABLE_WFE_A); + int wfe_b_enable = ((proc_data->engine_enable & PXP_ENABLE_WFE_B) == PXP_ENABLE_WFE_B); + int dither_enable = ((proc_data->engine_enable & PXP_ENABLE_DITHER) == PXP_ENABLE_DITHER); + int handshake = ((proc_data->engine_enable & PXP_ENABLE_HANDSHAKE) == PXP_ENABLE_HANDSHAKE); + int dither_bypass = ((proc_data->engine_enable & PXP_ENABLE_DITHER_BYPASS) == PXP_ENABLE_DITHER_BYPASS); + u32 val = 0; + + if (dither_enable) + count++; + if (wfe_a_enable) + count++; + if (wfe_b_enable) + count++; + + if (count == 0) + return; + if (handshake && (count == 1)) { + dev_warn(pxp->dev, "Warning: Can not use handshake mode when " + "only one sub-block is enabled!\n"); + handshake = 0; + } + + if (handshake && wfe_b_enable && (wfe_a_enable == 0)) { + dev_err(pxp->dev, "WFE_B only works when WFE_A is enabled!\n"); + return; + } + + if (handshake && dither_enable && wfe_a_enable) + dither_wfe_a_handshake = 1; + if (handshake && wfe_a_enable && wfe_b_enable) + wfe_a_b_handshake = 1; + + dev_dbg(pxp->dev, "handshake %d, dither_wfe_a_handshake %d, " + "wfe_a_b_handshake %d, dither_bypass %d\n", + handshake, + dither_wfe_a_handshake, + wfe_a_b_handshake, + dither_bypass); + + if (handshake) { + /* for handshake, we only enable the last completion INT */ + if (wfe_b_enable) + __raw_writel(0x8000, pxp->base + HW_PXP_IRQ_MASK); + else if (wfe_a_enable) + __raw_writel(0x4000, pxp->base + HW_PXP_IRQ_MASK); + + /* Dither fetch */ + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(1) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(32) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH0); + + if (dither_bypass) { + /* Dither store */ + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + /* WFE_A fetch */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(2) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + + } else if (dither_wfe_a_handshake) { + /* Dither store */ + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + /* WFE_A fetch */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + } + + if (wfe_a_b_handshake) { + /* WFE_A Store */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + + /* WFE_B fetch */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } else { + /* WFE_A Store */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + } + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_A(wfe_a_enable) | + BF_PXP_CTRL_ENABLE_WFE_B(wfe_b_enable); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_B(wfe_a_enable | + wfe_b_enable); + + /* trigger operation */ + __raw_writel( + BF_PXP_CTRL_ENABLE(1) | + BF_PXP_CTRL_IRQ_ENABLE(0) | + BF_PXP_CTRL_NEXT_IRQ_ENABLE(0) | + BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(0) | + BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(1) | + BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(1) | + BF_PXP_CTRL_ROTATE0(0) | + BF_PXP_CTRL_HFLIP0(0) | + BF_PXP_CTRL_VFLIP0(0) | + BF_PXP_CTRL_ROTATE1(0) | + BF_PXP_CTRL_HFLIP1(0) | + BF_PXP_CTRL_VFLIP1(0) | + BF_PXP_CTRL_ENABLE_PS_AS_OUT(0) | + BF_PXP_CTRL_ENABLE_DITHER(dither_enable) | + BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(0) | + BF_PXP_CTRL_ENABLE_ALPHA_B(0) | + BF_PXP_CTRL_BLOCK_SIZE(1) | + BF_PXP_CTRL_ENABLE_CSC2(0) | + BF_PXP_CTRL_ENABLE_LUT(1) | + BF_PXP_CTRL_ENABLE_ROTATE0(0) | + BF_PXP_CTRL_ENABLE_ROTATE1(0) | + BF_PXP_CTRL_EN_REPEAT(0) | + val, + pxp->base + HW_PXP_CTRL); + + return; + } + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_A(wfe_a_enable) | + BF_PXP_CTRL_ENABLE_WFE_B(wfe_b_enable) | + BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(0) | + BF_PXP_CTRL_ENABLE_ALPHA_B(0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_B(wfe_a_enable | + wfe_b_enable); + + __raw_writel( + BF_PXP_CTRL_ENABLE(1) | + BF_PXP_CTRL_IRQ_ENABLE(0) | + BF_PXP_CTRL_NEXT_IRQ_ENABLE(0) | + BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(0) | + BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(0) | + BF_PXP_CTRL_ROTATE0(0) | + BF_PXP_CTRL_HFLIP0(0) | + BF_PXP_CTRL_VFLIP0(0) | + BF_PXP_CTRL_ROTATE1(0) | + BF_PXP_CTRL_HFLIP1(0) | + BF_PXP_CTRL_VFLIP1(0) | + BF_PXP_CTRL_ENABLE_PS_AS_OUT(0) | + BF_PXP_CTRL_ENABLE_DITHER(dither_enable) | + BF_PXP_CTRL_BLOCK_SIZE(0) | + BF_PXP_CTRL_ENABLE_CSC2(0) | + BF_PXP_CTRL_ENABLE_LUT(0) | + BF_PXP_CTRL_ENABLE_ROTATE0(0) | + BF_PXP_CTRL_ENABLE_ROTATE1(0) | + BF_PXP_CTRL_EN_REPEAT(0) | + val, + pxp->base + HW_PXP_CTRL); + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL2_ENABLE_WFE_A (0) | + BF_PXP_CTRL2_ENABLE_WFE_B (0) | + BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE (0) | + BF_PXP_CTRL2_ENABLE_ALPHA_B (0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL2_ENABLE_WFE_B(0); + + __raw_writel( + BF_PXP_CTRL2_ENABLE (0) | + BF_PXP_CTRL2_ROTATE0 (0) | + BF_PXP_CTRL2_HFLIP0 (0) | + BF_PXP_CTRL2_VFLIP0 (0) | + BF_PXP_CTRL2_ROTATE1 (0) | + BF_PXP_CTRL2_HFLIP1 (0) | + BF_PXP_CTRL2_VFLIP1 (0) | + BF_PXP_CTRL2_ENABLE_DITHER (0) | + BF_PXP_CTRL2_BLOCK_SIZE (0) | + BF_PXP_CTRL2_ENABLE_CSC2 (0) | + BF_PXP_CTRL2_ENABLE_LUT (0) | + BF_PXP_CTRL2_ENABLE_ROTATE0 (0) | + BF_PXP_CTRL2_ENABLE_ROTATE1 (0), + pxp->base + HW_PXP_CTRL2); + + dump_pxp_reg2(pxp); +} + +static int pxp_dma_init(struct pxps *pxp) +{ + struct pxp_dma *pxp_dma = &pxp->pxp_dma; + struct dma_device *dma = &pxp_dma->dma; + int i; + + dma_cap_set(DMA_SLAVE, dma->cap_mask); + dma_cap_set(DMA_PRIVATE, dma->cap_mask); + + /* Compulsory common fields */ + dma->dev = pxp->dev; + dma->device_alloc_chan_resources = pxp_alloc_chan_resources; + dma->device_free_chan_resources = pxp_free_chan_resources; + dma->device_tx_status = pxp_tx_status; + dma->device_issue_pending = pxp_issue_pending; + + /* Compulsory for DMA_SLAVE fields */ + dma->device_prep_slave_sg = pxp_prep_slave_sg; + dma->device_terminate_all = pxp_device_terminate_all; + + /* Initialize PxP Channels */ + INIT_LIST_HEAD(&dma->channels); + for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { + struct pxp_channel *pxp_chan = pxp->channel + i; + struct dma_chan *dma_chan = &pxp_chan->dma_chan; + + spin_lock_init(&pxp_chan->lock); + + /* Only one EOF IRQ for PxP, shared by all channels */ + pxp_chan->eof_irq = pxp->irq; + pxp_chan->status = PXP_CHANNEL_FREE; + pxp_chan->completed = -ENXIO; + snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), + "PXP EOF %d", i); + + dma_chan->device = &pxp_dma->dma; + dma_chan->cookie = 1; + dma_chan->chan_id = i; + list_add_tail(&dma_chan->device_node, &dma->channels); + } + + return dma_async_device_register(&pxp_dma->dma); +} + +static ssize_t clk_off_timeout_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", timeout_in_ms); +} + +static ssize_t clk_off_timeout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int val; + if (sscanf(buf, "%d", &val) > 0) { + timeout_in_ms = val; + return count; + } + return -EINVAL; +} + +static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show, + clk_off_timeout_store); + +static ssize_t block_size_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", block_size); +} + +static ssize_t block_size_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char **last = NULL; + + block_size = simple_strtoul(buf, last, 0); + if (block_size > 1) + block_size = 1; + + return count; +} +static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO, + block_size_show, block_size_store); + +static struct platform_device_id imx_pxpdma_devtype[] = { + { + .name = "imx7d-pxp-dma", + .driver_data = PXP_V3, + }, { + .name = "imx6ull-pxp-dma", + .driver_data = PXP_V3P, + }, { + .name = "imx8ulp-pxp-dma", + .driver_data = PXP_V3_8ULP, + }, { + .name = "imx93-pxp-dma", + .driver_data = PXP_V3_IMX93, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(platform, imx_pxpdma_devtype); + +static const struct of_device_id imx_pxpdma_dt_ids[] = { + { .compatible = "fsl,imx7d-pxp-dma", .data = &imx_pxpdma_devtype[0], }, + { .compatible = "fsl,imx6ull-pxp-dma", .data = &imx_pxpdma_devtype[1], }, + { .compatible = "fsl,imx8ulp-pxp-dma", .data = &imx_pxpdma_devtype[2], }, + { .compatible = "fsl,imx93-pxp-dma", .data = &imx_pxpdma_devtype[3], }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids); + +static int has_pending_task(struct pxps *pxp, struct pxp_channel *task) +{ + int found; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + found = !list_empty(&head); + spin_unlock_irqrestore(&pxp->lock, flags); + + return found; +} + +static int pxp_dispatch_thread(void *argv) +{ + struct pxps *pxp = (struct pxps *)argv; + struct pxp_channel *pending = NULL; + unsigned long flags; + + set_freezable(); + + while (!kthread_should_stop()) { + int ret; + ret = wait_event_freezable(pxp->thread_waitq, + has_pending_task(pxp, pending) || + kthread_should_stop()); + if (ret < 0) + continue; + + if (kthread_should_stop()) + break; + + spin_lock_irqsave(&pxp->lock, flags); + pxp->pxp_ongoing = 1; + spin_unlock_irqrestore(&pxp->lock, flags); + init_completion(&pxp->complete); + ret = pxpdma_dostart_work(pxp); + if (ret) { + pxp->pxp_ongoing = 0; + continue; + } + ret = wait_for_completion_timeout(&pxp->complete, 2 * HZ); + if (ret == 0) { + printk(KERN_EMERG "%s: task is timeout\n\n", __func__); + break; + } + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, 0, 0); + } + + return 0; +} + +static int pxp_init_interrupt(struct platform_device *pdev) +{ + int legacy_irq, std_irq, err; + struct pxps *pxp = platform_get_drvdata(pdev); + int irq_cnt = 0; + + irq_cnt = platform_irq_count(pdev); + switch (irq_cnt) { + case 2: + std_irq = platform_get_irq(pdev, 1); + if (std_irq < 0) { + dev_err(&pdev->dev, "failed to get pxp standard irq: %d\n", + std_irq); + return std_irq; + } + err = devm_request_irq(&pdev->dev, std_irq, pxp_irq, 0, + "pxp-dmaengine-std", pxp); + if (err) { + dev_err(&pdev->dev, "Request pxp standard irq failed: %d\n", + err); + return err; + } + fallthrough; + case 1: + legacy_irq = platform_get_irq(pdev, 0); + if (legacy_irq < 0) { + dev_err(&pdev->dev, "failed to get pxp legacy irq: %d\n", + legacy_irq); + return legacy_irq; + } + err = devm_request_irq(&pdev->dev, legacy_irq, pxp_irq, 0, + "pxp-dmaengine-legacy", pxp); + if (err) { + dev_err(&pdev->dev, "Request pxp legacy irq failed: %d\n", err); + return -ENXIO; + } + break; + default: + pr_err("failed to get pxp irq count=(%d)\n", irq_cnt); + return -EINVAL; + } + + pxp->irq = legacy_irq; + + /* enable all the possible irq raised by PXP */ + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + + return 0; +} + +static int pxp_create_attrs(struct platform_device *pdev) +{ + int ret = 0; + + if ((ret = device_create_file(&pdev->dev, &dev_attr_clk_off_timeout))) { + dev_err(&pdev->dev, + "Unable to create file from clk_off_timeout\n"); + return ret; + } + + if ((ret = device_create_file(&pdev->dev, &dev_attr_block_size))) { + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + + dev_err(&pdev->dev, + "Unable to create file from block_size\n"); + return ret; + } + + return 0; +} + +static void pxp_remove_attrs(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + device_remove_file(&pdev->dev, &dev_attr_block_size); +} + +static void pxp_init_timer(struct pxps *pxp) +{ + INIT_WORK(&pxp->work, clkoff_callback); + + timer_setup(&pxp->clk_timer, pxp_clkoff_timer, 0); +} + +static bool is_mux_node(uint32_t node_id) +{ + if ((node_id < PXP_2D_MUX_MUX0) || + (node_id > PXP_2D_MUX_MUX15)) + return false; + + return true; +} + +static bool search_mux_chain(uint32_t mux_id, + struct edge_node *enode) +{ + bool found = false; + uint32_t i, j, next_mux = 0; + uint32_t output; + struct mux *muxes; + + muxes = (v3p_flag) ? muxes_v3p : muxes_v3; + + for (i = 0; i < 2; i++) { + output = muxes[mux_id].mux_outputs[i]; + if (output == 0xff) + break; + + if (output == enode->adjvex) { + /* found */ + found = true; + break; + } else if (is_mux_node(output)) { + next_mux = output - PXP_2D_MUX_BASE; + found = search_mux_chain(next_mux, enode); + + if (found) { + for (j = 0; j < 4; j++) { + if (muxes[next_mux].mux_inputs[j] == + (mux_id + PXP_2D_MUX_BASE)) + break; + } + + set_bit(next_mux, &enode->mux_used); + set_mux_val(&enode->muxes, next_mux, j); + break; + } + } + } + + return found; +} + +static void enode_mux_config(unsigned int vnode_id, + struct edge_node *enode) +{ + uint32_t i, j; + bool via_mux = false, need_search = false; + struct mux *muxes; + + BUG_ON(vnode_id >= PXP_2D_NUM); + BUG_ON(enode->adjvex >= PXP_2D_NUM); + + muxes = (v3p_flag) ? muxes_v3p : muxes_v3; + + for (i = 0; i < 16; i++) { + for (j = 0; j < 4; j++) { + if (muxes[i].mux_inputs[j] == 0xff) + break; + + if (muxes[i].mux_inputs[j] == vnode_id) + need_search = true; + else if (muxes[i].mux_inputs[j] == PXP_2D_ALPHA0_S0_S1) { + if ((vnode_id == PXP_2D_ALPHA0_S0) || + (vnode_id == PXP_2D_ALPHA0_S1)) + need_search = true; + } else if (muxes[i].mux_inputs[j] == PXP_2D_ALPHA1_S0_S1) { + if ((vnode_id == PXP_2D_ALPHA1_S0) || + (vnode_id == PXP_2D_ALPHA1_S1)) + need_search = true; + } + + if (need_search) { + via_mux = search_mux_chain(i, enode); + need_search = false; + break; + } + } + + if (via_mux) { + set_bit(i, &enode->mux_used); + set_mux_val(&enode->muxes, i, j); + break; + } + } +} + +static int pxp_create_initial_graph(struct platform_device *pdev) +{ + int i, j, first; + static bool (*adj_array)[PXP_2D_NUM]; + struct edge_node *enode, *curr = NULL; + + adj_array = (v3p_flag) ? adj_array_v3p : adj_array_v3; + + for (i = 0; i < PXP_2D_NUM; i++) { + switch (i) { + case PXP_2D_PS: + case PXP_2D_AS: + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + adj_list[i].type = PXP_2D_TYPE_INPUT; + break; + case PXP_2D_OUT: + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + adj_list[i].type = PXP_2D_TYPE_OUTPUT; + break; + default: + adj_list[i].type = PXP_2D_TYPE_ALU; + break; + } + + first = -1; + + for (j = 0; j < PXP_2D_NUM; j++) { + if (adj_array[i][j]) { + enode = kmem_cache_alloc(edge_node_cache, + GFP_KERNEL | __GFP_ZERO); + if (!enode) { + dev_err(&pdev->dev, "allocate edge node failed\n"); + return -ENOMEM; + } + enode->adjvex = j; + enode->prev_vnode = i; + + if (unlikely(first == -1)) { + first = j; + adj_list[i].first = enode; + } else + curr->next = enode; + + curr = enode; + enode_mux_config(i, enode); + dev_dbg(&pdev->dev, "(%d -> %d): mux_used 0x%lx, mux_config 0x%x\n\n", + i, j, enode->mux_used, *(unsigned int*)&enode->muxes); + } + } + } + + return 0; +} + +/* Calculate the shortest paths start via + * 'from' node to other nodes + */ +static void pxp_find_shortest_path(unsigned int from) +{ + int i; + struct edge_node *enode; + struct path_node *pnode, *adjnode; + struct list_head queue; + + INIT_LIST_HEAD(&queue); + list_add_tail(&path_table[from][from].node, &queue); + + while(!list_empty(&queue)) { + pnode = list_entry(queue.next, struct path_node, node); + enode = adj_list[pnode->id].first; + while (enode) { + adjnode = &path_table[from][enode->adjvex]; + + if (adjnode->distance == DISTANCE_INFINITY) { + adjnode->distance = pnode->distance + 1; + adjnode->prev_node = pnode->id; + list_add_tail(&adjnode->node, &queue); + } + + enode = enode->next; + } + list_del_init(&pnode->node); + } + + for (i = 0; i < PXP_2D_NUM; i++) + pr_debug("From %u: to %d (id = %d, distance = 0x%x, prev_node = %d\n", + from, i, path_table[from][i].id, path_table[from][i].distance, + path_table[from][i].prev_node); +} + +static int pxp_gen_shortest_paths(struct platform_device *pdev) +{ + int i, j; + + for (i = 0; i < PXP_2D_NUM; i++) { + for (j = 0; j < PXP_2D_NUM; j++) { + path_table[i][j].id = j; + path_table[i][j].distance = DISTANCE_INFINITY; + path_table[i][j].prev_node = NO_PATH_NODE; + INIT_LIST_HEAD(&path_table[i][j].node); + } + + path_table[i][i].distance = 0; + + pxp_find_shortest_path(i); + } + + return 0; +} + +#ifdef CONFIG_MXC_FPGA_M4_TEST +static void pxp_config_m4(struct platform_device *pdev) +{ + fpga_tcml_base = ioremap(FPGA_TCML_ADDR, SZ_32K); + if (fpga_tcml_base == NULL) { + dev_err(&pdev->dev, + "get fpga_tcml_base error.\n"); + goto exit; + } + pinctrl_base = ioremap(PINCTRL, SZ_4K); + if (pinctrl_base == NULL) { + dev_err(&pdev->dev, + "get fpga_tcml_base error.\n"); + goto exit; + } + + __raw_writel(0xC0000000, pinctrl_base + 0x08); + __raw_writel(0x3, pinctrl_base + PIN_DOUT); + int i; + + for (i = 0; i < 1024 * 32 / 4; i++) + *(((unsigned int *)(fpga_tcml_base)) + i) = cm4_image[i]; +} +#endif + +static int pxp_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id = + of_match_device(imx_pxpdma_dt_ids, &pdev->dev); + struct pxps *pxp; + struct resource *res; + int err = 0; + + if (of_id) + pdev->id_entry = of_id->data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + pxp->dev = &pdev->dev; + + platform_set_drvdata(pdev, pxp); + + spin_lock_init(&pxp->lock); + mutex_init(&pxp->clk_mutex); + + pxp->base = devm_ioremap_resource(&pdev->dev, res); + if (pxp->base == NULL) { + dev_err(&pdev->dev, "Couldn't ioremap regs\n"); + err = -ENODEV; + goto exit; + } + pxp_reg_base = pxp->base; + + pxp->pdev = pdev; + pxp->devdata = &pxp_devdata[pdev->id_entry->driver_data]; + + v3p_flag = (pxp_is_v3p(pxp)) ? true : false; + + pxp->ipg_clk = devm_clk_get(&pdev->dev, "pxp_ipg"); + pxp->axi_clk = devm_clk_get(&pdev->dev, "pxp_axi"); + + if (IS_ERR(pxp->ipg_clk) || IS_ERR(pxp->axi_clk)) { + dev_err(&pdev->dev, "pxp clocks invalid\n"); + err = -EINVAL; + goto exit; + } + + pxp->gpr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "pxp-gpr"); + if (IS_ERR(pxp->gpr)) + pxp->gpr = NULL; + + pxp_clk_enable(pxp); + pxp_soft_reset(pxp); + pxp_writel(0x0, HW_PXP_CTRL); + + /* Initialize DMA engine */ + err = pxp_dma_init(pxp); + if (err < 0) + goto exit; + + pxp_soft_reset(pxp); + + /* Initialize PXP Interrupt */ + err = pxp_init_interrupt(pdev); + if (err < 0) + goto exit; + + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + /* enable all the possible irq raised by PXP */ + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + + dump_pxp_reg(pxp); + pxp_clk_disable(pxp); + + pxp_init_timer(pxp); + + init_waitqueue_head(&pxp->thread_waitq); + /* allocate a kernel thread to dispatch pxp conf */ + pxp->dispatch = kthread_run(pxp_dispatch_thread, pxp, "pxp_dispatch"); + if (IS_ERR(pxp->dispatch)) { + err = PTR_ERR(pxp->dispatch); + goto exit; + } + tx_desc_cache = kmem_cache_create("tx_desc", sizeof(struct pxp_tx_desc), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!tx_desc_cache) { + err = -ENOMEM; + goto exit; + } + + edge_node_cache = kmem_cache_create("edge_node", sizeof(struct edge_node), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!edge_node_cache) { + err = -ENOMEM; + kmem_cache_destroy(tx_desc_cache); + goto exit; + } + + err = pxp_create_attrs(pdev); + if (err) { + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + goto exit; + } + + if ((err = pxp_create_initial_graph(pdev))) { + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + goto exit; + } + + pxp_gen_shortest_paths(pdev); + +#ifdef CONFIG_MXC_FPGA_M4_TEST + pxp_config_m4(pdev); +#endif + register_pxp_device(); + pm_runtime_enable(pxp->dev); + +exit: + if (err) + dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n"); + return err; +} + +static int pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + unregister_pxp_device(); + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + kthread_stop(pxp->dispatch); + cancel_work_sync(&pxp->work); + del_timer_sync(&pxp->clk_timer); + clk_disable_unprepare(pxp->ipg_clk); + clk_disable_unprepare(pxp->axi_clk); + pxp_remove_attrs(pdev); + dma_async_device_unregister(&(pxp->pxp_dma.dma)); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pxp_suspend(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} + +static int pxp_resume(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + /* Pull PxP out of reset */ + pxp_soft_reset(pxp); + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + /* enable all the possible irq raised by PXP */ + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + pxp_clk_disable(pxp); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +#ifdef CONFIG_PM +static int pxp_runtime_suspend(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high release.\n"); + + return 0; +} + +static int pxp_runtime_resume(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high request.\n"); + + return 0; +} +#else +#define pxp_runtime_suspend NULL +#define pxp_runtime_resume NULL +#endif + +static const struct dev_pm_ops pxp_pm_ops = { + SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume) +}; + +static struct platform_driver pxp_driver = { + .driver = { + .name = "imx-pxp-v3", + .of_match_table = of_match_ptr(imx_pxpdma_dt_ids), + .pm = &pxp_pm_ops, + }, + .probe = pxp_probe, + .remove = pxp_remove, +}; + +static int __init pxp_init(void) +{ + return platform_driver_register(&pxp_driver); +} +late_initcall(pxp_init); + +static void __exit pxp_exit(void) +{ + platform_driver_unregister(&pxp_driver); +} +module_exit(pxp_exit); + + +MODULE_DESCRIPTION("i.MX PxP driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/pxp/reg_bitfields.h linux-imx-phytec/drivers/dma/pxp/reg_bitfields.h --- linux-6.1.55/drivers/dma/pxp/reg_bitfields.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/dma/pxp/reg_bitfields.h 2024-06-19 12:33:59.836218832 +0200 @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef _REG_BITFIELDS_H +#define _REG_BITFIELDS_H +struct mux_config { + uint32_t mux0_sel : 2; + uint32_t mux1_sel : 2; + uint32_t mux2_sel : 2; + uint32_t mux3_sel : 2; + uint32_t mux4_sel : 2; + uint32_t mux5_sel : 2; + uint32_t mux6_sel : 2; + uint32_t mux7_sel : 2; + uint32_t mux8_sel : 2; + uint32_t mux9_sel : 2; + uint32_t mux10_sel : 2; + uint32_t mux11_sel : 2; + uint32_t mux12_sel : 2; + uint32_t mux13_sel : 2; + uint32_t mux14_sel : 2; + uint32_t mux15_sel : 2; +}; + +/* legacy engine registers */ +struct ps_ctrl { + uint32_t format : 6; + uint32_t wb_swap : 1; + uint32_t rsvd0 : 1; + uint32_t decy : 2; + uint32_t decx : 2; + uint32_t rsvd1 : 20; +}; + +struct ps_scale { + uint32_t xscale : 15; + uint32_t rsvd1 : 1; + uint32_t yscale : 15; + uint32_t rsvd2 : 1; +}; + +struct ps_offset { + uint32_t xoffset : 12; + uint32_t rsvd1 : 4; + uint32_t yoffset : 12; + uint32_t rsvd2 : 4; +}; + +struct as_ctrl { + uint32_t rsvd0 : 1; + uint32_t alpha_ctrl : 2; + uint32_t enable_colorkey : 1; + uint32_t format : 4; + uint32_t alpha : 8; + uint32_t rop : 4; + uint32_t alpha0_invert : 1; + uint32_t alpha1_invert : 1; + uint32_t rsvd1 : 10; +}; + +struct out_ctrl { + uint32_t format : 5; + uint32_t rsvd0 : 3; + uint32_t interlaced_output : 2; + uint32_t rsvd1 : 13; + uint32_t alpha_output : 1; + uint32_t alpha : 8; +}; + +struct coordinate { + uint32_t y : 14; + uint32_t rsvd0 : 2; + uint32_t x : 14; + uint32_t rsvd1 : 2; +}; + +struct pxp_alpha_ctrl { + uint32_t poter_duff_enable : 1; + uint32_t s0_s1_factor_mode : 2; + uint32_t s0_global_alpha_mode : 2; + uint32_t s0_alpha_mode : 1; + uint32_t s0_color_mode : 1; + uint32_t rsvd1 : 1; + uint32_t s1_s0_factor_mode : 2; + uint32_t s1_global_alpha_mode : 2; + uint32_t s1_alpha_mode : 1; + uint32_t s1_color_mode : 1; + uint32_t rsvd0 : 2; + uint32_t s0_global_alpha : 8; + uint32_t s1_global_alpha : 8; +}; + +/* store engine registers */ +struct store_ctrl { + uint32_t ch_en : 1; + uint32_t block_en : 1; + uint32_t block_16 : 1; + uint32_t handshake_en : 1; + uint32_t array_en : 1; + uint32_t array_line_num : 2; + uint32_t rsvd3 : 1; + uint32_t store_bypass_en : 1; + uint32_t store_memory_en : 1; + uint32_t pack_in_sel : 1; + uint32_t fill_data_en : 1; + uint32_t rsvd2 : 4; + uint32_t wr_num_bytes : 2; + uint32_t rsvd1 : 6; + uint32_t combine_2channel : 1; + uint32_t rsvd0 : 6; + uint32_t arbit_en : 1; +}; + +struct store_size { + uint32_t out_width : 16; + uint32_t out_height : 16; +}; + +struct store_pitch { + uint32_t ch0_out_pitch : 16; + uint32_t ch1_out_pitch : 16; +}; + +struct store_shift_ctrl { + uint32_t rsvd2 : 2; + uint32_t output_active_bpp : 2; + uint32_t out_yuv422_1p_en : 1; + uint32_t out_yuv422_2p_en : 1; + uint32_t rsvd1 : 1; + uint32_t shift_bypass : 1; + uint32_t rsvd0 : 24; +}; + +struct store_d_shift { + uint64_t d_shift_width0 : 6; + uint64_t rsvd3 : 1; + uint64_t d_shift_flag0 : 1; + uint64_t d_shift_width1 : 6; + uint64_t rsvd2 : 1; + uint64_t d_shift_flag1 : 1; + uint64_t d_shift_width2 : 6; + uint64_t rsvd1 : 1; + uint64_t d_shift_flag2 : 1; + uint64_t d_shift_width3 : 6; + uint64_t rsvd0 : 1; + uint64_t d_shift_flag3 : 1; + + uint64_t d_shift_width4 : 6; + uint64_t rsvd7 : 1; + uint64_t d_shift_flag4 : 1; + uint64_t d_shift_width5 : 6; + uint64_t rsvd6 : 1; + uint64_t d_shift_flag5 : 1; + uint64_t d_shift_width6 : 6; + uint64_t rsvd5 : 1; + uint64_t d_shift_flag6 : 1; + uint64_t d_shift_width7 : 6; + uint64_t rsvd4 : 1; + uint64_t d_shift_flag7 : 1; +}; + +struct store_f_shift { + uint64_t f_shift_width0 : 6; + uint64_t rsvd3 : 1; + uint64_t f_shift_flag0 : 1; + uint64_t f_shift_width1 : 6; + uint64_t rsvd2 : 1; + uint64_t f_shift_flag1 : 1; + uint64_t f_shift_width2 : 6; + uint64_t rsvd1 : 1; + uint64_t f_shift_flag2 : 1; + uint64_t f_shift_width3 : 6; + uint64_t rsvd0 : 1; + uint64_t f_shift_flag3 : 1; + + uint64_t f_shift_width4 : 6; + uint64_t rsvd7 : 1; + uint64_t f_shift_flag4 : 1; + uint64_t f_shift_width5 : 6; + uint64_t rsvd6 : 1; + uint64_t f_shift_flag5 : 1; + uint64_t f_shift_width6 : 6; + uint64_t rsvd5 : 1; + uint64_t f_shift_flag6 : 1; + uint64_t f_shift_width7 : 6; + uint64_t rsvd4 : 1; + uint64_t f_shift_flag7 : 1; +}; + +struct store_d_mask { + uint64_t d_mask_l : 32; + uint64_t d_mask_h : 32; +}; + +/* fetch engine registers */ +struct fetch_ctrl { + uint32_t ch_en : 1; + uint32_t block_en : 1; + uint32_t block_16 : 1; + uint32_t handshake_en : 1; + uint32_t bypass_pixel_en : 1; + uint32_t high_byte : 1; + uint32_t rsvd4 : 3; + uint32_t hflip : 1; + uint32_t vflip : 1; + uint32_t rsvd3 : 1; + uint32_t rotation_angle : 2; + uint32_t rsvd2 : 2; + uint32_t rd_num_bytes : 2; + uint32_t rsvd1 : 6; + uint32_t handshake_scan_line_num : 2; + uint32_t rsvd0 : 5; + uint32_t arbit_en : 1; +}; + +struct fetch_active_size_ulc { + uint32_t active_size_ulc_x : 16; + uint32_t active_size_ulc_y : 16; +}; + +struct fetch_active_size_lrc { + uint32_t active_size_lrc_x : 16; + uint32_t active_size_lrc_y : 16; +}; + +struct fetch_size { + uint32_t input_total_width : 16; + uint32_t input_total_height : 16; +}; + +struct fetch_pitch { + uint32_t ch0_input_pitch : 16; + uint32_t ch1_input_pitch : 16; +}; + +struct fetch_shift_ctrl { + uint32_t input_active_bpp : 2; + uint32_t rsvd1 : 6; + uint32_t expand_format : 3; + uint32_t expand_en : 1; + uint32_t shift_bypass : 1; + uint32_t rsvd0 : 19; +}; + +struct fetch_shift_offset { + uint32_t offset0 : 5; + uint32_t rsvd3 : 3; + uint32_t offset1 : 5; + uint32_t rsvd2 : 3; + uint32_t offset2 : 5; + uint32_t rsvd1 : 3; + uint32_t offset3 : 5; + uint32_t rsvd0 : 3; +}; + +struct fetch_shift_width { + uint32_t width0 : 4; + uint32_t width1 : 4; + uint32_t width2 : 4; + uint32_t width3 : 4; + uint32_t rsvd0 : 16; +}; +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/pxp/regs-pxp_v2.h linux-imx-phytec/drivers/dma/pxp/regs-pxp_v2.h --- linux-6.1.55/drivers/dma/pxp/regs-pxp_v2.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/dma/pxp/regs-pxp_v2.h 2024-06-19 12:33:59.836218832 +0200 @@ -0,0 +1,1139 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Freescale PXP Register Definitions + * + * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.29 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BM_PXP_CTRL_RSVD4 0x20000000 +#define BM_PXP_CTRL_EN_REPEAT 0x10000000 +#define BP_PXP_CTRL_RSVD3 26 +#define BM_PXP_CTRL_RSVD3 0x0C000000 +#define BF_PXP_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_CTRL_RSVD3) +#define BP_PXP_CTRL_INTERLACED_INPUT 24 +#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 +#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ + (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) +#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_ROT_POS 0x00400000 +#define BM_PXP_CTRL_IN_PLACE 0x00200000 +#define BP_PXP_CTRL_RSVD1 12 +#define BM_PXP_CTRL_RSVD1 0x001FF000 +#define BF_PXP_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_CTRL_RSVD1) +#define BM_PXP_CTRL_VFLIP 0x00000800 +#define BM_PXP_CTRL_HFLIP 0x00000400 +#define BP_PXP_CTRL_ROTATE 8 +#define BM_PXP_CTRL_ROTATE 0x00000300 +#define BF_PXP_CTRL_ROTATE(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE) +#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 +#define BP_PXP_CTRL_RSVD0 5 +#define BM_PXP_CTRL_RSVD0 0x000000E0 +#define BF_PXP_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_CTRL_RSVD0) +#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000010 +#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008 +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_RSVD2 9 +#define BM_PXP_STAT_RSVD2 0x0000FE00 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 9) & BM_PXP_STAT_RSVD2) +#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100 +#define BP_PXP_STAT_AXI_ERROR_ID 4 +#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 +#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 +#define BM_PXP_STAT_IRQ 0x00000001 + +#define HW_PXP_OUT_CTRL (0x00000020) +#define HW_PXP_OUT_CTRL_SET (0x00000024) +#define HW_PXP_OUT_CTRL_CLR (0x00000028) +#define HW_PXP_OUT_CTRL_TOG (0x0000002c) + +#define BP_PXP_OUT_CTRL_ALPHA 24 +#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000 +#define BF_PXP_OUT_CTRL_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA) +#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000 +#define BP_PXP_OUT_CTRL_RSVD1 10 +#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00 +#define BF_PXP_OUT_CTRL_RSVD1(v) \ + (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1) +#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8 +#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300 +#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_OUT_CTRL_RSVD0 5 +#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0 +#define BF_PXP_OUT_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0) +#define BP_PXP_OUT_CTRL_FORMAT 0 +#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F +#define BF_PXP_OUT_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) +#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B + +#define HW_PXP_OUT_BUF (0x00000030) + +#define BP_PXP_OUT_BUF_ADDR 0 +#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF_ADDR(v) (v) + +#define HW_PXP_OUT_BUF2 (0x00000040) + +#define BP_PXP_OUT_BUF2_ADDR 0 +#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF2_ADDR(v) (v) + +#define HW_PXP_OUT_PITCH (0x00000050) + +#define BP_PXP_OUT_PITCH_RSVD 16 +#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_OUT_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_OUT_PITCH_RSVD) +#define BP_PXP_OUT_PITCH_PITCH 0 +#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF +#define BF_PXP_OUT_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_OUT_PITCH_PITCH) + +#define HW_PXP_OUT_LRC (0x00000060) + +#define BP_PXP_OUT_LRC_RSVD1 30 +#define BM_PXP_OUT_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_LRC_RSVD1) +#define BP_PXP_OUT_LRC_X 16 +#define BM_PXP_OUT_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_LRC_X) +#define BP_PXP_OUT_LRC_RSVD0 14 +#define BM_PXP_OUT_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_LRC_RSVD0) +#define BP_PXP_OUT_LRC_Y 0 +#define BM_PXP_OUT_LRC_Y 0x00003FFF +#define BF_PXP_OUT_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_LRC_Y) + +#define HW_PXP_OUT_PS_ULC (0x00000070) + +#define BP_PXP_OUT_PS_ULC_RSVD1 30 +#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1) +#define BP_PXP_OUT_PS_ULC_X 16 +#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_ULC_X) +#define BP_PXP_OUT_PS_ULC_RSVD0 14 +#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0) +#define BP_PXP_OUT_PS_ULC_Y 0 +#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_PS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_ULC_Y) + +#define HW_PXP_OUT_PS_LRC (0x00000080) + +#define BP_PXP_OUT_PS_LRC_RSVD1 30 +#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1) +#define BP_PXP_OUT_PS_LRC_X 16 +#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_LRC_X) +#define BP_PXP_OUT_PS_LRC_RSVD0 14 +#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0) +#define BP_PXP_OUT_PS_LRC_Y 0 +#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_PS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_LRC_Y) + +#define HW_PXP_OUT_AS_ULC (0x00000090) + +#define BP_PXP_OUT_AS_ULC_RSVD1 30 +#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1) +#define BP_PXP_OUT_AS_ULC_X 16 +#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_ULC_X) +#define BP_PXP_OUT_AS_ULC_RSVD0 14 +#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0) +#define BP_PXP_OUT_AS_ULC_Y 0 +#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_AS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_ULC_Y) + +#define HW_PXP_OUT_AS_LRC (0x000000a0) + +#define BP_PXP_OUT_AS_LRC_RSVD1 30 +#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1) +#define BP_PXP_OUT_AS_LRC_X 16 +#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_LRC_X) +#define BP_PXP_OUT_AS_LRC_RSVD0 14 +#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0) +#define BP_PXP_OUT_AS_LRC_Y 0 +#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_AS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_LRC_Y) + +#define HW_PXP_PS_CTRL (0x000000b0) +#define HW_PXP_PS_CTRL_SET (0x000000b4) +#define HW_PXP_PS_CTRL_CLR (0x000000b8) +#define HW_PXP_PS_CTRL_TOG (0x000000bc) + +#define BP_PXP_PS_CTRL_RSVD1 12 +#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000 +#define BF_PXP_PS_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_CTRL_RSVD1) +#define BP_PXP_PS_CTRL_DECX 10 +#define BM_PXP_PS_CTRL_DECX 0x00000C00 +#define BF_PXP_PS_CTRL_DECX(v) \ + (((v) << 10) & BM_PXP_PS_CTRL_DECX) +#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECX__DECX2 0x1 +#define BV_PXP_PS_CTRL_DECX__DECX4 0x2 +#define BV_PXP_PS_CTRL_DECX__DECX8 0x3 +#define BP_PXP_PS_CTRL_DECY 8 +#define BM_PXP_PS_CTRL_DECY 0x00000300 +#define BF_PXP_PS_CTRL_DECY(v) \ + (((v) << 8) & BM_PXP_PS_CTRL_DECY) +#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECY__DECY2 0x1 +#define BV_PXP_PS_CTRL_DECY__DECY4 0x2 +#define BV_PXP_PS_CTRL_DECY__DECY8 0x3 +#define BP_PXP_PS_CTRL_SWAP 5 +#define BM_PXP_PS_CTRL_SWAP 0x000000E0 +#define BF_PXP_PS_CTRL_SWAP(v) \ + (((v) << 5) & BM_PXP_PS_CTRL_SWAP) +#define BP_PXP_PS_CTRL_FORMAT 0 +#define BM_PXP_PS_CTRL_FORMAT 0x0000001F +#define BF_PXP_PS_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) +#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B +#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E +#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F + +#define HW_PXP_PS_BUF (0x000000c0) + +#define BP_PXP_PS_BUF_ADDR 0 +#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_BUF_ADDR(v) (v) + +#define HW_PXP_PS_UBUF (0x000000d0) + +#define BP_PXP_PS_UBUF_ADDR 0 +#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_UBUF_ADDR(v) (v) + +#define HW_PXP_PS_VBUF (0x000000e0) + +#define BP_PXP_PS_VBUF_ADDR 0 +#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_VBUF_ADDR(v) (v) + +#define HW_PXP_PS_PITCH (0x000000f0) + +#define BP_PXP_PS_PITCH_RSVD 16 +#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_PS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_PS_PITCH_RSVD) +#define BP_PXP_PS_PITCH_PITCH 0 +#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_PS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_PS_PITCH_PITCH) + +#define HW_PXP_PS_BACKGROUND (0x00000100) + +#define BP_PXP_PS_BACKGROUND_RSVD 24 +#define BM_PXP_PS_BACKGROUND_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_RSVD) +#define BP_PXP_PS_BACKGROUND_COLOR 0 +#define BM_PXP_PS_BACKGROUND_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_COLOR) + +#define HW_PXP_PS_SCALE (0x00000110) + +#define BM_PXP_PS_SCALE_RSVD2 0x80000000 +#define BP_PXP_PS_SCALE_YSCALE 16 +#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_PS_SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) +#define BM_PXP_PS_SCALE_RSVD1 0x00008000 +#define BP_PXP_PS_SCALE_XSCALE 0 +#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF +#define BF_PXP_PS_SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) + +#define HW_PXP_PS_OFFSET (0x00000120) + +#define BP_PXP_PS_OFFSET_RSVD2 28 +#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000 +#define BF_PXP_PS_OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2) +#define BP_PXP_PS_OFFSET_YOFFSET 16 +#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_PS_OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET) +#define BP_PXP_PS_OFFSET_RSVD1 12 +#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_PS_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1) +#define BP_PXP_PS_OFFSET_XOFFSET 0 +#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_PS_OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET) + +#define HW_PXP_PS_CLRKEYLOW (0x00000130) + +#define BP_PXP_PS_CLRKEYLOW_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH (0x00000140) + +#define BP_PXP_PS_CLRKEYHIGH_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_PIXEL) + +#define HW_PXP_AS_CTRL (0x00000150) + +#define BP_PXP_AS_CTRL_RSVD1 21 +#define BM_PXP_AS_CTRL_RSVD1 0xFFE00000 +#define BF_PXP_AS_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_AS_CTRL_RSVD1) +#define BM_PXP_AS_CTRL_ALPHA_INVERT 0x00100000 +#define BP_PXP_AS_CTRL_ROP 16 +#define BM_PXP_AS_CTRL_ROP 0x000F0000 +#define BF_PXP_AS_CTRL_ROP(v) \ + (((v) << 16) & BM_PXP_AS_CTRL_ROP) +#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0 +#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 +#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2 +#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3 +#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4 +#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5 +#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6 +#define BV_PXP_AS_CTRL_ROP__NOT 0x7 +#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8 +#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9 +#define BV_PXP_AS_CTRL_ROP__XORAS 0xA +#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB +#define BP_PXP_AS_CTRL_ALPHA 8 +#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00 +#define BF_PXP_AS_CTRL_ALPHA(v) \ + (((v) << 8) & BM_PXP_AS_CTRL_ALPHA) +#define BP_PXP_AS_CTRL_FORMAT 4 +#define BM_PXP_AS_CTRL_FORMAT 0x000000F0 +#define BF_PXP_AS_CTRL_FORMAT(v) \ + (((v) << 4) & BM_PXP_AS_CTRL_FORMAT) +#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE +#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008 +#define BP_PXP_AS_CTRL_ALPHA_CTRL 1 +#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006 +#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \ + (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL) +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3 +#define BM_PXP_AS_CTRL_RSVD0 0x00000001 + +#define HW_PXP_AS_BUF (0x00000160) + +#define BP_PXP_AS_BUF_ADDR 0 +#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_AS_BUF_ADDR(v) (v) + +#define HW_PXP_AS_PITCH (0x00000170) + +#define BP_PXP_AS_PITCH_RSVD 16 +#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_AS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_AS_PITCH_RSVD) +#define BP_PXP_AS_PITCH_PITCH 0 +#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_AS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_AS_PITCH_PITCH) + +#define HW_PXP_AS_CLRKEYLOW (0x00000180) + +#define BP_PXP_AS_CLRKEYLOW_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH (0x00000190) + +#define BP_PXP_AS_CLRKEYHIGH_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_PIXEL) + +#define HW_PXP_CSC1_COEF0 (0x000001a0) + +#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000 +#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000 +#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000 +#define BP_PXP_CSC1_COEF0_C0 18 +#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000 +#define BF_PXP_CSC1_COEF0_C0(v) \ + (((v) << 18) & BM_PXP_CSC1_COEF0_C0) +#define BP_PXP_CSC1_COEF0_UV_OFFSET 9 +#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET) +#define BP_PXP_CSC1_COEF0_Y_OFFSET 0 +#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET) + +#define HW_PXP_CSC1_COEF1 (0x000001b0) + +#define BP_PXP_CSC1_COEF1_RSVD1 27 +#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1) +#define BP_PXP_CSC1_COEF1_C1 16 +#define BM_PXP_CSC1_COEF1_C1 0x07FF0000 +#define BF_PXP_CSC1_COEF1_C1(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF1_C1) +#define BP_PXP_CSC1_COEF1_RSVD0 11 +#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0) +#define BP_PXP_CSC1_COEF1_C4 0 +#define BM_PXP_CSC1_COEF1_C4 0x000007FF +#define BF_PXP_CSC1_COEF1_C4(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF1_C4) + +#define HW_PXP_CSC1_COEF2 (0x000001c0) + +#define BP_PXP_CSC1_COEF2_RSVD1 27 +#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1) +#define BP_PXP_CSC1_COEF2_C2 16 +#define BM_PXP_CSC1_COEF2_C2 0x07FF0000 +#define BF_PXP_CSC1_COEF2_C2(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF2_C2) +#define BP_PXP_CSC1_COEF2_RSVD0 11 +#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0) +#define BP_PXP_CSC1_COEF2_C3 0 +#define BM_PXP_CSC1_COEF2_C3 0x000007FF +#define BF_PXP_CSC1_COEF2_C3(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF2_C3) + +#define HW_PXP_CSC2_CTRL (0x000001d0) + +#define BP_PXP_CSC2_CTRL_RSVD 3 +#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8 +#define BF_PXP_CSC2_CTRL_RSVD(v) \ + (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD) +#define BP_PXP_CSC2_CTRL_CSC_MODE 1 +#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006 +#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \ + (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE) +#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0 +#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3 +#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001 + +#define HW_PXP_CSC2_COEF0 (0x000001e0) + +#define BP_PXP_CSC2_COEF0_RSVD1 27 +#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF0_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1) +#define BP_PXP_CSC2_COEF0_A2 16 +#define BM_PXP_CSC2_COEF0_A2 0x07FF0000 +#define BF_PXP_CSC2_COEF0_A2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF0_A2) +#define BP_PXP_CSC2_COEF0_RSVD0 11 +#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF0_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0) +#define BP_PXP_CSC2_COEF0_A1 0 +#define BM_PXP_CSC2_COEF0_A1 0x000007FF +#define BF_PXP_CSC2_COEF0_A1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF0_A1) + +#define HW_PXP_CSC2_COEF1 (0x000001f0) + +#define BP_PXP_CSC2_COEF1_RSVD1 27 +#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1) +#define BP_PXP_CSC2_COEF1_B1 16 +#define BM_PXP_CSC2_COEF1_B1 0x07FF0000 +#define BF_PXP_CSC2_COEF1_B1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF1_B1) +#define BP_PXP_CSC2_COEF1_RSVD0 11 +#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0) +#define BP_PXP_CSC2_COEF1_A3 0 +#define BM_PXP_CSC2_COEF1_A3 0x000007FF +#define BF_PXP_CSC2_COEF1_A3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF1_A3) + +#define HW_PXP_CSC2_COEF2 (0x00000200) + +#define BP_PXP_CSC2_COEF2_RSVD1 27 +#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1) +#define BP_PXP_CSC2_COEF2_B3 16 +#define BM_PXP_CSC2_COEF2_B3 0x07FF0000 +#define BF_PXP_CSC2_COEF2_B3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF2_B3) +#define BP_PXP_CSC2_COEF2_RSVD0 11 +#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0) +#define BP_PXP_CSC2_COEF2_B2 0 +#define BM_PXP_CSC2_COEF2_B2 0x000007FF +#define BF_PXP_CSC2_COEF2_B2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF2_B2) + +#define HW_PXP_CSC2_COEF3 (0x00000210) + +#define BP_PXP_CSC2_COEF3_RSVD1 27 +#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF3_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1) +#define BP_PXP_CSC2_COEF3_C2 16 +#define BM_PXP_CSC2_COEF3_C2 0x07FF0000 +#define BF_PXP_CSC2_COEF3_C2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF3_C2) +#define BP_PXP_CSC2_COEF3_RSVD0 11 +#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF3_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0) +#define BP_PXP_CSC2_COEF3_C1 0 +#define BM_PXP_CSC2_COEF3_C1 0x000007FF +#define BF_PXP_CSC2_COEF3_C1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF3_C1) + +#define HW_PXP_CSC2_COEF4 (0x00000220) + +#define BP_PXP_CSC2_COEF4_RSVD1 25 +#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF4_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1) +#define BP_PXP_CSC2_COEF4_D1 16 +#define BM_PXP_CSC2_COEF4_D1 0x01FF0000 +#define BF_PXP_CSC2_COEF4_D1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF4_D1) +#define BP_PXP_CSC2_COEF4_RSVD0 11 +#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF4_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0) +#define BP_PXP_CSC2_COEF4_C3 0 +#define BM_PXP_CSC2_COEF4_C3 0x000007FF +#define BF_PXP_CSC2_COEF4_C3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF4_C3) + +#define HW_PXP_CSC2_COEF5 (0x00000230) + +#define BP_PXP_CSC2_COEF5_RSVD1 25 +#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF5_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1) +#define BP_PXP_CSC2_COEF5_D3 16 +#define BM_PXP_CSC2_COEF5_D3 0x01FF0000 +#define BF_PXP_CSC2_COEF5_D3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF5_D3) +#define BP_PXP_CSC2_COEF5_RSVD0 9 +#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00 +#define BF_PXP_CSC2_COEF5_RSVD0(v) \ + (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0) +#define BP_PXP_CSC2_COEF5_D2 0 +#define BM_PXP_CSC2_COEF5_D2 0x000001FF +#define BF_PXP_CSC2_COEF5_D2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF5_D2) + +#define HW_PXP_LUT_CTRL (0x00000240) + +#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 +#define BP_PXP_LUT_CTRL_RSVD3 26 +#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000 +#define BF_PXP_LUT_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3) +#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24 +#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000 +#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \ + (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE) +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3 +#define BP_PXP_LUT_CTRL_RSVD2 18 +#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000 +#define BF_PXP_LUT_CTRL_RSVD2(v) \ + (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2) +#define BP_PXP_LUT_CTRL_OUT_MODE 16 +#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000 +#define BF_PXP_LUT_CTRL_OUT_MODE(v) \ + (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE) +#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0 +#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3 +#define BP_PXP_LUT_CTRL_RSVD1 11 +#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800 +#define BF_PXP_LUT_CTRL_RSVD1(v) \ + (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1) +#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400 +#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200 +#define BM_PXP_LUT_CTRL_INVALID 0x00000100 +#define BP_PXP_LUT_CTRL_RSVD0 1 +#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE +#define BF_PXP_LUT_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0) +#define BM_PXP_LUT_CTRL_DMA_START 0x00000001 + +#define HW_PXP_LUT_ADDR (0x00000250) + +#define BM_PXP_LUT_ADDR_RSVD2 0x80000000 +#define BP_PXP_LUT_ADDR_NUM_BYTES 16 +#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000 +#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES) +#define BP_PXP_LUT_ADDR_RSVD1 14 +#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000 +#define BF_PXP_LUT_ADDR_RSVD1(v) \ + (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1) +#define BP_PXP_LUT_ADDR_ADDR 0 +#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF +#define BF_PXP_LUT_ADDR_ADDR(v) \ + (((v) << 0) & BM_PXP_LUT_ADDR_ADDR) + +#define HW_PXP_LUT_DATA (0x00000260) + +#define BP_PXP_LUT_DATA_DATA 0 +#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF +#define BF_PXP_LUT_DATA_DATA(v) (v) + +#define HW_PXP_LUT_EXTMEM (0x00000270) + +#define BP_PXP_LUT_EXTMEM_ADDR 0 +#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF +#define BF_PXP_LUT_EXTMEM_ADDR(v) (v) + +#define HW_PXP_CFA (0x00000280) + +#define BP_PXP_CFA_DATA 0 +#define BM_PXP_CFA_DATA 0xFFFFFFFF +#define BF_PXP_CFA_DATA(v) (v) + +#define HW_PXP_HIST_CTRL (0x00000290) + +#define BP_PXP_HIST_CTRL_RSVD 6 +#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0 +#define BF_PXP_HIST_CTRL_RSVD(v) \ + (((v) << 6) & BM_PXP_HIST_CTRL_RSVD) +#define BP_PXP_HIST_CTRL_PANEL_MODE 4 +#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030 +#define BF_PXP_HIST_CTRL_PANEL_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE) +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4 0x0 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8 0x1 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3 +#define BP_PXP_HIST_CTRL_STATUS 0 +#define BM_PXP_HIST_CTRL_STATUS 0x0000000F +#define BF_PXP_HIST_CTRL_STATUS(v) \ + (((v) << 0) & BM_PXP_HIST_CTRL_STATUS) + +#define HW_PXP_HIST2_PARAM (0x000002a0) + +#define BP_PXP_HIST2_PARAM_RSVD 16 +#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 +#define BF_PXP_HIST2_PARAM_RSVD(v) \ + (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) +#define BP_PXP_HIST2_PARAM_RSVD1 13 +#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST2_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1) +#define BP_PXP_HIST2_PARAM_VALUE1 8 +#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST2_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) +#define BP_PXP_HIST2_PARAM_RSVD0 5 +#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST2_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0) +#define BP_PXP_HIST2_PARAM_VALUE0 0 +#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST2_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) + +#define HW_PXP_HIST4_PARAM (0x000002b0) + +#define BP_PXP_HIST4_PARAM_RSVD3 29 +#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000 +#define BF_PXP_HIST4_PARAM_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3) +#define BP_PXP_HIST4_PARAM_VALUE3 24 +#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000 +#define BF_PXP_HIST4_PARAM_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) +#define BP_PXP_HIST4_PARAM_RSVD2 21 +#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000 +#define BF_PXP_HIST4_PARAM_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2) +#define BP_PXP_HIST4_PARAM_VALUE2 16 +#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000 +#define BF_PXP_HIST4_PARAM_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) +#define BP_PXP_HIST4_PARAM_RSVD1 13 +#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST4_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1) +#define BP_PXP_HIST4_PARAM_VALUE1 8 +#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST4_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) +#define BP_PXP_HIST4_PARAM_RSVD0 5 +#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST4_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0) +#define BP_PXP_HIST4_PARAM_VALUE0 0 +#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST4_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) + +#define HW_PXP_HIST8_PARAM0 (0x000002c0) + +#define BP_PXP_HIST8_PARAM0_RSVD3 29 +#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3) +#define BP_PXP_HIST8_PARAM0_VALUE3 24 +#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) +#define BP_PXP_HIST8_PARAM0_RSVD2 21 +#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2) +#define BP_PXP_HIST8_PARAM0_VALUE2 16 +#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) +#define BP_PXP_HIST8_PARAM0_RSVD1 13 +#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1) +#define BP_PXP_HIST8_PARAM0_VALUE1 8 +#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) +#define BP_PXP_HIST8_PARAM0_RSVD0 5 +#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0) +#define BP_PXP_HIST8_PARAM0_VALUE0 0 +#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) + +#define HW_PXP_HIST8_PARAM1 (0x000002d0) + +#define BP_PXP_HIST8_PARAM1_RSVD7 29 +#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7) +#define BP_PXP_HIST8_PARAM1_VALUE7 24 +#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) +#define BP_PXP_HIST8_PARAM1_RSVD6 21 +#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6) +#define BP_PXP_HIST8_PARAM1_VALUE6 16 +#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) +#define BP_PXP_HIST8_PARAM1_RSVD5 13 +#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5) +#define BP_PXP_HIST8_PARAM1_VALUE5 8 +#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) +#define BP_PXP_HIST8_PARAM1_RSVD4 5 +#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4) +#define BP_PXP_HIST8_PARAM1_VALUE4 0 +#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM0 (0x000002e0) + +#define BP_PXP_HIST16_PARAM0_RSVD3 29 +#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3) +#define BP_PXP_HIST16_PARAM0_VALUE3 24 +#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) +#define BP_PXP_HIST16_PARAM0_RSVD2 21 +#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2) +#define BP_PXP_HIST16_PARAM0_VALUE2 16 +#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) +#define BP_PXP_HIST16_PARAM0_RSVD1 13 +#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1) +#define BP_PXP_HIST16_PARAM0_VALUE1 8 +#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) +#define BP_PXP_HIST16_PARAM0_RSVD0 5 +#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0) +#define BP_PXP_HIST16_PARAM0_VALUE0 0 +#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) + +#define HW_PXP_HIST16_PARAM1 (0x000002f0) + +#define BP_PXP_HIST16_PARAM1_RSVD7 29 +#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7) +#define BP_PXP_HIST16_PARAM1_VALUE7 24 +#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) +#define BP_PXP_HIST16_PARAM1_RSVD6 21 +#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6) +#define BP_PXP_HIST16_PARAM1_VALUE6 16 +#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) +#define BP_PXP_HIST16_PARAM1_RSVD5 13 +#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5) +#define BP_PXP_HIST16_PARAM1_VALUE5 8 +#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) +#define BP_PXP_HIST16_PARAM1_RSVD4 5 +#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4) +#define BP_PXP_HIST16_PARAM1_VALUE4 0 +#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM2 (0x00000300) + +#define BP_PXP_HIST16_PARAM2_RSVD11 29 +#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000 +#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11) +#define BP_PXP_HIST16_PARAM2_VALUE11 24 +#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000 +#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) +#define BP_PXP_HIST16_PARAM2_RSVD10 21 +#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000 +#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10) +#define BP_PXP_HIST16_PARAM2_VALUE10 16 +#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000 +#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) +#define BP_PXP_HIST16_PARAM2_RSVD9 13 +#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000 +#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9) +#define BP_PXP_HIST16_PARAM2_VALUE9 8 +#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00 +#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) +#define BP_PXP_HIST16_PARAM2_RSVD8 5 +#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0 +#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8) +#define BP_PXP_HIST16_PARAM2_VALUE8 0 +#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F +#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) + +#define HW_PXP_HIST16_PARAM3 (0x00000310) + +#define BP_PXP_HIST16_PARAM3_RSVD15 29 +#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000 +#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15) +#define BP_PXP_HIST16_PARAM3_VALUE15 24 +#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000 +#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) +#define BP_PXP_HIST16_PARAM3_RSVD14 21 +#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000 +#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14) +#define BP_PXP_HIST16_PARAM3_VALUE14 16 +#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000 +#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) +#define BP_PXP_HIST16_PARAM3_RSVD13 13 +#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000 +#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13) +#define BP_PXP_HIST16_PARAM3_VALUE13 8 +#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00 +#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) +#define BP_PXP_HIST16_PARAM3_RSVD12 5 +#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0 +#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12) +#define BP_PXP_HIST16_PARAM3_VALUE12 0 +#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F +#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) + +#define HW_PXP_POWER (0x00000320) + +#define BP_PXP_POWER_CTRL 12 +#define BM_PXP_POWER_CTRL 0xFFFFF000 +#define BF_PXP_POWER_CTRL(v) \ + (((v) << 12) & BM_PXP_POWER_CTRL) +#define BP_PXP_POWER_ROT_MEM_LP_STATE 9 +#define BM_PXP_POWER_ROT_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_ROT_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_ROT_MEM_LP_STATE) +#define BV_PXP_POWER_ROT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 6 +#define BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 0x000001C0 +#define BF_PXP_POWER_LUT_LP_STATE_WAY1_BANKN(v) \ + (((v) << 6) & BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN) +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 3 +#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 0x00000038 +#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANKN(v) \ + (((v) << 3) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN) +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0 +#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0x00000007 +#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANK0(v) \ + (((v) << 0) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0) +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__SD 0x4 + +#define HW_PXP_NEXT (0x00000400) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BM_PXP_NEXT_ENABLED 0x00000001 + +#define HW_PXP_DEBUGCTRL (0x00000410) + +#define BP_PXP_DEBUGCTRL_RSVD 12 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD) +#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8 +#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00 +#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \ + (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT) +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14 + +#define HW_PXP_DEBUG (0x00000420) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x00000430) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) +#endif /* __ARCH_ARM___PXP_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma/pxp/regs-pxp_v3.h linux-imx-phytec/drivers/dma/pxp/regs-pxp_v3.h --- linux-6.1.55/drivers/dma/pxp/regs-pxp_v3.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/dma/pxp/regs-pxp_v3.h 2024-06-19 12:33:59.840218900 +0200 @@ -0,0 +1,26939 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Freescale PXP Register Definitions + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.77 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BF_PXP_CTRL_SFTRST(v) \ + (((v) << 31) & BM_PXP_CTRL_SFTRST) +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BF_PXP_CTRL_CLKGATE(v) \ + (((v) << 30) & BM_PXP_CTRL_CLKGATE) +#define BM_PXP_CTRL_RSVD4 0x20000000 +#define BF_PXP_CTRL_RSVD4(v) \ + (((v) << 29) & BM_PXP_CTRL_RSVD4) +#define BM_PXP_CTRL_EN_REPEAT 0x10000000 +#define BF_PXP_CTRL_EN_REPEAT(v) \ + (((v) << 28) & BM_PXP_CTRL_EN_REPEAT) +#define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000 +#define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ + (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1) +#define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000 +#define BF_PXP_CTRL_ENABLE_ROTATE0(v) \ + (((v) << 26) & BM_PXP_CTRL_ENABLE_ROTATE0) +#define BM_PXP_CTRL_ENABLE_LUT 0x02000000 +#define BF_PXP_CTRL_ENABLE_LUT(v) \ + (((v) << 25) & BM_PXP_CTRL_ENABLE_LUT) +#define BM_PXP_CTRL_ENABLE_CSC2 0x01000000 +#define BF_PXP_CTRL_ENABLE_CSC2(v) \ + (((v) << 24) & BM_PXP_CTRL_ENABLE_CSC2) +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BF_PXP_CTRL_BLOCK_SIZE(v) \ + (((v) << 23) & BM_PXP_CTRL_BLOCK_SIZE) +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_RSVD1 0x00400000 +#define BF_PXP_CTRL_RSVD1(v) \ + (((v) << 22) & BM_PXP_CTRL_RSVD1) +#define BM_PXP_CTRL_ENABLE_ALPHA_B 0x00200000 +#define BF_PXP_CTRL_ENABLE_ALPHA_B(v) \ + (((v) << 21) & BM_PXP_CTRL_ENABLE_ALPHA_B) +#define BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE 0x00100000 +#define BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(v) \ + (((v) << 20) & BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE) +#define BM_PXP_CTRL_ENABLE_WFE_B 0x00080000 +#define BF_PXP_CTRL_ENABLE_WFE_B(v) \ + (((v) << 19) & BM_PXP_CTRL_ENABLE_WFE_B) +#define BM_PXP_CTRL_ENABLE_WFE_A 0x00040000 +#define BF_PXP_CTRL_ENABLE_WFE_A(v) \ + (((v) << 18) & BM_PXP_CTRL_ENABLE_WFE_A) +#define BM_PXP_CTRL_ENABLE_DITHER 0x00020000 +#define BF_PXP_CTRL_ENABLE_DITHER(v) \ + (((v) << 17) & BM_PXP_CTRL_ENABLE_DITHER) +#define BM_PXP_CTRL_ENABLE_PS_AS_OUT 0x00010000 +#define BF_PXP_CTRL_ENABLE_PS_AS_OUT(v) \ + (((v) << 16) & BM_PXP_CTRL_ENABLE_PS_AS_OUT) +#define BM_PXP_CTRL_VFLIP1 0x00008000 +#define BF_PXP_CTRL_VFLIP1(v) \ + (((v) << 15) & BM_PXP_CTRL_VFLIP1) +#define BM_PXP_CTRL_HFLIP1 0x00004000 +#define BF_PXP_CTRL_HFLIP1(v) \ + (((v) << 14) & BM_PXP_CTRL_HFLIP1) +#define BP_PXP_CTRL_ROTATE1 12 +#define BM_PXP_CTRL_ROTATE1 0x00003000 +#define BF_PXP_CTRL_ROTATE1(v) \ + (((v) << 12) & BM_PXP_CTRL_ROTATE1) +#define BV_PXP_CTRL_ROTATE1__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE1__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE1__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE1__ROT_270 0x3 +#define BM_PXP_CTRL_VFLIP0 0x00000800 +#define BF_PXP_CTRL_VFLIP0(v) \ + (((v) << 11) & BM_PXP_CTRL_VFLIP0) +#define BM_PXP_CTRL_HFLIP0 0x00000400 +#define BF_PXP_CTRL_HFLIP0(v) \ + (((v) << 10) & BM_PXP_CTRL_HFLIP0) +#define BP_PXP_CTRL_ROTATE0 8 +#define BM_PXP_CTRL_ROTATE0 0x00000300 +#define BF_PXP_CTRL_ROTATE0(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE0) +#define BV_PXP_CTRL_ROTATE0__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE0__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE0__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE0__ROT_270 0x3 +#define BP_PXP_CTRL_RSVD0 6 +#define BM_PXP_CTRL_RSVD0 0x000000C0 +#define BF_PXP_CTRL_RSVD0(v) \ + (((v) << 6) & BM_PXP_CTRL_RSVD0) +#define BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP 0x00000020 +#define BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(v) \ + (((v) << 5) & BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP) +#define BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE 0x00000010 +#define BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(v) \ + (((v) << 4) & BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE) +#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008 +#define BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(v) \ + (((v) << 3) & BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE) +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BF_PXP_CTRL_NEXT_IRQ_ENABLE(v) \ + (((v) << 2) & BM_PXP_CTRL_NEXT_IRQ_ENABLE) +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BF_PXP_CTRL_IRQ_ENABLE(v) \ + (((v) << 1) & BM_PXP_CTRL_IRQ_ENABLE) +#define BM_PXP_CTRL_ENABLE 0x00000001 +#define BF_PXP_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_CTRL_ENABLE) + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_AXI_ERROR_ID_1 12 +#define BM_PXP_STAT_AXI_ERROR_ID_1 0x0000F000 +#define BF_PXP_STAT_AXI_ERROR_ID_1(v) \ + (((v) << 12) & BM_PXP_STAT_AXI_ERROR_ID_1) +#define BM_PXP_STAT_RSVD2 0x00000800 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 11) & BM_PXP_STAT_RSVD2) +#define BM_PXP_STAT_AXI_READ_ERROR_1 0x00000400 +#define BF_PXP_STAT_AXI_READ_ERROR_1(v) \ + (((v) << 10) & BM_PXP_STAT_AXI_READ_ERROR_1) +#define BM_PXP_STAT_AXI_WRITE_ERROR_1 0x00000200 +#define BF_PXP_STAT_AXI_WRITE_ERROR_1(v) \ + (((v) << 9) & BM_PXP_STAT_AXI_WRITE_ERROR_1) +#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100 +#define BF_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(v) \ + (((v) << 8) & BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ) +#define BP_PXP_STAT_AXI_ERROR_ID_0 4 +#define BM_PXP_STAT_AXI_ERROR_ID_0 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID_0(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID_0) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BF_PXP_STAT_NEXT_IRQ(v) \ + (((v) << 3) & BM_PXP_STAT_NEXT_IRQ) +#define BM_PXP_STAT_AXI_READ_ERROR_0 0x00000004 +#define BF_PXP_STAT_AXI_READ_ERROR_0(v) \ + (((v) << 2) & BM_PXP_STAT_AXI_READ_ERROR_0) +#define BM_PXP_STAT_AXI_WRITE_ERROR_0 0x00000002 +#define BF_PXP_STAT_AXI_WRITE_ERROR_0(v) \ + (((v) << 1) & BM_PXP_STAT_AXI_WRITE_ERROR_0) +#define BM_PXP_STAT_IRQ0 0x00000001 +#define BF_PXP_STAT_IRQ0(v) \ + (((v) << 0) & BM_PXP_STAT_IRQ0) + +#define HW_PXP_OUT_CTRL (0x00000020) +#define HW_PXP_OUT_CTRL_SET (0x00000024) +#define HW_PXP_OUT_CTRL_CLR (0x00000028) +#define HW_PXP_OUT_CTRL_TOG (0x0000002c) + +#define BP_PXP_OUT_CTRL_ALPHA 24 +#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000 +#define BF_PXP_OUT_CTRL_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA) +#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000 +#define BF_PXP_OUT_CTRL_ALPHA_OUTPUT(v) \ + (((v) << 23) & BM_PXP_OUT_CTRL_ALPHA_OUTPUT) +#define BP_PXP_OUT_CTRL_RSVD1 10 +#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00 +#define BF_PXP_OUT_CTRL_RSVD1(v) \ + (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1) +#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8 +#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300 +#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_OUT_CTRL_RSVD0 5 +#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0 +#define BF_PXP_OUT_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0) +#define BP_PXP_OUT_CTRL_FORMAT 0 +#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F +#define BF_PXP_OUT_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) +#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B + +#define HW_PXP_OUT_BUF (0x00000030) + +#define BP_PXP_OUT_BUF_ADDR 0 +#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF_ADDR(v) (v) + +#define HW_PXP_OUT_BUF2 (0x00000040) + +#define BP_PXP_OUT_BUF2_ADDR 0 +#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF2_ADDR(v) (v) + +#define HW_PXP_OUT_PITCH (0x00000050) + +#define BP_PXP_OUT_PITCH_RSVD 16 +#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_OUT_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_OUT_PITCH_RSVD) +#define BP_PXP_OUT_PITCH_PITCH 0 +#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF +#define BF_PXP_OUT_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_OUT_PITCH_PITCH) + +#define HW_PXP_OUT_LRC (0x00000060) + +#define BP_PXP_OUT_LRC_RSVD1 30 +#define BM_PXP_OUT_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_LRC_RSVD1) +#define BP_PXP_OUT_LRC_X 16 +#define BM_PXP_OUT_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_LRC_X) +#define BP_PXP_OUT_LRC_RSVD0 14 +#define BM_PXP_OUT_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_LRC_RSVD0) +#define BP_PXP_OUT_LRC_Y 0 +#define BM_PXP_OUT_LRC_Y 0x00003FFF +#define BF_PXP_OUT_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_LRC_Y) + +#define HW_PXP_OUT_PS_ULC (0x00000070) + +#define BP_PXP_OUT_PS_ULC_RSVD1 30 +#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1) +#define BP_PXP_OUT_PS_ULC_X 16 +#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_ULC_X) +#define BP_PXP_OUT_PS_ULC_RSVD0 14 +#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0) +#define BP_PXP_OUT_PS_ULC_Y 0 +#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_PS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_ULC_Y) + +#define HW_PXP_OUT_PS_LRC (0x00000080) + +#define BP_PXP_OUT_PS_LRC_RSVD1 30 +#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1) +#define BP_PXP_OUT_PS_LRC_X 16 +#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_LRC_X) +#define BP_PXP_OUT_PS_LRC_RSVD0 14 +#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0) +#define BP_PXP_OUT_PS_LRC_Y 0 +#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_PS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_LRC_Y) + +#define HW_PXP_OUT_AS_ULC (0x00000090) + +#define BP_PXP_OUT_AS_ULC_RSVD1 30 +#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1) +#define BP_PXP_OUT_AS_ULC_X 16 +#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_ULC_X) +#define BP_PXP_OUT_AS_ULC_RSVD0 14 +#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0) +#define BP_PXP_OUT_AS_ULC_Y 0 +#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_AS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_ULC_Y) + +#define HW_PXP_OUT_AS_LRC (0x000000a0) + +#define BP_PXP_OUT_AS_LRC_RSVD1 30 +#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1) +#define BP_PXP_OUT_AS_LRC_X 16 +#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_LRC_X) +#define BP_PXP_OUT_AS_LRC_RSVD0 14 +#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0) +#define BP_PXP_OUT_AS_LRC_Y 0 +#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_AS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_LRC_Y) + +#define HW_PXP_PS_CTRL (0x000000b0) +#define HW_PXP_PS_CTRL_SET (0x000000b4) +#define HW_PXP_PS_CTRL_CLR (0x000000b8) +#define HW_PXP_PS_CTRL_TOG (0x000000bc) + +#define BP_PXP_PS_CTRL_RSVD1 12 +#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000 +#define BF_PXP_PS_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_CTRL_RSVD1) +#define BP_PXP_PS_CTRL_DECX 10 +#define BM_PXP_PS_CTRL_DECX 0x00000C00 +#define BF_PXP_PS_CTRL_DECX(v) \ + (((v) << 10) & BM_PXP_PS_CTRL_DECX) +#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECX__DECX2 0x1 +#define BV_PXP_PS_CTRL_DECX__DECX4 0x2 +#define BV_PXP_PS_CTRL_DECX__DECX8 0x3 +#define BP_PXP_PS_CTRL_DECY 8 +#define BM_PXP_PS_CTRL_DECY 0x00000300 +#define BF_PXP_PS_CTRL_DECY(v) \ + (((v) << 8) & BM_PXP_PS_CTRL_DECY) +#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECY__DECY2 0x1 +#define BV_PXP_PS_CTRL_DECY__DECY4 0x2 +#define BV_PXP_PS_CTRL_DECY__DECY8 0x3 +#define BM_PXP_PS_CTRL_RSVD0 0x00000080 +#define BF_PXP_PS_CTRL_RSVD0(v) \ + (((v) << 7) & BM_PXP_PS_CTRL_RSVD0) +#define BM_PXP_PS_CTRL_WB_SWAP 0x00000040 +#define BF_PXP_PS_CTRL_WB_SWAP(v) \ + (((v) << 6) & BM_PXP_PS_CTRL_WB_SWAP) +#define BP_PXP_PS_CTRL_FORMAT 0 +#define BM_PXP_PS_CTRL_FORMAT 0x0000003F +#define BF_PXP_PS_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) +#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B +#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E +#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F +#define BV_PXP_PS_CTRL_FORMAT__RGBA888 0x24 + +#define HW_PXP_PS_BUF (0x000000c0) + +#define BP_PXP_PS_BUF_ADDR 0 +#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_BUF_ADDR(v) (v) + +#define HW_PXP_PS_UBUF (0x000000d0) + +#define BP_PXP_PS_UBUF_ADDR 0 +#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_UBUF_ADDR(v) (v) + +#define HW_PXP_PS_VBUF (0x000000e0) + +#define BP_PXP_PS_VBUF_ADDR 0 +#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_VBUF_ADDR(v) (v) + +#define HW_PXP_PS_PITCH (0x000000f0) + +#define BP_PXP_PS_PITCH_RSVD 16 +#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_PS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_PS_PITCH_RSVD) +#define BP_PXP_PS_PITCH_PITCH 0 +#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_PS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_PS_PITCH_PITCH) + +#define HW_PXP_PS_BACKGROUND_0 (0x00000100) + +#define BP_PXP_PS_BACKGROUND_0_RSVD 24 +#define BM_PXP_PS_BACKGROUND_0_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_0_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_0_RSVD) +#define BP_PXP_PS_BACKGROUND_0_COLOR 0 +#define BM_PXP_PS_BACKGROUND_0_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_0_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_0_COLOR) + +#define HW_PXP_PS_SCALE (0x00000110) + +#define BM_PXP_PS_SCALE_RSVD2 0x80000000 +#define BF_PXP_PS_SCALE_RSVD2(v) \ + (((v) << 31) & BM_PXP_PS_SCALE_RSVD2) +#define BP_PXP_PS_SCALE_YSCALE 16 +#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_PS_SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) +#define BM_PXP_PS_SCALE_RSVD1 0x00008000 +#define BF_PXP_PS_SCALE_RSVD1(v) \ + (((v) << 15) & BM_PXP_PS_SCALE_RSVD1) +#define BP_PXP_PS_SCALE_XSCALE 0 +#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF +#define BF_PXP_PS_SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) + +#define BP_PXP_PS_SCALE_OFFSET 12 + +#define HW_PXP_PS_OFFSET (0x00000120) + +#define BP_PXP_PS_OFFSET_RSVD2 28 +#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000 +#define BF_PXP_PS_OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2) +#define BP_PXP_PS_OFFSET_YOFFSET 16 +#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_PS_OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET) +#define BP_PXP_PS_OFFSET_RSVD1 12 +#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_PS_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1) +#define BP_PXP_PS_OFFSET_XOFFSET 0 +#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_PS_OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET) + +#define HW_PXP_PS_CLRKEYLOW_0 (0x00000130) + +#define BP_PXP_PS_CLRKEYLOW_0_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_0_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_0_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_0_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_0_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_0_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH_0 (0x00000140) + +#define BP_PXP_PS_CLRKEYHIGH_0_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_0_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_0_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_0_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_0_PIXEL) + +#define HW_PXP_AS_CTRL (0x00000150) + +#define BP_PXP_AS_CTRL_RSVD1 22 +#define BM_PXP_AS_CTRL_RSVD1 0xFFC00000 +#define BF_PXP_AS_CTRL_RSVD1(v) \ + (((v) << 22) & BM_PXP_AS_CTRL_RSVD1) +#define BM_PXP_AS_CTRL_ALPHA1_INVERT 0x00200000 +#define BF_PXP_AS_CTRL_ALPHA1_INVERT(v) \ + (((v) << 21) & BM_PXP_AS_CTRL_ALPHA1_INVERT) +#define BM_PXP_AS_CTRL_ALPHA0_INVERT 0x00100000 +#define BF_PXP_AS_CTRL_ALPHA0_INVERT(v) \ + (((v) << 20) & BM_PXP_AS_CTRL_ALPHA0_INVERT) +#define BP_PXP_AS_CTRL_ROP 16 +#define BM_PXP_AS_CTRL_ROP 0x000F0000 +#define BF_PXP_AS_CTRL_ROP(v) \ + (((v) << 16) & BM_PXP_AS_CTRL_ROP) +#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0 +#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 +#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2 +#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3 +#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4 +#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5 +#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6 +#define BV_PXP_AS_CTRL_ROP__NOT 0x7 +#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8 +#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9 +#define BV_PXP_AS_CTRL_ROP__XORAS 0xA +#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB +#define BP_PXP_AS_CTRL_ALPHA 8 +#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00 +#define BF_PXP_AS_CTRL_ALPHA(v) \ + (((v) << 8) & BM_PXP_AS_CTRL_ALPHA) +#define BP_PXP_AS_CTRL_FORMAT 4 +#define BM_PXP_AS_CTRL_FORMAT 0x000000F0 +#define BF_PXP_AS_CTRL_FORMAT(v) \ + (((v) << 4) & BM_PXP_AS_CTRL_FORMAT) +#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_AS_CTRL_FORMAT__RGBA8888 0x1 +#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_AS_CTRL_FORMAT__RGBA5551 0xA +#define BV_PXP_AS_CTRL_FORMAT__RGBA4444 0xB +#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE +#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008 +#define BF_PXP_AS_CTRL_ENABLE_COLORKEY(v) \ + (((v) << 3) & BM_PXP_AS_CTRL_ENABLE_COLORKEY) +#define BP_PXP_AS_CTRL_ALPHA_CTRL 1 +#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006 +#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \ + (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL) +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3 +#define BM_PXP_AS_CTRL_RSVD0 0x00000001 +#define BF_PXP_AS_CTRL_RSVD0(v) \ + (((v) << 0) & BM_PXP_AS_CTRL_RSVD0) + +#define HW_PXP_AS_BUF (0x00000160) + +#define BP_PXP_AS_BUF_ADDR 0 +#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_AS_BUF_ADDR(v) (v) + +#define HW_PXP_AS_PITCH (0x00000170) + +#define BP_PXP_AS_PITCH_RSVD 16 +#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_AS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_AS_PITCH_RSVD) +#define BP_PXP_AS_PITCH_PITCH 0 +#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_AS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_AS_PITCH_PITCH) + +#define HW_PXP_AS_CLRKEYLOW_0 (0x00000180) + +#define BP_PXP_AS_CLRKEYLOW_0_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_0_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_0_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_0_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_0_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_0_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH_0 (0x00000190) + +#define BP_PXP_AS_CLRKEYHIGH_0_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_0_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_0_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_0_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_0_PIXEL) + +#define HW_PXP_CSC1_COEF0 (0x000001a0) + +#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000 +#define BF_PXP_CSC1_COEF0_YCBCR_MODE(v) \ + (((v) << 31) & BM_PXP_CSC1_COEF0_YCBCR_MODE) +#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000 +#define BF_PXP_CSC1_COEF0_BYPASS(v) \ + (((v) << 30) & BM_PXP_CSC1_COEF0_BYPASS) +#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000 +#define BF_PXP_CSC1_COEF0_RSVD1(v) \ + (((v) << 29) & BM_PXP_CSC1_COEF0_RSVD1) +#define BP_PXP_CSC1_COEF0_C0 18 +#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000 +#define BF_PXP_CSC1_COEF0_C0(v) \ + (((v) << 18) & BM_PXP_CSC1_COEF0_C0) +#define BP_PXP_CSC1_COEF0_UV_OFFSET 9 +#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET) +#define BP_PXP_CSC1_COEF0_Y_OFFSET 0 +#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET) + +#define HW_PXP_CSC1_COEF1 (0x000001b0) + +#define BP_PXP_CSC1_COEF1_RSVD1 27 +#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1) +#define BP_PXP_CSC1_COEF1_C1 16 +#define BM_PXP_CSC1_COEF1_C1 0x07FF0000 +#define BF_PXP_CSC1_COEF1_C1(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF1_C1) +#define BP_PXP_CSC1_COEF1_RSVD0 11 +#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0) +#define BP_PXP_CSC1_COEF1_C4 0 +#define BM_PXP_CSC1_COEF1_C4 0x000007FF +#define BF_PXP_CSC1_COEF1_C4(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF1_C4) + +#define HW_PXP_CSC1_COEF2 (0x000001c0) + +#define BP_PXP_CSC1_COEF2_RSVD1 27 +#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1) +#define BP_PXP_CSC1_COEF2_C2 16 +#define BM_PXP_CSC1_COEF2_C2 0x07FF0000 +#define BF_PXP_CSC1_COEF2_C2(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF2_C2) +#define BP_PXP_CSC1_COEF2_RSVD0 11 +#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0) +#define BP_PXP_CSC1_COEF2_C3 0 +#define BM_PXP_CSC1_COEF2_C3 0x000007FF +#define BF_PXP_CSC1_COEF2_C3(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF2_C3) + +#define HW_PXP_CSC2_CTRL (0x000001d0) + +#define BP_PXP_CSC2_CTRL_RSVD 3 +#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8 +#define BF_PXP_CSC2_CTRL_RSVD(v) \ + (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD) +#define BP_PXP_CSC2_CTRL_CSC_MODE 1 +#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006 +#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \ + (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE) +#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0 +#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3 +#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001 +#define BF_PXP_CSC2_CTRL_BYPASS(v) \ + (((v) << 0) & BM_PXP_CSC2_CTRL_BYPASS) + +#define HW_PXP_CSC2_COEF0 (0x000001e0) + +#define BP_PXP_CSC2_COEF0_RSVD1 27 +#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF0_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1) +#define BP_PXP_CSC2_COEF0_A2 16 +#define BM_PXP_CSC2_COEF0_A2 0x07FF0000 +#define BF_PXP_CSC2_COEF0_A2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF0_A2) +#define BP_PXP_CSC2_COEF0_RSVD0 11 +#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF0_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0) +#define BP_PXP_CSC2_COEF0_A1 0 +#define BM_PXP_CSC2_COEF0_A1 0x000007FF +#define BF_PXP_CSC2_COEF0_A1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF0_A1) + +#define HW_PXP_CSC2_COEF1 (0x000001f0) + +#define BP_PXP_CSC2_COEF1_RSVD1 27 +#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1) +#define BP_PXP_CSC2_COEF1_B1 16 +#define BM_PXP_CSC2_COEF1_B1 0x07FF0000 +#define BF_PXP_CSC2_COEF1_B1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF1_B1) +#define BP_PXP_CSC2_COEF1_RSVD0 11 +#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0) +#define BP_PXP_CSC2_COEF1_A3 0 +#define BM_PXP_CSC2_COEF1_A3 0x000007FF +#define BF_PXP_CSC2_COEF1_A3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF1_A3) + +#define HW_PXP_CSC2_COEF2 (0x00000200) + +#define BP_PXP_CSC2_COEF2_RSVD1 27 +#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1) +#define BP_PXP_CSC2_COEF2_B3 16 +#define BM_PXP_CSC2_COEF2_B3 0x07FF0000 +#define BF_PXP_CSC2_COEF2_B3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF2_B3) +#define BP_PXP_CSC2_COEF2_RSVD0 11 +#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0) +#define BP_PXP_CSC2_COEF2_B2 0 +#define BM_PXP_CSC2_COEF2_B2 0x000007FF +#define BF_PXP_CSC2_COEF2_B2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF2_B2) + +#define HW_PXP_CSC2_COEF3 (0x00000210) + +#define BP_PXP_CSC2_COEF3_RSVD1 27 +#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF3_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1) +#define BP_PXP_CSC2_COEF3_C2 16 +#define BM_PXP_CSC2_COEF3_C2 0x07FF0000 +#define BF_PXP_CSC2_COEF3_C2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF3_C2) +#define BP_PXP_CSC2_COEF3_RSVD0 11 +#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF3_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0) +#define BP_PXP_CSC2_COEF3_C1 0 +#define BM_PXP_CSC2_COEF3_C1 0x000007FF +#define BF_PXP_CSC2_COEF3_C1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF3_C1) + +#define HW_PXP_CSC2_COEF4 (0x00000220) + +#define BP_PXP_CSC2_COEF4_RSVD1 25 +#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF4_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1) +#define BP_PXP_CSC2_COEF4_D1 16 +#define BM_PXP_CSC2_COEF4_D1 0x01FF0000 +#define BF_PXP_CSC2_COEF4_D1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF4_D1) +#define BP_PXP_CSC2_COEF4_RSVD0 11 +#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF4_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0) +#define BP_PXP_CSC2_COEF4_C3 0 +#define BM_PXP_CSC2_COEF4_C3 0x000007FF +#define BF_PXP_CSC2_COEF4_C3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF4_C3) + +#define HW_PXP_CSC2_COEF5 (0x00000230) + +#define BP_PXP_CSC2_COEF5_RSVD1 25 +#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF5_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1) +#define BP_PXP_CSC2_COEF5_D3 16 +#define BM_PXP_CSC2_COEF5_D3 0x01FF0000 +#define BF_PXP_CSC2_COEF5_D3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF5_D3) +#define BP_PXP_CSC2_COEF5_RSVD0 9 +#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00 +#define BF_PXP_CSC2_COEF5_RSVD0(v) \ + (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0) +#define BP_PXP_CSC2_COEF5_D2 0 +#define BM_PXP_CSC2_COEF5_D2 0x000001FF +#define BF_PXP_CSC2_COEF5_D2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF5_D2) + +#define HW_PXP_LUT_CTRL (0x00000240) + +#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 +#define BF_PXP_LUT_CTRL_BYPASS(v) \ + (((v) << 31) & BM_PXP_LUT_CTRL_BYPASS) +#define BP_PXP_LUT_CTRL_RSVD3 26 +#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000 +#define BF_PXP_LUT_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3) +#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24 +#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000 +#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \ + (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE) +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3 +#define BP_PXP_LUT_CTRL_RSVD2 18 +#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000 +#define BF_PXP_LUT_CTRL_RSVD2(v) \ + (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2) +#define BP_PXP_LUT_CTRL_OUT_MODE 16 +#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000 +#define BF_PXP_LUT_CTRL_OUT_MODE(v) \ + (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE) +#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0 +#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3 +#define BP_PXP_LUT_CTRL_RSVD1 11 +#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800 +#define BF_PXP_LUT_CTRL_RSVD1(v) \ + (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1) +#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400 +#define BF_PXP_LUT_CTRL_SEL_8KB(v) \ + (((v) << 10) & BM_PXP_LUT_CTRL_SEL_8KB) +#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200 +#define BF_PXP_LUT_CTRL_LRU_UPD(v) \ + (((v) << 9) & BM_PXP_LUT_CTRL_LRU_UPD) +#define BM_PXP_LUT_CTRL_INVALID 0x00000100 +#define BF_PXP_LUT_CTRL_INVALID(v) \ + (((v) << 8) & BM_PXP_LUT_CTRL_INVALID) +#define BP_PXP_LUT_CTRL_RSVD0 1 +#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE +#define BF_PXP_LUT_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0) +#define BM_PXP_LUT_CTRL_DMA_START 0x00000001 +#define BF_PXP_LUT_CTRL_DMA_START(v) \ + (((v) << 0) & BM_PXP_LUT_CTRL_DMA_START) + +#define HW_PXP_LUT_ADDR (0x00000250) + +#define BM_PXP_LUT_ADDR_RSVD2 0x80000000 +#define BF_PXP_LUT_ADDR_RSVD2(v) \ + (((v) << 31) & BM_PXP_LUT_ADDR_RSVD2) +#define BP_PXP_LUT_ADDR_NUM_BYTES 16 +#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000 +#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES) +#define BP_PXP_LUT_ADDR_RSVD1 14 +#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000 +#define BF_PXP_LUT_ADDR_RSVD1(v) \ + (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1) +#define BP_PXP_LUT_ADDR_ADDR 0 +#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF +#define BF_PXP_LUT_ADDR_ADDR(v) \ + (((v) << 0) & BM_PXP_LUT_ADDR_ADDR) + +#define HW_PXP_LUT_DATA (0x00000260) + +#define BP_PXP_LUT_DATA_DATA 0 +#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF +#define BF_PXP_LUT_DATA_DATA(v) (v) + +#define HW_PXP_LUT_EXTMEM (0x00000270) + +#define BP_PXP_LUT_EXTMEM_ADDR 0 +#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF +#define BF_PXP_LUT_EXTMEM_ADDR(v) (v) + +#define HW_PXP_CFA (0x00000280) + +#define BP_PXP_CFA_DATA 0 +#define BM_PXP_CFA_DATA 0xFFFFFFFF +#define BF_PXP_CFA_DATA(v) (v) + +#define HW_PXP_ALPHA_A_CTRL (0x00000290) + +#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 24 +#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 0xFF000000 +#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(v) \ + (((v) << 24) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 16 +#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 +#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(v) \ + (((v) << 16) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_A_CTRL_RSVD0 14 +#define BM_PXP_ALPHA_A_CTRL_RSVD0 0x0000C000 +#define BF_PXP_ALPHA_A_CTRL_RSVD0(v) \ + (((v) << 14) & BM_PXP_ALPHA_A_CTRL_RSVD0) +#define BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE 0x00002000 +#define BF_PXP_ALPHA_A_CTRL_S1_COLOR_MODE(v) \ + (((v) << 13) & BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE 0x00001000 +#define BF_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(v) \ + (((v) << 12) & BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 10 +#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 +#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ + (((v) << 10) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x0 +#define BP_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 8 +#define BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 0x00000300 +#define BF_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(v) \ + (((v) << 8) & BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_A_CTRL_RSVD1 0x00000080 +#define BF_PXP_ALPHA_A_CTRL_RSVD1(v) \ + (((v) << 7) & BM_PXP_ALPHA_A_CTRL_RSVD1) +#define BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE 0x00000040 +#define BF_PXP_ALPHA_A_CTRL_S0_COLOR_MODE(v) \ + (((v) << 6) & BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE 0x00000020 +#define BF_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(v) \ + (((v) << 5) & BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 3 +#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 +#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ + (((v) << 3) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 1 +#define BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 0x00000006 +#define BF_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(v) \ + (((v) << 1) & BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE 0x00000001 +#define BF_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE) +#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__1 0x1 + +#define HW_PXP_ALPHA_B_CTRL (0x000002a0) + +#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 24 +#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 0xFF000000 +#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(v) \ + (((v) << 24) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 16 +#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 +#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(v) \ + (((v) << 16) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_B_CTRL_RSVD0 14 +#define BM_PXP_ALPHA_B_CTRL_RSVD0 0x0000C000 +#define BF_PXP_ALPHA_B_CTRL_RSVD0(v) \ + (((v) << 14) & BM_PXP_ALPHA_B_CTRL_RSVD0) +#define BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE 0x00002000 +#define BF_PXP_ALPHA_B_CTRL_S1_COLOR_MODE(v) \ + (((v) << 13) & BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE 0x00001000 +#define BF_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE(v) \ + (((v) << 12) & BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 10 +#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 +#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ + (((v) << 10) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 8 +#define BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 0x00000300 +#define BF_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(v) \ + (((v) << 8) & BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_B_CTRL_RSVD1 0x00000080 +#define BF_PXP_ALPHA_B_CTRL_RSVD1(v) \ + (((v) << 7) & BM_PXP_ALPHA_B_CTRL_RSVD1) +#define BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE 0x00000040 +#define BF_PXP_ALPHA_B_CTRL_S0_COLOR_MODE(v) \ + (((v) << 6) & BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE 0x00000020 +#define BF_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE(v) \ + (((v) << 5) & BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 3 +#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 +#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ + (((v) << 3) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 1 +#define BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 0x00000006 +#define BF_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(v) \ + (((v) << 1) & BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE 0x00000001 +#define BF_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE) +#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__1 0x1 + +#define HW_PXP_ALPHA_B_CTRL_1 (0x000002b0) + +#define BP_PXP_ALPHA_B_CTRL_1_RSVD0 8 +#define BM_PXP_ALPHA_B_CTRL_1_RSVD0 0xFFFFFF00 +#define BF_PXP_ALPHA_B_CTRL_1_RSVD0(v) \ + (((v) << 8) & BM_PXP_ALPHA_B_CTRL_1_RSVD0) +#define BP_PXP_ALPHA_B_CTRL_1_ROP 4 +#define BM_PXP_ALPHA_B_CTRL_1_ROP 0x000000F0 +#define BF_PXP_ALPHA_B_CTRL_1_ROP(v) \ + (((v) << 4) & BM_PXP_ALPHA_B_CTRL_1_ROP) +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKAS 0x0 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKNOTAS 0x1 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKASNOT 0x2 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEAS 0x3 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGENOTAS 0x4 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEASNOT 0x5 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTCOPYAS 0x6 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOT 0x7 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMASKAS 0x8 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMERGEAS 0x9 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__XORAS 0xA +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTXORAS 0xB +#define BP_PXP_ALPHA_B_CTRL_1_RSVD1 2 +#define BM_PXP_ALPHA_B_CTRL_1_RSVD1 0x0000000C +#define BF_PXP_ALPHA_B_CTRL_1_RSVD1(v) \ + (((v) << 2) & BM_PXP_ALPHA_B_CTRL_1_RSVD1) +#define BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE 0x00000002 +#define BF_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(v) \ + (((v) << 1) & BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE) +#define BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE 0x00000001 +#define BF_PXP_ALPHA_B_CTRL_1_ROP_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE) + +#define HW_PXP_PS_BACKGROUND_1 (0x000002c0) + +#define BP_PXP_PS_BACKGROUND_1_RSVD 24 +#define BM_PXP_PS_BACKGROUND_1_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_1_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_1_RSVD) +#define BP_PXP_PS_BACKGROUND_1_COLOR 0 +#define BM_PXP_PS_BACKGROUND_1_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_1_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_1_COLOR) + +#define HW_PXP_PS_CLRKEYLOW_1 (0x000002d0) + +#define BP_PXP_PS_CLRKEYLOW_1_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_1_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_1_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_1_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_1_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_1_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH_1 (0x000002e0) + +#define BP_PXP_PS_CLRKEYHIGH_1_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_1_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_1_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_1_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_1_PIXEL) + +#define HW_PXP_AS_CLRKEYLOW_1 (0x000002f0) + +#define BP_PXP_AS_CLRKEYLOW_1_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_1_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_1_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_1_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_1_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_1_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH_1 (0x00000300) + +#define BP_PXP_AS_CLRKEYHIGH_1_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_1_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_1_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_1_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_1_PIXEL) + +#define HW_PXP_CTRL2 (0x00000310) +#define HW_PXP_CTRL2_SET (0x00000314) +#define HW_PXP_CTRL2_CLR (0x00000318) +#define HW_PXP_CTRL2_TOG (0x0000031c) + +#define BP_PXP_CTRL2_RSVD3 28 +#define BM_PXP_CTRL2_RSVD3 0xF0000000 +#define BF_PXP_CTRL2_RSVD3(v) \ + (((v) << 28) & BM_PXP_CTRL2_RSVD3) +#define BM_PXP_CTRL2_ENABLE_ROTATE1 0x08000000 +#define BF_PXP_CTRL2_ENABLE_ROTATE1(v) \ + (((v) << 27) & BM_PXP_CTRL2_ENABLE_ROTATE1) +#define BM_PXP_CTRL2_ENABLE_ROTATE0 0x04000000 +#define BF_PXP_CTRL2_ENABLE_ROTATE0(v) \ + (((v) << 26) & BM_PXP_CTRL2_ENABLE_ROTATE0) +#define BM_PXP_CTRL2_ENABLE_LUT 0x02000000 +#define BF_PXP_CTRL2_ENABLE_LUT(v) \ + (((v) << 25) & BM_PXP_CTRL2_ENABLE_LUT) +#define BM_PXP_CTRL2_ENABLE_CSC2 0x01000000 +#define BF_PXP_CTRL2_ENABLE_CSC2(v) \ + (((v) << 24) & BM_PXP_CTRL2_ENABLE_CSC2) +#define BM_PXP_CTRL2_BLOCK_SIZE 0x00800000 +#define BF_PXP_CTRL2_BLOCK_SIZE(v) \ + (((v) << 23) & BM_PXP_CTRL2_BLOCK_SIZE) +#define BV_PXP_CTRL2_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL2_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL2_RSVD2 0x00400000 +#define BF_PXP_CTRL2_RSVD2(v) \ + (((v) << 22) & BM_PXP_CTRL2_RSVD2) +#define BM_PXP_CTRL2_ENABLE_ALPHA_B 0x00200000 +#define BF_PXP_CTRL2_ENABLE_ALPHA_B(v) \ + (((v) << 21) & BM_PXP_CTRL2_ENABLE_ALPHA_B) +#define BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE 0x00100000 +#define BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE(v) \ + (((v) << 20) & BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE) +#define BM_PXP_CTRL2_ENABLE_WFE_B 0x00080000 +#define BF_PXP_CTRL2_ENABLE_WFE_B(v) \ + (((v) << 19) & BM_PXP_CTRL2_ENABLE_WFE_B) +#define BM_PXP_CTRL2_ENABLE_WFE_A 0x00040000 +#define BF_PXP_CTRL2_ENABLE_WFE_A(v) \ + (((v) << 18) & BM_PXP_CTRL2_ENABLE_WFE_A) +#define BM_PXP_CTRL2_ENABLE_DITHER 0x00020000 +#define BF_PXP_CTRL2_ENABLE_DITHER(v) \ + (((v) << 17) & BM_PXP_CTRL2_ENABLE_DITHER) +#define BM_PXP_CTRL2_RSVD1 0x00010000 +#define BF_PXP_CTRL2_RSVD1(v) \ + (((v) << 16) & BM_PXP_CTRL2_RSVD1) +#define BM_PXP_CTRL2_VFLIP1 0x00008000 +#define BF_PXP_CTRL2_VFLIP1(v) \ + (((v) << 15) & BM_PXP_CTRL2_VFLIP1) +#define BM_PXP_CTRL2_HFLIP1 0x00004000 +#define BF_PXP_CTRL2_HFLIP1(v) \ + (((v) << 14) & BM_PXP_CTRL2_HFLIP1) +#define BP_PXP_CTRL2_ROTATE1 12 +#define BM_PXP_CTRL2_ROTATE1 0x00003000 +#define BF_PXP_CTRL2_ROTATE1(v) \ + (((v) << 12) & BM_PXP_CTRL2_ROTATE1) +#define BV_PXP_CTRL2_ROTATE1__ROT_0 0x0 +#define BV_PXP_CTRL2_ROTATE1__ROT_90 0x1 +#define BV_PXP_CTRL2_ROTATE1__ROT_180 0x2 +#define BV_PXP_CTRL2_ROTATE1__ROT_270 0x3 +#define BM_PXP_CTRL2_VFLIP0 0x00000800 +#define BF_PXP_CTRL2_VFLIP0(v) \ + (((v) << 11) & BM_PXP_CTRL2_VFLIP0) +#define BM_PXP_CTRL2_HFLIP0 0x00000400 +#define BF_PXP_CTRL2_HFLIP0(v) \ + (((v) << 10) & BM_PXP_CTRL2_HFLIP0) +#define BP_PXP_CTRL2_ROTATE0 8 +#define BM_PXP_CTRL2_ROTATE0 0x00000300 +#define BF_PXP_CTRL2_ROTATE0(v) \ + (((v) << 8) & BM_PXP_CTRL2_ROTATE0) +#define BV_PXP_CTRL2_ROTATE0__ROT_0 0x0 +#define BV_PXP_CTRL2_ROTATE0__ROT_90 0x1 +#define BV_PXP_CTRL2_ROTATE0__ROT_180 0x2 +#define BV_PXP_CTRL2_ROTATE0__ROT_270 0x3 +#define BP_PXP_CTRL2_RSVD0 1 +#define BM_PXP_CTRL2_RSVD0 0x000000FE +#define BF_PXP_CTRL2_RSVD0(v) \ + (((v) << 1) & BM_PXP_CTRL2_RSVD0) +#define BM_PXP_CTRL2_ENABLE 0x00000001 +#define BF_PXP_CTRL2_ENABLE(v) \ + (((v) << 0) & BM_PXP_CTRL2_ENABLE) + +#define HW_PXP_POWER_REG0 (0x00000320) + +#define BP_PXP_POWER_REG0_CTRL 12 +#define BM_PXP_POWER_REG0_CTRL 0xFFFFF000 +#define BF_PXP_POWER_REG0_CTRL(v) \ + (((v) << 12) & BM_PXP_POWER_REG0_CTRL) +#define BP_PXP_POWER_REG0_ROT0_MEM_LP_STATE 9 +#define BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_REG0_ROT0_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE) +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 6 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 0x000001C0 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(v) \ + (((v) << 6) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 3 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 0x00000038 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(v) \ + (((v) << 3) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0x00000007 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(v) \ + (((v) << 0) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__SD 0x4 + +#define HW_PXP_POWER_REG1 (0x00000330) + +#define BP_PXP_POWER_REG1_RSVD0 24 +#define BM_PXP_POWER_REG1_RSVD0 0xFF000000 +#define BF_PXP_POWER_REG1_RSVD0(v) \ + (((v) << 24) & BM_PXP_POWER_REG1_RSVD0) +#define BP_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 21 +#define BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 0x00E00000 +#define BF_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(v) \ + (((v) << 21) & BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 18 +#define BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 0x001C0000 +#define BF_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(v) \ + (((v) << 18) & BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 15 +#define BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 0x00038000 +#define BF_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(v) \ + (((v) << 15) & BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 12 +#define BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 0x00007000 +#define BF_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(v) \ + (((v) << 12) & BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 9 +#define BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 6 +#define BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 0x000001C0 +#define BF_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(v) \ + (((v) << 6) & BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 3 +#define BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 0x00000038 +#define BF_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(v) \ + (((v) << 3) & BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0 +#define BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0x00000007 +#define BF_PXP_POWER_REG1_ROT1_MEM_LP_STATE(v) \ + (((v) << 0) & BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__SD 0x4 + +#define HW_PXP_DATA_PATH_CTRL0 (0x00000340) +#define HW_PXP_DATA_PATH_CTRL0_SET (0x00000344) +#define HW_PXP_DATA_PATH_CTRL0_CLR (0x00000348) +#define HW_PXP_DATA_PATH_CTRL0_TOG (0x0000034c) + +#define BP_PXP_DATA_PATH_CTRL0_MUX15_SEL 30 +#define BM_PXP_DATA_PATH_CTRL0_MUX15_SEL 0xC0000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(v) \ + (((v) << 30) & BM_PXP_DATA_PATH_CTRL0_MUX15_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX14_SEL 28 +#define BM_PXP_DATA_PATH_CTRL0_MUX14_SEL 0x30000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(v) \ + (((v) << 28) & BM_PXP_DATA_PATH_CTRL0_MUX14_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX13_SEL 26 +#define BM_PXP_DATA_PATH_CTRL0_MUX13_SEL 0x0C000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(v) \ + (((v) << 26) & BM_PXP_DATA_PATH_CTRL0_MUX13_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX12_SEL 24 +#define BM_PXP_DATA_PATH_CTRL0_MUX12_SEL 0x03000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(v) \ + (((v) << 24) & BM_PXP_DATA_PATH_CTRL0_MUX12_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX11_SEL 22 +#define BM_PXP_DATA_PATH_CTRL0_MUX11_SEL 0x00C00000 +#define BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(v) \ + (((v) << 22) & BM_PXP_DATA_PATH_CTRL0_MUX11_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX10_SEL 20 +#define BM_PXP_DATA_PATH_CTRL0_MUX10_SEL 0x00300000 +#define BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(v) \ + (((v) << 20) & BM_PXP_DATA_PATH_CTRL0_MUX10_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX9_SEL 18 +#define BM_PXP_DATA_PATH_CTRL0_MUX9_SEL 0x000C0000 +#define BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(v) \ + (((v) << 18) & BM_PXP_DATA_PATH_CTRL0_MUX9_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX8_SEL 16 +#define BM_PXP_DATA_PATH_CTRL0_MUX8_SEL 0x00030000 +#define BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(v) \ + (((v) << 16) & BM_PXP_DATA_PATH_CTRL0_MUX8_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX7_SEL 14 +#define BM_PXP_DATA_PATH_CTRL0_MUX7_SEL 0x0000C000 +#define BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(v) \ + (((v) << 14) & BM_PXP_DATA_PATH_CTRL0_MUX7_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX6_SEL 12 +#define BM_PXP_DATA_PATH_CTRL0_MUX6_SEL 0x00003000 +#define BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(v) \ + (((v) << 12) & BM_PXP_DATA_PATH_CTRL0_MUX6_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX5_SEL 10 +#define BM_PXP_DATA_PATH_CTRL0_MUX5_SEL 0x00000C00 +#define BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(v) \ + (((v) << 10) & BM_PXP_DATA_PATH_CTRL0_MUX5_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX4_SEL 8 +#define BM_PXP_DATA_PATH_CTRL0_MUX4_SEL 0x00000300 +#define BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(v) \ + (((v) << 8) & BM_PXP_DATA_PATH_CTRL0_MUX4_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX3_SEL 6 +#define BM_PXP_DATA_PATH_CTRL0_MUX3_SEL 0x000000C0 +#define BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(v) \ + (((v) << 6) & BM_PXP_DATA_PATH_CTRL0_MUX3_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX2_SEL 4 +#define BM_PXP_DATA_PATH_CTRL0_MUX2_SEL 0x00000030 +#define BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(v) \ + (((v) << 4) & BM_PXP_DATA_PATH_CTRL0_MUX2_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX1_SEL 2 +#define BM_PXP_DATA_PATH_CTRL0_MUX1_SEL 0x0000000C +#define BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(v) \ + (((v) << 2) & BM_PXP_DATA_PATH_CTRL0_MUX1_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX0_SEL 0 +#define BM_PXP_DATA_PATH_CTRL0_MUX0_SEL 0x00000003 +#define BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(v) \ + (((v) << 0) & BM_PXP_DATA_PATH_CTRL0_MUX0_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__3 0x3 + +#define HW_PXP_DATA_PATH_CTRL1 (0x00000350) +#define HW_PXP_DATA_PATH_CTRL1_SET (0x00000354) +#define HW_PXP_DATA_PATH_CTRL1_CLR (0x00000358) +#define HW_PXP_DATA_PATH_CTRL1_TOG (0x0000035c) + +#define BP_PXP_DATA_PATH_CTRL1_RSVD0 4 +#define BM_PXP_DATA_PATH_CTRL1_RSVD0 0xFFFFFFF0 +#define BF_PXP_DATA_PATH_CTRL1_RSVD0(v) \ + (((v) << 4) & BM_PXP_DATA_PATH_CTRL1_RSVD0) +#define BP_PXP_DATA_PATH_CTRL1_MUX17_SEL 2 +#define BM_PXP_DATA_PATH_CTRL1_MUX17_SEL 0x0000000C +#define BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(v) \ + (((v) << 2) & BM_PXP_DATA_PATH_CTRL1_MUX17_SEL) +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL1_MUX16_SEL 0 +#define BM_PXP_DATA_PATH_CTRL1_MUX16_SEL 0x00000003 +#define BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(v) \ + (((v) << 0) & BM_PXP_DATA_PATH_CTRL1_MUX16_SEL) +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__3 0x3 + +#define HW_PXP_INIT_MEM_CTRL (0x00000360) +#define HW_PXP_INIT_MEM_CTRL_SET (0x00000364) +#define HW_PXP_INIT_MEM_CTRL_CLR (0x00000368) +#define HW_PXP_INIT_MEM_CTRL_TOG (0x0000036c) + +#define BM_PXP_INIT_MEM_CTRL_START 0x80000000 +#define BF_PXP_INIT_MEM_CTRL_START(v) \ + (((v) << 31) & BM_PXP_INIT_MEM_CTRL_START) +#define BP_PXP_INIT_MEM_CTRL_SELECT 27 +#define BM_PXP_INIT_MEM_CTRL_SELECT 0x78000000 +#define BF_PXP_INIT_MEM_CTRL_SELECT(v) \ + (((v) << 27) & BM_PXP_INIT_MEM_CTRL_SELECT) +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_LUT 0x0 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR0 0x1 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR1 0x2 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER1_LUT 0x3 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER2_LUT 0x4 +#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_A 0x5 +#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_B 0x6 +#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_A_FETCH 0x7 +#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_B_FETCH 0x8 +#define BV_PXP_INIT_MEM_CTRL_SELECT__RESERVED 0x15 +#define BP_PXP_INIT_MEM_CTRL_RSVD0 16 +#define BM_PXP_INIT_MEM_CTRL_RSVD0 0x07FF0000 +#define BF_PXP_INIT_MEM_CTRL_RSVD0(v) \ + (((v) << 16) & BM_PXP_INIT_MEM_CTRL_RSVD0) +#define BP_PXP_INIT_MEM_CTRL_ADDR 0 +#define BM_PXP_INIT_MEM_CTRL_ADDR 0x0000FFFF +#define BF_PXP_INIT_MEM_CTRL_ADDR(v) \ + (((v) << 0) & BM_PXP_INIT_MEM_CTRL_ADDR) + +#define HW_PXP_INIT_MEM_DATA (0x00000370) + +#define BP_PXP_INIT_MEM_DATA_DATA 0 +#define BM_PXP_INIT_MEM_DATA_DATA 0xFFFFFFFF +#define BF_PXP_INIT_MEM_DATA_DATA(v) (v) + +#define HW_PXP_INIT_MEM_DATA_HIGH (0x00000380) + +#define BP_PXP_INIT_MEM_DATA_HIGH_DATA 0 +#define BM_PXP_INIT_MEM_DATA_HIGH_DATA 0xFFFFFFFF +#define BF_PXP_INIT_MEM_DATA_HIGH_DATA(v) (v) + +#define HW_PXP_IRQ_MASK (0x00000390) +#define HW_PXP_IRQ_MASK_SET (0x00000394) +#define HW_PXP_IRQ_MASK_CLR (0x00000398) +#define HW_PXP_IRQ_MASK_TOG (0x0000039c) + +#define BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN 0x80000000 +#define BF_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN) +#define BP_PXP_IRQ_MASK_RSVD1 16 +#define BM_PXP_IRQ_MASK_RSVD1 0x7FFF0000 +#define BF_PXP_IRQ_MASK_RSVD1(v) \ + (((v) << 16) & BM_PXP_IRQ_MASK_RSVD1) +#define BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN 0x00008000 +#define BF_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(v) \ + (((v) << 15) & BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN 0x00004000 +#define BF_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN(v) \ + (((v) << 14) & BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN 0x00002000 +#define BF_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN(v) \ + (((v) << 13) & BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN 0x00001000 +#define BF_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(v) \ + (((v) << 12) & BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN 0x00000800 +#define BF_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(v) \ + (((v) << 11) & BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN 0x00000400 +#define BF_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(v) \ + (((v) << 10) & BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN 0x00000200 +#define BF_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN(v) \ + (((v) << 9) & BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN 0x00000100 +#define BF_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN(v) \ + (((v) << 8) & BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN 0x00000080 +#define BF_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN(v) \ + (((v) << 7) & BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN 0x00000040 +#define BF_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN(v) \ + (((v) << 6) & BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN 0x00000020 +#define BF_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN(v) \ + (((v) << 5) & BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN 0x00000010 +#define BF_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN(v) \ + (((v) << 4) & BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN 0x00000008 +#define BF_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN(v) \ + (((v) << 3) & BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN 0x00000004 +#define BF_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN(v) \ + (((v) << 2) & BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN 0x00000002 +#define BF_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN(v) \ + (((v) << 1) & BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN 0x00000001 +#define BF_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN(v) \ + (((v) << 0) & BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN) + +#define HW_PXP_IRQ (0x000003a0) +#define HW_PXP_IRQ_SET (0x000003a4) +#define HW_PXP_IRQ_CLR (0x000003a8) +#define HW_PXP_IRQ_TOG (0x000003ac) + +#define BM_PXP_IRQ_COMPRESS_DONE_IRQ 0x80000000 +#define BF_PXP_IRQ_COMPRESS_DONE_IRQ(v) \ + (((v) << 31) & BM_PXP_IRQ_COMPRESS_DONE_IRQ) +#define BP_PXP_IRQ_RSVD1 16 +#define BM_PXP_IRQ_RSVD1 0x7FFF0000 +#define BF_PXP_IRQ_RSVD1(v) \ + (((v) << 16) & BM_PXP_IRQ_RSVD1) +#define BM_PXP_IRQ_WFE_B_STORE_IRQ 0x00008000 +#define BF_PXP_IRQ_WFE_B_STORE_IRQ(v) \ + (((v) << 15) & BM_PXP_IRQ_WFE_B_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_STORE_IRQ 0x00004000 +#define BF_PXP_IRQ_WFE_A_STORE_IRQ(v) \ + (((v) << 14) & BM_PXP_IRQ_WFE_A_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_STORE_IRQ 0x00002000 +#define BF_PXP_IRQ_DITHER_STORE_IRQ(v) \ + (((v) << 13) & BM_PXP_IRQ_DITHER_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_STORE_IRQ 0x00001000 +#define BF_PXP_IRQ_FIRST_STORE_IRQ(v) \ + (((v) << 12) & BM_PXP_IRQ_FIRST_STORE_IRQ) +#define BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ 0x00000800 +#define BF_PXP_IRQ_WFE_B_CH1_STORE_IRQ(v) \ + (((v) << 11) & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ) +#define BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ 0x00000400 +#define BF_PXP_IRQ_WFE_B_CH0_STORE_IRQ(v) \ + (((v) << 10) & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ 0x00000200 +#define BF_PXP_IRQ_WFE_A_CH1_STORE_IRQ(v) \ + (((v) << 9) & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ 0x00000100 +#define BF_PXP_IRQ_WFE_A_CH0_STORE_IRQ(v) \ + (((v) << 8) & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH1_STORE_IRQ 0x00000080 +#define BF_PXP_IRQ_DITHER_CH1_STORE_IRQ(v) \ + (((v) << 7) & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH0_STORE_IRQ 0x00000040 +#define BF_PXP_IRQ_DITHER_CH0_STORE_IRQ(v) \ + (((v) << 6) & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ 0x00000020 +#define BF_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ(v) \ + (((v) << 5) & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ) +#define BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ 0x00000010 +#define BF_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ(v) \ + (((v) << 4) & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ) +#define BM_PXP_IRQ_FIRST_CH1_STORE_IRQ 0x00000008 +#define BF_PXP_IRQ_FIRST_CH1_STORE_IRQ(v) \ + (((v) << 3) & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_CH0_STORE_IRQ 0x00000004 +#define BF_PXP_IRQ_FIRST_CH0_STORE_IRQ(v) \ + (((v) << 2) & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ 0x00000002 +#define BF_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ(v) \ + (((v) << 1) & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ) +#define BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ 0x00000001 +#define BF_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ(v) \ + (((v) << 0) & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ) + +#define HW_PXP_NEXT (0x00000400) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BF_PXP_NEXT_RSVD(v) \ + (((v) << 1) & BM_PXP_NEXT_RSVD) +#define BM_PXP_NEXT_ENABLED 0x00000001 +#define BF_PXP_NEXT_ENABLED(v) \ + (((v) << 0) & BM_PXP_NEXT_ENABLED) + +#define HW_PXP_DEBUGCTRL (0x00000410) + +#define BP_PXP_DEBUGCTRL_RSVD 12 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD) +#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8 +#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00 +#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \ + (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT) +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14 + +#define HW_PXP_DEBUG (0x00000420) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x00000430) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) + +#define HW_PXP_INPUT_FETCH_CTRL_CH0 (0x00000450) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_SET (0x00000454) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_CLR (0x00000458) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_TOG (0x0000045c) + +#define BM_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD0 26 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD0 0x7C000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD0(v) \ + (((v) << 26) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD1 18 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES 16 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD2 14 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD2 0x0000C000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD2) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE 12 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE 0x00003000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD3 0x00000800 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD3(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD3) +#define BM_PXP_INPUT_FETCH_CTRL_CH0_VFLIP 0x00000400 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_VFLIP(v) \ + (((v) << 10) & BM_PXP_INPUT_FETCH_CTRL_CH0_VFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_VFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_VFLIP__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HFLIP 0x00000200 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HFLIP(v) \ + (((v) << 9) & BM_PXP_INPUT_FETCH_CTRL_CH0_HFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HFLIP__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD4 6 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD4 0x000001C0 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD4(v) \ + (((v) << 6) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD4) +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE 0x00000020 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_CTRL_CH0_CH_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_INPUT_FETCH_CTRL_CH1 (0x00000460) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_SET (0x00000464) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_CLR (0x00000468) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_TOG (0x0000046c) + +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD0 26 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD0 0xFC000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD0(v) \ + (((v) << 26) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD1 18 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES 16 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD2 14 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD2 0x0000C000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD2) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE 12 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE 0x00003000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD3 0x00000800 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD3(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD3) +#define BM_PXP_INPUT_FETCH_CTRL_CH1_VFLIP 0x00000400 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_VFLIP(v) \ + (((v) << 10) & BM_PXP_INPUT_FETCH_CTRL_CH1_VFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_VFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_VFLIP__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HFLIP 0x00000200 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HFLIP(v) \ + (((v) << 9) & BM_PXP_INPUT_FETCH_CTRL_CH1_HFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HFLIP__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD4 5 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD4 0x000001E0 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD4(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD4) +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_CTRL_CH1_CH_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_INPUT_FETCH_STATUS_CH0 (0x00000470) + +#define BP_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 16 +#define BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y) +#define BP_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0 +#define BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X) + +#define HW_PXP_INPUT_FETCH_STATUS_CH1 (0x00000480) + +#define BP_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 16 +#define BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y) +#define BP_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0 +#define BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 (0x00000490) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 (0x000004a0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 (0x000004b0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 (0x000004c0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_INPUT_FETCH_SIZE_CH0 (0x000004d0) + +#define BP_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT) +#define BP_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH) + +#define HW_PXP_INPUT_FETCH_SIZE_CH1 (0x000004e0) + +#define BP_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT) +#define BP_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH) + +#define HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0 (0x000004f0) + +#define BP_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0 +#define BM_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1 (0x00000500) + +#define BP_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0 +#define BM_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_INPUT_FETCH_PITCH (0x00000510) + +#define BP_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH 16 +#define BM_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH) +#define BP_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH 0 +#define BM_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH) + +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0 (0x00000520) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET (0x00000524) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR (0x00000528) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG (0x0000052c) + +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0 13 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0 0xFFFFE000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00001000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN 0x00000800 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 8 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 0x00000700 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__3 0x3 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__4 0x4 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__5 0x5 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__6 0x6 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__7 0x7 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1 2 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1 0x000000FC +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1 (0x00000530) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET (0x00000534) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR (0x00000538) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG (0x0000053c) + +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0 13 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0 0xFFFFE000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS 0x00001000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN 0x00000800 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 8 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 0x00000700 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__3 0x3 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__4 0x4 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__5 0x5 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__6 0x6 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__7 0x7 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1 2 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1 0x000000FC +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0 (0x00000540) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET (0x00000544) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR (0x00000548) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG (0x0000054c) + +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0 29 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0 0xE0000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0(v) \ + (((v) << 29) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3 24 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3 0x1F000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1 21 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1 0x00E00000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1(v) \ + (((v) << 21) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2 16 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2 0x001F0000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2 13 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2 0x0000E000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1 8 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1 0x00001F00 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3 5 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3 0x000000E0 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0x0000001F +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0) + +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1 (0x00000550) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET (0x00000554) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR (0x00000558) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG (0x0000055c) + +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0 29 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0 0xE0000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0(v) \ + (((v) << 29) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3 24 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3 0x1F000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1 21 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1 0x00E00000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1(v) \ + (((v) << 21) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2 16 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2 0x001F0000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2 13 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2 0x0000E000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1 8 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1 0x00001F00 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3 5 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3 0x000000E0 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0x0000001F +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0) + +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0 (0x00000560) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET (0x00000564) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR (0x00000568) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG (0x0000056c) + +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0 16 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3 12 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3 0x0000F000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2 8 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2 0x00000F00 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1 4 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1 0x000000F0 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0x0000000F +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0) + +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1 (0x00000570) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET (0x00000574) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR (0x00000578) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG (0x0000057c) + +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0 16 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3 12 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3 0x0000F000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2 8 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2 0x00000F00 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1 4 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1 0x000000F0 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0x0000000F +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0) + +#define HW_PXP_INPUT_FETCH_ADDR_0_CH0 (0x00000580) + +#define BP_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_1_CH0 (0x00000590) + +#define BP_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_0_CH1 (0x000005a0) + +#define BP_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_1_CH1 (0x000005b0) + +#define BP_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_CTRL_CH0 (0x000005c0) +#define HW_PXP_INPUT_STORE_CTRL_CH0_SET (0x000005c4) +#define HW_PXP_INPUT_STORE_CTRL_CH0_CLR (0x000005c8) +#define HW_PXP_INPUT_STORE_CTRL_CH0_TOG (0x000005cc) + +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_INPUT_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_INPUT_STORE_CTRL_CH1 (0x000005d0) +#define HW_PXP_INPUT_STORE_CTRL_CH1_SET (0x000005d4) +#define HW_PXP_INPUT_STORE_CTRL_CH1_CLR (0x000005d8) +#define HW_PXP_INPUT_STORE_CTRL_CH1_TOG (0x000005dc) + +#define BP_PXP_INPUT_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_INPUT_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_INPUT_STORE_STATUS_CH0 (0x000005e0) + +#define BP_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_INPUT_STORE_STATUS_CH1 (0x000005f0) + +#define BP_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_INPUT_STORE_SIZE_CH0 (0x00000600) + +#define BP_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_INPUT_STORE_SIZE_CH1 (0x00000610) + +#define BP_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_INPUT_STORE_PITCH (0x00000620) + +#define BP_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0 (0x00000630) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET (0x00000634) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR (0x00000638) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG (0x0000063c) + +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1 (0x00000640) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET (0x00000644) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR (0x00000648) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG (0x0000064c) + +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_INPUT_STORE_ADDR_0_CH0 (0x00000690) + +#define BP_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_1_CH0 (0x000006a0) + +#define BP_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_FILL_DATA_CH0 (0x000006b0) + +#define BP_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_0_CH1 (0x000006c0) + +#define BP_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_1_CH1 (0x000006d0) + +#define BP_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK0_H_CH0 (0x000006e0) + +#define BP_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK0_L_CH0 (0x000006f0) + +#define BP_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK1_H_CH0 (0x00000700) + +#define BP_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK1_L_CH0 (0x00000710) + +#define BP_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK2_H_CH0 (0x00000720) + +#define BP_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK2_L_CH0 (0x00000730) + +#define BP_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK3_H_CH0 (0x00000740) + +#define BP_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK3_L_CH0 (0x00000750) + +#define BP_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK4_H_CH0 (0x00000760) + +#define BP_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK4_L_CH0 (0x00000770) + +#define BP_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK5_H_CH0 (0x00000780) + +#define BP_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK5_L_CH0 (0x00000790) + +#define BP_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK6_H_CH0 (0x000007a0) + +#define BP_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK6_L_CH0 (0x000007b0) + +#define BP_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK7_H_CH0 (0x000007c0) + +#define BP_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK7_L_CH0 (0x000007e0) + +#define BP_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_SHIFT_L_CH0 (0x000007f0) + +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_INPUT_STORE_D_SHIFT_H_CH0 (0x00000800) + +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_INPUT_STORE_F_SHIFT_L_CH0 (0x00000810) + +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_INPUT_STORE_F_SHIFT_H_CH0 (0x00000820) + +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_INPUT_STORE_F_MASK_L_CH0 (0x00000830) + +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_INPUT_STORE_F_MASK_H_CH0 (0x00000840) + +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_DITHER_FETCH_CTRL_CH0 (0x00000850) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_SET (0x00000854) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_CLR (0x00000858) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_TOG (0x0000085c) + +#define BM_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD0 26 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD0 0x7C000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD0(v) \ + (((v) << 26) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD1 18 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES 16 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD2 14 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD2 0x0000C000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD2) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE 12 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE 0x00003000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD3 0x00000800 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD3(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD3) +#define BM_PXP_DITHER_FETCH_CTRL_CH0_VFLIP 0x00000400 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(v) \ + (((v) << 10) & BM_PXP_DITHER_FETCH_CTRL_CH0_VFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_VFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_VFLIP__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HFLIP 0x00000200 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(v) \ + (((v) << 9) & BM_PXP_DITHER_FETCH_CTRL_CH0_HFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HFLIP__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD4 6 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD4 0x000001C0 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD4(v) \ + (((v) << 6) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD4) +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE 0x00000020 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_CTRL_CH0_CH_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_DITHER_FETCH_CTRL_CH1 (0x00000860) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_SET (0x00000864) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_CLR (0x00000868) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_TOG (0x0000086c) + +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD0 26 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD0 0xFC000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD0(v) \ + (((v) << 26) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD1 18 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES 16 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD2 14 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD2 0x0000C000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD2) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE 12 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE 0x00003000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD3 0x00000800 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD3(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD3) +#define BM_PXP_DITHER_FETCH_CTRL_CH1_VFLIP 0x00000400 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_VFLIP(v) \ + (((v) << 10) & BM_PXP_DITHER_FETCH_CTRL_CH1_VFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_VFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_VFLIP__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HFLIP 0x00000200 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HFLIP(v) \ + (((v) << 9) & BM_PXP_DITHER_FETCH_CTRL_CH1_HFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HFLIP__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD4 5 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD4 0x000001E0 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD4(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD4) +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_CTRL_CH1_CH_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_DITHER_FETCH_STATUS_CH0 (0x00000870) + +#define BP_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 16 +#define BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y) +#define BP_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0 +#define BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X) + +#define HW_PXP_DITHER_FETCH_STATUS_CH1 (0x00000880) + +#define BP_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 16 +#define BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y) +#define BP_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0 +#define BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 (0x00000890) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 (0x000008a0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 (0x000008b0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 (0x000008c0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_DITHER_FETCH_SIZE_CH0 (0x000008d0) + +#define BP_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT) +#define BP_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH) + +#define HW_PXP_DITHER_FETCH_SIZE_CH1 (0x000008e0) + +#define BP_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT) +#define BP_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH) + +#define HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0 (0x000008f0) + +#define BP_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0 +#define BM_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1 (0x00000900) + +#define BP_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0 +#define BM_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_DITHER_FETCH_PITCH (0x00000910) + +#define BP_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH 16 +#define BM_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH) +#define BP_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH 0 +#define BM_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH) + +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0 (0x00000920) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET (0x00000924) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR (0x00000928) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG (0x0000092c) + +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0 13 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0 0xFFFFE000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00001000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN 0x00000800 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 8 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 0x00000700 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__3 0x3 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__4 0x4 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__5 0x5 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__6 0x6 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__7 0x7 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1 2 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1 0x000000FC +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1 (0x00000930) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET (0x00000934) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR (0x00000938) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG (0x0000093c) + +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0 13 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0 0xFFFFE000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS 0x00001000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN 0x00000800 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 8 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 0x00000700 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__3 0x3 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__4 0x4 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__5 0x5 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__6 0x6 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__7 0x7 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1 2 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1 0x000000FC +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0 (0x00000940) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET (0x00000944) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR (0x00000948) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG (0x0000094c) + +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0 29 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0 0xE0000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0(v) \ + (((v) << 29) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3 24 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3 0x1F000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1 21 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1 0x00E00000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1(v) \ + (((v) << 21) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2 16 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2 0x001F0000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2 13 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2 0x0000E000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1 8 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1 0x00001F00 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3 5 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3 0x000000E0 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0x0000001F +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0) + +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1 (0x00000950) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET (0x00000954) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR (0x00000958) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG (0x0000095c) + +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0 29 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0 0xE0000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0(v) \ + (((v) << 29) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3 24 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3 0x1F000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1 21 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1 0x00E00000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1(v) \ + (((v) << 21) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2 16 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2 0x001F0000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2 13 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2 0x0000E000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1 8 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1 0x00001F00 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3 5 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3 0x000000E0 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0x0000001F +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0) + +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0 (0x00000960) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET (0x00000964) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR (0x00000968) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG (0x0000096c) + +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0 16 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3 12 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3 0x0000F000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2 8 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2 0x00000F00 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1 4 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1 0x000000F0 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0x0000000F +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0) + +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1 (0x00000970) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET (0x00000974) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR (0x00000978) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG (0x0000097c) + +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0 16 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3 12 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3 0x0000F000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2 8 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2 0x00000F00 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1 4 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1 0x000000F0 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0x0000000F +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0) + +#define HW_PXP_DITHER_FETCH_ADDR_0_CH0 (0x00000980) + +#define BP_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_1_CH0 (0x00000990) + +#define BP_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_0_CH1 (0x000009a0) + +#define BP_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_1_CH1 (0x000009b0) + +#define BP_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_CTRL_CH0 (0x000009c0) +#define HW_PXP_DITHER_STORE_CTRL_CH0_SET (0x000009c4) +#define HW_PXP_DITHER_STORE_CTRL_CH0_CLR (0x000009c8) +#define HW_PXP_DITHER_STORE_CTRL_CH0_TOG (0x000009cc) + +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_DITHER_STORE_CTRL_CH1 (0x000009d0) +#define HW_PXP_DITHER_STORE_CTRL_CH1_SET (0x000009d4) +#define HW_PXP_DITHER_STORE_CTRL_CH1_CLR (0x000009d8) +#define HW_PXP_DITHER_STORE_CTRL_CH1_TOG (0x000009dc) + +#define BP_PXP_DITHER_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_DITHER_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_DITHER_STORE_STATUS_CH0 (0x000009e0) + +#define BP_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_DITHER_STORE_STATUS_CH1 (0x000009f0) + +#define BP_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_DITHER_STORE_SIZE_CH0 (0x00000a00) + +#define BP_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_DITHER_STORE_SIZE_CH1 (0x00000a10) + +#define BP_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_DITHER_STORE_PITCH (0x00000a20) + +#define BP_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0 (0x00000a30) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET (0x00000a34) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR (0x00000a38) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG (0x00000a3c) + +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1 (0x00000a40) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET (0x00000a44) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR (0x00000a48) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG (0x00000a4c) + +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_DITHER_STORE_ADDR_0_CH0 (0x00000a90) + +#define BP_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_1_CH0 (0x00000aa0) + +#define BP_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_FILL_DATA_CH0 (0x00000ab0) + +#define BP_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_0_CH1 (0x00000ac0) + +#define BP_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_1_CH1 (0x00000ad0) + +#define BP_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK0_H_CH0 (0x00000ae0) + +#define BP_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK0_L_CH0 (0x00000af0) + +#define BP_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK1_H_CH0 (0x00000b00) + +#define BP_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK1_L_CH0 (0x00000b10) + +#define BP_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK2_H_CH0 (0x00000b20) + +#define BP_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK2_L_CH0 (0x00000b30) + +#define BP_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK3_H_CH0 (0x00000b40) + +#define BP_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK3_L_CH0 (0x00000b50) + +#define BP_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK4_H_CH0 (0x00000b60) + +#define BP_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK4_L_CH0 (0x00000b70) + +#define BP_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK5_H_CH0 (0x00000b80) + +#define BP_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK5_L_CH0 (0x00000b90) + +#define BP_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK6_H_CH0 (0x00000ba0) + +#define BP_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK6_L_CH0 (0x00000bb0) + +#define BP_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK7_H_CH0 (0x00000bc0) + +#define BP_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK7_L_CH0 (0x00000bd0) + +#define BP_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_SHIFT_L_CH0 (0x00000be0) + +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_DITHER_STORE_D_SHIFT_H_CH0 (0x00000bf0) + +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_DITHER_STORE_F_SHIFT_L_CH0 (0x00000c00) + +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_DITHER_STORE_F_SHIFT_H_CH0 (0x00000c10) + +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_DITHER_STORE_F_MASK_L_CH0 (0x00000c20) + +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_DITHER_STORE_F_MASK_H_CH0 (0x00000c30) + +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_WFA_FETCH_CTRL (0x00000c40) +#define HW_PXP_WFA_FETCH_CTRL_SET (0x00000c44) +#define HW_PXP_WFA_FETCH_CTRL_CLR (0x00000c48) +#define HW_PXP_WFA_FETCH_CTRL_TOG (0x00000c4c) + +#define BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN 0x80000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN) +#define BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN 0x40000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN) +#define BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ 0x20000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ(v) \ + (((v) << 29) & BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ) +#define BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ 0x10000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ(v) \ + (((v) << 28) & BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ) +#define BP_PXP_WFA_FETCH_CTRL_RSVD0 24 +#define BM_PXP_WFA_FETCH_CTRL_RSVD0 0x0F000000 +#define BF_PXP_WFA_FETCH_CTRL_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFA_FETCH_CTRL_RSVD0) +#define BP_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE 22 +#define BM_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE 0x00C00000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(v) \ + (((v) << 22) & BM_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__1 0x1 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__2 0x2 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__3 0x3 +#define BP_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP 20 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP 0x00300000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(v) \ + (((v) << 20) & BM_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP) +#define BP_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE 18 +#define BM_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE 0x000C0000 +#define BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(v) \ + (((v) << 18) & BM_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__1 0x1 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__2 0x2 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__3 0x3 +#define BP_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP 16 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP 0x00030000 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP) +#define BP_PXP_WFA_FETCH_CTRL_RSVD1 14 +#define BM_PXP_WFA_FETCH_CTRL_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_CTRL_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_CTRL_RSVD1) +#define BM_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE 0x00002000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE(v) \ + (((v) << 13) & BM_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN 0x00001000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(v) \ + (((v) << 12) & BM_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE 0x00000800 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(v) \ + (((v) << 11) & BM_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE 0x00000400 +#define BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(v) \ + (((v) << 10) & BM_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF 0x00000200 +#define BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(v) \ + (((v) << 9) & BM_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF) +#define BV_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_EN 0x00000100 +#define BF_PXP_WFA_FETCH_CTRL_BF2_EN(v) \ + (((v) << 8) & BM_PXP_WFA_FETCH_CTRL_BF2_EN) +#define BV_PXP_WFA_FETCH_CTRL_BF2_EN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_EN__1 0x1 +#define BP_PXP_WFA_FETCH_CTRL_RSVD2 6 +#define BM_PXP_WFA_FETCH_CTRL_RSVD2 0x000000C0 +#define BF_PXP_WFA_FETCH_CTRL_RSVD2(v) \ + (((v) << 6) & BM_PXP_WFA_FETCH_CTRL_RSVD2) +#define BM_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE 0x00000020 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE(v) \ + (((v) << 5) & BM_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN 0x00000010 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(v) \ + (((v) << 4) & BM_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE 0x00000008 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(v) \ + (((v) << 3) & BM_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE 0x00000004 +#define BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(v) \ + (((v) << 2) & BM_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF 0x00000002 +#define BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(v) \ + (((v) << 1) & BM_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF) +#define BV_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_EN 0x00000001 +#define BF_PXP_WFA_FETCH_CTRL_BF1_EN(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_CTRL_BF1_EN) +#define BV_PXP_WFA_FETCH_CTRL_BF1_EN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_EN__1 0x1 + +#define HW_PXP_WFA_FETCH_BUF1_ADDR (0x00000c50) + +#define BP_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR 0 +#define BM_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFA_FETCH_BUF1_PITCH (0x00000c60) + +#define BP_PXP_WFA_FETCH_BUF1_PITCH_RSVD 16 +#define BM_PXP_WFA_FETCH_BUF1_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFA_FETCH_BUF1_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_PITCH_RSVD) +#define BP_PXP_WFA_FETCH_BUF1_PITCH_PITCH 0 +#define BM_PXP_WFA_FETCH_BUF1_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFA_FETCH_BUF1_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_PITCH_PITCH) + +#define HW_PXP_WFA_FETCH_BUF1_SIZE (0x00000c70) + +#define BP_PXP_WFA_FETCH_BUF1_SIZE_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD0) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD1) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH) + +#define HW_PXP_WFA_FETCH_BUF2_ADDR (0x00000c80) + +#define BP_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR 0 +#define BM_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFA_FETCH_BUF2_PITCH (0x00000c90) + +#define BP_PXP_WFA_FETCH_BUF2_PITCH_RSVD 16 +#define BM_PXP_WFA_FETCH_BUF2_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFA_FETCH_BUF2_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_PITCH_RSVD) +#define BP_PXP_WFA_FETCH_BUF2_PITCH_PITCH 0 +#define BM_PXP_WFA_FETCH_BUF2_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFA_FETCH_BUF2_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_PITCH_PITCH) + +#define HW_PXP_WFA_FETCH_BUF2_SIZE (0x00000ca0) + +#define BP_PXP_WFA_FETCH_BUF2_SIZE_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD0) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD1) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH) + +#define HW_PXP_WFA_ARRAY_PIXEL0_MASK (0x00000cb0) + +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL1_MASK (0x00000cc0) + +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL2_MASK (0x00000cd0) + +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL3_MASK (0x00000ce0) + +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL4_MASK (0x00000cf0) + +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL5_MASK (0x00000d00) + +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL6_MASK (0x00000d10) + +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL7_MASK (0x00000d20) + +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG0_MASK (0x00000d30) + +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG1_MASK (0x00000d40) + +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG2_MASK (0x00000d50) + +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG3_MASK (0x00000d60) + +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG4_MASK (0x00000d70) + +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG5_MASK (0x00000d80) + +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG6_MASK (0x00000d90) + +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG7_MASK (0x00000da0) + +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS) + +#define HW_PXP_WFA_FETCH_BUF1_CORD (0x00000db0) + +#define BP_PXP_WFA_FETCH_BUF1_CORD_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF1_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF1_CORD_RSVD0) +#define BP_PXP_WFA_FETCH_BUF1_CORD_YCORD 16 +#define BM_PXP_WFA_FETCH_BUF1_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_CORD_YCORD) +#define BP_PXP_WFA_FETCH_BUF1_CORD_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF1_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF1_CORD_RSVD1) +#define BP_PXP_WFA_FETCH_BUF1_CORD_XCORD 0 +#define BM_PXP_WFA_FETCH_BUF1_CORD_XCORD 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF1_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_CORD_XCORD) + +#define HW_PXP_WFA_FETCH_BUF2_CORD (0x00000dc0) + +#define BP_PXP_WFA_FETCH_BUF2_CORD_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF2_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF2_CORD_RSVD0) +#define BP_PXP_WFA_FETCH_BUF2_CORD_YCORD 16 +#define BM_PXP_WFA_FETCH_BUF2_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_CORD_YCORD) +#define BP_PXP_WFA_FETCH_BUF2_CORD_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF2_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF2_CORD_RSVD1) +#define BP_PXP_WFA_FETCH_BUF2_CORD_XCORD 0 +#define BM_PXP_WFA_FETCH_BUF2_CORD_XCORD 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF2_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_CORD_XCORD) + +#define HW_PXP_WFA_ARRAY_FLAG8_MASK (0x00000dd0) + +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG9_MASK (0x00000de0) + +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG10_MASK (0x00000df0) + +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG11_MASK (0x00000e00) + +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG12_MASK (0x00000e10) + +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG13_MASK (0x00000e20) + +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG14_MASK (0x00000e30) + +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG15_MASK (0x00000e40) + +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_REG0 (0x00000e50) + +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE3 24 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE3 0xFF000000 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE3(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE3) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE2 16 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE2 0x00FF0000 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE2(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE2) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE1 8 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE1 0x0000FF00 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE1(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE1) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE0 0 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE0 0x000000FF +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE0(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE0) + +#define HW_PXP_WFA_ARRAY_REG1 (0x00000e60) + +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE7 24 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE7 0xFF000000 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE7(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE7) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE6 16 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE6 0x00FF0000 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE6(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE6) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE5 8 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE5 0x0000FF00 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE5(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE5) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE4 0 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE4 0x000000FF +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE4(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE4) + +#define HW_PXP_WFA_ARRAY_REG2 (0x00000e70) + +#define BP_PXP_WFA_ARRAY_REG2_RSVD0 16 +#define BM_PXP_WFA_ARRAY_REG2_RSVD0 0xFFFF0000 +#define BF_PXP_WFA_ARRAY_REG2_RSVD0(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG2_RSVD0) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG15 0x00008000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG15(v) \ + (((v) << 15) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG15) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG14 0x00004000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG14(v) \ + (((v) << 14) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG14) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG13 0x00002000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG13(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG13) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG12 0x00001000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG12(v) \ + (((v) << 12) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG12) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG11 0x00000800 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG11(v) \ + (((v) << 11) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG11) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG10 0x00000400 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG10(v) \ + (((v) << 10) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG10) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG9 0x00000200 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG9(v) \ + (((v) << 9) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG9) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG8 0x00000100 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG8(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG8) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG7 0x00000080 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG7(v) \ + (((v) << 7) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG7) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG6 0x00000040 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG6(v) \ + (((v) << 6) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG6) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG5 0x00000020 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG5) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG4 0x00000010 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG4(v) \ + (((v) << 4) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG4) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG3 0x00000008 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG3(v) \ + (((v) << 3) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG3) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG2 0x00000004 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG2(v) \ + (((v) << 2) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG2) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG1 0x00000002 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG1(v) \ + (((v) << 1) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG1) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG0 0x00000001 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG0(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG0) + +#define HW_PXP_WFE_A_STORE_CTRL_CH0 (0x00000e80) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_SET (0x00000e84) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_CLR (0x00000e88) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_TOG (0x00000e8c) + +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_WFE_A_STORE_CTRL_CH1 (0x00000e90) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_SET (0x00000e94) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_CLR (0x00000e98) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_TOG (0x00000e9c) + +#define BP_PXP_WFE_A_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_A_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_WFE_A_STORE_STATUS_CH0 (0x00000ea0) + +#define BP_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_WFE_A_STORE_STATUS_CH1 (0x00000eb0) + +#define BP_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_WFE_A_STORE_SIZE_CH0 (0x00000ec0) + +#define BP_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_WFE_A_STORE_SIZE_CH1 (0x00000ed0) + +#define BP_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_WFE_A_STORE_PITCH (0x00000ee0) + +#define BP_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0 (0x00000ef0) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET (0x00000ef4) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR (0x00000ef8) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG (0x00000efc) + +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1 (0x00000f00) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET (0x00000f04) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR (0x00000f08) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG (0x00000f0c) + +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_WFE_A_STORE_ADDR_0_CH0 (0x00000f50) + +#define BP_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_1_CH0 (0x00000f60) + +#define BP_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_A_STORE_FILL_DATA_CH0 (0x00000f70) + +#define BP_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_0_CH1 (0x00000f80) + +#define BP_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_1_CH1 (0x00000f90) + +#define BP_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK0_H_CH0 (0x00000fa0) + +#define BP_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK0_L_CH0 (0x00000fb0) + +#define BP_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK1_H_CH0 (0x00000fc0) + +#define BP_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK1_L_CH0 (0x00000fd0) + +#define BP_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK2_H_CH0 (0x00000fe0) + +#define BP_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK2_L_CH0 (0x00000ff0) + +#define BP_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK3_H_CH0 (0x00001000) + +#define BP_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK3_L_CH0 (0x00001010) + +#define BP_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK4_H_CH0 (0x00001020) + +#define BP_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK4_L_CH0 (0x00001030) + +#define BP_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK5_H_CH0 (0x00001040) + +#define BP_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK5_L_CH0 (0x00001050) + +#define BP_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK6_H_CH0 (0x00001060) + +#define BP_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK6_L_CH0 (0x00001070) + +#define BP_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK7_H_CH0 (0x00001080) + +#define BP_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK7_L_CH0 (0x00001090) + +#define BP_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_SHIFT_L_CH0 (0x000010a0) + +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_WFE_A_STORE_D_SHIFT_H_CH0 (0x000010b0) + +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_WFE_A_STORE_F_SHIFT_L_CH0 (0x000010c0) + +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_WFE_A_STORE_F_SHIFT_H_CH0 (0x000010d0) + +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_WFE_A_STORE_F_MASK_L_CH0 (0x000010e0) + +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_WFE_A_STORE_F_MASK_H_CH0 (0x000010f0) + +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_WFB_FETCH_CTRL (0x00001100) +#define HW_PXP_WFB_FETCH_CTRL_SET (0x00001104) +#define HW_PXP_WFB_FETCH_CTRL_CLR (0x00001108) +#define HW_PXP_WFB_FETCH_CTRL_TOG (0x0000110c) + +#define BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN 0x80000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN) +#define BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN 0x40000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN) +#define BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ 0x20000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ(v) \ + (((v) << 29) & BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ) +#define BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ 0x10000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ(v) \ + (((v) << 28) & BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ) +#define BP_PXP_WFB_FETCH_CTRL_RSVD0 24 +#define BM_PXP_WFB_FETCH_CTRL_RSVD0 0x0F000000 +#define BF_PXP_WFB_FETCH_CTRL_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFB_FETCH_CTRL_RSVD0) +#define BP_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE 22 +#define BM_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE 0x00C00000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(v) \ + (((v) << 22) & BM_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__1 0x1 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__2 0x2 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__3 0x3 +#define BP_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP 20 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP 0x00300000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(v) \ + (((v) << 20) & BM_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP) +#define BP_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE 18 +#define BM_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE 0x000C0000 +#define BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(v) \ + (((v) << 18) & BM_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__1 0x1 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__2 0x2 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__3 0x3 +#define BP_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP 16 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP 0x00030000 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP) +#define BP_PXP_WFB_FETCH_CTRL_RSVD1 14 +#define BM_PXP_WFB_FETCH_CTRL_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_CTRL_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_CTRL_RSVD1) +#define BM_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE 0x00002000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(v) \ + (((v) << 13) & BM_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN 0x00001000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(v) \ + (((v) << 12) & BM_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE 0x00000800 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(v) \ + (((v) << 11) & BM_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE 0x00000400 +#define BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(v) \ + (((v) << 10) & BM_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF 0x00000200 +#define BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(v) \ + (((v) << 9) & BM_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF) +#define BV_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_EN 0x00000100 +#define BF_PXP_WFB_FETCH_CTRL_BF2_EN(v) \ + (((v) << 8) & BM_PXP_WFB_FETCH_CTRL_BF2_EN) +#define BV_PXP_WFB_FETCH_CTRL_BF2_EN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_EN__1 0x1 +#define BP_PXP_WFB_FETCH_CTRL_RSVD2 6 +#define BM_PXP_WFB_FETCH_CTRL_RSVD2 0x000000C0 +#define BF_PXP_WFB_FETCH_CTRL_RSVD2(v) \ + (((v) << 6) & BM_PXP_WFB_FETCH_CTRL_RSVD2) +#define BM_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE 0x00000020 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(v) \ + (((v) << 5) & BM_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN 0x00000010 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(v) \ + (((v) << 4) & BM_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE 0x00000008 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(v) \ + (((v) << 3) & BM_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE 0x00000004 +#define BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(v) \ + (((v) << 2) & BM_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF 0x00000002 +#define BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(v) \ + (((v) << 1) & BM_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF) +#define BV_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_EN 0x00000001 +#define BF_PXP_WFB_FETCH_CTRL_BF1_EN(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_CTRL_BF1_EN) +#define BV_PXP_WFB_FETCH_CTRL_BF1_EN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_EN__1 0x1 + +#define HW_PXP_WFB_FETCH_BUF1_ADDR (0x00001110) + +#define BP_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR 0 +#define BM_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFB_FETCH_BUF1_PITCH (0x00001120) + +#define BP_PXP_WFB_FETCH_BUF1_PITCH_RSVD 16 +#define BM_PXP_WFB_FETCH_BUF1_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF1_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_PITCH_RSVD) +#define BP_PXP_WFB_FETCH_BUF1_PITCH_PITCH 0 +#define BM_PXP_WFB_FETCH_BUF1_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF1_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_PITCH_PITCH) + +#define HW_PXP_WFB_FETCH_BUF1_SIZE (0x00001130) + +#define BP_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT) +#define BP_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH) + +#define HW_PXP_WFB_FETCH_BUF2_ADDR (0x00001140) + +#define BP_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR 0 +#define BM_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFB_FETCH_BUF2_PITCH (0x00001150) + +#define BP_PXP_WFB_FETCH_BUF2_PITCH_RSVD 16 +#define BM_PXP_WFB_FETCH_BUF2_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF2_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_PITCH_RSVD) +#define BP_PXP_WFB_FETCH_BUF2_PITCH_PITCH 0 +#define BM_PXP_WFB_FETCH_BUF2_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF2_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_PITCH_PITCH) + +#define HW_PXP_WFB_FETCH_BUF2_SIZE (0x00001160) + +#define BP_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT) +#define BP_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH) + +#define HW_PXP_WFB_ARRAY_PIXEL0_MASK (0x00001170) + +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL1_MASK (0x00001180) + +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL2_MASK (0x00001190) + +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL3_MASK (0x000011a0) + +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL4_MASK (0x000011b0) + +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL5_MASK (0x000011c0) + +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL6_MASK (0x000011d0) + +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL7_MASK (0x000011e0) + +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG0_MASK (0x000011f0) + +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG1_MASK (0x00001200) + +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG2_MASK (0x00001210) + +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG3_MASK (0x00001220) + +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG4_MASK (0x00001230) + +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG5_MASK (0x00001240) + +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG6_MASK (0x00001250) + +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG7_MASK (0x00001260) + +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS) + +#define HW_PXP_WFB_FETCH_BUF1_CORD (0x00001270) + +#define BP_PXP_WFB_FETCH_BUF1_CORD_RSVD0 30 +#define BM_PXP_WFB_FETCH_BUF1_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_BUF1_CORD_RSVD0) +#define BP_PXP_WFB_FETCH_BUF1_CORD_YCORD 16 +#define BM_PXP_WFB_FETCH_BUF1_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_CORD_YCORD) +#define BP_PXP_WFB_FETCH_BUF1_CORD_RSVD1 14 +#define BM_PXP_WFB_FETCH_BUF1_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_BUF1_CORD_RSVD1) +#define BP_PXP_WFB_FETCH_BUF1_CORD_XCORD 0 +#define BM_PXP_WFB_FETCH_BUF1_CORD_XCORD 0x00003FFF +#define BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_CORD_XCORD) + +#define HW_PXP_WFB_FETCH_BUF2_CORD (0x00001280) + +#define BP_PXP_WFB_FETCH_BUF2_CORD_RSVD0 30 +#define BM_PXP_WFB_FETCH_BUF2_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_BUF2_CORD_RSVD0) +#define BP_PXP_WFB_FETCH_BUF2_CORD_YCORD 16 +#define BM_PXP_WFB_FETCH_BUF2_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_CORD_YCORD) +#define BP_PXP_WFB_FETCH_BUF2_CORD_RSVD1 14 +#define BM_PXP_WFB_FETCH_BUF2_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_BUF2_CORD_RSVD1) +#define BP_PXP_WFB_FETCH_BUF2_CORD_XCORD 0 +#define BM_PXP_WFB_FETCH_BUF2_CORD_XCORD 0x00003FFF +#define BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_CORD_XCORD) + +#define HW_PXP_WFB_ARRAY_FLAG8_MASK (0x00001290) + +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG9_MASK (0x000012a0) + +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG10_MASK (0x000012b0) + +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG11_MASK (0x000012c0) + +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG12_MASK (0x000012d0) + +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG13_MASK (0x000012e0) + +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG14_MASK (0x000012f0) + +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG15_MASK (0x00001300) + +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_REG0 (0x00001310) + +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE3 24 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE3 0xFF000000 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE3(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE3) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE2 16 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE2 0x00FF0000 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE2(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE2) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE1 8 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE1 0x0000FF00 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE1(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE1) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE0 0 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE0 0x000000FF +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE0(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE0) + +#define HW_PXP_WFB_ARRAY_REG1 (0x00001320) + +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE7 24 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE7 0xFF000000 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE7(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE7) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE6 16 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE6 0x00FF0000 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE6(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE6) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE5 8 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE5 0x0000FF00 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE5(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE5) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE4 0 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE4 0x000000FF +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE4(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE4) + +#define HW_PXP_WFB_ARRAY_REG2 (0x00001330) + +#define BP_PXP_WFB_ARRAY_REG2_RSVD0 16 +#define BM_PXP_WFB_ARRAY_REG2_RSVD0 0xFFFF0000 +#define BF_PXP_WFB_ARRAY_REG2_RSVD0(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG2_RSVD0) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG15 0x00008000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG15(v) \ + (((v) << 15) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG15) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG14 0x00004000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG14(v) \ + (((v) << 14) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG14) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG13 0x00002000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG13(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG13) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG12 0x00001000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG12(v) \ + (((v) << 12) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG12) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG11 0x00000800 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG11(v) \ + (((v) << 11) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG11) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG10 0x00000400 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG10(v) \ + (((v) << 10) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG10) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG9 0x00000200 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG9(v) \ + (((v) << 9) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG9) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG8 0x00000100 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG8(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG8) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG7 0x00000080 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG7(v) \ + (((v) << 7) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG7) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG6 0x00000040 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG6(v) \ + (((v) << 6) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG6) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG5 0x00000020 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG5) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG4 0x00000010 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG4(v) \ + (((v) << 4) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG4) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG3 0x00000008 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG3(v) \ + (((v) << 3) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG3) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG2 0x00000004 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG2(v) \ + (((v) << 2) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG2) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG1 0x00000002 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG1(v) \ + (((v) << 1) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG1) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG0 0x00000001 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG0(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG0) + +#define HW_PXP_WFE_B_STORE_CTRL_CH0 (0x00001340) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_SET (0x00001344) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_CLR (0x00001348) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_TOG (0x0000134c) + +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_WFE_B_STORE_CTRL_CH1 (0x00001350) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_SET (0x00001354) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_CLR (0x00001358) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_TOG (0x0000135c) + +#define BP_PXP_WFE_B_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_B_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_WFE_B_STORE_STATUS_CH0 (0x00001360) + +#define BP_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_WFE_B_STORE_STATUS_CH1 (0x00001370) + +#define BP_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_WFE_B_STORE_SIZE_CH0 (0x00001380) + +#define BP_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_WFE_B_STORE_SIZE_CH1 (0x00001390) + +#define BP_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_WFE_B_STORE_PITCH (0x000013a0) + +#define BP_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0 (0x000013b0) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET (0x000013b4) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR (0x000013b8) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG (0x000013bc) + +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1 (0x000013c0) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET (0x000013c4) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR (0x000013c8) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG (0x000013cc) + +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_WFE_B_STORE_ADDR_0_CH0 (0x00001410) + +#define BP_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_1_CH0 (0x00001420) + +#define BP_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_B_STORE_FILL_DATA_CH0 (0x00001430) + +#define BP_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_0_CH1 (0x00001440) + +#define BP_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_1_CH1 (0x00001450) + +#define BP_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK0_H_CH0 (0x00001460) + +#define BP_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK0_L_CH0 (0x00001470) + +#define BP_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK1_H_CH0 (0x00001480) + +#define BP_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK1_L_CH0 (0x00001490) + +#define BP_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK2_H_CH0 (0x000014a0) + +#define BP_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK2_L_CH0 (0x000014b0) + +#define BP_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK3_H_CH0 (0x000014c0) + +#define BP_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK3_L_CH0 (0x000014d0) + +#define BP_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK4_H_CH0 (0x000014e0) + +#define BP_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK4_L_CH0 (0x000014f0) + +#define BP_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK5_H_CH0 (0x00001500) + +#define BP_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK5_L_CH0 (0x00001510) + +#define BP_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK6_H_CH0 (0x00001520) + +#define BP_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK6_L_CH0 (0x00001530) + +#define BP_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK7_H_CH0 (0x00001540) + +#define BP_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK7_L_CH0 (0x00001550) + +#define BP_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0 (0x00001560) + +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0 (0x00001570) + +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0 (0x00001580) + +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_WFE_B_STORE_F_SHIFT_H_CH0 (0x00001590) + +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_WFE_B_STORE_F_MASK_L_CH0 (0x000015a0) + +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_WFE_B_STORE_F_MASK_H_CH0 (0x000015b0) + +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_FETCH_WFE_A_DEBUG (0x000015c0) + +#define BP_PXP_FETCH_WFE_A_DEBUG_RSVD 29 +#define BM_PXP_FETCH_WFE_A_DEBUG_RSVD 0xE0000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_RSVD(v) \ + (((v) << 29) & BM_PXP_FETCH_WFE_A_DEBUG_RSVD) +#define BM_PXP_FETCH_WFE_A_DEBUG_BUF_SEL 0x10000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_FETCH_WFE_A_DEBUG_BUF_SEL) +#define BV_PXP_FETCH_WFE_A_DEBUG_BUF_SEL__BF0 0x0 +#define BV_PXP_FETCH_WFE_A_DEBUG_BUF_SEL__BF1 0x1 +#define BP_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL 24 +#define BM_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL 0x0F000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL(v) \ + (((v) << 24) & BM_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL) +#define BP_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE 0 +#define BM_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE) + +#define HW_PXP_FETCH_WFE_B_DEBUG (0x000015d0) + +#define BP_PXP_FETCH_WFE_B_DEBUG_RSVD 29 +#define BM_PXP_FETCH_WFE_B_DEBUG_RSVD 0xE0000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_RSVD(v) \ + (((v) << 29) & BM_PXP_FETCH_WFE_B_DEBUG_RSVD) +#define BM_PXP_FETCH_WFE_B_DEBUG_BUF_SEL 0x10000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_FETCH_WFE_B_DEBUG_BUF_SEL) +#define BV_PXP_FETCH_WFE_B_DEBUG_BUF_SEL__BF0 0x0 +#define BV_PXP_FETCH_WFE_B_DEBUG_BUF_SEL__BF1 0x1 +#define BP_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL 24 +#define BM_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL 0x0F000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL(v) \ + (((v) << 24) & BM_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL) +#define BP_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE 0 +#define BM_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE) + +#define HW_PXP_DITHER_CTRL (0x00001670) +#define HW_PXP_DITHER_CTRL_SET (0x00001674) +#define HW_PXP_DITHER_CTRL_CLR (0x00001678) +#define HW_PXP_DITHER_CTRL_TOG (0x0000167c) + +#define BM_PXP_DITHER_CTRL_BUSY0 0x80000000 +#define BF_PXP_DITHER_CTRL_BUSY0(v) \ + (((v) << 31) & BM_PXP_DITHER_CTRL_BUSY0) +#define BM_PXP_DITHER_CTRL_BUSY1 0x40000000 +#define BF_PXP_DITHER_CTRL_BUSY1(v) \ + (((v) << 30) & BM_PXP_DITHER_CTRL_BUSY1) +#define BM_PXP_DITHER_CTRL_BUSY2 0x20000000 +#define BF_PXP_DITHER_CTRL_BUSY2(v) \ + (((v) << 29) & BM_PXP_DITHER_CTRL_BUSY2) +#define BP_PXP_DITHER_CTRL_RSVD0 25 +#define BM_PXP_DITHER_CTRL_RSVD0 0x1E000000 +#define BF_PXP_DITHER_CTRL_RSVD0(v) \ + (((v) << 25) & BM_PXP_DITHER_CTRL_RSVD0) +#define BM_PXP_DITHER_CTRL_ORDERED_ROUND_MODE 0x01000000 +#define BF_PXP_DITHER_CTRL_ORDERED_ROUND_MODE(v) \ + (((v) << 24) & BM_PXP_DITHER_CTRL_ORDERED_ROUND_MODE) +#define BV_PXP_DITHER_CTRL_ORDERED_ROUND_MODE__0 0x0 +#define BV_PXP_DITHER_CTRL_ORDERED_ROUND_MODE__1 0x1 +#define BM_PXP_DITHER_CTRL_FINAL_LUT_ENABLE 0x00800000 +#define BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE(v) \ + (((v) << 23) & BM_PXP_DITHER_CTRL_FINAL_LUT_ENABLE) +#define BV_PXP_DITHER_CTRL_FINAL_LUT_ENABLE__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_FINAL_LUT_ENABLE__Enabled 0x1 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE 21 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE 0x00600000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(v) \ + (((v) << 21) & BM_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE 19 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE 0x00180000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(v) \ + (((v) << 19) & BM_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE 17 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE 0x00060000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(v) \ + (((v) << 17) & BM_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_LUT_MODE 15 +#define BM_PXP_DITHER_CTRL_LUT_MODE 0x00018000 +#define BF_PXP_DITHER_CTRL_LUT_MODE(v) \ + (((v) << 15) & BM_PXP_DITHER_CTRL_LUT_MODE) +#define BV_PXP_DITHER_CTRL_LUT_MODE__0 0x0 +#define BV_PXP_DITHER_CTRL_LUT_MODE__1 0x1 +#define BV_PXP_DITHER_CTRL_LUT_MODE__2 0x2 +#define BV_PXP_DITHER_CTRL_LUT_MODE__3 0x3 +#define BP_PXP_DITHER_CTRL_NUM_QUANT_BIT 12 +#define BM_PXP_DITHER_CTRL_NUM_QUANT_BIT 0x00007000 +#define BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(v) \ + (((v) << 12) & BM_PXP_DITHER_CTRL_NUM_QUANT_BIT) +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__0 0x0 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__1 0x1 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__2 0x2 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__3 0x3 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__4 0x4 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__5 0x5 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__6 0x6 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE2 9 +#define BM_PXP_DITHER_CTRL_DITHER_MODE2 0x00000E00 +#define BF_PXP_DITHER_CTRL_DITHER_MODE2(v) \ + (((v) << 9) & BM_PXP_DITHER_CTRL_DITHER_MODE2) +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE1 6 +#define BM_PXP_DITHER_CTRL_DITHER_MODE1 0x000001C0 +#define BF_PXP_DITHER_CTRL_DITHER_MODE1(v) \ + (((v) << 6) & BM_PXP_DITHER_CTRL_DITHER_MODE1) +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE0 3 +#define BM_PXP_DITHER_CTRL_DITHER_MODE0 0x00000038 +#define BF_PXP_DITHER_CTRL_DITHER_MODE0(v) \ + (((v) << 3) & BM_PXP_DITHER_CTRL_DITHER_MODE0) +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__7 0x7 +#define BM_PXP_DITHER_CTRL_ENABLE2 0x00000004 +#define BF_PXP_DITHER_CTRL_ENABLE2(v) \ + (((v) << 2) & BM_PXP_DITHER_CTRL_ENABLE2) +#define BV_PXP_DITHER_CTRL_ENABLE2__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE2__Enabled 0x1 +#define BM_PXP_DITHER_CTRL_ENABLE1 0x00000002 +#define BF_PXP_DITHER_CTRL_ENABLE1(v) \ + (((v) << 1) & BM_PXP_DITHER_CTRL_ENABLE1) +#define BV_PXP_DITHER_CTRL_ENABLE1__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE1__Enabled 0x1 +#define BM_PXP_DITHER_CTRL_ENABLE0 0x00000001 +#define BF_PXP_DITHER_CTRL_ENABLE0(v) \ + (((v) << 0) & BM_PXP_DITHER_CTRL_ENABLE0) +#define BV_PXP_DITHER_CTRL_ENABLE0__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE0__Enabled 0x1 + +#define HW_PXP_DITHER_FINAL_LUT_DATA0 (0x00001680) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_SET (0x00001684) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_CLR (0x00001688) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_TOG (0x0000168c) + +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA3 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA3 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA3) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA2 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA2 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA2) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA1 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA1 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA1) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA0 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA0 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA0) + +#define HW_PXP_DITHER_FINAL_LUT_DATA1 (0x00001690) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_SET (0x00001694) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_CLR (0x00001698) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_TOG (0x0000169c) + +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA7 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA7 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA7) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA6 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA6 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA6) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA5 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA5 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA5) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA4 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA4 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA4) + +#define HW_PXP_DITHER_FINAL_LUT_DATA2 (0x000016a0) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_SET (0x000016a4) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_CLR (0x000016a8) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_TOG (0x000016ac) + +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA11 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA11 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA11) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA10 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA10 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA10) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA9 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA9 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA9) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA8 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA8 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA8) + +#define HW_PXP_DITHER_FINAL_LUT_DATA3 (0x000016b0) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_SET (0x000016b4) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_CLR (0x000016b8) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_TOG (0x000016bc) + +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA15 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA15 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA15) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA14 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA14 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA14) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA13 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA13 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA13) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA12 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA12 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA12) + +#define HW_PXP_WFE_A_CTRL (0x000016c0) +#define HW_PXP_WFE_A_CTRL_SET (0x000016c4) +#define HW_PXP_WFE_A_CTRL_CLR (0x000016c8) +#define HW_PXP_WFE_A_CTRL_TOG (0x000016cc) + +#define BM_PXP_WFE_A_CTRL_DONE 0x80000000 +#define BF_PXP_WFE_A_CTRL_DONE(v) \ + (((v) << 31) & BM_PXP_WFE_A_CTRL_DONE) +#define BP_PXP_WFE_A_CTRL_RSVD0 3 +#define BM_PXP_WFE_A_CTRL_RSVD0 0x7FFFFFF8 +#define BF_PXP_WFE_A_CTRL_RSVD0(v) \ + (((v) << 3) & BM_PXP_WFE_A_CTRL_RSVD0) +#define BM_PXP_WFE_A_CTRL_SW_RESET 0x00000004 +#define BF_PXP_WFE_A_CTRL_SW_RESET(v) \ + (((v) << 2) & BM_PXP_WFE_A_CTRL_SW_RESET) +#define BM_PXP_WFE_A_CTRL_RSVD1 0x00000002 +#define BF_PXP_WFE_A_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_WFE_A_CTRL_RSVD1) +#define BM_PXP_WFE_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_WFE_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_WFE_A_CTRL_ENABLE) +#define BV_PXP_WFE_A_CTRL_ENABLE__0 0x0 +#define BV_PXP_WFE_A_CTRL_ENABLE__1 0x1 + +#define HW_PXP_WFE_A_DIMENSIONS (0x000016d0) + +#define BP_PXP_WFE_A_DIMENSIONS_RSVD0 28 +#define BM_PXP_WFE_A_DIMENSIONS_RSVD0 0xF0000000 +#define BF_PXP_WFE_A_DIMENSIONS_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_A_DIMENSIONS_RSVD0) +#define BP_PXP_WFE_A_DIMENSIONS_HEIGHT 16 +#define BM_PXP_WFE_A_DIMENSIONS_HEIGHT 0x0FFF0000 +#define BF_PXP_WFE_A_DIMENSIONS_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_DIMENSIONS_HEIGHT) +#define BP_PXP_WFE_A_DIMENSIONS_RSVD1 12 +#define BM_PXP_WFE_A_DIMENSIONS_RSVD1 0x0000F000 +#define BF_PXP_WFE_A_DIMENSIONS_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_A_DIMENSIONS_RSVD1) +#define BP_PXP_WFE_A_DIMENSIONS_WIDTH 0 +#define BM_PXP_WFE_A_DIMENSIONS_WIDTH 0x00000FFF +#define BF_PXP_WFE_A_DIMENSIONS_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_DIMENSIONS_WIDTH) + +#define HW_PXP_WFE_A_OFFSET (0x000016e0) + +#define BP_PXP_WFE_A_OFFSET_RSVD0 28 +#define BM_PXP_WFE_A_OFFSET_RSVD0 0xF0000000 +#define BF_PXP_WFE_A_OFFSET_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_A_OFFSET_RSVD0) +#define BP_PXP_WFE_A_OFFSET_Y_OFFSET 16 +#define BM_PXP_WFE_A_OFFSET_Y_OFFSET 0x0FFF0000 +#define BF_PXP_WFE_A_OFFSET_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_WFE_A_OFFSET_Y_OFFSET) +#define BP_PXP_WFE_A_OFFSET_RSVD1 12 +#define BM_PXP_WFE_A_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_WFE_A_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_A_OFFSET_RSVD1) +#define BP_PXP_WFE_A_OFFSET_X_OFFSET 0 +#define BM_PXP_WFE_A_OFFSET_X_OFFSET 0x00000FFF +#define BF_PXP_WFE_A_OFFSET_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_WFE_A_OFFSET_X_OFFSET) + +#define HW_PXP_WFE_A_SW_DATA_REGS (0x000016f0) + +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL3 24 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL3 0xFF000000 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL3(v) \ + (((v) << 24) & BM_PXP_WFE_A_SW_DATA_REGS_VAL3) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL2 16 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL2 0x00FF0000 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL2(v) \ + (((v) << 16) & BM_PXP_WFE_A_SW_DATA_REGS_VAL2) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL1 8 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL1 0x0000FF00 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL1(v) \ + (((v) << 8) & BM_PXP_WFE_A_SW_DATA_REGS_VAL1) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL0 0 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL0 0x000000FF +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_A_SW_DATA_REGS_VAL0) + +#define HW_PXP_WFE_A_SW_FLAG_REGS (0x00001700) + +#define BP_PXP_WFE_A_SW_FLAG_REGS_RSVD 4 +#define BM_PXP_WFE_A_SW_FLAG_REGS_RSVD 0xFFFFFFF0 +#define BF_PXP_WFE_A_SW_FLAG_REGS_RSVD(v) \ + (((v) << 4) & BM_PXP_WFE_A_SW_FLAG_REGS_RSVD) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL3 0x00000008 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL3(v) \ + (((v) << 3) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL3) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL2 0x00000004 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL2(v) \ + (((v) << 2) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL2) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL1 0x00000002 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL1(v) \ + (((v) << 1) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL1) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL0 0x00000001 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL0) + +#define HW_PXP_WFE_A_STAGE1_MUX0 (0x00001710) +#define HW_PXP_WFE_A_STAGE1_MUX0_SET (0x00001714) +#define HW_PXP_WFE_A_STAGE1_MUX0_CLR (0x00001718) +#define HW_PXP_WFE_A_STAGE1_MUX0_TOG (0x0000171c) + +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE1_MUX1 (0x00001720) +#define HW_PXP_WFE_A_STAGE1_MUX1_SET (0x00001724) +#define HW_PXP_WFE_A_STAGE1_MUX1_CLR (0x00001728) +#define HW_PXP_WFE_A_STAGE1_MUX1_TOG (0x0000172c) + +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX1_MUX7) +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__INC 0x0 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__DEC 0x1 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__ADD 0x2 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__AND 0x4 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__OR 0x5 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__XOR 0x6 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__NOP 0xc +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX1_MUX4) +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__INC 0x0 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__DEC 0x1 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__ADD 0x2 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__AND 0x4 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__OR 0x5 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__XOR 0x6 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__NOP 0xc + +#define HW_PXP_WFE_A_STAGE1_MUX2 (0x00001730) +#define HW_PXP_WFE_A_STAGE1_MUX2_SET (0x00001734) +#define HW_PXP_WFE_A_STAGE1_MUX2_CLR (0x00001738) +#define HW_PXP_WFE_A_STAGE1_MUX2_TOG (0x0000173c) + +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE1_MUX3 (0x00001740) +#define HW_PXP_WFE_A_STAGE1_MUX3_SET (0x00001744) +#define HW_PXP_WFE_A_STAGE1_MUX3_CLR (0x00001748) +#define HW_PXP_WFE_A_STAGE1_MUX3_TOG (0x0000174c) + +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX3_MUX12) + +#define HW_PXP_WFE_A_STAGE1_MUX4 (0x00001750) +#define HW_PXP_WFE_A_STAGE1_MUX4_SET (0x00001754) +#define HW_PXP_WFE_A_STAGE1_MUX4_CLR (0x00001758) +#define HW_PXP_WFE_A_STAGE1_MUX4_TOG (0x0000175c) + +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD0 24 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD0 0xFF000000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD1 16 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD1 0x00FF0000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD1(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX4_MUX17 8 +#define BM_PXP_WFE_A_STAGE1_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX4_MUX17) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX4_MUX16 0 +#define BM_PXP_WFE_A_STAGE1_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX4_MUX16) + +#define HW_PXP_WFE_A_STAGE2_MUX0 (0x00001760) +#define HW_PXP_WFE_A_STAGE2_MUX0_SET (0x00001764) +#define HW_PXP_WFE_A_STAGE2_MUX0_CLR (0x00001768) +#define HW_PXP_WFE_A_STAGE2_MUX0_TOG (0x0000176c) + +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE2_MUX1 (0x00001770) +#define HW_PXP_WFE_A_STAGE2_MUX1_SET (0x00001774) +#define HW_PXP_WFE_A_STAGE2_MUX1_CLR (0x00001778) +#define HW_PXP_WFE_A_STAGE2_MUX1_TOG (0x0000177c) + +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX1_MUX7) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX1_MUX4) + +#define HW_PXP_WFE_A_STAGE2_MUX2 (0x00001780) +#define HW_PXP_WFE_A_STAGE2_MUX2_SET (0x00001784) +#define HW_PXP_WFE_A_STAGE2_MUX2_CLR (0x00001788) +#define HW_PXP_WFE_A_STAGE2_MUX2_TOG (0x0000178c) + +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE2_MUX3 (0x00001790) +#define HW_PXP_WFE_A_STAGE2_MUX3_SET (0x00001794) +#define HW_PXP_WFE_A_STAGE2_MUX3_CLR (0x00001798) +#define HW_PXP_WFE_A_STAGE2_MUX3_TOG (0x0000179c) + +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX3_MUX12) + +#define HW_PXP_WFE_A_STAGE2_MUX4 (0x000017a0) +#define HW_PXP_WFE_A_STAGE2_MUX4_SET (0x000017a4) +#define HW_PXP_WFE_A_STAGE2_MUX4_CLR (0x000017a8) +#define HW_PXP_WFE_A_STAGE2_MUX4_TOG (0x000017ac) + +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX19 24 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX4_MUX19) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX18 16 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX4_MUX18) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX17 8 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX4_MUX17) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX16 0 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX4_MUX16) + +#define HW_PXP_WFE_A_STAGE2_MUX5 (0x000017b0) +#define HW_PXP_WFE_A_STAGE2_MUX5_SET (0x000017b4) +#define HW_PXP_WFE_A_STAGE2_MUX5_CLR (0x000017b8) +#define HW_PXP_WFE_A_STAGE2_MUX5_TOG (0x000017bc) + +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX23 24 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX5_MUX23) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX22 16 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX5_MUX22) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX21 8 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX5_MUX21) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX20 0 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX5_MUX20) + +#define HW_PXP_WFE_A_STAGE2_MUX6 (0x000017c0) +#define HW_PXP_WFE_A_STAGE2_MUX6_SET (0x000017c4) +#define HW_PXP_WFE_A_STAGE2_MUX6_CLR (0x000017c8) +#define HW_PXP_WFE_A_STAGE2_MUX6_TOG (0x000017cc) + +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX27 24 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX6_MUX27) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX26 16 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX6_MUX26) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX25 8 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX6_MUX25) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX24 0 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX6_MUX24) + +#define HW_PXP_WFE_A_STAGE2_MUX7 (0x000017d0) +#define HW_PXP_WFE_A_STAGE2_MUX7_SET (0x000017d4) +#define HW_PXP_WFE_A_STAGE2_MUX7_CLR (0x000017d8) +#define HW_PXP_WFE_A_STAGE2_MUX7_TOG (0x000017dc) + +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX31 24 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX7_MUX31) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX30 16 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX7_MUX30) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX29 8 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX7_MUX29) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX28 0 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX7_MUX28) + +#define HW_PXP_WFE_A_STAGE2_MUX8 (0x000017e0) +#define HW_PXP_WFE_A_STAGE2_MUX8_SET (0x000017e4) +#define HW_PXP_WFE_A_STAGE2_MUX8_CLR (0x000017e8) +#define HW_PXP_WFE_A_STAGE2_MUX8_TOG (0x000017ec) + +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX35 24 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX8_MUX35) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX34 16 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX8_MUX34) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX33 8 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX8_MUX33) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX32 0 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX8_MUX32) + +#define HW_PXP_WFE_A_STAGE2_MUX9 (0x000017f0) +#define HW_PXP_WFE_A_STAGE2_MUX9_SET (0x000017f4) +#define HW_PXP_WFE_A_STAGE2_MUX9_CLR (0x000017f8) +#define HW_PXP_WFE_A_STAGE2_MUX9_TOG (0x000017fc) + +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX39 24 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX9_MUX39) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX38 16 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX9_MUX38) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX37 8 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX9_MUX37) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX36 0 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX9_MUX36) + +#define HW_PXP_WFE_A_STAGE2_MUX10 (0x00001800) +#define HW_PXP_WFE_A_STAGE2_MUX10_SET (0x00001804) +#define HW_PXP_WFE_A_STAGE2_MUX10_CLR (0x00001808) +#define HW_PXP_WFE_A_STAGE2_MUX10_TOG (0x0000180c) + +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX43 24 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX10_MUX43) +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__INC 0x0 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__DEC 0x1 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__ADD 0x2 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__AND 0x4 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__OR 0x5 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__XOR 0x6 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__NOP 0xc +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX42 16 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX10_MUX42) +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX41 8 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX10_MUX41) +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX40 0 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX10_MUX40) +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__INC 0x0 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__DEC 0x1 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__ADD 0x2 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__AND 0x4 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__OR 0x5 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__XOR 0x6 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__NOP 0xc + +#define HW_PXP_WFE_A_STAGE2_MUX11 (0x00001810) +#define HW_PXP_WFE_A_STAGE2_MUX11_SET (0x00001814) +#define HW_PXP_WFE_A_STAGE2_MUX11_CLR (0x00001818) +#define HW_PXP_WFE_A_STAGE2_MUX11_TOG (0x0000181c) + +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX47 24 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX47 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX47(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX11_MUX47) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX46 16 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX46 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX46(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX11_MUX46) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX45 8 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX45 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX45(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX11_MUX45) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX44 0 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX44 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX44(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX11_MUX44) + +#define HW_PXP_WFE_A_STAGE2_MUX12 (0x00001820) +#define HW_PXP_WFE_A_STAGE2_MUX12_SET (0x00001824) +#define HW_PXP_WFE_A_STAGE2_MUX12_CLR (0x00001828) +#define HW_PXP_WFE_A_STAGE2_MUX12_TOG (0x0000182c) + +#define BP_PXP_WFE_A_STAGE2_MUX12_RSVD0 14 +#define BM_PXP_WFE_A_STAGE2_MUX12_RSVD0 0xFFFFC000 +#define BF_PXP_WFE_A_STAGE2_MUX12_RSVD0(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX12_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX12_MUX49 8 +#define BM_PXP_WFE_A_STAGE2_MUX12_MUX49 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX12_MUX49(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX12_MUX49) +#define BP_PXP_WFE_A_STAGE2_MUX12_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX12_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX12_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX12_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX12_MUX48 0 +#define BM_PXP_WFE_A_STAGE2_MUX12_MUX48 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX12_MUX48(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX12_MUX48) + +#define HW_PXP_WFE_A_STAGE3_MUX0 (0x00001830) +#define HW_PXP_WFE_A_STAGE3_MUX0_SET (0x00001834) +#define HW_PXP_WFE_A_STAGE3_MUX0_CLR (0x00001838) +#define HW_PXP_WFE_A_STAGE3_MUX0_TOG (0x0000183c) + +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE3_MUX1 (0x00001840) +#define HW_PXP_WFE_A_STAGE3_MUX1_SET (0x00001844) +#define HW_PXP_WFE_A_STAGE3_MUX1_CLR (0x00001848) +#define HW_PXP_WFE_A_STAGE3_MUX1_TOG (0x0000184c) + +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX1_MUX7) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX1_MUX4) + +#define HW_PXP_WFE_A_STAGE3_MUX2 (0x00001850) +#define HW_PXP_WFE_A_STAGE3_MUX2_SET (0x00001854) +#define HW_PXP_WFE_A_STAGE3_MUX2_CLR (0x00001858) +#define HW_PXP_WFE_A_STAGE3_MUX2_TOG (0x0000185c) + +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE3_MUX3 (0x00001860) +#define HW_PXP_WFE_A_STAGE3_MUX3_SET (0x00001864) +#define HW_PXP_WFE_A_STAGE3_MUX3_CLR (0x00001868) +#define HW_PXP_WFE_A_STAGE3_MUX3_TOG (0x0000186c) + +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX3_MUX12) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_0 (0x00001870) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_1 (0x00001880) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_2 (0x00001890) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_3 (0x000018a0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_4 (0x000018b0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_5 (0x000018c0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_6 (0x000018d0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_7 (0x000018e0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_0 (0x000018f0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_1 (0x00001900) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_2 (0x00001910) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_3 (0x00001920) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_4 (0x00001930) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_5 (0x00001940) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_6 (0x00001950) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_7 (0x00001960) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_0 (0x00001970) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_1 (0x00001980) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_2 (0x00001990) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_3 (0x000019a0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_4 (0x000019b0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_5 (0x000019c0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_6 (0x000019d0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_7 (0x000019e0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_0 (0x000019f0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_1 (0x00001a00) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_2 (0x00001a10) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_3 (0x00001a20) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_4 (0x00001a30) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_5 (0x00001a40) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_6 (0x00001a50) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_7 (0x00001a60) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_0 (0x00001a70) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_1 (0x00001a80) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_2 (0x00001a90) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_3 (0x00001aa0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_4 (0x00001ab0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_5 (0x00001ac0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_6 (0x00001ad0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_7 (0x00001ae0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_0 (0x00001af0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_1 (0x00001b00) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_2 (0x00001b10) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_3 (0x00001b20) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_4 (0x00001b30) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_5 (0x00001b40) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_6 (0x00001b50) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_7 (0x00001b60) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_0 (0x00001b70) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_1 (0x00001b80) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_2 (0x00001b90) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_3 (0x00001ba0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_4 (0x00001bb0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_5 (0x00001bc0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_6 (0x00001bd0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_7 (0x00001be0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_0 (0x00001bf0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_1 (0x00001c00) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_2 (0x00001c10) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_3 (0x00001c20) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_4 (0x00001c30) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_5 (0x00001c40) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_6 (0x00001c50) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_7 (0x00001c60) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28) + +#define HW_PXP_WFE_A_STAGE2_5X6_MASKS_0 (0x00001c70) + +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0 29 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0 0xE0000000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0(v) \ + (((v) << 29) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3 24 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3 0x1F000000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1 21 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1 0x00E00000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1(v) \ + (((v) << 21) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2 16 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2 0x001F0000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2 13 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2 0x0000E000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2(v) \ + (((v) << 13) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1 8 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3 5 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3 0x000000E0 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3(v) \ + (((v) << 5) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0 0 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0) + +#define HW_PXP_WFE_A_STAGE2_5X6_ADDR_0 (0x00001c80) + +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3 24 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2 16 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1 8 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0 0 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0 0x0000003F +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT0 (0x00001c90) + +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT1 (0x00001ca0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT2 (0x00001cb0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT3 (0x00001cc0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_MASKS (0x00001cd0) + +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD3 29 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD3 0xE0000000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD3) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK3 24 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK3 0x1F000000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK3) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD2 21 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD2 0x00E00000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD2) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK2 16 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK2 0x001F0000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK2) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD1 13 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD1 0x0000E000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD1) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK1 8 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK1 0x00001F00 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK1) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD0 0x000000E0 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_CTRL (0x00001d00) +#define HW_PXP_WFE_B_CTRL_SET (0x00001d04) +#define HW_PXP_WFE_B_CTRL_CLR (0x00001d08) +#define HW_PXP_WFE_B_CTRL_TOG (0x00001d0c) + +#define BM_PXP_WFE_B_CTRL_DONE 0x80000000 +#define BF_PXP_WFE_B_CTRL_DONE(v) \ + (((v) << 31) & BM_PXP_WFE_B_CTRL_DONE) +#define BP_PXP_WFE_B_CTRL_RSVD0 3 +#define BM_PXP_WFE_B_CTRL_RSVD0 0x7FFFFFF8 +#define BF_PXP_WFE_B_CTRL_RSVD0(v) \ + (((v) << 3) & BM_PXP_WFE_B_CTRL_RSVD0) +#define BM_PXP_WFE_B_CTRL_SW_RESET 0x00000004 +#define BF_PXP_WFE_B_CTRL_SW_RESET(v) \ + (((v) << 2) & BM_PXP_WFE_B_CTRL_SW_RESET) +#define BM_PXP_WFE_B_CTRL_RSVD1 0x00000002 +#define BF_PXP_WFE_B_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_WFE_B_CTRL_RSVD1) +#define BM_PXP_WFE_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_WFE_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_WFE_B_CTRL_ENABLE) +#define BV_PXP_WFE_B_CTRL_ENABLE__0 0x0 +#define BV_PXP_WFE_B_CTRL_ENABLE__1 0x1 + +#define HW_PXP_WFE_B_DIMENSIONS (0x00001d10) + +#define BP_PXP_WFE_B_DIMENSIONS_RSVD0 28 +#define BM_PXP_WFE_B_DIMENSIONS_RSVD0 0xF0000000 +#define BF_PXP_WFE_B_DIMENSIONS_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_B_DIMENSIONS_RSVD0) +#define BP_PXP_WFE_B_DIMENSIONS_HEIGHT 16 +#define BM_PXP_WFE_B_DIMENSIONS_HEIGHT 0x0FFF0000 +#define BF_PXP_WFE_B_DIMENSIONS_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_DIMENSIONS_HEIGHT) +#define BP_PXP_WFE_B_DIMENSIONS_RSVD1 12 +#define BM_PXP_WFE_B_DIMENSIONS_RSVD1 0x0000F000 +#define BF_PXP_WFE_B_DIMENSIONS_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_B_DIMENSIONS_RSVD1) +#define BP_PXP_WFE_B_DIMENSIONS_WIDTH 0 +#define BM_PXP_WFE_B_DIMENSIONS_WIDTH 0x00000FFF +#define BF_PXP_WFE_B_DIMENSIONS_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_DIMENSIONS_WIDTH) + +#define HW_PXP_WFE_B_OFFSET (0x00001d20) + +#define BP_PXP_WFE_B_OFFSET_RSVD0 28 +#define BM_PXP_WFE_B_OFFSET_RSVD0 0xF0000000 +#define BF_PXP_WFE_B_OFFSET_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_B_OFFSET_RSVD0) +#define BP_PXP_WFE_B_OFFSET_Y_OFFSET 16 +#define BM_PXP_WFE_B_OFFSET_Y_OFFSET 0x0FFF0000 +#define BF_PXP_WFE_B_OFFSET_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_WFE_B_OFFSET_Y_OFFSET) +#define BP_PXP_WFE_B_OFFSET_RSVD1 12 +#define BM_PXP_WFE_B_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_WFE_B_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_B_OFFSET_RSVD1) +#define BP_PXP_WFE_B_OFFSET_X_OFFSET 0 +#define BM_PXP_WFE_B_OFFSET_X_OFFSET 0x00000FFF +#define BF_PXP_WFE_B_OFFSET_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_WFE_B_OFFSET_X_OFFSET) + +#define HW_PXP_WFE_B_SW_DATA_REGS (0x00001d30) + +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL3 24 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL3 0xFF000000 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL3(v) \ + (((v) << 24) & BM_PXP_WFE_B_SW_DATA_REGS_VAL3) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL2 16 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL2 0x00FF0000 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL2(v) \ + (((v) << 16) & BM_PXP_WFE_B_SW_DATA_REGS_VAL2) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL1 8 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL1 0x0000FF00 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL1(v) \ + (((v) << 8) & BM_PXP_WFE_B_SW_DATA_REGS_VAL1) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL0 0 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL0 0x000000FF +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_B_SW_DATA_REGS_VAL0) + +#define HW_PXP_WFE_B_SW_FLAG_REGS (0x00001d40) + +#define BP_PXP_WFE_B_SW_FLAG_REGS_RSVD 4 +#define BM_PXP_WFE_B_SW_FLAG_REGS_RSVD 0xFFFFFFF0 +#define BF_PXP_WFE_B_SW_FLAG_REGS_RSVD(v) \ + (((v) << 4) & BM_PXP_WFE_B_SW_FLAG_REGS_RSVD) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL3 0x00000008 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL3(v) \ + (((v) << 3) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL3) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL2 0x00000004 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL2(v) \ + (((v) << 2) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL2) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL1 0x00000002 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL1(v) \ + (((v) << 1) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL1) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL0 0x00000001 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL0) + +#define HW_PXP_WFE_B_STAGE1_MUX0 (0x00001d50) +#define HW_PXP_WFE_B_STAGE1_MUX0_SET (0x00001d54) +#define HW_PXP_WFE_B_STAGE1_MUX0_CLR (0x00001d58) +#define HW_PXP_WFE_B_STAGE1_MUX0_TOG (0x00001d5c) + +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE1_MUX1 (0x00001d60) +#define HW_PXP_WFE_B_STAGE1_MUX1_SET (0x00001d64) +#define HW_PXP_WFE_B_STAGE1_MUX1_CLR (0x00001d68) +#define HW_PXP_WFE_B_STAGE1_MUX1_TOG (0x00001d6c) + +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE1_MUX2 (0x00001d70) +#define HW_PXP_WFE_B_STAGE1_MUX2_SET (0x00001d74) +#define HW_PXP_WFE_B_STAGE1_MUX2_CLR (0x00001d78) +#define HW_PXP_WFE_B_STAGE1_MUX2_TOG (0x00001d7c) + +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE1_MUX3 (0x00001d80) +#define HW_PXP_WFE_B_STAGE1_MUX3_SET (0x00001d84) +#define HW_PXP_WFE_B_STAGE1_MUX3_CLR (0x00001d88) +#define HW_PXP_WFE_B_STAGE1_MUX3_TOG (0x00001d8c) + +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE1_MUX4 (0x00001d90) +#define HW_PXP_WFE_B_STAGE1_MUX4_SET (0x00001d94) +#define HW_PXP_WFE_B_STAGE1_MUX4_CLR (0x00001d98) +#define HW_PXP_WFE_B_STAGE1_MUX4_TOG (0x00001d9c) + +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE1_MUX5 (0x00001da0) +#define HW_PXP_WFE_B_STAGE1_MUX5_SET (0x00001da4) +#define HW_PXP_WFE_B_STAGE1_MUX5_CLR (0x00001da8) +#define HW_PXP_WFE_B_STAGE1_MUX5_TOG (0x00001dac) + +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX5_MUX20) +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__INC 0x0 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__DEC 0x1 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__ADD 0x2 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__MINUS 0x3 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__AND 0x4 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__OR 0x5 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__XOR 0x6 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__SHIFTLEFT 0x7 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_AND 0x9 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_OR 0xa +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_CMP 0xb +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__NOP 0xc + +#define HW_PXP_WFE_B_STAGE1_MUX6 (0x00001db0) +#define HW_PXP_WFE_B_STAGE1_MUX6_SET (0x00001db4) +#define HW_PXP_WFE_B_STAGE1_MUX6_CLR (0x00001db8) +#define HW_PXP_WFE_B_STAGE1_MUX6_TOG (0x00001dbc) + +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE1_MUX7 (0x00001dc0) +#define HW_PXP_WFE_B_STAGE1_MUX7_SET (0x00001dc4) +#define HW_PXP_WFE_B_STAGE1_MUX7_CLR (0x00001dc8) +#define HW_PXP_WFE_B_STAGE1_MUX7_TOG (0x00001dcc) + +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE1_MUX8 (0x00001dd0) +#define HW_PXP_WFE_B_STAGE1_MUX8_SET (0x00001dd4) +#define HW_PXP_WFE_B_STAGE1_MUX8_CLR (0x00001dd8) +#define HW_PXP_WFE_B_STAGE1_MUX8_TOG (0x00001ddc) + +#define BP_PXP_WFE_B_STAGE1_MUX8_RSVD0 6 +#define BM_PXP_WFE_B_STAGE1_MUX8_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STAGE1_MUX8_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE1_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE2_MUX0 (0x00001de0) +#define HW_PXP_WFE_B_STAGE2_MUX0_SET (0x00001de4) +#define HW_PXP_WFE_B_STAGE2_MUX0_CLR (0x00001de8) +#define HW_PXP_WFE_B_STAGE2_MUX0_TOG (0x00001dec) + +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE2_MUX1 (0x00001df0) +#define HW_PXP_WFE_B_STAGE2_MUX1_SET (0x00001df4) +#define HW_PXP_WFE_B_STAGE2_MUX1_CLR (0x00001df8) +#define HW_PXP_WFE_B_STAGE2_MUX1_TOG (0x00001dfc) + +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE2_MUX2 (0x00001e00) +#define HW_PXP_WFE_B_STAGE2_MUX2_SET (0x00001e04) +#define HW_PXP_WFE_B_STAGE2_MUX2_CLR (0x00001e08) +#define HW_PXP_WFE_B_STAGE2_MUX2_TOG (0x00001e0c) + +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE2_MUX3 (0x00001e10) +#define HW_PXP_WFE_B_STAGE2_MUX3_SET (0x00001e14) +#define HW_PXP_WFE_B_STAGE2_MUX3_CLR (0x00001e18) +#define HW_PXP_WFE_B_STAGE2_MUX3_TOG (0x00001e1c) + +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE2_MUX4 (0x00001e20) +#define HW_PXP_WFE_B_STAGE2_MUX4_SET (0x00001e24) +#define HW_PXP_WFE_B_STAGE2_MUX4_CLR (0x00001e28) +#define HW_PXP_WFE_B_STAGE2_MUX4_TOG (0x00001e2c) + +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE2_MUX5 (0x00001e30) +#define HW_PXP_WFE_B_STAGE2_MUX5_SET (0x00001e34) +#define HW_PXP_WFE_B_STAGE2_MUX5_CLR (0x00001e38) +#define HW_PXP_WFE_B_STAGE2_MUX5_TOG (0x00001e3c) + +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX5_MUX20) + +#define HW_PXP_WFE_B_STAGE2_MUX6 (0x00001e40) +#define HW_PXP_WFE_B_STAGE2_MUX6_SET (0x00001e44) +#define HW_PXP_WFE_B_STAGE2_MUX6_CLR (0x00001e48) +#define HW_PXP_WFE_B_STAGE2_MUX6_TOG (0x00001e4c) + +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE2_MUX7 (0x00001e50) +#define HW_PXP_WFE_B_STAGE2_MUX7_SET (0x00001e54) +#define HW_PXP_WFE_B_STAGE2_MUX7_CLR (0x00001e58) +#define HW_PXP_WFE_B_STAGE2_MUX7_TOG (0x00001e5c) + +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE2_MUX8 (0x00001e60) +#define HW_PXP_WFE_B_STAGE2_MUX8_SET (0x00001e64) +#define HW_PXP_WFE_B_STAGE2_MUX8_CLR (0x00001e68) +#define HW_PXP_WFE_B_STAGE2_MUX8_TOG (0x00001e6c) + +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX35 24 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX8_MUX35) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX34 16 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX8_MUX34) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX33 8 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX8_MUX33) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE2_MUX9 (0x00001e70) +#define HW_PXP_WFE_B_STAGE2_MUX9_SET (0x00001e74) +#define HW_PXP_WFE_B_STAGE2_MUX9_CLR (0x00001e78) +#define HW_PXP_WFE_B_STAGE2_MUX9_TOG (0x00001e7c) + +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX39 24 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX9_MUX39) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX38 16 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX9_MUX38) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX37 8 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX9_MUX37) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX36 0 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX9_MUX36) + +#define HW_PXP_WFE_B_STAGE2_MUX10 (0x00001e80) +#define HW_PXP_WFE_B_STAGE2_MUX10_SET (0x00001e84) +#define HW_PXP_WFE_B_STAGE2_MUX10_CLR (0x00001e88) +#define HW_PXP_WFE_B_STAGE2_MUX10_TOG (0x00001e8c) + +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX43 24 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX10_MUX43) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX42 16 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX10_MUX42) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX41 8 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX10_MUX41) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX40 0 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX10_MUX40) +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__INC 0x0 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__DEC 0x1 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__ADD 0x2 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__MINUS 0x3 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__AND 0x4 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__OR 0x5 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__XOR 0x6 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__SHIFTLEFT 0x7 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_AND 0x9 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_OR 0xa +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_CMP 0xb +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__NOP 0xc + +#define HW_PXP_WFE_B_STAGE2_MUX11 (0x00001e90) +#define HW_PXP_WFE_B_STAGE2_MUX11_SET (0x00001e94) +#define HW_PXP_WFE_B_STAGE2_MUX11_CLR (0x00001e98) +#define HW_PXP_WFE_B_STAGE2_MUX11_TOG (0x00001e9c) + +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX47 24 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX47 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX47(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX11_MUX47) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX46 16 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX46 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX46(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX11_MUX46) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX45 8 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX45 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX45(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX11_MUX45) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX44 0 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX44 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX44(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX11_MUX44) + +#define HW_PXP_WFE_B_STAGE2_MUX12 (0x00001ea0) +#define HW_PXP_WFE_B_STAGE2_MUX12_SET (0x00001ea4) +#define HW_PXP_WFE_B_STAGE2_MUX12_CLR (0x00001ea8) +#define HW_PXP_WFE_B_STAGE2_MUX12_TOG (0x00001eac) + +#define BP_PXP_WFE_B_STAGE2_MUX12_RSVD0 6 +#define BM_PXP_WFE_B_STAGE2_MUX12_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STAGE2_MUX12_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX12_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX12_MUX48 0 +#define BM_PXP_WFE_B_STAGE2_MUX12_MUX48 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX12_MUX48(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX12_MUX48) + +#define HW_PXP_WFE_B_STAGE3_MUX0 (0x00001eb0) +#define HW_PXP_WFE_B_STAGE3_MUX0_SET (0x00001eb4) +#define HW_PXP_WFE_B_STAGE3_MUX0_CLR (0x00001eb8) +#define HW_PXP_WFE_B_STAGE3_MUX0_TOG (0x00001ebc) + +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE3_MUX1 (0x00001ec0) +#define HW_PXP_WFE_B_STAGE3_MUX1_SET (0x00001ec4) +#define HW_PXP_WFE_B_STAGE3_MUX1_CLR (0x00001ec8) +#define HW_PXP_WFE_B_STAGE3_MUX1_TOG (0x00001ecc) + +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE3_MUX2 (0x00001ed0) +#define HW_PXP_WFE_B_STAGE3_MUX2_SET (0x00001ed4) +#define HW_PXP_WFE_B_STAGE3_MUX2_CLR (0x00001ed8) +#define HW_PXP_WFE_B_STAGE3_MUX2_TOG (0x00001edc) + +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE3_MUX3 (0x00001ee0) +#define HW_PXP_WFE_B_STAGE3_MUX3_SET (0x00001ee4) +#define HW_PXP_WFE_B_STAGE3_MUX3_CLR (0x00001ee8) +#define HW_PXP_WFE_B_STAGE3_MUX3_TOG (0x00001eec) + +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE3_MUX4 (0x00001ef0) +#define HW_PXP_WFE_B_STAGE3_MUX4_SET (0x00001ef4) +#define HW_PXP_WFE_B_STAGE3_MUX4_CLR (0x00001ef8) +#define HW_PXP_WFE_B_STAGE3_MUX4_TOG (0x00001efc) + +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE3_MUX5 (0x00001f00) +#define HW_PXP_WFE_B_STAGE3_MUX5_SET (0x00001f04) +#define HW_PXP_WFE_B_STAGE3_MUX5_CLR (0x00001f08) +#define HW_PXP_WFE_B_STAGE3_MUX5_TOG (0x00001f0c) + +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX5_MUX20) + +#define HW_PXP_WFE_B_STAGE3_MUX6 (0x00001f10) +#define HW_PXP_WFE_B_STAGE3_MUX6_SET (0x00001f14) +#define HW_PXP_WFE_B_STAGE3_MUX6_CLR (0x00001f18) +#define HW_PXP_WFE_B_STAGE3_MUX6_TOG (0x00001f1c) + +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE3_MUX7 (0x00001f20) +#define HW_PXP_WFE_B_STAGE3_MUX7_SET (0x00001f24) +#define HW_PXP_WFE_B_STAGE3_MUX7_CLR (0x00001f28) +#define HW_PXP_WFE_B_STAGE3_MUX7_TOG (0x00001f2c) + +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE3_MUX8 (0x00001f30) +#define HW_PXP_WFE_B_STAGE3_MUX8_SET (0x00001f34) +#define HW_PXP_WFE_B_STAGE3_MUX8_CLR (0x00001f38) +#define HW_PXP_WFE_B_STAGE3_MUX8_TOG (0x00001f3c) + +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX35 24 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX8_MUX35) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX34 16 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX8_MUX34) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX33 8 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX8_MUX33) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE3_MUX9 (0x00001f40) +#define HW_PXP_WFE_B_STAGE3_MUX9_SET (0x00001f44) +#define HW_PXP_WFE_B_STAGE3_MUX9_CLR (0x00001f48) +#define HW_PXP_WFE_B_STAGE3_MUX9_TOG (0x00001f4c) + +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX39 24 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX9_MUX39) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX38 16 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX9_MUX38) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX37 8 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX9_MUX37) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX36 0 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX9_MUX36) + +#define HW_PXP_WFE_B_STAGE3_MUX10 (0x00001f50) +#define HW_PXP_WFE_B_STAGE3_MUX10_SET (0x00001f54) +#define HW_PXP_WFE_B_STAGE3_MUX10_CLR (0x00001f58) +#define HW_PXP_WFE_B_STAGE3_MUX10_TOG (0x00001f5c) + +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX43 24 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX10_MUX43) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX42 16 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX10_MUX42) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX41 8 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX10_MUX41) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX40 0 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX10_MUX40) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_0 (0x00001f60) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_1 (0x00001f70) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_2 (0x00001f80) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_3 (0x00001f90) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_4 (0x00001fa0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_5 (0x00001fb0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_6 (0x00001fc0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_7 (0x00001fd0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_0 (0x00001fe0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_1 (0x00001ff0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_2 (0x00002000) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_3 (0x00002010) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_4 (0x00002020) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_5 (0x00002030) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_6 (0x00002040) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_7 (0x00002050) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_B_STAGE1_5X8_MASKS_0 (0x00002060) + +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2 13 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2 0xFFFFE000 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2(v) \ + (((v) << 13) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1 8 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3 5 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3 0x000000E0 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3(v) \ + (((v) << 5) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0 0 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0) + +#define HW_PXP_WFE_B_STG1_5X1_OUT0 (0x00002070) + +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X1_MASKS (0x00002080) + +#define BP_PXP_WFE_B_STG1_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_B_STG1_5X1_MASKS_RSVD0 0xFFFFFFE0 +#define BF_PXP_WFE_B_STG1_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_B_STG1_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG1_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_B_STG1_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_0 (0x00002090) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_1 (0x000020a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_2 (0x000020b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_3 (0x000020c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_4 (0x000020d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_5 (0x000020e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_6 (0x000020f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_7 (0x00002100) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_0 (0x00002110) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_1 (0x00002120) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_2 (0x00002130) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_3 (0x00002140) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_4 (0x00002150) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_5 (0x00002160) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_6 (0x00002170) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_7 (0x00002180) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_0 (0x00002190) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_1 (0x000021a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_2 (0x000021b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_3 (0x000021c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_4 (0x000021d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_5 (0x000021e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_6 (0x000021f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_7 (0x00002200) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_0 (0x00002210) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_1 (0x00002220) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_2 (0x00002230) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_3 (0x00002240) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_4 (0x00002250) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_5 (0x00002260) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_6 (0x00002270) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_7 (0x00002280) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_0 (0x00002290) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_1 (0x000022a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_2 (0x000022b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_3 (0x000022c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_4 (0x000022d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_5 (0x000022e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_6 (0x000022f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_7 (0x00002300) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_0 (0x00002310) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_1 (0x00002320) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_2 (0x00002330) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_3 (0x00002340) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_4 (0x00002350) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_5 (0x00002360) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_6 (0x00002370) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_7 (0x00002380) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_0 (0x00002390) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_1 (0x000023a0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_2 (0x000023b0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_3 (0x000023c0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_4 (0x000023d0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_5 (0x000023e0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_6 (0x000023f0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_7 (0x00002400) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_0 (0x00002410) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_1 (0x00002420) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_2 (0x00002430) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_3 (0x00002440) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_4 (0x00002450) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_5 (0x00002460) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_6 (0x00002470) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_7 (0x00002480) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_0 (0x00002490) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_1 (0x000024a0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_2 (0x000024b0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_3 (0x000024c0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_4 (0x000024e0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_5 (0x000024f0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_6 (0x00002500) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_7 (0x00002510) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28) + +#define HW_PXP_WFE_B_STAGE2_5X6_MASKS_0 (0x00002520) + +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3 29 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3 0xE0000000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3 24 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3 0x1F000000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2 21 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2 0x00E00000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2 16 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2 0x001F0000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1 13 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1 0x0000E000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1 8 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0 5 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0 0x000000E0 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0 0 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0) + +#define HW_PXP_WFE_B_STAGE2_5X6_ADDR_0 (0x00002530) + +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3 30 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3 24 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2 22 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2 16 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1 14 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1 8 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0 6 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0 0 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0 0x0000003F +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT0 (0x00002540) + +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT1 (0x00002550) + +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT2 (0x00002560) + +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT3 (0x00002570) + +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_MASKS (0x00002580) + +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD3 29 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD3 0xE0000000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD3) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK3 24 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK3 0x1F000000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK3) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD2 21 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD2 0x00E00000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD2) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK2 16 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK2 0x001F0000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK2) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD1 13 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD1 0x0000E000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD1) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK1 8 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK1) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD0 0x000000E0 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_0 (0x00002590) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_1 (0x000025a0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_2 (0x000025b0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_3 (0x000025c0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_4 (0x000025d0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_5 (0x000025e0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_6 (0x000025f0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_7 (0x00002600) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_0 (0x00002610) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_1 (0x00002620) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_2 (0x00002630) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_3 (0x00002640) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_4 (0x00002650) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_5 (0x00002660) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_6 (0x00002670) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_7 (0x00002680) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_0 (0x00002690) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_1 (0x000026a0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_2 (0x000026b0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_3 (0x000026c0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_4 (0x000026d0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_5 (0x000026e0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_6 (0x000026f0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_7 (0x00002700) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_0 (0x00002710) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_1 (0x00002720) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_2 (0x00002730) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_3 (0x00002740) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_4 (0x00002750) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_5 (0x00002760) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_6 (0x00002770) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_7 (0x00002780) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_MASKS (0x00002790) + +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK3 24 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK3 0xFF000000 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK3) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK2 16 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK2 0x00FF0000 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK2) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK1 8 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK1 0x0000FF00 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK1) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK0 0x000000FF +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK0) + +#define HW_PXP_ALU_A_CTRL (0x00002810) +#define HW_PXP_ALU_A_CTRL_SET (0x00002814) +#define HW_PXP_ALU_A_CTRL_CLR (0x00002818) +#define HW_PXP_ALU_A_CTRL_TOG (0x0000281c) + +#define BP_PXP_ALU_A_CTRL_RSVD0 29 +#define BM_PXP_ALU_A_CTRL_RSVD0 0xE0000000 +#define BF_PXP_ALU_A_CTRL_RSVD0(v) \ + (((v) << 29) & BM_PXP_ALU_A_CTRL_RSVD0) +#define BM_PXP_ALU_A_CTRL_DONE 0x10000000 +#define BF_PXP_ALU_A_CTRL_DONE(v) \ + (((v) << 28) & BM_PXP_ALU_A_CTRL_DONE) +#define BP_PXP_ALU_A_CTRL_RSVD1 21 +#define BM_PXP_ALU_A_CTRL_RSVD1 0x0FE00000 +#define BF_PXP_ALU_A_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_ALU_A_CTRL_RSVD1) +#define BM_PXP_ALU_A_CTRL_DONE_IRQ_EN 0x00100000 +#define BF_PXP_ALU_A_CTRL_DONE_IRQ_EN(v) \ + (((v) << 20) & BM_PXP_ALU_A_CTRL_DONE_IRQ_EN) +#define BP_PXP_ALU_A_CTRL_RSVD2 17 +#define BM_PXP_ALU_A_CTRL_RSVD2 0x000E0000 +#define BF_PXP_ALU_A_CTRL_RSVD2(v) \ + (((v) << 17) & BM_PXP_ALU_A_CTRL_RSVD2) +#define BM_PXP_ALU_A_CTRL_DONE_IRQ_FLAG 0x00010000 +#define BF_PXP_ALU_A_CTRL_DONE_IRQ_FLAG(v) \ + (((v) << 16) & BM_PXP_ALU_A_CTRL_DONE_IRQ_FLAG) +#define BP_PXP_ALU_A_CTRL_RSVD3 13 +#define BM_PXP_ALU_A_CTRL_RSVD3 0x0000E000 +#define BF_PXP_ALU_A_CTRL_RSVD3(v) \ + (((v) << 13) & BM_PXP_ALU_A_CTRL_RSVD3) +#define BM_PXP_ALU_A_CTRL_BYPASS 0x00001000 +#define BF_PXP_ALU_A_CTRL_BYPASS(v) \ + (((v) << 12) & BM_PXP_ALU_A_CTRL_BYPASS) +#define BV_PXP_ALU_A_CTRL_BYPASS__0 0x0 +#define BV_PXP_ALU_A_CTRL_BYPASS__1 0x1 +#define BP_PXP_ALU_A_CTRL_RSVD4 9 +#define BM_PXP_ALU_A_CTRL_RSVD4 0x00000E00 +#define BF_PXP_ALU_A_CTRL_RSVD4(v) \ + (((v) << 9) & BM_PXP_ALU_A_CTRL_RSVD4) +#define BM_PXP_ALU_A_CTRL_SW_RESET 0x00000100 +#define BF_PXP_ALU_A_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_ALU_A_CTRL_SW_RESET) +#define BP_PXP_ALU_A_CTRL_RSVD5 5 +#define BM_PXP_ALU_A_CTRL_RSVD5 0x000000E0 +#define BF_PXP_ALU_A_CTRL_RSVD5(v) \ + (((v) << 5) & BM_PXP_ALU_A_CTRL_RSVD5) +#define BM_PXP_ALU_A_CTRL_START 0x00000010 +#define BF_PXP_ALU_A_CTRL_START(v) \ + (((v) << 4) & BM_PXP_ALU_A_CTRL_START) +#define BP_PXP_ALU_A_CTRL_RSVD6 1 +#define BM_PXP_ALU_A_CTRL_RSVD6 0x0000000E +#define BF_PXP_ALU_A_CTRL_RSVD6(v) \ + (((v) << 1) & BM_PXP_ALU_A_CTRL_RSVD6) +#define BM_PXP_ALU_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_ALU_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALU_A_CTRL_ENABLE) +#define BV_PXP_ALU_A_CTRL_ENABLE__0 0x0 +#define BV_PXP_ALU_A_CTRL_ENABLE__1 0x1 + +#define HW_PXP_ALU_A_BUF_SIZE (0x00002820) + +#define BP_PXP_ALU_A_BUF_SIZE_RSVD0 28 +#define BM_PXP_ALU_A_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_ALU_A_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_ALU_A_BUF_SIZE_RSVD0) +#define BP_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT 16 +#define BM_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT 0x0FFF0000 +#define BF_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT) +#define BP_PXP_ALU_A_BUF_SIZE_RSVD1 12 +#define BM_PXP_ALU_A_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_ALU_A_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_ALU_A_BUF_SIZE_RSVD1) +#define BP_PXP_ALU_A_BUF_SIZE_BUF_WIDTH 0 +#define BM_PXP_ALU_A_BUF_SIZE_BUF_WIDTH 0x00000FFF +#define BF_PXP_ALU_A_BUF_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_ALU_A_BUF_SIZE_BUF_WIDTH) + +#define HW_PXP_ALU_A_INST_ENTRY (0x00002830) + +#define BP_PXP_ALU_A_INST_ENTRY_RSVD0 16 +#define BM_PXP_ALU_A_INST_ENTRY_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_A_INST_ENTRY_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_A_INST_ENTRY_RSVD0) +#define BP_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR 0 +#define BM_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR 0x0000FFFF +#define BF_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR(v) \ + (((v) << 0) & BM_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR) + +#define HW_PXP_ALU_A_PARAM (0x00002840) + +#define BP_PXP_ALU_A_PARAM_RSVD0 16 +#define BM_PXP_ALU_A_PARAM_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_A_PARAM_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_A_PARAM_RSVD0) +#define BP_PXP_ALU_A_PARAM_PARAM1 8 +#define BM_PXP_ALU_A_PARAM_PARAM1 0x0000FF00 +#define BF_PXP_ALU_A_PARAM_PARAM1(v) \ + (((v) << 8) & BM_PXP_ALU_A_PARAM_PARAM1) +#define BP_PXP_ALU_A_PARAM_PARAM0 0 +#define BM_PXP_ALU_A_PARAM_PARAM0 0x000000FF +#define BF_PXP_ALU_A_PARAM_PARAM0(v) \ + (((v) << 0) & BM_PXP_ALU_A_PARAM_PARAM0) + +#define HW_PXP_ALU_A_CONFIG (0x00002850) + +#define BP_PXP_ALU_A_CONFIG_BUF_ADDR 0 +#define BM_PXP_ALU_A_CONFIG_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_ALU_A_CONFIG_BUF_ADDR(v) (v) + +#define HW_PXP_ALU_A_LUT_CONFIG (0x00002860) +#define HW_PXP_ALU_A_LUT_CONFIG_SET (0x00002864) +#define HW_PXP_ALU_A_LUT_CONFIG_CLR (0x00002868) +#define HW_PXP_ALU_A_LUT_CONFIG_TOG (0x0000286c) + +#define BP_PXP_ALU_A_LUT_CONFIG_RSVD0 6 +#define BM_PXP_ALU_A_LUT_CONFIG_RSVD0 0xFFFFFFC0 +#define BF_PXP_ALU_A_LUT_CONFIG_RSVD0(v) \ + (((v) << 6) & BM_PXP_ALU_A_LUT_CONFIG_RSVD0) +#define BP_PXP_ALU_A_LUT_CONFIG_MODE 4 +#define BM_PXP_ALU_A_LUT_CONFIG_MODE 0x00000030 +#define BF_PXP_ALU_A_LUT_CONFIG_MODE(v) \ + (((v) << 4) & BM_PXP_ALU_A_LUT_CONFIG_MODE) +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__0 0x0 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__1 0x1 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__2 0x2 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__3 0x3 +#define BP_PXP_ALU_A_LUT_CONFIG_RSVD1 1 +#define BM_PXP_ALU_A_LUT_CONFIG_RSVD1 0x0000000E +#define BF_PXP_ALU_A_LUT_CONFIG_RSVD1(v) \ + (((v) << 1) & BM_PXP_ALU_A_LUT_CONFIG_RSVD1) +#define BM_PXP_ALU_A_LUT_CONFIG_EN 0x00000001 +#define BF_PXP_ALU_A_LUT_CONFIG_EN(v) \ + (((v) << 0) & BM_PXP_ALU_A_LUT_CONFIG_EN) + +#define HW_PXP_ALU_A_LUT_DATA0 (0x00002870) + +#define BP_PXP_ALU_A_LUT_DATA0_LUT_DATA_L 0 +#define BM_PXP_ALU_A_LUT_DATA0_LUT_DATA_L 0xFFFFFFFF +#define BF_PXP_ALU_A_LUT_DATA0_LUT_DATA_L(v) (v) + +#define HW_PXP_ALU_A_LUT_DATA1 (0x00002880) + +#define BP_PXP_ALU_A_LUT_DATA1_LUT_DATA_H 0 +#define BM_PXP_ALU_A_LUT_DATA1_LUT_DATA_H 0xFFFFFFFF +#define BF_PXP_ALU_A_LUT_DATA1_LUT_DATA_H(v) (v) + +#define HW_PXP_ALU_A_DBG (0x00002890) + +#define BP_PXP_ALU_A_DBG_DEBUG_SEL 24 +#define BM_PXP_ALU_A_DBG_DEBUG_SEL 0xFF000000 +#define BF_PXP_ALU_A_DBG_DEBUG_SEL(v) \ + (((v) << 24) & BM_PXP_ALU_A_DBG_DEBUG_SEL) +#define BP_PXP_ALU_A_DBG_DEBUG_VALUE 0 +#define BM_PXP_ALU_A_DBG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_ALU_A_DBG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_ALU_A_DBG_DEBUG_VALUE) + +#define HW_PXP_ALU_B_CTRL (0x000028a0) +#define HW_PXP_ALU_B_CTRL_SET (0x000028a4) +#define HW_PXP_ALU_B_CTRL_CLR (0x000028a8) +#define HW_PXP_ALU_B_CTRL_TOG (0x000028ac) + +#define BP_PXP_ALU_B_CTRL_RSVD0 29 +#define BM_PXP_ALU_B_CTRL_RSVD0 0xE0000000 +#define BF_PXP_ALU_B_CTRL_RSVD0(v) \ + (((v) << 29) & BM_PXP_ALU_B_CTRL_RSVD0) +#define BM_PXP_ALU_B_CTRL_DONE 0x10000000 +#define BF_PXP_ALU_B_CTRL_DONE(v) \ + (((v) << 28) & BM_PXP_ALU_B_CTRL_DONE) +#define BP_PXP_ALU_B_CTRL_RSVD1 21 +#define BM_PXP_ALU_B_CTRL_RSVD1 0x0FE00000 +#define BF_PXP_ALU_B_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_ALU_B_CTRL_RSVD1) +#define BM_PXP_ALU_B_CTRL_DONE_IRQ_EN 0x00100000 +#define BF_PXP_ALU_B_CTRL_DONE_IRQ_EN(v) \ + (((v) << 20) & BM_PXP_ALU_B_CTRL_DONE_IRQ_EN) +#define BP_PXP_ALU_B_CTRL_RSVD2 17 +#define BM_PXP_ALU_B_CTRL_RSVD2 0x000E0000 +#define BF_PXP_ALU_B_CTRL_RSVD2(v) \ + (((v) << 17) & BM_PXP_ALU_B_CTRL_RSVD2) +#define BM_PXP_ALU_B_CTRL_DONE_IRQ_FLAG 0x00010000 +#define BF_PXP_ALU_B_CTRL_DONE_IRQ_FLAG(v) \ + (((v) << 16) & BM_PXP_ALU_B_CTRL_DONE_IRQ_FLAG) +#define BP_PXP_ALU_B_CTRL_RSVD3 13 +#define BM_PXP_ALU_B_CTRL_RSVD3 0x0000E000 +#define BF_PXP_ALU_B_CTRL_RSVD3(v) \ + (((v) << 13) & BM_PXP_ALU_B_CTRL_RSVD3) +#define BM_PXP_ALU_B_CTRL_BYPASS 0x00001000 +#define BF_PXP_ALU_B_CTRL_BYPASS(v) \ + (((v) << 12) & BM_PXP_ALU_B_CTRL_BYPASS) +#define BV_PXP_ALU_B_CTRL_BYPASS__0 0x0 +#define BV_PXP_ALU_B_CTRL_BYPASS__1 0x1 +#define BP_PXP_ALU_B_CTRL_RSVD4 9 +#define BM_PXP_ALU_B_CTRL_RSVD4 0x00000E00 +#define BF_PXP_ALU_B_CTRL_RSVD4(v) \ + (((v) << 9) & BM_PXP_ALU_B_CTRL_RSVD4) +#define BM_PXP_ALU_B_CTRL_SW_RESET 0x00000100 +#define BF_PXP_ALU_B_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_ALU_B_CTRL_SW_RESET) +#define BP_PXP_ALU_B_CTRL_RSVD5 5 +#define BM_PXP_ALU_B_CTRL_RSVD5 0x000000E0 +#define BF_PXP_ALU_B_CTRL_RSVD5(v) \ + (((v) << 5) & BM_PXP_ALU_B_CTRL_RSVD5) +#define BM_PXP_ALU_B_CTRL_START 0x00000010 +#define BF_PXP_ALU_B_CTRL_START(v) \ + (((v) << 4) & BM_PXP_ALU_B_CTRL_START) +#define BP_PXP_ALU_B_CTRL_RSVD6 1 +#define BM_PXP_ALU_B_CTRL_RSVD6 0x0000000E +#define BF_PXP_ALU_B_CTRL_RSVD6(v) \ + (((v) << 1) & BM_PXP_ALU_B_CTRL_RSVD6) +#define BM_PXP_ALU_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_ALU_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALU_B_CTRL_ENABLE) +#define BV_PXP_ALU_B_CTRL_ENABLE__0 0x0 +#define BV_PXP_ALU_B_CTRL_ENABLE__1 0x1 + +#define HW_PXP_ALU_B_BUF_SIZE (0x000028b0) + +#define BP_PXP_ALU_B_BUF_SIZE_RSVD0 28 +#define BM_PXP_ALU_B_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_ALU_B_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_ALU_B_BUF_SIZE_RSVD0) +#define BP_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT 16 +#define BM_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT 0x0FFF0000 +#define BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT) +#define BP_PXP_ALU_B_BUF_SIZE_RSVD1 12 +#define BM_PXP_ALU_B_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_ALU_B_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_ALU_B_BUF_SIZE_RSVD1) +#define BP_PXP_ALU_B_BUF_SIZE_BUF_WIDTH 0 +#define BM_PXP_ALU_B_BUF_SIZE_BUF_WIDTH 0x00000FFF +#define BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_ALU_B_BUF_SIZE_BUF_WIDTH) + +#define HW_PXP_ALU_B_INST_ENTRY (0x000028c0) + +#define BP_PXP_ALU_B_INST_ENTRY_RSVD0 16 +#define BM_PXP_ALU_B_INST_ENTRY_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_B_INST_ENTRY_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_B_INST_ENTRY_RSVD0) +#define BP_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR 0 +#define BM_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR 0x0000FFFF +#define BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(v) \ + (((v) << 0) & BM_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR) + +#define HW_PXP_ALU_B_PARAM (0x000028d0) + +#define BP_PXP_ALU_B_PARAM_RSVD0 16 +#define BM_PXP_ALU_B_PARAM_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_B_PARAM_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_B_PARAM_RSVD0) +#define BP_PXP_ALU_B_PARAM_PARAM1 8 +#define BM_PXP_ALU_B_PARAM_PARAM1 0x0000FF00 +#define BF_PXP_ALU_B_PARAM_PARAM1(v) \ + (((v) << 8) & BM_PXP_ALU_B_PARAM_PARAM1) +#define BP_PXP_ALU_B_PARAM_PARAM0 0 +#define BM_PXP_ALU_B_PARAM_PARAM0 0x000000FF +#define BF_PXP_ALU_B_PARAM_PARAM0(v) \ + (((v) << 0) & BM_PXP_ALU_B_PARAM_PARAM0) + +#define HW_PXP_ALU_B_CONFIG (0x000028e0) + +#define BP_PXP_ALU_B_CONFIG_BUF_ADDR 0 +#define BM_PXP_ALU_B_CONFIG_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_ALU_B_CONFIG_BUF_ADDR(v) (v) + +#define HW_PXP_ALU_B_LUT_CONFIG (0x000028f0) +#define HW_PXP_ALU_B_LUT_CONFIG_SET (0x000028f4) +#define HW_PXP_ALU_B_LUT_CONFIG_CLR (0x000028f8) +#define HW_PXP_ALU_B_LUT_CONFIG_TOG (0x000028fc) + +#define BP_PXP_ALU_B_LUT_CONFIG_RSVD0 6 +#define BM_PXP_ALU_B_LUT_CONFIG_RSVD0 0xFFFFFFC0 +#define BF_PXP_ALU_B_LUT_CONFIG_RSVD0(v) \ + (((v) << 6) & BM_PXP_ALU_B_LUT_CONFIG_RSVD0) +#define BP_PXP_ALU_B_LUT_CONFIG_MODE 4 +#define BM_PXP_ALU_B_LUT_CONFIG_MODE 0x00000030 +#define BF_PXP_ALU_B_LUT_CONFIG_MODE(v) \ + (((v) << 4) & BM_PXP_ALU_B_LUT_CONFIG_MODE) +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__0 0x0 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__1 0x1 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__2 0x2 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__3 0x3 +#define BP_PXP_ALU_B_LUT_CONFIG_RSVD1 1 +#define BM_PXP_ALU_B_LUT_CONFIG_RSVD1 0x0000000E +#define BF_PXP_ALU_B_LUT_CONFIG_RSVD1(v) \ + (((v) << 1) & BM_PXP_ALU_B_LUT_CONFIG_RSVD1) +#define BM_PXP_ALU_B_LUT_CONFIG_EN 0x00000001 +#define BF_PXP_ALU_B_LUT_CONFIG_EN(v) \ + (((v) << 0) & BM_PXP_ALU_B_LUT_CONFIG_EN) + +#define HW_PXP_ALU_B_LUT_DATA0 (0x00002900) + +#define BP_PXP_ALU_B_LUT_DATA0_LUT_DATA_L 0 +#define BM_PXP_ALU_B_LUT_DATA0_LUT_DATA_L 0xFFFFFFFF +#define BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(v) (v) + +#define HW_PXP_ALU_B_LUT_DATA1 (0x00002910) + +#define BP_PXP_ALU_B_LUT_DATA1_LUT_DATA_H 0 +#define BM_PXP_ALU_B_LUT_DATA1_LUT_DATA_H 0xFFFFFFFF +#define BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(v) (v) + +#define HW_PXP_ALU_B_DBG (0x00002920) + +#define BP_PXP_ALU_B_DBG_DEBUG_SEL 24 +#define BM_PXP_ALU_B_DBG_DEBUG_SEL 0xFF000000 +#define BF_PXP_ALU_B_DBG_DEBUG_SEL(v) \ + (((v) << 24) & BM_PXP_ALU_B_DBG_DEBUG_SEL) +#define BP_PXP_ALU_B_DBG_DEBUG_VALUE 0 +#define BM_PXP_ALU_B_DBG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_ALU_B_DBG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_ALU_B_DBG_DEBUG_VALUE) + +#define HW_PXP_HIST_A_CTRL (0x00002a00) + +#define BP_PXP_HIST_A_CTRL_RSVD4 27 +#define BM_PXP_HIST_A_CTRL_RSVD4 0xF8000000 +#define BF_PXP_HIST_A_CTRL_RSVD4(v) \ + (((v) << 27) & BM_PXP_HIST_A_CTRL_RSVD4) +#define BP_PXP_HIST_A_CTRL_PIXEL_WIDTH 24 +#define BM_PXP_HIST_A_CTRL_PIXEL_WIDTH 0x07000000 +#define BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(v) \ + (((v) << 24) & BM_PXP_HIST_A_CTRL_PIXEL_WIDTH) +#define BM_PXP_HIST_A_CTRL_RSVD3 0x00800000 +#define BF_PXP_HIST_A_CTRL_RSVD3(v) \ + (((v) << 23) & BM_PXP_HIST_A_CTRL_RSVD3) +#define BP_PXP_HIST_A_CTRL_PIXEL_OFFSET 16 +#define BM_PXP_HIST_A_CTRL_PIXEL_OFFSET 0x007F0000 +#define BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_CTRL_PIXEL_OFFSET) +#define BP_PXP_HIST_A_CTRL_RSVD2 13 +#define BM_PXP_HIST_A_CTRL_RSVD2 0x0000E000 +#define BF_PXP_HIST_A_CTRL_RSVD2(v) \ + (((v) << 13) & BM_PXP_HIST_A_CTRL_RSVD2) +#define BP_PXP_HIST_A_CTRL_STATUS 8 +#define BM_PXP_HIST_A_CTRL_STATUS 0x00001F00 +#define BF_PXP_HIST_A_CTRL_STATUS(v) \ + (((v) << 8) & BM_PXP_HIST_A_CTRL_STATUS) +#define BP_PXP_HIST_A_CTRL_RSVD1 5 +#define BM_PXP_HIST_A_CTRL_RSVD1 0x000000E0 +#define BF_PXP_HIST_A_CTRL_RSVD1(v) \ + (((v) << 5) & BM_PXP_HIST_A_CTRL_RSVD1) +#define BM_PXP_HIST_A_CTRL_CLEAR 0x00000010 +#define BF_PXP_HIST_A_CTRL_CLEAR(v) \ + (((v) << 4) & BM_PXP_HIST_A_CTRL_CLEAR) +#define BP_PXP_HIST_A_CTRL_RSVD0 1 +#define BM_PXP_HIST_A_CTRL_RSVD0 0x0000000E +#define BF_PXP_HIST_A_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_A_CTRL_RSVD0) +#define BM_PXP_HIST_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_HIST_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_HIST_A_CTRL_ENABLE) + +#define HW_PXP_HIST_A_MASK (0x00002a10) + +#define BP_PXP_HIST_A_MASK_MASK_VALUE1 24 +#define BM_PXP_HIST_A_MASK_MASK_VALUE1 0xFF000000 +#define BF_PXP_HIST_A_MASK_MASK_VALUE1(v) \ + (((v) << 24) & BM_PXP_HIST_A_MASK_MASK_VALUE1) +#define BP_PXP_HIST_A_MASK_MASK_VALUE0 16 +#define BM_PXP_HIST_A_MASK_MASK_VALUE0 0x00FF0000 +#define BF_PXP_HIST_A_MASK_MASK_VALUE0(v) \ + (((v) << 16) & BM_PXP_HIST_A_MASK_MASK_VALUE0) +#define BP_PXP_HIST_A_MASK_MASK_WIDTH 13 +#define BM_PXP_HIST_A_MASK_MASK_WIDTH 0x0000E000 +#define BF_PXP_HIST_A_MASK_MASK_WIDTH(v) \ + (((v) << 13) & BM_PXP_HIST_A_MASK_MASK_WIDTH) +#define BP_PXP_HIST_A_MASK_MASK_OFFSET 6 +#define BM_PXP_HIST_A_MASK_MASK_OFFSET 0x00001FC0 +#define BF_PXP_HIST_A_MASK_MASK_OFFSET(v) \ + (((v) << 6) & BM_PXP_HIST_A_MASK_MASK_OFFSET) +#define BP_PXP_HIST_A_MASK_MASK_MODE 4 +#define BM_PXP_HIST_A_MASK_MASK_MODE 0x00000030 +#define BF_PXP_HIST_A_MASK_MASK_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_A_MASK_MASK_MODE) +#define BV_PXP_HIST_A_MASK_MASK_MODE__EQUAL 0x0 +#define BV_PXP_HIST_A_MASK_MASK_MODE__NOT_EQUAL 0x1 +#define BV_PXP_HIST_A_MASK_MASK_MODE__INSIDE 0x2 +#define BV_PXP_HIST_A_MASK_MASK_MODE__OUTSIDE 0x3 +#define BP_PXP_HIST_A_MASK_RSVD0 1 +#define BM_PXP_HIST_A_MASK_RSVD0 0x0000000E +#define BF_PXP_HIST_A_MASK_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_A_MASK_RSVD0) +#define BM_PXP_HIST_A_MASK_MASK_EN 0x00000001 +#define BF_PXP_HIST_A_MASK_MASK_EN(v) \ + (((v) << 0) & BM_PXP_HIST_A_MASK_MASK_EN) + +#define HW_PXP_HIST_A_BUF_SIZE (0x00002a20) + +#define BP_PXP_HIST_A_BUF_SIZE_RSVD0 28 +#define BM_PXP_HIST_A_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_HIST_A_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_HIST_A_BUF_SIZE_RSVD0) +#define BP_PXP_HIST_A_BUF_SIZE_HEIGHT 16 +#define BM_PXP_HIST_A_BUF_SIZE_HEIGHT 0x0FFF0000 +#define BF_PXP_HIST_A_BUF_SIZE_HEIGHT(v) \ + (((v) << 16) & BM_PXP_HIST_A_BUF_SIZE_HEIGHT) +#define BP_PXP_HIST_A_BUF_SIZE_RSVD1 12 +#define BM_PXP_HIST_A_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_HIST_A_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_HIST_A_BUF_SIZE_RSVD1) +#define BP_PXP_HIST_A_BUF_SIZE_WIDTH 0 +#define BM_PXP_HIST_A_BUF_SIZE_WIDTH 0x00000FFF +#define BF_PXP_HIST_A_BUF_SIZE_WIDTH(v) \ + (((v) << 0) & BM_PXP_HIST_A_BUF_SIZE_WIDTH) + +#define HW_PXP_HIST_A_TOTAL_PIXEL (0x00002a30) + +#define BP_PXP_HIST_A_TOTAL_PIXEL_RSVD0 24 +#define BM_PXP_HIST_A_TOTAL_PIXEL_RSVD0 0xFF000000 +#define BF_PXP_HIST_A_TOTAL_PIXEL_RSVD0(v) \ + (((v) << 24) & BM_PXP_HIST_A_TOTAL_PIXEL_RSVD0) +#define BP_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL 0 +#define BM_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL 0x00FFFFFF +#define BF_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(v) \ + (((v) << 0) & BM_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL) + +#define HW_PXP_HIST_A_ACTIVE_AREA_X (0x00002a40) + +#define BP_PXP_HIST_A_ACTIVE_AREA_X_RSVD1 28 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD1 0xF0000000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD1) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET 16 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_RSVD0 12 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD0 0x0000F000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD0) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET 0 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET 0x00000FFF +#define BF_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET) + +#define HW_PXP_HIST_A_ACTIVE_AREA_Y (0x00002a50) + +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1 28 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1 0xF0000000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET 16 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0 12 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0 0x0000F000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET 0 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET 0x00000FFF +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET) + +#define HW_PXP_HIST_A_RAW_STAT0 (0x00002a60) + +#define BP_PXP_HIST_A_RAW_STAT0_STAT0 0 +#define BM_PXP_HIST_A_RAW_STAT0_STAT0 0xFFFFFFFF +#define BF_PXP_HIST_A_RAW_STAT0_STAT0(v) (v) + +#define HW_PXP_HIST_A_RAW_STAT1 (0x00002a70) + +#define BP_PXP_HIST_A_RAW_STAT1_STAT1 0 +#define BM_PXP_HIST_A_RAW_STAT1_STAT1 0xFFFFFFFF +#define BF_PXP_HIST_A_RAW_STAT1_STAT1(v) (v) + +#define HW_PXP_HIST_B_CTRL (0x00002a80) + +#define BP_PXP_HIST_B_CTRL_RSVD4 27 +#define BM_PXP_HIST_B_CTRL_RSVD4 0xF8000000 +#define BF_PXP_HIST_B_CTRL_RSVD4(v) \ + (((v) << 27) & BM_PXP_HIST_B_CTRL_RSVD4) +#define BP_PXP_HIST_B_CTRL_PIXEL_WIDTH 24 +#define BM_PXP_HIST_B_CTRL_PIXEL_WIDTH 0x07000000 +#define BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(v) \ + (((v) << 24) & BM_PXP_HIST_B_CTRL_PIXEL_WIDTH) +#define BM_PXP_HIST_B_CTRL_RSVD3 0x00800000 +#define BF_PXP_HIST_B_CTRL_RSVD3(v) \ + (((v) << 23) & BM_PXP_HIST_B_CTRL_RSVD3) +#define BP_PXP_HIST_B_CTRL_PIXEL_OFFSET 16 +#define BM_PXP_HIST_B_CTRL_PIXEL_OFFSET 0x007F0000 +#define BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_CTRL_PIXEL_OFFSET) +#define BP_PXP_HIST_B_CTRL_RSVD2 13 +#define BM_PXP_HIST_B_CTRL_RSVD2 0x0000E000 +#define BF_PXP_HIST_B_CTRL_RSVD2(v) \ + (((v) << 13) & BM_PXP_HIST_B_CTRL_RSVD2) +#define BP_PXP_HIST_B_CTRL_STATUS 8 +#define BM_PXP_HIST_B_CTRL_STATUS 0x00001F00 +#define BF_PXP_HIST_B_CTRL_STATUS(v) \ + (((v) << 8) & BM_PXP_HIST_B_CTRL_STATUS) +#define BP_PXP_HIST_B_CTRL_RSVD1 5 +#define BM_PXP_HIST_B_CTRL_RSVD1 0x000000E0 +#define BF_PXP_HIST_B_CTRL_RSVD1(v) \ + (((v) << 5) & BM_PXP_HIST_B_CTRL_RSVD1) +#define BM_PXP_HIST_B_CTRL_CLEAR 0x00000010 +#define BF_PXP_HIST_B_CTRL_CLEAR(v) \ + (((v) << 4) & BM_PXP_HIST_B_CTRL_CLEAR) +#define BP_PXP_HIST_B_CTRL_RSVD0 1 +#define BM_PXP_HIST_B_CTRL_RSVD0 0x0000000E +#define BF_PXP_HIST_B_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_B_CTRL_RSVD0) +#define BM_PXP_HIST_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_HIST_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_HIST_B_CTRL_ENABLE) + +#define HW_PXP_HIST_B_MASK (0x00002a90) + +#define BP_PXP_HIST_B_MASK_MASK_VALUE1 24 +#define BM_PXP_HIST_B_MASK_MASK_VALUE1 0xFF000000 +#define BF_PXP_HIST_B_MASK_MASK_VALUE1(v) \ + (((v) << 24) & BM_PXP_HIST_B_MASK_MASK_VALUE1) +#define BP_PXP_HIST_B_MASK_MASK_VALUE0 16 +#define BM_PXP_HIST_B_MASK_MASK_VALUE0 0x00FF0000 +#define BF_PXP_HIST_B_MASK_MASK_VALUE0(v) \ + (((v) << 16) & BM_PXP_HIST_B_MASK_MASK_VALUE0) +#define BP_PXP_HIST_B_MASK_MASK_WIDTH 13 +#define BM_PXP_HIST_B_MASK_MASK_WIDTH 0x0000E000 +#define BF_PXP_HIST_B_MASK_MASK_WIDTH(v) \ + (((v) << 13) & BM_PXP_HIST_B_MASK_MASK_WIDTH) +#define BP_PXP_HIST_B_MASK_MASK_OFFSET 6 +#define BM_PXP_HIST_B_MASK_MASK_OFFSET 0x00001FC0 +#define BF_PXP_HIST_B_MASK_MASK_OFFSET(v) \ + (((v) << 6) & BM_PXP_HIST_B_MASK_MASK_OFFSET) +#define BP_PXP_HIST_B_MASK_MASK_MODE 4 +#define BM_PXP_HIST_B_MASK_MASK_MODE 0x00000030 +#define BF_PXP_HIST_B_MASK_MASK_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_B_MASK_MASK_MODE) +#define BV_PXP_HIST_B_MASK_MASK_MODE__EQUAL 0x0 +#define BV_PXP_HIST_B_MASK_MASK_MODE__NOT_EQUAL 0x1 +#define BV_PXP_HIST_B_MASK_MASK_MODE__INSIDE 0x2 +#define BV_PXP_HIST_B_MASK_MASK_MODE__OUTSIDE 0x3 +#define BP_PXP_HIST_B_MASK_RSVD0 1 +#define BM_PXP_HIST_B_MASK_RSVD0 0x0000000E +#define BF_PXP_HIST_B_MASK_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_B_MASK_RSVD0) +#define BM_PXP_HIST_B_MASK_MASK_EN 0x00000001 +#define BF_PXP_HIST_B_MASK_MASK_EN(v) \ + (((v) << 0) & BM_PXP_HIST_B_MASK_MASK_EN) + +#define HW_PXP_HIST_B_BUF_SIZE (0x00002aa0) + +#define BP_PXP_HIST_B_BUF_SIZE_RSVD0 28 +#define BM_PXP_HIST_B_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_HIST_B_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_HIST_B_BUF_SIZE_RSVD0) +#define BP_PXP_HIST_B_BUF_SIZE_HEIGHT 16 +#define BM_PXP_HIST_B_BUF_SIZE_HEIGHT 0x0FFF0000 +#define BF_PXP_HIST_B_BUF_SIZE_HEIGHT(v) \ + (((v) << 16) & BM_PXP_HIST_B_BUF_SIZE_HEIGHT) +#define BP_PXP_HIST_B_BUF_SIZE_RSVD1 12 +#define BM_PXP_HIST_B_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_HIST_B_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_HIST_B_BUF_SIZE_RSVD1) +#define BP_PXP_HIST_B_BUF_SIZE_WIDTH 0 +#define BM_PXP_HIST_B_BUF_SIZE_WIDTH 0x00000FFF +#define BF_PXP_HIST_B_BUF_SIZE_WIDTH(v) \ + (((v) << 0) & BM_PXP_HIST_B_BUF_SIZE_WIDTH) + +#define HW_PXP_HIST_B_TOTAL_PIXEL (0x00002ab0) + +#define BP_PXP_HIST_B_TOTAL_PIXEL_RSVD0 24 +#define BM_PXP_HIST_B_TOTAL_PIXEL_RSVD0 0xFF000000 +#define BF_PXP_HIST_B_TOTAL_PIXEL_RSVD0(v) \ + (((v) << 24) & BM_PXP_HIST_B_TOTAL_PIXEL_RSVD0) +#define BP_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL 0 +#define BM_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL 0x00FFFFFF +#define BF_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(v) \ + (((v) << 0) & BM_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL) + +#define HW_PXP_HIST_B_ACTIVE_AREA_X (0x00002ac0) + +#define BP_PXP_HIST_B_ACTIVE_AREA_X_RSVD1 28 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD1 0xF0000000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD1) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET 16 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_RSVD0 12 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD0 0x0000F000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD0) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET 0 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET 0x00000FFF +#define BF_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET) + +#define HW_PXP_HIST_B_ACTIVE_AREA_Y (0x00002ad0) + +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1 28 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1 0xF0000000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET 16 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0 12 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0 0x0000F000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET 0 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET 0x00000FFF +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET) + +#define HW_PXP_HIST_B_RAW_STAT0 (0x00002ae0) + +#define BP_PXP_HIST_B_RAW_STAT0_STAT0 0 +#define BM_PXP_HIST_B_RAW_STAT0_STAT0 0xFFFFFFFF +#define BF_PXP_HIST_B_RAW_STAT0_STAT0(v) (v) + +#define HW_PXP_HIST_B_RAW_STAT1 (0x00002af0) + +#define BP_PXP_HIST_B_RAW_STAT1_STAT1 0 +#define BM_PXP_HIST_B_RAW_STAT1_STAT1 0xFFFFFFFF +#define BF_PXP_HIST_B_RAW_STAT1_STAT1(v) (v) + +#define HW_PXP_HIST2_PARAM (0x00002b00) + +#define BP_PXP_HIST2_PARAM_RSVD 16 +#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 +#define BF_PXP_HIST2_PARAM_RSVD(v) \ + (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) +#define BP_PXP_HIST2_PARAM_RSVD1 14 +#define BM_PXP_HIST2_PARAM_RSVD1 0x0000C000 +#define BF_PXP_HIST2_PARAM_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST2_PARAM_RSVD1) +#define BP_PXP_HIST2_PARAM_VALUE1 8 +#define BM_PXP_HIST2_PARAM_VALUE1 0x00003F00 +#define BF_PXP_HIST2_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) +#define BP_PXP_HIST2_PARAM_RSVD0 6 +#define BM_PXP_HIST2_PARAM_RSVD0 0x000000C0 +#define BF_PXP_HIST2_PARAM_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST2_PARAM_RSVD0) +#define BP_PXP_HIST2_PARAM_VALUE0 0 +#define BM_PXP_HIST2_PARAM_VALUE0 0x0000003F +#define BF_PXP_HIST2_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) + +#define HW_PXP_HIST4_PARAM (0x00002b10) + +#define BP_PXP_HIST4_PARAM_RSVD3 30 +#define BM_PXP_HIST4_PARAM_RSVD3 0xC0000000 +#define BF_PXP_HIST4_PARAM_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST4_PARAM_RSVD3) +#define BP_PXP_HIST4_PARAM_VALUE3 24 +#define BM_PXP_HIST4_PARAM_VALUE3 0x3F000000 +#define BF_PXP_HIST4_PARAM_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) +#define BP_PXP_HIST4_PARAM_RSVD2 22 +#define BM_PXP_HIST4_PARAM_RSVD2 0x00C00000 +#define BF_PXP_HIST4_PARAM_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST4_PARAM_RSVD2) +#define BP_PXP_HIST4_PARAM_VALUE2 16 +#define BM_PXP_HIST4_PARAM_VALUE2 0x003F0000 +#define BF_PXP_HIST4_PARAM_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) +#define BP_PXP_HIST4_PARAM_RSVD1 14 +#define BM_PXP_HIST4_PARAM_RSVD1 0x0000C000 +#define BF_PXP_HIST4_PARAM_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST4_PARAM_RSVD1) +#define BP_PXP_HIST4_PARAM_VALUE1 8 +#define BM_PXP_HIST4_PARAM_VALUE1 0x00003F00 +#define BF_PXP_HIST4_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) +#define BP_PXP_HIST4_PARAM_RSVD0 6 +#define BM_PXP_HIST4_PARAM_RSVD0 0x000000C0 +#define BF_PXP_HIST4_PARAM_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST4_PARAM_RSVD0) +#define BP_PXP_HIST4_PARAM_VALUE0 0 +#define BM_PXP_HIST4_PARAM_VALUE0 0x0000003F +#define BF_PXP_HIST4_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) + +#define HW_PXP_HIST8_PARAM0 (0x00002b20) + +#define BP_PXP_HIST8_PARAM0_RSVD3 30 +#define BM_PXP_HIST8_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST8_PARAM0_RSVD3) +#define BP_PXP_HIST8_PARAM0_VALUE3 24 +#define BM_PXP_HIST8_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) +#define BP_PXP_HIST8_PARAM0_RSVD2 22 +#define BM_PXP_HIST8_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST8_PARAM0_RSVD2) +#define BP_PXP_HIST8_PARAM0_VALUE2 16 +#define BM_PXP_HIST8_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) +#define BP_PXP_HIST8_PARAM0_RSVD1 14 +#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST8_PARAM0_RSVD1) +#define BP_PXP_HIST8_PARAM0_VALUE1 8 +#define BM_PXP_HIST8_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) +#define BP_PXP_HIST8_PARAM0_RSVD0 6 +#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST8_PARAM0_RSVD0) +#define BP_PXP_HIST8_PARAM0_VALUE0 0 +#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) + +#define HW_PXP_HIST8_PARAM1 (0x00002b30) + +#define BP_PXP_HIST8_PARAM1_RSVD7 30 +#define BM_PXP_HIST8_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST8_PARAM1_RSVD7) +#define BP_PXP_HIST8_PARAM1_VALUE7 24 +#define BM_PXP_HIST8_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) +#define BP_PXP_HIST8_PARAM1_RSVD6 22 +#define BM_PXP_HIST8_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST8_PARAM1_RSVD6) +#define BP_PXP_HIST8_PARAM1_VALUE6 16 +#define BM_PXP_HIST8_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) +#define BP_PXP_HIST8_PARAM1_RSVD5 14 +#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST8_PARAM1_RSVD5) +#define BP_PXP_HIST8_PARAM1_VALUE5 8 +#define BM_PXP_HIST8_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) +#define BP_PXP_HIST8_PARAM1_RSVD4 6 +#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST8_PARAM1_RSVD4) +#define BP_PXP_HIST8_PARAM1_VALUE4 0 +#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM0 (0x00002b40) + +#define BP_PXP_HIST16_PARAM0_RSVD3 30 +#define BM_PXP_HIST16_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM0_RSVD3) +#define BP_PXP_HIST16_PARAM0_VALUE3 24 +#define BM_PXP_HIST16_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) +#define BP_PXP_HIST16_PARAM0_RSVD2 22 +#define BM_PXP_HIST16_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM0_RSVD2) +#define BP_PXP_HIST16_PARAM0_VALUE2 16 +#define BM_PXP_HIST16_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) +#define BP_PXP_HIST16_PARAM0_RSVD1 14 +#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM0_RSVD1) +#define BP_PXP_HIST16_PARAM0_VALUE1 8 +#define BM_PXP_HIST16_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) +#define BP_PXP_HIST16_PARAM0_RSVD0 6 +#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM0_RSVD0) +#define BP_PXP_HIST16_PARAM0_VALUE0 0 +#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) + +#define HW_PXP_HIST16_PARAM1 (0x00002b50) + +#define BP_PXP_HIST16_PARAM1_RSVD7 30 +#define BM_PXP_HIST16_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM1_RSVD7) +#define BP_PXP_HIST16_PARAM1_VALUE7 24 +#define BM_PXP_HIST16_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) +#define BP_PXP_HIST16_PARAM1_RSVD6 22 +#define BM_PXP_HIST16_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM1_RSVD6) +#define BP_PXP_HIST16_PARAM1_VALUE6 16 +#define BM_PXP_HIST16_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) +#define BP_PXP_HIST16_PARAM1_RSVD5 14 +#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM1_RSVD5) +#define BP_PXP_HIST16_PARAM1_VALUE5 8 +#define BM_PXP_HIST16_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) +#define BP_PXP_HIST16_PARAM1_RSVD4 6 +#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM1_RSVD4) +#define BP_PXP_HIST16_PARAM1_VALUE4 0 +#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM2 (0x00002b60) + +#define BP_PXP_HIST16_PARAM2_RSVD11 30 +#define BM_PXP_HIST16_PARAM2_RSVD11 0xC0000000 +#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM2_RSVD11) +#define BP_PXP_HIST16_PARAM2_VALUE11 24 +#define BM_PXP_HIST16_PARAM2_VALUE11 0x3F000000 +#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) +#define BP_PXP_HIST16_PARAM2_RSVD10 22 +#define BM_PXP_HIST16_PARAM2_RSVD10 0x00C00000 +#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM2_RSVD10) +#define BP_PXP_HIST16_PARAM2_VALUE10 16 +#define BM_PXP_HIST16_PARAM2_VALUE10 0x003F0000 +#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) +#define BP_PXP_HIST16_PARAM2_RSVD9 14 +#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000C000 +#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM2_RSVD9) +#define BP_PXP_HIST16_PARAM2_VALUE9 8 +#define BM_PXP_HIST16_PARAM2_VALUE9 0x00003F00 +#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) +#define BP_PXP_HIST16_PARAM2_RSVD8 6 +#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000C0 +#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM2_RSVD8) +#define BP_PXP_HIST16_PARAM2_VALUE8 0 +#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000003F +#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) + +#define HW_PXP_HIST16_PARAM3 (0x00002b70) + +#define BP_PXP_HIST16_PARAM3_RSVD15 30 +#define BM_PXP_HIST16_PARAM3_RSVD15 0xC0000000 +#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM3_RSVD15) +#define BP_PXP_HIST16_PARAM3_VALUE15 24 +#define BM_PXP_HIST16_PARAM3_VALUE15 0x3F000000 +#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) +#define BP_PXP_HIST16_PARAM3_RSVD14 22 +#define BM_PXP_HIST16_PARAM3_RSVD14 0x00C00000 +#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM3_RSVD14) +#define BP_PXP_HIST16_PARAM3_VALUE14 16 +#define BM_PXP_HIST16_PARAM3_VALUE14 0x003F0000 +#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) +#define BP_PXP_HIST16_PARAM3_RSVD13 14 +#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000C000 +#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM3_RSVD13) +#define BP_PXP_HIST16_PARAM3_VALUE13 8 +#define BM_PXP_HIST16_PARAM3_VALUE13 0x00003F00 +#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) +#define BP_PXP_HIST16_PARAM3_RSVD12 6 +#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000C0 +#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM3_RSVD12) +#define BP_PXP_HIST16_PARAM3_VALUE12 0 +#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000003F +#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) + +#define HW_PXP_HIST32_PARAM0 (0x00002b80) + +#define BP_PXP_HIST32_PARAM0_RSVD3 30 +#define BM_PXP_HIST32_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST32_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM0_RSVD3) +#define BP_PXP_HIST32_PARAM0_VALUE3 24 +#define BM_PXP_HIST32_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST32_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM0_VALUE3) +#define BP_PXP_HIST32_PARAM0_RSVD2 22 +#define BM_PXP_HIST32_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST32_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM0_RSVD2) +#define BP_PXP_HIST32_PARAM0_VALUE2 16 +#define BM_PXP_HIST32_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST32_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM0_VALUE2) +#define BP_PXP_HIST32_PARAM0_RSVD1 14 +#define BM_PXP_HIST32_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST32_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM0_RSVD1) +#define BP_PXP_HIST32_PARAM0_VALUE1 8 +#define BM_PXP_HIST32_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST32_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM0_VALUE1) +#define BP_PXP_HIST32_PARAM0_RSVD0 6 +#define BM_PXP_HIST32_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST32_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM0_RSVD0) +#define BP_PXP_HIST32_PARAM0_VALUE0 0 +#define BM_PXP_HIST32_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST32_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM0_VALUE0) + +#define HW_PXP_HIST32_PARAM1 (0x00002b90) + +#define BP_PXP_HIST32_PARAM1_RSVD7 30 +#define BM_PXP_HIST32_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST32_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM1_RSVD7) +#define BP_PXP_HIST32_PARAM1_VALUE7 24 +#define BM_PXP_HIST32_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST32_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM1_VALUE7) +#define BP_PXP_HIST32_PARAM1_RSVD6 22 +#define BM_PXP_HIST32_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST32_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM1_RSVD6) +#define BP_PXP_HIST32_PARAM1_VALUE6 16 +#define BM_PXP_HIST32_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST32_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM1_VALUE6) +#define BP_PXP_HIST32_PARAM1_RSVD5 14 +#define BM_PXP_HIST32_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST32_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM1_RSVD5) +#define BP_PXP_HIST32_PARAM1_VALUE5 8 +#define BM_PXP_HIST32_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST32_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM1_VALUE5) +#define BP_PXP_HIST32_PARAM1_RSVD4 6 +#define BM_PXP_HIST32_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST32_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM1_RSVD4) +#define BP_PXP_HIST32_PARAM1_VALUE4 0 +#define BM_PXP_HIST32_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST32_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM1_VALUE4) + +#define HW_PXP_HIST32_PARAM2 (0x00002ba0) + +#define BP_PXP_HIST32_PARAM2_RSVD11 30 +#define BM_PXP_HIST32_PARAM2_RSVD11 0xC0000000 +#define BF_PXP_HIST32_PARAM2_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM2_RSVD11) +#define BP_PXP_HIST32_PARAM2_VALUE11 24 +#define BM_PXP_HIST32_PARAM2_VALUE11 0x3F000000 +#define BF_PXP_HIST32_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM2_VALUE11) +#define BP_PXP_HIST32_PARAM2_RSVD10 22 +#define BM_PXP_HIST32_PARAM2_RSVD10 0x00C00000 +#define BF_PXP_HIST32_PARAM2_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM2_RSVD10) +#define BP_PXP_HIST32_PARAM2_VALUE10 16 +#define BM_PXP_HIST32_PARAM2_VALUE10 0x003F0000 +#define BF_PXP_HIST32_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM2_VALUE10) +#define BP_PXP_HIST32_PARAM2_RSVD9 14 +#define BM_PXP_HIST32_PARAM2_RSVD9 0x0000C000 +#define BF_PXP_HIST32_PARAM2_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM2_RSVD9) +#define BP_PXP_HIST32_PARAM2_VALUE9 8 +#define BM_PXP_HIST32_PARAM2_VALUE9 0x00003F00 +#define BF_PXP_HIST32_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM2_VALUE9) +#define BP_PXP_HIST32_PARAM2_RSVD8 6 +#define BM_PXP_HIST32_PARAM2_RSVD8 0x000000C0 +#define BF_PXP_HIST32_PARAM2_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM2_RSVD8) +#define BP_PXP_HIST32_PARAM2_VALUE8 0 +#define BM_PXP_HIST32_PARAM2_VALUE8 0x0000003F +#define BF_PXP_HIST32_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM2_VALUE8) + +#define HW_PXP_HIST32_PARAM3 (0x00002bb0) + +#define BP_PXP_HIST32_PARAM3_RSVD15 30 +#define BM_PXP_HIST32_PARAM3_RSVD15 0xC0000000 +#define BF_PXP_HIST32_PARAM3_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM3_RSVD15) +#define BP_PXP_HIST32_PARAM3_VALUE15 24 +#define BM_PXP_HIST32_PARAM3_VALUE15 0x3F000000 +#define BF_PXP_HIST32_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM3_VALUE15) +#define BP_PXP_HIST32_PARAM3_RSVD14 22 +#define BM_PXP_HIST32_PARAM3_RSVD14 0x00C00000 +#define BF_PXP_HIST32_PARAM3_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM3_RSVD14) +#define BP_PXP_HIST32_PARAM3_VALUE14 16 +#define BM_PXP_HIST32_PARAM3_VALUE14 0x003F0000 +#define BF_PXP_HIST32_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM3_VALUE14) +#define BP_PXP_HIST32_PARAM3_RSVD13 14 +#define BM_PXP_HIST32_PARAM3_RSVD13 0x0000C000 +#define BF_PXP_HIST32_PARAM3_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM3_RSVD13) +#define BP_PXP_HIST32_PARAM3_VALUE13 8 +#define BM_PXP_HIST32_PARAM3_VALUE13 0x00003F00 +#define BF_PXP_HIST32_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM3_VALUE13) +#define BP_PXP_HIST32_PARAM3_RSVD12 6 +#define BM_PXP_HIST32_PARAM3_RSVD12 0x000000C0 +#define BF_PXP_HIST32_PARAM3_RSVD12(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM3_RSVD12) +#define BP_PXP_HIST32_PARAM3_VALUE12 0 +#define BM_PXP_HIST32_PARAM3_VALUE12 0x0000003F +#define BF_PXP_HIST32_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM3_VALUE12) + +#define HW_PXP_HIST32_PARAM4 (0x00002bc0) + +#define BP_PXP_HIST32_PARAM4_RSVD3 30 +#define BM_PXP_HIST32_PARAM4_RSVD3 0xC0000000 +#define BF_PXP_HIST32_PARAM4_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM4_RSVD3) +#define BP_PXP_HIST32_PARAM4_VALUE19 24 +#define BM_PXP_HIST32_PARAM4_VALUE19 0x3F000000 +#define BF_PXP_HIST32_PARAM4_VALUE19(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM4_VALUE19) +#define BP_PXP_HIST32_PARAM4_RSVD2 22 +#define BM_PXP_HIST32_PARAM4_RSVD2 0x00C00000 +#define BF_PXP_HIST32_PARAM4_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM4_RSVD2) +#define BP_PXP_HIST32_PARAM4_VALUE18 16 +#define BM_PXP_HIST32_PARAM4_VALUE18 0x003F0000 +#define BF_PXP_HIST32_PARAM4_VALUE18(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM4_VALUE18) +#define BP_PXP_HIST32_PARAM4_RSVD1 14 +#define BM_PXP_HIST32_PARAM4_RSVD1 0x0000C000 +#define BF_PXP_HIST32_PARAM4_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM4_RSVD1) +#define BP_PXP_HIST32_PARAM4_VALUE17 8 +#define BM_PXP_HIST32_PARAM4_VALUE17 0x00003F00 +#define BF_PXP_HIST32_PARAM4_VALUE17(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM4_VALUE17) +#define BP_PXP_HIST32_PARAM4_RSVD0 6 +#define BM_PXP_HIST32_PARAM4_RSVD0 0x000000C0 +#define BF_PXP_HIST32_PARAM4_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM4_RSVD0) +#define BP_PXP_HIST32_PARAM4_VALUE16 0 +#define BM_PXP_HIST32_PARAM4_VALUE16 0x0000003F +#define BF_PXP_HIST32_PARAM4_VALUE16(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM4_VALUE16) + +#define HW_PXP_HIST32_PARAM5 (0x00002bd0) + +#define BP_PXP_HIST32_PARAM5_RSVD7 30 +#define BM_PXP_HIST32_PARAM5_RSVD7 0xC0000000 +#define BF_PXP_HIST32_PARAM5_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM5_RSVD7) +#define BP_PXP_HIST32_PARAM5_VALUE23 24 +#define BM_PXP_HIST32_PARAM5_VALUE23 0x3F000000 +#define BF_PXP_HIST32_PARAM5_VALUE23(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM5_VALUE23) +#define BP_PXP_HIST32_PARAM5_RSVD6 22 +#define BM_PXP_HIST32_PARAM5_RSVD6 0x00C00000 +#define BF_PXP_HIST32_PARAM5_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM5_RSVD6) +#define BP_PXP_HIST32_PARAM5_VALUE22 16 +#define BM_PXP_HIST32_PARAM5_VALUE22 0x003F0000 +#define BF_PXP_HIST32_PARAM5_VALUE22(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM5_VALUE22) +#define BP_PXP_HIST32_PARAM5_RSVD5 14 +#define BM_PXP_HIST32_PARAM5_RSVD5 0x0000C000 +#define BF_PXP_HIST32_PARAM5_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM5_RSVD5) +#define BP_PXP_HIST32_PARAM5_VALUE21 8 +#define BM_PXP_HIST32_PARAM5_VALUE21 0x00003F00 +#define BF_PXP_HIST32_PARAM5_VALUE21(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM5_VALUE21) +#define BP_PXP_HIST32_PARAM5_RSVD4 6 +#define BM_PXP_HIST32_PARAM5_RSVD4 0x000000C0 +#define BF_PXP_HIST32_PARAM5_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM5_RSVD4) +#define BP_PXP_HIST32_PARAM5_VALUE20 0 +#define BM_PXP_HIST32_PARAM5_VALUE20 0x0000003F +#define BF_PXP_HIST32_PARAM5_VALUE20(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM5_VALUE20) + +#define HW_PXP_HIST32_PARAM6 (0x00002be0) + +#define BP_PXP_HIST32_PARAM6_RSVD11 30 +#define BM_PXP_HIST32_PARAM6_RSVD11 0xC0000000 +#define BF_PXP_HIST32_PARAM6_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM6_RSVD11) +#define BP_PXP_HIST32_PARAM6_VALUE27 24 +#define BM_PXP_HIST32_PARAM6_VALUE27 0x3F000000 +#define BF_PXP_HIST32_PARAM6_VALUE27(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM6_VALUE27) +#define BP_PXP_HIST32_PARAM6_RSVD10 22 +#define BM_PXP_HIST32_PARAM6_RSVD10 0x00C00000 +#define BF_PXP_HIST32_PARAM6_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM6_RSVD10) +#define BP_PXP_HIST32_PARAM6_VALUE26 16 +#define BM_PXP_HIST32_PARAM6_VALUE26 0x003F0000 +#define BF_PXP_HIST32_PARAM6_VALUE26(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM6_VALUE26) +#define BP_PXP_HIST32_PARAM6_RSVD9 14 +#define BM_PXP_HIST32_PARAM6_RSVD9 0x0000C000 +#define BF_PXP_HIST32_PARAM6_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM6_RSVD9) +#define BP_PXP_HIST32_PARAM6_VALUE25 8 +#define BM_PXP_HIST32_PARAM6_VALUE25 0x00003F00 +#define BF_PXP_HIST32_PARAM6_VALUE25(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM6_VALUE25) +#define BP_PXP_HIST32_PARAM6_RSVD8 6 +#define BM_PXP_HIST32_PARAM6_RSVD8 0x000000C0 +#define BF_PXP_HIST32_PARAM6_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM6_RSVD8) +#define BP_PXP_HIST32_PARAM6_VALUE24 0 +#define BM_PXP_HIST32_PARAM6_VALUE24 0x0000003F +#define BF_PXP_HIST32_PARAM6_VALUE24(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM6_VALUE24) + +#define HW_PXP_HIST32_PARAM7 (0x00002bf0) + +#define BP_PXP_HIST32_PARAM7_RSVD15 30 +#define BM_PXP_HIST32_PARAM7_RSVD15 0xC0000000 +#define BF_PXP_HIST32_PARAM7_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM7_RSVD15) +#define BP_PXP_HIST32_PARAM7_VALUE31 24 +#define BM_PXP_HIST32_PARAM7_VALUE31 0x3F000000 +#define BF_PXP_HIST32_PARAM7_VALUE31(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM7_VALUE31) +#define BP_PXP_HIST32_PARAM7_RSVD14 22 +#define BM_PXP_HIST32_PARAM7_RSVD14 0x00C00000 +#define BF_PXP_HIST32_PARAM7_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM7_RSVD14) +#define BP_PXP_HIST32_PARAM7_VALUE30 16 +#define BM_PXP_HIST32_PARAM7_VALUE30 0x003F0000 +#define BF_PXP_HIST32_PARAM7_VALUE30(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM7_VALUE30) +#define BP_PXP_HIST32_PARAM7_RSVD13 14 +#define BM_PXP_HIST32_PARAM7_RSVD13 0x0000C000 +#define BF_PXP_HIST32_PARAM7_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM7_RSVD13) +#define BP_PXP_HIST32_PARAM7_VALUE29 8 +#define BM_PXP_HIST32_PARAM7_VALUE29 0x00003F00 +#define BF_PXP_HIST32_PARAM7_VALUE29(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM7_VALUE29) +#define BP_PXP_HIST32_PARAM7_RSVD2 6 +#define BM_PXP_HIST32_PARAM7_RSVD2 0x000000C0 +#define BF_PXP_HIST32_PARAM7_RSVD2(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM7_RSVD2) +#define BP_PXP_HIST32_PARAM7_VALUE28 0 +#define BM_PXP_HIST32_PARAM7_VALUE28 0x0000003F +#define BF_PXP_HIST32_PARAM7_VALUE28(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM7_VALUE28) + +#define HW_PXP_COMP_CTRL (0x00002c00) +#define HW_PXP_COMP_CTRL_SET (0x00002c04) +#define HW_PXP_COMP_CTRL_CLR (0x00002c08) +#define HW_PXP_COMP_CTRL_TOG (0x00002c0c) + +#define BP_PXP_COMP_CTRL_RSVD0 9 +#define BM_PXP_COMP_CTRL_RSVD0 0xFFFFFE00 +#define BF_PXP_COMP_CTRL_RSVD0(v) \ + (((v) << 9) & BM_PXP_COMP_CTRL_RSVD0) +#define BM_PXP_COMP_CTRL_SW_RESET 0x00000100 +#define BF_PXP_COMP_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_COMP_CTRL_SW_RESET) +#define BP_PXP_COMP_CTRL_RSVD1 1 +#define BM_PXP_COMP_CTRL_RSVD1 0x000000FE +#define BF_PXP_COMP_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_COMP_CTRL_RSVD1) +#define BM_PXP_COMP_CTRL_START 0x00000001 +#define BF_PXP_COMP_CTRL_START(v) \ + (((v) << 0) & BM_PXP_COMP_CTRL_START) + +#define HW_PXP_COMP_FORMAT0 (0x00002c10) +#define HW_PXP_COMP_FORMAT0_SET (0x00002c14) +#define HW_PXP_COMP_FORMAT0_CLR (0x00002c18) +#define HW_PXP_COMP_FORMAT0_TOG (0x00002c1c) + +#define BP_PXP_COMP_FORMAT0_RSVD0 28 +#define BM_PXP_COMP_FORMAT0_RSVD0 0xF0000000 +#define BF_PXP_COMP_FORMAT0_RSVD0(v) \ + (((v) << 28) & BM_PXP_COMP_FORMAT0_RSVD0) +#define BP_PXP_COMP_FORMAT0_PIXEL_PITCH_64B 16 +#define BM_PXP_COMP_FORMAT0_PIXEL_PITCH_64B 0x0FFF0000 +#define BF_PXP_COMP_FORMAT0_PIXEL_PITCH_64B(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT0_PIXEL_PITCH_64B) +#define BP_PXP_COMP_FORMAT0_RSVD1 10 +#define BM_PXP_COMP_FORMAT0_RSVD1 0x0000FC00 +#define BF_PXP_COMP_FORMAT0_RSVD1(v) \ + (((v) << 10) & BM_PXP_COMP_FORMAT0_RSVD1) +#define BP_PXP_COMP_FORMAT0_MASK_INDEX 8 +#define BM_PXP_COMP_FORMAT0_MASK_INDEX 0x00000300 +#define BF_PXP_COMP_FORMAT0_MASK_INDEX(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT0_MASK_INDEX) +#define BP_PXP_COMP_FORMAT0_RSVD2 6 +#define BM_PXP_COMP_FORMAT0_RSVD2 0x000000C0 +#define BF_PXP_COMP_FORMAT0_RSVD2(v) \ + (((v) << 6) & BM_PXP_COMP_FORMAT0_RSVD2) +#define BP_PXP_COMP_FORMAT0_FIELD_NUM 4 +#define BM_PXP_COMP_FORMAT0_FIELD_NUM 0x00000030 +#define BF_PXP_COMP_FORMAT0_FIELD_NUM(v) \ + (((v) << 4) & BM_PXP_COMP_FORMAT0_FIELD_NUM) +#define BP_PXP_COMP_FORMAT0_RSVD3 1 +#define BM_PXP_COMP_FORMAT0_RSVD3 0x0000000E +#define BF_PXP_COMP_FORMAT0_RSVD3(v) \ + (((v) << 1) & BM_PXP_COMP_FORMAT0_RSVD3) +#define BM_PXP_COMP_FORMAT0_FLAG_32B 0x00000001 +#define BF_PXP_COMP_FORMAT0_FLAG_32B(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT0_FLAG_32B) + +#define HW_PXP_COMP_FORMAT1 (0x00002c20) + +#define BP_PXP_COMP_FORMAT1_D_LEN 29 +#define BM_PXP_COMP_FORMAT1_D_LEN 0xE0000000 +#define BF_PXP_COMP_FORMAT1_D_LEN(v) \ + (((v) << 29) & BM_PXP_COMP_FORMAT1_D_LEN) +#define BP_PXP_COMP_FORMAT1_D_OFFSET 24 +#define BM_PXP_COMP_FORMAT1_D_OFFSET 0x1F000000 +#define BF_PXP_COMP_FORMAT1_D_OFFSET(v) \ + (((v) << 24) & BM_PXP_COMP_FORMAT1_D_OFFSET) +#define BP_PXP_COMP_FORMAT1_C_LEN 21 +#define BM_PXP_COMP_FORMAT1_C_LEN 0x00E00000 +#define BF_PXP_COMP_FORMAT1_C_LEN(v) \ + (((v) << 21) & BM_PXP_COMP_FORMAT1_C_LEN) +#define BP_PXP_COMP_FORMAT1_C_OFFSET 16 +#define BM_PXP_COMP_FORMAT1_C_OFFSET 0x001F0000 +#define BF_PXP_COMP_FORMAT1_C_OFFSET(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT1_C_OFFSET) +#define BP_PXP_COMP_FORMAT1_B_LEN 13 +#define BM_PXP_COMP_FORMAT1_B_LEN 0x0000E000 +#define BF_PXP_COMP_FORMAT1_B_LEN(v) \ + (((v) << 13) & BM_PXP_COMP_FORMAT1_B_LEN) +#define BP_PXP_COMP_FORMAT1_B_OFFSET 8 +#define BM_PXP_COMP_FORMAT1_B_OFFSET 0x00001F00 +#define BF_PXP_COMP_FORMAT1_B_OFFSET(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT1_B_OFFSET) +#define BP_PXP_COMP_FORMAT1_A_LEN 5 +#define BM_PXP_COMP_FORMAT1_A_LEN 0x000000E0 +#define BF_PXP_COMP_FORMAT1_A_LEN(v) \ + (((v) << 5) & BM_PXP_COMP_FORMAT1_A_LEN) +#define BP_PXP_COMP_FORMAT1_A_OFFSET 0 +#define BM_PXP_COMP_FORMAT1_A_OFFSET 0x0000001F +#define BF_PXP_COMP_FORMAT1_A_OFFSET(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT1_A_OFFSET) + +#define HW_PXP_COMP_FORMAT2 (0x00002c30) + +#define BP_PXP_COMP_FORMAT2_RSVD 16 +#define BM_PXP_COMP_FORMAT2_RSVD 0xFFFF0000 +#define BF_PXP_COMP_FORMAT2_RSVD(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT2_RSVD) +#define BP_PXP_COMP_FORMAT2_D_RUNLEN 12 +#define BM_PXP_COMP_FORMAT2_D_RUNLEN 0x0000F000 +#define BF_PXP_COMP_FORMAT2_D_RUNLEN(v) \ + (((v) << 12) & BM_PXP_COMP_FORMAT2_D_RUNLEN) +#define BP_PXP_COMP_FORMAT2_C_RUNLEN 8 +#define BM_PXP_COMP_FORMAT2_C_RUNLEN 0x00000F00 +#define BF_PXP_COMP_FORMAT2_C_RUNLEN(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT2_C_RUNLEN) +#define BP_PXP_COMP_FORMAT2_B_RUNLEN 4 +#define BM_PXP_COMP_FORMAT2_B_RUNLEN 0x000000F0 +#define BF_PXP_COMP_FORMAT2_B_RUNLEN(v) \ + (((v) << 4) & BM_PXP_COMP_FORMAT2_B_RUNLEN) +#define BP_PXP_COMP_FORMAT2_A_RUNLEN 0 +#define BM_PXP_COMP_FORMAT2_A_RUNLEN 0x0000000F +#define BF_PXP_COMP_FORMAT2_A_RUNLEN(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT2_A_RUNLEN) + +#define HW_PXP_COMP_MASK0 (0x00002c40) + +#define BP_PXP_COMP_MASK0_VLD_MASK_LOW 0 +#define BM_PXP_COMP_MASK0_VLD_MASK_LOW 0xFFFFFFFF +#define BF_PXP_COMP_MASK0_VLD_MASK_LOW(v) (v) + +#define HW_PXP_COMP_MASK1 (0x00002c50) + +#define BP_PXP_COMP_MASK1_VLD_MASK_HIGH 0 +#define BM_PXP_COMP_MASK1_VLD_MASK_HIGH 0xFFFFFFFF +#define BF_PXP_COMP_MASK1_VLD_MASK_HIGH(v) (v) + +#define HW_PXP_COMP_BUFFER_SIZE (0x00002c60) + +#define BP_PXP_COMP_BUFFER_SIZE_RSVD0 29 +#define BM_PXP_COMP_BUFFER_SIZE_RSVD0 0xE0000000 +#define BF_PXP_COMP_BUFFER_SIZE_RSVD0(v) \ + (((v) << 29) & BM_PXP_COMP_BUFFER_SIZE_RSVD0) +#define BP_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH 16 +#define BM_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH 0x1FFF0000 +#define BF_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH(v) \ + (((v) << 16) & BM_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH) +#define BP_PXP_COMP_BUFFER_SIZE_RSVD1 13 +#define BM_PXP_COMP_BUFFER_SIZE_RSVD1 0x0000E000 +#define BF_PXP_COMP_BUFFER_SIZE_RSVD1(v) \ + (((v) << 13) & BM_PXP_COMP_BUFFER_SIZE_RSVD1) +#define BP_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH 0 +#define BM_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH 0x00001FFF +#define BF_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH(v) \ + (((v) << 0) & BM_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH) + +#define HW_PXP_COMP_SOURCE (0x00002c70) + +#define BP_PXP_COMP_SOURCE_SOURCE_ADDR 0 +#define BM_PXP_COMP_SOURCE_SOURCE_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_SOURCE_SOURCE_ADDR(v) (v) + +#define HW_PXP_COMP_TARGET (0x00002c80) + +#define BP_PXP_COMP_TARGET_TARGET_ADDR 0 +#define BM_PXP_COMP_TARGET_TARGET_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_TARGET_TARGET_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_A (0x00002c90) + +#define BP_PXP_COMP_BUFFER_A_A_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_A_A_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_A_A_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_B (0x00002ca0) + +#define BP_PXP_COMP_BUFFER_B_B_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_B_B_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_B_B_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_C (0x00002cb0) + +#define BP_PXP_COMP_BUFFER_C_C_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_C_C_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_C_C_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_D (0x00002cc0) + +#define BP_PXP_COMP_BUFFER_D_D_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_D_D_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_D_D_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_DEBUG (0x00002cd0) + +#define BP_PXP_COMP_DEBUG_DEBUG_VALUE 8 +#define BM_PXP_COMP_DEBUG_DEBUG_VALUE 0xFFFFFF00 +#define BF_PXP_COMP_DEBUG_DEBUG_VALUE(v) \ + (((v) << 8) & BM_PXP_COMP_DEBUG_DEBUG_VALUE) +#define BP_PXP_COMP_DEBUG_DEBUG_SEL 0 +#define BM_PXP_COMP_DEBUG_DEBUG_SEL 0x000000FF +#define BF_PXP_COMP_DEBUG_DEBUG_SEL(v) \ + (((v) << 0) & BM_PXP_COMP_DEBUG_DEBUG_SEL) + +#define HW_PXP_BUS_MUX (0x00002ce0) + +#define BP_PXP_BUS_MUX_RSVD1 24 +#define BM_PXP_BUS_MUX_RSVD1 0xFF000000 +#define BF_PXP_BUS_MUX_RSVD1(v) \ + (((v) << 24) & BM_PXP_BUS_MUX_RSVD1) +#define BP_PXP_BUS_MUX_WR_SEL 16 +#define BM_PXP_BUS_MUX_WR_SEL 0x00FF0000 +#define BF_PXP_BUS_MUX_WR_SEL(v) \ + (((v) << 16) & BM_PXP_BUS_MUX_WR_SEL) +#define BP_PXP_BUS_MUX_RSVD0 8 +#define BM_PXP_BUS_MUX_RSVD0 0x0000FF00 +#define BF_PXP_BUS_MUX_RSVD0(v) \ + (((v) << 8) & BM_PXP_BUS_MUX_RSVD0) +#define BP_PXP_BUS_MUX_RD_SEL 0 +#define BM_PXP_BUS_MUX_RD_SEL 0x000000FF +#define BF_PXP_BUS_MUX_RD_SEL(v) \ + (((v) << 0) & BM_PXP_BUS_MUX_RD_SEL) + +#define HW_PXP_HANDSHAKE_READY_MUX0 (0x00002cf0) + +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK7 28 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK7 0xF0000000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK7(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_READY_MUX0_HSK7) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK6 24 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK6 0x0F000000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK6(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_READY_MUX0_HSK6) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK5 20 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK5 0x00F00000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK5(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_READY_MUX0_HSK5) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK4 16 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK4 0x000F0000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK4(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_READY_MUX0_HSK4) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK3 12 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK3 0x0000F000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK3(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_READY_MUX0_HSK3) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK2 8 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK2 0x00000F00 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK2(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_READY_MUX0_HSK2) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK1 4 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK1 0x000000F0 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK1(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_READY_MUX0_HSK1) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK0 0 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK0 0x0000000F +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK0(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_READY_MUX0_HSK0) + +#define HW_PXP_HANDSHAKE_READY_MUX1 (0x00002d00) + +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK15 28 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK15 0xF0000000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK15(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_READY_MUX1_HSK15) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK14 24 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK14 0x0F000000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK14(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_READY_MUX1_HSK14) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK13 20 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK13 0x00F00000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK13(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_READY_MUX1_HSK13) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK12 16 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK12 0x000F0000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK12(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_READY_MUX1_HSK12) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK11 12 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK11 0x0000F000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK11(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_READY_MUX1_HSK11) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK10 8 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK10 0x00000F00 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK10(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_READY_MUX1_HSK10) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK9 4 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK9 0x000000F0 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK9(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_READY_MUX1_HSK9) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK8 0 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK8 0x0000000F +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK8(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_READY_MUX1_HSK8) + +#define HW_PXP_HANDSHAKE_DONE_MUX0 (0x00002d10) + +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK7 28 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK7 0xF0000000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK7(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK7) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK6 24 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK6 0x0F000000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK6(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK6) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK5 20 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK5 0x00F00000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK5(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK5) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK4 16 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK4 0x000F0000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK4(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK4) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK3 12 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK3 0x0000F000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK3(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK3) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK2 8 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK2 0x00000F00 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK2(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK2) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK1 4 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK1 0x000000F0 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK1(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK1) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK0 0 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK0 0x0000000F +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK0(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK0) + +#define HW_PXP_HANDSHAKE_DONE_MUX1 (0x00002d20) + +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK15 28 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK15 0xF0000000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK15(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK15) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK14 24 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK14 0x0F000000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK14(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK14) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK13 20 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK13 0x00F00000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK13(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK13) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK12 16 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK12 0x000F0000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK12(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK12) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK11 12 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK11 0x0000F000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK11(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK11) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK10 8 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK10 0x00000F00 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK10(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK10) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK9 4 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK9 0x000000F0 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK9(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK9) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK8 0 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK8 0x0000000F +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK8(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK8) + +#define HW_PXP_HANDSHAKE_CPU_FETCH (0x00002d30) +#define HW_PXP_HANDSHAKE_CPU_FETCH_SET (0x00002d34) +#define HW_PXP_HANDSHAKE_CPU_FETCH_CLR (0x00002d38) +#define HW_PXP_HANDSHAKE_CPU_FETCH_TOG (0x00002d3c) + +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN 0x80000000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN(v) \ + (((v) << 31) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_FETCH_RSVD1 22 +#define BM_PXP_HANDSHAKE_CPU_FETCH_RSVD1 0x7FC00000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_RSVD1(v) \ + (((v) << 22) & BM_PXP_HANDSHAKE_CPU_FETCH_RSVD1) +#define BP_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES 20 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES 0x00300000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE 0x00080000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE(v) \ + (((v) << 19) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE 0x00040000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE(v) \ + (((v) << 18) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY 0x00020000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY(v) \ + (((v) << 17) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY 0x00010000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN 0x00008000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN(v) \ + (((v) << 15) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_FETCH_RSVD0 6 +#define BM_PXP_HANDSHAKE_CPU_FETCH_RSVD0 0x00007FC0 +#define BF_PXP_HANDSHAKE_CPU_FETCH_RSVD0(v) \ + (((v) << 6) & BM_PXP_HANDSHAKE_CPU_FETCH_RSVD0) +#define BP_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES 4 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES 0x00000030 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE 0x00000008 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE(v) \ + (((v) << 3) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE 0x00000004 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE(v) \ + (((v) << 2) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY 0x00000002 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY(v) \ + (((v) << 1) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY 0x00000001 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY) + +#define HW_PXP_HANDSHAKE_CPU_STORE (0x00002d40) +#define HW_PXP_HANDSHAKE_CPU_STORE_SET (0x00002d44) +#define HW_PXP_HANDSHAKE_CPU_STORE_CLR (0x00002d48) +#define HW_PXP_HANDSHAKE_CPU_STORE_TOG (0x00002d4c) + +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN 0x80000000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN(v) \ + (((v) << 31) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_STORE_RSVD1 22 +#define BM_PXP_HANDSHAKE_CPU_STORE_RSVD1 0x7FC00000 +#define BF_PXP_HANDSHAKE_CPU_STORE_RSVD1(v) \ + (((v) << 22) & BM_PXP_HANDSHAKE_CPU_STORE_RSVD1) +#define BP_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES 20 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES 0x00300000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE 0x00080000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE(v) \ + (((v) << 19) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE 0x00040000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE(v) \ + (((v) << 18) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY 0x00020000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY(v) \ + (((v) << 17) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY 0x00010000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN 0x00008000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN(v) \ + (((v) << 15) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_STORE_RSVD0 6 +#define BM_PXP_HANDSHAKE_CPU_STORE_RSVD0 0x00007FC0 +#define BF_PXP_HANDSHAKE_CPU_STORE_RSVD0(v) \ + (((v) << 6) & BM_PXP_HANDSHAKE_CPU_STORE_RSVD0) +#define BP_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES 4 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES 0x00000030 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE 0x00000008 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE(v) \ + (((v) << 3) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE 0x00000004 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE(v) \ + (((v) << 2) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY 0x00000002 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY(v) \ + (((v) << 1) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY 0x00000001 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY) +#endif /* __ARCH_ARM___PXP_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma-buf/dma-buf.c linux-imx-phytec/drivers/dma-buf/dma-buf.c --- linux-6.1.55/drivers/dma-buf/dma-buf.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma-buf/dma-buf.c 2024-06-19 12:33:59.808218353 +0200 @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,7 @@ #include #include #include +#include #include #include @@ -448,6 +450,36 @@ dmabuf = file->private_data; switch (cmd) { + case DMA_BUF_IOCTL_PHYS: { + struct dma_buf_attachment *attachment = NULL; + struct sg_table *sgt = NULL; + unsigned long phys = 0; + struct device dev; + + if (!dmabuf || IS_ERR(dmabuf)) { + return -EFAULT; + } + memset(&dev, 0, sizeof(dev)); + device_initialize(&dev); + dev.coherent_dma_mask = DMA_BIT_MASK(64); + dev.dma_mask = &dev.coherent_dma_mask; + arch_setup_dma_ops(&dev, 0, 0, NULL, false); + attachment = dma_buf_attach(dmabuf, &dev); + if (!attachment || IS_ERR(attachment)) { + return -EFAULT; + } + + sgt = dma_buf_map_attachment(attachment, DMA_BIDIRECTIONAL); + if (sgt && !IS_ERR(sgt)) { + phys = sg_dma_address(sgt->sgl); + dma_buf_unmap_attachment(attachment, sgt, + DMA_BIDIRECTIONAL); + } + dma_buf_detach(dmabuf, attachment); + if (copy_to_user((void __user *) arg, &phys, sizeof(phys))) + return -EFAULT; + return 0; + } case DMA_BUF_IOCTL_SYNC: if (copy_from_user(&sync, (void __user *) arg, sizeof(sync))) return -EFAULT; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma-buf/dma-heap.c linux-imx-phytec/drivers/dma-buf/dma-heap.c --- linux-6.1.55/drivers/dma-buf/dma-heap.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma-buf/dma-heap.c 2024-06-19 12:33:59.808218353 +0200 @@ -31,6 +31,7 @@ * @heap_devt heap device node * @list list head connecting to list of heaps * @heap_cdev heap char device + * @heap_dev heap device struct * * Represents a heap of memory from which buffers can be made. */ @@ -41,6 +42,7 @@ dev_t heap_devt; struct list_head list; struct cdev heap_cdev; + struct device *heap_dev; }; static LIST_HEAD(heap_list); @@ -216,10 +218,21 @@ return heap->name; } +/** + * dma_heap_get_dev() - get device struct for the heap + * @heap: DMA-Heap to retrieve device struct from + * + * Returns: + * The device struct for the heap. + */ +struct device *dma_heap_get_dev(struct dma_heap *heap) +{ + return heap->heap_dev; +} + struct dma_heap *dma_heap_add(const struct dma_heap_export_info *exp_info) { struct dma_heap *heap, *h, *err_ret; - struct device *dev_ret; unsigned int minor; int ret; @@ -261,17 +274,20 @@ goto err1; } - dev_ret = device_create(dma_heap_class, - NULL, - heap->heap_devt, - NULL, - heap->name); - if (IS_ERR(dev_ret)) { + heap->heap_dev = device_create(dma_heap_class, + NULL, + heap->heap_devt, + NULL, + heap->name); + if (IS_ERR(heap->heap_dev)) { pr_err("dma_heap: Unable to create device\n"); - err_ret = ERR_CAST(dev_ret); + err_ret = ERR_CAST(heap->heap_dev); goto err2; } + /* Make sure it doesn't disappear on us */ + heap->heap_dev = get_device(heap->heap_dev); + mutex_lock(&heap_list_lock); /* check the name is unique */ list_for_each_entry(h, &heap_list, list) { diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma-buf/heaps/cma_heap.c linux-imx-phytec/drivers/dma-buf/heaps/cma_heap.c --- linux-6.1.55/drivers/dma-buf/heaps/cma_heap.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma-buf/heaps/cma_heap.c 2024-06-19 12:33:59.808218353 +0200 @@ -38,6 +38,7 @@ pgoff_t pagecount; int vmap_cnt; void *vaddr; + bool uncached; }; struct dma_heap_attachment { @@ -45,6 +46,7 @@ struct sg_table table; struct list_head list; bool mapped; + bool uncached; }; static int cma_heap_attach(struct dma_buf *dmabuf, @@ -70,6 +72,7 @@ a->dev = attachment->dev; INIT_LIST_HEAD(&a->list); a->mapped = false; + a->uncached = buffer->uncached; attachment->priv = a; @@ -99,9 +102,13 @@ { struct dma_heap_attachment *a = attachment->priv; struct sg_table *table = &a->table; + int attr = 0; int ret; - ret = dma_map_sgtable(attachment->dev, table, direction, 0); + if (a->uncached) + attr = DMA_ATTR_SKIP_CPU_SYNC; + + ret = dma_map_sgtable(attachment->dev, table, direction, attr); if (ret) return ERR_PTR(-ENOMEM); a->mapped = true; @@ -113,9 +120,13 @@ enum dma_data_direction direction) { struct dma_heap_attachment *a = attachment->priv; + int attr = 0; + + if (a->uncached) + attr = DMA_ATTR_SKIP_CPU_SYNC; a->mapped = false; - dma_unmap_sgtable(attachment->dev, table, direction, 0); + dma_unmap_sgtable(attachment->dev, table, direction, attr); } static int cma_heap_dma_buf_begin_cpu_access(struct dma_buf *dmabuf, @@ -129,10 +140,12 @@ if (buffer->vmap_cnt) invalidate_kernel_vmap_range(buffer->vaddr, buffer->len); - list_for_each_entry(a, &buffer->attachments, list) { - if (!a->mapped) - continue; - dma_sync_sgtable_for_cpu(a->dev, &a->table, direction); + if (!buffer->uncached) { + list_for_each_entry(a, &buffer->attachments, list) { + if (!a->mapped) + continue; + dma_sync_sgtable_for_cpu(a->dev, &a->table, direction); + } } mutex_unlock(&buffer->lock); @@ -150,10 +163,12 @@ if (buffer->vmap_cnt) flush_kernel_vmap_range(buffer->vaddr, buffer->len); - list_for_each_entry(a, &buffer->attachments, list) { - if (!a->mapped) - continue; - dma_sync_sgtable_for_device(a->dev, &a->table, direction); + if (!buffer->uncached) { + list_for_each_entry(a, &buffer->attachments, list) { + if (!a->mapped) + continue; + dma_sync_sgtable_for_device(a->dev, &a->table, direction); + } } mutex_unlock(&buffer->lock); @@ -185,6 +200,9 @@ if ((vma->vm_flags & (VM_SHARED | VM_MAYSHARE)) == 0) return -EINVAL; + if (buffer->uncached) + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + vma->vm_ops = &dma_heap_vm_ops; vma->vm_private_data = buffer; @@ -193,9 +211,13 @@ static void *cma_heap_do_vmap(struct cma_heap_buffer *buffer) { + pgprot_t pgprot = PAGE_KERNEL; void *vaddr; - vaddr = vmap(buffer->pages, buffer->pagecount, VM_MAP, PAGE_KERNEL); + if (buffer->uncached) + pgprot = pgprot_writecombine(PAGE_KERNEL); + + vaddr = vmap(buffer->pages, buffer->pagecount, VM_MAP, pgprot); if (!vaddr) return ERR_PTR(-ENOMEM); @@ -273,10 +295,11 @@ .release = cma_heap_dma_buf_release, }; -static struct dma_buf *cma_heap_allocate(struct dma_heap *heap, +static struct dma_buf *cma_heap_do_allocate(struct dma_heap *heap, unsigned long len, unsigned long fd_flags, - unsigned long heap_flags) + unsigned long heap_flags, + bool uncached) { struct cma_heap *cma_heap = dma_heap_get_drvdata(heap); struct cma_heap_buffer *buffer; @@ -285,8 +308,9 @@ pgoff_t pagecount = size >> PAGE_SHIFT; unsigned long align = get_order(size); struct page *cma_pages; + struct sg_table table; struct dma_buf *dmabuf; - int ret = -ENOMEM; + int ret = -ENOMEM, ret_sg_table; pgoff_t pg; buffer = kzalloc(sizeof(*buffer), GFP_KERNEL); @@ -296,6 +320,7 @@ INIT_LIST_HEAD(&buffer->attachments); mutex_init(&buffer->lock); buffer->len = size; + buffer->uncached = uncached; if (align > CONFIG_CMA_ALIGNMENT) align = CONFIG_CMA_ALIGNMENT; @@ -340,6 +365,20 @@ buffer->heap = cma_heap; buffer->pagecount = pagecount; + if (buffer->uncached) { + ret_sg_table = sg_alloc_table(&table, 1, GFP_KERNEL); + if (ret_sg_table) { + ret = -ENOMEM; + goto free_pages; + } + + sg_set_page(table.sgl, cma_pages, size, 0); + + dma_map_sgtable(dma_heap_get_dev(heap), &table, DMA_BIDIRECTIONAL, 0); + dma_unmap_sgtable(dma_heap_get_dev(heap), &table, DMA_BIDIRECTIONAL, 0); + sg_free_table(&table); + } + /* create the dmabuf */ exp_info.exp_name = dma_heap_get_name(heap); exp_info.ops = &cma_heap_buf_ops; @@ -363,14 +402,45 @@ return ERR_PTR(ret); } +static struct dma_buf *cma_heap_allocate(struct dma_heap *heap, + unsigned long len, + unsigned long fd_flags, + unsigned long heap_flags) +{ + return cma_heap_do_allocate(heap, len, fd_flags, heap_flags, false); +} + +static struct dma_buf *cma_uncached_heap_allocate(struct dma_heap *heap, + unsigned long len, + unsigned long fd_flags, + unsigned long heap_flags) +{ + return cma_heap_do_allocate(heap, len, fd_flags, heap_flags, true); +} + +/* Dummy function to be used until we can call coerce_mask_and_coherent */ +static struct dma_buf *cma_uncached_heap_not_initialized(struct dma_heap *heap, + unsigned long len, + unsigned long fd_flags, + unsigned long heap_flags) +{ + return ERR_PTR(-EBUSY); +} + static const struct dma_heap_ops cma_heap_ops = { .allocate = cma_heap_allocate, }; +static struct dma_heap_ops cma_uncached_heap_ops = { + .allocate = cma_uncached_heap_not_initialized, +}; + static int __add_cma_heap(struct cma *cma, void *data) { struct cma_heap *cma_heap; struct dma_heap_export_info exp_info; + const char *postfixed = "-uncached"; + char *cma_name; cma_heap = kzalloc(sizeof(*cma_heap), GFP_KERNEL); if (!cma_heap) @@ -389,6 +459,34 @@ return ret; } + cma_heap = kzalloc(sizeof(*cma_heap), GFP_KERNEL); + if (!cma_heap) + return -ENOMEM; + cma_heap->cma = cma; + + cma_name = kzalloc(strlen(cma_get_name(cma)) + strlen(postfixed) + 1, GFP_KERNEL); + if (!cma_name) { + kfree(cma_heap); + return -ENOMEM; + } + + exp_info.name = strcat(strcpy(cma_name, cma_get_name(cma)), postfixed); + exp_info.ops = &cma_uncached_heap_ops; + exp_info.priv = cma_heap; + + cma_heap->heap = dma_heap_add(&exp_info); + if (IS_ERR(cma_heap->heap)) { + int ret = PTR_ERR(cma_heap->heap); + + kfree(cma_heap); + kfree(cma_name); + return ret; + } + + dma_coerce_mask_and_coherent(dma_heap_get_dev(cma_heap->heap), DMA_BIT_MASK(64)); + mb(); /* make sure we only set allocate after dma_mask is set */ + cma_uncached_heap_ops.allocate = cma_uncached_heap_allocate; + return 0; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma-buf/heaps/dsp_heap.c linux-imx-phytec/drivers/dma-buf/heaps/dsp_heap.c --- linux-6.1.55/drivers/dma-buf/heaps/dsp_heap.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/dma-buf/heaps/dsp_heap.c 2024-06-19 12:33:59.808218353 +0200 @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DMABUF dsp heap exporter + * + * Copyright 2021 NXP. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct dsp_heap_buffer { + struct dma_heap *heap; + struct list_head attachments; + struct mutex lock; /* mutex lock */ +}; + +struct dsp_heap { + struct dma_heap *heap; + phys_addr_t base; + phys_addr_t size; +}; + +static int dsp_heap_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma) +{ + struct dsp_heap_buffer *buffer = dmabuf->priv; + struct dsp_heap *dsp_heap = dma_heap_get_drvdata(buffer->heap); + unsigned long pfn; + size_t size; + int ret; + + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + size = dsp_heap->size; + pfn = dsp_heap->base >> PAGE_SHIFT; + + ret = remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot); + if (ret < 0) + return ret; + + return 0; +} + +static void dsp_heap_dma_buf_release(struct dma_buf *dmabuf) +{ + struct dsp_heap_buffer *buffer = dmabuf->priv; + + kfree(buffer); +} + +static struct sg_table *dsp_heap_map_dma_buf(struct dma_buf_attachment *attachment, + enum dma_data_direction direction) +{ + return NULL; +} + +static void dsp_heap_unmap_dma_buf(struct dma_buf_attachment *attachment, + struct sg_table *table, + enum dma_data_direction direction) +{ +} + +static const struct dma_buf_ops dsp_heap_buf_ops = { + .mmap = dsp_heap_mmap, + .map_dma_buf = dsp_heap_map_dma_buf, + .unmap_dma_buf = dsp_heap_unmap_dma_buf, + .release = dsp_heap_dma_buf_release, +}; + +static struct dma_buf * dsp_heap_allocate(struct dma_heap *heap, + unsigned long len, + unsigned long fd_flags, + unsigned long heap_flags) +{ + struct dsp_heap *dsp_heap = dma_heap_get_drvdata(heap); + DEFINE_DMA_BUF_EXPORT_INFO(exp_info); + struct dsp_heap_buffer *buffer; + struct dma_buf *dmabuf; + + if (len > dsp_heap->size) + return ERR_PTR(-ENOMEM); + + buffer = kzalloc(sizeof(*buffer), GFP_KERNEL); + if (!buffer) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&buffer->attachments); + mutex_init(&buffer->lock); + buffer->heap = heap; + + /* create the dmabuf */ + exp_info.ops = &dsp_heap_buf_ops; + exp_info.size = len; + exp_info.flags = fd_flags; + exp_info.priv = buffer; + dmabuf = dma_buf_export(&exp_info); + if (IS_ERR(dmabuf)) { + kfree(buffer); + return dmabuf; + } + + return dmabuf; +} + +static const struct dma_heap_ops dsp_heap_ops = { + .allocate = dsp_heap_allocate, +}; + +static int dsp_heap_create(void) +{ + struct dma_heap_export_info exp_info; + struct dsp_heap *dsp_heap; + struct reserved_mem *rmem; + struct device_node np; + + np.full_name = "dsp_reserved_heap"; + np.name = "dsp_reserved_heap"; + rmem = of_reserved_mem_lookup(&np); + if (!rmem) { + pr_err("of_reserved_mem_lookup() returned NULL\n"); + return 0; + } + + if (rmem->base == 0 || rmem->size == 0) { + pr_err("dsp_data base or size is not correct\n"); + return -EINVAL; + } + + dsp_heap = kzalloc(sizeof(*dsp_heap), GFP_KERNEL); + if (!dsp_heap) + return -ENOMEM; + + dsp_heap->base = rmem->base; + dsp_heap->size = rmem->size; + + exp_info.name = "dsp"; + exp_info.ops = &dsp_heap_ops; + exp_info.priv = dsp_heap; + dsp_heap->heap = dma_heap_add(&exp_info); + if (IS_ERR(dsp_heap->heap)) { + int ret = PTR_ERR(dsp_heap->heap); + + kfree(dsp_heap); + return ret; + } + + return 0; +} +module_init(dsp_heap_create); +MODULE_LICENSE("GPL v2"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma-buf/heaps/Kconfig linux-imx-phytec/drivers/dma-buf/heaps/Kconfig --- linux-6.1.55/drivers/dma-buf/heaps/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma-buf/heaps/Kconfig 2024-06-19 12:33:59.808218353 +0200 @@ -12,3 +12,11 @@ Choose this option to enable dma-buf CMA heap. This heap is backed by the Contiguous Memory Allocator (CMA). If your system has these regions, you should say Y here. + +config DMABUF_HEAPS_DSP + tristate "DMA-BUF DSP Heap" + depends on DMABUF_HEAPS + help + Choose this option to enable the dsp dmabuf heap. The dsp heap + is allocated by gen allocater. it's allocated according the dts. + If in doubt, say Y. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/dma-buf/heaps/Makefile linux-imx-phytec/drivers/dma-buf/heaps/Makefile --- linux-6.1.55/drivers/dma-buf/heaps/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/dma-buf/heaps/Makefile 2024-06-19 12:33:59.808218353 +0200 @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_DMABUF_HEAPS_SYSTEM) += system_heap.o obj-$(CONFIG_DMABUF_HEAPS_CMA) += cma_heap.o +obj-$(CONFIG_DMABUF_HEAPS_DSP) += dsp_heap.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/edac/fsl_ddr_edac.c linux-imx-phytec/drivers/edac/fsl_ddr_edac.c --- linux-6.1.55/drivers/edac/fsl_ddr_edac.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/edac/fsl_ddr_edac.c 2024-06-19 12:33:59.860219242 +0200 @@ -7,7 +7,7 @@ * split out from mpc85xx_edac EDAC driver. * * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc. - * + * Parts Copyrighted (c) 2022 NXP * Author: Dave Jiang * * 2006-2007 (c) MontaVista Software, Inc. @@ -36,13 +36,26 @@ static u32 orig_ddr_err_sbe; static bool little_endian; -static inline u32 ddr_in32(void __iomem *addr) +static inline void __iomem *ddr_reg_addr(struct fsl_mc_pdata *pdata, unsigned int off) +{ + if (pdata->flag == TYPE_IMX9 && off >= FSL_MC_DATA_ERR_INJECT_HI && off <= FSL_MC_ERR_SBE) + return pdata->mc_vbase + off - FSL_MC_DATA_ERR_INJECT_HI + + IMX9_MC_DATA_ERR_INJECT_HI; + + return pdata->mc_vbase + off; +} + +static inline u32 ddr_in32(struct fsl_mc_pdata *pdata, unsigned int off) { + void __iomem *addr = ddr_reg_addr(pdata, off); + return little_endian ? ioread32(addr) : ioread32be(addr); } -static inline void ddr_out32(void __iomem *addr, u32 value) +static inline void ddr_out32(struct fsl_mc_pdata *pdata, unsigned int off, u32 value) { + void __iomem *addr = ddr_reg_addr(pdata, off); + if (little_endian) iowrite32(value, addr); else @@ -61,7 +74,7 @@ struct mem_ctl_info *mci = to_mci(dev); struct fsl_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", - ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI)); + ddr_in32(pdata, FSL_MC_DATA_ERR_INJECT_HI)); } static ssize_t fsl_mc_inject_data_lo_show(struct device *dev, @@ -71,7 +84,7 @@ struct mem_ctl_info *mci = to_mci(dev); struct fsl_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", - ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO)); + ddr_in32(pdata, FSL_MC_DATA_ERR_INJECT_LO)); } static ssize_t fsl_mc_inject_ctrl_show(struct device *dev, @@ -81,7 +94,7 @@ struct mem_ctl_info *mci = to_mci(dev); struct fsl_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", - ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT)); + ddr_in32(pdata, FSL_MC_ECC_ERR_INJECT)); } static ssize_t fsl_mc_inject_data_hi_store(struct device *dev, @@ -98,7 +111,7 @@ if (rc) return rc; - ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI, val); + ddr_out32(pdata, FSL_MC_DATA_ERR_INJECT_HI, val); return count; } return 0; @@ -118,7 +131,7 @@ if (rc) return rc; - ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO, val); + ddr_out32(pdata, FSL_MC_DATA_ERR_INJECT_LO, val); return count; } return 0; @@ -138,7 +151,7 @@ if (rc) return rc; - ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT, val); + ddr_out32(pdata, FSL_MC_ECC_ERR_INJECT, val); return count; } return 0; @@ -287,7 +300,7 @@ int bad_data_bit; int bad_ecc_bit; - err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT); + err_detect = ddr_in32(pdata, FSL_MC_ERR_DETECT); if (!err_detect) return; @@ -296,14 +309,14 @@ /* no more processing if not ECC bit errors */ if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect); + ddr_out32(pdata, FSL_MC_ERR_DETECT, err_detect); return; } - syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC); + syndrome = ddr_in32(pdata, FSL_MC_CAPTURE_ECC); /* Mask off appropriate bits of syndrome based on bus width */ - bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) & + bus_width = (ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG) & DSC_DBW_MASK) ? 32 : 64; if (bus_width == 64) syndrome &= 0xff; @@ -311,8 +324,8 @@ syndrome &= 0xffff; err_addr = make64( - ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS), - ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS)); + ddr_in32(pdata, FSL_MC_CAPTURE_EXT_ADDRESS), + ddr_in32(pdata, FSL_MC_CAPTURE_ADDRESS)); pfn = err_addr >> PAGE_SHIFT; for (row_index = 0; row_index < mci->nr_csrows; row_index++) { @@ -321,8 +334,8 @@ break; } - cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI); - cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO); + cap_high = ddr_in32(pdata, FSL_MC_CAPTURE_DATA_HI); + cap_low = ddr_in32(pdata, FSL_MC_CAPTURE_DATA_LO); /* * Analyze single-bit errors on 64-bit wide buses @@ -332,18 +345,24 @@ sbe_ecc_decode(cap_high, cap_low, syndrome, &bad_data_bit, &bad_ecc_bit); - if (bad_data_bit != -1) + if (bad_data_bit >= 0) fsl_mc_printk(mci, KERN_ERR, "Faulty Data bit: %d\n", bad_data_bit); - if (bad_ecc_bit != -1) + if (bad_ecc_bit >= 0) fsl_mc_printk(mci, KERN_ERR, - "Faulty ECC bit: %d\n", bad_ecc_bit); - - fsl_mc_printk(mci, KERN_ERR, - "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", - cap_high ^ (1 << (bad_data_bit - 32)), - cap_low ^ (1 << bad_data_bit), - syndrome ^ (1 << bad_ecc_bit)); + "Faulty ECC bit: %d\n", bad_ecc_bit); + if ((bad_data_bit > 0 && bad_data_bit < 32) && bad_ecc_bit > 0) { + fsl_mc_printk(mci, KERN_ERR, + "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", + cap_high, cap_low ^ (1 << bad_data_bit), + syndrome ^ (1 << bad_ecc_bit)); + } + if (bad_data_bit >= 32 && bad_ecc_bit > 0) { + fsl_mc_printk(mci, KERN_ERR, + "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", + cap_high ^ (1 << (bad_data_bit - 32)), + cap_low, syndrome ^ (1 << bad_ecc_bit)); + } } fsl_mc_printk(mci, KERN_ERR, @@ -368,7 +387,7 @@ row_index, 0, -1, mci->ctl_name, ""); - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect); + ddr_out32(pdata, FSL_MC_ERR_DETECT, err_detect); } static irqreturn_t fsl_mc_isr(int irq, void *dev_id) @@ -377,7 +396,7 @@ struct fsl_mc_pdata *pdata = mci->pvt_info; u32 err_detect; - err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT); + err_detect = ddr_in32(pdata, FSL_MC_ERR_DETECT); if (!err_detect) return IRQ_NONE; @@ -397,7 +416,7 @@ u32 cs_bnds; int index; - sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG); + sdram_ctl = ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG); sdtype = sdram_ctl & DSC_SDTYPE_MASK; if (sdram_ctl & DSC_RD_EN) { @@ -432,6 +451,9 @@ case 0x05000000: mtype = MEM_DDR4; break; + case 0x04000000: + mtype = MEM_LPDDR4; + break; default: mtype = MEM_UNKNOWN; break; @@ -445,7 +467,7 @@ csrow = mci->csrows[index]; dimm = csrow->channels[0]->dimm; - cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 + + cs_bnds = ddr_in32(pdata, FSL_MC_CS_BNDS_0 + (index * FSL_MC_CS_BNDS_OFS)); start = (cs_bnds & 0xffff0000) >> 16; @@ -465,7 +487,9 @@ dimm->grain = 8; dimm->mtype = mtype; dimm->dtype = DEV_UNKNOWN; - if (sdram_ctl & DSC_X32_EN) + if (pdata->flag == TYPE_IMX9) + dimm->dtype = DEV_X16; + else if (sdram_ctl & DSC_X32_EN) dimm->dtype = DEV_X32; dimm->edac_mode = EDAC_SECDED; } @@ -477,7 +501,7 @@ struct edac_mc_layer layers[2]; struct fsl_mc_pdata *pdata; struct resource r; - u32 sdram_ctl; + u32 sdram_ctl, ecc_en_mask; int res; if (!devres_open_group(&op->dev, fsl_mc_err_probe, GFP_KERNEL)) @@ -504,6 +528,8 @@ mci->ctl_name = pdata->name; mci->dev_name = pdata->name; + pdata->flag = (unsigned long)device_get_match_data(&op->dev); + /* * Get the endianness of DDR controller registers. * Default is big endian. @@ -532,8 +558,14 @@ goto err; } - sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG); - if (!(sdram_ctl & DSC_ECC_EN)) { + if (pdata->flag == TYPE_IMX9) { + sdram_ctl = ddr_in32(pdata, IMX9_MC_ERR_EN); + ecc_en_mask = ERR_ECC_EN | ERR_INLINE_ECC; + } else { + sdram_ctl = ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG); + ecc_en_mask = DSC_ECC_EN; + } + if ((sdram_ctl & ecc_en_mask) != ecc_en_mask) { /* no ECC */ pr_warn("%s: No ECC DIMMs discovered\n", __func__); res = -ENODEV; @@ -544,7 +576,8 @@ mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR | MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 | MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 | - MEM_FLAG_DDR4 | MEM_FLAG_RDDR4; + MEM_FLAG_DDR4 | MEM_FLAG_RDDR4 | + MEM_FLAG_LPDDR4; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; mci->edac_cap = EDAC_FLAG_SECDED; mci->mod_name = EDAC_MOD_STR; @@ -559,11 +592,11 @@ fsl_ddr_init_csrows(mci); /* store the original error disable bits */ - orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE); - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0); + orig_ddr_err_disable = ddr_in32(pdata, FSL_MC_ERR_DISABLE); + ddr_out32(pdata, FSL_MC_ERR_DISABLE, 0); /* clear all error bits */ - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0); + ddr_out32(pdata, FSL_MC_ERR_DETECT, ~0); res = edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups); if (res) { @@ -572,15 +605,15 @@ } if (edac_op_state == EDAC_OPSTATE_INT) { - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, + ddr_out32(pdata, FSL_MC_ERR_INT_EN, DDR_EIE_MBEE | DDR_EIE_SBEE); /* store the original error management threshold */ - orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase + + orig_ddr_err_sbe = ddr_in32(pdata, FSL_MC_ERR_SBE) & 0xff0000; /* set threshold to 1 error per interrupt */ - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000); + ddr_out32(pdata, FSL_MC_ERR_SBE, 0x10000); /* register interrupts */ pdata->irq = platform_get_irq(op, 0); @@ -621,12 +654,12 @@ edac_dbg(0, "\n"); if (edac_op_state == EDAC_OPSTATE_INT) { - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0); + ddr_out32(pdata, FSL_MC_ERR_INT_EN, 0); } - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, + ddr_out32(pdata, FSL_MC_ERR_DISABLE, orig_ddr_err_disable); - ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe); + ddr_out32(pdata, FSL_MC_ERR_SBE, orig_ddr_err_sbe); edac_mc_del_mc(&op->dev); edac_mc_free(mci); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/edac/fsl_ddr_edac.h linux-imx-phytec/drivers/edac/fsl_ddr_edac.h --- linux-6.1.55/drivers/edac/fsl_ddr_edac.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/edac/fsl_ddr_edac.h 2024-06-19 12:33:59.860219242 +0200 @@ -39,6 +39,9 @@ #define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54 #define FSL_MC_ERR_SBE 0x0e58 +#define IMX9_MC_ERR_EN 0x1000 +#define IMX9_MC_DATA_ERR_INJECT_HI 0x1100 + #define DSC_MEM_EN 0x80000000 #define DSC_ECC_EN 0x20000000 #define DSC_RD_EN 0x10000000 @@ -46,6 +49,9 @@ #define DSC_DBW_32 0x00080000 #define DSC_DBW_64 0x00000000 +#define ERR_ECC_EN 0x80000000 +#define ERR_INLINE_ECC 0x40000000 + #define DSC_SDTYPE_MASK 0x07000000 #define DSC_X32_EN 0x00000020 @@ -65,11 +71,14 @@ #define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */ #define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */ +#define TYPE_IMX9 0x1 /* MC used by iMX9 having registers changed */ + struct fsl_mc_pdata { char *name; int edac_idx; void __iomem *mc_vbase; int irq; + unsigned long flag; }; int fsl_mc_err_probe(struct platform_device *op); int fsl_mc_err_remove(struct platform_device *op); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/edac/layerscape_edac.c linux-imx-phytec/drivers/edac/layerscape_edac.c --- linux-6.1.55/drivers/edac/layerscape_edac.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/edac/layerscape_edac.c 2024-06-19 12:33:59.864219310 +0200 @@ -21,6 +21,7 @@ static const struct of_device_id fsl_ddr_mc_err_of_match[] = { { .compatible = "fsl,qoriq-memory-controller", }, + { .compatible = "nxp,imx9-memory-controller", .data = (void *)TYPE_IMX9, }, {}, }; MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/ele_base_msg.c linux-imx-phytec/drivers/firmware/imx/ele_base_msg.c --- linux-6.1.55/drivers/firmware/imx/ele_base_msg.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/firmware/imx/ele_base_msg.c 2024-06-19 12:33:59.892219789 +0200 @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021-2022 NXP + * Author: Pankaj + Alice Guo + */ + +#include +#include + +#include +#include + +#include "ele_mu.h" + +/* Fill a command message header with a given command ID and length in bytes. */ +static int plat_fill_cmd_msg_hdr(struct mu_hdr *hdr, uint8_t cmd, uint32_t len) +{ + struct ele_mu_priv *priv = NULL; + int err; + + err = get_ele_mu_priv(&priv); + if (err) { + pr_err("Error: iMX EdgeLock Enclave MU is not probed successfully.\n"); + return err; + } + + hdr->tag = priv->cmd_tag; + hdr->ver = MESSAGING_VERSION_6; + hdr->command = cmd; + hdr->size = (uint8_t)(len / sizeof(uint32_t)); + + return err; +} + +static u32 plat_add_msg_crc(uint32_t *msg, uint32_t msg_len) +{ + uint32_t i; + uint32_t crc = 0; + uint32_t nb_words = msg_len / (uint32_t)sizeof(uint32_t); + + for (i = 0; i < nb_words - 1; i++) + crc ^= *(msg + i); + + return crc; +} + +int imx_ele_msg_send_rcv(struct ele_mu_priv *priv) +{ + unsigned int wait; + int err; + + mutex_lock(&priv->mu_cmd_lock); + mutex_lock(&priv->mu_lock); + + err = mbox_send_message(priv->tx_chan, &priv->tx_msg); + if (err < 0) { + pr_err("Error: mbox_send_message failure.\n"); + mutex_unlock(&priv->mu_lock); + return err; + } + mutex_unlock(&priv->mu_lock); + + wait = msecs_to_jiffies(1000); + if (!wait_for_completion_timeout(&priv->done, wait)) { + pr_err("Error: wait_for_completion timed out.\n"); + err = -ETIMEDOUT; + } + + mutex_unlock(&priv->mu_cmd_lock); + + return err; +} + +static int read_otp_uniq_id(struct ele_mu_priv *priv, u32 *value) +{ + unsigned int tag, command, size, ver, status; + + tag = MSG_TAG(priv->rx_msg.header); + command = MSG_COMMAND(priv->rx_msg.header); + size = MSG_SIZE(priv->rx_msg.header); + ver = MSG_VER(priv->rx_msg.header); + status = RES_STATUS(priv->rx_msg.data[0]); + + if (tag == 0xe1 && command == ELE_READ_FUSE_REQ && + size == 0x07 && ver == ELE_VERSION && status == ELE_SUCCESS_IND) { + value[0] = priv->rx_msg.data[1]; + value[1] = priv->rx_msg.data[2]; + value[2] = priv->rx_msg.data[3]; + value[3] = priv->rx_msg.data[4]; + return 0; + } + + return -EINVAL; +} + +static int read_fuse_word(struct ele_mu_priv *priv, u32 *value) +{ + unsigned int tag, command, size, ver, status; + + tag = MSG_TAG(priv->rx_msg.header); + command = MSG_COMMAND(priv->rx_msg.header); + size = MSG_SIZE(priv->rx_msg.header); + ver = MSG_VER(priv->rx_msg.header); + status = RES_STATUS(priv->rx_msg.data[0]); + + if (tag == 0xe1 && command == ELE_READ_FUSE_REQ && + size == 0x03 && ver == 0x06 && status == ELE_SUCCESS_IND) { + value[0] = priv->rx_msg.data[1]; + return 0; + } + + return -EINVAL; +} + +int read_common_fuse(uint16_t fuse_id, u32 *value, bool special_id) +{ + struct ele_mu_priv *priv = NULL; + int err; + + err = get_ele_mu_priv(&priv); + if (err) { + pr_err("Error: iMX EdgeLock Enclave MU is not probed successfully.\n"); + return err; + } + err = plat_fill_cmd_msg_hdr((struct mu_hdr *)&priv->tx_msg.header, ELE_READ_FUSE_REQ, 8); + if (err) { + pr_err("Error: plat_fill_cmd_msg_hdr failed.\n"); + return err; + } + + priv->tx_msg.data[0] = fuse_id; + err = imx_ele_msg_send_rcv(priv); + if (err < 0) + return err; + + switch (fuse_id) { + case OTP_UNIQ_ID: + if (special_id) + err = read_otp_uniq_id(priv, value); + else + err = read_fuse_word(priv, value); + + break; + default: + err = read_fuse_word(priv, value); + break; + } + + return err; +} +EXPORT_SYMBOL_GPL(read_common_fuse); + +int ele_ping(void) +{ + struct ele_mu_priv *priv = NULL; + unsigned int tag, command, size, ver, status; + int err; + + err = get_ele_mu_priv(&priv); + if (err) { + pr_err("Error: iMX EdgeLock Enclave MU is not probed successfully.\n"); + return err; + } + err = plat_fill_cmd_msg_hdr((struct mu_hdr *)&priv->tx_msg.header, ELE_PING_REQ, 4); + if (err) { + pr_err("Error: plat_fill_cmd_msg_hdr failed.\n"); + return err; + } + + err = imx_ele_msg_send_rcv(priv); + if (err < 0) + return err; + + tag = MSG_TAG(priv->rx_msg.header); + command = MSG_COMMAND(priv->rx_msg.header); + size = MSG_SIZE(priv->rx_msg.header); + ver = MSG_VER(priv->rx_msg.header); + status = RES_STATUS(priv->rx_msg.data[0]); + + if (tag == 0xe1 && command == ELE_PING_REQ && + size == 0x2 && ver == ELE_VERSION && status == ELE_SUCCESS_IND) + return 0; + + return -EAGAIN; +} +EXPORT_SYMBOL_GPL(ele_ping); + +int ele_service_swap(phys_addr_t addr, u32 addr_size, u16 flag) +{ + struct ele_mu_priv *priv; + int ret; + unsigned int tag, command, size, ver, status; + + ret = get_ele_mu_priv(&priv); + if (ret) + return ret; + + ret = plat_fill_cmd_msg_hdr((struct mu_hdr *)&priv->tx_msg.header, + ELE_SERVICE_SWAP_REQ, 24); + if (ret) + return ret; + + priv->tx_msg.data[0] = flag; + priv->tx_msg.data[1] = addr_size; + priv->tx_msg.data[2] = 0x0; + priv->tx_msg.data[3] = lower_32_bits(addr); + priv->tx_msg.data[4] = plat_add_msg_crc((uint32_t *)&priv->tx_msg, 24); + ret = imx_ele_msg_send_rcv(priv); + if (ret < 0) + return ret; + + tag = MSG_TAG(priv->rx_msg.header); + command = MSG_COMMAND(priv->rx_msg.header); + size = MSG_SIZE(priv->rx_msg.header); + ver = MSG_VER(priv->rx_msg.header); + status = RES_STATUS(priv->rx_msg.data[0]); + if (tag == 0xe1 && command == ELE_SERVICE_SWAP_REQ && size == 0x03 && + ver == 0x06 && status == 0xd6) { + if (flag == ELE_IMEM_EXPORT) + return priv->rx_msg.data[1]; + else + return 0; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(ele_service_swap); + +int ele_get_info(phys_addr_t addr, u32 data_size) +{ + struct ele_mu_priv *priv; + int ret; + unsigned int tag, command, size, ver, status; + + ret = get_ele_mu_priv(&priv); + if (ret) + return ret; + + ret = plat_fill_cmd_msg_hdr((struct mu_hdr *)&priv->tx_msg.header, ELE_GET_INFO_REQ, 16); + if (ret) + return ret; + + priv->tx_msg.data[0] = upper_32_bits(addr); + priv->tx_msg.data[1] = lower_32_bits(addr); + priv->tx_msg.data[2] = data_size; + ret = imx_ele_msg_send_rcv(priv); + if (ret < 0) + return ret; + + tag = MSG_TAG(priv->rx_msg.header); + command = MSG_COMMAND(priv->rx_msg.header); + size = MSG_SIZE(priv->rx_msg.header); + ver = MSG_VER(priv->rx_msg.header); + status = RES_STATUS(priv->rx_msg.data[0]); + if (tag == 0xe1 && command == ELE_GET_INFO_REQ && size == 0x02 && + ver == 0x06 && status == 0xd6) + return 0; + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(ele_get_info); + +/* + * ele_get_trng_state() - prepare and send the command to read + * crypto lib and TRNG state + * TRNG state + * 0x1 TRNG is in program mode + * 0x2 TRNG is still generating entropy + * 0x3 TRNG entropy is valid and ready to be read + * 0x4 TRNG encounter an error while generating entropy + * + * CSAL state + * 0x0 Crypto Lib random context initialization is not done yet + * 0x1 Crypto Lib random context initialization is on-going + * 0x2 Crypto Lib random context initialization succeed + * 0x3 Crypto Lib random context initialization failed + * + * returns: csal and trng state. + * + */ +int ele_get_trng_state(void) +{ + struct ele_mu_priv *priv; + int ret; + unsigned int tag, command, size, ver, status; + + /* access ele_mu_priv data structure pointer*/ + ret = get_ele_mu_priv(&priv); + if (ret) + return ret; + + ret = plat_fill_cmd_msg_hdr((struct mu_hdr *)&priv->tx_msg.header, + ELE_GET_TRNG_STATE_REQ, 4); + if (ret) + return ret; + + ret = imx_ele_msg_send_rcv(priv); + if (ret < 0) + return ret; + + tag = MSG_TAG(priv->rx_msg.header); + command = MSG_COMMAND(priv->rx_msg.header); + size = MSG_SIZE(priv->rx_msg.header); + ver = MSG_VER(priv->rx_msg.header); + status = RES_STATUS(priv->rx_msg.data[0]); + if (tag == 0xe1 && command == ELE_GET_TRNG_STATE_REQ && size == 0x03 && + ver == 0x06 && status == 0xd6) { + return (priv->rx_msg.data[1] & CSAL_TRNG_STATE_MASK); + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(ele_get_trng_state); + +/* + * ele_start_rng() - prepare and send the command to start + * initialization of the Sentinel RNG context + * + * returns: 0 on success. + */ +int ele_start_rng(void) +{ + struct ele_mu_priv *priv; + int ret; + unsigned int tag, command, size, ver, status; + + /* access ele_mu_priv data structure pointer*/ + ret = get_ele_mu_priv(&priv); + if (ret) + return ret; + + ret = plat_fill_cmd_msg_hdr((struct mu_hdr *)&priv->tx_msg.header, ELE_START_RNG_REQ, 4); + if (ret) + return ret; + + ret = imx_ele_msg_send_rcv(priv); + if (ret < 0) + return ret; + + tag = MSG_TAG(priv->rx_msg.header); + command = MSG_COMMAND(priv->rx_msg.header); + size = MSG_SIZE(priv->rx_msg.header); + ver = MSG_VER(priv->rx_msg.header); + status = RES_STATUS(priv->rx_msg.data[0]); + if (tag == 0xe1 && command == ELE_START_RNG_REQ && size == 0x02 && + ver == 0x06 && status == 0xd6) { + return 0; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(ele_start_rng); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/ele_fw_api.c linux-imx-phytec/drivers/firmware/imx/ele_fw_api.c --- linux-6.1.55/drivers/firmware/imx/ele_fw_api.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/firmware/imx/ele_fw_api.c 2024-06-19 12:33:59.892219789 +0200 @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2023 NXP + */ + +#include +#include + +#include "ele_mu.h" + +/* Fill a command message header with a given command ID and length in bytes. */ +static int plat_fill_cmd_msg_hdr(struct mu_hdr *hdr, uint8_t cmd, uint32_t len) +{ + struct ele_mu_priv *priv = NULL; + int err = 0; + + err = get_ele_mu_priv(&priv); + if (err) { + pr_err("Error: iMX EdgeLock Enclave MU is not probed successfully.\n"); + return err; + } + hdr->tag = priv->cmd_tag; + hdr->ver = MESSAGING_VERSION_7; + hdr->command = cmd; + hdr->size = (uint8_t)(len / sizeof(uint32_t)); + + return err; +} + +/* + * ele_get_random() - prepare and send the command to proceed + * with a random number generation operation + * + * returns: size of the rondom number generated + */ +int ele_get_random(struct hwrng *rng, void *data, size_t len, bool wait) +{ + struct ele_mu_priv *priv; + unsigned int tag, command, size, ver, status; + dma_addr_t dst_dma; + u8 *buf; + int ret; + + /* access ele_mu_priv data structure pointer*/ + ret = get_ele_mu_priv(&priv); + if (ret) + return ret; + + buf = dmam_alloc_coherent(priv->dev, len, &dst_dma, GFP_KERNEL); + if (!buf) { + dev_err(priv->dev, "Failed to map destination buffer memory\n"); + return -ENOMEM; + } + + ret = plat_fill_cmd_msg_hdr((struct mu_hdr *)&priv->tx_msg.header, ELE_GET_RANDOM_REQ, 16); + if (ret) + goto exit; + + priv->tx_msg.data[0] = 0x0; + priv->tx_msg.data[1] = dst_dma; + priv->tx_msg.data[2] = len; + ret = imx_ele_msg_send_rcv(priv); + if (ret < 0) + goto exit; + + tag = MSG_TAG(priv->rx_msg.header); + command = MSG_COMMAND(priv->rx_msg.header); + size = MSG_SIZE(priv->rx_msg.header); + ver = MSG_VER(priv->rx_msg.header); + status = RES_STATUS(priv->rx_msg.data[0]); + if (tag == 0xe1 && command == ELE_GET_RANDOM_REQ && size == 0x02 && + ver == 0x07 && status == 0xd6) { + memcpy(data, buf, len); + ret = len; + } else + ret = -EINVAL; + +exit: + dmam_free_coherent(priv->dev, len, buf, dst_dma); + return ret; +} + +int ele_init_fw(void) +{ + struct ele_mu_priv *priv; + int ret; + unsigned int tag, command, size, ver, status; + + ret = get_ele_mu_priv(&priv); + if (ret) + return ret; + + ret = plat_fill_cmd_msg_hdr((struct mu_hdr *)&priv->tx_msg.header, ELE_INIT_FW_REQ, 4); + if (ret) + return ret; + + ret = imx_ele_msg_send_rcv(priv); + if (ret < 0) + return ret; + + tag = MSG_TAG(priv->rx_msg.header); + command = MSG_COMMAND(priv->rx_msg.header); + size = MSG_SIZE(priv->rx_msg.header); + ver = MSG_VER(priv->rx_msg.header); + status = RES_STATUS(priv->rx_msg.data[0]); + + if (tag == 0xe1 && command == ELE_INIT_FW_REQ && size == 0x02 && + ver == MESSAGING_VERSION_7 && status == 0xd6) + return 0; + + return -EINVAL; +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/ele_mu.c linux-imx-phytec/drivers/firmware/imx/ele_mu.c --- linux-6.1.55/drivers/firmware/imx/ele_mu.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/firmware/imx/ele_mu.c 2024-06-19 12:33:59.892219789 +0200 @@ -0,0 +1,1297 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021-2023 NXP + * Author: Alice Guo + * Author: Pankaj Gupta + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ele_mu.h" + +#define ELE_PING_INTERVAL (3600 * HZ) +#define ELE_TRNG_STATE_OK 0x203 +#define ELE_GET_INFO_BUFF_SZ 0x100 +#define ELE_GET_INFO_READ_SZ 0xA0 +#define ELE_IMEM_SIZE 0x10000 +#define ELE_IMEM_STATE_OK 0xCA +#define ELE_IMEM_STATE_BAD 0xFE +#define ELE_IMEM_STATE_WORD 0x27 +#define ELE_IMEM_STATE_MASK 0x00ff0000 + +#define RESERVED_DMA_POOL BIT(1) + +struct ele_mu_priv *ele_priv_export; + +struct imx_info { + bool socdev; + /* platform specific flag to enable/disable the Sentinel True RNG */ + bool enable_ele_trng; + bool reserved_dma_ranges; + bool init_fw; +}; + +static const struct imx_info imx8ulp_info = { + .socdev = true, + .enable_ele_trng = false, + .reserved_dma_ranges = true, + .init_fw = false, +}; + +static const struct imx_info imx93_info = { + .socdev = false, + .enable_ele_trng = true, + .reserved_dma_ranges = true, + .init_fw = true, +}; + +static const struct of_device_id ele_mu_match[] = { + { .compatible = "fsl,imx-ele", .data = (void *)&imx8ulp_info}, + { .compatible = "fsl,imx93-ele", .data = (void *)&imx93_info}, + {}, +}; + +int get_ele_mu_priv(struct ele_mu_priv **export) +{ + if (!ele_priv_export) + return -EPROBE_DEFER; + + *export = ele_priv_export; + return 0; +} +EXPORT_SYMBOL_GPL(get_ele_mu_priv); + +/* + * Callback called by mailbox FW when data are received + */ +static void ele_mu_rx_callback(struct mbox_client *c, void *msg) +{ + struct device *dev = c->dev; + struct ele_mu_priv *priv = dev_get_drvdata(dev); + struct ele_mu_device_ctx *dev_ctx; + bool is_response = false; + int msg_size; + struct mu_hdr header; + + dev_dbg(dev, "Message received on mailbox\n"); + + /* The function can be called with NULL msg */ + if (!msg) { + dev_err(dev, "Message is invalid\n"); + return; + } + + if (IS_ERR(msg)) { + dev_err(dev, "Error during reception of message: %ld\n", + PTR_ERR(msg)); + return; + } + + header.tag = ((u8 *)msg)[3]; + header.command = ((u8 *)msg)[2]; + header.size = ((u8 *)msg)[1]; + header.ver = ((u8 *)msg)[0]; + + dev_dbg(dev, "Selecting device\n"); + + /* Incoming command: wake up the receiver if any. */ + if (header.tag == priv->cmd_tag) { + dev_dbg(dev, "Selecting cmd receiver\n"); + dev_ctx = priv->cmd_receiver_dev; + } else if (header.tag == priv->rsp_tag) { + if (priv->waiting_rsp_dev) { + dev_dbg(dev, "Selecting rsp waiter\n"); + dev_ctx = priv->waiting_rsp_dev; + is_response = true; + } else { + /* Reading the EdgeLock Enclave response + * to the command sent by other + * linux kernel services. + */ + spin_lock(&priv->lock); + priv->rx_msg = *(struct ele_api_msg *)msg; + complete(&priv->done); + spin_unlock(&priv->lock); + return; + } + } else { + dev_err(dev, "Failed to select a device for message: %.8x\n", + *((u32 *) &header)); + return; + } + + if (!dev_ctx) { + dev_err(dev, "No device context selected for message: %.8x\n", + *((u32 *)&header)); + return; + } + /* Init reception */ + msg_size = header.size; + if (msg_size > MAX_RECV_SIZE) { + devctx_err(dev_ctx, "Message is too big (%d > %d)", msg_size, + MAX_RECV_SIZE); + return; + } + + memcpy(dev_ctx->temp_resp, msg, msg_size * sizeof(u32)); + dev_ctx->temp_resp_size = msg_size; + + /* Allow user to read */ + dev_ctx->pending_hdr = dev_ctx->temp_resp[0]; + wake_up_interruptible(&dev_ctx->wq); + + if (is_response) + priv->waiting_rsp_dev = NULL; + +} + +static void ele_ping_handler(struct work_struct *work) +{ + int ret; + + ret = ele_ping(); + if (ret) + pr_err("ping ele failed, try again!\n"); + + /* reschedule the delay work */ + schedule_delayed_work(to_delayed_work(work), ELE_PING_INTERVAL); +} +static DECLARE_DELAYED_WORK(ele_ping_work, ele_ping_handler); + +static int imx_soc_device_register(struct platform_device *pdev) +{ + struct soc_device_attribute *attr; + struct soc_device *dev; + struct gen_pool *sram_pool; + u32 *get_info_data; + phys_addr_t get_info_addr; + u8 major_ver, minor_ver; + u32 v[4]; + int err; + + err = read_common_fuse(OTP_UNIQ_ID, v, true); + if (err) + return err; + + sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram-pool", 0); + if (!sram_pool) { + pr_err("Unable to get sram pool\n"); + return -EINVAL; + } + + get_info_data = (u32 *)gen_pool_alloc(sram_pool, 0x100); + if (!get_info_data) { + pr_err("Unable to alloc sram from sram pool\n"); + return -ENOMEM; + } + + get_info_addr = gen_pool_virt_to_phys(sram_pool, (ulong)get_info_data); + + attr = kzalloc(sizeof(*attr), GFP_KERNEL); + if (!attr) + return -ENOMEM; + + err = ele_get_info(get_info_addr, ELE_GET_INFO_READ_SZ); + if (err) { + attr->revision = kasprintf(GFP_KERNEL, "A0"); + } else { + major_ver = (get_info_data[1] & 0xffff0000) >> 24; + minor_ver = (get_info_data[1] & 0xffff0000) & 0xFF; + if (minor_ver) + attr->revision = kasprintf(GFP_KERNEL, "%x.%x", major_ver, minor_ver); + else + attr->revision = kasprintf(GFP_KERNEL, "%x", major_ver); + } + + gen_pool_free(sram_pool, (unsigned long)get_info_data, 0x100); + + err = of_property_read_string(of_root, "model", &attr->machine); + if (err) { + kfree(attr); + return -EINVAL; + } + attr->family = kasprintf(GFP_KERNEL, "Freescale i.MX"); + + attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", (u64)v[3] << 32 | v[0]); + attr->soc_id = kasprintf(GFP_KERNEL, "i.MX8ULP"); + + dev = soc_device_register(attr); + if (IS_ERR(dev)) { + kfree(attr->soc_id); + kfree(attr->serial_number); + kfree(attr->revision); + kfree(attr->family); + kfree(attr->machine); + kfree(attr); + return PTR_ERR(dev); + } + + return 0; +} + +static int ele_do_start_rng(void) +{ + int ret; + int count = 5; + + ret = ele_get_trng_state(); + if (ret < 0) { + pr_err("Failed to get trng state\n"); + return ret; + } else if (ret != ELE_TRNG_STATE_OK) { + /* call start rng */ + ret = ele_start_rng(); + if (ret) { + pr_err("Failed to start rng\n"); + return ret; + } + + /* poll get trng state API 5 times or while trng state != 0x203 */ + do { + msleep(10); + ret = ele_get_trng_state(); + if (ret < 0) { + pr_err("Failed to get trng state\n"); + return ret; + } + count--; + } while ((ret != ELE_TRNG_STATE_OK) && count); + if (ret != ELE_TRNG_STATE_OK) + return -EIO; + } + + return 0; +} + +/* + * File operations for user-space + */ + +/* Write a message to the MU. */ +static ssize_t ele_mu_fops_write(struct file *fp, const char __user *buf, + size_t size, loff_t *ppos) +{ + struct ele_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct ele_mu_device_ctx, + miscdev); + struct ele_mu_priv *ele_mu_priv = dev_ctx->priv; + u32 nb_words = 0; + struct mu_hdr header; + int err; + + devctx_dbg(dev_ctx, "write from buf (%p)%ld, ppos=%lld\n", buf, size, + ((ppos) ? *ppos : 0)); + + if (down_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + if (dev_ctx->status != MU_OPENED) { + err = -EINVAL; + goto exit; + } + + if (size < 4) {//sizeof(struct she_mu_hdr)) { + devctx_err(dev_ctx, "User buffer too small(%ld < %x)\n", size, 0x4); + //devctx_err(dev_ctx, "User buffer too small(%ld < %lu)\n", size, ()0x4); + // sizeof(struct she_mu_hdr)); + err = -ENOSPC; + goto exit; + } + + if (size > MAX_MESSAGE_SIZE_BYTES) { + devctx_err(dev_ctx, "User buffer too big(%ld > %lu)\n", size, + MAX_MESSAGE_SIZE_BYTES); + err = -ENOSPC; + goto exit; + } + + /* Copy data to buffer */ + err = (int)copy_from_user(dev_ctx->temp_cmd, buf, size); + if (err) { + err = -EFAULT; + devctx_err(dev_ctx, "Fail copy message from user\n"); + goto exit; + } + + print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4, + dev_ctx->temp_cmd, size, false); + + header = *((struct mu_hdr *) (&dev_ctx->temp_cmd[0])); + + /* Check the message is valid according to tags */ + if (header.tag == ele_mu_priv->cmd_tag) { + /* + * unlocked in ele_mu_fops_read when the + * response to this command is read. + */ + mutex_lock(&ele_mu_priv->mu_cmd_lock); + ele_mu_priv->waiting_rsp_dev = dev_ctx; + } else if (header.tag == ele_mu_priv->rsp_tag) { + /* Check the device context can send the command */ + if (dev_ctx != ele_mu_priv->cmd_receiver_dev) { + devctx_err(dev_ctx, + "This channel is not configured to send response to SECO\n"); + err = -EPERM; + goto exit; + } + } else { + devctx_err(dev_ctx, "The message does not have a valid TAG\n"); + err = -EINVAL; + goto exit; + } + + /* + * Check that the size passed as argument matches the size + * carried in the message. + */ + nb_words = header.size; + if (nb_words * sizeof(u32) != size) { + err = -EINVAL; + devctx_err(dev_ctx, "User buffer too small\n"); + goto exit; + } + + mutex_lock(&ele_mu_priv->mu_lock); + + /* Send message */ + devctx_dbg(dev_ctx, "sending message\n"); + err = mbox_send_message(ele_mu_priv->tx_chan, dev_ctx->temp_cmd); + if (err < 0) { + devctx_err(dev_ctx, "Failed to send message\n"); + goto unlock; + } + + err = nb_words * (u32)sizeof(u32); + +unlock: + mutex_unlock(&ele_mu_priv->mu_lock); + +exit: + if (err < 0) + mutex_unlock(&ele_mu_priv->mu_cmd_lock); + up(&dev_ctx->fops_lock); + return err; +} + +/* + * Read a message from the MU. + * Blocking until a message is available. + */ +static ssize_t ele_mu_fops_read(struct file *fp, char __user *buf, + size_t size, loff_t *ppos) +{ + struct ele_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct ele_mu_device_ctx, + miscdev); + struct ele_mu_priv *ele_mu_priv = dev_ctx->priv; + u32 data_size = 0, size_to_copy = 0; + struct ele_buf_desc *b_desc; + int err; + struct mu_hdr header = {0}; + + devctx_dbg(dev_ctx, "read to buf %p(%ld), ppos=%lld\n", buf, size, + ((ppos) ? *ppos : 0)); + + if (down_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + if (dev_ctx->status != MU_OPENED) { + err = -EINVAL; + goto exit; + } + + /* Wait until the complete message is received on the MU. */ + err = wait_event_interruptible(dev_ctx->wq, dev_ctx->pending_hdr != 0); + if (err) { + devctx_err(dev_ctx, "Err[0x%x]:Interrupted by signal.\n", err); + goto exit; + } + + devctx_dbg(dev_ctx, "%s %s\n", __func__, + "message received, start transmit to user"); + + /* Check that the size passed as argument is larger than + * the one carried in the message. + */ + data_size = dev_ctx->temp_resp_size * sizeof(u32); + size_to_copy = data_size; + if (size_to_copy > size) { + devctx_dbg(dev_ctx, "User buffer too small (%ld < %d)\n", + size, size_to_copy); + size_to_copy = size; + } + + /* We may need to copy the output data to user before + * delivering the completion message. + */ + while (!list_empty(&dev_ctx->pending_out)) { + b_desc = list_first_entry_or_null(&dev_ctx->pending_out, + struct ele_buf_desc, + link); + if (b_desc->usr_buf_ptr && b_desc->shared_buf_ptr) { + devctx_dbg(dev_ctx, "Copy output data to user\n"); + err = (int)copy_to_user(b_desc->usr_buf_ptr, + b_desc->shared_buf_ptr, + b_desc->size); + if (err) { + devctx_err(dev_ctx, + "Failed to copy output data to user\n"); + err = -EFAULT; + goto exit; + } + } + + if (b_desc->shared_buf_ptr) + memset(b_desc->shared_buf_ptr, 0, b_desc->size); + + __list_del_entry(&b_desc->link); + devm_kfree(dev_ctx->dev, b_desc); + } + + header = *((struct mu_hdr *) (&dev_ctx->temp_resp[0])); + + /* Copy data from the buffer */ + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4, + dev_ctx->temp_resp, size_to_copy, false); + err = (int)copy_to_user(buf, dev_ctx->temp_resp, size_to_copy); + if (err) { + devctx_err(dev_ctx, "Failed to copy to user\n"); + err = -EFAULT; + goto exit; + } + + err = size_to_copy; + + /* free memory allocated on the shared buffers. */ + dev_ctx->secure_mem.pos = 0; + dev_ctx->non_secure_mem.pos = 0; + + dev_ctx->pending_hdr = 0; + +exit: + /* + * Clean the used Shared Memory space, + * whether its Input Data copied from user buffers, or + * Data received from FW. + */ + while (!list_empty(&dev_ctx->pending_in) || + !list_empty(&dev_ctx->pending_out)) { + if (!list_empty(&dev_ctx->pending_in)) + b_desc = list_first_entry_or_null(&dev_ctx->pending_in, + struct ele_buf_desc, + link); + else + b_desc = list_first_entry_or_null(&dev_ctx->pending_out, + struct ele_buf_desc, + link); + + if (b_desc->shared_buf_ptr) + memset(b_desc->shared_buf_ptr, 0, b_desc->size); + + __list_del_entry(&b_desc->link); + devm_kfree(dev_ctx->dev, b_desc); + } + if (header.tag == ele_mu_priv->rsp_tag) + mutex_unlock(&ele_mu_priv->mu_cmd_lock); + + up(&dev_ctx->fops_lock); + return err; +} + +/* Give access to EdgeLock Enclave, to the memory we want to share */ +static int ele_mu_setup_ele_mem_access(struct ele_mu_device_ctx *dev_ctx, + u64 addr, u32 len) +{ + /* Assuming EdgeLock Enclave has access to all the memory regions */ + int ret = 0; + + if (ret) { + devctx_err(dev_ctx, "Fail find memreg\n"); + goto exit; + } + + if (ret) { + devctx_err(dev_ctx, "Fail set permission for resource\n"); + goto exit; + } + +exit: + return ret; +} + +static int ele_mu_ioctl_get_mu_info(struct ele_mu_device_ctx *dev_ctx, + unsigned long arg) +{ + struct ele_mu_priv *priv = dev_get_drvdata(dev_ctx->dev); + struct ele_mu_ioctl_get_mu_info info; + int err = -EINVAL; + + info.ele_mu_id = (u8)priv->ele_mu_id; + info.interrupt_idx = 0; + info.tz = 0; + info.did = (u8)priv->ele_mu_did; + + devctx_dbg(dev_ctx, + "info [mu_idx: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n", + info.ele_mu_id, info.interrupt_idx, info.tz, info.did); + + err = (int)copy_to_user((u8 *)arg, &info, + sizeof(info)); + if (err) { + devctx_err(dev_ctx, "Failed to copy mu info to user\n"); + err = -EFAULT; + goto exit; + } + +exit: + return err; +} + +/* + * Copy a buffer of daa to/from the user and return the address to use in + * messages + */ +static int ele_mu_ioctl_setup_iobuf_handler(struct ele_mu_device_ctx *dev_ctx, + unsigned long arg) +{ + struct ele_buf_desc *b_desc; + struct ele_mu_ioctl_setup_iobuf io = {0}; + struct ele_shared_mem *shared_mem; + int err = -EINVAL; + u32 pos; + + err = (int)copy_from_user(&io, + (u8 *)arg, + sizeof(io)); + if (err) { + devctx_err(dev_ctx, "Failed copy iobuf config from user\n"); + err = -EFAULT; + goto exit; + } + + devctx_dbg(dev_ctx, "io [buf: %p(%d) flag: %x]\n", + io.user_buf, io.length, io.flags); + + if (io.length == 0 || !io.user_buf) { + /* + * Accept NULL pointers since some buffers are optional + * in SECO commands. In this case we should return 0 as + * pointer to be embedded into the message. + * Skip all data copy part of code below. + */ + io.ele_addr = 0; + goto copy; + } + + /* Select the shared memory to be used for this buffer. */ + if (io.flags & SECO_MU_IO_FLAGS_USE_SEC_MEM) { + /* App requires to use secure memory for this buffer.*/ + devctx_err(dev_ctx, "Failed allocate SEC MEM memory\n"); + err = -EFAULT; + goto exit; + } else { + /* No specific requirement for this buffer. */ + shared_mem = &dev_ctx->non_secure_mem; + } + + /* Check there is enough space in the shared memory. */ + if (io.length >= shared_mem->size - shared_mem->pos) { + devctx_err(dev_ctx, "Not enough space in shared memory\n"); + err = -ENOMEM; + goto exit; + } + + /* Allocate space in shared memory. 8 bytes aligned. */ + pos = shared_mem->pos; + shared_mem->pos += round_up(io.length, 8u); + io.ele_addr = (u64)shared_mem->dma_addr + pos; + + if ((io.flags & SECO_MU_IO_FLAGS_USE_SEC_MEM) && + !(io.flags & SECO_MU_IO_FLAGS_USE_SHORT_ADDR)) { + /*Add base address to get full address.*/ + devctx_err(dev_ctx, "Failed allocate SEC MEM memory\n"); + err = -EFAULT; + goto exit; + } + + memset(shared_mem->ptr + pos, 0, io.length); + if ((io.flags & SECO_MU_IO_FLAGS_IS_INPUT) || + (io.flags & SECO_MU_IO_FLAGS_IS_IN_OUT)) { + /* + * buffer is input: + * copy data from user space to this allocated buffer. + */ + err = (int)copy_from_user(shared_mem->ptr + pos, io.user_buf, + io.length); + if (err) { + devctx_err(dev_ctx, + "Failed copy data to shared memory\n"); + err = -EFAULT; + goto exit; + } + } + + b_desc = devm_kmalloc(dev_ctx->dev, sizeof(*b_desc), GFP_KERNEL); + if (!b_desc) { + err = -ENOMEM; + devctx_err(dev_ctx, + "Failed allocating mem for pending buffer\n" + ); + goto exit; + } + + b_desc->shared_buf_ptr = shared_mem->ptr + pos; + b_desc->usr_buf_ptr = io.user_buf; + b_desc->size = io.length; + + if (io.flags & SECO_MU_IO_FLAGS_IS_INPUT) { + /* + * buffer is input: + * add an entry in the "pending input buffers" list so + * that copied data can be cleaned from shared memory + * later. + */ + list_add_tail(&b_desc->link, &dev_ctx->pending_in); + } else { + /* + * buffer is output: + * add an entry in the "pending out buffers" list so data + * can be copied to user space when receiving ELE + * response. + */ + list_add_tail(&b_desc->link, &dev_ctx->pending_out); + } +copy: + /* Provide the EdgeLock Enclave address to user space only if success. */ + err = (int)copy_to_user((u8 *)arg, &io, + sizeof(io)); + if (err) { + devctx_err(dev_ctx, "Failed to copy iobuff setup to user\n"); + err = -EFAULT; + goto exit; + } +exit: + return err; +} + + + +/* Open a char device. */ +static int ele_mu_fops_open(struct inode *nd, struct file *fp) +{ + struct ele_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct ele_mu_device_ctx, + miscdev); + int err; + + /* Avoid race if opened at the same time */ + if (down_trylock(&dev_ctx->fops_lock)) + return -EBUSY; + + /* Authorize only 1 instance. */ + if (dev_ctx->status != MU_FREE) { + err = -EBUSY; + goto exit; + } + + /* + * Allocate some memory for data exchanges with S40x. + * This will be used for data not requiring secure memory. + */ + dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx->dev, + MAX_DATA_SIZE_PER_USER, + &dev_ctx->non_secure_mem.dma_addr, + GFP_KERNEL); + if (!dev_ctx->non_secure_mem.ptr) { + err = -ENOMEM; + devctx_err(dev_ctx, "Failed to map shared memory with S40x\n"); + goto exit; + } + + err = ele_mu_setup_ele_mem_access(dev_ctx, + dev_ctx->non_secure_mem.dma_addr, + MAX_DATA_SIZE_PER_USER); + if (err) { + err = -EPERM; + devctx_err(dev_ctx, + "Failed to share access to shared memory\n"); + goto free_coherent; + } + + dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER; + dev_ctx->non_secure_mem.pos = 0; + dev_ctx->status = MU_OPENED; + + dev_ctx->pending_hdr = 0; + + goto exit; + +free_coherent: + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER, + dev_ctx->non_secure_mem.ptr, + dev_ctx->non_secure_mem.dma_addr); + +exit: + up(&dev_ctx->fops_lock); + return err; +} + +/* Close a char device. */ +static int ele_mu_fops_close(struct inode *nd, struct file *fp) +{ + struct ele_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct ele_mu_device_ctx, miscdev); + struct ele_mu_priv *priv = dev_ctx->priv; + struct ele_buf_desc *b_desc; + + /* Avoid race if closed at the same time */ + if (down_trylock(&dev_ctx->fops_lock)) + return -EBUSY; + + /* The device context has not been opened */ + if (dev_ctx->status != MU_OPENED) + goto exit; + + /* check if this device was registered as command receiver. */ + if (priv->cmd_receiver_dev == dev_ctx) + priv->cmd_receiver_dev = NULL; + + /* check if this device was registered as waiting response. */ + if (priv->waiting_rsp_dev == dev_ctx) { + priv->waiting_rsp_dev = NULL; + mutex_unlock(&priv->mu_cmd_lock); + } + + /* Unmap secure memory shared buffer. */ + if (dev_ctx->secure_mem.ptr) + devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr); + + dev_ctx->secure_mem.ptr = NULL; + dev_ctx->secure_mem.dma_addr = 0; + dev_ctx->secure_mem.size = 0; + dev_ctx->secure_mem.pos = 0; + + /* Free non-secure shared buffer. */ + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER, + dev_ctx->non_secure_mem.ptr, + dev_ctx->non_secure_mem.dma_addr); + + dev_ctx->non_secure_mem.ptr = NULL; + dev_ctx->non_secure_mem.dma_addr = 0; + dev_ctx->non_secure_mem.size = 0; + dev_ctx->non_secure_mem.pos = 0; + + while (!list_empty(&dev_ctx->pending_in) || + !list_empty(&dev_ctx->pending_out)) { + if (!list_empty(&dev_ctx->pending_in)) + b_desc = list_first_entry_or_null(&dev_ctx->pending_in, + struct ele_buf_desc, + link); + else + b_desc = list_first_entry_or_null(&dev_ctx->pending_out, + struct ele_buf_desc, + link); + + if (b_desc->shared_buf_ptr) + memset(b_desc->shared_buf_ptr, 0, b_desc->size); + + __list_del_entry(&b_desc->link); + devm_kfree(dev_ctx->dev, b_desc); + } + + dev_ctx->status = MU_FREE; + +exit: + up(&dev_ctx->fops_lock); + return 0; +} + +/* IOCTL entry point of a char device */ +static long ele_mu_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) +{ + struct ele_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct ele_mu_device_ctx, + miscdev); + struct ele_mu_priv *ele_mu_priv = dev_ctx->priv; + int err = -EINVAL; + + /* Prevent race during change of device context */ + if (down_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + switch (cmd) { + case ELE_MU_IOCTL_ENABLE_CMD_RCV: + if (!ele_mu_priv->cmd_receiver_dev) { + ele_mu_priv->cmd_receiver_dev = dev_ctx; + err = 0; + }; + break; + case ELE_MU_IOCTL_GET_MU_INFO: + err = ele_mu_ioctl_get_mu_info(dev_ctx, arg); + break; + case ELE_MU_IOCTL_SHARED_BUF_CFG: + devctx_err(dev_ctx, "ELE_MU_IOCTL_SHARED_BUF_CFG not supported [0x%x].\n", err); + break; + case ELE_MU_IOCTL_SETUP_IOBUF: + err = ele_mu_ioctl_setup_iobuf_handler(dev_ctx, arg); + break; + case ELE_MU_IOCTL_SIGNED_MESSAGE: + devctx_err(dev_ctx, "ELE_MU_IOCTL_SIGNED_MESSAGE not supported [0x%x].\n", err); + break; + default: + err = -EINVAL; + devctx_dbg(dev_ctx, "IOCTL %.8x not supported\n", cmd); + } + + up(&dev_ctx->fops_lock); + return (long)err; +} + +/* Char driver setup */ +static const struct file_operations ele_mu_fops = { + .open = ele_mu_fops_open, + .owner = THIS_MODULE, + .release = ele_mu_fops_close, + .unlocked_ioctl = ele_mu_ioctl, + .read = ele_mu_fops_read, + .write = ele_mu_fops_write, +}; + +/* interface for managed res to free a mailbox channel */ +static void if_mbox_free_channel(void *mbox_chan) +{ + mbox_free_channel(mbox_chan); +} + +/* interface for managed res to unregister a char device */ +static void if_misc_deregister(void *miscdevice) +{ + misc_deregister(miscdevice); +} + +static int ele_mu_request_channel(struct device *dev, + struct mbox_chan **chan, + struct mbox_client *cl, + const char *name) +{ + struct mbox_chan *t_chan; + int ret = 0; + + t_chan = mbox_request_channel_byname(cl, name); + if (IS_ERR(t_chan)) { + ret = PTR_ERR(t_chan); + if (ret != -EPROBE_DEFER) + dev_err(dev, + "Failed to request chan %s ret %d\n", name, + ret); + goto exit; + } + + ret = devm_add_action(dev, if_mbox_free_channel, t_chan); + if (ret) { + dev_err(dev, "failed to add devm removal of mbox %s\n", name); + goto exit; + } + + *chan = t_chan; + +exit: + return ret; +} + +static int ele_mu_probe(struct platform_device *pdev) +{ + struct ele_mu_device_ctx *dev_ctx; + struct device *dev = &pdev->dev; + struct ele_mu_priv *priv; + struct device_node *np; + const struct of_device_id *of_id = of_match_device(ele_mu_match, dev); + struct imx_info *info = (of_id != NULL) ? (struct imx_info *)of_id->data + : NULL; + int max_nb_users = 0; + char *devname; + int ret; + int i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + dev_err(dev, "Fail allocate mem for private data\n"); + goto exit; + } + priv->dev = dev; + dev_set_drvdata(dev, priv); + + /* + * Get the address of MU to be used for communication with the SCU + */ + np = pdev->dev.of_node; + if (!np) { + dev_err(dev, "Cannot find MU User entry in device tree\n"); + ret = -EOPNOTSUPP; + goto exit; + } + + /* Initialize the mutex. */ + mutex_init(&priv->mu_cmd_lock); + mutex_init(&priv->mu_lock); + + /* TBD */ + priv->cmd_receiver_dev = NULL; + priv->waiting_rsp_dev = NULL; + + ret = of_property_read_u32(np, "fsl,ele_mu_did", &priv->ele_mu_did); + if (ret) { + ret = -EINVAL; + dev_err(dev, "%s: Not able to read ele_mu_did", __func__); + goto exit; + } + + ret = of_property_read_u32(np, "fsl,ele_mu_id", &priv->ele_mu_id); + if (ret) { + ret = -EINVAL; + dev_err(dev, "%s: Not able to read ele_mu_id", __func__); + goto exit; + } + + ret = of_property_read_u32(np, "fsl,ele_mu_max_users", &max_nb_users); + if (ret) { + dev_warn(dev, "%s: Not able to read mu_max_user", __func__); + max_nb_users = S4_MUAP_DEFAULT_MAX_USERS; + } + + ret = of_property_read_u8(np, "fsl,cmd_tag", &priv->cmd_tag); + if (ret) { + dev_warn(dev, "%s: Not able to read cmd_tag", __func__); + priv->cmd_tag = DEFAULT_MESSAGING_TAG_COMMAND; + } + + ret = of_property_read_u8(np, "fsl,rsp_tag", &priv->rsp_tag); + if (ret) { + dev_warn(dev, "%s: Not able to read rsp_tag", __func__); + priv->rsp_tag = DEFAULT_MESSAGING_TAG_RESPONSE; + } + + /* Mailbox client configuration */ + priv->ele_mb_cl.dev = dev; + priv->ele_mb_cl.tx_block = false; + priv->ele_mb_cl.knows_txdone = true; + priv->ele_mb_cl.rx_callback = ele_mu_rx_callback; + + ret = ele_mu_request_channel(dev, &priv->tx_chan, &priv->ele_mb_cl, "tx"); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to request tx channel\n"); + + goto exit; + } + + ret = ele_mu_request_channel(dev, &priv->rx_chan, &priv->ele_mb_cl, "rx"); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to request rx channel\n"); + + goto exit; + } + + priv->max_dev_ctx = max_nb_users; + priv->ctxs = devm_kzalloc(dev, sizeof(dev_ctx) * max_nb_users, GFP_KERNEL); + + /* Create users */ + for (i = 0; i < max_nb_users; i++) { + dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL); + if (!dev_ctx) { + ret = -ENOMEM; + dev_err(dev, + "Fail to allocate memory for device context\n"); + goto exit; + } + + dev_ctx->dev = dev; + dev_ctx->status = MU_FREE; + dev_ctx->priv = priv; + + priv->ctxs[i] = dev_ctx; + + /* Default value invalid for an header. */ + init_waitqueue_head(&dev_ctx->wq); + + INIT_LIST_HEAD(&dev_ctx->pending_out); + INIT_LIST_HEAD(&dev_ctx->pending_in); + sema_init(&dev_ctx->fops_lock, 1); + + devname = devm_kasprintf(dev, GFP_KERNEL, "ele_mu%d_ch%d", + priv->ele_mu_id, i); + if (!devname) { + ret = -ENOMEM; + dev_err(dev, + "Fail to allocate memory for misc dev name\n"); + goto exit; + } + + dev_ctx->miscdev.name = devname; + dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR; + dev_ctx->miscdev.fops = &ele_mu_fops; + dev_ctx->miscdev.parent = dev; + ret = misc_register(&dev_ctx->miscdev); + if (ret) { + dev_err(dev, "failed to register misc device %d\n", + ret); + goto exit; + } + + ret = devm_add_action(dev, if_misc_deregister, + &dev_ctx->miscdev); + if (ret) { + dev_err(dev, + "failed[%d] to add action to the misc-dev\n", + ret); + goto exit; + } + } + + init_completion(&priv->done); + spin_lock_init(&priv->lock); + + ele_priv_export = priv; + + if (info && info->reserved_dma_ranges) { + ret = of_reserved_mem_device_init(dev); + if (ret) { + dev_err(dev, "failed to init reserved memory region %d\n", ret); + priv->flags &= (~RESERVED_DMA_POOL); + goto exit; + } + priv->flags |= RESERVED_DMA_POOL; + } + + if (info && info->init_fw) { + /* start initializing ele fw */ + ret = ele_init_fw(); + if (ret) + dev_err(dev, "Failed to initialize ele fw.\n"); + } + + if (info && info->socdev) { + ret = imx_soc_device_register(pdev); + if (ret) { + dev_err(dev, + "failed[%d] to register SoC device\n", ret); + goto exit; + } + + /* allocate buffer where sentinel store encrypted IMEM */ + priv->imem.buf = dmam_alloc_coherent(dev, ELE_IMEM_SIZE, + &priv->imem.phyaddr, + GFP_KERNEL); + if (!priv->imem.buf) { + dev_err(dev, "Failed to alloc buffer to store encrypted IMEM\n"); + ret = -ENOMEM; + goto exit; + } + } + + /* start ele rng */ + ret = ele_do_start_rng(); + if (ret) + dev_err(dev, "Failed to start ele rng\n"); + + if (!ret && info && info->enable_ele_trng) { + ret = ele_trng_init(dev); + if (ret) + dev_err(dev, "Failed to init ele-trng\n"); + } + + /* + * A ELE ping request must be send at least once every day(24 hours), + * so setup a delay work with 1 hour interval to ping sentinel periodically. + */ + schedule_delayed_work(&ele_ping_work, ELE_PING_INTERVAL); + + dev_set_drvdata(dev, priv); + return devm_of_platform_populate(dev); + +exit: + /* if execution control reaches here, ele-mu probe fail. + * hence doing the cleanup + */ + if (priv && (priv->flags & RESERVED_DMA_POOL)) { + of_reserved_mem_device_release(dev); + priv->flags &= (~RESERVED_DMA_POOL); + } + return ret; +} + +static int ele_mu_remove(struct platform_device *pdev) +{ + struct ele_mu_priv *priv; + + cancel_delayed_work_sync(&ele_ping_work); + priv = dev_get_drvdata(&pdev->dev); + mbox_free_channel(priv->tx_chan); + mbox_free_channel(priv->rx_chan); + + /* free the buffer in ele-mu remove, previously allocated + * in ele-mu probe to store encrypted IMEM + */ + if (priv->imem.buf) { + dmam_free_coherent(&pdev->dev, ELE_IMEM_SIZE, priv->imem.buf, priv->imem.phyaddr); + priv->imem.buf = NULL; + } + + if (priv->flags & RESERVED_DMA_POOL) { + of_reserved_mem_device_release(&pdev->dev); + priv->flags &= (~RESERVED_DMA_POOL); + } + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int ele_mu_suspend(struct device *dev) +{ + struct ele_mu_priv *priv = dev_get_drvdata(dev); + const struct of_device_id *of_id = of_match_device(ele_mu_match, dev); + struct imx_info *info = (of_id != NULL) ? (struct imx_info *)of_id->data : NULL; + + if (info && info->socdev) { + int ret; + + /* EXPORT command will save encrypted IMEM to given address, + * so later in resume, IMEM can be restored from the given address. + * size must be at least 64 kB. + */ + ret = ele_service_swap(priv->imem.phyaddr, ELE_IMEM_SIZE, ELE_IMEM_EXPORT); + if (ret < 0) + dev_err(dev, "Failed to export IMEM\n"); + else { + priv->imem.size = ret; + dev_info(dev, "Exported %d bytes of encrypted IMEM\n", ret); + } + } + + return 0; +} + +static int ele_mu_resume(struct device *dev) +{ + struct ele_mu_priv *priv = dev_get_drvdata(dev); + int i; + const struct of_device_id *of_id = of_match_device(ele_mu_match, dev); + struct imx_info *info = (of_id != NULL) ? (struct imx_info *)of_id->data : NULL; + + for (i = 0; i < priv->max_dev_ctx; i++) + wake_up_interruptible(&priv->ctxs[i]->wq); + + if (info && info->socdev) { + struct gen_pool *sram_pool; + u32 *get_info_buf; + phys_addr_t get_info_phyaddr; + u32 imem_state; + int ret; + + ret = ele_do_start_rng(); + if (ret) + return ret; + + /* allocate buffer to get info from sentinel */ + sram_pool = of_gen_pool_get(dev->of_node, "sram-pool", 0); + if (!sram_pool) { + dev_err(dev, "Unable to get sram pool\n"); + return -EINVAL; + } + + get_info_buf = (u32 *)gen_pool_alloc(sram_pool, ELE_GET_INFO_BUFF_SZ); + if (!get_info_buf) { + dev_err(dev, "Unable to alloc sram from sram pool\n"); + return -ENOMEM; + } + get_info_phyaddr = gen_pool_virt_to_phys(sram_pool, (ulong)get_info_buf); + + /* get info from sentinel */ + ret = ele_get_info(get_info_phyaddr, ELE_GET_INFO_READ_SZ); + if (ret) { + dev_err(dev, "Failed to get info from sentinel\n"); + goto exit; + } + + /* Get IMEM state, if 0xFE then import IMEM */ + imem_state = (get_info_buf[ELE_IMEM_STATE_WORD] & ELE_IMEM_STATE_MASK) >> 16; + if (imem_state == ELE_IMEM_STATE_BAD) { + /* IMPORT command will restore IMEM from the given address, + * here size is the actual size returned by sentinel + * during the export operation + */ + ret = ele_service_swap(priv->imem.phyaddr, + priv->imem.size, + ELE_IMEM_IMPORT); + if (ret) { + dev_err(dev, "Failed to import IMEM\n"); + goto exit; + } + } else + goto exit; + + /* After importing IMEM, check if IMEM state is 0xCA to make sure + * IMEM is fully loaded and ELE functionality can be used + */ + ret = ele_get_info(get_info_phyaddr, ELE_GET_INFO_READ_SZ); + if (ret) { + dev_err(dev, "Failed to get info from sentinel\n"); + goto exit; + } + + imem_state = (get_info_buf[ELE_IMEM_STATE_WORD] & ELE_IMEM_STATE_MASK) >> 16; + if (imem_state == ELE_IMEM_STATE_OK) + dev_info(dev, "Successfully restored IMEM\n"); + else + dev_err(dev, "Failed to restore IMEM\n"); + +exit: + gen_pool_free(sram_pool, (ulong)get_info_buf, ELE_GET_INFO_BUFF_SZ); + } + + return 0; +} +#endif + +static const struct dev_pm_ops ele_mu_pm = { + SET_SYSTEM_SLEEP_PM_OPS(ele_mu_suspend, ele_mu_resume) +}; + +static struct platform_driver ele_mu_driver = { + .driver = { + .name = "fsl-ele-mu", + .of_match_table = ele_mu_match, + .pm = &ele_mu_pm, + }, + .probe = ele_mu_probe, + .remove = ele_mu_remove, +}; +MODULE_DEVICE_TABLE(of, ele_mu_match); + +module_platform_driver(ele_mu_driver); + +MODULE_AUTHOR("Pankaj Gupta "); +MODULE_DESCRIPTION("iMX Secure Enclave MU Driver."); +MODULE_LICENSE("GPL v2"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/ele_mu.h linux-imx-phytec/drivers/firmware/imx/ele_mu.h --- linux-6.1.55/drivers/firmware/imx/ele_mu.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/firmware/imx/ele_mu.h 2024-06-19 12:33:59.892219789 +0200 @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021-2023 NXP + */ + +#ifndef ELE_MU_H +#define ELE_MU_H + +#include +#include +#include + +/* macro to log operation of a misc device */ +#define miscdev_dbg(p_miscdev, fmt, va_args...) \ + ({ \ + struct miscdevice *_p_miscdev = p_miscdev; \ + dev_dbg((_p_miscdev)->parent, "%s: " fmt, (_p_miscdev)->name, \ + ##va_args); \ + }) + +#define miscdev_info(p_miscdev, fmt, va_args...) \ + ({ \ + struct miscdevice *_p_miscdev = p_miscdev; \ + dev_info((_p_miscdev)->parent, "%s: " fmt, (_p_miscdev)->name, \ + ##va_args); \ + }) + +#define miscdev_err(p_miscdev, fmt, va_args...) \ + ({ \ + struct miscdevice *_p_miscdev = p_miscdev; \ + dev_err((_p_miscdev)->parent, "%s: " fmt, (_p_miscdev)->name, \ + ##va_args); \ + }) +/* macro to log operation of a device context */ +#define devctx_dbg(p_devctx, fmt, va_args...) \ + miscdev_dbg(&((p_devctx)->miscdev), fmt, ##va_args) +#define devctx_info(p_devctx, fmt, va_args...) \ + miscdev_info(&((p_devctx)->miscdev), fmt, ##va_args) +#define devctx_err(p_devctx, fmt, va_args...) \ + miscdev_err((&(p_devctx)->miscdev), fmt, ##va_args) + +#define MAX_RECV_SIZE 31 +#define MAX_RECV_SIZE_BYTES (MAX_RECV_SIZE * sizeof(u32)) +#define MAX_MESSAGE_SIZE 31 +#define MAX_MESSAGE_SIZE_BYTES (MAX_MESSAGE_SIZE * sizeof(u32)) +#define ELE_SUCCESS_IND 0xD6 +#define ELE_FAILURE_IND 0x29 + +#define ELE_MSG_DATA_NUM 10 + +#define MSG_TAG(x) (((x) & 0xff000000) >> 24) +#define MSG_COMMAND(x) (((x) & 0x00ff0000) >> 16) +#define MSG_SIZE(x) (((x) & 0x0000ff00) >> 8) +#define MSG_VER(x) ((x) & 0x000000ff) +#define RES_STATUS(x) ((x) & 0x000000ff) +#define MAX_DATA_SIZE_PER_USER (65 * 1024) +#define S4_DEFAULT_MUAP_INDEX (2) +#define S4_MUAP_DEFAULT_MAX_USERS (4) + +#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u) +#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u) + +#define SECO_MU_IO_FLAGS_IS_INPUT (0x01u) +#define SECO_MU_IO_FLAGS_IS_OUTPUT (0x00u) +#define SECO_MU_IO_FLAGS_IS_IN_OUT (0X10u) +#define SECO_MU_IO_FLAGS_USE_SEC_MEM (0x02u) +#define SECO_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u) + +struct ele_imem_buf { + u8 *buf; + phys_addr_t phyaddr; + u32 size; +}; + +struct ele_buf_desc { + u8 *shared_buf_ptr; + u8 *usr_buf_ptr; + u32 size; + struct list_head link; +}; + +/* Status of a char device */ +enum mu_device_status_t { + MU_FREE, + MU_OPENED +}; + +struct ele_shared_mem { + dma_addr_t dma_addr; + u32 size; + u32 pos; + u8 *ptr; +}; + +/* Private struct for each char device instance. */ +struct ele_mu_device_ctx { + struct device *dev; + struct ele_mu_priv *priv; + struct miscdevice miscdev; + + enum mu_device_status_t status; + wait_queue_head_t wq; + struct semaphore fops_lock; + + u32 pending_hdr; + struct list_head pending_in; + struct list_head pending_out; + + struct ele_shared_mem secure_mem; + struct ele_shared_mem non_secure_mem; + + u32 temp_cmd[MAX_MESSAGE_SIZE]; + u32 temp_resp[MAX_RECV_SIZE]; + u32 temp_resp_size; + struct notifier_block ele_notify; +}; + +/* Header of the messages exchange with the EdgeLock Enclave */ +struct mu_hdr { + u8 ver; + u8 size; + u8 command; + u8 tag; +} __packed; + +struct ele_api_msg { + u32 header; /* u8 Tag; u8 Command; u8 Size; u8 Ver; */ + u32 data[ELE_MSG_DATA_NUM]; +}; + +struct ele_mu_priv { + struct ele_mu_device_ctx *cmd_receiver_dev; + struct ele_mu_device_ctx *waiting_rsp_dev; + /* + * prevent parallel access to the MU registers + * e.g. a user trying to send a command while the other one is + * sending a response. + */ + struct mutex mu_lock; + /* + * prevent a command to be sent on the MU while another one is still + * processing. (response to a command is allowed) + */ + struct mutex mu_cmd_lock; + struct device *dev; + u32 ele_mu_did; + u32 ele_mu_id; + u8 cmd_tag; + u8 rsp_tag; + + struct mbox_client ele_mb_cl; + struct mbox_chan *tx_chan, *rx_chan; + struct ele_api_msg tx_msg, rx_msg; + struct completion done; + spinlock_t lock; + /* Flag to retain the state of initialization done at + * the time of ele-mu probe. + */ + int flags; + int max_dev_ctx; + struct ele_mu_device_ctx **ctxs; + struct ele_imem_buf imem; +}; + +int get_ele_mu_priv(struct ele_mu_priv **export); + +int imx_ele_msg_send_rcv(struct ele_mu_priv *priv); +#ifdef CONFIG_IMX_ELE_TRNG +int ele_trng_init(struct device *dev); +#else +static inline int ele_trng_init(struct device *dev) +{ + return 0; +} +#endif + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/ele_trng.c linux-imx-phytec/drivers/firmware/imx/ele_trng.c --- linux-6.1.55/drivers/firmware/imx/ele_trng.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/firmware/imx/ele_trng.c 2024-06-19 12:33:59.892219789 +0200 @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ELE Random Number Generator Driver NXP's Platforms + * + * Author: Gaurav Jain: + * + * Copyright 2022 NXP + */ + +#include + +#include "ele_mu.h" + +struct ele_trng { + struct hwrng rng; +}; + +int ele_trng_init(struct device *dev) +{ + struct ele_trng *trng; + int ret; + + trng = devm_kzalloc(dev, sizeof(*trng), GFP_KERNEL); + if (!trng) + return -ENOMEM; + + trng->rng.name = "ele-trng"; + trng->rng.read = ele_get_random; + trng->rng.priv = (unsigned long)trng; + trng->rng.quality = 1024; + + dev_info(dev, "registering ele-trng\n"); + + ret = devm_hwrng_register(dev, &trng->rng); + if (ret) + return ret; + + dev_info(dev, "Successfully registered ele-trng\n"); + return 0; +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/imx-scu.c linux-imx-phytec/drivers/firmware/imx/imx-scu.c --- linux-6.1.55/drivers/firmware/imx/imx-scu.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/firmware/imx/imx-scu.c 2024-06-19 12:33:59.892219789 +0200 @@ -7,6 +7,7 @@ * */ +#include #include #include #include @@ -19,8 +20,11 @@ #include #include +#include + +#define FSL_HVC_SC 0xC6000000 #define SCU_MU_CHAN_NUM 8 -#define MAX_RX_TIMEOUT (msecs_to_jiffies(30)) +#define MAX_RX_TIMEOUT (msecs_to_jiffies(3000)) struct imx_sc_chan { struct imx_sc_ipc *sc_ipc; @@ -204,6 +208,7 @@ { uint8_t saved_svc, saved_func; struct imx_sc_rpc_msg *hdr; + struct arm_smccc_res res; int ret; if (WARN_ON(!sc_ipc || !msg)) @@ -218,33 +223,45 @@ saved_func = ((struct imx_sc_rpc_msg *)msg)->func; } sc_ipc->count = 0; - ret = imx_scu_ipc_write(sc_ipc, msg); - if (ret < 0) { - dev_err(sc_ipc->dev, "RPC send msg failed: %d\n", ret); - goto out; - } - - if (have_resp) { - if (!wait_for_completion_timeout(&sc_ipc->done, - MAX_RX_TIMEOUT)) { - dev_err(sc_ipc->dev, "RPC send msg timeout\n"); - mutex_unlock(&sc_ipc->lock); - return -ETIMEDOUT; + sc_ipc->rx_size = 0; + if (xen_initial_domain()) { + arm_smccc_hvc(FSL_HVC_SC, (uint64_t)msg, !have_resp, 0, 0, 0, + 0, 0, &res); + if (res.a0) + printk("Error FSL_HVC_SC %ld\n", res.a0); + + ret = res.a0; + + } else { + ret = imx_scu_ipc_write(sc_ipc, msg); + if (ret < 0) { + dev_err(sc_ipc->dev, "RPC send msg failed: %d\n", ret); + goto out; } - /* response status is stored in hdr->func field */ - hdr = msg; - ret = hdr->func; - /* - * Some special SCU firmware APIs do NOT have return value - * in hdr->func, but they do have response data, those special - * APIs are defined as void function in SCU firmware, so they - * should be treated as return success always. - */ - if ((saved_svc == IMX_SC_RPC_SVC_MISC) && - (saved_func == IMX_SC_MISC_FUNC_UNIQUE_ID || - saved_func == IMX_SC_MISC_FUNC_GET_BUTTON_STATUS)) - ret = 0; + if (have_resp) { + if (!wait_for_completion_timeout(&sc_ipc->done, + MAX_RX_TIMEOUT)) { + dev_err(sc_ipc->dev, "RPC send msg timeout\n"); + mutex_unlock(&sc_ipc->lock); + return -ETIMEDOUT; + } + + /* response status is stored in hdr->func field */ + hdr = msg; + ret = hdr->func; + + /* + * Some special SCU firmware APIs do NOT have return value + * in hdr->func, but they do have response data, those special + * APIs are defined as void function in SCU firmware, so they + * should be treated as return success always. + */ + if ((saved_svc == IMX_SC_RPC_SVC_MISC) && + (saved_func == IMX_SC_MISC_FUNC_UNIQUE_ID || + saved_func == IMX_SC_MISC_FUNC_GET_BUTTON_STATUS)) + ret = 0; + } } out: @@ -354,7 +371,12 @@ }, .probe = imx_scu_probe, }; -builtin_platform_driver(imx_scu_driver); + +static int __init imx_scu_driver_init(void) +{ + return platform_driver_register(&imx_scu_driver); +} +subsys_initcall_sync(imx_scu_driver_init); MODULE_AUTHOR("Dong Aisheng "); MODULE_DESCRIPTION("IMX SCU firmware protocol driver"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/imx-scu-irq.c linux-imx-phytec/drivers/firmware/imx/imx-scu-irq.c --- linux-6.1.55/drivers/firmware/imx/imx-scu-irq.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/firmware/imx/imx-scu-irq.c 2024-06-19 12:33:59.892219789 +0200 @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019-2020 NXP * * Implementation of the SCU IRQ functions using MU. * @@ -11,10 +11,11 @@ #include #include #include +#include +#include #define IMX_SC_IRQ_FUNC_ENABLE 1 #define IMX_SC_IRQ_FUNC_STATUS 2 -#define IMX_SC_IRQ_NUM_GROUP 4 static u32 mu_resource_id; @@ -40,63 +41,100 @@ u8 enable; } __packed; +struct scu_wakeup { + u32 mask; + u32 wakeup_src; + bool valid; +}; + +/* Sysfs functions */ +struct kobject *wakeup_obj; +static ssize_t wakeup_source_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf); +static struct kobj_attribute wakeup_source_attr = __ATTR(wakeup_src, 0660, wakeup_source_show, NULL); + +static struct scu_wakeup scu_irq_wakeup[IMX_SC_IRQ_NUM_GROUP]; + + static struct imx_sc_ipc *imx_sc_irq_ipc_handle; static struct work_struct imx_sc_irq_work; -static ATOMIC_NOTIFIER_HEAD(imx_scu_irq_notifier_chain); +static BLOCKING_NOTIFIER_HEAD(imx_scu_irq_notifier_chain); int imx_scu_irq_register_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_register( + return blocking_notifier_chain_register( &imx_scu_irq_notifier_chain, nb); } EXPORT_SYMBOL(imx_scu_irq_register_notifier); int imx_scu_irq_unregister_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_unregister( + return blocking_notifier_chain_unregister( &imx_scu_irq_notifier_chain, nb); } EXPORT_SYMBOL(imx_scu_irq_unregister_notifier); static int imx_scu_irq_notifier_call_chain(unsigned long status, u8 *group) { - return atomic_notifier_call_chain(&imx_scu_irq_notifier_chain, + return blocking_notifier_call_chain(&imx_scu_irq_notifier_chain, status, (void *)group); } static void imx_scu_irq_work_handler(struct work_struct *work) { - struct imx_sc_msg_irq_get_status msg; - struct imx_sc_rpc_msg *hdr = &msg.hdr; u32 irq_status; int ret; u8 i; for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) { - hdr->ver = IMX_SC_RPC_VERSION; - hdr->svc = IMX_SC_RPC_SVC_IRQ; - hdr->func = IMX_SC_IRQ_FUNC_STATUS; - hdr->size = 2; - - msg.data.req.resource = mu_resource_id; - msg.data.req.group = i; - - ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true); + if (scu_irq_wakeup[i].mask) { + scu_irq_wakeup[i].valid = false; + scu_irq_wakeup[i].wakeup_src = 0; + } + ret = imx_scu_irq_get_status(i, &irq_status); if (ret) { pr_err("get irq group %d status failed, ret %d\n", i, ret); return; } - irq_status = msg.data.resp.status; if (!irq_status) continue; - + if (scu_irq_wakeup[i].mask & irq_status) { + scu_irq_wakeup[i].valid = true; + scu_irq_wakeup[i].wakeup_src = irq_status & scu_irq_wakeup[i].mask; + } else { + scu_irq_wakeup[i].wakeup_src = irq_status; + } pm_system_wakeup(); imx_scu_irq_notifier_call_chain(irq_status, &i); } } +int imx_scu_irq_get_status(u8 group, u32 *irq_status) +{ + struct imx_sc_msg_irq_get_status msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_IRQ; + hdr->func = IMX_SC_IRQ_FUNC_STATUS; + hdr->size = 2; + + msg.data.req.resource = mu_resource_id; + msg.data.req.group = group; + + ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true); + if (ret) + return ret; + + if (irq_status) + *irq_status = msg.data.resp.status; + + return 0; +} +EXPORT_SYMBOL(imx_scu_irq_get_status); + int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable) { struct imx_sc_msg_irq_enable msg; @@ -121,6 +159,11 @@ pr_err("enable irq failed, group %d, mask %d, ret %d\n", group, mask, ret); + if (enable) + scu_irq_wakeup[group].mask |= mask; + else + scu_irq_wakeup[group].mask &= ~mask; + return ret; } EXPORT_SYMBOL(imx_scu_irq_group_enable); @@ -130,6 +173,24 @@ schedule_work(&imx_sc_irq_work); } +static ssize_t wakeup_source_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + u8 i = 0, size = 0; + + for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) { + if (scu_irq_wakeup[i].wakeup_src != 0) { + if (scu_irq_wakeup[i].valid) + size += sprintf(buf + size, "Wakeup source group = %d, irq = 0x%x\n", + i, scu_irq_wakeup[i].wakeup_src); + else + size += sprintf(buf + size, "Spurious SCU wakeup, group = %d, irq = 0x%x\n", + i, scu_irq_wakeup[i].wakeup_src); + } + } + return strlen(buf); +} + int imx_scu_enable_general_irq_channel(struct device *dev) { struct of_phandle_args spec; @@ -169,6 +230,15 @@ mu_resource_id = IMX_SC_R_MU_0A + i; + /* Create directory under /sysfs/firmware */ + wakeup_obj = kobject_create_and_add("scu_wakeup_source", firmware_kobj); + + if (sysfs_create_file(wakeup_obj, &wakeup_source_attr.attr)) { + pr_err("Cannot create sysfs file......\n"); + kobject_put(wakeup_obj); + sysfs_remove_file(firmware_kobj, &wakeup_source_attr.attr); + } + return ret; } EXPORT_SYMBOL(imx_scu_enable_general_irq_channel); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/imx-scu-soc.c linux-imx-phytec/drivers/firmware/imx/imx-scu-soc.c --- linux-6.1.55/drivers/firmware/imx/imx-scu-soc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/firmware/imx/imx-scu-soc.c 2024-06-19 12:33:59.892219789 +0200 @@ -12,6 +12,8 @@ static struct imx_sc_ipc *imx_sc_soc_ipc_handle; +extern bool TKT340553_SW_WORKAROUND; + struct imx_sc_msg_misc_get_soc_id { struct imx_sc_rpc_msg hdr; union { @@ -35,18 +37,15 @@ { struct imx_sc_msg_misc_get_soc_uid msg; struct imx_sc_rpc_msg *hdr = &msg.hdr; - int ret; + + memset(&msg, 0, sizeof(msg)); hdr->ver = IMX_SC_RPC_VERSION; hdr->svc = IMX_SC_RPC_SVC_MISC; hdr->func = IMX_SC_MISC_FUNC_UNIQUE_ID; hdr->size = 1; - ret = imx_scu_call_rpc(imx_sc_soc_ipc_handle, &msg, true); - if (ret) { - pr_err("%s: get soc uid failed, ret %d\n", __func__, ret); - return ret; - } + imx_scu_call_rpc(imx_sc_soc_ipc_handle, &msg, true); *soc_uid = msg.uid_high; *soc_uid <<= 32; @@ -113,9 +112,13 @@ /* format soc_id value passed from SCU firmware */ val = id & 0x1f; - soc_dev_attr->soc_id = devm_kasprintf(dev, GFP_KERNEL, "0x%x", val); - if (!soc_dev_attr->soc_id) - return -ENOMEM; + if (of_machine_is_compatible("fsl,imx8qm")) { + soc_dev_attr->soc_id = "i.MX8QM"; + TKT340553_SW_WORKAROUND = true; + } else if (of_machine_is_compatible("fsl,imx8qxp")) + soc_dev_attr->soc_id = "i.MX8QXP"; + else if (of_machine_is_compatible("fsl,imx8dxl")) + soc_dev_attr->soc_id = "i.MX8DXL"; /* format revision value passed from SCU firmware */ val = (id >> 5) & 0xf; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/Kconfig linux-imx-phytec/drivers/firmware/imx/Kconfig --- linux-6.1.55/drivers/firmware/imx/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/firmware/imx/Kconfig 2024-06-19 12:33:59.892219789 +0200 @@ -28,3 +28,34 @@ depends on IMX_SCU help The System Controller Firmware (SCFW) based power domain driver. + +config IMX_SECO_MU + tristate "i.MX Security Controller (SECO) support" + depends on IMX_MBOX + default y if IMX_SCU + + help + It is possible to use APIs exposed by the SECO like HSM and SHE using the + SAB protocol via the shared Messaging Unit. This driver exposes these + interfaces via a set of file descriptors allowing to configure shared + memory, send and receive messages. + +config IMX_EL_ENCLAVE + tristate "i.MX Embedded EdgeLock Enclave support." + depends on IMX_MBOX + default m if ARM64 + + help + It is possible to use APIs exposed by the iMX EdgeLock Enclave like base, HSM & + SHE using the SAB protocol via the shared Messaging Unit. This driver exposes + these interfaces via a set of file descriptors allowing to configure shared + memory, send and receive messages. + +config IMX_ELE_TRNG + tristate "i.MX ELE True Random Number Generator" + default y + select CRYPTO_RNG + select HW_RANDOM + help + This driver provides kernel-side support for the Random Number + Generator with ELE TRNG. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/Makefile linux-imx-phytec/drivers/firmware/imx/Makefile --- linux-6.1.55/drivers/firmware/imx/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/firmware/imx/Makefile 2024-06-19 12:33:59.892219789 +0200 @@ -1,4 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_IMX_DSP) += imx-dsp.o -obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o +obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o seco.o obj-$(CONFIG_IMX_SCU_PD) += scu-pd.o +obj-${CONFIG_IMX_SECO_MU} += seco_mu.o +el_enclave-objs = ele_mu.o ele_base_msg.o ele_fw_api.o +obj-${CONFIG_IMX_EL_ENCLAVE} += el_enclave.o +el_enclave-${CONFIG_IMX_ELE_TRNG} += ele_trng.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/misc.c linux-imx-phytec/drivers/firmware/imx/misc.c --- linux-6.1.55/drivers/firmware/imx/misc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/firmware/imx/misc.c 2024-06-19 12:33:59.892219789 +0200 @@ -18,6 +18,13 @@ u16 resource; } __packed __aligned(4); + +struct imx_sc_msg_req_misc_set_dma_group { + struct imx_sc_rpc_msg hdr; + u16 resource; + u8 val; +} __packed __aligned(4); + struct imx_sc_msg_req_cpu_start { struct imx_sc_rpc_msg hdr; u32 address_hi; @@ -67,6 +74,24 @@ } EXPORT_SYMBOL(imx_sc_misc_set_control); +int imx_sc_misc_set_dma_group(struct imx_sc_ipc *ipc, u32 resource, + u32 val) +{ + struct imx_sc_msg_req_misc_set_dma_group msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = (uint8_t)IMX_SC_RPC_SVC_MISC; + hdr->func = (uint8_t)IMX_SC_MISC_FUNC_SET_DMA_GROUP; + hdr->size = 2; + + msg.val = val; + msg.resource = resource; + + return imx_scu_call_rpc(ipc, &msg, true); +} +EXPORT_SYMBOL(imx_sc_misc_set_dma_group); + /* * This function gets a miscellaneous control value. * diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/rm.c linux-imx-phytec/drivers/firmware/imx/rm.c --- linux-6.1.55/drivers/firmware/imx/rm.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/firmware/imx/rm.c 2024-06-19 12:33:59.892219789 +0200 @@ -13,6 +13,11 @@ u16 resource; } __packed __aligned(4); +struct imx_sc_msg_rm_pt { + struct imx_sc_rpc_msg hdr; + u8 val; +} __packed __aligned(4); + /* * This function check @resource is owned by current partition or not * @@ -88,3 +93,124 @@ return 0; } EXPORT_SYMBOL(imx_sc_rm_get_resource_owner); + +/* + * This function returns the current partition number + * + * @param[in] ipc IPC handle + * @param[out] pt holding the partition number + * + * @return Returns 0 for success and < 0 for errors. + */ +int imx_sc_rm_get_partition(struct imx_sc_ipc *ipc, u8 *pt) +{ + struct imx_sc_msg_rm_pt msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_RM; + hdr->func = IMX_SC_RM_FUNC_GET_PARTITION; + hdr->size = 1; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret) + return ret; + + if (pt != NULL) + *pt = msg.val; + + return 0; +} +EXPORT_SYMBOL(imx_sc_rm_get_partition); + +struct imx_sc_msg_rm_find_memreg { + struct imx_sc_rpc_msg hdr; + union { + struct { + u32 add_start_hi; + u32 add_start_lo; + u32 add_end_hi; + u32 add_end_lo; + } req; + struct { + u8 val; + } resp; + } data; +} __packed __aligned(4); + +int imx_sc_rm_find_memreg(struct imx_sc_ipc *ipc, u8 *mr, u64 addr_start, + u64 addr_end) +{ + struct imx_sc_msg_rm_find_memreg msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_RM; + hdr->func = IMX_SC_RM_FUNC_FIND_MEMREG; + hdr->size = 5; + + msg.data.req.add_start_hi = addr_start >> 32; + msg.data.req.add_start_lo = addr_start; + msg.data.req.add_end_hi = addr_end >> 32; + msg.data.req.add_end_lo = addr_end; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret) + return ret; + + if (mr) + *mr = msg.data.resp.val; + + return 0; +} +EXPORT_SYMBOL(imx_sc_rm_find_memreg); + +struct imx_sc_msg_set_memreg_permissions { + struct imx_sc_rpc_msg hdr; + u8 mr; + u8 pt; + u8 perm; +} __packed __aligned(4); + +int imx_sc_rm_set_memreg_permissions(struct imx_sc_ipc *ipc, u8 mr, + u8 pt, u8 perm) +{ + struct imx_sc_msg_set_memreg_permissions msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_RM; + hdr->func = IMX_SC_RM_FUNC_SET_MEMREG_PERMISSIONS; + hdr->size = 2; + + msg.mr = mr; + msg.pt = pt; + msg.perm = perm; + + return imx_scu_call_rpc(ipc, &msg, true); +} +EXPORT_SYMBOL(imx_sc_rm_set_memreg_permissions); + +int imx_sc_rm_get_did(struct imx_sc_ipc *ipc, u8 *did) +{ + struct imx_sc_rpc_msg msg; + struct imx_sc_rpc_msg *hdr = &msg; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_RM; + hdr->func = IMX_SC_RM_FUNC_GET_DID; + hdr->size = 1; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret < 0) + return ret; + + if (did) + *did = msg.func; + + return 0; +} +EXPORT_SYMBOL(imx_sc_rm_get_did); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/scu-pd.c linux-imx-phytec/drivers/firmware/imx/scu-pd.c --- linux-6.1.55/drivers/firmware/imx/scu-pd.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/firmware/imx/scu-pd.c 2024-06-19 12:33:59.892219789 +0200 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2018,2020 NXP * Dong Aisheng * * Implementation of the SCU based Power Domains @@ -51,10 +51,13 @@ * */ +#include #include +#include #include #include #include +#include #include #include #include @@ -63,6 +66,17 @@ #include #include #include +#include + +#define IMX_WU_MAX_IRQS (((IMX_SC_R_LAST + 31) / 32 ) * 32 ) + +#define IMX_SIP_WAKEUP_SRC 0xc2000009 +#define IMX_SIP_WAKEUP_SRC_SCU 0x1 +#define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2 + +static u32 wu[IMX_WU_MAX_IRQS]; +static int wu_num; +static void __iomem *gic_dist_base; /* SCU Power Mode Protocol definition */ struct imx_sc_msg_req_set_resource_power_mode { @@ -108,24 +122,29 @@ /* CONN SS */ { "usb", IMX_SC_R_USB_0, 2, true, 0 }, { "usb0phy", IMX_SC_R_USB_0_PHY, 1, false, 0 }, + { "usb1phy", IMX_SC_R_USB_1_PHY, 1, false, 0}, { "usb2", IMX_SC_R_USB_2, 1, false, 0 }, { "usb2phy", IMX_SC_R_USB_2_PHY, 1, false, 0 }, { "sdhc", IMX_SC_R_SDHC_0, 3, true, 0 }, { "enet", IMX_SC_R_ENET_0, 2, true, 0 }, { "nand", IMX_SC_R_NAND, 1, false, 0 }, - { "mlb", IMX_SC_R_MLB_0, 1, true, 0 }, /* AUDIO SS */ { "audio-pll0", IMX_SC_R_AUDIO_PLL_0, 1, false, 0 }, { "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 }, { "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 }, { "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 }, - { "dma0-ch", IMX_SC_R_DMA_0_CH0, 16, true, 0 }, + { "mclk-out-0", IMX_SC_R_MCLK_OUT_0, 1, false, 0 }, + { "mclk-out-1", IMX_SC_R_MCLK_OUT_1, 1, false, 0 }, + { "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 }, { "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 }, - { "dma2-ch", IMX_SC_R_DMA_2_CH0, 5, true, 0 }, + { "dma2-ch-0", IMX_SC_R_DMA_2_CH0, 5, true, 0 }, + { "dma2-ch-1", IMX_SC_R_DMA_2_CH5, 27, true, 0 }, + { "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 }, { "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 }, { "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 }, { "esai0", IMX_SC_R_ESAI_0, 1, false, 0 }, + { "esai1", IMX_SC_R_ESAI_1, 1, false, 0 }, { "spdif0", IMX_SC_R_SPDIF_0, 1, false, 0 }, { "spdif1", IMX_SC_R_SPDIF_1, 1, false, 0 }, { "sai", IMX_SC_R_SAI_0, 3, true, 0 }, @@ -142,11 +161,13 @@ /* DMA SS */ { "can", IMX_SC_R_CAN_0, 3, true, 0 }, { "ftm", IMX_SC_R_FTM_0, 2, true, 0 }, - { "lpi2c", IMX_SC_R_I2C_0, 4, true, 0 }, + { "lpi2c", IMX_SC_R_I2C_0, 5, true, 0 }, { "adc", IMX_SC_R_ADC_0, 2, true, 0 }, { "lcd", IMX_SC_R_LCD_0, 1, true, 0 }, + { "lcd-pll", IMX_SC_R_ELCDIF_PLL, 1, true, 0 }, { "lcd0-pwm", IMX_SC_R_LCD_0_PWM_0, 1, true, 0 }, - { "lpuart", IMX_SC_R_UART_0, 4, true, 0 }, + { "lpuart", IMX_SC_R_UART_0, 5, true, 0 }, + { "sim", IMX_SC_R_EMVSIM_0, 2, true, 0 }, { "lpspi", IMX_SC_R_SPI_0, 4, true, 0 }, { "irqstr_dsp", IMX_SC_R_IRQSTR_DSP, 1, false, 0 }, @@ -162,10 +183,15 @@ /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 }, + { "gpu1-pid", IMX_SC_R_GPU_1_PID0, 4, true, 0 }, + /* HSIO SS */ + { "pcie-a", IMX_SC_R_PCIE_A, 1, false, 0 }, + { "serdes-0", IMX_SC_R_SERDES_0, 1, false, 0 }, { "pcie-b", IMX_SC_R_PCIE_B, 1, false, 0 }, { "serdes-1", IMX_SC_R_SERDES_1, 1, false, 0 }, + { "sata-0", IMX_SC_R_SATA_0, 1, false, 0 }, { "hsio-gpio", IMX_SC_R_HSIO_GPIO, 1, false, 0 }, /* MIPI SS */ @@ -179,13 +205,26 @@ /* LVDS SS */ { "lvds0", IMX_SC_R_LVDS_0, 1, false, 0 }, + { "lvds0-pwm", IMX_SC_R_LVDS_0_PWM_0, 1, false, 0 }, + { "lvds0-lpi2c", IMX_SC_R_LVDS_0_I2C_0, 2, true, 0 }, { "lvds1", IMX_SC_R_LVDS_1, 1, false, 0 }, + { "lvds1-pwm", IMX_SC_R_LVDS_1_PWM_0, 1, false, 0 }, + { "lvds1-lpi2c", IMX_SC_R_LVDS_1_I2C_0, 2, true, 0 }, + + { "mipi1", IMX_SC_R_MIPI_1, 1, 0 }, + { "mipi1-pwm0", IMX_SC_R_MIPI_1_PWM_0, 1, 0 }, + { "mipi1-i2c", IMX_SC_R_MIPI_1_I2C_0, 2, 1 }, + { "lvds1", IMX_SC_R_LVDS_1, 1, 0 }, /* DC SS */ { "dc0", IMX_SC_R_DC_0, 1, false, 0 }, { "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, true, 0 }, { "dc0-video", IMX_SC_R_DC_0_VIDEO0, 2, true, 0 }, + { "dc1", IMX_SC_R_DC_1, 1, false, 0 }, + { "dc1-pll", IMX_SC_R_DC_1_PLL_0, 2, true, 0 }, + { "dc1-video", IMX_SC_R_DC_1_VIDEO0, 2, true, 0 }, + /* CM40 SS */ { "cm40-i2c", IMX_SC_R_M4_0_I2C, 1, false, 0 }, { "cm40-intmux", IMX_SC_R_M4_0_INTMUX, 1, false, 0 }, @@ -200,11 +239,56 @@ { "cm41-mu-a1", IMX_SC_R_M4_1_MU_1A, 1, false, 0}, { "cm41-lpuart", IMX_SC_R_M4_1_UART, 1, false, 0}, + /* CM41 SS */ + { "cm41_i2c", IMX_SC_R_M4_1_I2C, 1, false, 0 }, + { "cm41_intmux", IMX_SC_R_M4_1_INTMUX, 1, false, 0 }, + + /* DB SS */ + { "perf", IMX_SC_R_PERF, 1, false, 0}, + /* IMAGE SS */ { "img-jpegdec-mp", IMX_SC_R_MJPEG_DEC_MP, 1, false, 0 }, { "img-jpegdec-s0", IMX_SC_R_MJPEG_DEC_S0, 4, true, 0 }, { "img-jpegenc-mp", IMX_SC_R_MJPEG_ENC_MP, 1, false, 0 }, { "img-jpegenc-s0", IMX_SC_R_MJPEG_ENC_S0, 4, true, 0 }, + + /* SECO SS */ + { "seco_mu", IMX_SC_R_SECO_MU_2, 3, true, 2}, + + /* V2X SS */ + { "v2x_mu", IMX_SC_R_V2X_MU_0, 2, true, 0}, + { "v2x_mu", IMX_SC_R_V2X_MU_2, 1, true, 2}, + { "v2x_mu", IMX_SC_R_V2X_MU_3, 2, true, 3}, + { "img-pdma", IMX_SC_R_ISI_CH0, 8, true, 0 }, + { "img-csi0", IMX_SC_R_CSI_0, 1, false, 0 }, + { "img-csi0-i2c0", IMX_SC_R_CSI_0_I2C_0, 1, false, 0 }, + { "img-csi0-pwm0", IMX_SC_R_CSI_0_PWM_0, 1, false, 0 }, + { "img-csi1", IMX_SC_R_CSI_1, 1, false, 0 }, + { "img-csi1-i2c0", IMX_SC_R_CSI_1_I2C_0, 1, false, 0 }, + { "img-csi1-pwm0", IMX_SC_R_CSI_1_PWM_0, 1, false, 0 }, + { "img-parallel", IMX_SC_R_PI_0, 1, false, 0 }, + { "img-parallel-i2c0", IMX_SC_R_PI_0_I2C_0, 1, false, 0 }, + { "img-parallel-pwm0", IMX_SC_R_PI_0_PWM_0, 2, true, 0 }, + { "img-parallel-pll", IMX_SC_R_PI_0_PLL, 1, false, 0 }, + + /* HDMI TX SS */ + { "hdmi-tx", IMX_SC_R_HDMI, 1, false, 0}, + { "hdmi-tx-i2s", IMX_SC_R_HDMI_I2S, 1, false, 0}, + { "hdmi-tx-i2c0", IMX_SC_R_HDMI_I2C_0, 1, false, 0}, + { "hdmi-tx-pll0", IMX_SC_R_HDMI_PLL_0, 1, false, 0}, + { "hdmi-tx-pll1", IMX_SC_R_HDMI_PLL_1, 1, false, 0}, + + /* HDMI RX SS */ + { "hdmi-rx", IMX_SC_R_HDMI_RX, 1, false, 0}, + { "hdmi-rx-pwm", IMX_SC_R_HDMI_RX_PWM_0, 1, false, 0}, + { "hdmi-rx-i2c0", IMX_SC_R_HDMI_RX_I2C_0, 1, false, 0}, + { "hdmi-rx-bypass", IMX_SC_R_HDMI_RX_BYPASS, 1, false, 0}, + + /* SECURITY SS */ + { "sec-jr", IMX_SC_R_CAAM_JR2, 2, true, 2}, + + /* BOARD SS */ + { "board", IMX_SC_R_BOARD_R0, 8, true, 0}, }; static const struct imx_sc_pd_soc imx8qxp_scu_pd = { @@ -220,6 +304,56 @@ return container_of(genpd, struct imx_sc_pm_domain, pd); } +static int imx_pm_domains_suspend(void) +{ + struct arm_smccc_res res; + u32 offset; + int i; + + for (i = 0; i < wu_num; i++) { + offset = GICD_ISENABLER + ((wu[i] + 32) / 32) * 4; + if (BIT(wu[i] % 32) & readl_relaxed(gic_dist_base + offset)) { + arm_smccc_smc(IMX_SIP_WAKEUP_SRC, + IMX_SIP_WAKEUP_SRC_IRQSTEER, + 0, 0, 0, 0, 0, 0, &res); + return 0; + } + } + + arm_smccc_smc(IMX_SIP_WAKEUP_SRC, + IMX_SIP_WAKEUP_SRC_SCU, + 0, 0, 0, 0, 0, 0, &res); + + return 0; +} + +struct syscore_ops imx_pm_domains_syscore_ops = { + .suspend = imx_pm_domains_suspend, +}; + +static void imx_sc_pd_enable_irqsteer_wakeup(struct device_node *np) +{ + struct device_node *gic_node; + unsigned int i; + + wu_num = of_property_count_u32_elems(np, "wakeup-irq"); + if (wu_num <= 0) { + pr_warn("no irqsteer wakeup source supported!\n"); + return; + } + + gic_node = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); + WARN_ON(!gic_node); + + gic_dist_base = of_iomap(gic_node, 0); + WARN_ON(!gic_dist_base); + + for (i = 0; i < wu_num; i++) + WARN_ON(of_property_read_u32_index(np, "wakeup-irq", i, &wu[i])); + + register_syscore_ops(&imx_pm_domains_syscore_ops); +} + static void imx_sc_pd_get_console_rsrc(void) { struct of_phandle_args specs; @@ -252,9 +386,20 @@ hdr->size = 2; msg.resource = pd->rsrc; - msg.mode = power_on ? IMX_SC_PM_PW_MODE_ON : IMX_SC_PM_PW_MODE_LP; + msg.mode = power_on ? IMX_SC_PM_PW_MODE_ON : pd->pd.state_idx ? + IMX_SC_PM_PW_MODE_OFF : IMX_SC_PM_PW_MODE_LP; + + /* keep uart console power on for no_console_suspend */ + if (imx_con_rsrc == pd->rsrc && !console_suspend_enabled && !power_on) + return 0; ret = imx_scu_call_rpc(pm_ipc_handle, &msg, true); + if (ret == -EACCES) + { + pr_warn("Resource %d not owned by partition, power state unchanged\n", + pd->rsrc); + return 0; + } if (ret) dev_err(&domain->dev, "failed to power %s resource %d ret %d\n", power_on ? "up" : "off", pd->rsrc, ret); @@ -297,6 +442,7 @@ const struct imx_sc_pd_range *pd_ranges) { struct imx_sc_pm_domain *sc_pd; + struct genpd_power_state *states; bool is_off = true; int ret; @@ -307,9 +453,23 @@ if (!sc_pd) return ERR_PTR(-ENOMEM); + states = devm_kcalloc(dev, 2, sizeof(*states), GFP_KERNEL); + if (!states) { + devm_kfree(dev, sc_pd); + return ERR_PTR(-ENOMEM); + } + sc_pd->rsrc = pd_ranges->rsrc + idx; sc_pd->pd.power_off = imx_sc_pd_power_off; sc_pd->pd.power_on = imx_sc_pd_power_on; + sc_pd->pd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; + states[0].power_off_latency_ns = 25000; + states[0].power_on_latency_ns = 25000; + states[1].power_off_latency_ns = 2500000; + states[1].power_on_latency_ns = 2500000; + + sc_pd->pd.states = states; + sc_pd->pd.state_count = 2; if (pd_ranges->postfix) snprintf(sc_pd->name, sizeof(sc_pd->name), @@ -320,7 +480,7 @@ sc_pd->pd.name = sc_pd->name; if (imx_con_rsrc == sc_pd->rsrc) { - sc_pd->pd.flags = GENPD_FLAG_RPM_ALWAYS_ON; + sc_pd->pd.flags |= GENPD_FLAG_RPM_ALWAYS_ON; is_off = false; } @@ -329,6 +489,7 @@ sc_pd->name, sc_pd->rsrc); devm_kfree(dev, sc_pd); + devm_kfree(dev, states); return NULL; } @@ -337,6 +498,7 @@ dev_warn(dev, "failed to init pd %s rsrc id %d", sc_pd->name, sc_pd->rsrc); devm_kfree(dev, sc_pd); + devm_kfree(dev, states); return NULL; } @@ -399,6 +561,7 @@ return -ENODEV; imx_sc_pd_get_console_rsrc(); + imx_sc_pd_enable_irqsteer_wakeup(pdev->dev.of_node); return imx_scu_init_pm_domains(&pdev->dev, pd_soc); } @@ -416,7 +579,12 @@ }, .probe = imx_sc_pd_probe, }; -builtin_platform_driver(imx_sc_pd_driver); + +static int __init imx_sc_pd_driver_init(void) +{ + return platform_driver_register(&imx_sc_pd_driver); +} +subsys_initcall(imx_sc_pd_driver_init); MODULE_AUTHOR("Dong Aisheng "); MODULE_DESCRIPTION("IMX SCU Power Domain driver"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/seco.c linux-imx-phytec/drivers/firmware/imx/seco.c --- linux-6.1.55/drivers/firmware/imx/seco.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/firmware/imx/seco.c 2024-06-19 12:33:59.892219789 +0200 @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * + * File containing client-side RPC functions for the SECO service. These + * function are ported to clients that communicate to the SC. + */ + +#include + +struct imx_sc_msg_seco_get_build_id { + struct imx_sc_rpc_msg hdr; + u32 version; + u32 commit; +} __packed __aligned(4); + +int imx_sc_seco_build_info(struct imx_sc_ipc *ipc, uint32_t *version, + uint32_t *commit) +{ + struct imx_sc_msg_seco_get_build_id msg = {0}; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_SECO; + hdr->func = IMX_SC_SECO_FUNC_BUILD_INFO; + hdr->size = 1; + + imx_scu_call_rpc(ipc, &msg, true); + + if (version) + *version = msg.version; + if (commit) + *commit = msg.commit; + + return 0; +} +EXPORT_SYMBOL(imx_sc_seco_build_info); + +struct imx_sc_msg_seco_sab_msg { + struct imx_sc_rpc_msg hdr; + u32 smsg_addr_hi; + u32 smsg_addr_lo; +} __packed __aligned(4); + +int imx_sc_seco_sab_msg(struct imx_sc_ipc *ipc, u64 smsg_addr) +{ + struct imx_sc_msg_seco_sab_msg msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_SECO; + hdr->func = IMX_SC_SECO_FUNC_SAB_MSG; + hdr->size = 3; + + msg.smsg_addr_hi = smsg_addr >> 32; + msg.smsg_addr_lo = smsg_addr; + + ret = imx_scu_call_rpc(ipc, &msg, true); + return ret; +} +EXPORT_SYMBOL(imx_sc_seco_sab_msg); + +int imx_sc_seco_secvio_enable(struct imx_sc_ipc *ipc) +{ + struct imx_sc_rpc_msg msg; + struct imx_sc_rpc_msg *hdr = &msg; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = (uint8_t)IMX_SC_RPC_SVC_SECO; + hdr->func = (uint8_t)IMX_SC_SECO_FUNC_SECVIO_ENABLE; + hdr->size = 1; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret) + return ret; + + return 0; +} +EXPORT_SYMBOL(imx_sc_seco_secvio_enable); + +struct imx_sc_msg_req_seco_config { + struct imx_sc_rpc_msg hdr; + u32 data0; + u32 data1; + u32 data2; + u32 data3; + u32 data4; + u8 id; + u8 access; + u8 size; +} __packed __aligned(4); + +struct imx_sc_msg_resp_seco_config { + struct imx_sc_rpc_msg hdr; + u32 data0; + u32 data1; + u32 data2; + u32 data3; + u32 data4; +} __packed __aligned(4); + +int imx_sc_seco_secvio_config(struct imx_sc_ipc *ipc, u8 id, u8 access, + u32 *data0, u32 *data1, u32 *data2, u32 *data3, + u32 *data4, u8 size) +{ + struct imx_sc_msg_req_seco_config msg; + struct imx_sc_msg_resp_seco_config *resp; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + if (!ipc) + return -EINVAL; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = (uint8_t)IMX_SC_RPC_SVC_SECO; + hdr->func = (uint8_t)IMX_SC_SECO_FUNC_SECVIO_CONFIG; + hdr->size = 7; + + /* Check the pointers on data are valid and set it if doing a write */ + switch (size) { + case 5: + if (data4) { + if (access) + msg.data4 = *data4; + } else { + return -EINVAL; + } + fallthrough; + case 4: + if (data3) { + if (access) + msg.data3 = *data3; + } else { + return -EINVAL; + } + fallthrough; + case 3: + if (data2) { + if (access) + msg.data2 = *data2; + } else { + return -EINVAL; + } + fallthrough; + case 2: + if (data1) { + if (access) + msg.data1 = *data1; + } else { + return -EINVAL; + } + fallthrough; + case 1: + if (data0) { + if (access) + msg.data0 = *data0; + } else { + return -EINVAL; + } + break; + default: + return -EINVAL; + } + + msg.id = id; + msg.access = access; + msg.size = size; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret) + return ret; + + resp = (struct imx_sc_msg_resp_seco_config *)&msg; + + /* Pointers already checked so we just copy the data if reading */ + if (!access) + switch (size) { + case 5: + *data4 = resp->data4; + fallthrough; + case 4: + *data3 = resp->data3; + fallthrough; + case 3: + *data2 = resp->data2; + fallthrough; + case 2: + *data1 = resp->data1; + fallthrough; + case 1: + *data0 = resp->data0; + } + + return 0; +} +EXPORT_SYMBOL(imx_sc_seco_secvio_config); + +struct imx_sc_msg_req_seco_dgo_config { + struct imx_sc_rpc_msg hdr; + u32 data; + u8 id; + u8 access; +} __packed __aligned(4); + +struct imx_sc_msg_resp_seco_dgo_config { + struct imx_sc_rpc_msg hdr; + u32 data; +} __packed __aligned(4); + +int imx_sc_seco_secvio_dgo_config(struct imx_sc_ipc *ipc, u8 id, u8 access, + u32 *data) +{ + struct imx_sc_msg_req_seco_dgo_config msg; + struct imx_sc_msg_resp_seco_dgo_config *resp; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + if (!ipc) + return -EINVAL; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = (uint8_t)IMX_SC_RPC_SVC_SECO; + hdr->func = (uint8_t)IMX_SC_SECO_FUNC_SECVIO_DGO_CONFIG; + hdr->size = 3; + + if (access) { + if (data) + msg.data = *data; + else + return -EINVAL; + } + + msg.access = access; + msg.id = id; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret) + return ret; + + resp = (struct imx_sc_msg_resp_seco_dgo_config *)&msg; + + if (!access && data) + *data = resp->data; + + return 0; +} +EXPORT_SYMBOL(imx_sc_seco_secvio_dgo_config); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/firmware/imx/seco_mu.c linux-imx-phytec/drivers/firmware/imx/seco_mu.c --- linux-6.1.55/drivers/firmware/imx/seco_mu.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/firmware/imx/seco_mu.c 2024-06-19 12:33:59.892219789 +0200 @@ -0,0 +1,1266 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright 2019-2020 NXP + */ + +/* + * This driver allows to send messages to the SECO using a shared mailbox. The + * messages must follow the protocol defined. + */ + +/* + * Architecture of the driver: + * + * Non-Secure + Secure + * | + * | + * +---------+ +-------------+ | + * |seco_mu.c+<---->+imx-mailbox.c| | + * | | | mailbox.c +<-->+------+ +------+ + * +---+-----+ +-------------+ | MU X +<-->+ SECO | + * | +------+ +------+ + * +----------------+ | + * | | | + * v v | + * logical logical | + * receiver waiter | + * + + | + * | | | + * | | | + * | +----+------+ | + * | | | | + * | | | | + * device_ctx device_ctx device_ctx | + * | + * User 0 User 1 User Y | + * +------+ +------+ +------+ | + * |misc.c| |misc.c| |misc.c| | + * kernel space +------+ +------+ +------+ | + * | + * +------------------------------------------------------ | + * | | | | + * userspace /dev/seco_muXch0 | | | + * /dev/seco_muXch1 | | + * /dev/seco_muXchY | + * | + * + * When a user sends a command to the seco, it registers its device_ctx as + * waiter of a response from SECO + * + * A user can be registered as receiver of command by the SECO. + * + * When a message is received, the driver select the device_ctx receiving the + * message depending on the tag in the message. It selects the device_ctx + * accordingly. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_RECV_SIZE 31 +#define MAX_RECV_SIZE_BYTES (MAX_RECV_SIZE * sizeof(u32)) +#define MAX_MESSAGE_SIZE 31 +#define MAX_MESSAGE_SIZE_BYTES (MAX_MESSAGE_SIZE * sizeof(u32)) +#define MESSAGE_SIZE(hdr) (((struct she_mu_hdr *)(&(hdr)))->size) +#define MESSAGE_TAG(hdr) (((struct she_mu_hdr *)(&(hdr)))->tag) + +#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u) +#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u) + +#define SECURE_RAM_BASE_ADDRESS (0x31800000ULL) +#define SECURE_RAM_BASE_ADDRESS_SCU (0x20800000u) +#define SECURE_RAM_SIZE (0x10000ULL) + +#define SECO_MU_DEFAULT_MAX_USERS 4 + +#define SECO_MU_INTERRUPT_INDEX (0u) +#define SECO_DEFAULT_MU_INDEX (1u) +#define SECO_DEFAULT_TZ (0u) +#define DEFAULT_DID (0u) + +#define MAX_DATA_SIZE_PER_USER (65 * 1024) + +/* Header of the messages exchange with the SECO */ +struct she_mu_hdr { + u8 ver; + u8 size; + u8 command; + u8 tag; +} __packed; + +/* Status of a char device */ +enum mu_device_status_t { + MU_FREE, + MU_OPENED +}; + +struct seco_shared_mem { + dma_addr_t dma_addr; + u32 size; + u32 pos; + u8 *ptr; +}; + +struct seco_out_buffer_desc { + u8 *out_ptr; + u8 *out_usr_ptr; + u32 out_size; + struct list_head link; +}; + +/* Private struct for each char device instance. */ +struct seco_mu_device_ctx { + struct device *dev; + struct seco_mu_priv *mu_priv; + struct miscdevice miscdev; + + enum mu_device_status_t status; + wait_queue_head_t wq; + struct semaphore fops_lock; + + u32 pending_hdr; + struct list_head pending_out; + + struct seco_shared_mem secure_mem; + struct seco_shared_mem non_secure_mem; + + u32 temp_cmd[MAX_MESSAGE_SIZE]; + u32 temp_resp[MAX_RECV_SIZE]; + u32 temp_resp_size; + struct notifier_block scu_notify; + bool v2x_reset; +}; + +/* Private struct for seco MU driver. */ +struct seco_mu_priv { + struct seco_mu_device_ctx *cmd_receiver_dev; + struct seco_mu_device_ctx *waiting_rsp_dev; + /* + * prevent parallel access to the MU registers + * e.g. a user trying to send a command while the other one is + * sending a response. + */ + struct mutex mu_lock; + /* + * prevent a command to be sent on the MU while another one is still + * processing. (response to a command is allowed) + */ + struct mutex mu_cmd_lock; + struct device *dev; + u32 seco_mu_id; + u8 cmd_tag; + u8 rsp_tag; + + struct mbox_client cl; + struct mbox_chan *tx_chan; + struct mbox_chan *rx_chan; + + struct imx_sc_ipc *ipc_scu; + u8 seco_part_owner; + + int max_ctx; + struct seco_mu_device_ctx **ctxs; +}; + +/* macro to log operation of a misc device */ +#define miscdev_dbg(p_miscdev, fmt, va_args...) \ + ({ \ + struct miscdevice *_p_miscdev = p_miscdev; \ + dev_dbg((_p_miscdev)->parent, "%s: " fmt, (_p_miscdev)->name, \ + ##va_args); \ + }) + +#define miscdev_info(p_miscdev, fmt, va_args...) \ + ({ \ + struct miscdevice *_p_miscdev = p_miscdev; \ + dev_info((_p_miscdev)->parent, "%s: " fmt, (_p_miscdev)->name, \ + ##va_args); \ + }) + +#define miscdev_err(p_miscdev, fmt, va_args...) \ + ({ \ + struct miscdevice *_p_miscdev = p_miscdev; \ + dev_err((_p_miscdev)->parent, "%s: " fmt, (_p_miscdev)->name, \ + ##va_args); \ + }) + +/* macro to log operation of a device context */ +#define devctx_dbg(p_devctx, fmt, va_args...) \ + miscdev_dbg(&((p_devctx)->miscdev), fmt, ##va_args) +#define devctx_info(p_devctx, fmt, va_args...) \ + miscdev_info(&((p_devctx)->miscdev), fmt, ##va_args) +#define devctx_err(p_devctx, fmt, va_args...) \ + miscdev_err((&(p_devctx)->miscdev), fmt, ##va_args) + +#define IMX_SC_RM_PERM_FULL 7U /* Full access */ + +/* Give access to SECU to the memory we want to share */ +static int seco_mu_setup_seco_memory_access(struct seco_mu_device_ctx *dev_ctx, + u64 addr, u32 len) +{ + struct seco_mu_priv *priv = dev_get_drvdata(dev_ctx->dev); + int ret; + u8 mr; + + ret = imx_sc_rm_find_memreg(priv->ipc_scu, &mr, addr, addr + len); + if (ret) { + devctx_err(dev_ctx, "Fail find memreg\n"); + goto exit; + } + + ret = imx_sc_rm_set_memreg_permissions(priv->ipc_scu, mr, + priv->seco_part_owner, + IMX_SC_RM_PERM_FULL); + if (ret) { + devctx_err(dev_ctx, "Fail set permission for resource\n"); + goto exit; + } + +exit: + return ret; +} + +/* + * File operations for user-space + */ +/* Open a char device. */ +static int seco_mu_fops_open(struct inode *nd, struct file *fp) +{ + struct seco_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct seco_mu_device_ctx, miscdev); + int err; + + /* Avoid race if opened at the same time */ + if (down_trylock(&dev_ctx->fops_lock)) + return -EBUSY; + + /* Authorize only 1 instance. */ + if (dev_ctx->status != MU_FREE) { + err = -EBUSY; + goto exit; + } + + /* + * Allocate some memory for data exchanges with SECO. + * This will be used for data not requiring secure memory. + */ + dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx->dev, + MAX_DATA_SIZE_PER_USER, + &dev_ctx->non_secure_mem.dma_addr, + GFP_KERNEL); + if (!dev_ctx->non_secure_mem.ptr) { + err = -ENOMEM; + devctx_err(dev_ctx, "Failed to map shared memory with SECO\n"); + goto exit; + } + + err = seco_mu_setup_seco_memory_access(dev_ctx, + dev_ctx->non_secure_mem.dma_addr, + MAX_DATA_SIZE_PER_USER); + if (err) { + err = -EPERM; + devctx_err(dev_ctx, + "Failed to share access to shared memory\n"); + goto free_coherent; + } + + dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER; + dev_ctx->non_secure_mem.pos = 0; + dev_ctx->status = MU_OPENED; + + dev_ctx->pending_hdr = 0; + dev_ctx->v2x_reset = 0; + + goto exit; + +free_coherent: + dmam_free_coherent(dev_ctx->mu_priv->dev, MAX_DATA_SIZE_PER_USER, + dev_ctx->non_secure_mem.ptr, + dev_ctx->non_secure_mem.dma_addr); + +exit: + up(&dev_ctx->fops_lock); + return err; +} + +/* Close a char device. */ +static int seco_mu_fops_close(struct inode *nd, struct file *fp) +{ + struct seco_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct seco_mu_device_ctx, miscdev); + struct seco_mu_priv *mu_priv = dev_ctx->mu_priv; + struct seco_out_buffer_desc *out_buf_desc; + + /* Avoid race if closed at the same time */ + if (down_trylock(&dev_ctx->fops_lock)) + return -EBUSY; + + /* The device context has not been opened */ + if (dev_ctx->status != MU_OPENED) + goto exit; + + /* check if this device was registered as command receiver. */ + if (mu_priv->cmd_receiver_dev == dev_ctx) + mu_priv->cmd_receiver_dev = NULL; + + /* check if this device was registered as waiting response. */ + if (mu_priv->waiting_rsp_dev == dev_ctx) { + mu_priv->waiting_rsp_dev = NULL; + mutex_unlock(&mu_priv->mu_cmd_lock); + } + + /* Unmap secure memory shared buffer. */ + if (dev_ctx->secure_mem.ptr) + devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr); + + dev_ctx->secure_mem.ptr = NULL; + dev_ctx->secure_mem.dma_addr = 0; + dev_ctx->secure_mem.size = 0; + dev_ctx->secure_mem.pos = 0; + + /* Free non-secure shared buffer. */ + dmam_free_coherent(dev_ctx->mu_priv->dev, MAX_DATA_SIZE_PER_USER, + dev_ctx->non_secure_mem.ptr, + dev_ctx->non_secure_mem.dma_addr); + + dev_ctx->non_secure_mem.ptr = NULL; + dev_ctx->non_secure_mem.dma_addr = 0; + dev_ctx->non_secure_mem.size = 0; + dev_ctx->non_secure_mem.pos = 0; + + while (!list_empty(&dev_ctx->pending_out)) { + out_buf_desc = list_first_entry_or_null(&dev_ctx->pending_out, + struct seco_out_buffer_desc, + link); + __list_del_entry(&out_buf_desc->link); + devm_kfree(dev_ctx->dev, out_buf_desc); + } + + dev_ctx->status = MU_FREE; + +exit: + up(&dev_ctx->fops_lock); + return 0; +} + +/* Write a message to the MU. */ +static ssize_t seco_mu_fops_write(struct file *fp, const char __user *buf, + size_t size, loff_t *ppos) +{ + struct seco_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct seco_mu_device_ctx, miscdev); + struct seco_mu_priv *mu_priv = dev_ctx->mu_priv; + u32 nb_words = 0, header; + int err; + + devctx_dbg(dev_ctx, "write from buf (%p)%ld, ppos=%lld\n", buf, size, + ((ppos) ? *ppos : 0)); + + if (down_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + if (dev_ctx->status != MU_OPENED) { + err = -EINVAL; + goto exit; + } + + if (size < sizeof(struct she_mu_hdr)) { + devctx_err(dev_ctx, "User buffer too small(%ld < %lu)\n", size, + sizeof(struct she_mu_hdr)); + err = -ENOSPC; + goto exit; + } + + if (size > MAX_MESSAGE_SIZE_BYTES) { + devctx_err(dev_ctx, "User buffer too big(%ld > %lu)\n", size, + MAX_MESSAGE_SIZE_BYTES); + err = -ENOSPC; + goto exit; + } + + /* Copy data to buffer */ + err = (int)copy_from_user(dev_ctx->temp_cmd, buf, size); + if (err) { + err = -EFAULT; + devctx_err(dev_ctx, "Fail copy message from user\n"); + goto exit; + } + + print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4, + dev_ctx->temp_cmd, size, false); + + header = dev_ctx->temp_cmd[0]; + + /* Check the message is valid according to tags */ + if (MESSAGE_TAG(header) == mu_priv->cmd_tag) { + /* + * unlocked in seco_mu_receive_work_handler when the + * response to this command is received. + */ + mutex_lock(&mu_priv->mu_cmd_lock); + mu_priv->waiting_rsp_dev = dev_ctx; + } else if (MESSAGE_TAG(header) == mu_priv->rsp_tag) { + /* Check the device context can send the command */ + if (dev_ctx != mu_priv->cmd_receiver_dev) { + devctx_err(dev_ctx, + "This channel is not configured to send response to SECO\n"); + err = -EPERM; + goto exit; + } + } else { + devctx_err(dev_ctx, "The message does not have a valid TAG\n"); + err = -EINVAL; + goto exit; + } + + /* + * Check that the size passed as argument matches the size + * carried in the message. + */ + nb_words = MESSAGE_SIZE(header); + if (nb_words * sizeof(u32) != size) { + devctx_err(dev_ctx, "User buffer too small\n"); + goto exit; + } + + mutex_lock(&mu_priv->mu_lock); + + /* Send message */ + devctx_dbg(dev_ctx, "sending message\n"); + err = mbox_send_message(mu_priv->tx_chan, dev_ctx->temp_cmd); + if (err < 0) { + devctx_err(dev_ctx, "Failed to send message\n"); + goto unlock; + } + + err = nb_words * (u32)sizeof(u32); + +unlock: + mutex_unlock(&mu_priv->mu_lock); + +exit: + up(&dev_ctx->fops_lock); + return err; +} + +/* + * Read a message from the MU. + * Blocking until a message is available. + */ +static ssize_t seco_mu_fops_read(struct file *fp, char __user *buf, + size_t size, loff_t *ppos) +{ + struct seco_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct seco_mu_device_ctx, miscdev); + u32 data_size = 0, size_to_copy = 0; + struct seco_out_buffer_desc *b_desc; + int err; + + devctx_dbg(dev_ctx, "read to buf %p(%ld), ppos=%lld\n", buf, size, + ((ppos) ? *ppos : 0)); + + if (down_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + if (dev_ctx->status != MU_OPENED) { + err = -EINVAL; + goto exit; + } + + if (dev_ctx->v2x_reset) { + err = -EINVAL; + goto exit; + } + + /* Wait until the complete message is received on the MU. */ + err = wait_event_interruptible(dev_ctx->wq, dev_ctx->pending_hdr != 0); + if (err) { + devctx_err(dev_ctx, "Interrupted by signal\n"); + goto exit; + } + + if (dev_ctx->v2x_reset) { + err = -EINVAL; + dev_ctx->v2x_reset = 0; + goto exit; + } + + devctx_dbg(dev_ctx, "%s %s\n", __func__, + "message received, start transmit to user"); + + /* Check that the size passed as argument is larger than + * the one carried in the message. + */ + data_size = dev_ctx->temp_resp_size * sizeof(u32); + size_to_copy = data_size; + if (size_to_copy > size) { + devctx_dbg(dev_ctx, "User buffer too small (%ld < %d)\n", + size, size_to_copy); + size_to_copy = size; + } + + /* We may need to copy the output data to user before + * delivering the completion message. + */ + while (!list_empty(&dev_ctx->pending_out)) { + b_desc = list_first_entry_or_null(&dev_ctx->pending_out, + struct seco_out_buffer_desc, + link); + if (b_desc->out_usr_ptr && b_desc->out_ptr) { + devctx_dbg(dev_ctx, "Copy output data to user\n"); + err = (int)copy_to_user(b_desc->out_usr_ptr, + b_desc->out_ptr, + b_desc->out_size); + if (err) { + devctx_err(dev_ctx, + "Failed to copy output data to user\n"); + err = -EFAULT; + goto exit; + } + } + __list_del_entry(&b_desc->link); + devm_kfree(dev_ctx->dev, b_desc); + } + + /* Copy data from the buffer */ + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4, + dev_ctx->temp_resp, size_to_copy, false); + err = (int)copy_to_user(buf, dev_ctx->temp_resp, size_to_copy); + if (err) { + devctx_err(dev_ctx, "Failed to copy to user\n"); + err = -EFAULT; + goto exit; + } + + err = size_to_copy; + + /* free memory allocated on the shared buffers. */ + dev_ctx->secure_mem.pos = 0; + dev_ctx->non_secure_mem.pos = 0; + + dev_ctx->pending_hdr = 0; + +exit: + up(&dev_ctx->fops_lock); + return err; +} + +/* Configure the shared memory according to user config */ +static int +seco_mu_ioctl_shared_mem_cfg_handler(struct seco_mu_device_ctx *dev_ctx, + unsigned long arg) +{ + struct seco_mu_ioctl_shared_mem_cfg cfg; + int err = -EINVAL; + u64 high_boundary; + + /* Check if not already configured. */ + if (dev_ctx->secure_mem.dma_addr != 0u) { + devctx_err(dev_ctx, "Shared memory not configured\n"); + goto exit; + } + + err = (int)copy_from_user(&cfg, (u8 *)arg, + sizeof(cfg)); + if (err) { + devctx_err(dev_ctx, "Fail copy shared memory config to user\n"); + err = -EFAULT; + goto exit; + } + + devctx_dbg(dev_ctx, "cfg offset: %u(%d)\n", cfg.base_offset, cfg.size); + + high_boundary = cfg.base_offset; + if (high_boundary > SECURE_RAM_SIZE) { + devctx_err(dev_ctx, "base offset is over secure memory\n"); + err = -ENOMEM; + goto exit; + } + + high_boundary += cfg.size; + if (high_boundary > SECURE_RAM_SIZE) { + devctx_err(dev_ctx, "total memory is over secure memory\n"); + err = -ENOMEM; + goto exit; + } + + dev_ctx->secure_mem.dma_addr = (dma_addr_t)cfg.base_offset; + dev_ctx->secure_mem.size = cfg.size; + dev_ctx->secure_mem.pos = 0; + dev_ctx->secure_mem.ptr = devm_ioremap(dev_ctx->dev, + (phys_addr_t)(SECURE_RAM_BASE_ADDRESS + + (u64)dev_ctx->secure_mem.dma_addr), + dev_ctx->secure_mem.size); + if (!dev_ctx->secure_mem.ptr) { + devctx_err(dev_ctx, "Failed to map secure memory\n"); + err = -ENOMEM; + goto exit; + } + +exit: + return err; +} + +/* + * Copy a buffer of daa to/from the user and return the address to use in + * messages + */ +static int seco_mu_ioctl_setup_iobuf_handler(struct seco_mu_device_ctx *dev_ctx, + unsigned long arg) +{ + struct seco_out_buffer_desc *out_buf_desc; + struct seco_mu_ioctl_setup_iobuf io; + struct seco_shared_mem *shared_mem; + int err = -EINVAL; + u32 pos; + u8 *addr; + + struct seco_mu_priv *priv = dev_get_drvdata(dev_ctx->dev); + + err = (int)copy_from_user(&io, + (u8 *)arg, + sizeof(io)); + if (err) { + devctx_err(dev_ctx, "Failed copy iobuf config from user\n"); + err = -EFAULT; + goto exit; + } + + /* Function call to retrieve MU Buffer address */ + if (io.flags & SECO_MU_IO_FLAGS_SHE_V2X) + addr = get_mu_buf(priv->tx_chan); + + devctx_dbg(dev_ctx, "io [buf: %p(%d) flag: %x]\n", + io.user_buf, io.length, io.flags); + + if (io.length == 0 || !io.user_buf) { + /* + * Accept NULL pointers since some buffers are optional + * in SECO commands. In this case we should return 0 as + * pointer to be embedded into the message. + * Skip all data copy part of code below. + */ + io.seco_addr = 0; + goto copy; + } + + /* Select the shared memory to be used for this buffer. */ + if (!(io.flags & SECO_MU_IO_FLAGS_SHE_V2X)) { + if (io.flags & SECO_MU_IO_FLAGS_USE_SEC_MEM) { + /* App requires to use secure memory for this buffer.*/ + shared_mem = &dev_ctx->secure_mem; + } else { + /* No specific requirement for this buffer. */ + shared_mem = &dev_ctx->non_secure_mem; + } + } + + /* Check there is enough space in the shared memory. */ + if (!(io.flags & SECO_MU_IO_FLAGS_SHE_V2X) && + (io.length >= shared_mem->size - shared_mem->pos)) { + devctx_err(dev_ctx, "Not enough space in shared memory\n"); + err = -ENOMEM; + goto exit; + } + + if (!(io.flags & SECO_MU_IO_FLAGS_SHE_V2X)) { + /* Allocate space in shared memory. 8 bytes aligned. */ + pos = shared_mem->pos; + shared_mem->pos += round_up(io.length, 8u); + io.seco_addr = (u64)shared_mem->dma_addr + pos; + } else { + if (io.length > MAX_DATA_SIZE_PER_USER) { + devctx_err(dev_ctx, "Buffer length exceeded the max limit\n"); + err = -ENOMEM; + goto exit; + } + + io.seco_addr = (u64)addr; + } + + if ((io.flags & SECO_MU_IO_FLAGS_USE_SEC_MEM) && + !(io.flags & SECO_MU_IO_FLAGS_USE_SHORT_ADDR)) + /*Add base address to get full address.*/ + io.seco_addr += SECURE_RAM_BASE_ADDRESS_SCU; + + if (io.flags & SECO_MU_IO_FLAGS_IS_INPUT) { + /* + * buffer is input: + * copy data from user space to this allocated buffer. + */ + if (io.flags & SECO_MU_IO_FLAGS_SHE_V2X) { + err = (int)copy_from_user(addr, io.user_buf, io.length); + } else { + err = (int)copy_from_user(shared_mem->ptr + pos, + io.user_buf, + io.length); + } + if (err) { + devctx_err(dev_ctx, + "Failed copy data to shared memory\n"); + err = -EFAULT; + goto exit; + } + } else { + /* + * buffer is output: + * add an entry in the "pending buffers" list so data + * can be copied to user space when receiving SECO + * response. + */ + out_buf_desc = devm_kmalloc(dev_ctx->dev, sizeof(*out_buf_desc), + GFP_KERNEL); + if (!out_buf_desc) { + err = -ENOMEM; + devctx_err(dev_ctx, + "Failed allocating mem for pending buffer\n" + ); + goto exit; + } + + if (io.flags & SECO_MU_IO_FLAGS_SHE_V2X) + out_buf_desc->out_ptr = addr; + else + out_buf_desc->out_ptr = shared_mem->ptr + pos; + out_buf_desc->out_usr_ptr = io.user_buf; + out_buf_desc->out_size = io.length; + list_add_tail(&out_buf_desc->link, &dev_ctx->pending_out); + } + +copy: + /* Provide the seco address to user space only if success. */ + err = (int)copy_to_user((u8 *)arg, &io, + sizeof(io)); + if (err) { + devctx_err(dev_ctx, "Failed to copy iobuff setup to user\n"); + err = -EFAULT; + goto exit; + } + +exit: + return err; +} + +/* Retrieve info about the MU */ +static int seco_mu_ioctl_get_mu_info_handler(struct seco_mu_device_ctx *dev_ctx, + unsigned long arg) +{ + struct seco_mu_priv *priv = dev_get_drvdata(dev_ctx->dev); + struct seco_mu_ioctl_get_mu_info info; + int err = -EINVAL; + + info.seco_mu_idx = (u8)priv->seco_mu_id; + info.interrupt_idx = SECO_MU_INTERRUPT_INDEX; + info.tz = SECO_DEFAULT_TZ; + + err = imx_sc_rm_get_did(priv->ipc_scu, &info.did); + if (err) { + devctx_err(dev_ctx, "Get did failed\n"); + goto exit; + } + + devctx_dbg(dev_ctx, + "info [mu_idx: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n", + info.seco_mu_idx, info.interrupt_idx, info.tz, info.did); + + err = (int)copy_to_user((u8 *)arg, &info, + sizeof(info)); + if (err) { + devctx_err(dev_ctx, "Failed to copy mu info to user\n"); + err = -EFAULT; + goto exit; + } + +exit: + return err; +} + +static int seco_mu_ioctl_signed_msg_handler(struct seco_mu_device_ctx *dev_ctx, + unsigned long arg) +{ + struct seco_shared_mem *shared_mem = &dev_ctx->non_secure_mem; + struct seco_mu_priv *priv = dev_get_drvdata(dev_ctx->dev); + struct seco_mu_ioctl_signed_message msg; + int err = -EINVAL; + u64 addr; + u32 pos; + + err = (int)copy_from_user(&msg, + (u8 *)arg, + sizeof(msg)); + if (err) { + devctx_err(dev_ctx, "Failed to copy from user: %d\n", err); + err = -EFAULT; + goto exit; + } + + /* Check there is enough space in the shared memory. */ + if (msg.msg_size >= shared_mem->size - shared_mem->pos) { + devctx_err(dev_ctx, "Not enough mem: %d left, %d required\n", + shared_mem->size - shared_mem->pos, msg.msg_size); + err = -ENOMEM; + goto exit; + } + + /* Allocate space in shared memory. 8 bytes aligned. */ + pos = shared_mem->pos; + + /* get physical address from the pos */ + addr = (u64)shared_mem->dma_addr + pos; + + /* copy signed message from user space to this allocated buffer */ + err = (int)copy_from_user(shared_mem->ptr + pos, msg.message, + msg.msg_size); + if (err) { + devctx_err(dev_ctx, "Failed to signed message from user: %d\n", + err); + err = -EFAULT; + goto exit; + } + + /* Send the message to SECO through SCU */ + msg.error_code = imx_sc_seco_sab_msg(priv->ipc_scu, addr); + + err = (int)copy_to_user((u8 *)arg, &msg, + sizeof(msg)); + if (err) { + devctx_err(dev_ctx, "Failed to copy to user: %d\n", err); + err = -EFAULT; + goto exit; + } + +exit: + return err; +} + +/* IOCTL entry point of a char device */ +static long seco_mu_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) +{ + struct seco_mu_device_ctx *dev_ctx = container_of(fp->private_data, + struct seco_mu_device_ctx, miscdev); + struct seco_mu_priv *mu_priv = dev_ctx->mu_priv; + int err = -EINVAL; + + /* Prevent race during change of device context */ + if (down_interruptible(&dev_ctx->fops_lock)) + return -EBUSY; + + switch (cmd) { + case SECO_MU_IOCTL_ENABLE_CMD_RCV: + if (!mu_priv->cmd_receiver_dev) { + devctx_dbg(dev_ctx, "setting as receiver\n"); + mu_priv->cmd_receiver_dev = dev_ctx; + err = 0; + }; + break; + case SECO_MU_IOCTL_SHARED_BUF_CFG: + err = seco_mu_ioctl_shared_mem_cfg_handler(dev_ctx, arg); + break; + case SECO_MU_IOCTL_SETUP_IOBUF: + err = seco_mu_ioctl_setup_iobuf_handler(dev_ctx, arg); + break; + case SECO_MU_IOCTL_GET_MU_INFO: + err = seco_mu_ioctl_get_mu_info_handler(dev_ctx, arg); + break; + case SECO_MU_IOCTL_SIGNED_MESSAGE: + err = seco_mu_ioctl_signed_msg_handler(dev_ctx, arg); + break; + default: + err = -EINVAL; + devctx_dbg(dev_ctx, "IOCTL %.8x not supported\n", cmd); + } + + up(&dev_ctx->fops_lock); + return (long)err; +} + +/* + * Callback called by mailbox FW when data are received + */ +static void seco_mu_rx_callback(struct mbox_client *c, void *msg) +{ + struct device *dev = c->dev; + struct seco_mu_priv *priv = dev_get_drvdata(dev); + struct seco_mu_device_ctx *dev_ctx; + bool is_response = false; + int msg_size; + u32 header; + + dev_dbg(dev, "Message received on mailbox\n"); + + /* The function can be called with NULL msg */ + if (!msg) { + dev_err(dev, "Message is invalid\n"); + return; + } + + if (IS_ERR(msg)) { + dev_err(dev, "Error during reception of message: %ld\n", + PTR_ERR(msg)); + return; + } + + header = *(u32 *)msg; + + dev_dbg(dev, "Selecting device\n"); + + /* Incoming command: wake up the receiver if any. */ + if (MESSAGE_TAG(header) == priv->cmd_tag) { + dev_dbg(dev, "Selecting cmd receiver\n"); + dev_ctx = priv->cmd_receiver_dev; + } else if (MESSAGE_TAG(header) == priv->rsp_tag) { + dev_dbg(dev, "Selecting rsp waiter\n"); + dev_ctx = priv->waiting_rsp_dev; + is_response = true; + } else { + dev_err(dev, "Failed to select a device for message: %.8x\n", + header); + return; + } + + if (!dev_ctx) { + dev_err(dev, "No device context selected for message: %.8x\n", + header); + return; + } + + /* Init reception */ + msg_size = MESSAGE_SIZE(header); + if (msg_size > MAX_RECV_SIZE) { + devctx_err(dev_ctx, "Message is too big (%d > %d)", msg_size, + MAX_RECV_SIZE); + return; + } + + memcpy(dev_ctx->temp_resp, msg, msg_size * sizeof(u32)); + dev_ctx->temp_resp_size = msg_size; + + /* Allow user to read */ + dev_ctx->pending_hdr = dev_ctx->temp_resp[0]; + wake_up_interruptible(&dev_ctx->wq); + + if (is_response) { + /* Allow user to send new command */ + mutex_unlock(&priv->mu_cmd_lock); + } +} + +#define SECO_FW_VER_FEAT_MASK (0x0000FFF0u) +#define SECO_FW_VER_FEAT_SHIFT (0x04u) +#define SECO_FW_VER_FEAT_MIN_ALL_MU (0x04u) + +/* + * Get SECO FW version and check if it supports receiving commands on all MUs + * The version is retrieved through SCU since this is the only communication + * channel to SECO always present. + */ +static int seco_mu_check_all_mu_supported(struct device *dev) +{ + struct seco_mu_priv *priv = dev_get_drvdata(dev); + u32 seco_ver; + int ret; + + ret = imx_sc_seco_build_info(priv->ipc_scu, &seco_ver, NULL); + if (ret) { + dev_err(dev, "failed to retrieve SECO build info\n"); + goto exit; + } + + if (((seco_ver & SECO_FW_VER_FEAT_MASK) >> SECO_FW_VER_FEAT_SHIFT) + < SECO_FW_VER_FEAT_MIN_ALL_MU) { + dev_err(dev, "current SECO FW do not support MU with Linux\n"); + ret = -ENOTSUPP; + goto exit; + } + +exit: + return ret; +} + +/* Char driver setup */ +static const struct file_operations seco_mu_fops = { + .open = seco_mu_fops_open, + .owner = THIS_MODULE, + .read = seco_mu_fops_read, + .release = seco_mu_fops_close, + .write = seco_mu_fops_write, + .unlocked_ioctl = seco_mu_ioctl, +}; + +/* interface for managed res to free a mailbox channel */ +static void if_mbox_free_channel(void *mbox_chan) +{ + mbox_free_channel(mbox_chan); +} + +/* interface for managed res to unregister a char device */ +static void if_misc_deregister(void *miscdevice) +{ + misc_deregister(miscdevice); +} + +static int seco_mu_request_channel(struct device *dev, + struct mbox_chan **chan, + const char *name) +{ + struct seco_mu_priv *priv = dev_get_drvdata(dev); + struct mbox_chan *t_chan; + int ret = 0; + + t_chan = mbox_request_channel_byname(&priv->cl, name); + if (IS_ERR(t_chan)) { + ret = PTR_ERR(t_chan); + if (ret != -EPROBE_DEFER) + dev_err(dev, + "Failed to request chan %s ret %d\n", name, + ret); + goto exit; + } + + ret = devm_add_action(dev, if_mbox_free_channel, t_chan); + if (ret) { + dev_err(dev, "failed to add devm removal of mbox %s\n", name); + goto exit; + } + + *chan = t_chan; + +exit: + return ret; +} + +static int imx_sc_v2x_reset_notify(struct notifier_block *nb, + unsigned long event, void *group) +{ + struct seco_mu_device_ctx *dev_ctx = container_of(nb, + struct seco_mu_device_ctx, scu_notify); + + if (!(event & IMX_SC_IRQ_V2X_RESET)) + return 0; + + dev_ctx->v2x_reset = true; + + wake_up_interruptible(&dev_ctx->wq); + return 0; +} +/* Driver probe.*/ +static int seco_mu_probe(struct platform_device *pdev) +{ + struct seco_mu_device_ctx *dev_ctx; + struct device *dev = &pdev->dev; + struct seco_mu_priv *priv; + struct device_node *np; + int max_nb_users = 0; + char *devname; + int ret; + int i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + dev_err(dev, "Fail allocate mem for private data\n"); + goto exit; + } + priv->dev = dev; + dev_set_drvdata(dev, priv); + + /* + * Get the address of MU to be used for communication with the SCU + */ + np = pdev->dev.of_node; + if (!np) { + dev_err(dev, "Cannot find MU User entry in device tree\n"); + ret = -ENOTSUPP; + goto exit; + } + + ret = imx_scu_get_handle(&priv->ipc_scu); + if (ret) { + dev_err(dev, "Fail to retrieve IPC handle\n"); + goto exit; + } + + ret = imx_sc_rm_get_resource_owner(priv->ipc_scu, IMX_SC_R_SECO, + &priv->seco_part_owner); + if (ret) { + dev_err(dev, "Fail get owner of SECO resource\n"); + goto exit; + } + + ret = seco_mu_check_all_mu_supported(dev); + if (ret) { + dev_err(dev, "Fail seco_mu_check_all_mu_supported\n"); + goto exit; + } + + /* Initialize the mutex. */ + mutex_init(&priv->mu_cmd_lock); + mutex_init(&priv->mu_lock); + + priv->cmd_receiver_dev = NULL; + priv->waiting_rsp_dev = NULL; + + ret = of_property_read_u32(np, "fsl,seco_mu_id", &priv->seco_mu_id); + if (ret) { + dev_warn(dev, "%s: Not able to read mu_id", __func__); + priv->seco_mu_id = SECO_DEFAULT_MU_INDEX; + } + + ret = of_property_read_u32(np, "fsl,seco_max_users", &max_nb_users); + if (ret) { + dev_warn(dev, "%s: Not able to read mu_max_user", __func__); + max_nb_users = SECO_MU_DEFAULT_MAX_USERS; + } + + ret = of_property_read_u8(np, "fsl,cmd_tag", &priv->cmd_tag); + if (ret) + priv->cmd_tag = DEFAULT_MESSAGING_TAG_COMMAND; + + ret = of_property_read_u8(np, "fsl,rsp_tag", &priv->rsp_tag); + if (ret) + priv->rsp_tag = DEFAULT_MESSAGING_TAG_RESPONSE; + + /* Mailbox client configuration */ + priv->cl.dev = dev; + priv->cl.knows_txdone = true; + priv->cl.rx_callback = seco_mu_rx_callback; + + ret = seco_mu_request_channel(dev, &priv->tx_chan, "txdb"); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to request txdb channel\n"); + + goto exit; + } + + ret = seco_mu_request_channel(dev, &priv->rx_chan, "rxdb"); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to request rxdb channel\n"); + + goto exit; + } + + priv->max_ctx = max_nb_users; + priv->ctxs = devm_kzalloc(dev, sizeof(dev_ctx) * max_nb_users, GFP_KERNEL); + + /* Create users */ + for (i = 0; i < max_nb_users; i++) { + dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL); + if (!dev_ctx) { + ret = -ENOMEM; + dev_err(dev, + "Fail to allocate memory for device context\n"); + goto exit; + } + + dev_ctx->dev = dev; + dev_ctx->status = MU_FREE; + dev_ctx->mu_priv = priv; + + priv->ctxs[i] = dev_ctx; + + /* Default value invalid for an header. */ + init_waitqueue_head(&dev_ctx->wq); + + INIT_LIST_HEAD(&dev_ctx->pending_out); + sema_init(&dev_ctx->fops_lock, 1); + + devname = devm_kasprintf(dev, GFP_KERNEL, "seco_mu%d_ch%d", + priv->seco_mu_id, i); + if (!devname) { + ret = -ENOMEM; + dev_err(dev, + "Fail to allocate memory for misc dev name\n"); + goto exit; + } + + dev_ctx->miscdev.name = devname; + dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR; + dev_ctx->miscdev.fops = &seco_mu_fops; + dev_ctx->miscdev.parent = dev; + ret = misc_register(&dev_ctx->miscdev); + if (ret) { + dev_err(dev, "failed to register misc device %d\n", + ret); + goto exit; + } + + ret = devm_add_action(dev, if_misc_deregister, + &dev_ctx->miscdev); + + dev_ctx->scu_notify.notifier_call = imx_sc_v2x_reset_notify; + + ret = imx_scu_irq_register_notifier(&dev_ctx->scu_notify); + if (ret) { + dev_err(&pdev->dev, "v2x reqister scu notifier failed.\n"); + return ret; + } + + if (ret) + dev_warn(dev, + "failed to add managed removal of miscdev\n"); + } + + ret = imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_WAKE, + IMX_SC_IRQ_V2X_RESET, true); + if (ret) { + dev_warn(&pdev->dev, "v2x Enable irq failed.\n"); + return ret; + } + +exit: + return ret; +} + +#ifdef CONFIG_PM_SLEEP +static int secu_mu_resume(struct device *dev) +{ + struct seco_mu_priv *priv = dev_get_drvdata(dev); + int i=0; + + for (i = 0; i < priv->max_ctx; i++) { + priv->ctxs[i]->v2x_reset = true; + wake_up_interruptible(&priv->ctxs[i]->wq); + } + return 0; +} +#endif + +static const struct of_device_id seco_mu_match[] = { + { + .compatible = "fsl,imx-seco-mu", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, seco_mu_match); + +static const struct dev_pm_ops secu_mu_pm = { + SET_SYSTEM_SLEEP_PM_OPS(NULL, secu_mu_resume) +}; + +static struct platform_driver seco_mu_driver = { + .driver = { + .name = "seco_mu", + .of_match_table = seco_mu_match, + .pm = &secu_mu_pm, + }, + .probe = seco_mu_probe, +}; + +module_platform_driver(seco_mu_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("IMX Seco MU"); +MODULE_AUTHOR("NXP"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/gpio-74x164.c linux-imx-phytec/drivers/gpio/gpio-74x164.c --- linux-6.1.55/drivers/gpio/gpio-74x164.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpio/gpio-74x164.c 2024-06-19 12:33:59.908220063 +0200 @@ -141,6 +141,9 @@ chip->registers = nregs; chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; + of_property_read_u8_array(spi->dev.of_node, "registers-default", + chip->buffer, chip->registers); + chip->gpio_chip.can_sleep = true; chip->gpio_chip.parent = &spi->dev; chip->gpio_chip.owner = THIS_MODULE; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/gpio-adp5585.c linux-imx-phytec/drivers/gpio/gpio-adp5585.c --- linux-6.1.55/drivers/gpio/gpio-adp5585.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpio/gpio-adp5585.c 2024-06-19 12:33:59.908220063 +0200 @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * GPIO driver for Analog Devices ADP5585 MFD + * + * Copyright 2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#define ADP5585_GPIO_MAX 10 + +struct adp5585_gpio_dev { + struct device *parent; + struct gpio_chip gpio_chip; + struct mutex lock; + u8 dat_out[2]; + u8 dir[2]; +}; + +static int adp5585_gpio_reg_read(struct adp5585_gpio_dev *adp5585_gpio, u8 reg, u8 *val) +{ + struct adp5585_dev *adp5585; + adp5585 = dev_get_drvdata(adp5585_gpio->parent); + + return adp5585->read_reg(adp5585, reg, val); +} + +static int adp5585_gpio_reg_write(struct adp5585_gpio_dev *adp5585_gpio, u8 reg, u8 val) +{ + struct adp5585_dev *adp5585; + adp5585 = dev_get_drvdata(adp5585_gpio->parent); + + return adp5585->write_reg(adp5585, reg, val); +} + +static int adp5585_gpio_get_value(struct gpio_chip *chip, unsigned int off) +{ + struct adp5585_gpio_dev *adp5585_gpio; + unsigned int bank, bit; + u8 val; + + adp5585_gpio = gpiochip_get_data(chip); + bank = ADP5585_BANK(off); + bit = ADP5585_BIT(off); + + mutex_lock(&adp5585_gpio->lock); + /* There are dedicated registers for GPIO IN/OUT. */ + if (adp5585_gpio->dir[bank] & bit) + val = adp5585_gpio->dat_out[bank]; + else + adp5585_gpio_reg_read(adp5585_gpio, ADP5585_GPI_STATUS_A + bank, &val); + mutex_unlock(&adp5585_gpio->lock); + + return !!(val & bit); +} + +static void adp5585_gpio_set_value(struct gpio_chip *chip, unsigned int off, int val) +{ + struct adp5585_gpio_dev *adp5585_gpio; + unsigned int bank, bit; + + adp5585_gpio = gpiochip_get_data(chip); + bank = ADP5585_BANK(off); + bit = ADP5585_BIT(off); + + mutex_lock(&adp5585_gpio->lock); + if (val) + adp5585_gpio->dat_out[bank] |= bit; + else + adp5585_gpio->dat_out[bank] &= ~bit; + + adp5585_gpio_reg_write(adp5585_gpio, ADP5585_GPO_DATA_OUT_A + bank, + adp5585_gpio->dat_out[bank]); + mutex_unlock(&adp5585_gpio->lock); +} + +static int adp5585_gpio_direction_input(struct gpio_chip *chip, unsigned int off) +{ + struct adp5585_gpio_dev *adp5585_gpio; + unsigned int bank, bit; + int ret; + + adp5585_gpio = gpiochip_get_data(chip); + bank = ADP5585_BANK(off); + bit = ADP5585_BIT(off); + + mutex_lock(&adp5585_gpio->lock); + adp5585_gpio->dir[bank] &= ~bit; + ret = adp5585_gpio_reg_write(adp5585_gpio, ADP5585_GPIO_DIRECTION_A + bank, + adp5585_gpio->dir[bank]); + mutex_unlock(&adp5585_gpio->lock); + return ret; +} + +static int adp5585_gpio_direction_output(struct gpio_chip *chip, unsigned int off, int val) +{ + struct adp5585_gpio_dev *adp5585_gpio; + unsigned int bank, bit; + int ret; + + adp5585_gpio = gpiochip_get_data(chip); + bank = ADP5585_BANK(off); + bit = ADP5585_BIT(off); + + mutex_lock(&adp5585_gpio->lock); + adp5585_gpio->dir[bank] |= bit; + + if (val) + adp5585_gpio->dat_out[bank] |= bit; + else + adp5585_gpio->dat_out[bank] &= ~bit; + + ret = adp5585_gpio_reg_write(adp5585_gpio, ADP5585_GPO_DATA_OUT_A + bank, + adp5585_gpio->dat_out[bank]); + ret |= adp5585_gpio_reg_write(adp5585_gpio, ADP5585_GPIO_DIRECTION_A + bank, + adp5585_gpio->dir[bank]); + mutex_unlock(&adp5585_gpio->lock); + + return ret; +} + +static int adp5585_gpio_probe(struct platform_device *pdev) +{ + struct adp5585_gpio_dev *adp5585_gpio; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct gpio_chip *gc; + int i; + + adp5585_gpio = devm_kzalloc(&pdev->dev, sizeof(struct adp5585_gpio_dev), GFP_KERNEL); + if (adp5585_gpio == NULL) + return -ENOMEM; + + adp5585_gpio->parent = pdev->dev.parent; + + gc = &adp5585_gpio->gpio_chip; + gc->of_node = np; + gc->parent = dev; + gc->direction_input = adp5585_gpio_direction_input; + gc->direction_output = adp5585_gpio_direction_output; + gc->get = adp5585_gpio_get_value; + gc->set = adp5585_gpio_set_value; + gc->can_sleep = true; + + gc->base = -1; + gc->ngpio = ADP5585_GPIO_MAX; + gc->label = pdev->name; + gc->owner = THIS_MODULE; + + mutex_init(&adp5585_gpio->lock); + + for (i = 0; i < 2; i++) { + u8 *dat_out, *dir; + dat_out = adp5585_gpio->dat_out; + dir = adp5585_gpio->dir; + adp5585_gpio_reg_read(adp5585_gpio, + ADP5585_GPO_DATA_OUT_A + i, dat_out + i); + adp5585_gpio_reg_read(adp5585_gpio, + ADP5585_GPIO_DIRECTION_A + i, dir + i); + } + + return devm_gpiochip_add_data(&pdev->dev, &adp5585_gpio->gpio_chip, adp5585_gpio); +} + +static const struct of_device_id adp5585_of_match[] = { + {.compatible = "adp5585-gpio", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, adp5585_of_match); + +static struct platform_driver adp5585_gpio_driver = { + .driver = { + .name = "adp5585-gpio", + .of_match_table = adp5585_of_match, + }, + .probe = adp5585_gpio_probe, +}; + +module_platform_driver(adp5585_gpio_driver); + +MODULE_AUTHOR("Haibo Chen "); +MODULE_DESCRIPTION("GPIO ADP5585 Driver"); +MODULE_LICENSE("GPL"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/gpio-imx-rpmsg.c linux-imx-phytec/drivers/gpio/gpio-imx-rpmsg.c --- linux-6.1.55/drivers/gpio/gpio-imx-rpmsg.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpio/gpio-imx-rpmsg.c 2024-06-19 12:33:59.912220131 +0200 @@ -0,0 +1,534 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMX_RPMSG_GPIO_PER_PORT 32 +#define RPMSG_TIMEOUT 1000 +#define IMX_RPMSG_GPIO_PORT_PER_SOC_MAX 10 + +enum gpio_input_trigger_type { + GPIO_RPMSG_TRI_IGNORE, + GPIO_RPMSG_TRI_RISING, + GPIO_RPMSG_TRI_FALLING, + GPIO_RPMSG_TRI_BOTH_EDGE, + GPIO_RPMSG_TRI_LOW_LEVEL, + GPIO_RPMSG_TRI_HIGH_LEVEL, +}; + +enum gpio_rpmsg_header_type { + GPIO_RPMSG_SETUP, + GPIO_RPMSG_REPLY, + GPIO_RPMSG_NOTIFY, +}; + +enum gpio_rpmsg_header_cmd { + GPIO_RPMSG_INPUT_INIT, + GPIO_RPMSG_OUTPUT_INIT, + GPIO_RPMSG_INPUT_GET, +}; + +struct gpio_rpmsg_data { + struct imx_rpmsg_head header; + u8 pin_idx; + u8 port_idx; + union { + u8 event; + u8 retcode; + u8 value; + } out; + union { + u8 wakeup; + u8 value; + } in; +} __packed __aligned(8); + +struct imx_rpmsg_gpio_pin { + u32 irq_type; + struct gpio_rpmsg_data msg; +}; + +struct imx_rpmsg_gpio_port { + struct gpio_chip gc; + struct irq_chip chip; + struct irq_domain *domain; + struct imx_rpmsg_gpio_pin gpio_pins[IMX_RPMSG_GPIO_PER_PORT]; + int idx; +}; + +struct imx_gpio_rpmsg_info { + struct rpmsg_device *rpdev; + struct gpio_rpmsg_data *notify_msg; + struct gpio_rpmsg_data *reply_msg; + struct pm_qos_request pm_qos_req; + struct completion cmd_complete; + struct imx_rpmsg_gpio_port *port_store[IMX_RPMSG_GPIO_PORT_PER_SOC_MAX]; + struct mutex lock; +}; + +struct imx_rpmsg_gpio_work { + struct gpio_rpmsg_data *msg; + struct imx_rpmsg_gpio_port *port; + struct work_struct rpmsg_send_wq; +}; + +static struct imx_rpmsg_gpio_work imx_rpmsg_gpio_send_work; +static struct workqueue_struct *imx_rpmsg_gpio_workqueue; +static struct imx_gpio_rpmsg_info gpio_rpmsg; + +static int gpio_send_message(struct imx_rpmsg_gpio_port *port, + struct gpio_rpmsg_data *msg, + struct imx_gpio_rpmsg_info *info, + bool sync) +{ + int err; + + if (!info->rpdev) { + dev_dbg(&info->rpdev->dev, + "rpmsg channel not ready, m4 image ready?\n"); + return -EINVAL; + } + + mutex_lock(&info->lock); + cpu_latency_qos_add_request(&info->pm_qos_req, + 0); + + reinit_completion(&info->cmd_complete); + + err = rpmsg_send(info->rpdev->ept, (void *)msg, + sizeof(struct gpio_rpmsg_data)); + + if (err) { + dev_err(&info->rpdev->dev, "rpmsg_send failed: %d\n", err); + goto err_out; + } + + if (sync) { + err = wait_for_completion_timeout(&info->cmd_complete, + msecs_to_jiffies(RPMSG_TIMEOUT)); + if (!err) { + dev_err(&info->rpdev->dev, "rpmsg_send timeout!\n"); + err = -ETIMEDOUT; + goto err_out; + } + + if (info->reply_msg->out.retcode != 0) { + dev_err(&info->rpdev->dev, "rpmsg not ack %d!\n", + info->reply_msg->out.retcode); + err = -EINVAL; + goto err_out; + } + + /* copy the reply message */ + memcpy(&port->gpio_pins[info->reply_msg->pin_idx].msg, + info->reply_msg, sizeof(*info->reply_msg)); + + err = 0; + } + +err_out: + cpu_latency_qos_remove_request(&info->pm_qos_req); + mutex_unlock(&info->lock); + + return err; +} + +static int gpio_rpmsg_cb(struct rpmsg_device *rpdev, + void *data, int len, void *priv, u32 src) +{ + struct gpio_rpmsg_data *msg = (struct gpio_rpmsg_data *)data; + unsigned long flags; + + if (msg->header.type == GPIO_RPMSG_REPLY) { + /* TBD: Add irq request_id check for A core msg */ + gpio_rpmsg.reply_msg = msg; + complete(&gpio_rpmsg.cmd_complete); + } else if (msg->header.type == GPIO_RPMSG_NOTIFY) { + gpio_rpmsg.notify_msg = msg; + local_irq_save(flags); + generic_handle_irq(irq_find_mapping(gpio_rpmsg.port_store[msg->port_idx]->domain, msg->pin_idx)); + local_irq_restore(flags); + } else + dev_err(&gpio_rpmsg.rpdev->dev, "wrong command type!\n"); + + return 0; +} + +static struct gpio_rpmsg_data *gpio_get_pin_msg(struct imx_rpmsg_gpio_port *port, unsigned int offset) +{ + struct gpio_rpmsg_data *msg = &port->gpio_pins[offset].msg; + + memset(msg, 0, sizeof(struct gpio_rpmsg_data)); + + return msg; +}; + +static int imx_rpmsg_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data *msg = NULL; + int ret; + + msg = gpio_get_pin_msg(port, gpio); + msg->header.cate = IMX_RPMSG_GPIO; + msg->header.major = IMX_RMPSG_MAJOR; + msg->header.minor = IMX_RMPSG_MINOR; + msg->header.type = GPIO_RPMSG_SETUP; + msg->header.cmd = GPIO_RPMSG_INPUT_GET; + msg->pin_idx = gpio; + msg->port_idx = port->idx; + + ret = gpio_send_message(port, msg, &gpio_rpmsg, true); + if (!ret) + return !!port->gpio_pins[gpio].msg.in.value; + + return ret; +} + +static int imx_rpmsg_gpio_direction_input(struct gpio_chip *gc, + unsigned int gpio) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data *msg = NULL; + + msg = gpio_get_pin_msg(port, gpio); + msg->header.cate = IMX_RPMSG_GPIO; + msg->header.major = IMX_RMPSG_MAJOR; + msg->header.minor = IMX_RMPSG_MINOR; + msg->header.type = GPIO_RPMSG_SETUP; + msg->header.cmd = GPIO_RPMSG_INPUT_INIT; + msg->pin_idx = gpio; + msg->port_idx = port->idx; + + msg->out.event = GPIO_RPMSG_TRI_IGNORE; + msg->in.wakeup = 0; + + return gpio_send_message(port, msg, &gpio_rpmsg, true); +} + +static inline void imx_rpmsg_gpio_direction_output_init(struct gpio_chip *gc, + unsigned int gpio, int val, struct gpio_rpmsg_data *msg) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + + msg->header.cate = IMX_RPMSG_GPIO; + msg->header.major = IMX_RMPSG_MAJOR; + msg->header.minor = IMX_RMPSG_MINOR; + msg->header.type = GPIO_RPMSG_SETUP; + msg->header.cmd = GPIO_RPMSG_OUTPUT_INIT; + msg->pin_idx = gpio; + msg->port_idx = port->idx; + msg->out.value = val; +} + +static void imx_rpmsg_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data *msg = NULL; + + msg = gpio_get_pin_msg(port, gpio); + imx_rpmsg_gpio_direction_output_init(gc, gpio, val, msg); + gpio_send_message(port, msg, &gpio_rpmsg, true); +} + +static int imx_rpmsg_gpio_direction_output(struct gpio_chip *gc, + unsigned int gpio, int val) +{ + struct imx_rpmsg_gpio_port *port = gpiochip_get_data(gc); + struct gpio_rpmsg_data *msg = NULL; + + msg = gpio_get_pin_msg(port, gpio); + imx_rpmsg_gpio_direction_output_init(gc, gpio, val, msg); + return gpio_send_message(port, msg, &gpio_rpmsg, true); +} + +static int imx_rpmsg_irq_set_type(struct irq_data *d, u32 type) +{ + struct imx_rpmsg_gpio_port *port = irq_data_get_irq_chip_data(d); + u32 gpio_idx = d->hwirq; + int edge = 0; + int ret = 0; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + edge = GPIO_RPMSG_TRI_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + edge = GPIO_RPMSG_TRI_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + edge = GPIO_RPMSG_TRI_BOTH_EDGE; + break; + case IRQ_TYPE_LEVEL_LOW: + edge = GPIO_RPMSG_TRI_LOW_LEVEL; + break; + case IRQ_TYPE_LEVEL_HIGH: + edge = GPIO_RPMSG_TRI_HIGH_LEVEL; + break; + default: + ret = -EINVAL; + break; + } + + port->gpio_pins[gpio_idx].irq_type = edge; + return ret; +} + +static int imx_rpmsg_irq_set_wake(struct irq_data *d, u32 enable) +{ + struct imx_rpmsg_gpio_port *port = irq_data_get_irq_chip_data(d); + struct gpio_rpmsg_data *msg = NULL; + u32 gpio_idx = d->hwirq; + + msg = gpio_get_pin_msg(port, gpio_idx); + msg->header.cate = IMX_RPMSG_GPIO; + msg->header.major = IMX_RMPSG_MAJOR; + msg->header.minor = IMX_RMPSG_MINOR; + msg->header.type = GPIO_RPMSG_SETUP; + msg->header.cmd = GPIO_RPMSG_INPUT_INIT; + msg->pin_idx = gpio_idx; + msg->port_idx = port->idx; + + /* set wakeup trigger source, + * if not set irq type, then use high level as trigger type + */ + msg->out.event = port->gpio_pins[gpio_idx].irq_type; + if (!msg->out.event) + msg->out.event = GPIO_RPMSG_TRI_LOW_LEVEL; + + msg->in.wakeup = enable; + + /* here should be atomic context */ + gpio_send_message(port, msg, &gpio_rpmsg, false); + + return 0; +} + +void imx_rpmsg_gpio_do_send(struct work_struct *w) +{ + struct imx_rpmsg_gpio_work *gpio_send_work = + container_of(w, struct imx_rpmsg_gpio_work, rpmsg_send_wq); + + gpio_send_message(gpio_send_work->port, + gpio_send_work->msg, &gpio_rpmsg, false); +} + +/* + * This function will be called at: + * - one interrupt setup. + * - the end of one interrupt happened + * The gpio over rpmsg driver will not write the real register, so save + * all infos before this function and then send all infos to M core in this + * step. + */ +static void imx_rpmsg_unmask_irq(struct irq_data *d) +{ + struct imx_rpmsg_gpio_port *port = irq_data_get_irq_chip_data(d); + struct gpio_rpmsg_data *msg = NULL; + u32 gpio_idx = d->hwirq; + + msg = gpio_get_pin_msg(port, gpio_idx); + msg->header.cate = IMX_RPMSG_GPIO; + msg->header.major = IMX_RMPSG_MAJOR; + msg->header.minor = IMX_RMPSG_MINOR; + msg->header.type = GPIO_RPMSG_SETUP; + msg->header.cmd = GPIO_RPMSG_INPUT_INIT; + msg->pin_idx = gpio_idx; + msg->port_idx = port->idx; + + /* + * set wakeup trigger source, + * if not set irq type, then use high level as trigger type + */ + msg->out.event = port->gpio_pins[gpio_idx].irq_type; + if (!msg->out.event) + msg->out.event = GPIO_RPMSG_TRI_LOW_LEVEL; + + msg->in.wakeup = 0; + + imx_rpmsg_gpio_send_work.msg = msg; + imx_rpmsg_gpio_send_work.port = port; + + queue_work(imx_rpmsg_gpio_workqueue, &(imx_rpmsg_gpio_send_work.rpmsg_send_wq)); +} + +static void imx_rpmsg_mask_irq(struct irq_data *d) +{ + /* + * No need to implement the callback at A core side. + * M core will mask interrupt after a interrupt occurred, and then + * sends a notify to A core. + * After A core dealt with the notify, A core will send a rpmsg to + * M core to enable this interrupt again. + */ +} + +static void imx_rpmsg_irq_shutdown(struct irq_data *d) +{ + struct imx_rpmsg_gpio_port *port = irq_data_get_irq_chip_data(d); + struct gpio_rpmsg_data *msg = NULL; + u32 gpio_idx = d->hwirq; + + msg = gpio_get_pin_msg(port, gpio_idx); + msg->header.cate = IMX_RPMSG_GPIO; + msg->header.major = IMX_RMPSG_MAJOR; + msg->header.minor = IMX_RMPSG_MINOR; + msg->header.type = GPIO_RPMSG_SETUP; + msg->header.cmd = GPIO_RPMSG_INPUT_INIT; + msg->pin_idx = gpio_idx; + msg->port_idx = port->idx; + + /* Disable interrupt here */ + msg->out.event = GPIO_RPMSG_TRI_IGNORE; + msg->in.wakeup = 0; + + imx_rpmsg_gpio_send_work.msg = msg; + imx_rpmsg_gpio_send_work.port = port; + + queue_work(imx_rpmsg_gpio_workqueue, &(imx_rpmsg_gpio_send_work.rpmsg_send_wq)); +} + +static struct irq_chip imx_rpmsg_irq_chip = { + .irq_mask = imx_rpmsg_mask_irq, + .irq_unmask = imx_rpmsg_unmask_irq, + .irq_set_wake = imx_rpmsg_irq_set_wake, + .irq_set_type = imx_rpmsg_irq_set_type, + .irq_shutdown = imx_rpmsg_irq_shutdown, + /* TBD: Add .irq_disable support */ +}; + +static int imx_rpmsg_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct imx_rpmsg_gpio_port *port; + struct gpio_chip *gc; + int i, irq_base; + int ret; + + port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + ret = of_property_read_u32(np, "port_idx", &port->idx); + if (ret) + return ret; + + gpio_rpmsg.port_store[port->idx] = port; + + gc = &port->gc; + gc->of_node = np; + gc->parent = dev; + gc->label = kasprintf(GFP_KERNEL, "imx-rpmsg-gpio-%d", port->idx); + gc->ngpio = IMX_RPMSG_GPIO_PER_PORT; + gc->base = of_alias_get_id(np, "gpio") * IMX_RPMSG_GPIO_PER_PORT; + + gc->direction_input = imx_rpmsg_gpio_direction_input; + gc->direction_output = imx_rpmsg_gpio_direction_output; + gc->get = imx_rpmsg_gpio_get; + gc->set = imx_rpmsg_gpio_set; + + platform_set_drvdata(pdev, port); + + ret = devm_gpiochip_add_data(dev, gc, port); + if (ret < 0) + return ret; + + /* generate one new irq domain */ + port->chip = imx_rpmsg_irq_chip; + port->chip.name = kasprintf(GFP_KERNEL, "rpmsg-irq-port-%d", port->idx); + + irq_base = irq_alloc_descs(-1, 0, IMX_RPMSG_GPIO_PER_PORT, + numa_node_id()); + WARN_ON(irq_base < 0); + + port->domain = irq_domain_add_legacy(np, IMX_RPMSG_GPIO_PER_PORT, + irq_base, 0, + &irq_domain_simple_ops, port); + WARN_ON(!port->domain); + for (i = irq_base; i < irq_base + IMX_RPMSG_GPIO_PER_PORT; i++) { + irq_set_chip_and_handler(i, &port->chip, handle_level_irq); + irq_set_chip_data(i, port); + irq_clear_status_flags(i, IRQ_NOREQUEST); + irq_set_probe(i); + } + + imx_rpmsg_gpio_workqueue = create_workqueue("imx_rpmsg_gpio_workqueue"); + if (!imx_rpmsg_gpio_workqueue) + dev_err(&pdev->dev, "Failed to create imx_rpmsg_gpio_workqueue\n"); + INIT_WORK(&(imx_rpmsg_gpio_send_work.rpmsg_send_wq), imx_rpmsg_gpio_do_send); + + return 0; +} +static const struct of_device_id imx_rpmsg_gpio_dt_ids[] = { + { .compatible = "fsl,imx-rpmsg-gpio" }, + { /* sentinel */ } +}; + +static struct platform_driver imx_rpmsg_gpio_driver = { + .driver = { + .name = "gpio-imx-rpmsg", + .of_match_table = imx_rpmsg_gpio_dt_ids, + }, + .probe = imx_rpmsg_gpio_probe, +}; + +static int gpio_rpmsg_probe(struct rpmsg_device *rpdev) +{ + gpio_rpmsg.rpdev = rpdev; + dev_info(&rpdev->dev, "new channel: 0x%x -> 0x%x!\n", + rpdev->src, rpdev->dst); + + init_completion(&gpio_rpmsg.cmd_complete); + mutex_init(&gpio_rpmsg.lock); + + return platform_driver_register(&imx_rpmsg_gpio_driver); +} + +static struct rpmsg_device_id gpio_rpmsg_id_table[] = { + { .name = "rpmsg-io-channel" }, + {}, +}; + +static struct rpmsg_driver gpio_rpmsg_driver = { + .drv.name = "gpio_rpmsg", + .drv.owner = THIS_MODULE, + .id_table = gpio_rpmsg_id_table, + .probe = gpio_rpmsg_probe, + .callback = gpio_rpmsg_cb, +}; + + +static int __init gpio_imx_rpmsg_init(void) +{ + return register_rpmsg_driver(&gpio_rpmsg_driver); +} +device_initcall(gpio_imx_rpmsg_init); + +MODULE_AUTHOR("NXP Semiconductor"); +MODULE_DESCRIPTION("NXP i.MX7ULP rpmsg gpio driver"); +MODULE_LICENSE("GPL v2"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/gpio-max732x.c linux-imx-phytec/drivers/gpio/gpio-max732x.c --- linux-6.1.55/drivers/gpio/gpio-max732x.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpio/gpio-max732x.c 2024-06-19 12:33:59.916220200 +0200 @@ -19,6 +19,7 @@ #include #include #include +#include /* @@ -77,6 +78,12 @@ #define INT_CAPS(x) (((uint64_t)(x)) << 32) enum { + OUTPUT_MASK, + OUTPUT_VAL, + OUTPUT_NUM, +}; + +enum { MAX7319, MAX7320, MAX7321, @@ -617,6 +624,8 @@ struct i2c_client *c; uint16_t addr_a, addr_b; int ret, nr_port; + u16 out_set[OUTPUT_NUM]; + unsigned long mask, val; pdata = dev_get_platdata(&client->dev); node = client->dev.of_node; @@ -634,6 +643,10 @@ return -ENOMEM; chip->client = client; + ret = device_reset(&client->dev); + if (ret == -EPROBE_DEFER) + return ret; + nr_port = max732x_setup_gpio(chip, id, pdata->gpio_base); chip->gpio_chip.parent = &client->dev; @@ -699,6 +712,15 @@ return ret; i2c_set_clientdata(client, chip); + + /* set the output IO default voltage */ + if (!of_property_read_u16_array(node, "out-default", out_set, + ARRAY_SIZE(out_set))) { + mask = out_set[OUTPUT_MASK] & chip->dir_output; + val = out_set[OUTPUT_VAL]; + max732x_gpio_set_multiple(&chip->gpio_chip, &mask, &val); + } + return 0; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/gpio-mpc8xxx.c linux-imx-phytec/drivers/gpio/gpio-mpc8xxx.c --- linux-6.1.55/drivers/gpio/gpio-mpc8xxx.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpio/gpio-mpc8xxx.c 2024-06-19 12:33:59.916220200 +0200 @@ -430,6 +430,16 @@ return 0; } +static void mpc8xxx_shutdown(struct platform_device *pdev) +{ + struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev); + + if (mpc8xxx_gc->irq) { + irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); + irq_domain_remove(mpc8xxx_gc->irq); + } +} + #ifdef CONFIG_ACPI static const struct acpi_device_id gpio_acpi_ids[] = { {"NXP0031",}, @@ -441,6 +451,7 @@ static struct platform_driver mpc8xxx_plat_driver = { .probe = mpc8xxx_probe, .remove = mpc8xxx_remove, + .shutdown = mpc8xxx_shutdown, .driver = { .name = "gpio-mpc8xxx", .of_match_table = mpc8xxx_gpio_ids, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/gpio-mxc.c linux-imx-phytec/drivers/gpio/gpio-mxc.c --- linux-6.1.55/drivers/gpio/gpio-mxc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpio/gpio-mxc.c 2024-06-19 12:33:59.916220200 +0200 @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,12 @@ #include #include +#define IMX_SCU_WAKEUP_OFF 0 +#define IMX_SCU_WAKEUP_LOW_LVL 4 +#define IMX_SCU_WAKEUP_FALL_EDGE 5 +#define IMX_SCU_WAKEUP_RISE_EDGE 6 +#define IMX_SCU_WAKEUP_HIGH_LVL 7 + /* device type dependent stuff */ struct mxc_gpio_hwdata { unsigned dr_reg; @@ -56,13 +63,19 @@ struct clk *clk; int irq; int irq_high; + void (*mx_irq_handler)(struct irq_desc *desc); struct irq_domain *domain; struct gpio_chip gc; struct device *dev; u32 both_edges; struct mxc_gpio_reg_saved gpio_saved_reg; bool power_off; + u32 wakeup_pads; + u32 wakeup_pads_save; + bool is_pad_wakeup; + u32 pad_type[32]; const struct mxc_gpio_hwdata *hwdata; + bool gpio_ranges; }; static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { @@ -131,6 +144,9 @@ { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata }, { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata }, { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids); @@ -207,6 +223,7 @@ } writel(1 << gpio_idx, port->base + GPIO_ISR); + port->pad_type[gpio_idx] = type; raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); @@ -266,6 +283,9 @@ struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); + if (port->is_pad_wakeup) + return; + chained_irq_enter(chip, desc); irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); @@ -318,17 +338,43 @@ ret = enable_irq_wake(port->irq_high); else ret = enable_irq_wake(port->irq); + port->wakeup_pads |= (1 << gpio_idx); } else { if (port->irq_high && (gpio_idx >= 16)) ret = disable_irq_wake(port->irq_high); else ret = disable_irq_wake(port->irq); + port->wakeup_pads &= ~(1 << gpio_idx); } return ret; } -static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) +static int mxc_gpio_irq_reqres(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct mxc_gpio_port *port = gc->private; + + if (gpiochip_lock_as_irq(&port->gc, d->hwirq)) { + dev_err(port->gc.parent, + "unable to lock HW IRQ %lu for IRQ\n", + d->hwirq); + return -EINVAL; + } + + return 0; +} + +static void mxc_gpio_irq_relres(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct mxc_gpio_port *port = gc->private; + + gpiochip_unlock_as_irq(&port->gc, d->hwirq); +} + +static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base, + struct device *dev) { struct irq_chip_generic *gc; struct irq_chip_type *ct; @@ -340,6 +386,7 @@ return -ENOMEM; gc->private = port; + irq_domain_set_pm_device(port->domain, dev); ct = gc->chip_types; ct->chip.irq_ack = irq_gc_ack_set_bit; ct->chip.irq_mask = irq_gc_mask_clr_bit; @@ -347,6 +394,8 @@ ct->chip.irq_set_type = gpio_set_irq_type; ct->chip.irq_set_wake = gpio_set_wake_irq; ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND; + ct->chip.irq_request_resources = mxc_gpio_irq_reqres; + ct->chip.irq_release_resources = mxc_gpio_irq_relres, ct->regs.ack = GPIO_ISR; ct->regs.mask = GPIO_IMR; @@ -364,6 +413,30 @@ return irq_find_mapping(port->domain, offset); } +static int mxc_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + struct mxc_gpio_port *port = gpiochip_get_data(chip); + int ret; + + if (port->gpio_ranges) { + ret = gpiochip_generic_request(chip, offset); + if (ret) + return ret; + } + + ret = pm_runtime_get_sync(chip->parent); + return ret < 0 ? ret : 0; +} + +static void mxc_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + struct mxc_gpio_port *port = gpiochip_get_data(chip); + + if (port->gpio_ranges) + gpiochip_generic_free(chip, offset); + pm_runtime_put(chip->parent); +} + static int mxc_gpio_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -377,7 +450,6 @@ return -ENOMEM; port->dev = &pdev->dev; - port->hwdata = device_get_match_data(&pdev->dev); port->base = devm_platform_ioremap_resource(pdev, 0); @@ -389,7 +461,7 @@ return irq_count; if (irq_count > 1) { - port->irq_high = platform_get_irq(pdev, 1); + port->irq_high = platform_get_irq_optional(pdev, 1); if (port->irq_high < 0) port->irq_high = 0; } @@ -412,6 +484,12 @@ if (of_device_is_compatible(np, "fsl,imx7d-gpio")) port->power_off = true; + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + err = pm_runtime_get_sync(&pdev->dev); + if (err < 0) + goto out_pm_dis; + /* disable the interrupt and clear the status */ writel(0, port->base + GPIO_IMR); writel(~0, port->base + GPIO_ISR); @@ -423,6 +501,8 @@ * is more robust and easier. */ irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); + port->irq_high = -1; + port->mx_irq_handler = mx2_gpio_irq_handler; } else { /* setup one handler for each entry */ irq_set_chained_handler_and_data(port->irq, @@ -432,6 +512,7 @@ irq_set_chained_handler_and_data(port->irq_high, mx3_gpio_irq_handler, port); + port->mx_irq_handler = mx3_gpio_irq_handler; } err = bgpio_init(&port->gc, &pdev->dev, 4, @@ -442,8 +523,14 @@ if (err) goto out_bgio; - port->gc.request = gpiochip_generic_request; - port->gc.free = gpiochip_generic_free; + if (of_property_read_bool(np, "gpio_ranges")) + port->gpio_ranges = true; + else + port->gpio_ranges = false; + + port->gc.request = mxc_gpio_request; + port->gc.free = mxc_gpio_free; + port->gc.parent = &pdev->dev; port->gc.to_irq = mxc_gpio_to_irq; port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : pdev->id * 32; @@ -466,16 +553,20 @@ } /* gpio-mxc can be a generic irq chip */ - err = mxc_gpio_init_gc(port, irq_base); + err = mxc_gpio_init_gc(port, irq_base, &pdev->dev); if (err < 0) goto out_irqdomain_remove; list_add_tail(&port->node, &mxc_gpio_ports); platform_set_drvdata(pdev, port); + pm_runtime_put(&pdev->dev); return 0; +out_pm_dis: + pm_runtime_disable(&pdev->dev); + clk_disable_unprepare(port->clk); out_irqdomain_remove: irq_domain_remove(port->domain); out_bgio: @@ -510,12 +601,147 @@ writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); } +static bool mxc_gpio_generic_config(struct mxc_gpio_port *port, + unsigned int offset, unsigned long conf) +{ + struct device_node *np = port->dev->of_node; + + if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") || + of_device_is_compatible(np, "fsl,imx8qxp-gpio") || + of_device_is_compatible(np, "fsl,imx8qm-gpio")) + return (gpiochip_generic_config(&port->gc, offset, conf) == 0); + + return false; +} + +static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable) +{ + unsigned long config; + bool ret = false; + int i, type; + + static const u32 pad_type_map[] = { + IMX_SCU_WAKEUP_OFF, /* 0 */ + IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */ + IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */ + IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_BOTH */ + IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */ + IMX_SCU_WAKEUP_OFF, /* 5 */ + IMX_SCU_WAKEUP_OFF, /* 6 */ + IMX_SCU_WAKEUP_OFF, /* 7 */ + IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */ + }; + + for (i = 0; i < 32; i++) { + if ((port->wakeup_pads & (1 << i))) { + type = port->pad_type[i]; + if (enable) + config = pad_type_map[type]; + else + config = IMX_SCU_WAKEUP_OFF; + ret |= mxc_gpio_generic_config(port, i, config); + } + } + + return ret; +} + +static int __maybe_unused mxc_gpio_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + + mxc_gpio_save_regs(port); + clk_disable_unprepare(port->clk); + irq_set_chained_handler_and_data(port->irq, NULL, NULL); + if (port->irq_high > 0) + irq_set_chained_handler_and_data(port->irq_high, NULL, NULL); + + return 0; +} + +static int __maybe_unused mxc_gpio_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + int ret; + + irq_set_chained_handler_and_data(port->irq, + port->mx_irq_handler, port); + if (port->irq_high > 0) + /* setup handler for GPIO 16 to 31 */ + irq_set_chained_handler_and_data(port->irq_high, + port->mx_irq_handler, + port); + + ret = clk_prepare_enable(port->clk); + if (ret) { + irq_set_chained_handler_and_data(port->irq, NULL, NULL); + if (port->irq_high > 0) + irq_set_chained_handler_and_data(port->irq_high, NULL, NULL); + return ret; + } + + mxc_gpio_restore_regs(port); + + return 0; +} + +static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + + if (port->wakeup_pads > 0) + port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true); + + return 0; +} + +static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + + if (port->wakeup_pads > 0) { + mxc_gpio_set_pad_wakeup(port, false); + port->wakeup_pads_save = port->wakeup_pads; + } + port->is_pad_wakeup = false; + + return 0; +} + +static void mxc_gpio_complete(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + struct irq_desc *desc = irq_to_desc(port->irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + + if (port->wakeup_pads_save > 0) { + chained_irq_enter(chip, desc); + chained_irq_exit(chip, desc); + port->wakeup_pads_save = 0; + } +} + +static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume) + SET_RUNTIME_PM_OPS(mxc_gpio_runtime_suspend, mxc_gpio_runtime_resume, NULL) + .complete = mxc_gpio_complete, +}; + static int mxc_gpio_syscore_suspend(void) { struct mxc_gpio_port *port; + int ret; /* walk through all ports */ list_for_each_entry(port, &mxc_gpio_ports, node) { + ret = clk_prepare_enable(port->clk); + if (ret) + return ret; mxc_gpio_save_regs(port); clk_disable_unprepare(port->clk); } @@ -536,6 +762,7 @@ return; } mxc_gpio_restore_regs(port); + clk_disable_unprepare(port->clk); } } @@ -549,6 +776,7 @@ .name = "gpio-mxc", .of_match_table = mxc_gpio_dt_ids, .suppress_bind_attrs = true, + .pm = &mxc_gpio_dev_pm_ops, }, .probe = mxc_gpio_probe, }; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/gpio-pca953x.c linux-imx-phytec/drivers/gpio/gpio-pca953x.c --- linux-6.1.55/drivers/gpio/gpio-pca953x.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpio/gpio-pca953x.c 2024-06-19 12:33:59.920220268 +0200 @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -308,7 +309,7 @@ int bank; int offset; - if (reg >= 0x30) { + if (reg >= 0x30 && reg < 0x54) { /* * Reserved block between 14h and 2Fh does not align on * expected bank boundaries like other devices. @@ -452,7 +453,7 @@ static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off) { int addr; - int pinctrl; + int pinctrl = 0; addr = (reg & PCAL_GPIO_MASK) * NBANK(chip); @@ -1167,6 +1168,10 @@ lockdep_set_subclass(&chip->i2c_lock, i2c_adapter_depth(client->adapter)); + ret = device_reset(&client->dev); + if (ret == -EPROBE_DEFER) + return -EPROBE_DEFER; + /* initialize cached registers from their original values. * we can't share this chip with another i2c master. */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/gpio-qixis-cpld.c linux-imx-phytec/drivers/gpio/gpio-qixis-cpld.c --- linux-6.1.55/drivers/gpio/gpio-qixis-cpld.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpio/gpio-qixis-cpld.c 2024-06-19 12:33:59.920220268 +0200 @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Layerscape GPIO CPLD driver + * + * Copyright 2023 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +enum qixis_cpld_gpio_type { + LX2160ARDB_CPLD_GPIO = 0, +}; + +struct qixis_cpld_gpio_config { + enum qixis_cpld_gpio_type type; + unsigned int input_lines; +}; + +static struct qixis_cpld_gpio_config lx2160ardb_cpld_gpio_cfg = { + .type = LX2160ARDB_CPLD_GPIO, + .input_lines = GENMASK(7, 1), +}; + +static int qixis_cpld_gpio_get_direction(struct gpio_regmap *gpio, unsigned int offset) +{ + struct qixis_cpld_gpio_config *cfg = gpio_regmap_get_drvdata(gpio); + + if (cfg->input_lines & BIT(offset)) + return GPIO_LINE_DIRECTION_IN; + else + return GPIO_LINE_DIRECTION_OUT; +} + +static int qixis_cpld_gpio_probe(struct platform_device *pdev) +{ + const struct qixis_cpld_gpio_config *cfg; + struct gpio_regmap_config config = {0}; + struct regmap *regmap; + u32 base; + int ret; + + if (!pdev->dev.parent) + return -ENODEV; + + cfg = device_get_match_data(&pdev->dev); + if (!cfg) + return -ENODEV; + + ret = device_property_read_u32(&pdev->dev, "reg", &base); + if (ret) + return ret; + + regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!regmap) + return -ENODEV; + + config.get_direction = qixis_cpld_gpio_get_direction; + config.drvdata = (void *)cfg; + config.regmap = regmap; + config.parent = &pdev->dev; + config.ngpio_per_reg = 8; + config.ngpio = 8; + + switch (cfg->type) { + case LX2160ARDB_CPLD_GPIO: + config.reg_dat_base = base; + config.reg_set_base = base; + break; + } + + return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(&pdev->dev, &config)); +} + +static const struct of_device_id qixis_cpld_gpio_of_match[] = { + { + .compatible = "fsl,lx2160a-rdb-qixis-cpld-gpio", + .data = &lx2160ardb_cpld_gpio_cfg + }, + {} +}; +MODULE_DEVICE_TABLE(of, qixis_cpld_gpio_of_match); + +static struct platform_driver qixis_cpld_gpio_driver = { + .probe = qixis_cpld_gpio_probe, + .driver = { + .name = "gpio-qixis-cpld", + .of_match_table = qixis_cpld_gpio_of_match, + }, +}; +module_platform_driver(qixis_cpld_gpio_driver); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/gpio-regmap.c linux-imx-phytec/drivers/gpio/gpio-regmap.c --- linux-6.1.55/drivers/gpio/gpio-regmap.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpio/gpio-regmap.c 2024-06-19 12:33:59.920220268 +0200 @@ -24,6 +24,8 @@ unsigned int reg_dir_in_base; unsigned int reg_dir_out_base; + int (*get_direction)(struct gpio_regmap *gpio, unsigned int offset); + int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base, unsigned int offset, unsigned int *reg, unsigned int *mask); @@ -111,6 +113,9 @@ unsigned int base, val, reg, mask; int invert, ret; + if (gpio->get_direction) + return gpio->get_direction(gpio, offset); + if (gpio->reg_dir_out_base) { base = gpio_regmap_addr(gpio->reg_dir_out_base); invert = 0; @@ -140,7 +145,16 @@ { struct gpio_regmap *gpio = gpiochip_get_data(chip); unsigned int base, val, reg, mask; - int invert, ret; + int invert, ret, dir; + + if (gpio->get_direction) { + dir = gpio->get_direction(gpio, offset); + if (dir == GPIO_LINE_DIRECTION_IN && output) + return -EOPNOTSUPP; + if (dir == GPIO_LINE_DIRECTION_OUT && !output) + return -EOPNOTSUPP; + return 0; + } if (gpio->reg_dir_out_base) { base = gpio_regmap_addr(gpio->reg_dir_out_base); @@ -230,6 +244,7 @@ gpio->reg_clr_base = config->reg_clr_base; gpio->reg_dir_in_base = config->reg_dir_in_base; gpio->reg_dir_out_base = config->reg_dir_out_base; + gpio->get_direction = config->get_direction; /* if not set, assume there is only one register */ if (!gpio->ngpio_per_reg) @@ -265,7 +280,8 @@ else if (gpio->reg_set_base) chip->set = gpio_regmap_set; - if (gpio->reg_dir_in_base || gpio->reg_dir_out_base) { + if (gpio->reg_dir_in_base || gpio->reg_dir_out_base || + gpio->get_direction) { chip->get_direction = gpio_regmap_get_direction; chip->direction_input = gpio_regmap_direction_input; chip->direction_output = gpio_regmap_direction_output; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/gpio-vf610.c linux-imx-phytec/drivers/gpio/gpio-vf610.c --- linux-6.1.55/drivers/gpio/gpio-vf610.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpio/gpio-vf610.c 2024-06-19 12:33:59.924220336 +0200 @@ -30,7 +30,6 @@ struct vf610_gpio_port { struct gpio_chip gc; - struct irq_chip ic; void __iomem *base; void __iomem *gpio_base; const struct fsl_gpio_soc_data *sdata; @@ -207,20 +206,24 @@ static void vf610_gpio_irq_mask(struct irq_data *d) { - struct vf610_gpio_port *port = - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct vf610_gpio_port *port = gpiochip_get_data(gc); + irq_hw_number_t gpio_num = irqd_to_hwirq(d); + void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); vf610_gpio_writel(0, pcr_base); + gpiochip_disable_irq(gc, gpio_num); } static void vf610_gpio_irq_unmask(struct irq_data *d) { - struct vf610_gpio_port *port = - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct vf610_gpio_port *port = gpiochip_get_data(gc); + irq_hw_number_t gpio_num = irqd_to_hwirq(d); + void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); - vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET, + gpiochip_enable_irq(gc, gpio_num); + vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET, pcr_base); } @@ -237,6 +240,17 @@ return 0; } +static const struct irq_chip vf610_irqchip = { + .name = "gpio-vf610", + .irq_ack = vf610_gpio_irq_ack, + .irq_mask = vf610_gpio_irq_mask, + .irq_unmask = vf610_gpio_irq_unmask, + .irq_set_type = vf610_gpio_irq_set_type, + .irq_set_wake = vf610_gpio_irq_set_wake, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static void vf610_gpio_disable_clk(void *data) { clk_disable_unprepare(data); @@ -249,7 +263,6 @@ struct vf610_gpio_port *port; struct gpio_chip *gc; struct gpio_irq_chip *girq; - struct irq_chip *ic; int i; int ret; @@ -315,14 +328,6 @@ gc->direction_output = vf610_gpio_direction_output; gc->set = vf610_gpio_set; - ic = &port->ic; - ic->name = "gpio-vf610"; - ic->irq_ack = vf610_gpio_irq_ack; - ic->irq_mask = vf610_gpio_irq_mask; - ic->irq_unmask = vf610_gpio_irq_unmask; - ic->irq_set_type = vf610_gpio_irq_set_type; - ic->irq_set_wake = vf610_gpio_irq_set_wake; - /* Mask all GPIO interrupts */ for (i = 0; i < gc->ngpio; i++) vf610_gpio_writel(0, port->base + PORT_PCR(i)); @@ -331,7 +336,7 @@ vf610_gpio_writel(~0, port->base + PORT_ISFR); girq = &gc->irq; - girq->chip = ic; + gpio_irq_chip_set_chip(girq, &vf610_irqchip); girq->parent_handler = vf610_gpio_irq_handler; girq->num_parents = 1; girq->parents = devm_kcalloc(&pdev->dev, 1, diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/Kconfig linux-imx-phytec/drivers/gpio/Kconfig --- linux-6.1.55/drivers/gpio/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpio/Kconfig 2024-06-19 12:33:59.908220063 +0200 @@ -341,6 +341,12 @@ If unsure, say N. +config GPIO_IMX_RPMSG + tristate "NXP i.MX7ULP RPMSG GPIO support" + depends on ARCH_MXC && RPMSG && GPIOLIB + help + This driver support i.MX7ULP RPMSG virtual GPIOs. + config GPIO_IMX_SCU def_bool y depends on IMX_SCU @@ -1129,6 +1135,13 @@ This option enables support for on-chip GPIO found on Analog Devices ADP5520 PMICs. +config GPIO_ADP5585 + tristate "GPIO Support for ADP5585" + depends on MFD_ADP5585 + help + This option enables support for on-chip GPIO found + on Analog Devices ADP5585. + config GPIO_ALTERA_A10SR tristate "Altera Arria10 System Resource GPIO" depends on MFD_ALTERA_A10SR @@ -1681,6 +1694,16 @@ industrial control context, to be operated from userspace using the GPIO chardev interface. +config GPIO_QIXIS_CPLD + tristate "NXP QIXIS CPLD GPIO support" + depends on MFD_SIMPLE_MFD_I2C || COMPILE_TEST + select GPIO_REGMAP + help + This enables support for the GPIOs found on the QIXIS CPLD which is + integrated on some NXP Layerscape boards such as LX2160ARDB. The + driver can be build as a module as well which will be names + gpio-qixis-cpld. + config GPIO_MOCKUP tristate "GPIO Testing Driver" select IRQ_SIM diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpio/Makefile linux-imx-phytec/drivers/gpio/Makefile --- linux-6.1.55/drivers/gpio/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpio/Makefile 2024-06-19 12:33:59.908220063 +0200 @@ -25,6 +25,7 @@ obj-$(CONFIG_GPIO_74XX_MMIO) += gpio-74xx-mmio.o obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o +obj-$(CONFIG_GPIO_ADP5585) += gpio-adp5585.o obj-$(CONFIG_GPIO_AGGREGATOR) += gpio-aggregator.o obj-$(CONFIG_GPIO_ALTERA_A10SR) += gpio-altera-a10sr.o obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o @@ -121,6 +122,7 @@ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o +obj-$(CONFIG_GPIO_QIXIS_CPLD) += gpio-qixis-cpld.o obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o @@ -167,6 +169,7 @@ obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_GPIO_VF610) += gpio-vf610.o +obj-$(CONFIG_GPIO_IMX_RPMSG) += gpio-imx-rpmsg.o obj-$(CONFIG_GPIO_VIPERBOARD) += gpio-viperboard.o obj-$(CONFIG_GPIO_VIRTIO) += gpio-virtio.o obj-$(CONFIG_GPIO_VISCONTI) += gpio-visconti.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/arm/malidp_crtc.c linux-imx-phytec/drivers/gpu/drm/arm/malidp_crtc.c --- linux-6.1.55/drivers/gpu/drm/arm/malidp_crtc.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/arm/malidp_crtc.c 2024-06-19 12:34:01.880253784 +0200 @@ -32,7 +32,7 @@ * check that the hardware can drive the required clock rate, * but skip the check if the clock is meant to be disabled (req_rate = 0) */ - long rate, req_rate = mode->crtc_clock * 1000; + long rate, req_rate = mode->clock * 1000; if (req_rate) { rate = clk_round_rate(hwdev->pxlclk, req_rate); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c linux-imx-phytec/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c --- linux-6.1.55/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 2024-06-19 12:34:01.888253921 +0200 @@ -8,8 +8,11 @@ #include #include #include +#include #include +#include #include +#include #include #include @@ -74,6 +77,25 @@ 0x00, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; +/* + * TODO: Currently, filter-out unsupported modes by their clocks. + * Need to find a better way to do this. + * These are the pixel clocks that the converter can handle successfully. + */ + +static const int valid_clocks[] = { + 148500, + 135000, + 132000, + 108000, + 78750, + 74250, + 65000, + 49500, + 40000, + 31500, +}; + static bool adv7511_register_volatile(struct device *dev, unsigned int reg) { switch (reg) { @@ -329,6 +351,7 @@ { adv7511->current_edid_segment = -1; + /* 01-02 Power */ regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, ADV7511_POWER_POWER_DOWN, 0); if (adv7511->i2c_main->irq) { @@ -346,6 +369,7 @@ } /* + * 01-01 HPD Manual Override * Per spec it is allowed to pulse the HPD signal to indicate that the * EDID information has changed. Some monitors do this when they wakeup * from standby or are enabled. When the HPD goes low the adv7511 is @@ -427,17 +451,16 @@ static void adv7511_hpd_work(struct work_struct *work) { struct adv7511 *adv7511 = container_of(work, struct adv7511, hpd_work); - enum drm_connector_status status; + enum drm_connector_status status = connector_status_disconnected; unsigned int val; int ret; ret = regmap_read(adv7511->regmap, ADV7511_REG_STATUS, &val); - if (ret < 0) - status = connector_status_disconnected; - else if (val & ADV7511_STATUS_HPD) + if (ret >= 0 && (val & ADV7511_STATUS_HPD)) status = connector_status_connected; - else - status = connector_status_disconnected; + + DRM_DEV_DEBUG_DRIVER(adv7511->connector.kdev, "HDMI HPD event: %s\n", + drm_get_connector_status_name(status)); /* * The bridge resets its registers on unplug. So when we get a plug @@ -639,6 +662,8 @@ { struct edid *edid; unsigned int count; + u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; + int ret; edid = adv7511_get_edid(adv7511, connector); @@ -647,6 +672,14 @@ kfree(edid); + connector->display_info.bus_flags = DRM_BUS_FLAG_DE_LOW | + DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE; + + ret = drm_display_info_set_bus_formats(&connector->display_info, + &bus_format, 1); + if (ret) + return ret; + return count; } @@ -699,9 +732,21 @@ static enum drm_mode_status adv7511_mode_valid(struct adv7511 *adv7511, const struct drm_display_mode *mode) { + size_t i, num_modes = ARRAY_SIZE(valid_clocks); + bool clock_ok = false; + if (mode->clock > 165000) return MODE_CLOCK_HIGH; + for (i = 0; i < num_modes; i++) + if (mode->clock == valid_clocks[i]) { + clock_ok = true; + break; + } + + if (!clock_ok) + return MODE_NOCLOCK; + return MODE_OK; } @@ -906,6 +951,14 @@ adv7511_power_off(adv); } +static int adv7511_bridge_get_modes(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct adv7511 *adv = bridge_to_adv7511(bridge); + + return adv7511_get_modes(adv, connector); +} + static void adv7511_bridge_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *mode, const struct drm_display_mode *adj_mode) @@ -939,6 +992,9 @@ return ret; } + if (adv->type == ADV7533 || adv->type == ADV7535) + ret = adv7533_attach_dsi(adv); + if (adv->i2c_main->irq) regmap_write(adv->regmap, ADV7511_REG_INT_ENABLE(0), ADV7511_INT0_HPD); @@ -970,15 +1026,32 @@ cec_phys_addr_invalidate(adv->cec_adap); } +static void adv7511_bridge_detach(struct drm_bridge *bridge) +{ + struct adv7511 *adv = bridge_to_adv7511(bridge); + + if (adv->i2c_main->irq) + regmap_write(adv->regmap, ADV7511_REG_INT_ENABLE(0), 0); + + if (adv->type == ADV7533 || adv->type == ADV7535) { + mipi_dsi_detach(adv->dsi); + mipi_dsi_device_unregister(adv->dsi); + } + + drm_connector_cleanup(&adv->connector); +} + static const struct drm_bridge_funcs adv7511_bridge_funcs = { .enable = adv7511_bridge_enable, .disable = adv7511_bridge_disable, + .get_modes = adv7511_bridge_get_modes, .mode_set = adv7511_bridge_mode_set, .mode_valid = adv7511_bridge_mode_valid, .attach = adv7511_bridge_attach, .detect = adv7511_bridge_detect, .get_edid = adv7511_bridge_get_edid, .hpd_notify = adv7511_bridge_hpd_notify, + .detach = adv7511_bridge_detach, }; /* ----------------------------------------------------------------------------- @@ -1077,7 +1150,7 @@ int ret; adv->i2c_cec = i2c_new_ancillary_device(adv->i2c_main, "cec", - ADV7511_CEC_I2C_ADDR_DEFAULT); + adv->addr_cec); if (IS_ERR(adv->i2c_cec)) return PTR_ERR(adv->i2c_cec); @@ -1195,6 +1268,14 @@ struct adv7511_link_config link_config; struct adv7511 *adv7511; struct device *dev = &i2c->dev; +#if IS_ENABLED(CONFIG_OF_DYNAMIC) + struct device_node *remote_node = NULL, *endpoint = NULL; + struct of_changeset ocs; +#endif + unsigned int main_i2c_addr = i2c->addr << 1; + unsigned int edid_i2c_addr = main_i2c_addr + 4; + unsigned int cec_i2c_addr = main_i2c_addr - 2; + unsigned int pkt_i2c_addr = main_i2c_addr - 0xa; unsigned int val; int ret; @@ -1229,6 +1310,21 @@ return ret; } + if (adv7511->addr_cec != 0) + cec_i2c_addr = adv7511->addr_cec << 1; + else + adv7511->addr_cec = cec_i2c_addr >> 1; + + if (adv7511->addr_edid != 0) + edid_i2c_addr = adv7511->addr_edid << 1; + else + adv7511->addr_edid = edid_i2c_addr >> 1; + + if (adv7511->addr_pkt != 0) + pkt_i2c_addr = adv7511->addr_pkt << 1; + else + adv7511->addr_pkt = pkt_i2c_addr >> 1; + /* * The power down GPIO is optional. If present, toggle it from active to * inactive to wake up the encoder. @@ -1266,25 +1362,28 @@ adv7511_packet_disable(adv7511, 0xffff); + regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR, + edid_i2c_addr); + adv7511->i2c_edid = i2c_new_ancillary_device(i2c, "edid", - ADV7511_EDID_I2C_ADDR_DEFAULT); + adv7511->addr_edid); if (IS_ERR(adv7511->i2c_edid)) { ret = PTR_ERR(adv7511->i2c_edid); goto uninit_regulators; } - regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR, - adv7511->i2c_edid->addr << 1); + regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR, + pkt_i2c_addr); adv7511->i2c_packet = i2c_new_ancillary_device(i2c, "packet", - ADV7511_PACKET_I2C_ADDR_DEFAULT); + adv7511->addr_pkt); if (IS_ERR(adv7511->i2c_packet)) { ret = PTR_ERR(adv7511->i2c_packet); goto err_i2c_unregister_edid; } - regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR, - adv7511->i2c_packet->addr << 1); + regmap_write(adv7511->regmap, ADV7511_REG_CEC_I2C_ADDR, + cec_i2c_addr); ret = adv7511_init_cec_regmap(adv7511); if (ret) @@ -1325,18 +1424,8 @@ drm_bridge_add(&adv7511->bridge); adv7511_audio_init(dev, adv7511); - - if (adv7511->type == ADV7533 || adv7511->type == ADV7535) { - ret = adv7533_attach_dsi(adv7511); - if (ret) - goto err_unregister_audio; - } - return 0; -err_unregister_audio: - adv7511_audio_exit(adv7511); - drm_bridge_remove(&adv7511->bridge); err_unregister_cec: cec_unregister_adapter(adv7511->cec_adap); i2c_unregister_device(adv7511->i2c_cec); @@ -1347,6 +1436,40 @@ i2c_unregister_device(adv7511->i2c_edid); uninit_regulators: adv7511_uninit_regulators(adv7511); +#if IS_ENABLED(CONFIG_OF_DYNAMIC) + if (ret == -EPROBE_DEFER) + return ret; + + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); + if (endpoint) + remote_node = of_graph_get_remote_port_parent(endpoint); + + if (!remote_node) + return ret; + + /* Find remote's endpoint connected to us and detach it */ + endpoint = NULL; + while ((endpoint = of_graph_get_next_endpoint(remote_node, + endpoint))) { + struct device_node *us; + + us = of_graph_get_remote_port_parent(endpoint); + if (us == dev->of_node) + break; + } + of_node_put(remote_node); + + if (!endpoint) + return ret; + + of_changeset_init(&ocs); + of_changeset_detach_node(&ocs, endpoint); + ret = of_changeset_apply(&ocs); + if (!ret) + dev_warn(dev, + "Probe failed. Remote port '%s' disabled\n", + remote_node->full_name); +#endif return ret; } diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/adv7511/adv7511.h linux-imx-phytec/drivers/gpu/drm/bridge/adv7511/adv7511.h --- linux-6.1.55/drivers/gpu/drm/bridge/adv7511/adv7511.h 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/adv7511/adv7511.h 2024-06-19 12:34:01.888253921 +0200 @@ -227,6 +227,9 @@ #define ADV7511_REG_CEC_SOFT_RESET 0x50 #define ADV7533_REG_CEC_OFFSET 0x70 +#define FORMAT_RATIO(x, y) (((x) * 100) / (y)) +#define RATIO_16_9 FORMAT_RATIO(16, 9) +#define RATIO_4_3 FORMAT_RATIO(4, 3) enum adv7511_input_clock { ADV7511_INPUT_CLOCK_1X, @@ -339,6 +342,10 @@ struct i2c_client *i2c_packet; struct i2c_client *i2c_cec; + u32 addr_cec; + u32 addr_edid; + u32 addr_pkt; + struct regmap *regmap; struct regmap *regmap_cec; unsigned int reg_cec_offset; @@ -375,6 +382,7 @@ struct device_node *host_node; struct mipi_dsi_device *dsi; u8 num_dsi_lanes; + u8 channel_id; bool use_timing_gen; enum adv7511_type type; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/adv7511/adv7533.c linux-imx-phytec/drivers/gpu/drm/bridge/adv7511/adv7533.c --- linux-6.1.55/drivers/gpu/drm/bridge/adv7511/adv7533.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/adv7511/adv7533.c 2024-06-19 12:34:01.888253921 +0200 @@ -26,10 +26,8 @@ static void adv7511_dsi_config_timing_gen(struct adv7511 *adv) { - struct mipi_dsi_device *dsi = adv->dsi; struct drm_display_mode *mode = &adv->curr_mode; unsigned int hsw, hfp, hbp, vsw, vfp, vbp; - static const u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */ hsw = mode->hsync_end - mode->hsync_start; hfp = mode->hsync_start - mode->hdisplay; @@ -38,9 +36,10 @@ vfp = mode->vsync_start - mode->vdisplay; vbp = mode->vtotal - mode->vsync_end; - /* set pixel clock divider mode */ - regmap_write(adv->regmap_cec, 0x16, - clock_div_by_lanes[dsi->lanes - 2] << 3); + /* 03-01 Enable Internal Timing Generator */ + regmap_write(adv->regmap_cec, 0x27, 0xcb); + + /* 03-08 Timing Configuration */ /* horizontal porch params */ regmap_write(adv->regmap_cec, 0x28, mode->htotal >> 4); @@ -61,35 +60,66 @@ regmap_write(adv->regmap_cec, 0x35, (vfp << 4) & 0xff); regmap_write(adv->regmap_cec, 0x36, vbp >> 4); regmap_write(adv->regmap_cec, 0x37, (vbp << 4) & 0xff); + + /* 03-03 Reset Internal Timing Generator */ + regmap_write(adv->regmap_cec, 0x27, 0xcb); + regmap_write(adv->regmap_cec, 0x27, 0x8b); + regmap_write(adv->regmap_cec, 0x27, 0xcb); + } void adv7533_dsi_power_on(struct adv7511 *adv) { struct mipi_dsi_device *dsi = adv->dsi; + struct drm_display_mode *mode = &adv->curr_mode; + u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */ - if (adv->use_timing_gen) - adv7511_dsi_config_timing_gen(adv); + /* Gate DSI LP Oscillator */ + regmap_update_bits(adv->regmap_cec, 0x03, 0x02, 0x00); + + /* 01-03 Initialisation (Fixed) Registers */ + regmap_register_patch(adv->regmap_cec, adv7533_cec_fixed_registers, + ARRAY_SIZE(adv7533_cec_fixed_registers)); - /* set number of dsi lanes */ + /* 02-04 DSI Lanes */ regmap_write(adv->regmap_cec, 0x1c, dsi->lanes << 4); - if (adv->use_timing_gen) { - /* reset internal timing generator */ - regmap_write(adv->regmap_cec, 0x27, 0xcb); - regmap_write(adv->regmap_cec, 0x27, 0x8b); - regmap_write(adv->regmap_cec, 0x27, 0xcb); - } else { - /* disable internal timing generator */ + /* 02-05 DSI Pixel Clock Divider */ + regmap_write(adv->regmap_cec, 0x16, + clock_div_by_lanes[dsi->lanes - 2] << 3); + + if (adv->use_timing_gen) + adv7511_dsi_config_timing_gen(adv); + else regmap_write(adv->regmap_cec, 0x27, 0x0b); - } - /* enable hdmi */ + /* 04-01 HDMI Output */ + regmap_write(adv->regmap, 0xaf, 0x16); + + /* 09-03 AVI Infoframe - RGB - 16-9 Aspect Ratio */ + regmap_write(adv->regmap, ADV7511_REG_AVI_INFOFRAME(0), 0x10); + if (FORMAT_RATIO(mode->hdisplay, mode->vdisplay) == RATIO_16_9) + regmap_write(adv->regmap, ADV7511_REG_AVI_INFOFRAME(1), 0x28); + else if (FORMAT_RATIO(mode->hdisplay, mode->vdisplay) == RATIO_4_3) + regmap_write(adv->regmap, ADV7511_REG_AVI_INFOFRAME(1), 0x18); + + /* 04-04 GC Packet Enable */ + regmap_write(adv->regmap, ADV7511_REG_PACKET_ENABLE0, 0x80); + + /* 04-06 GC Colour Depth - 24 Bit */ + regmap_write(adv->regmap, 0x4c, 0x04); + + /* 04-09 Down Dither Output Colour Depth - 8 Bit (default) */ + regmap_write(adv->regmap, 0x49, 0x00); + + /* 07-01 CEC Power Mode - Always Active */ + regmap_write(adv->regmap_cec, 0xbe, 0x3d); + + /* 04-03 HDMI Output Enable */ regmap_write(adv->regmap_cec, 0x03, 0x89); /* disable test mode */ regmap_write(adv->regmap_cec, 0x55, 0x00); - regmap_register_patch(adv->regmap_cec, adv7533_cec_fixed_registers, - ARRAY_SIZE(adv7533_cec_fixed_registers)); } void adv7533_dsi_power_off(struct adv7511 *adv) @@ -141,7 +171,7 @@ struct mipi_dsi_device *dsi; int ret = 0; const struct mipi_dsi_device_info info = { .type = "adv7533", - .channel = 0, + .channel = adv->channel_id, .node = NULL, }; @@ -175,14 +205,24 @@ int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv) { - u32 num_lanes; + struct device *dev = &adv->i2c_main->dev; + u32 num_lanes = 0, channel_id = 0; + of_property_read_u32(np, "adi,dsi-channel", &channel_id); of_property_read_u32(np, "adi,dsi-lanes", &num_lanes); - if (num_lanes < 1 || num_lanes > 4) + if (num_lanes < 1 || num_lanes > 4) { + dev_err(dev, "Invalid dsi-lanes: %d\n", num_lanes); + return -EINVAL; + } + + if (channel_id > 3) { + dev_err(dev, "Invalid dsi-channel: %d\n", channel_id); return -EINVAL; + } adv->num_dsi_lanes = num_lanes; + adv->channel_id = channel_id; adv->host_node = of_graph_get_remote_node(np, 0, 0); if (!adv->host_node) @@ -193,6 +233,10 @@ adv->use_timing_gen = !of_property_read_bool(np, "adi,disable-timing-generator"); + of_property_read_u32(np, "adi,addr-cec", &adv->addr_cec); + of_property_read_u32(np, "adi,addr-edid", &adv->addr_edid); + of_property_read_u32(np, "adi,addr-pkt", &adv->addr_pkt); + /* TODO: Check if these need to be parsed by DT or not */ adv->rgb = true; adv->embedded_sync = false; diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/adv7511/Kconfig linux-imx-phytec/drivers/gpu/drm/bridge/adv7511/Kconfig --- linux-6.1.55/drivers/gpu/drm/bridge/adv7511/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/adv7511/Kconfig 2024-06-19 12:34:01.888253921 +0200 @@ -5,6 +5,7 @@ select DRM_KMS_HELPER select REGMAP_I2C select DRM_MIPI_DSI + select OF_OVERLAY help Support for the Analog Devices ADV7511(W)/13/33/35 HDMI encoders. diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,895 @@ +/* + * Cadence Display Port Interface (DP) driver + * + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cdns-mhdp-hdcp.h" +#include "cdns-hdcp-common.h" + +#define CDNS_DP_HPD_POLL_DWN_LOOP 5 +#define CDNS_DP_HPD_POLL_DWN_DLY_US 200 +#define CDNS_DP_HPD_POLL_UP_LOOP 5 +#define CDNS_DP_HPD_POLL_UP_DLY_US 1000 + +/* + * This function only implements native DPDC reads and writes + */ +static ssize_t dp_aux_transfer(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(aux->dev); + bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); + int ret; + + /* Ignore address only message , for native */ + if ((native == true) && ((msg->size == 0) || (msg->buffer == NULL))) { + msg->reply = DP_AUX_NATIVE_REPLY_ACK; + return msg->size; + } + + /* msg sanity check */ + if (msg->size > DP_AUX_MAX_PAYLOAD_BYTES) { + dev_err(mhdp->dev, "%s: invalid msg: size(%zu), request(%x)\n", + __func__, msg->size, (unsigned int)msg->request); + return -EINVAL; + } + + if (msg->request == DP_AUX_NATIVE_WRITE) { + const u8 *buf = msg->buffer; + int i; + for (i = 0; i < msg->size; ++i) { + ret = cdns_mhdp_dpcd_write(mhdp, + msg->address + i, buf[i]); + if (!ret) + continue; + + DRM_DEV_ERROR(mhdp->dev, "Failed to write DPCD\n"); + + return ret; + } + msg->reply = DP_AUX_NATIVE_REPLY_ACK; + return msg->size; + } + + if (msg->request == DP_AUX_NATIVE_READ) { + ret = cdns_mhdp_dpcd_read(mhdp, msg->address, msg->buffer, + msg->size); + if (ret < 0) + return -EIO; + msg->reply = DP_AUX_NATIVE_REPLY_ACK; + return msg->size; + } + + if (((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) + || ((msg->request & ~DP_AUX_I2C_MOT) == + DP_AUX_I2C_WRITE_STATUS_UPDATE)) { + + u8 i2c_status = 0u; + u16 respSize = 0u; + + ret = cdns_mhdp_i2c_write(mhdp, msg->address, + msg->buffer, + !!(msg->request & DP_AUX_I2C_MOT), + msg->size, &respSize); + + if (ret < 0) { + dev_err(aux->dev, "cdns_mhdp_i2c_write status %d\n", + ret); + return -EIO; + } + + ret = cdns_mhdp_get_last_i2c_status(mhdp, &i2c_status); + if (ret < 0) { + dev_err(aux->dev, + "cdns_mhdp_get_last_i2c_status status %d\n", + ret); + return -EIO; + } + + switch (i2c_status) { + case 0u: + msg->reply = DP_AUX_I2C_REPLY_ACK; + break; + case 1u: + msg->reply = DP_AUX_I2C_REPLY_NACK; + break; + case 2u: + msg->reply = DP_AUX_I2C_REPLY_DEFER; + break; + default: + msg->reply = DP_AUX_I2C_REPLY_NACK; + break; + } + + return respSize; + } + + if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ) { + + u8 i2c_status = 0u; + u16 respSize = 0u; + + ret = cdns_mhdp_i2c_read(mhdp, msg->address, msg->buffer, + msg->size, + !!(msg->request & DP_AUX_I2C_MOT), + &respSize); + if (ret < 0) + return -EIO; + + ret = cdns_mhdp_get_last_i2c_status(mhdp, &i2c_status); + + if (ret < 0) { + dev_err(aux->dev, + "cdns_mhdp_get_last_i2c_status ret %d\n", ret); + return -EIO; + } + + switch (i2c_status) { + case 0u: + msg->reply = DP_AUX_I2C_REPLY_ACK; + break; + case 1u: + msg->reply = DP_AUX_I2C_REPLY_NACK; + break; + case 2u: + msg->reply = DP_AUX_I2C_REPLY_DEFER; + break; + default: + msg->reply = DP_AUX_I2C_REPLY_NACK; + break; + } + + return respSize; + } + + return 0; +} + +static int dp_aux_init(struct cdns_mhdp_device *mhdp, + struct device *dev) +{ + int ret; + + mhdp->dp.aux.name = "imx_dp_aux"; + mhdp->dp.aux.dev = dev; + mhdp->dp.aux.drm_dev = mhdp->drm_dev; + mhdp->dp.aux.transfer = dp_aux_transfer; + + ret = drm_dp_aux_register(&mhdp->dp.aux); + + return ret; +} + +static int dp_aux_destroy(struct cdns_mhdp_device *mhdp) +{ + drm_dp_aux_unregister(&mhdp->dp.aux); + return 0; +} + +static void dp_pixel_clk_reset(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + /* reset pixel clk */ + val = cdns_mhdp_reg_read(mhdp, SOURCE_HDTX_CAR); + cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, val & 0xFD); + cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, val); +} + +static void cdns_dp_mode_set(struct cdns_mhdp_device *mhdp) +{ + u32 lane_mapping = mhdp->lane_mapping; + int ret; + + cdns_mhdp_plat_call(mhdp, pclk_rate); + + /* delay for DP FW stable after pixel clock relock */ + msleep(50); + + dp_pixel_clk_reset(mhdp); + + /* Get DP Caps */ + ret = drm_dp_dpcd_read(&mhdp->dp.aux, DP_DPCD_REV, mhdp->dp.dpcd, + DP_RECEIVER_CAP_SIZE); + if (ret < 0) { + DRM_ERROR("Failed to get caps %d\n", ret); + return; + } + + mhdp->dp.rate = drm_dp_max_link_rate(mhdp->dp.dpcd); + mhdp->dp.num_lanes = drm_dp_max_lane_count(mhdp->dp.dpcd); + mhdp->dp.link_training_type = DP_TX_FULL_LINK_TRAINING; + + /* check the max link rate */ + if (mhdp->dp.rate > CDNS_DP_MAX_LINK_RATE) + mhdp->dp.rate = CDNS_DP_MAX_LINK_RATE; + + /* Initialize link rate/num_lanes as panel max link rate/max_num_lanes */ + cdns_mhdp_plat_call(mhdp, phy_set); + + /* Video off */ + ret = cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_IDLE); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to valid video %d\n", ret); + return; + } + + /* Line swaping */ + cdns_mhdp_reg_write(mhdp, LANES_CONFIG, 0x00400000 | lane_mapping); + + /* Set DP host capability */ + ret = cdns_mhdp_set_host_cap(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to set host cap %d\n", ret); + return; + } + + ret = cdns_mhdp_config_video(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to config video %d\n", ret); + return; + } + + return; +} + +void cdns_dp_handle_hpd_irq(struct cdns_mhdp_device *mhdp) +{ + u8 status[6]; + + mutex_lock(&mhdp->lock); + cdns_mhdp_dpcd_read(mhdp, 0x200, &status[0], 6); + DRM_DEBUG_DRIVER("DPCD HPD IRQ STATUS: %08x\n", status[1]); + cdns_mhdp_dpcd_write(mhdp, 0x201, status[1]); + mutex_unlock(&mhdp->lock); +} + +/* ----------------------------------------------------------------------------- + * dp TX Setup + */ +static enum drm_connector_status +cdns_dp_connector_detect(struct drm_connector *connector, bool force) +{ + struct cdns_mhdp_device *mhdp = container_of(connector, + struct cdns_mhdp_device, connector.base); + u8 hpd = 0xf; + mutex_lock(&mhdp->lock); + hpd = cdns_mhdp_read_hpd(mhdp); + mutex_unlock(&mhdp->lock); + DRM_DEBUG_DRIVER("%s hpd = %d\n", __func__, hpd); + + if (mhdp->force_disconnected_sts && (hpd == 1)) { + DRM_DEBUG_DRIVER("Returning disconnect status until ready\n"); + return connector_status_disconnected; + } + if (hpd == 0) + /* Cable Disconnedted */ + return connector_status_disconnected; + else if (hpd == 3) { + /* Cable Connected and seen IRQ*/ + DRM_DEBUG_DRIVER("Warning! Missed HPD IRQ event seen\n"); + return connector_status_connected; + } else if (hpd == 1) + /* Cable Connected */ + return connector_status_connected; + + /* Cable status unknown */ + DRM_DEBUG_DRIVER("Unknown cable status, hdp=%u\n", hpd); + return connector_status_unknown; +} + +static int cdns_dp_connector_get_modes(struct drm_connector *connector) +{ + struct cdns_mhdp_device *mhdp = container_of(connector, + struct cdns_mhdp_device, connector.base); + int num_modes = 0; + struct edid *edid; + + edid = drm_do_get_edid(&mhdp->connector.base, + cdns_mhdp_get_edid_block, mhdp); + if (edid) { + DRM_DEBUG_DRIVER("%x,%x,%x,%x,%x,%x,%x,%x\n", + edid->header[0], edid->header[1], + edid->header[2], edid->header[3], + edid->header[4], edid->header[5], + edid->header[6], edid->header[7]); + drm_connector_update_edid_property(connector, edid); + num_modes = drm_add_edid_modes(connector, edid); + kfree(edid); + } + + if (num_modes == 0) + DRM_ERROR("Invalid edid\n"); + return num_modes; +} + +static bool blob_equal(const struct drm_property_blob *a, + const struct drm_property_blob *b) +{ + if (a && b) + return a->length == b->length && + !memcmp(a->data, b->data, a->length); + + return !a == !b; +} + +static int cdns_dp_connector_atomic_check(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + struct drm_connector_state *new_con_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_connector_state *old_con_state = + drm_atomic_get_old_connector_state(state, connector); + struct drm_crtc *crtc = new_con_state->crtc; + struct drm_crtc_state *new_crtc_state; + + cdns_hdcp_atomic_check(connector, old_con_state, new_con_state); + if (!new_con_state->crtc) + return 0; + + new_crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(new_crtc_state)) + return PTR_ERR(new_crtc_state); + + if (!blob_equal(new_con_state->hdr_output_metadata, + old_con_state->hdr_output_metadata) || + new_con_state->colorspace != old_con_state->colorspace) { + + new_crtc_state->mode_changed = + !new_con_state->hdr_output_metadata || + !old_con_state->hdr_output_metadata || + new_con_state->colorspace != old_con_state->colorspace; + } + + /* + * These properties are handled by fastset, and might not end up in a + * modeset. + */ + if (new_con_state->picture_aspect_ratio != + old_con_state->picture_aspect_ratio || + new_con_state->content_type != old_con_state->content_type || + new_con_state->scaling_mode != old_con_state->scaling_mode) + new_crtc_state->mode_changed = true; + return 0; +} + +static const struct drm_connector_funcs cdns_dp_connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = cdns_dp_connector_detect, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_connector_helper_funcs cdns_dp_connector_helper_funcs = { + .get_modes = cdns_dp_connector_get_modes, + .atomic_check = cdns_dp_connector_atomic_check, +}; + +static int cdns_dp_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_encoder *encoder = bridge->encoder; + struct drm_connector *connector = &mhdp->connector.base; + int ret; + + connector->interlace_allowed = 1; + + if (mhdp->is_hpd) + connector->polled = DRM_CONNECTOR_POLL_HPD; + else + connector->polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; + + drm_connector_helper_add(connector, &cdns_dp_connector_helper_funcs); + + ret = drm_connector_init(bridge->dev, connector, &cdns_dp_connector_funcs, + DRM_MODE_CONNECTOR_DisplayPort); + if (ret < 0) { + DRM_ERROR("Failed to initialize connector\n"); + return ret; + } + + drm_connector_attach_encoder(connector, encoder); + + drm_connector_attach_content_protection_property(connector, true); + + return 0; +} + +static enum drm_mode_status +cdns_dp_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + enum drm_mode_status mode_status = MODE_OK; + + /* We don't support double-clocked modes */ + if (mode->flags & DRM_MODE_FLAG_DBLCLK || + mode->flags & DRM_MODE_FLAG_INTERLACE) + return MODE_BAD; + + /* MAX support pixel clock rate 594MHz */ + if (mode->clock > 594000) + return MODE_CLOCK_HIGH; + + /* 5120 x 2160 is the maximum supported resulution */ + if (mode->hdisplay > 5120) + return MODE_BAD_HVALUE; + + if (mode->vdisplay > 2160) + return MODE_BAD_VVALUE; + + return mode_status; +} + +static void cdns_dp_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *orig_mode, + const struct drm_display_mode *mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_display_info *display_info = &mhdp->connector.base.display_info; + struct video_info *video = &mhdp->video_info; + + switch (display_info->bpc) { + case 10: + video->color_depth = 10; + break; + case 6: + video->color_depth = 6; + break; + default: + video->color_depth = 8; + break; + } + + video->color_fmt = PXL_RGB; + video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); + video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); + + DRM_DEBUG_DRIVER("Mode: %dx%dp%d\n", mode->hdisplay, mode->vdisplay, + mode->clock); + memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode)); + + mutex_lock(&mhdp->lock); + cdns_dp_mode_set(mhdp); + mutex_unlock(&mhdp->lock); + + /* reset force mode set flag */ + mhdp->force_mode_set = false; +} + +static void cdn_dp_bridge_enable(struct drm_bridge *bridge) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_connector_state *conn_state = mhdp->connector.base.state; + int ret; + + mutex_lock(&mhdp->lock); + /* Link trainning */ + ret = cdns_mhdp_train_link(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed link train %d\n", ret); + mutex_unlock(&mhdp->lock); + return; + } + mutex_unlock(&mhdp->lock); + + ret = cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_VALID); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to valid video %d\n", ret); + return; + } + + if (conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) + cdns_hdcp_enable(mhdp); + +} + +static void cdn_dp_bridge_disable(struct drm_bridge *bridge) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + + cdns_hdcp_disable(mhdp); + + cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_IDLE); +} + +static const struct drm_bridge_funcs cdns_dp_bridge_funcs = { + .attach = cdns_dp_bridge_attach, + .enable = cdn_dp_bridge_enable, + .disable = cdn_dp_bridge_disable, + .mode_set = cdns_dp_bridge_mode_set, + .mode_valid = cdns_dp_bridge_mode_valid, +}; + +static void hotplug_work_func(struct work_struct *work) +{ + struct cdns_mhdp_device *mhdp = container_of(work, + struct cdns_mhdp_device, + hotplug_work.work); + struct drm_connector *connector = &mhdp->connector.base; + enum drm_connector_status connector_sts; + int loop_cnt, retry; + + DRM_DEBUG_DRIVER("Starting %s\n", __func__); + + if (connector->status == connector_status_connected) { + /* Need to check if we had an IRQ event */ + u8 hpd = 0xf; + + mutex_lock(&mhdp->lock); + hpd = cdns_mhdp_read_hpd(mhdp); + mutex_unlock(&mhdp->lock); + DRM_DEBUG_DRIVER("cdns_mhdp_read_hpd = %d\n", hpd); + if (hpd == 3) { + /* Cable Connected and seen IRQ*/ + DRM_DEBUG_DRIVER("HPD IRQ event seen\n"); + cdns_dp_handle_hpd_irq(mhdp); + connector_sts = connector_status_connected; + } else if (hpd == 1) + connector_sts = connector_status_connected; + else if (hpd == 0) + connector_sts = connector_status_disconnected; + else + connector_sts = connector_status_unknown; + + /* if was connected then there may have been unplug event, + * either wait 900us then call cdns_dp_connector_detect and if + * still connected then just ignore and finish or poll a + * certain number of times. Otherwise set status to unconnected + * and call the hotplug_event function. + */ + for (loop_cnt = 0; loop_cnt < CDNS_DP_HPD_POLL_DWN_LOOP; + loop_cnt++) { + udelay(CDNS_DP_HPD_POLL_DWN_DLY_US); + if (loop_cnt > 0) + connector_sts = + cdns_dp_connector_detect(connector, false); + if (connector_sts != connector_status_connected) { + DRM_DEBUG_DRIVER("HDMI/DP Cable Plug Out\n"); + break; + } + } + if (connector_sts == connector_status_connected) { + DRM_DEBUG_DRIVER("Finished %s - early\n", __func__); + return; + } + /* Disable HDCP when cable plugout, + * set content_protection to DESIRED, recovery HDCP state after cable plugin + */ + if (connector->state->content_protection + != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { + connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; + mhdp->hdcp.state = HDCP_STATE_DISABLING; + } + DRM_DEBUG_DRIVER("Calling drm_kms_helper_hotplug_event\n"); + /* Note that before we call the helper functions we need + * to force the cdns_dp_connector_detect function from + * returning a connected status since the DRM functions + * still end up calling that in a roundabout way when we + * signal a status change. We need to do this to ensure + * that a shutdown proper completes and don't end up in + * a strange state. + */ + mhdp->force_disconnected_sts = true; + connector->status = connector_sts; + drm_kms_helper_hotplug_event(connector->dev); + /* There was a disconnection so give some time to allow + * things to clean up + */ + DRM_DEBUG_DRIVER("Start sleep\n"); + msleep(75); + DRM_DEBUG_DRIVER("End sleep\n"); + mhdp->force_disconnected_sts = false; + } else { + /* Disconnected or unknown status */ + /* if was disconnected possibly a connect event, call + * cdns_dp_connector_detect multiple times to validate before + * updating to connected status and calling the hotplug event + * function. This is needed since the HW/FW can take some time + * to validate. + */ + for (loop_cnt = 0; loop_cnt < CDNS_DP_HPD_POLL_UP_LOOP; + loop_cnt++) { + msleep(CDNS_DP_HPD_POLL_UP_DLY_US / 1000); + connector_sts = + cdns_dp_connector_detect(connector, false); + if (connector_sts == connector_status_connected) { + DRM_DEBUG_DRIVER("HDMI/DP Cable Plug In\n"); + /* Recovery HDCP state */ + if (connector->state->content_protection + != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) + mhdp->hdcp.state = HDCP_STATE_ENABLING; + break; + } + } + if (connector_sts == connector_status_connected) { + DRM_DEBUG_DRIVER("Calling drm_kms_helper_hotplug_event\n"); + connector->status = connector_sts; + drm_kms_helper_hotplug_event(connector->dev); + } + } + + /* check connection status one more time in case there had been a short + * disconnect that might have caused re-connect to be missed, if so + * schedule again. + */ + retry = 1; + do { + connector_sts = cdns_dp_connector_detect(connector, false); + if (connector_sts != connector->status) { + DRM_DEBUG_DRIVER("Re-queuing work_func due to possible change\n"); + queue_delayed_work(system_wq, &mhdp->hotplug_work, + usecs_to_jiffies(50)); + break; + } + retry--; + } while (retry > 0); + DRM_DEBUG_DRIVER("Finished %s\n", __func__); +} + +static irqreturn_t cdns_dp_irq_thread(int irq, void *data) +{ + struct cdns_mhdp_device *mhdp = data; + + disable_irq_nosync(irq); + + /* Need to handle the enable HERE */ + if (irq == mhdp->irq[IRQ_IN]) { + DRM_DEBUG_DRIVER("HDMI/DP IRQ IN\n"); + enable_irq(mhdp->irq[IRQ_OUT]); + } else if (irq == mhdp->irq[IRQ_OUT]) { + DRM_DEBUG_DRIVER("HDMI/DP IRQ OUT\n"); + enable_irq(mhdp->irq[IRQ_IN]); + } + + /* Queue job as long as not already in queue */ + queue_delayed_work(system_wq, &mhdp->hotplug_work, + usecs_to_jiffies(5)); + + return IRQ_HANDLED; +} + +static void cdns_dp_parse_dt(struct cdns_mhdp_device *mhdp) +{ + struct device_node *of_node = mhdp->dev->of_node; + int ret; + + ret = of_property_read_u32(of_node, "lane-mapping", + &mhdp->lane_mapping); + if (ret) { + mhdp->lane_mapping = 0xc6; + dev_warn(mhdp->dev, "Failed to get lane_mapping - using default 0xc6\n"); + } + dev_info(mhdp->dev, "lane-mapping 0x%02x\n", mhdp->lane_mapping); + + ret = of_property_read_u32(of_node, "i2c-over-aux-retries", + &mhdp->i2c_over_aux_retries); + if (ret) { + mhdp->i2c_over_aux_retries = 5; + dev_warn(mhdp->dev, + "Failed to get i2c-over-aux-retries - using default 5\n"); + } + + dev_info(mhdp->dev, "i2c-over-aux-retries 0x%02x\n", + mhdp->i2c_over_aux_retries); +} + +static int __cdns_dp_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + struct device *dev = &pdev->dev; + struct resource *iores = NULL; + int ret; + + mutex_init(&mhdp->lock); + mutex_init(&mhdp->api_lock); + mutex_init(&mhdp->iolock); + + INIT_DELAYED_WORK(&mhdp->hotplug_work, hotplug_work_func); + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (iores) { + mhdp->regs_base = devm_ioremap(dev, iores->start, + resource_size(iores)); + if (IS_ERR(mhdp->regs_base)) + return -ENOMEM; + } + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (iores) { + mhdp->regs_sec = devm_ioremap(dev, iores->start, + resource_size(iores)); + if (IS_ERR(mhdp->regs_sec)) + return -ENOMEM; + } + + mhdp->is_hpd = true; + mhdp->is_dp = true; + mhdp->is_ls1028a = false; + + mhdp->irq[IRQ_IN] = platform_get_irq_byname(pdev, "plug_in"); + if (mhdp->irq[IRQ_IN] < 0) { + mhdp->is_hpd = false; + dev_info(dev, "No plug_in irq number\n"); + } + + mhdp->irq[IRQ_OUT] = platform_get_irq_byname(pdev, "plug_out"); + if (mhdp->irq[IRQ_OUT] < 0) { + mhdp->is_hpd = false; + dev_info(dev, "No plug_out irq number\n"); + } + + cdns_dp_parse_dt(mhdp); + + cnds_hdcp_create_device_files(mhdp); + + if (of_device_is_compatible(dev->of_node, "cdn,ls1028a-dp")) + mhdp->is_ls1028a = true; + + cdns_mhdp_plat_call(mhdp, power_on); + + cdns_mhdp_plat_call(mhdp, firmware_init); + + /* DP FW alive check */ + ret = cdns_mhdp_check_alive(mhdp); + if (ret == false) { + DRM_ERROR("NO dp FW running\n"); + return -ENXIO; + } + + ret = cdns_hdcp_init(mhdp, pdev->dev.of_node); + if (ret < 0) + DRM_WARN("Failed to initialize HDCP\n"); + + /* DP PHY init before AUX init */ + cdns_mhdp_plat_call(mhdp, phy_set); + + /* Enable Hotplug Detect IRQ thread */ + if (mhdp->is_hpd) { + irq_set_status_flags(mhdp->irq[IRQ_IN], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_IN], + NULL, cdns_dp_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + + if (ret) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_IN]); + return -EINVAL; + } + + irq_set_status_flags(mhdp->irq[IRQ_OUT], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_OUT], + NULL, cdns_dp_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + + if (ret) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_OUT]); + return -EINVAL; + } + + // Call to clear any latched values first... + cdns_mhdp_read_hpd(mhdp); + if (cdns_mhdp_read_hpd(mhdp)) + enable_irq(mhdp->irq[IRQ_OUT]); + else + enable_irq(mhdp->irq[IRQ_IN]); + } + + mhdp->bridge.base.driver_private = mhdp; + mhdp->bridge.base.funcs = &cdns_dp_bridge_funcs; +#ifdef CONFIG_OF + mhdp->bridge.base.of_node = dev->of_node; +#endif + + dev_set_drvdata(dev, mhdp); + + /* register audio driver */ + cdns_mhdp_register_audio_driver(dev); + + dp_aux_init(mhdp, dev); + + return 0; +} + +static void __cdns_dp_remove(struct cdns_mhdp_device *mhdp) +{ + dp_aux_destroy(mhdp); + cdns_mhdp_unregister_audio_driver(mhdp->dev); + cnds_hdcp_remove_device_files(mhdp); + + cdns_mhdp_plat_call(mhdp, power_off); +} + +/* ----------------------------------------------------------------------------- + * Probe/remove API, used from platforms based on the DRM bridge API. + */ +int cdns_dp_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_dp_probe(pdev, mhdp); + if (ret) + return ret; + + drm_bridge_add(&mhdp->bridge.base); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_dp_probe); + +void cdns_dp_remove(struct platform_device *pdev) +{ + struct cdns_mhdp_device *mhdp = platform_get_drvdata(pdev); + + drm_bridge_remove(&mhdp->bridge.base); + + __cdns_dp_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_dp_remove); + +/* ----------------------------------------------------------------------------- + * Bind/unbind API, used from platforms based on the component framework. + */ +int cdns_dp_bind(struct platform_device *pdev, struct drm_encoder *encoder, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_dp_probe(pdev, mhdp); + if (ret < 0) + return ret; + + ret = drm_bridge_attach(encoder, &mhdp->bridge.base, NULL, 0); + if (ret) { + cdns_dp_remove(pdev); + DRM_ERROR("Failed to initialize bridge with drm\n"); + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_dp_bind); + +void cdns_dp_unbind(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + __cdns_dp_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_dp_unbind); + +MODULE_AUTHOR("Sandor Yu "); +MODULE_DESCRIPTION("Cadence Display Port transmitter driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:cdn-dp"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.c linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.c --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.c 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,1331 @@ +/* + * Cadence HDMI/DP HDCP driver + * + * Copyright 2021 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include +#include +#include +#include + +#include "cdns-mhdp-hdcp.h" + +/* Default will be to use KM unless it has been explicitly */ +#ifndef HDCP_USE_KMKEY + #define HDCP_USE_KMKEY 1 +#endif + +#define CDNS_HDCP_ACTIVATE (0x1 << 2) + +#define IMX_FW_TIMEOUT_MS (64 * 1000) +#define IMX_HDCP_PAIRING_FIRMWARE "imx/hdcp-pairing.bin" + +#define GENERAL_BUS_SETTINGS_DPCD_BUS_BIT 0 +#define GENERAL_BUS_SETTINGS_DPCD_BUS_LOCK_BIT 1 +#define GENERAL_BUS_SETTINGS_HDCP_BUS_BIT 2 +#define GENERAL_BUS_SETTINGS_HDCP_BUS_LOCK_BIT 3 +#define GENERAL_BUS_SETTINGS_CAPB_OWNER_BIT 4 +#define GENERAL_BUS_SETTINGS_CAPB_OWNER_LOCK_BIT 5 + +#define GENERAL_BUS_SETTINGS_RESP_DPCD_BUS_BIT 0 +#define GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT 1 +#define GENERAL_BUS_SETTINGS_RESP_CAPB_OWNER_BIT 2 + +/* HDCP TX ports working mode (HDCP 2.2 or 1.4) */ +enum { + HDCP_TX_2, /* lock only with HDCP2 */ + HDCP_TX_1, /* lock only with HDCP1 */ + HDCP_TX_BOTH, /* lock on HDCP2 or 1 depend on other side */ +}; + +/* HDCP TX ports stream type (relevant if receiver is repeater) */ +enum { + HDCP_CONTENT_TYPE_0, /* May be transmitted by + The HDCP Repeater to all HDCP Devices. */ + HDCP_CONTENT_TYPE_1, /* Must not be transmitted by the HDCP Repeater to + HDCP 1.x-compliant Devices and HDCP 2.0-compliant Repeaters */ +}; + +/* different error types for HDCP_TX_STATUS_CHANGE */ +enum { + HDCP_TRAN_ERR_NO_ERROR, + HDCP_TRAN_ERR_HPD_IS_DOWN, + HDCP_TRAN_ERR_SRM_FAILURE, + HDCP_TRAN_ERR_SIGNATURE_VERIFICATION, + HDCP_TRAN_ERR_H_TAG_DIFF_H, + HDCP_TRAN_ERR_V_TAG_DIFF_V, + HDCP_TRAN_ERR_LOCALITY_CHECK, + HDCP_TRAN_ERR_DDC, + HDCP_TRAN_ERR_REAUTH_REQ, + HDCP_TRAN_ERR_TOPOLOGY, + HDCP_TRAN_ERR_HDCP_RSVD1, + HDCP_TRAN_ERR_HDMI_CAPABILITY, + HDCP_TRAN_ERR_RI, + HDCP_TRAN_ERR_WATCHDOG_EXPIRED, +}; + +static char const *g_last_error[16] = { + "No Error", + "HPD is down", + "SRM failure", + "Signature verification error", + "h tag != h", + "V tag diff v", + "Locality check", + "DDC error", + "REAUTH_REQ", + "Topology error", + "Verify receiver ID list failed", + "HDCP_RSVD1 was not 0,0,0", + "HDMI capability or mode", + "RI result was different than expected", + "WatchDog expired", + "Repeater integrity failed" +}; + +#define HDCP_MAX_RECEIVERS 32 +#define HDCP_RECEIVER_ID_SIZE_BYTES 5 +#define HPD_EVENT 1 +#define HDCP_STATUS_SIZE 0x5 +#define HDCP_PORT_STS_AUTH 0x1 +#define HDCP_PORT_STS_REPEATER 0x2 +#define HDCP_PORT_STS_TYPE_MASK 0xc +#define HDCP_PORT_STS_TYPE_SHIFT 0x2 +#define HDCP_PORT_STS_AUTH_STREAM_ID_SHIFT 0x4 +#define HDCP_PORT_STS_AUTH_STREAM_ID_MASK 0x10 +#define HDCP_PORT_STS_LAST_ERR_SHIFT 0x5 +#define HDCP_PORT_STS_LAST_ERR_MASK (0x0F << 5) +#define GET_HDCP_PORT_STS_LAST_ERR(__sts__) \ + (((__sts__) & HDCP_PORT_STS_LAST_ERR_MASK) >> \ + HDCP_PORT_STS_LAST_ERR_SHIFT) +#define HDCP_PORT_STS_1_1_FEATURES 0x200 + +#define HDCP_CONFIG_NONE ((u8) 0) +#define HDCP_CONFIG_1_4 ((u8) 1) /* use HDCP 1.4 only */ +#define HDCP_CONFIG_2_2 ((u8) 2) /* use HDCP 2.2 only */ + +/* Default timeout to use for wait4event in milliseconds */ +#define HDCP_EVENT_TO_DEF 800 +/* Timeout value to use for repeater receiver ID check, spec says 3s */ +#define HDCP_EVENT_TO_RPT 3500 + +static int cdns_hdcp_check_link(struct cdns_mhdp_device *mhdp); + +static void print_port_status(u16 sts) +{ + char const *rx_type[4] = { "Unknown", "HDCP 1", "HDCP 2", "Unknown" }; + + DRM_DEBUG_KMS("INFO: HDCP Port Status: 0x%04x\n", sts); + DRM_DEBUG_KMS(" Authenticated: %d\n", sts & HDCP_PORT_STS_AUTH); + DRM_DEBUG_KMS(" Receiver is repeater: %d\n", sts & HDCP_PORT_STS_REPEATER); + DRM_DEBUG_KMS(" RX Type: %s\n", + rx_type[(sts & HDCP_PORT_STS_TYPE_MASK) >> HDCP_PORT_STS_TYPE_SHIFT]); + DRM_DEBUG_KMS(" AuthStreamId: %d\n", sts & HDCP_PORT_STS_AUTH_STREAM_ID_MASK); + DRM_DEBUG_KMS(" Last Error: %s\n", + g_last_error[(sts & HDCP_PORT_STS_LAST_ERR_MASK) >> HDCP_PORT_STS_LAST_ERR_SHIFT]); + DRM_DEBUG_KMS(" Enable 1.1 Features: %d\n", sts & HDCP_PORT_STS_1_1_FEATURES); +} + +static void print_events(u8 events) +{ + if (events & HDMI_TX_HPD_EVENT) + DRM_INFO("INFO: HDMI_TX_HPD_EVENT\n"); + if (events & HDCPTX_STATUS_EVENT) + DRM_INFO("INFO: HDCPTX_STATUS_EVENT\n"); + if (events & HDCPTX_IS_KM_STORED_EVENT) + DRM_INFO("INFO: HDCPTX_IS_KM_STORED_EVENT\n"); + if (events & HDCPTX_STORE_KM_EVENT) + DRM_INFO("INFO: HDCPTX_STORE_KM_EVENT\n"); + if (events & HDCPTX_IS_RECEIVER_ID_VALID_EVENT) + DRM_INFO("INFO: HDCPTX_IS_RECEIVER_ID_VALID_EVENT\n"); +} + +static u8 wait4event(struct cdns_mhdp_device *mhdp, u8 *events, + u32 event_to_wait, u32 timeout_ms) +{ + u8 reg_events; + u8 returned_events; + u8 event_mask = event_to_wait | HDCPTX_STATUS_EVENT; + unsigned timeout; + + timeout = timeout_ms; + do { + if (timeout == 0) + goto timeout_err; + timeout--; + udelay(1000); + reg_events = cdns_mhdp_get_event(mhdp); + *events |= reg_events; + } while (((event_mask & *events) == 0) && (event_to_wait > HDMI_TX_HPD_EVENT)); + + returned_events = *events & event_mask; + if (*events != returned_events) { + u32 unexpected_events = ~event_mask & *events; + + DRM_INFO("INFO: %s() all 0x%08x expected 0x%08x unexpected 0x%08x", + __func__, *events, returned_events, unexpected_events); + DRM_INFO("INFO: %s() All events:\n", __func__); + print_events(*events); + + DRM_INFO("INFO: %s() expected events:\n", __func__); + print_events(returned_events); + + DRM_INFO("INFO: %s() unexpected events:\n", __func__); + print_events(unexpected_events); + } else + print_events(*events); + + *events &= ~event_mask; + + return returned_events; + +timeout_err: + DRM_INFO("INFO: %s() Timed out with events:\n", __func__); + print_events(event_to_wait); + return 0; +} + +static u16 cdns_hdcp_get_status(struct cdns_mhdp_device *mhdp) +{ + u8 hdcp_status[HDCP_STATUS_SIZE]; + u16 hdcp_port_status; + + cdns_mhdp_hdcp_tx_status_req(mhdp, hdcp_status, HDCP_STATUS_SIZE); + hdcp_port_status = (hdcp_status[0] << 8) | hdcp_status[1]; + + return hdcp_port_status; +} + +static inline u8 check_event(u8 events, u8 tested) +{ + if ((events & tested) == 0) + return 0; + return 1; +} + +/* Prints status. Returns error code (0 = no error) */ +static u8 cdns_hdcp_handle_status(u16 status) +{ + print_port_status(status); + if (status & HDCP_PORT_STS_LAST_ERR_MASK) + DRM_ERROR("ERROR: HDCP error was set to %s\n", + g_last_error[((status & HDCP_PORT_STS_LAST_ERR_MASK) + >> HDCP_PORT_STS_LAST_ERR_SHIFT)]); + return GET_HDCP_PORT_STS_LAST_ERR(status); +} + +static int cdns_hdcp_set_config(struct cdns_mhdp_device *mhdp, u8 hdcp_config) +{ + u8 bus_config, retEvents; + u16 hdcp_port_status; + int ret; + + /* Clearing out existing events */ + wait4event(mhdp, &mhdp->hdcp.events, HDMI_TX_HPD_EVENT, HDCP_EVENT_TO_DEF); + mhdp->hdcp.events = 0; + + if (!strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { + DRM_DEBUG_KMS("INFO: Switching HDCP Commands to SAPB.\n"); + bus_config = (1 << GENERAL_BUS_SETTINGS_HDCP_BUS_BIT); + ret = cdns_mhdp_apb_conf(mhdp, bus_config); + if (ret) { + DRM_ERROR("Failed to set APB configuration.\n"); + if (ret & (1 << GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT))/* 1 - locked */ + DRM_ERROR("Failed to switch HDCP to SAPB Mailbox\n"); + return -1; + } + DRM_DEBUG_KMS("INFO: HDCP switched to SAPB\n"); + } + + /* HDCP 2.2(and/or 1.4) | activate | km-key | 0 */ + hdcp_config |= CDNS_HDCP_ACTIVATE | (HDCP_USE_KMKEY << 4) | (HDCP_CONTENT_TYPE_0 << 3); + + DRM_DEBUG_KMS("INFO: Enabling HDCP...\n"); + ret = cdns_mhdp_hdcp_tx_config(mhdp, hdcp_config); + if (ret < 0) + DRM_DEBUG_KMS("cdns_mhdp_hdcp_tx_config failed\n"); + + /* Wait until HDCP_TX_STATUS EVENT appears */ + DRM_DEBUG_KMS("INFO: wait4event -> HDCPTX_STATUS_EVENT\n"); + retEvents = wait4event(mhdp, &mhdp->hdcp.events, HDCPTX_STATUS_EVENT, HDCP_EVENT_TO_DEF); + + /* Set TX STATUS REQUEST */ + DRM_DEBUG_KMS("INFO: Getting port status\n"); + hdcp_port_status = cdns_hdcp_get_status(mhdp); + if (cdns_hdcp_handle_status(hdcp_port_status) != 0) + return -1; + + return 0; +} + +static int cdns_hdcp_auth_check(struct cdns_mhdp_device *mhdp) +{ + u16 hdcp_port_status; + int ret; + + DRM_DEBUG_KMS("INFO: wait4event -> HDCPTX_STATUS_EVENT\n"); + mhdp->hdcp.events = wait4event(mhdp, &mhdp->hdcp.events, HDCPTX_STATUS_EVENT, HDCP_EVENT_TO_DEF+HDCP_EVENT_TO_DEF); + if (mhdp->hdcp.events == 0) + return -1; + + DRM_DEBUG_KMS("HDCP: HDCPTX_STATUS_EVENT\n"); + hdcp_port_status = cdns_hdcp_get_status(mhdp); + ret = cdns_hdcp_handle_status(hdcp_port_status); + if (ret != 0) { + if (ret == HDCP_TRAN_ERR_REAUTH_REQ) { + DRM_ERROR("HDCP_TRAN_ERR_REAUTH_REQ-->one more try!\n"); + return 1; + } else + return -1; + } + + if (hdcp_port_status & HDCP_PORT_STS_AUTH) { + DRM_INFO("Authentication completed successfully!\n"); + /* Dump hdmi and phy register */ + mhdp->hdcp.state = HDCP_STATE_AUTHENTICATED; + mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_ENABLED; + schedule_work(&mhdp->hdcp.prop_work); + return 0; + } + + DRM_WARN("Authentication failed\n"); + mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; + return -1; +} + +inline void cdns_hdcp_swap_id(u8 *in, u8 *out) +{ + int i; + + for (i = 0; i < HDCP_RECEIVER_ID_SIZE_BYTES; i++) + out[HDCP_RECEIVER_ID_SIZE_BYTES - (i + 1)] = in[i]; +} + +inline void cdns_hdcp_swap_list(u8 *list_in, u8 *list_out, int num_ids) +{ + int i; + + for (i = 0; i < num_ids; i++) + cdns_hdcp_swap_id(&list_in[i * HDCP_RECEIVER_ID_SIZE_BYTES], + &list_out[i * HDCP_RECEIVER_ID_SIZE_BYTES]); +} + +static int cdns_hdcp_check_receviers(struct cdns_mhdp_device *mhdp) +{ + u8 ret_events; + u8 hdcp_num_rec, i; + u8 hdcp_rec_id[HDCP_MAX_RECEIVERS][HDCP_RECEIVER_ID_SIZE_BYTES]; + u8 hdcp_rec_id_temp[HDCP_MAX_RECEIVERS][HDCP_RECEIVER_ID_SIZE_BYTES]; + u16 hdcp_port_status = 0; + int ret; + + DRM_INFO("INFO: Waiting for Receiver ID valid event\n"); + ret_events = 0; + do { + u8 events = 0; + u8 hdcp_last_error = 0; + events = check_event(ret_events, + HDCPTX_IS_RECEIVER_ID_VALID_EVENT); + DRM_DEBUG_KMS("INFO: Waiting HDCPTX_IS_RECEIVER_ID_VALID_EVENT\n"); + ret_events = wait4event(mhdp, &mhdp->hdcp.events, + HDCPTX_IS_RECEIVER_ID_VALID_EVENT, + (mhdp->hdcp.sink_is_repeater ? + HDCP_EVENT_TO_RPT : HDCP_EVENT_TO_DEF)); + if (ret_events == 0) { + /* time out occurred, return error */ + DRM_ERROR("HDCP error did not get receiver IDs\n"); + return -1; + } + if (check_event(ret_events, HDCPTX_STATUS_EVENT) != 0) { + /* There was a status update, could be due to HPD + going down or some other error, check if an error + was set, if so exit. + */ + hdcp_port_status = cdns_hdcp_get_status(mhdp); + hdcp_last_error = GET_HDCP_PORT_STS_LAST_ERR(hdcp_port_status); + if (cdns_hdcp_handle_status(hdcp_port_status)) { + DRM_ERROR("HDCP error no: %u\n", hdcp_last_error); + return -1; + } else { + /* No error logged, keep going. + * If this somehow happened at same time, then need to + * put the HDCPTX_STATUS_EVENT back into the global + * events pool and checked later. */ + mhdp->hdcp.events |= HDCPTX_STATUS_EVENT; + + /* Special condition when connected to HDCP 1.4 repeater + * with no downstream devices attached, then will not + * get receiver ID list but instead will reach + * authenticated state. */ + if ((mhdp->hdcp.hdcp_version == HDCP_TX_1) && (mhdp->hdcp.sink_is_repeater == 1) && + ((hdcp_port_status & HDCP_PORT_STS_AUTH) == HDCP_PORT_STS_AUTH)) { + DRM_INFO("Connected to HDCP 1.4 repeater with no downstream devices!\n"); + return 0; + } + + msleep(20); + } + } + } while (check_event(ret_events, + HDCPTX_IS_RECEIVER_ID_VALID_EVENT) == 0); + + DRM_INFO("INFO: Requesting Receivers ID's\n"); + + hdcp_num_rec = 0; + memset(&hdcp_rec_id, 0, sizeof(hdcp_rec_id)); + + ret = cdns_mhdp_hdcp_tx_is_receiver_id_valid(mhdp, (u8 *)hdcp_rec_id, &hdcp_num_rec); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to hdcp tx receiver ID.\n"); + return -1; + } + + if (hdcp_num_rec == 0) { + DRM_DEBUG_KMS("WARN: Failed to get receiver list\n"); + /* Unknown problem, return error */ + return -1; + } + + DRM_INFO("INFO: Number of Receivers: %d\n", hdcp_num_rec); + + for (i = 0; i < hdcp_num_rec; ++i) { + DRM_INFO("\tReceiver ID%2d: %.2X%.2X%.2X%.2X%.2X\n", + i, + hdcp_rec_id[i][0], + hdcp_rec_id[i][1], + hdcp_rec_id[i][2], + hdcp_rec_id[i][3], + hdcp_rec_id[i][4] + ); + } + + /* swap ids byte order */ + cdns_hdcp_swap_list(&hdcp_rec_id[0][0], + &hdcp_rec_id_temp[0][0], hdcp_num_rec); + + /* Check Receiver ID's against revocation list in SRM */ + if (drm_hdcp_check_ksvs_revoked(mhdp->drm_dev, (u8 *)hdcp_rec_id_temp, hdcp_num_rec)) { + mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; + DRM_ERROR("INFO: Receiver check fails\n"); + return -1; + } + + ret = cdns_mhdp_hdcp_tx_respond_receiver_id_valid(mhdp, 1); + DRM_INFO("INFO: Responding with Receiver ID's OK!, ret=%d\n", ret); + return ret; +} + +#ifdef STORE_PAIRING +static int cdns_hdcp_get_stored_pairing(struct cdns_mhdp_device *mhdp) +{ + int ret = 0; + unsigned long timeout = jiffies + msecs_to_jiffies(IMX_FW_TIMEOUT_MS); + unsigned long sleep = 1000; + const struct firmware *fw; + + DRM_DEBUG_KMS("%s()\n", __func__); + + while (time_before(jiffies, timeout)) { + ret = request_firmware(&fw, cdns_hdcp_PAIRING_FIRMWARE, mhdp->dev); + if (ret == -ENOENT) { + msleep(sleep); + sleep *= 2; + continue; + } else if (ret) { + DRM_DEV_INFO(mhdp->dev, "HDCP pairing data not found\n"); + goto out; + } + + mhdp->hdcp.num_paired = fw->size / + sizeof(struct hdcp_trans_pairing_data); + if (mhdp->hdcp.num_paired > MAX_STORED_KM) { + /* todo: handle dropping */ + mhdp->hdcp.num_paired = MAX_STORED_KM; + DRM_DEV_INFO(mhdp->dev, + "too many paired receivers - dropping older entries\n"); + } + memcpy(&mhdp->hdcp.pairing[0], fw->data, + sizeof(struct hdcp_trans_pairing_data) * mhdp->hdcp.num_paired); + release_firmware(fw); + goto out; + } + + DRM_DEV_ERROR(mhdp->dev, "Timed out trying to load firmware\n"); + ret = -ETIMEDOUT; + out: + return ret; +} +#endif + +static int cdns_hdcp_find_km_store(struct cdns_mhdp_device *mhdp, + u8 receiver[HDCP_PAIRING_R_ID]) +{ + int i; + + DRM_DEBUG_KMS("%s()\n", __func__); + for (i = 0; i < mhdp->hdcp.num_paired; i++) { + if (memcmp(receiver, mhdp->hdcp.pairing[i].receiver_id, + HDCP_PAIRING_R_ID) == 0) { + DRM_INFO("HDCP: found receiver id: 0x%x%x%x%x%x\n", + receiver[0], receiver[1], receiver[2], receiver[3], receiver[4]); + return i; + } + } + DRM_INFO("HDCP: receiver id: 0x%x%x%x%x%x not stored\n", + receiver[0], receiver[1], receiver[2], receiver[3], receiver[4]); + return -1; +} + +static int cdns_hdcp_store_km(struct cdns_mhdp_device *mhdp, + struct hdcp_trans_pairing_data *pairing, + int stored_km_index) +{ + int i, temp_index; + struct hdcp_trans_pairing_data temp_pairing; + + DRM_DEBUG_KMS("%s()\n", __func__); + + if (stored_km_index < 0) { + /* drop one entry if array is full */ + if (mhdp->hdcp.num_paired == MAX_STORED_KM) + mhdp->hdcp.num_paired--; + + temp_index = mhdp->hdcp.num_paired; + mhdp->hdcp.num_paired++; + if (!pairing) { + DRM_ERROR("NULL HDCP pairing data!\n"); + return -1; + } else + /* save the new stored km */ + temp_pairing = *pairing; + } else { + /* save the current stored km */ + temp_index = stored_km_index; + temp_pairing = mhdp->hdcp.pairing[stored_km_index]; + } + + /* move entries one slot to the end */ + for (i = temp_index; i > 0; i--) + mhdp->hdcp.pairing[i] = mhdp->hdcp.pairing[i - 1]; + + /* save the current/new entry at the beginning */ + mhdp->hdcp.pairing[0] = temp_pairing; + + return 0; +} + +static inline int cdns_hdcp_auth_22(struct cdns_mhdp_device *mhdp) +{ + int km_idx = -1; + u8 retEvents; + u16 hdcp_port_status; + u8 resp[HDCP_STATUS_SIZE]; + struct hdcp_trans_pairing_data pairing; + int ret; + + DRM_DEBUG_KMS("HDCP: Start 2.2 Authentication\n"); + mhdp->hdcp.sink_is_repeater = 0; + + /* Wait until HDCP2_TX_IS_KM_STORED EVENT appears */ + retEvents = 0; + DRM_DEBUG_KMS("INFO: Wait until HDCP2_TX_IS_KM_STORED EVENT appears\n"); + while (check_event(retEvents, HDCPTX_IS_KM_STORED_EVENT) == 0) { + DRM_DEBUG_KMS("INFO: Waiting FOR _IS_KM_STORED EVENT\n"); + retEvents = wait4event(mhdp, &mhdp->hdcp.events, + HDCPTX_IS_KM_STORED_EVENT, HDCP_EVENT_TO_DEF); + if (retEvents == 0) + /* time out occurred, return error */ + return -1; + if (check_event(retEvents, HDCPTX_STATUS_EVENT) != 0) { + /* There was a status update, could be due to HPD + going down or some other error, check if an error + was set, if so exit. + */ + hdcp_port_status = cdns_hdcp_get_status(mhdp); + if (cdns_hdcp_handle_status(hdcp_port_status) != 0) + return -1; + } + } + + DRM_DEBUG_KMS("HDCP: HDCPTX_IS_KM_STORED_EVENT\n"); + + /* Set HDCP2 TX KM STORED REQUEST */ + ret = cdns_mhdp_hdcp2_tx_is_km_stored_req(mhdp, resp, HDCP_STATUS_SIZE); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to hdcp2 tx km stored.\n"); + return -1; + } + + DRM_DEBUG_KMS("HDCP: CDN_API_HDCP2_TX_IS_KM_STORED_REQ_blocking\n"); + DRM_DEBUG_KMS("HDCP: Receiver ID: 0x%x%x%x%x%x\n", + resp[0], resp[1], resp[2], resp[3], resp[4]); + + km_idx = cdns_hdcp_find_km_store(mhdp, resp); + + /* Check if KM is stored */ + if (km_idx >= 0) { + DRM_DEBUG_KMS("INFO: KM is stored\n"); + /* Set HDCP2 TX RESPOND KM with stored KM */ + ret = cdns_mhdp_hdcp2_tx_respond_km(mhdp, (u8 *)&mhdp->hdcp.pairing[km_idx], + sizeof(struct hdcp_trans_pairing_data)); + + DRM_DEBUG_KMS("HDCP: CDN_API_HDCP2_TX_RESPOND_KM_blocking, ret=%d\n", ret); + } else { /* KM is not stored */ + /* Set HDCP2 TX RESPOND KM with empty data */ + ret = cdns_mhdp_hdcp2_tx_respond_km(mhdp, NULL, 0); + DRM_DEBUG_KMS("INFO: KM is not stored ret=%d\n", ret); + } + + if (cdns_hdcp_check_receviers(mhdp)) + return -1; + + /* Check if KM is not stored */ + if (km_idx < 0) { + int loop_cnt = 0; + + /* Wait until HDCP2_TX_STORE_KM EVENT appears */ + retEvents = 0; + DRM_DEBUG_KMS("INFO: wait4event -> HDCPTX_STORE_KM_EVENT\n"); + while (check_event(retEvents, HDCPTX_STORE_KM_EVENT) == 0) { + retEvents = wait4event(mhdp, &mhdp->hdcp.events, + HDCPTX_STORE_KM_EVENT, HDCP_EVENT_TO_DEF); + if (check_event(retEvents, HDCPTX_STATUS_EVENT) + != 0) { + hdcp_port_status = cdns_hdcp_get_status(mhdp); + if (cdns_hdcp_handle_status(hdcp_port_status) + != 0) + return -1; + } + if (loop_cnt > 2) { + DRM_ERROR("Did not get event HDCPTX_STORE_KM_EVENT in time\n"); + return -1; + } else + loop_cnt++; + } + DRM_DEBUG_KMS("HDCP: HDCPTX_STORE_KM_EVENT\n"); + + /* Set HDCP2_TX_STORE_KM REQUEST */ + ret = cdns_mhdp_hdcp2_tx_store_km(mhdp, (u8 *)&pairing, sizeof(struct hdcp_trans_pairing_data)); + DRM_DEBUG_KMS("HDCP: CDN_API_HDCP2_TX_STORE_KM_REQ_blocking ret=%d\n", ret); + cdns_hdcp_store_km(mhdp, &pairing, km_idx); + } else + cdns_hdcp_store_km(mhdp, NULL, km_idx); + + /* Check if device was a repeater */ + hdcp_port_status = cdns_hdcp_get_status(mhdp); + + /* Exit if there was any errors logged at this point... */ + if (GET_HDCP_PORT_STS_LAST_ERR(hdcp_port_status) > 0) { + cdns_hdcp_handle_status(hdcp_port_status); + return -1; + } + + if (hdcp_port_status & HDCP_PORT_STS_REPEATER) + mhdp->hdcp.sink_is_repeater = 1; + + /* If sink was a repeater, we will be getting additional IDs to validate... + * Note that this one may take some time since spec allows up to 3s... */ + if (mhdp->hdcp.sink_is_repeater) + if (cdns_hdcp_check_receviers(mhdp)) + return -1; + + /* Slight delay to allow firmware to finish setting up authenticated state */ + msleep(300); + + DRM_INFO("Finished cdns_hdcp_auth_22\n"); + return 0; +} + +static inline int cdns_hdcp_auth_14(struct cdns_mhdp_device *mhdp) +{ + u16 hdcp_port_status; + int ret = 0; + + DRM_DEBUG_KMS("HDCP: Starting 1.4 Authentication\n"); + mhdp->hdcp.sink_is_repeater = 0; + + ret = cdns_hdcp_check_receviers(mhdp); + if (ret) + return -1; + + /* Check if device was a repeater */ + hdcp_port_status = cdns_hdcp_get_status(mhdp); + + /* Exit if there was any errors logged at this point... */ + if (GET_HDCP_PORT_STS_LAST_ERR(hdcp_port_status) > 0) { + cdns_hdcp_handle_status(hdcp_port_status); + return -1; + } + + if (hdcp_port_status & HDCP_PORT_STS_REPEATER) { + DRM_INFO("Connected to a repeater\n"); + mhdp->hdcp.sink_is_repeater = 1; + } else + DRM_INFO("Connected to a normal sink\n"); + + /* If sink was a repeater, we will be getting additional IDs to validate... + * Note that this one may take some time since spec allows up to 3s... */ + if (mhdp->hdcp.sink_is_repeater) + ret = cdns_hdcp_check_receviers(mhdp); + + /* Slight delay to allow firmware to finish setting up authenticated state */ + msleep(300); + + return ret; +} + +static int cdns_hdcp_auth(struct cdns_mhdp_device *mhdp, u8 hdcp_config) +{ + int ret = 0; + + DRM_DEBUG_KMS("HDCP: Start Authentication\n"); + + if (mhdp->hdcp.reauth_in_progress == 0) { + ret = cdns_hdcp_set_config(mhdp, hdcp_config); + if (ret) { + DRM_ERROR("cdns_hdcp_set_config failed\n"); + return -1; + } + } + + mhdp->hdcp.reauth_in_progress = 0; + mhdp->hdcp.sink_is_repeater = 0; + mhdp->hdcp.hdcp_version = hdcp_config; + + do { + if (mhdp->hdcp.cancel == 1) { + DRM_ERROR("mhdp->hdcp.cancel is TRUE\n"); + return -ECANCELED; + } + + if (hdcp_config == HDCP_TX_1) + ret = cdns_hdcp_auth_14(mhdp); + else + ret = cdns_hdcp_auth_22(mhdp); + if (ret) { + u16 hdcp_port_status; + DRM_ERROR("cdns_hdcp_auth_%s failed\n", + (hdcp_config == HDCP_TX_1) ? "14" : "22"); + hdcp_port_status = cdns_hdcp_get_status(mhdp); + cdns_hdcp_handle_status(hdcp_port_status); + return -1; + } + + ret = cdns_hdcp_auth_check(mhdp); + } while (ret == 1); + + return ret; +} + +static int _cdns_hdcp_disable(struct cdns_mhdp_device *mhdp) +{ + int ret = 0; + u8 hdcp_cfg = (HDCP_USE_KMKEY << 4); + + DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n", + mhdp->connector.base.name, mhdp->connector.base.base.id); + DRM_DEBUG_KMS("INFO: Disabling HDCP...\n"); + + ret = cdns_mhdp_hdcp_tx_config(mhdp, hdcp_cfg); + if (ret < 0) + DRM_DEBUG_KMS("cdns_mhdp_hdcp_tx_config failed\n"); + + DRM_DEBUG_KMS("HDCP is disabled\n"); + + mhdp->hdcp.events = 0; + + return ret; +} + +static int _cdns_hdcp_enable(struct cdns_mhdp_device *mhdp) +{ + int i, ret = 0, tries = 9, tries14 = 50; + u8 hpd_sts; + + hpd_sts = cdns_mhdp_read_hpd(mhdp); + if (hpd_sts == 0) { + dev_info(mhdp->dev, "%s HDP detected low, set state to DISABLING\n", __func__); + mhdp->hdcp.state = HDCP_STATE_DISABLING; + return -1; + } + + DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n", + mhdp->connector.base.name, mhdp->connector.base.base.id); + + mhdp->hdcp.events = 0; + + /* Incase of authentication failures, HDCP spec expects reauth. */ + /* TBD should this actually try 2.2 n times then 1.4? */ + for (i = 0; i < tries; i++) { + if (mhdp->hdcp.config & HDCP_CONFIG_2_2) { + ret = cdns_hdcp_auth(mhdp, HDCP_TX_2); + if (ret == 0) + return 0; + else if (ret == -ECANCELED) + return ret; + _cdns_hdcp_disable(mhdp); + } + } + + for (i = 0; i < tries14; i++) { + if (mhdp->hdcp.config & HDCP_CONFIG_1_4) { + ret = cdns_hdcp_auth(mhdp, HDCP_TX_1); + if (ret == 0) + return 0; + else if (ret == -ECANCELED) + return ret; + _cdns_hdcp_disable(mhdp); + } + DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret); + } + + DRM_ERROR("HDCP authentication failed (%d tries/%d)\n", tries, ret); + return ret; +} + +static void cdns_hdcp_check_work(struct work_struct *work) +{ + struct cdns_mhdp_hdcp *hdcp = container_of(work, + struct cdns_mhdp_hdcp, check_work.work); + struct cdns_mhdp_device *mhdp = container_of(hdcp, + struct cdns_mhdp_device, hdcp); + + /* todo: maybe we don't need to always schedule */ + cdns_hdcp_check_link(mhdp); + schedule_delayed_work(&hdcp->check_work, 50); +} + +static void cdns_hdcp_prop_work(struct work_struct *work) +{ + struct cdns_mhdp_hdcp *hdcp = container_of(work, + struct cdns_mhdp_hdcp, prop_work); + struct cdns_mhdp_device *mhdp = container_of(hdcp, + struct cdns_mhdp_device, hdcp); + + struct drm_device *dev = mhdp->drm_dev; + + drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); + mutex_lock(&mhdp->hdcp.mutex); + + /* + * This worker is only used to flip between ENABLED/DESIRED. Either of + * those to UNDESIRED is handled by core. If hdcp_value == UNDESIRED, + * we're running just after hdcp has been disabled, so just exit + */ + if (mhdp->hdcp.value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { + drm_hdcp_update_content_protection(&mhdp->connector.base, + mhdp->hdcp.value); + } + + mutex_unlock(&mhdp->hdcp.mutex); + drm_modeset_unlock(&dev->mode_config.connection_mutex); +} + +static void show_hdcp_supported(struct cdns_mhdp_device *mhdp) +{ + if ((mhdp->hdcp.config & (HDCP_CONFIG_1_4 | HDCP_CONFIG_2_2)) == + (HDCP_CONFIG_1_4 | HDCP_CONFIG_2_2)) + DRM_INFO("Both HDCP 1.4 and 2.2 are enabled\n"); + else if (mhdp->hdcp.config & HDCP_CONFIG_1_4) + DRM_INFO("Only HDCP 1.4 is enabled\n"); + else if (mhdp->hdcp.config & HDCP_CONFIG_2_2) + DRM_INFO("Only HDCP 2.2 is enabled\n"); + else + DRM_INFO("HDCP is disabled\n"); +} + +static ssize_t HDCPTX_do_reauth_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count); +static struct device_attribute HDCPTX_do_reauth = __ATTR_WO(HDCPTX_do_reauth); + +static ssize_t HDCPTX_do_reauth_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int ret; + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + ret = cdns_mhdp_hdcp_tx_reauth(mhdp, 1); + if (ret < 0) { + dev_err(dev, "%s cdns_mhdp_hdcp_tx_reauth failed\n", __func__); + return -1; + } + + return count; +} + +static ssize_t HDCPTX_Version_show(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t HDCPTX_Version_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count); +static struct device_attribute HDCPTX_Version = __ATTR_RW(HDCPTX_Version); + +static ssize_t HDCPTX_Version_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + int value, ret; + + ret = kstrtoint(buf, 10, &value); + if (ret != 0) + return -EINVAL; + + if (value == 2) + mhdp->hdcp.config = 2; + else if (value == 1) + mhdp->hdcp.config = 1; + else if (value == 3) + mhdp->hdcp.config = 3; + else + mhdp->hdcp.config = 0; + + return count; +} + +ssize_t HDCPTX_Version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", mhdp->hdcp.config); +} + +static ssize_t HDCPTX_Status_show(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t HDCPTX_Status_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count); +static struct device_attribute HDCPTX_Status = __ATTR_RW(HDCPTX_Status); + +ssize_t HDCPTX_Status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + switch (mhdp->hdcp.state) { + case HDCP_STATE_NO_AKSV: + return sprintf(buf, "%d :HDCP_STATE_NO_AKSV\n", mhdp->hdcp.state); + case HDCP_STATE_INACTIVE: + return sprintf(buf, "%d :HDCP_STATE_INACTIVE\n", mhdp->hdcp.state); + case HDCP_STATE_ENABLING: + return sprintf(buf, "%d :HDCP_STATE_ENABLING\n", mhdp->hdcp.state); + case HDCP_STATE_AUTHENTICATING: + return sprintf(buf, "%d :HDCP_STATE_AUTHENTICATING\n", mhdp->hdcp.state); + case HDCP_STATE_AUTHENTICATED: + return sprintf(buf, "%d :HDCP_STATE_AUTHENTICATED\n", mhdp->hdcp.state); + case HDCP_STATE_DISABLING: + return sprintf(buf, "%d :HDCP_STATE_DISABLING\n", mhdp->hdcp.state); + case HDCP_STATE_AUTH_FAILED: + return sprintf(buf, "%d :HDCP_STATE_AUTH_FAILED\n", mhdp->hdcp.state); + default: + return sprintf(buf, "%d :HDCP_STATE don't exist\n", mhdp->hdcp.state); + } +} + +ssize_t HDCPTX_Status_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + int value, ret; + + if (count == 2) { + ret = kstrtoint(buf, 10, &value); + if (ret != 0) + return -EINVAL; + + if ((value >= HDCP_STATE_NO_AKSV) && (value <= HDCP_STATE_AUTH_FAILED)) { + mhdp->hdcp.state = value; + return count; + } + dev_err(dev, "%s &hdp->state invalid\n", __func__); + return -1; + } + + dev_info(dev, "%s &hdp->state desired %s count=%d\n ", __func__, buf, (int)count); + + if (strncmp(buf, "HDCP_STATE_NO_AKSV", count - 1) == 0) + mhdp->hdcp.state = HDCP_STATE_NO_AKSV; + else if (strncmp(buf, "HDCP_STATE_INACTIVE", count - 1) == 0) + mhdp->hdcp.state = HDCP_STATE_INACTIVE; + else if (strncmp(buf, "HDCP_STATE_ENABLING", count - 1) == 0) + mhdp->hdcp.state = HDCP_STATE_ENABLING; + else if (strncmp(buf, "HDCP_STATE_AUTHENTICATING", count - 1) == 0) + mhdp->hdcp.state = HDCP_STATE_AUTHENTICATING; + else if (strncmp(buf, "HDCP_STATE_AUTHENTICATED", count - 1) == 0) + mhdp->hdcp.state = HDCP_STATE_AUTHENTICATED; + else if (strncmp(buf, "HDCP_STATE_DISABLING", count - 1) == 0) + mhdp->hdcp.state = HDCP_STATE_DISABLING; + else if (strncmp(buf, "HDCP_STATE_AUTH_FAILED", count - 1) == 0) + mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; + else + dev_err(dev, "%s &hdp->state invalid\n", __func__); + return -1; +} + +void cnds_hdcp_create_device_files(struct cdns_mhdp_device *mhdp) +{ + + if (device_create_file(mhdp->dev, &HDCPTX_do_reauth)) { + DRM_ERROR("Unable to create HDCPTX_do_reauth sysfs\n"); + device_remove_file(mhdp->dev, &HDCPTX_do_reauth); + } + + if (device_create_file(mhdp->dev, &HDCPTX_Version)) { + DRM_ERROR("Unable to create HDCPTX_Version sysfs\n"); + device_remove_file(mhdp->dev, &HDCPTX_Version); + } + + if (device_create_file(mhdp->dev, &HDCPTX_Status)) { + DRM_ERROR(KERN_ERR "Unable to create HDCPTX_Status sysfs\n"); + device_remove_file(mhdp->dev, &HDCPTX_Status); + } +} +EXPORT_SYMBOL(cnds_hdcp_create_device_files); + +void cnds_hdcp_remove_device_files(struct cdns_mhdp_device *mhdp) +{ + device_remove_file(mhdp->dev, &HDCPTX_Status); + device_remove_file(mhdp->dev, &HDCPTX_Version); + device_remove_file(mhdp->dev, &HDCPTX_do_reauth); +} +EXPORT_SYMBOL(cnds_hdcp_remove_device_files); + +#ifdef DEBUG +void cdns_hdcp_show_pairing(struct cdns_mhdp_device *mhdp, struct hdcp_trans_pairing_data *p) +{ + char s[80]; + int i, k; + + DRM_INFO("Reveiver ID: %.2X%.2X%.2X%.2X%.2X\n", + p->receiver_id[0], + p->receiver_id[1], + p->receiver_id[2], + p->receiver_id[3], + p->receiver_id[4]); + for (k = 0, i = 0; k < 16; k++) + i += snprintf(&s[i], sizeof(s), "%02x", p->m[k]); + + DRM_INFO("\tm: %s\n", s); + + for (k = 0, i = 0; k < 16; k++) + i += snprintf(&s[i], sizeof(s), "%02x", p->km[k]); + + DRM_INFO("\tkm: %s\n", s); + + for (k = 0, i = 0; k < 16; k++) + i += snprintf(&s[i], sizeof(s), "%02x", p->ekh[k]); + + DRM_INFO("\tekh: %s\n", s); +} +#endif + +static int cdns_hdcp_dump_pairing(struct seq_file *s, void *data) +{ + struct cdns_mhdp_device *mhdp = data; +#ifdef DEBUG + int i; + for (i = 0; i < mhdp->hdcp.num_paired; i++) + cdns_hdcp_show_pairing(mhdp, &mhdp->hdcp.pairing[i]); +#endif + return seq_write(s, &mhdp->hdcp.pairing[0], + mhdp->hdcp.num_paired * sizeof(struct hdcp_trans_pairing_data)); +} + +static int cdns_hdcp_pairing_show(struct seq_file *s, void *data) +{ + return cdns_hdcp_dump_pairing(s, s->private); +} + +static int cdns_hdcp_dump_pairing_open(struct inode *inode, struct file *file) +{ + return single_open(file, cdns_hdcp_pairing_show, inode->i_private); +} + +static const struct file_operations cdns_hdcp_dump_fops = { + .open = cdns_hdcp_dump_pairing_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void cdns_hdcp_debugfs_init(struct cdns_mhdp_device *mhdp) +{ + struct dentry *d, *root; + + root = debugfs_create_dir("imx-hdcp", NULL); + if (IS_ERR(root) || !root) + goto err; + + d = debugfs_create_file("dump_pairing", 0444, root, mhdp, + &cdns_hdcp_dump_fops); + if (!d) + goto err; + return; + +err: + dev_err(mhdp->dev, "Unable to create debugfs entries\n"); +} + +int cdns_hdcp_init(struct cdns_mhdp_device *mhdp, struct device_node *of_node) +{ + const char *compat; + u32 temp; + int ret; + + ret = of_property_read_string(of_node, "compatible", &compat); + if (ret) { + DRM_ERROR("Failed to compatible dts string\n"); + return ret; + } + + if (!(strstr(compat, "hdmi") || strstr(compat, "dp"))) + return -EPERM; + + ret = of_property_read_u32(of_node, "hdcp-config", &temp); + if (ret) { + /* using highest level by default */ + mhdp->hdcp.config = HDCP_CONFIG_2_2; + DRM_INFO("Failed to get HDCP config - using HDCP 2.2 only\n"); + } else { + mhdp->hdcp.config = temp; + show_hdcp_supported(mhdp); + } + + cdns_hdcp_debugfs_init(mhdp); + +#ifdef USE_DEBUG_KEYS /* reserve for hdcp test key */ + { + u8 hdcp_cfg; + hdcp_cfg = HDCP_TX_2 | (HDCP_USE_KMKEY << 4) | (HDCP_CONTENT_TYPE_0 << 3); + imx_hdmi_load_test_keys(mhdp, &hdcp_cfg); + } +#endif + + mhdp->hdcp.state = HDCP_STATE_INACTIVE; + + mutex_init(&mhdp->hdcp.mutex); + INIT_DELAYED_WORK(&mhdp->hdcp.check_work, cdns_hdcp_check_work); + INIT_WORK(&mhdp->hdcp.prop_work, cdns_hdcp_prop_work); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_hdcp_init); + +int cdns_hdcp_enable(struct cdns_mhdp_device *mhdp) +{ + int ret = 0; + + mhdp->hdcp.reauth_in_progress = 0; + +#ifdef STORE_PAIRING + cdns_hdcp_get_stored_pairing(mhdp); +#endif + msleep(500); + + mutex_lock(&mhdp->hdcp.mutex); + + mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_DESIRED; + mhdp->hdcp.state = HDCP_STATE_ENABLING; + mhdp->hdcp.cancel = 0; + + schedule_work(&mhdp->hdcp.prop_work); + schedule_delayed_work(&mhdp->hdcp.check_work, 50); + + mutex_unlock(&mhdp->hdcp.mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_hdcp_enable); + +int cdns_hdcp_disable(struct cdns_mhdp_device *mhdp) +{ + int ret = 0; + + cancel_delayed_work_sync(&mhdp->hdcp.check_work); + + mutex_lock(&mhdp->hdcp.mutex); + if (mhdp->hdcp.value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { + mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; + mhdp->hdcp.state = HDCP_STATE_DISABLING; + mhdp->hdcp.cancel = 1; + schedule_work(&mhdp->hdcp.prop_work); + } + + mutex_unlock(&mhdp->hdcp.mutex); + + /* Make sure HDCP_STATE_DISABLING state is handled */ + cdns_hdcp_check_link(mhdp); + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_hdcp_disable); + +void cdns_hdcp_atomic_check(struct drm_connector *connector, + struct drm_connector_state *old_state, + struct drm_connector_state *new_state) +{ + u64 old_cp = old_state->content_protection; + u64 new_cp = new_state->content_protection; + struct drm_crtc_state *crtc_state; + + if (!new_state->crtc) { + /* + * If the connector is being disabled with CP enabled, mark it + * desired so it's re-enabled when the connector is brought back + */ + if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) + new_state->content_protection = + DRM_MODE_CONTENT_PROTECTION_DESIRED; + return; + } + + /* + * Nothing to do if the state didn't change, or HDCP was activated since + * the last commit + */ + if (old_cp == new_cp || + (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && + new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) + return; + + crtc_state = drm_atomic_get_new_crtc_state(new_state->state, new_state->crtc); + crtc_state->mode_changed = true; +} +EXPORT_SYMBOL_GPL(cdns_hdcp_atomic_check); + +static int cdns_hdcp_check_link(struct cdns_mhdp_device *mhdp) +{ + u16 hdcp_port_status = 0; + u8 hdcp_last_error = 0; + u8 hpd_sts; + int ret = 0; + + mhdp->hdcp.reauth_in_progress = 0; + mutex_lock(&mhdp->lock); + + if (mhdp->hdcp.state == HDCP_STATE_INACTIVE) + goto out; + + if (mhdp->hdcp.state == HDCP_STATE_DISABLING) { + _cdns_hdcp_disable(mhdp); + mhdp->hdcp.state = HDCP_STATE_INACTIVE; + goto out; + } + + if ((mhdp->hdcp.state == HDCP_STATE_AUTHENTICATED) || + (mhdp->hdcp.state == HDCP_STATE_AUTHENTICATING) || + (mhdp->hdcp.state == HDCP_STATE_REAUTHENTICATING) || + (mhdp->hdcp.state == HDCP_STATE_ENABLING)) { + + /* In active states, check the HPD signal. Because of the IRQ + * debounce delay, the state might not reflect the disconnection. + * The FW could already have detected the HDP down and reported error */ + hpd_sts = cdns_mhdp_read_hpd(mhdp); + if (hpd_sts == 0) { + mhdp->hdcp.state = HDCP_STATE_DISABLING; + goto out; + } + } + +/* TODO items: + Need to make sure that any requests from the firmware are actually + processed so want to remove this first jump to 'out', i.e. process + reauthentication requests, cleanup errors and repeater receiver id + checks. +*/ + if (mhdp->hdcp.state == HDCP_STATE_AUTHENTICATED) { + /* get port status */ + hdcp_port_status = cdns_hdcp_get_status(mhdp); + hdcp_last_error = GET_HDCP_PORT_STS_LAST_ERR(hdcp_port_status); + if (hdcp_last_error == HDCP_TRAN_ERR_REAUTH_REQ) { + DRM_INFO("Sink requesting re-authentication\n"); + mhdp->hdcp.state = HDCP_STATE_REAUTHENTICATING; + } else if (hdcp_last_error) { + DRM_ERROR("HDCP error no: %u\n", hdcp_last_error); + + if (mhdp->hdcp.value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) + goto out; + if (hdcp_port_status & HDCP_PORT_STS_AUTH) { + if (mhdp->hdcp.value != + DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { + mhdp->hdcp.value = + DRM_MODE_CONTENT_PROTECTION_ENABLED; + schedule_work(&mhdp->hdcp.prop_work); + goto out; + } + } + + mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; + + } else if (mhdp->hdcp.sink_is_repeater) { + u8 new_events; + /* Check events... and process if HDCPTX_IS_RECEIVER_ID_VALID_EVENT. */ + new_events = cdns_mhdp_get_event(mhdp); + mhdp->hdcp.events |= new_events; + if (check_event(mhdp->hdcp.events, HDCPTX_IS_RECEIVER_ID_VALID_EVENT)) { + DRM_INFO("Sink repeater updating receiver ID list...\n"); + if (cdns_hdcp_check_receviers(mhdp)) + mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; + } + } + } + + if (mhdp->hdcp.state == HDCP_STATE_REAUTHENTICATING) { + /* For now just deal with HDCP2.2 */ + if (mhdp->hdcp.hdcp_version == HDCP_TX_2) + mhdp->hdcp.reauth_in_progress = 1; + else + mhdp->hdcp.state = HDCP_STATE_AUTH_FAILED; + } + + if (mhdp->hdcp.state == HDCP_STATE_ENABLING) { + mhdp->hdcp.state = HDCP_STATE_AUTHENTICATING; + ret = _cdns_hdcp_enable(mhdp); + if (ret == -ECANCELED) + goto out; + else if (ret) { + DRM_ERROR("Failed to enable hdcp (%d)\n", ret); + mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_DESIRED; + schedule_work(&mhdp->hdcp.prop_work); + goto out; + } + } + + if ((mhdp->hdcp.state == HDCP_STATE_AUTH_FAILED) || + (mhdp->hdcp.state == HDCP_STATE_REAUTHENTICATING)) { + + print_port_status(hdcp_port_status); + if (mhdp->hdcp.state == HDCP_STATE_AUTH_FAILED) { + DRM_DEBUG_KMS("[%s:%d] HDCP link failed, retrying authentication 0x%2x\n", + mhdp->connector.base.name, mhdp->connector.base.base.id, hdcp_port_status); + ret = _cdns_hdcp_disable(mhdp); + if (ret) { + DRM_ERROR("Failed to disable hdcp (%d)\n", ret); + mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_DESIRED; + schedule_work(&mhdp->hdcp.prop_work); + goto out; + } + } else + DRM_DEBUG_KMS("[%s:%d] HDCP attempt reauthentication 0x%2x\n", + mhdp->connector.base.name, mhdp->connector.base.base.id, hdcp_port_status); + + ret = _cdns_hdcp_enable(mhdp); + if (ret == -ECANCELED) + goto out; + else if (ret) { + DRM_ERROR("Failed to enable hdcp (%d)\n", ret); + mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_DESIRED; + schedule_work(&mhdp->hdcp.prop_work); + goto out; + } + } + +out: + mutex_unlock(&mhdp->lock); + + return ret; +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.h linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.h --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-hdcp-common.h 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 NXP Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef CDNS_HDCP_COMMON_H +#define CDNS_HDCP_COMMON_H + +int cdns_hdcp_init(struct cdns_mhdp_device *mhdp, struct device_node *of_node); +int cdns_hdcp_enable(struct cdns_mhdp_device *mhdp); +int cdns_hdcp_disable(struct cdns_mhdp_device *mhdp); +void cdns_hdcp_atomic_check(struct drm_connector *connector, + struct drm_connector_state *old_state, + struct drm_connector_state *new_state); +void cnds_hdcp_create_device_files(struct cdns_mhdp_device *mhdp); +void cnds_hdcp_remove_device_files(struct cdns_mhdp_device *mhdp); + +#endif /* CDNS_HDCP_COMMON_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,839 @@ +/* + * Cadence High-Definition Multimedia Interface (HDMI) driver + * + * Copyright 2019-2021 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cdns-mhdp-hdcp.h" +#include "cdns-hdcp-common.h" + +static void hdmi_sink_config(struct cdns_mhdp_device *mhdp) +{ + struct drm_display_info *display = &mhdp->connector.base.display_info; + u8 buff = 0; + + /* check sink type (HDMI or DVI) */ + if (!display->is_hdmi) { + mhdp->hdmi.hdmi_type = MODE_DVI; + return; + } + + mhdp->hdmi.hdmi_type = MODE_HDMI_1_4; + + /* check HDMI2.0 sink */ + if (!display->hdmi.scdc.supported) + return; + + if (mhdp->hdmi.char_rate > 340000) { + /* + * TMDS Character Rate above 340MHz should working in HDMI2.0 + * Enable scrambling and TMDS_Bit_Clock_Ratio + */ + buff = SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE; + mhdp->hdmi.hdmi_type = MODE_HDMI_2_0; + } else if (display->hdmi.scdc.scrambling.low_rates) { + /* + * Enable scrambling and HDMI2.0 when scrambling capability of sink + * be indicated in the HF-VSDB LTE_340Mcsc_scramble bit + */ + buff = SCDC_SCRAMBLING_ENABLE; + mhdp->hdmi.hdmi_type = MODE_HDMI_2_0; + } + + /* TMDS config */ + cdns_hdmi_scdc_write(mhdp, 0x20, buff); +} + +static void hdmi_lanes_config(struct cdns_mhdp_device *mhdp) +{ + /* Line swaping */ + cdns_mhdp_reg_write(mhdp, LANES_CONFIG, 0x00400000 | mhdp->lane_mapping); +} + +static int hdmi_avi_info_set(struct cdns_mhdp_device *mhdp, + struct drm_display_mode *mode) +{ + struct hdmi_avi_infoframe frame; + int format = mhdp->video_info.color_fmt; + struct drm_connector_state *conn_state = mhdp->connector.base.state; + struct drm_display_mode *adj_mode; + enum hdmi_quantization_range qr; + u8 buf[32]; + int ret; + + /* Initialise info frame from DRM mode */ + drm_hdmi_avi_infoframe_from_display_mode(&frame, &mhdp->connector.base, + mode); + + switch (format) { + case YCBCR_4_4_4: + frame.colorspace = HDMI_COLORSPACE_YUV444; + break; + case YCBCR_4_2_2: + frame.colorspace = HDMI_COLORSPACE_YUV422; + break; + case YCBCR_4_2_0: + frame.colorspace = HDMI_COLORSPACE_YUV420; + break; + default: + frame.colorspace = HDMI_COLORSPACE_RGB; + break; + } + + drm_hdmi_avi_infoframe_colorimetry(&frame, conn_state); + + adj_mode = &mhdp->bridge.base.encoder->crtc->state->adjusted_mode; + + qr = drm_default_rgb_quant_range(adj_mode); + + drm_hdmi_avi_infoframe_quant_range(&frame, &mhdp->connector.base, + adj_mode, qr); + + ret = hdmi_avi_infoframe_check(&frame); + if (WARN_ON(ret)) + return false; + + ret = hdmi_avi_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_ERROR("failed to pack AVI infoframe: %d\n", ret); + return -1; + } + + buf[0] = 0; + cdns_mhdp_infoframe_set(mhdp, 0, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_AVI); + return 0; +} + +static void hdmi_vendor_info_set(struct cdns_mhdp_device *mhdp, + struct drm_display_mode *mode) +{ + struct hdmi_vendor_infoframe frame; + u8 buf[32]; + int ret; + + /* Initialise vendor frame from DRM mode */ + ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame, &mhdp->connector.base, mode); + if (ret < 0) { + DRM_INFO("No vendor infoframe\n"); + return; + } + + ret = hdmi_vendor_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_WARN("Unable to pack vendor infoframe: %d\n", ret); + return; + } + + buf[0] = 0; + cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_VENDOR); +} + +static void hdmi_drm_info_set(struct cdns_mhdp_device *mhdp) +{ + struct drm_connector_state *conn_state; + struct hdmi_drm_infoframe frame; + u8 buf[32]; + int ret; + + conn_state = mhdp->connector.base.state; + + if (!conn_state->hdr_output_metadata) + return; + + ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); + if (ret < 0) { + DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); + return; + } + + ret = hdmi_drm_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_DEBUG_KMS("couldn't pack HDR infoframe\n"); + return; + } + + buf[0] = 0; + cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), + buf, HDMI_INFOFRAME_TYPE_DRM); +} + +void cdns_hdmi_mode_set(struct cdns_mhdp_device *mhdp) +{ + struct drm_display_mode *mode = &mhdp->mode; + int ret; + + /* video mode valid check */ + if (mode->clock == 0 || mode->hdisplay == 0 || mode->vdisplay == 0) + return; + + hdmi_lanes_config(mhdp); + + cdns_mhdp_plat_call(mhdp, pclk_rate); + + /* delay for HDMI FW stable after pixel clock relock */ + msleep(20); + + cdns_mhdp_plat_call(mhdp, phy_set); + + hdmi_sink_config(mhdp); + + ret = cdns_hdmi_ctrl_init(mhdp, mhdp->hdmi.hdmi_type, mhdp->hdmi.char_rate); + if (ret < 0) { + DRM_ERROR("%s, ret = %d\n", __func__, ret); + return; + } + + /* Config GCP */ + if (mhdp->video_info.color_depth == 8) + cdns_hdmi_disable_gcp(mhdp); + else + cdns_hdmi_enable_gcp(mhdp); + + ret = hdmi_avi_info_set(mhdp, mode); + if (ret < 0) { + DRM_ERROR("%s ret = %d\n", __func__, ret); + return; + } + + /* vendor info frame is enable only when HDMI1.4 4K mode */ + hdmi_vendor_info_set(mhdp, mode); + + hdmi_drm_info_set(mhdp); + + ret = cdns_hdmi_mode_config(mhdp, mode, &mhdp->video_info); + if (ret < 0) { + DRM_ERROR("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret); + return; + } +} + +static void handle_plugged_change(struct cdns_mhdp_device *mhdp, bool plugged) +{ + if (mhdp->plugged_cb && mhdp->codec_dev) + mhdp->plugged_cb(mhdp->codec_dev, plugged); +} + +int cdns_hdmi_set_plugged_cb(struct cdns_mhdp_device *mhdp, + hdmi_codec_plugged_cb fn, + struct device *codec_dev) +{ + bool plugged; + + mutex_lock(&mhdp->lock); + mhdp->plugged_cb = fn; + mhdp->codec_dev = codec_dev; + plugged = mhdp->last_connector_result == connector_status_connected; + handle_plugged_change(mhdp, plugged); + mutex_unlock(&mhdp->lock); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_hdmi_set_plugged_cb); + +static enum drm_connector_status +cdns_hdmi_connector_detect(struct drm_connector *connector, bool force) +{ + struct cdns_mhdp_device *mhdp = + container_of(connector, struct cdns_mhdp_device, connector.base); + enum drm_connector_status result; + + u8 hpd = 0xf; + + hpd = cdns_mhdp_read_hpd(mhdp); + + if (hpd == 1) + /* Cable Connected */ + result = connector_status_connected; + else if (hpd == 0) + /* Cable Disconnedted */ + result = connector_status_disconnected; + else { + /* Cable status unknown */ + DRM_INFO("Unknow cable status, hdp=%u\n", hpd); + result = connector_status_unknown; + } + + mutex_lock(&mhdp->lock); + if (result != mhdp->last_connector_result) { + handle_plugged_change(mhdp, + result == connector_status_connected); + mhdp->last_connector_result = result; + } + mutex_unlock(&mhdp->lock); + + return result; +} + +static int cdns_hdmi_connector_get_modes(struct drm_connector *connector) +{ + struct cdns_mhdp_device *mhdp = + container_of(connector, struct cdns_mhdp_device, connector.base); + int num_modes = 0; + struct edid *edid; + + edid = drm_do_get_edid(&mhdp->connector.base, + cdns_hdmi_get_edid_block, mhdp); + if (edid) { + dev_info(mhdp->dev, "%x,%x,%x,%x,%x,%x,%x,%x\n", + edid->header[0], edid->header[1], + edid->header[2], edid->header[3], + edid->header[4], edid->header[5], + edid->header[6], edid->header[7]); + drm_connector_update_edid_property(connector, edid); + num_modes = drm_add_edid_modes(connector, edid); + kfree(edid); + } + + if (num_modes == 0) + DRM_ERROR("Invalid edid\n"); + return num_modes; +} + +static bool blob_equal(const struct drm_property_blob *a, + const struct drm_property_blob *b) +{ + if (a && b) + return a->length == b->length && + !memcmp(a->data, b->data, a->length); + + return !a == !b; +} + +static void cdns_hdmi_bridge_disable(struct drm_bridge *bridge) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + + cdns_hdcp_disable(mhdp); +} + +static void cdns_hdmi_bridge_enable(struct drm_bridge *bridge) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_connector_state *conn_state = mhdp->connector.base.state; + + if (conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) + cdns_hdcp_enable(mhdp); +} + +static int cdns_hdmi_connector_atomic_check(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + struct drm_connector_state *new_con_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_connector_state *old_con_state = + drm_atomic_get_old_connector_state(state, connector); + struct drm_crtc *crtc = new_con_state->crtc; + struct drm_crtc_state *new_crtc_state; + struct cdns_mhdp_device *mhdp = + container_of(connector, struct cdns_mhdp_device, connector.base); + + cdns_hdcp_atomic_check(connector, old_con_state, new_con_state); + if (!new_con_state->crtc) + return 0; + + new_crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(new_crtc_state)) + return PTR_ERR(new_crtc_state); + + if (!blob_equal(new_con_state->hdr_output_metadata, + old_con_state->hdr_output_metadata) || + new_con_state->colorspace != old_con_state->colorspace) { + + new_crtc_state->mode_changed = + !new_con_state->hdr_output_metadata || + !old_con_state->hdr_output_metadata || + new_con_state->colorspace != old_con_state->colorspace; + } + /* save new connector state */ + memcpy(&mhdp->connector.new_state, new_con_state, sizeof(struct drm_connector_state)); + + /* + * These properties are handled by fastset, and might not end up in a + * modeset. + */ + if (new_con_state->picture_aspect_ratio != + old_con_state->picture_aspect_ratio || + new_con_state->content_type != old_con_state->content_type || + new_con_state->scaling_mode != old_con_state->scaling_mode) + new_crtc_state->mode_changed = true; + return 0; +} + +static const struct drm_connector_funcs cdns_hdmi_connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = cdns_hdmi_connector_detect, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_connector_helper_funcs cdns_hdmi_connector_helper_funcs = { + .get_modes = cdns_hdmi_connector_get_modes, + .atomic_check = cdns_hdmi_connector_atomic_check, +}; + +static int cdns_hdmi_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_mode_config *config = &bridge->dev->mode_config; + struct drm_encoder *encoder = bridge->encoder; + struct drm_connector *connector = &mhdp->connector.base; + int ret; + + connector->interlace_allowed = 1; + connector->polled = DRM_CONNECTOR_POLL_HPD; + if (!strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) + connector->ycbcr_420_allowed = true; + + drm_connector_helper_add(connector, &cdns_hdmi_connector_helper_funcs); + + ret = drm_connector_init(bridge->dev, connector, &cdns_hdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + if (ret < 0) { + DRM_ERROR("Failed to initialize connector\n"); + return ret; + } + + if (!strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { + drm_object_attach_property(&connector->base, + config->hdr_output_metadata_property, + 0); + + if (!drm_mode_create_hdmi_colorspace_property(connector)) + drm_object_attach_property(&connector->base, + connector->colorspace_property, + 0); + } + + drm_connector_attach_encoder(connector, encoder); + + drm_connector_attach_content_protection_property(connector, true); + return 0; +} + +static enum drm_mode_status +cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + enum drm_mode_status mode_status = MODE_OK; + u32 vic; + int ret; + + /* We don't support double-clocked and Interlaced modes */ + if (mode->flags & DRM_MODE_FLAG_DBLCLK || + mode->flags & DRM_MODE_FLAG_INTERLACE) + return MODE_BAD; + + /* MAX support pixel clock rate 594MHz */ + if (mode->clock > 594000) + return MODE_CLOCK_HIGH; + + /* 5120 x 2160 is the maximum supported resolution */ + if (mode->hdisplay > 5120 || mode->vdisplay > 2160) + return MODE_BAD_HVALUE; + + /* imx8mq-hdmi does not support non CEA modes */ + if (!strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { + vic = drm_match_cea_mode(mode); + if (vic == 0) + return MODE_BAD; + } + + mhdp->valid_mode = mode; + ret = cdns_mhdp_plat_call(mhdp, phy_video_valid); + if (ret == false) + return MODE_CLOCK_RANGE; + + return mode_status; +} + +static void cdns_hdmi_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *orig_mode, + const struct drm_display_mode *mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct video_info *video = &mhdp->video_info; + + video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); + video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); + + DRM_INFO("Mode: %dx%dp%d\n", mode->hdisplay, mode->vdisplay, mode->clock); + memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode)); + + mutex_lock(&mhdp->lock); + cdns_hdmi_mode_set(mhdp); + mutex_unlock(&mhdp->lock); +} + +bool cdns_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_connector_state *new_state = &mhdp->connector.new_state; + struct drm_display_info *di = &mhdp->connector.base.display_info; + struct video_info *video = &mhdp->video_info; + int vic = drm_match_cea_mode(mode); + + video->color_depth = 8; + video->color_fmt = PXL_RGB; + + /* for all other platforms, other than imx8mq */ + if (strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { + /* In color depth mode, + * if the character clock rate exceed max_tmds_clock + * video should default work in bpc = 8. + */ + if ((mode->clock * di->bpc / 8) > di->max_tmds_clock) + return true; + + /* only bpc less than 12 is supported */ + if (di->bpc == 10 || di->bpc == 6) + video->color_depth = di->bpc; + + return true; + } + + /* H20 Section 7.2.2, Colorimetry BT2020 for pixel encoding 10bpc or more */ + if (new_state->colorspace == DRM_MODE_COLORIMETRY_BT2020_RGB) { + if (drm_mode_is_420_only(di, mode)) + return false; + + /* BT2020_RGB for RGB 10bit or more */ + /* 10b RGB is not supported for following VICs */ + if (vic == 97 || vic == 96 || vic == 95 || vic == 93 || vic == 94) + return false; + + video->color_depth = 10; + } else if (new_state->colorspace == DRM_MODE_COLORIMETRY_BT2020_CYCC || + new_state->colorspace == DRM_MODE_COLORIMETRY_BT2020_YCC) { + /* BT2020_YCC/CYCC for YUV 10bit or more */ + if (drm_mode_is_420_only(di, mode) || + drm_mode_is_420_also(di, mode)) + video->color_fmt = YCBCR_4_2_0; + else + video->color_fmt = YCBCR_4_2_2; + + if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) + video->color_depth = 12; + else if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) + video->color_depth = 10; + } else if (new_state->colorspace == DRM_MODE_COLORIMETRY_SMPTE_170M_YCC || + new_state->colorspace == DRM_MODE_COLORIMETRY_BT709_YCC || + new_state->colorspace == DRM_MODE_COLORIMETRY_XVYCC_601 || + new_state->colorspace == DRM_MODE_COLORIMETRY_XVYCC_709 || + new_state->colorspace == DRM_MODE_COLORIMETRY_SYCC_601) { + /* Colorimetry for HD and SD YUV */ + if (drm_mode_is_420_only(di, mode) || drm_mode_is_420_also(di, mode)) + video->color_fmt = YCBCR_4_2_0; + else + video->color_fmt = YCBCR_4_4_4; + } else if (new_state->colorspace == DRM_MODE_COLORIMETRY_DEFAULT) { + /* set default color fmt for YUV420 only mode */ + if (drm_mode_is_420_only(di, mode)) + video->color_fmt = YCBCR_4_2_0; + } + + return true; +} + +static const struct drm_bridge_funcs cdns_hdmi_bridge_funcs = { + .attach = cdns_hdmi_bridge_attach, + .enable = cdns_hdmi_bridge_enable, + .disable = cdns_hdmi_bridge_disable, + .mode_set = cdns_hdmi_bridge_mode_set, + .mode_valid = cdns_hdmi_bridge_mode_valid, + .mode_fixup = cdns_hdmi_bridge_mode_fixup, +}; + +static void hotplug_work_func(struct work_struct *work) +{ + struct cdns_mhdp_device *mhdp = container_of(work, + struct cdns_mhdp_device, hotplug_work.work); + struct drm_connector *connector = &mhdp->connector.base; + + drm_helper_hpd_irq_event(connector->dev); + + if (connector->status == connector_status_connected) { + DRM_INFO("HDMI Cable Plug In\n"); + + /* Recovery HDCP state */ + if (connector->state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) + mhdp->hdcp.state = HDCP_STATE_ENABLING; + + mhdp->force_mode_set = true; + enable_irq(mhdp->irq[IRQ_OUT]); + } else if (connector->status == connector_status_disconnected) { + /* Cable Disconnedted */ + DRM_INFO("HDMI Cable Plug Out\n"); + + /* Disable HDCP when cable plugout, + * set content_protection to DESIRED, recovery HDCP state after cable plugin + */ + if (connector->state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { + connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; + mhdp->hdcp.state = HDCP_STATE_DISABLING; + } + + /* force mode set for cable replugin to recovery HDMI2.0 video modes */ + mhdp->force_mode_set = true; + enable_irq(mhdp->irq[IRQ_IN]); + } +} + +static irqreturn_t cdns_hdmi_irq_thread(int irq, void *data) +{ + struct cdns_mhdp_device *mhdp = data; + + disable_irq_nosync(irq); + + mod_delayed_work(system_wq, &mhdp->hotplug_work, + msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); + + return IRQ_HANDLED; +} + +static void cdns_hdmi_parse_dt(struct cdns_mhdp_device *mhdp) +{ + struct device_node *of_node = mhdp->dev->of_node; + int ret; + + ret = of_property_read_u32(of_node, "lane-mapping", &mhdp->lane_mapping); + if (ret) { + mhdp->lane_mapping = 0xc6; + dev_warn(mhdp->dev, "Failed to get lane_mapping - using default 0xc6\n"); + } + dev_info(mhdp->dev, "lane-mapping 0x%02x\n", mhdp->lane_mapping); +} + +#ifdef CONFIG_DRM_CDNS_HDMI_CEC +static void cdns_mhdp_cec_init(struct cdns_mhdp_device *mhdp) +{ + struct cdns_mhdp_cec *cec = &mhdp->hdmi.cec; + + cec->dev = mhdp->dev; + cec->iolock = &mhdp->iolock; + cec->regs_base = mhdp->regs_base; + cec->regs_sec = mhdp->regs_sec; + cec->bus_type = mhdp->bus_type; +} +#endif + +static int __cdns_hdmi_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + struct device *dev = &pdev->dev; + struct platform_device_info pdevinfo; + struct resource *iores = NULL; + int ret; + + mutex_init(&mhdp->lock); + mutex_init(&mhdp->api_lock); + mutex_init(&mhdp->iolock); + + INIT_DELAYED_WORK(&mhdp->hotplug_work, hotplug_work_func); + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mhdp->regs_base = devm_ioremap(dev, iores->start, resource_size(iores)); + if (IS_ERR(mhdp->regs_base)) { + dev_err(dev, "No regs_base memory\n"); + return -ENOMEM; + } + + /* sec register base */ + iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); + mhdp->regs_sec = devm_ioremap(dev, iores->start, resource_size(iores)); + if (IS_ERR(mhdp->regs_sec)) { + dev_err(dev, "No regs_sec memory\n"); + return -ENOMEM; + } + + mhdp->irq[IRQ_IN] = platform_get_irq_byname(pdev, "plug_in"); + if (mhdp->irq[IRQ_IN] < 0) { + dev_info(dev, "No plug_in irq number\n"); + return -EPROBE_DEFER; + } + + mhdp->irq[IRQ_OUT] = platform_get_irq_byname(pdev, "plug_out"); + if (mhdp->irq[IRQ_OUT] < 0) { + dev_info(dev, "No plug_out irq number\n"); + return -EPROBE_DEFER; + } + + cdns_mhdp_plat_call(mhdp, power_on); + + /* Initialize FW */ + cdns_mhdp_plat_call(mhdp, firmware_init); + + /* HDMI FW alive check */ + ret = cdns_mhdp_check_alive(mhdp); + if (ret == false) { + dev_err(dev, "NO HDMI FW running\n"); + return -ENXIO; + } + + /* Enable Hotplug Detect thread */ + irq_set_status_flags(mhdp->irq[IRQ_IN], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_IN], + NULL, cdns_hdmi_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + if (ret < 0) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_IN]); + return -EINVAL; + } + + irq_set_status_flags(mhdp->irq[IRQ_OUT], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_OUT], + NULL, cdns_hdmi_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + if (ret < 0) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_OUT]); + return -EINVAL; + } + + cdns_hdmi_parse_dt(mhdp); + + ret = cdns_hdcp_init(mhdp, pdev->dev.of_node); + if (ret < 0) + DRM_WARN("Failed to initialize HDCP\n"); + + cnds_hdcp_create_device_files(mhdp); + + if (cdns_mhdp_read_hpd(mhdp)) + enable_irq(mhdp->irq[IRQ_OUT]); + else + enable_irq(mhdp->irq[IRQ_IN]); + + mhdp->bridge.base.driver_private = mhdp; + mhdp->bridge.base.funcs = &cdns_hdmi_bridge_funcs; +#ifdef CONFIG_OF + mhdp->bridge.base.of_node = dev->of_node; +#endif + mhdp->last_connector_result = connector_status_disconnected; + + memset(&pdevinfo, 0, sizeof(pdevinfo)); + pdevinfo.parent = dev; + pdevinfo.id = PLATFORM_DEVID_AUTO; + + dev_set_drvdata(dev, mhdp); + + /* register audio driver */ + cdns_mhdp_register_audio_driver(dev); + + /* register cec driver */ +#ifdef CONFIG_DRM_CDNS_HDMI_CEC + cdns_mhdp_cec_init(mhdp); + cdns_mhdp_register_cec_driver(&mhdp->hdmi.cec); +#endif + + return 0; +} + +static void __cdns_hdmi_remove(struct cdns_mhdp_device *mhdp) +{ + /* unregister cec driver */ +#ifdef CONFIG_DRM_CDNS_HDMI_CEC + cdns_mhdp_unregister_cec_driver(&mhdp->hdmi.cec); +#endif + cdns_mhdp_unregister_audio_driver(mhdp->dev); + cnds_hdcp_remove_device_files(mhdp); + + cdns_mhdp_plat_call(mhdp, power_off); +} + +/* ----------------------------------------------------------------------------- + * Probe/remove API, used from platforms based on the DRM bridge API. + */ +int cdns_hdmi_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_hdmi_probe(pdev, mhdp); + if (ret < 0) + return ret; + + drm_bridge_add(&mhdp->bridge.base); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_hdmi_probe); + +void cdns_hdmi_remove(struct platform_device *pdev) +{ + struct cdns_mhdp_device *mhdp = platform_get_drvdata(pdev); + + drm_bridge_remove(&mhdp->bridge.base); + + __cdns_hdmi_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_hdmi_remove); + +/* ----------------------------------------------------------------------------- + * Bind/unbind API, used from platforms based on the component framework. + */ +int cdns_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_hdmi_probe(pdev, mhdp); + if (ret) + return ret; + + ret = drm_bridge_attach(encoder, &mhdp->bridge.base, NULL, 0); + if (ret) { + cdns_hdmi_remove(pdev); + DRM_ERROR("Failed to initialize bridge with drm\n"); + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_hdmi_bind); + +void cdns_hdmi_unbind(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + __cdns_hdmi_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_hdmi_unbind); + +MODULE_AUTHOR("Sandor Yu "); +MODULE_DESCRIPTION("Cadence HDMI transmitter driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:cdn-hdmi"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Author: Chris Zhong + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include + +#define CDNS_DP_SPDIF_CLK 200000000 + +static u32 TMDS_rate_table[7] = { + 25200, 27000, 54000, 74250, 148500, 297000, 594000, +}; + +static u32 N_table_32k[7] = { +/* 25200/27000/54000/74250/148500/297000/594000 */ + 4096, 4096, 4096, 4096, 4096, 3072, 3072, +}; + +static u32 N_table_44k[7] = { + 6272, 6272, 6272, 6272, 6272, 4704, 9408, +}; + +static u32 N_table_48k[7] = { + 6144, 6144, 6144, 6144, 6144, 5120, 6144, +}; + +static int select_N_index(u32 pclk) +{ + int num = sizeof(TMDS_rate_table)/sizeof(int); + int i = 0; + + for (i = 0; i < num ; i++) + if (pclk == TMDS_rate_table[i]) + break; + + if (i == num) { + DRM_WARN("pclkc %d is not supported!\n", pclk); + return num-1; + } + + return i; +} + +static void hdmi_audio_avi_set(struct cdns_mhdp_device *mhdp, + u32 channels) +{ + struct hdmi_audio_infoframe frame; + u8 buf[32]; + int ret; + + hdmi_audio_infoframe_init(&frame); + + frame.channels = channels; + frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; + + if (channels == 2) + frame.channel_allocation = 0; + else if (channels == 4) + frame.channel_allocation = 0x3; + else if (channels == 6) + frame.channel_allocation = 0xB; + else if (channels == 8) + frame.channel_allocation = 0x13; + + ret = hdmi_audio_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_ERROR("failed to pack audio infoframe: %d\n", ret); + return; + } + + buf[0] = 0; + + cdns_mhdp_infoframe_set(mhdp, 1, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_AUDIO); +} + +int cdns_mhdp_audio_stop(struct cdns_mhdp_device *mhdp, + struct audio_info *audio) +{ + int ret; + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { + ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, 0); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "audio stop failed: %d\n", ret); + return ret; + } + } + + cdns_mhdp_bus_write(0, mhdp, SPDIF_CTRL_ADDR); + + /* clearn the audio config and reset */ + cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNTL); + cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNFG); + cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, AUDIO_SRC_CNTL); + cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNTL); + + /* reset smpl2pckt component */ + cdns_mhdp_bus_write(0, mhdp, SMPL2PKT_CNTL); + cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, SMPL2PKT_CNTL); + cdns_mhdp_bus_write(0, mhdp, SMPL2PKT_CNTL); + + /* reset FIFO */ + cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, FIFO_CNTL); + cdns_mhdp_bus_write(0, mhdp, FIFO_CNTL); + + if (audio->format == AFMT_SPDIF_INT) + clk_disable_unprepare(mhdp->spdif_clk); + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_audio_stop); + +int cdns_mhdp_audio_mute(struct cdns_mhdp_device *mhdp, bool enable) +{ + struct audio_info *audio = &mhdp->audio_info; + int ret = true; + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { + ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 4, 1, enable); + if (ret) + DRM_DEV_ERROR(mhdp->dev, "audio mute failed: %d\n", ret); + } + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_audio_mute); + +static void cdns_mhdp_audio_config_i2s(struct cdns_mhdp_device *mhdp, + struct audio_info *audio) +{ + int sub_pckt_num = 1, i2s_port_en_val = 0xf, i; + int idx = select_N_index(mhdp->mode.clock); + int numofchannels = audio->channels; + u32 val, ncts; + u32 disable_port3 = 0; + u32 audio_type = 0x2; /* L-PCM */ + u32 transmission_type = 0; /* not required for L-PCM */ + + if (numofchannels == 2) { + if (mhdp->dp.num_lanes == 1) + sub_pckt_num = 2; + else + sub_pckt_num = 4; + + i2s_port_en_val = 1; + } else if (numofchannels == 4) { + i2s_port_en_val = 3; + } else if (numofchannels == 6) { + numofchannels = 8; + disable_port3 = 1; + } else if ((numofchannels == 8) && (audio->non_pcm)) { + audio_type = 0x9; /* HBR packet type */ + transmission_type = 0x9; /* HBR packet type */ + } + + cdns_mhdp_bus_write(0x0, mhdp, SPDIF_CTRL_ADDR); + + val = SYNC_WR_TO_CH_ZERO; + val |= disable_port3 << 4; + cdns_mhdp_bus_write(val, mhdp, FIFO_CNTL); + + val = MAX_NUM_CH(numofchannels); + val |= NUM_OF_I2S_PORTS(numofchannels); + val |= audio_type << 7; + val |= CFG_SUB_PCKT_NUM(sub_pckt_num); + cdns_mhdp_bus_write(val, mhdp, SMPL2PKT_CNFG); + + if (audio->sample_width == 16) + val = 0; + else if (audio->sample_width == 24) + val = 1 << 9; + else + val = 2 << 9; + + val |= AUDIO_CH_NUM(numofchannels); + val |= I2S_DEC_PORT_EN(i2s_port_en_val); + val |= TRANS_SMPL_WIDTH_32; + val |= transmission_type << 13; + cdns_mhdp_bus_write(val, mhdp, AUDIO_SRC_CNFG); + + for (i = 0; i < (numofchannels + 1) / 2; i++) { + if (audio->sample_width == 16) + val = (0x02 << 8) | (0x02 << 20); + else if (audio->sample_width == 24) + val = (0x0b << 8) | (0x0b << 20); + + val |= ((2 * i) << 4) | ((2 * i + 1) << 16); + cdns_mhdp_bus_write(val, mhdp, STTS_BIT_CH(i)); + } + + switch (audio->sample_rate) { + case 32000: + val = SAMPLING_FREQ(3) | + ORIGINAL_SAMP_FREQ(0xc); + ncts = N_table_32k[idx]; + break; + case 44100: + val = SAMPLING_FREQ(0) | + ORIGINAL_SAMP_FREQ(0xf); + ncts = N_table_44k[idx]; + break; + case 48000: + val = SAMPLING_FREQ(2) | + ORIGINAL_SAMP_FREQ(0xd); + ncts = N_table_48k[idx]; + break; + case 88200: + val = SAMPLING_FREQ(8) | + ORIGINAL_SAMP_FREQ(0x7); + ncts = N_table_44k[idx] * 2; + break; + case 96000: + val = SAMPLING_FREQ(0xa) | + ORIGINAL_SAMP_FREQ(5); + ncts = N_table_48k[idx] * 2; + break; + case 176400: + val = SAMPLING_FREQ(0xc) | + ORIGINAL_SAMP_FREQ(3); + ncts = N_table_44k[idx] * 4; + break; + case 192000: + default: + val = SAMPLING_FREQ(0xe) | + ORIGINAL_SAMP_FREQ(1); + ncts = N_table_48k[idx] * 4; + break; + } + val |= 4; + cdns_mhdp_bus_write(val, mhdp, COM_CH_STTS_BITS); + + if (audio->connector_type == DRM_MODE_CONNECTOR_HDMIA) + cdns_mhdp_reg_write(mhdp, CM_I2S_CTRL, ncts | 0x4000000); + + cdns_mhdp_bus_write(SMPL2PKT_EN, mhdp, SMPL2PKT_CNTL); + cdns_mhdp_bus_write(I2S_DEC_START, mhdp, AUDIO_SRC_CNTL); +} + +static void cdns_mhdp_audio_config_spdif(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + cdns_mhdp_bus_write(SYNC_WR_TO_CH_ZERO, mhdp, FIFO_CNTL); + + val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4); + cdns_mhdp_bus_write(val, mhdp, SMPL2PKT_CNFG); + cdns_mhdp_bus_write(SMPL2PKT_EN, mhdp, SMPL2PKT_CNTL); + + val = SPDIF_ENABLE | SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS; + cdns_mhdp_bus_write(val, mhdp, SPDIF_CTRL_ADDR); + + clk_prepare_enable(mhdp->spdif_clk); + clk_set_rate(mhdp->spdif_clk, CDNS_DP_SPDIF_CLK); +} + +int cdns_mhdp_audio_config(struct cdns_mhdp_device *mhdp, + struct audio_info *audio) +{ + int ret; + + /* reset the spdif clk before config */ + if (audio->format == AFMT_SPDIF_INT) { + reset_control_assert(mhdp->spdif_rst); + reset_control_deassert(mhdp->spdif_rst); + } + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { + ret = cdns_mhdp_reg_write(mhdp, CM_LANE_CTRL, LANE_REF_CYC); + if (ret) + goto err_audio_config; + + ret = cdns_mhdp_reg_write(mhdp, CM_CTRL, 0); + if (ret) + goto err_audio_config; + } else { + /* HDMI Mode */ + ret = cdns_mhdp_reg_write(mhdp, CM_CTRL, 8); + if (ret) + goto err_audio_config; + } + + if (audio->format == AFMT_I2S) + cdns_mhdp_audio_config_i2s(mhdp, audio); + else if (audio->format == AFMT_SPDIF_INT) + cdns_mhdp_audio_config_spdif(mhdp); + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) + ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, AUDIO_PACK_EN); + + if (audio->connector_type == DRM_MODE_CONNECTOR_HDMIA) + hdmi_audio_avi_set(mhdp, audio->channels); + +err_audio_config: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "audio config failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_audio_config); + +static int audio_hw_params(struct device *dev, void *data, + struct hdmi_codec_daifmt *daifmt, + struct hdmi_codec_params *params) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + struct audio_info audio = { + .sample_width = params->sample_width, + .sample_rate = params->sample_rate, + .channels = params->channels, + .connector_type = mhdp->connector.base.connector_type, + }; + int ret; + + switch (daifmt->fmt) { + case HDMI_I2S: + audio.format = AFMT_I2S; + break; + case HDMI_SPDIF: + audio.format = AFMT_SPDIF_EXT; + break; + default: + DRM_DEV_ERROR(dev, "Invalid format %d\n", daifmt->fmt); + ret = -EINVAL; + goto out; + } + + audio.non_pcm = params->iec.status[0] & IEC958_AES0_NONAUDIO; + + ret = cdns_mhdp_audio_config(mhdp, &audio); + if (!ret) + mhdp->audio_info = audio; + +out: + return ret; +} + +static void audio_shutdown(struct device *dev, void *data) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + int ret; + + ret = cdns_mhdp_audio_stop(mhdp, &mhdp->audio_info); + if (!ret) + mhdp->audio_info.format = AFMT_UNUSED; +} + +static int audio_mute_stream(struct device *dev, void *data, + bool enable, int direction) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + int ret; + + ret = cdns_mhdp_audio_mute(mhdp, enable); + + return ret; +} + +static int audio_get_eld(struct device *dev, void *data, + u8 *buf, size_t len) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + memcpy(buf, mhdp->connector.base.eld, + min(sizeof(mhdp->connector.base.eld), len)); + + return 0; +} + +static int audio_hook_plugged_cb(struct device *dev, void *data, + hdmi_codec_plugged_cb fn, + struct device *codec_dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + return cdns_hdmi_set_plugged_cb(mhdp, fn, codec_dev); +} + +static const struct hdmi_codec_ops audio_codec_ops = { + .hw_params = audio_hw_params, + .audio_shutdown = audio_shutdown, + .mute_stream = audio_mute_stream, + .get_eld = audio_get_eld, + .hook_plugged_cb = audio_hook_plugged_cb, + .no_capture_mute = 1, +}; + +int cdns_mhdp_register_audio_driver(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + struct hdmi_codec_pdata codec_data = { + .i2s = 1, + .spdif = 1, + .ops = &audio_codec_ops, + .max_i2s_channels = 8, + }; + + mhdp->audio_pdev = platform_device_register_data( + dev, HDMI_CODEC_DRV_NAME, 1, + &codec_data, sizeof(codec_data)); + + return PTR_ERR_OR_ZERO(mhdp->audio_pdev); +} + +void cdns_mhdp_unregister_audio_driver(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + platform_device_unregister(mhdp->audio_pdev); +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,365 @@ +/* + * Copyright 2019-2020 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include + +#define CEC_NAME "cdns-mhdp-cec" + +#define REG_ADDR_OFF 4 + +/* regsiter define */ +#define TX_MSG_HEADER 0x33800 +#define TX_MSG_LENGTH 0x33840 +#define TX_MSG_CMD 0x33844 +#define RX_MSG_CMD 0x33850 +#define RX_CLEAR_BUF 0x33854 +#define LOGICAL_ADDRESS_LA0 0x33858 + +#define CLK_DIV_MSB 0x3386c +#define CLK_DIV_LSB 0x33870 +#define RX_MSG_DATA1 0x33900 +#define RX_MSG_LENGTH 0x33940 +#define RX_MSG_STATUS 0x33944 +#define NUM_OF_MSG_RX_BUF 0x33948 +#define TX_MSG_STATUS 0x3394c +#define DB_L_TIMER 0x33980 + +/** + * CEC Transceiver operation. + */ +enum { + CEC_TX_STOP, + CEC_TX_TRANSMIT, + CEC_TX_ABORT, + CEC_TX_ABORT_AND_TRANSMIT +}; + +/** + * CEC Transceiver status. + */ +enum { + CEC_STS_IDLE, + CEC_STS_BUSY, + CEC_STS_SUCCESS, + CEC_STS_ERROR +}; + +/** + * CEC Receiver operation. + */ +enum { + CEC_RX_STOP, + CEC_RX_READ, + CEC_RX_DISABLE, + CEC_RX_ABORT_AND_CLR_FIFO +}; +/** + * Maximum number of Messages in the RX Buffers. + */ +#define CEC_MAX_RX_MSGS 2 + +static u32 mhdp_cec_read(struct cdns_mhdp_cec *cec, u32 offset) +{ + u32 val; + + mutex_lock(cec->iolock); + + if (cec->bus_type == BUS_TYPE_LOW4K_HDMI_RX) { + /* Remap address to low 4K HDMI RX */ + writel(offset >> 12, cec->regs_sec + 4); + val = readl((offset & 0xfff) + cec->regs_base); + } else if (cec->bus_type == BUS_TYPE_LOW4K_APB) { + /* Remap address to low 4K memory */ + writel(offset >> 12, cec->regs_sec + 8); + val = readl((offset & 0xfff) + cec->regs_base); + } else + val = readl(cec->regs_base + offset); + + mutex_unlock(cec->iolock); + + return val; +} + +static void mhdp_cec_write(struct cdns_mhdp_cec *cec, u32 offset, u32 val) +{ + mutex_lock(cec->iolock); + + if (cec->bus_type == BUS_TYPE_LOW4K_HDMI_RX) { + /* Remap address to low 4K SAPB bus */ + writel(offset >> 12, cec->regs_sec + 4); + writel(val, (offset & 0xfff) + cec->regs_base); + } else if (cec->bus_type == BUS_TYPE_LOW4K_APB) { + /* Remap address to low 4K memory */ + writel(offset >> 12, cec->regs_sec + 8); + writel(val, (offset & 0xfff) + cec->regs_base); + } else if (cec->bus_type == BUS_TYPE_NORMAL_SAPB) + writel(val, cec->regs_sec + offset); + else + writel(val, cec->regs_base + offset); + + mutex_unlock(cec->iolock); +} + +static u32 mhdp_get_fw_clk(struct cdns_mhdp_cec *cec) +{ + return mhdp_cec_read(cec, SW_CLK_H); +} + +static void mhdp_cec_clear_rx_buffer(struct cdns_mhdp_cec *cec) +{ + mhdp_cec_write(cec, RX_CLEAR_BUF, 1); + mhdp_cec_write(cec, RX_CLEAR_BUF, 0); +} + +static void mhdp_cec_set_divider(struct cdns_mhdp_cec *cec) +{ + u32 clk_div; + + /* Set clock divider */ + clk_div = mhdp_get_fw_clk(cec) * 10; + + mhdp_cec_write(cec, CLK_DIV_MSB, + (clk_div >> 8) & 0xFF); + mhdp_cec_write(cec, CLK_DIV_LSB, clk_div & 0xFF); +} + +static u32 mhdp_cec_read_message(struct cdns_mhdp_cec *cec) +{ + struct cec_msg *msg = &cec->msg; + int len; + int i; + + mhdp_cec_write(cec, RX_MSG_CMD, CEC_RX_READ); + + len = mhdp_cec_read(cec, RX_MSG_LENGTH); + msg->len = len + 1; + dev_dbg(cec->dev, "RX MSG len =%d\n", len); + + /* Read RX MSG bytes */ + for (i = 0; i < msg->len; ++i) { + msg->msg[i] = (u8) mhdp_cec_read(cec, RX_MSG_DATA1 + (i * REG_ADDR_OFF)); + dev_dbg(cec->dev, "RX MSG[%d]=0x%x\n", i, msg->msg[i]); + } + + mhdp_cec_write(cec, RX_MSG_CMD, CEC_RX_STOP); + + return true; +} + +static u32 mhdp_cec_write_message(struct cdns_mhdp_cec *cec, struct cec_msg *msg) +{ + u8 i; + + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); + + if (msg->len > CEC_MAX_MSG_SIZE) { + dev_err(cec->dev, "Invalid MSG size!\n"); + return -EINVAL; + } + + for (i = 0; i < msg->len; ++i) + printk("msg[%d]=0x%x\n",i, msg->msg[i]); + + /* Write Message to register */ + for (i = 0; i < msg->len; ++i) { + mhdp_cec_write(cec, TX_MSG_HEADER + (i * REG_ADDR_OFF), + msg->msg[i]); + } + /* Write Message Length (payload + opcode) */ + mhdp_cec_write(cec, TX_MSG_LENGTH, msg->len - 1); + + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_TRANSMIT); + + return true; +} + +static int mhdp_cec_set_logical_addr(struct cdns_mhdp_cec *cec, u32 la) +{ + u8 la_reg; + u8 i; + + if (la == CEC_LOG_ADDR_INVALID) { + /* invalid all LA address */ + for (i = 0; i < CEC_MAX_LOG_ADDRS; i++) + mhdp_cec_write(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF), 0); + return 0; + } + + /* In fact cdns mhdp cec could support max 5 La address */ + for (i = 0; i < CEC_MAX_LOG_ADDRS; i++) { + la_reg = mhdp_cec_read(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF)); + /* Check LA already used */ + if (la_reg & 0x10) + continue; + + if ((la_reg & 0xF) == la) { + dev_warn(cec->dev, "Warning. LA already in use.\n"); + return 0; + } + + la = (la & 0xF) | (1 << 4); + + mhdp_cec_write(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF), la); + return 0; + } + + dev_warn(cec->dev, "All LA in use\n"); + + return -ENXIO; +} + +static int mhdp_cec_poll_worker(void *_cec) +{ + struct cdns_mhdp_cec *cec = (struct cdns_mhdp_cec *)_cec; + int num_rx_msgs, i; + int sts; + + set_freezable(); + + for (;;) { + if (kthread_freezable_should_stop(NULL)) + break; + + /* Check TX State */ + sts = mhdp_cec_read(cec, TX_MSG_STATUS); + switch (sts) { + case CEC_STS_SUCCESS: + cec_transmit_done(cec->adap, CEC_TX_STATUS_OK, 0, 0, 0, + 0); + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); + break; + case CEC_STS_ERROR: + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); + cec_transmit_done(cec->adap, + CEC_TX_STATUS_MAX_RETRIES | + CEC_TX_STATUS_NACK, 0, 1, 0, 0); + break; + case CEC_STS_BUSY: + default: + break; + } + + /* Check RX State */ + sts = mhdp_cec_read(cec, RX_MSG_STATUS); + num_rx_msgs = mhdp_cec_read(cec, NUM_OF_MSG_RX_BUF); + switch (sts) { + case CEC_STS_SUCCESS: + if (num_rx_msgs == 0xf) + num_rx_msgs = CEC_MAX_RX_MSGS; + + if (num_rx_msgs > CEC_MAX_RX_MSGS) { + dev_err(cec->dev, "Error rx msg num %d\n", + num_rx_msgs); + mhdp_cec_clear_rx_buffer(cec); + break; + } + + /* Rx FIFO Depth 2 RX MSG */ + for (i = 0; i < num_rx_msgs; i++) { + mhdp_cec_read_message(cec); + cec->msg.rx_status = CEC_RX_STATUS_OK; + cec_received_msg(cec->adap, &cec->msg); + } + break; + default: + break; + } + + if (!kthread_should_stop()) + schedule_timeout_idle(20); + } + + return 0; +} + +static int mhdp_cec_adap_enable(struct cec_adapter *adap, bool enable) +{ + struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); + + if (enable) { + mhdp_cec_write(cec, DB_L_TIMER, 0x10); + mhdp_cec_set_divider(cec); + } else + mhdp_cec_set_divider(cec); + + return 0; +} + +static int mhdp_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) +{ + struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); + + return mhdp_cec_set_logical_addr(cec, addr); +} + +static int mhdp_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, + u32 signal_free_time, struct cec_msg *msg) +{ + struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); + + mhdp_cec_write_message(cec, msg); + + return 0; +} + +static const struct cec_adap_ops cdns_mhdp_cec_adap_ops = { + .adap_enable = mhdp_cec_adap_enable, + .adap_log_addr = mhdp_cec_adap_log_addr, + .adap_transmit = mhdp_cec_adap_transmit, +}; + +int cdns_mhdp_register_cec_driver(struct cdns_mhdp_cec *cec) +{ + int ret; + + cec->adap = cec_allocate_adapter(&cdns_mhdp_cec_adap_ops, cec, + CEC_NAME, + CEC_CAP_PHYS_ADDR | CEC_CAP_LOG_ADDRS | + CEC_CAP_TRANSMIT | CEC_CAP_PASSTHROUGH + | CEC_CAP_RC, CEC_MAX_LOG_ADDRS); + ret = PTR_ERR_OR_ZERO(cec->adap); + if (ret) + return ret; + ret = cec_register_adapter(cec->adap, cec->dev); + if (ret) { + cec_delete_adapter(cec->adap); + return ret; + } + + cec->cec_worker = kthread_create(mhdp_cec_poll_worker, cec, "cdns-mhdp-cec"); + if (IS_ERR(cec->cec_worker)) + dev_err(cec->dev, "failed create hdp cec thread\n"); + + wake_up_process(cec->cec_worker); + + dev_dbg(cec->dev, "CEC successfuly probed\n"); + return 0; +} + +int cdns_mhdp_unregister_cec_driver(struct cdns_mhdp_cec *cec) +{ + if (cec->cec_worker) { + kthread_stop(cec->cec_worker); + cec->cec_worker = NULL; + } + cec_unregister_adapter(cec->adap); + return 0; +} + +MODULE_AUTHOR("Sandor.Yu@NXP.com"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("NXP CDNS MHDP HDMI CEC driver"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,875 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Author: Chris Zhong + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include "cdns-mhdp.h" + +#define CDNS_DP_SPDIF_CLK 200000000 +#define FW_ALIVE_TIMEOUT_US 1000000 +u32 cdns_mhdp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset) +{ + u32 val; + + mutex_lock(&mhdp->iolock); + + if (mhdp->bus_type == BUS_TYPE_LOW4K_SAPB) { + /* Remap address to low 4K SAPB bus */ + writel(offset >> 12, mhdp->regs_sec + 0xc); + val = readl((offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { + /* Remap address to low 4K memory */ + writel(offset >> 12, mhdp->regs_sec + 8); + val = readl((offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_NORMAL_SAPB) + val = readl(mhdp->regs_sec + offset); + else + val = readl(mhdp->regs_base + offset); + + mutex_unlock(&mhdp->iolock); + + return val; +} +EXPORT_SYMBOL(cdns_mhdp_bus_read); + +void cdns_mhdp_bus_write(u32 val, struct cdns_mhdp_device *mhdp, u32 offset) +{ + mutex_lock(&mhdp->iolock); + + if (mhdp->bus_type == BUS_TYPE_LOW4K_SAPB) { + /* Remap address to low 4K SAPB bus */ + writel(offset >> 12, mhdp->regs_sec + 0xc); + writel(val, (offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { + /* Remap address to low 4K memory */ + writel(offset >> 12, mhdp->regs_sec + 8); + writel(val, (offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_NORMAL_SAPB) + writel(val, mhdp->regs_sec + offset); + else + writel(val, mhdp->regs_base + offset); + + mutex_unlock(&mhdp->iolock); +} +EXPORT_SYMBOL(cdns_mhdp_bus_write); + +void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk) +{ + cdns_mhdp_bus_write(clk / 1000000, mhdp, SW_CLK_H); +} +EXPORT_SYMBOL(cdns_mhdp_set_fw_clk); + +void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + val = DPTX_FRMR_DATA_CLK_RSTN_EN | + DPTX_FRMR_DATA_CLK_EN | + DPTX_PHY_DATA_RSTN_EN | + DPTX_PHY_DATA_CLK_EN | + DPTX_PHY_CHAR_RSTN_EN | + DPTX_PHY_CHAR_CLK_EN | + SOURCE_AUX_SYS_CLK_RSTN_EN | + SOURCE_AUX_SYS_CLK_EN | + DPTX_SYS_CLK_RSTN_EN | + DPTX_SYS_CLK_EN | + CFG_DPTX_VIF_CLK_RSTN_EN | + CFG_DPTX_VIF_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_DPTX_CAR); + + val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_PHY_CAR); + + val = SOURCE_PKT_SYS_RSTN_EN | + SOURCE_PKT_SYS_CLK_EN | + SOURCE_PKT_DATA_RSTN_EN | + SOURCE_PKT_DATA_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_PKT_CAR); + + val = SPDIF_CDR_CLK_RSTN_EN | + SPDIF_CDR_CLK_EN | + SOURCE_AIF_SYS_RSTN_EN | + SOURCE_AIF_SYS_CLK_EN | + SOURCE_AIF_CLK_RSTN_EN | + SOURCE_AIF_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_AIF_CAR); + + val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN | + SOURCE_CIPHER_SYS_CLK_EN | + SOURCE_CIPHER_CHAR_CLK_RSTN_EN | + SOURCE_CIPHER_CHAR_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_CIPHER_CAR); + + val = SOURCE_CRYPTO_SYS_CLK_RSTN_EN | + SOURCE_CRYPTO_SYS_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_CRYPTO_CAR); + + /* enable Mailbox and PIF interrupt */ + cdns_mhdp_bus_write(0, mhdp, APB_INT_MASK); +} +EXPORT_SYMBOL(cdns_mhdp_clock_reset); + +bool cdns_mhdp_check_alive(struct cdns_mhdp_device *mhdp) +{ + u32 alive, newalive; + u8 retries_left = 50; + + alive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE); + + while (retries_left--) { + msleep(1); + + newalive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE); + if (alive == newalive) + continue; + return true; + } + return false; +} +EXPORT_SYMBOL(cdns_mhdp_check_alive); + +int mhdp_mailbox_read(struct cdns_mhdp_device *mhdp) +{ + int val, ret; + + ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, MAILBOX_EMPTY_ADDR, + val, !val, MAILBOX_RETRY_US, + MAILBOX_TIMEOUT_US); + if (ret < 0) + return ret; + + return cdns_mhdp_bus_read(mhdp, MAILBOX0_RD_DATA) & 0xff; +} + +static int mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val) +{ + int ret, full; + + ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, MAILBOX_FULL_ADDR, + full, !full, MAILBOX_RETRY_US, + MAILBOX_TIMEOUT_US); + if (ret < 0) + return ret; + + cdns_mhdp_bus_write(val, mhdp, MAILBOX0_WR_DATA); + + return 0; +} + +int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp, + u8 module_id, u8 opcode, + u16 req_size) +{ + u32 mbox_size, i; + u8 header[4]; + int ret; + + /* read the header of the message */ + for (i = 0; i < 4; i++) { + ret = mhdp_mailbox_read(mhdp); + if (ret < 0) + return ret; + + header[i] = ret; + } + + mbox_size = get_unaligned_be16(header + 2); + + if (opcode != header[0] || module_id != header[1] || + req_size != mbox_size) { + DRM_DEV_INFO(mhdp->dev, + "Hmmm spurious mailbox data maybe, cleaning out...%d:%d:%d vs %d:%d:%d\n", + module_id, opcode, req_size, header[1], + header[0], mbox_size); + /* + * If the message in mailbox is not what we want, we need to + * clear the mailbox by reading its contents. + */ + for (i = 0; i < mbox_size; i++) + if (mhdp_mailbox_read(mhdp) < 0) + break; + + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_mailbox_validate_receive); + +int cdns_mhdp_mailbox_read_receive(struct cdns_mhdp_device *mhdp, + u8 *buff, u16 buff_size) +{ + u32 i; + int ret; + + for (i = 0; i < buff_size; i++) { + ret = mhdp_mailbox_read(mhdp); + if (ret < 0) + return ret; + + buff[i] = ret; + } + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_mailbox_read_receive); + +int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id, + u8 opcode, u16 size, u8 *message) +{ + u8 header[4]; + int ret, i; + + header[0] = opcode; + header[1] = module_id; + put_unaligned_be16(size, header + 2); + + for (i = 0; i < 4; i++) { + ret = mhdp_mailbox_write(mhdp, header[i]); + if (ret) + return ret; + } + + for (i = 0; i < size; i++) { + ret = mhdp_mailbox_write(mhdp, message[i]); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_mailbox_send); + +int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr) +{ + u8 msg[4], resp[8]; + u32 val; + int ret; + + mutex_lock(&mhdp->api_lock); + + if (addr == 0) { + ret = -EINVAL; + goto err_reg_read; + } + + put_unaligned_be32(addr, msg); + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_READ_REGISTER, + sizeof(msg), msg); + if (ret) + goto err_reg_read; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_READ_REGISTER, + sizeof(resp)); + if (ret) + goto err_reg_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, resp, sizeof(resp)); + if (ret) + goto err_reg_read; + + /* Returned address value should be the same as requested */ + if (memcmp(msg, resp, sizeof(msg))) { + ret = -EINVAL; + goto err_reg_read; + } + + val = get_unaligned_be32(resp + 4); + + mutex_unlock(&mhdp->api_lock); + return val; +err_reg_read: + mutex_unlock(&mhdp->api_lock); + DRM_DEV_ERROR(mhdp->dev, "Failed to read register.\n"); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_reg_read); + +int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val) +{ + int ret; + u8 msg[8]; + + mutex_lock(&mhdp->api_lock); + + put_unaligned_be32(addr, msg); + put_unaligned_be32(val, msg + 4); + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_WRITE_REGISTER, + sizeof(msg), msg); + mutex_unlock(&mhdp->api_lock); +return ret; +} +EXPORT_SYMBOL(cdns_mhdp_reg_write); + +int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr, + u8 start_bit, u8 bits_no, u32 val) +{ + int ret; + u8 field[8]; + + mutex_lock(&mhdp->api_lock); + + put_unaligned_be16(addr, field); + field[2] = start_bit; + field[3] = bits_no; + put_unaligned_be32(val, field + 4); + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_WRITE_FIELD, sizeof(field), field); + mutex_unlock(&mhdp->api_lock); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_reg_write_bit); + +int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem, + u32 i_size, const u32 *d_mem, u32 d_size) +{ + u32 reg; + int i, ret; + + /* reset ucpu before load firmware*/ + cdns_mhdp_bus_write(APB_IRAM_PATH | APB_DRAM_PATH | APB_XT_RESET, + mhdp, APB_CTRL); + + for (i = 0; i < i_size; i += 4) + cdns_mhdp_bus_write(*i_mem++, mhdp, ADDR_IMEM + i); + + for (i = 0; i < d_size; i += 4) + cdns_mhdp_bus_write(*d_mem++, mhdp, ADDR_DMEM + i); + + /* un-reset ucpu */ + cdns_mhdp_bus_write(0, mhdp, APB_CTRL); + + /* check the keep alive register to make sure fw working */ + ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, KEEP_ALIVE, + reg, reg, 2000, FW_ALIVE_TIMEOUT_US); + if (ret < 0) { + DRM_DEV_ERROR(mhdp->dev, "failed to loaded the FW reg = %x\n", + reg); + return -EINVAL; + } + + reg = cdns_mhdp_bus_read(mhdp, VER_L) & 0xff; + mhdp->fw_version = reg; + reg = cdns_mhdp_bus_read(mhdp, VER_H) & 0xff; + mhdp->fw_version |= reg << 8; + reg = cdns_mhdp_bus_read(mhdp, VER_LIB_L_ADDR) & 0xff; + mhdp->fw_version |= reg << 16; + reg = cdns_mhdp_bus_read(mhdp, VER_LIB_H_ADDR) & 0xff; + mhdp->fw_version |= reg << 24; + + DRM_DEV_DEBUG(mhdp->dev, "firmware version: %x\n", mhdp->fw_version); + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_load_firmware); + +int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable) +{ + u8 msg[5]; + int ret, i; + + mutex_lock(&mhdp->api_lock); + + msg[0] = GENERAL_MAIN_CONTROL; + msg[1] = MB_MODULE_ID_GENERAL; + msg[2] = 0; + msg[3] = 1; + msg[4] = enable ? FW_ACTIVE : FW_STANDBY; + + for (i = 0; i < sizeof(msg); i++) { + ret = mhdp_mailbox_write(mhdp, msg[i]); + if (ret) + goto err_set_firmware_active; + } + + /* read the firmware state */ + for (i = 0; i < sizeof(msg); i++) { + ret = mhdp_mailbox_read(mhdp); + if (ret < 0) + goto err_set_firmware_active; + + msg[i] = ret; + } + + ret = 0; + +err_set_firmware_active: + if (ret < 0) + DRM_DEV_ERROR(mhdp->dev, "set firmware active failed\n"); + mutex_unlock(&mhdp->api_lock); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_set_firmware_active); + +int cdns_mhdp_apb_conf(struct cdns_mhdp_device *mhdp, u8 sel) +{ + u8 status; + int ret; + + mutex_lock(&mhdp->api_lock); + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, GENERAL_BUS_SETTINGS, + sizeof(sel), &sel); + if (ret) + goto err_apb_conf; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_BUS_SETTINGS, sizeof(status)); + if (ret) + goto err_apb_conf; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status)); + if (ret) + goto err_apb_conf; + + mutex_unlock(&mhdp->api_lock); + + return status; + +err_apb_conf: + DRM_ERROR("apb conf failed: %d\n", ret); +mutex_unlock(&mhdp->api_lock); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_apb_conf); + +int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp) +{ + u8 msg[8]; + int ret, lane; + + mutex_lock(&mhdp->api_lock); + + msg[0] = drm_dp_link_rate_to_bw_code(mhdp->dp.rate); + msg[1] = mhdp->dp.num_lanes | SCRAMBLER_EN; + if (mhdp->dp.link_training_type == DP_TX_FULL_LINK_TRAINING) { + msg[2] = (VOLTAGE_LEVEL_3 & 0x3) | (mhdp->dp.force_vswing & 0x1) << 4; + msg[3] = (PRE_EMPHASIS_LEVEL_2 & 0x3) | (mhdp->dp.force_preemphasis & 0x1) << 4; + } else { + msg[2] = 0; + msg[3] = 0; + for (lane = 0; lane < mhdp->dp.num_lanes; lane++) { + msg[2] |= (mhdp->dp.vswing[lane] & 0x3) << (2 * lane); + msg[3] |= (mhdp->dp.preemphasis[lane] & 0x3) << (2 * lane); + } + } + msg[4] = PTS1 | PTS2 | PTS3 | PTS4; + msg[5] = mhdp->dp.link_training_type; + msg[6] = mhdp->lane_mapping; + msg[7] = ENHANCED; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_SET_HOST_CAPABILITIES, + sizeof(msg), msg); + if (ret) + goto err_set_host_cap; + +/* TODO Sandor */ +// ret = cdns_mhdp_reg_write(mhdp, DP_AUX_SWAP_INVERSION_CONTROL, +// AUX_HOST_INVERT); + +err_set_host_cap: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "set host cap failed: %d\n", ret); + mutex_unlock(&mhdp->api_lock); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_set_host_cap); + +int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp) +{ + u8 msg[5]; + int ret; + + mutex_lock(&mhdp->api_lock); + + memset(msg, 0, sizeof(msg)); + + msg[0] = MHDP_EVENT_ENABLE_HPD | MHDP_EVENT_ENABLE_TRAINING; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_ENABLE_EVENT, sizeof(msg), msg); + if (ret) + DRM_DEV_ERROR(mhdp->dev, "set event config failed: %d\n", ret); + + mutex_unlock(&mhdp->api_lock); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_event_config); + +u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp) +{ + return cdns_mhdp_bus_read(mhdp, SW_EVENTS0); +} +EXPORT_SYMBOL(cdns_mhdp_get_event); + +int cdns_mhdp_read_hpd(struct cdns_mhdp_device *mhdp) +{ + u8 status; + int ret; + + mutex_lock(&mhdp->api_lock); + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE, + 0, NULL); + if (ret) + goto err_get_hpd; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_GET_HPD_STATE, sizeof(status)); + if (ret) + goto err_get_hpd; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status)); + if (ret) + goto err_get_hpd; + + mutex_unlock(&mhdp->api_lock); + + return status; + +err_get_hpd: + DRM_ERROR("read hpd failed: %d\n", ret); + mutex_unlock(&mhdp->api_lock); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_read_hpd); + +int cdns_mhdp_get_edid_block(void *data, u8 *edid, + unsigned int block, size_t length) +{ + struct cdns_mhdp_device *mhdp = data; + u8 msg[2], reg[2], i; + int ret; + + mutex_lock(&mhdp->api_lock); + + for (i = 0; i < 4; i++) { + msg[0] = block / 2; + msg[1] = block % 2; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_GET_EDID, sizeof(msg), msg); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, + MB_MODULE_ID_DP_TX, + DPTX_GET_EDID, + sizeof(reg) + length); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length); + if (ret) + continue; + + if (reg[0] == length && reg[1] == block / 2) + break; + } + + if (ret) + DRM_DEV_ERROR(mhdp->dev, "get block[%d] edid failed: %d\n", + block, ret); + + mutex_unlock(&mhdp->api_lock); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_get_edid_block); + +int cdns_mhdp_set_video_status(struct cdns_mhdp_device *mhdp, int active) +{ + u8 msg; + int ret; + + mutex_lock(&mhdp->api_lock); + + msg = !!active; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_SET_VIDEO, sizeof(msg), &msg); + if (ret) + DRM_DEV_ERROR(mhdp->dev, "set video status failed: %d\n", ret); + + mutex_unlock(&mhdp->api_lock); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_set_video_status); + +int cdns_mhdp_set_maximum_defer_retry(struct cdns_mhdp_device *mhdp, + int number_of_retry) +{ + u8 msg; + int ret; + + mutex_lock(&mhdp->api_lock); + + msg = (u8)number_of_retry; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_SET_AUX_MAX_DEFER_TRIES, + sizeof(msg), &msg); + if (ret) + DRM_DEV_ERROR(mhdp->dev, + "set aux maximum defer retries failed.\n"); + + mutex_unlock(&mhdp->api_lock); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_set_maximum_defer_retry); + +static int mhdp_get_msa_misc(struct video_info *video, + struct drm_display_mode *mode) +{ + u32 msa_misc; + u8 val[2] = {0}; + + switch (video->color_fmt) { + case PXL_RGB: + case Y_ONLY: + val[0] = 0; + break; + /* set YUV default color space conversion to BT601 */ + case YCBCR_4_4_4: + val[0] = 6 + BT_601 * 8; + break; + case YCBCR_4_2_2: + val[0] = 5 + BT_601 * 8; + break; + case YCBCR_4_2_0: + val[0] = 5; + break; + } + + switch (video->color_depth) { + case 6: + val[1] = 0; + break; + case 8: + val[1] = 1; + break; + case 10: + val[1] = 2; + break; + case 12: + val[1] = 3; + break; + case 16: + val[1] = 4; + break; + } + + msa_misc = 2 * val[0] + 32 * val[1] + + ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0); + + return msa_misc; +} + +int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp) +{ + struct video_info *video = &mhdp->video_info; + struct drm_display_mode *mode = &mhdp->mode; + u64 symbol; + u32 val, link_rate, rem; + u8 bit_per_pix, tu_size_reg = TU_SIZE; + int ret; + + bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ? + (video->color_depth * 2) : (video->color_depth * 3); + + link_rate = mhdp->dp.rate / 1000; + + ret = cdns_mhdp_reg_write(mhdp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE); + if (ret) + goto err_config_video; + + ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, 0); + if (ret) + goto err_config_video; + + /* + * get a best tu_size and valid symbol: + * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32 + * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes) + * 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set + * TU += 2 and repeat 2nd step. + */ + do { + tu_size_reg += 2; + symbol = (u64) tu_size_reg * mode->clock * bit_per_pix; + do_div(symbol, mhdp->dp.num_lanes * link_rate * 8); + rem = do_div(symbol, 1000); + if (tu_size_reg > 64) { + ret = -EINVAL; + DRM_DEV_ERROR(mhdp->dev, + "tu error, clk:%d, lanes:%d, rate:%d\n", + mode->clock, mhdp->dp.num_lanes, + link_rate); + goto err_config_video; + } + } while ((symbol <= 1) || (tu_size_reg - symbol < 4) || + (rem > 850) || (rem < 100)); + + val = symbol + (tu_size_reg << 8); + val |= TU_CNT_RST_EN; + ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_TU, val); + if (ret) + goto err_config_video; + + /* set the FIFO Buffer size */ + val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate; + val /= (mhdp->dp.num_lanes * link_rate); + val = div_u64(8 * (symbol + 1), bit_per_pix) - val; + val += 2; + ret = cdns_mhdp_reg_write(mhdp, DP_VC_TABLE(15), val); + + switch (video->color_depth) { + case 6: + val = BCS_6; + break; + case 8: + val = BCS_8; + break; + case 10: + val = BCS_10; + break; + case 12: + val = BCS_12; + break; + case 16: + val = BCS_16; + break; + } + + val += video->color_fmt << 8; + ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_PXL_REPR, val); + if (ret) + goto err_config_video; + + val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0; + val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0; + ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_SP, val); + if (ret) + goto err_config_video; + + val = (mode->hsync_start - mode->hdisplay) << 16; + val |= mode->htotal - mode->hsync_end; + ret = cdns_mhdp_reg_write(mhdp, DP_FRONT_BACK_PORCH, val); + if (ret) + goto err_config_video; + + val = mode->hdisplay * bit_per_pix / 8; + ret = cdns_mhdp_reg_write(mhdp, DP_BYTE_COUNT, val); + if (ret) + goto err_config_video; + + val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16); + ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_0, val); + if (ret) + goto err_config_video; + + val = mode->hsync_end - mode->hsync_start; + val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15); + ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_1, val); + if (ret) + goto err_config_video; + + val = mode->vtotal; + val |= (mode->vtotal - mode->vsync_start) << 16; + ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_0, val); + if (ret) + goto err_config_video; + + val = mode->vsync_end - mode->vsync_start; + val |= (mode->vdisplay << 16) | (video->v_sync_polarity << 15); + ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_1, val); + if (ret) + goto err_config_video; + + val = mhdp_get_msa_misc(video, mode); + ret = cdns_mhdp_reg_write(mhdp, MSA_MISC, val); + if (ret) + goto err_config_video; + + ret = cdns_mhdp_reg_write(mhdp, STREAM_CONFIG, 1); + if (ret) + goto err_config_video; + + val = mode->hsync_end - mode->hsync_start; + val |= mode->hdisplay << 16; + ret = cdns_mhdp_reg_write(mhdp, DP_HORIZONTAL, val); + if (ret) + goto err_config_video; + + val = mode->vdisplay; + val |= (mode->vtotal - mode->vsync_start) << 16; + ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_0, val); + if (ret) + goto err_config_video; + + val = mode->vtotal; + ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_1, val); + if (ret) + goto err_config_video; + + ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 2, 1, 0); + +err_config_video: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "config video failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_config_video); + +int cdns_phy_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val) +{ + return cdns_mhdp_reg_write(mhdp, ADDR_PHY_AFE + (addr << 2), val); +} +EXPORT_SYMBOL(cdns_phy_reg_write); + +u32 cdns_phy_reg_read(struct cdns_mhdp_device *mhdp, u32 addr) +{ + return cdns_mhdp_reg_read(mhdp, ADDR_PHY_AFE + (addr << 2)); +} +EXPORT_SYMBOL(cdns_phy_reg_read); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include + +#define LINK_TRAINING_TIMEOUT_MS 500 +#define LINK_TRAINING_RETRY_MS 20 + +int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp, + u32 addr, u8 *data, u16 len) +{ + u8 msg[5], reg[5]; + int ret; + + put_unaligned_be16(len, msg); + put_unaligned_be24(addr, msg + 2); + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_DPCD, sizeof(msg), msg); + if (ret) + goto err_dpcd_read; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_DPCD, + sizeof(reg) + len); + if (ret) + goto err_dpcd_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_dpcd_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, data, len); + +err_dpcd_read: + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_dpcd_read); + +int cdns_mhdp_i2c_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data, + u16 len, u8 mot, u16 *respLength) +{ + u8 msg[5], reg[3]; + int ret; + + put_unaligned_be16(len, msg); + msg[2] = addr; + msg[3] = mot; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_I2C_READ, sizeof(msg), msg); + if (ret) + goto err_i2c_read; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_I2C_READ, + sizeof(reg) + len); + if (ret) + goto err_i2c_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_i2c_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, data, len); + *respLength = (reg[0] << 8u) + reg[1]; + +err_i2c_read: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "i2c read failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_i2c_read); + +int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value) +{ + u8 msg[6], reg[5]; + int ret; + + put_unaligned_be16(1, msg); + put_unaligned_be24(addr, msg + 2); + msg[5] = value; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_WRITE_DPCD, sizeof(msg), msg); + if (ret) + goto err_dpcd_write; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_WRITE_DPCD, sizeof(reg)); + if (ret) + goto err_dpcd_write; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_dpcd_write; + + if (addr != get_unaligned_be24(reg + 2)) + ret = -EINVAL; + +err_dpcd_write: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "dpcd write failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_dpcd_write); + +int cdns_mhdp_i2c_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 *value, + u8 mot, u16 len, u16 *respLength) +{ + u8 msg[4+DP_AUX_MAX_PAYLOAD_BYTES], reg[3]; + int ret; + + put_unaligned_be16(len, msg); + msg[2] = addr; + msg[3] = mot; + memcpy(&msg[4], value, len); + + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_I2C_WRITE, sizeof(msg), msg); + if (ret) + goto err_i2c_write; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_I2C_WRITE, sizeof(reg)); + if (ret) + goto err_i2c_write; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_i2c_write; + + if (addr != reg[2]) + ret = -EINVAL; + + *respLength = (reg[0]<<8u) + reg[1]; + +err_i2c_write: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "i2c write failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_i2c_write); + + +int cdns_mhdp_get_last_i2c_status(struct cdns_mhdp_device *mhdp, u8 *resp) +{ + u8 status[1]; + int ret; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_GET_LAST_I2C_STATUS, 0, NULL); + if (ret) + goto err_get_i2c_status; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_GET_LAST_I2C_STATUS, + sizeof(status)); + if (ret) + goto err_get_i2c_status; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, status, sizeof(status)); + if (ret) + goto err_get_i2c_status; + + *resp = status[0]; + +err_get_i2c_status: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "get i2c status failed: %d\n", + ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_get_last_i2c_status); + +static int cdns_mhdp_training_start(struct cdns_mhdp_device *mhdp) +{ + unsigned long timeout; + u8 msg, event[2]; + int ret; + + msg = LINK_TRAINING_RUN; + + /* start training */ + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_TRAINING_CONTROL, sizeof(msg), &msg); + if (ret) + goto err_training_start; + + timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS); + while (time_before(jiffies, timeout)) { + msleep(LINK_TRAINING_RETRY_MS); + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_EVENT, 0, NULL); + if (ret) + goto err_training_start; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, + MB_MODULE_ID_DP_TX, + DPTX_READ_EVENT, + sizeof(event)); + if (ret) + goto err_training_start; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, event, + sizeof(event)); + if (ret) + goto err_training_start; + + if (event[1] & CLK_RECOVERY_FAILED) + DRM_DEV_ERROR(mhdp->dev, "clock recovery failed\n"); + else if (event[1] & EQ_PHASE_FINISHED) + return 0; + } + + ret = -ETIMEDOUT; + +err_training_start: + DRM_DEV_ERROR(mhdp->dev, "training failed: %d\n", ret); + return ret; +} + +static int cdns_mhdp_get_training_status(struct cdns_mhdp_device *mhdp) +{ + u8 status[13]; + int ret; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_LINK_STAT, 0, NULL); + if (ret) + goto err_get_training_status; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_LINK_STAT, + sizeof(status)); + if (ret) + goto err_get_training_status; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, status, sizeof(status)); + if (ret) + goto err_get_training_status; + + mhdp->dp.rate = drm_dp_bw_code_to_link_rate(status[0]); + mhdp->dp.num_lanes = status[1]; + +err_get_training_status: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "get training status failed: %d\n", + ret); + return ret; +} + +int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = cdns_mhdp_training_start(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to start training %d\n", + ret); + return ret; + } + + ret = cdns_mhdp_get_training_status(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to get training stat %d\n", + ret); + return ret; + } + + DRM_DEV_DEBUG_KMS(mhdp->dev, "rate:0x%x, lanes:%d\n", mhdp->dp.rate, + mhdp->dp.num_lanes); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_train_link); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Cadence MHDP DP MST bridge driver. + * + * Copyright: 2018 Cadence Design Systems, Inc. + * + * Author: Quentin Schulz + */ + + +#ifndef CDNS_MHDP_H +#define CDNS_MHDP_H + +#include + +#define CDNS_APB_CFG 0x00000 +#define CDNS_APB_CTRL (CDNS_APB_CFG + 0x00) +#define CDNS_MAILBOX_FULL (CDNS_APB_CFG + 0x08) +#define CDNS_MAILBOX_EMPTY (CDNS_APB_CFG + 0x0c) +#define CDNS_MAILBOX_TX_DATA (CDNS_APB_CFG + 0x10) +#define CDNS_MAILBOX_RX_DATA (CDNS_APB_CFG + 0x14) +#define CDNS_KEEP_ALIVE (CDNS_APB_CFG + 0x18) +#define CDNS_KEEP_ALIVE_MASK GENMASK(7, 0) + +#define CDNS_MB_INT_MASK (CDNS_APB_CFG + 0x34) + +#define CDNS_SW_CLK_L (CDNS_APB_CFG + 0x3c) +#define CDNS_SW_CLK_H (CDNS_APB_CFG + 0x40) +#define CDNS_SW_EVENT0 (CDNS_APB_CFG + 0x44) +#define CDNS_DPTX_HPD BIT(0) + +#define CDNS_SW_EVENT1 (CDNS_APB_CFG + 0x48) +#define CDNS_SW_EVENT2 (CDNS_APB_CFG + 0x4c) +#define CDNS_SW_EVENT3 (CDNS_APB_CFG + 0x50) + +#define CDNS_APB_INT_MASK (CDNS_APB_CFG + 0x6C) +#define CDNS_APB_INT_MASK_MAILBOX_INT BIT(0) +#define CDNS_APB_INT_MASK_SW_EVENT_INT BIT(1) + +#define CDNS_DPTX_CAR (CDNS_APB_CFG + 0x904) +#define CDNS_VIF_CLK_EN BIT(0) +#define CDNS_VIF_CLK_RSTN BIT(1) + +#define CDNS_SOURCE_VIDEO_IF(s) (0x00b00 + (s * 0x20)) +#define CDNS_BND_HSYNC2VSYNC(s) (CDNS_SOURCE_VIDEO_IF(s) + \ + 0x00) +#define CDNS_IP_DTCT_WIN GENMASK(11, 0) +#define CDNS_IP_DET_INTERLACE_FORMAT BIT(12) +#define CDNS_IP_BYPASS_V_INTERFACE BIT(13) + +#define CDNS_HSYNC2VSYNC_POL_CTRL(s) (CDNS_SOURCE_VIDEO_IF(s) + \ + 0x10) +#define CDNS_H2V_HSYNC_POL_ACTIVE_LOW BIT(1) +#define CDNS_H2V_VSYNC_POL_ACTIVE_LOW BIT(2) + +#define CDNS_DPTX_PHY_CONFIG 0x02000 +#define CDNS_PHY_TRAINING_EN BIT(0) +#define CDNS_PHY_TRAINING_TYPE(x) (((x) & GENMASK(3, 0)) << 1) +#define CDNS_PHY_SCRAMBLER_BYPASS BIT(5) +#define CDNS_PHY_ENCODER_BYPASS BIT(6) +#define CDNS_PHY_SKEW_BYPASS BIT(7) +#define CDNS_PHY_TRAINING_AUTO BIT(8) +#define CDNS_PHY_LANE0_SKEW(x) (((x) & GENMASK(2, 0)) << 9) +#define CDNS_PHY_LANE1_SKEW(x) (((x) & GENMASK(2, 0)) << 12) +#define CDNS_PHY_LANE2_SKEW(x) (((x) & GENMASK(2, 0)) << 15) +#define CDNS_PHY_LANE3_SKEW(x) (((x) & GENMASK(2, 0)) << 18) +#define CDNS_PHY_COMMON_CONFIG (CDNS_PHY_LANE1_SKEW(1) | \ + CDNS_PHY_LANE2_SKEW(2) | \ + CDNS_PHY_LANE3_SKEW(3)) +#define CDNS_PHY_10BIT_EN BIT(21) + +#define CDNS_DPTX_FRAMER 0x02200 +#define CDNS_DP_FRAMER_GLOBAL_CONFIG (CDNS_DPTX_FRAMER + 0x00) +#define CDNS_DP_NUM_LANES(x) (x - 1) +#define CDNS_DP_MST_EN BIT(2) +#define CDNS_DP_FRAMER_EN BIT(3) +#define CDNS_DP_RATE_GOVERNOR_EN BIT(4) +#define CDNS_DP_NO_VIDEO_MODE BIT(5) +#define CDNS_DP_DISABLE_PHY_RST BIT(6) +#define CDNS_DP_WR_FAILING_EDGE_VSYNC BIT(7) + +#define CDNS_DP_SW_RESET (CDNS_DPTX_FRAMER + 0x04) +#define CDNS_DP_FRAMER_TU (CDNS_DPTX_FRAMER + 0x08) +#define CDNS_DP_FRAMER_TU_SIZE(x) (((x) & GENMASK(6, 0)) << 8) +#define CDNS_DP_FRAMER_TU_VS(x) ((x) & GENMASK(5, 0)) +#define CDNS_DP_FRAMER_TU_CNT_RST_EN BIT(15) + +#define CDNS_DPTX_STREAM(s) (0x03000 + s * 0x80) +#define CDNS_DP_MSA_HORIZONTAL_0(s) (CDNS_DPTX_STREAM(s) + 0x00) +#define CDNS_DP_MSAH0_H_TOTAL(x) (x) +#define CDNS_DP_MSAH0_HSYNC_START(x) ((x) << 16) + +#define CDNS_DP_MSA_HORIZONTAL_1(s) (CDNS_DPTX_STREAM(s) + 0x04) +#define CDNS_DP_MSAH1_HSYNC_WIDTH(x) (x) +#define CDNS_DP_MSAH1_HSYNC_POL_LOW BIT(15) +#define CDNS_DP_MSAH1_HDISP_WIDTH(x) ((x) << 16) + +#define CDNS_DP_MSA_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x08) +#define CDNS_DP_MSAV0_V_TOTAL(x) (x) +#define CDNS_DP_MSAV0_VSYNC_START(x) ((x) << 16) + +#define CDNS_DP_MSA_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x0c) +#define CDNS_DP_MSAV1_VSYNC_WIDTH(x) (x) +#define CDNS_DP_MSAV1_VSYNC_POL_LOW BIT(15) +#define CDNS_DP_MSAV1_VDISP_WIDTH(x) ((x) << 16) + +#define CDNS_DP_MSA_MISC(s) (CDNS_DPTX_STREAM(s) + 0x10) +#define CDNS_DP_STREAM_CONFIGs(s) (CDNS_DPTX_STREAM(s) + 0x14) +#define CDNS_DP_STREAM_CONFIG_2(s) (CDNS_DPTX_STREAM(s) + 0x2c) +#define CDNS_DP_SC2_TU_VS_DIFF(x) ((x) << 8) + +#define CDNS_DP_HORIZONTAL(s) (CDNS_DPTX_STREAM(s) + 0x30) +#define CDNS_DP_H_HSYNC_WIDTH(x) (x) +#define CDNS_DP_H_H_TOTAL(x) ((x) << 16) + +#define CDNS_DP_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x34) +#define CDNS_DP_V0_VHEIGHT(x) (x) +#define CDNS_DP_V0_VSTART(x) ((x) << 16) + +#define CDNS_DP_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x38) +#define CDNS_DP_V1_VTOTAL(x) (x) +#define CDNS_DP_V1_VTOTAL_EVEN BIT(16) + +#define CDNS_DP_FRAMER_PXL_REPR(s) (CDNS_DPTX_STREAM(s) + 0x4c) +#define CDNS_DP_FRAMER_6_BPC BIT(0) +#define CDNS_DP_FRAMER_8_BPC BIT(1) +#define CDNS_DP_FRAMER_10_BPC BIT(2) +#define CDNS_DP_FRAMER_12_BPC BIT(3) +#define CDNS_DP_FRAMER_16_BPC BIT(4) +#define CDNS_DP_FRAMER_PXL_FORMAT 0x8 +#define CDNS_DP_FRAMER_RGB BIT(0) +#define CDNS_DP_FRAMER_YCBCR444 BIT(1) +#define CDNS_DP_FRAMER_YCBCR422 BIT(2) +#define CDNS_DP_FRAMER_YCBCR420 BIT(3) +#define CDNS_DP_FRAMER_Y_ONLY BIT(4) + +#define CDNS_DP_FRAMER_SP(s) (CDNS_DPTX_STREAM(s) + 0x10) +#define CDNS_DP_FRAMER_VSYNC_POL_LOW BIT(0) +#define CDNS_DP_FRAMER_HSYNC_POL_LOW BIT(1) +#define CDNS_DP_FRAMER_INTERLACE BIT(2) + +#define CDNS_DP_LINE_THRESH(s) (CDNS_DPTX_STREAM(s) + 0x64) +#define CDNS_DP_ACTIVE_LINE_THRESH(x) (x) + +#define CDNS_DP_VB_ID(s) (CDNS_DPTX_STREAM(s) + 0x68) +#define CDNS_DP_VB_ID_INTERLACED BIT(2) +#define CDNS_DP_VB_ID_COMPRESSED BIT(6) + +#define CDNS_DP_FRONT_BACK_PORCH(s) (CDNS_DPTX_STREAM(s) + 0x78) +#define CDNS_DP_BACK_PORCH(x) (x) +#define CDNS_DP_FRONT_PORCH(x) ((x) << 16) + +#define CDNS_DP_BYTE_COUNT(s) (CDNS_DPTX_STREAM(s) + 0x7c) +#define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT 16 + +#define CDNS_DP_MST_STREAM_CONFIG(s) (CDNS_DPTX_STREAM(s) + 0x14) +#define CDNS_DP_MST_STRM_CFG_STREAM_EN BIT(0) +#define CDNS_DP_MST_STRM_CFG_NO_VIDEO BIT(1) + +#define CDNS_DP_MST_SLOT_ALLOCATE(s) (CDNS_DPTX_STREAM(s) + 0x44) +#define CDNS_DP_S_ALLOC_START_SLOT(x) (x) +#define CDNS_DP_S_ALLOC_END_SLOT(x) ((x) << 8) + +#define CDNS_DP_RATE_GOVERNING(s) (CDNS_DPTX_STREAM(s) + 0x48) +#define CDNS_DP_RG_TARG_AV_SLOTS_Y(x) (x) +#define CDNS_DP_RG_TARG_AV_SLOTS_X(x) (x << 4) +#define CDNS_DP_RG_ENABLE BIT(10) + +#define CDNS_DP_MTPH_CONTROL 0x2264 +#define CDNS_DP_MTPH_ECF_EN BIT(0) +#define CDNS_DP_MTPH_ACT_EN BIT(1) +#define CDNS_DP_MTPH_LVP_EN BIT(2) + +#define CDNS_DP_MTPH_STATUS 0x226C +#define CDNS_DP_MTPH_ACT_STATUS BIT(0) + +#define CDNS_DPTX_GLOBAL 0x02300 +#define CDNS_DP_LANE_EN (CDNS_DPTX_GLOBAL + 0x00) +#define CDNS_DP_LANE_EN_LANES(x) GENMASK(x - 1, 0) +#define CDNS_DP_ENHNCD (CDNS_DPTX_GLOBAL + 0x04) + + +#define to_mhdp_connector(x) container_of(x, struct cdns_mhdp_connector, base) +#define to_mhdp_bridge(x) container_of(x, struct cdns_mhdp_bridge, base) +#define mgr_to_mhdp(x) container_of(x, struct cdns_mhdp_device, mst_mgr) + +#define CDNS_MHDP_MAX_STREAMS 4 + +#define MAILBOX_RETRY_US 1000 +#define MAILBOX_TIMEOUT_US 5000000 + +#define mhdp_readx_poll_timeout(op, addr, offset, val, cond, sleep_us, timeout_us) \ +({ \ + u64 __timeout_us = (timeout_us); \ + unsigned long __sleep_us = (sleep_us); \ + ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \ + might_sleep_if((__sleep_us) != 0); \ + for (;;) { \ + (val) = op(addr, offset); \ + if (cond) \ + break; \ + if (__timeout_us && \ + ktime_compare(ktime_get(), __timeout) > 0) { \ + (val) = op(addr, offset); \ + break; \ + } \ + if (__sleep_us) \ + usleep_range((__sleep_us >> 2) + 1, __sleep_us); \ + } \ + (cond) ? 0 : -ETIMEDOUT; \ +}) + +enum pixel_format { + PIXEL_FORMAT_RGB = 1, + PIXEL_FORMAT_YCBCR_444 = 2, + PIXEL_FORMAT_YCBCR_422 = 4, + PIXEL_FORMAT_YCBCR_420 = 8, + PIXEL_FORMAT_Y_ONLY = 16, +}; + + +int cdns_mhdp_mst_init(struct cdns_mhdp_device *mhdp); +void cdns_mhdp_mst_deinit(struct cdns_mhdp_device *mhdp); +bool cdns_mhdp_mst_probe(struct cdns_mhdp_device *mhdp); +enum pixel_format cdns_mhdp_get_pxlfmt(u32 color_formats); +u32 cdns_mhdp_get_bpp(u32 bpc, u32 color_formats); +void cdns_mhdp_configure_video(struct drm_bridge *bridge); +void cdns_mhdp_mst_enable(struct drm_bridge *bridge); +void cdns_mhdp_mst_disable(struct drm_bridge *bridge); +void cdns_mhdp_enable(struct drm_bridge *bridge); + +#endif diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.c linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.c --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.c 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,350 @@ +/* + * Cadence HDCP API driver + * + * Copyright 2021 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include + +#include "cdns-mhdp.h" + +static u32 mhdp_hdcp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset) +{ + u32 val; + + mutex_lock(&mhdp->iolock); + + if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { + /* Remap address to low 4K APB bus */ + writel(offset >> 12, mhdp->regs_sec + 8); + val = readl((offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_NORMAL_APB) + val = readl(mhdp->regs_sec + offset); + else + val = readl(mhdp->regs_base + offset); + + mutex_unlock(&mhdp->iolock); + + return val; +} + +static void mhdp_hdcp_bus_write(u32 val, struct cdns_mhdp_device *mhdp, u32 offset) +{ + mutex_lock(&mhdp->iolock); + + if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { + /* Remap address to low 4K APB bus */ + writel(offset >> 12, mhdp->regs_sec + 8); + writel(val, (offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_NORMAL_APB) + writel(val, mhdp->regs_sec + offset); + + mutex_unlock(&mhdp->iolock); +} + +static int mhdp_hdcp_mailbox_read(struct cdns_mhdp_device *mhdp) +{ + int val, ret; + + ret = mhdp_readx_poll_timeout(mhdp_hdcp_bus_read, mhdp, MAILBOX_EMPTY_ADDR, + val, !val, MAILBOX_RETRY_US, + MAILBOX_TIMEOUT_US); + if (ret < 0) + return ret; + + return mhdp_hdcp_bus_read(mhdp, MAILBOX0_RD_DATA) & 0xff; +} + +static int mhdp_hdcp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val) +{ + int ret, full; + + ret = mhdp_readx_poll_timeout(mhdp_hdcp_bus_read, mhdp, MAILBOX_FULL_ADDR, + full, !full, MAILBOX_RETRY_US, + MAILBOX_TIMEOUT_US); + if (ret < 0) + return ret; + + mhdp_hdcp_bus_write(val, mhdp, MAILBOX0_WR_DATA); + + return 0; +} + +static int mhdp_hdcp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp, + u8 module_id, u8 opcode, u16 req_size) +{ + u32 mbox_size, i; + u8 header[4]; + int ret; + + /* read the header of the message */ + for (i = 0; i < 4; i++) { + ret = mhdp_hdcp_mailbox_read(mhdp); + if (ret < 0) + return ret; + + header[i] = ret; + } + + mbox_size = get_unaligned_be16(header + 2); + + if (opcode != header[0] || module_id != header[1] || + req_size != mbox_size) { + /* + * If the message in mailbox is not what we want, we need to + * clear the mailbox by reading its contents. + */ + for (i = 0; i < mbox_size; i++) + if (mhdp_hdcp_mailbox_read(mhdp) < 0) + break; + + return -EINVAL; + } + + return 0; +} + +static int mhdp_hdcp_mailbox_read_receive(struct cdns_mhdp_device *mhdp, + u8 *buff, u16 buff_size) +{ + u32 i; + int ret; + + for (i = 0; i < buff_size; i++) { + ret = mhdp_hdcp_mailbox_read(mhdp); + if (ret < 0) + return ret; + + buff[i] = ret; + } + + return 0; +} + +static int mhdp_hdcp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id, + u8 opcode, u16 size, u8 *message) +{ + u8 header[4]; + int ret, i; + + header[0] = opcode; + header[1] = module_id; + put_unaligned_be16(size, header + 2); + + for (i = 0; i < 4; i++) { + ret = mhdp_hdcp_mailbox_write(mhdp, header[i]); + if (ret) + return ret; + } + + for (i = 0; i < size; i++) { + ret = mhdp_hdcp_mailbox_write(mhdp, message[i]); + if (ret) + return ret; + } + + return 0; +} + +/* HDCP API */ +int cdns_mhdp_hdcp_tx_config(struct cdns_mhdp_device *mhdp, u8 config) +{ + int ret; + + mutex_lock(&mhdp->api_lock); + ret = mhdp_hdcp_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TX_CONFIGURATION, sizeof(config), &config); + + mutex_unlock(&mhdp->api_lock); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_hdcp_tx_config); + +int cdns_mhdp_hdcp2_tx_respond_km(struct cdns_mhdp_device *mhdp, + u8 *msg, u16 len) +{ + int ret; + + mutex_lock(&mhdp->api_lock); + + ret = mhdp_hdcp_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP2_TX_RESPOND_KM, len, msg); + mutex_unlock(&mhdp->api_lock); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_hdcp2_tx_respond_km); + +int cdns_mhdp_hdcp_tx_status_req(struct cdns_mhdp_device *mhdp, + u8 *status, u16 len) +{ + int ret; + + mutex_lock(&mhdp->api_lock); + + ret = mhdp_hdcp_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TX_STATUS_CHANGE, 0, NULL); + if (ret) + goto err_tx_req; + + ret = mhdp_hdcp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TX_STATUS_CHANGE, len); + if (ret) + goto err_tx_req; + + ret = mhdp_hdcp_mailbox_read_receive(mhdp, status, len); + if (ret) + goto err_tx_req; + +err_tx_req: + if (ret) + DRM_ERROR("hdcp tx status req failed: %d\n", ret); + mutex_unlock(&mhdp->api_lock); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_hdcp_tx_status_req); + +int cdns_mhdp_hdcp2_tx_is_km_stored_req(struct cdns_mhdp_device *mhdp, u8 *data, u16 len) +{ + int ret; + + mutex_lock(&mhdp->api_lock); + + ret = mhdp_hdcp_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP2_TX_IS_KM_STORED, 0, NULL); + if (ret) + goto err_is_km; + + ret = mhdp_hdcp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP2_TX_IS_KM_STORED, len); + if (ret) + goto err_is_km; + + ret = mhdp_hdcp_mailbox_read_receive(mhdp, data, len); + +err_is_km: + if (ret) + DRM_ERROR("hdcp2 tx is km stored req failed: %d\n", ret); + mutex_unlock(&mhdp->api_lock); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_hdcp2_tx_is_km_stored_req); + +int cdns_mhdp_hdcp2_tx_store_km(struct cdns_mhdp_device *mhdp, + u8 *resp, u16 len) +{ + int ret; + + mutex_lock(&mhdp->api_lock); + + ret = mhdp_hdcp_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP2_TX_STORE_KM, 0, NULL); + if (ret) + goto err_store_km; + + ret = mhdp_hdcp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP2_TX_STORE_KM, len); + if (ret) + goto err_store_km; + + ret = mhdp_hdcp_mailbox_read_receive(mhdp, resp, len); + +err_store_km: + mutex_unlock(&mhdp->api_lock); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_hdcp2_tx_store_km); + +int cdns_mhdp_hdcp_tx_is_receiver_id_valid(struct cdns_mhdp_device *mhdp, + u8 *rx_id, u8 *num) +{ + u32 mbox_size, i; + u8 header[4]; + u8 temp; + int ret; + + mutex_lock(&mhdp->api_lock); + + ret = mhdp_hdcp_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TX_IS_RECEIVER_ID_VALID, 0, NULL); + if (ret) + goto err_rx_id; + + /* read the header of the message */ + for (i = 0; i < 4; i++) { + ret = mhdp_hdcp_mailbox_read(mhdp); + if (ret < 0) { + + mutex_unlock(&mhdp->api_lock); + return ret; + } + + header[i] = ret; + } + + mbox_size = get_unaligned_be16(header + 2); + + if (header[0] != HDCP_TX_IS_RECEIVER_ID_VALID || + header[1] != MB_MODULE_ID_HDCP_TX){ + + mutex_unlock(&mhdp->api_lock); + return -EINVAL; + } + /* First get num of receivers */ + ret = mhdp_hdcp_mailbox_read_receive(mhdp, num, 1); + if (ret) + goto err_rx_id; + + /* skip second data */ + ret = mhdp_hdcp_mailbox_read_receive(mhdp, &temp, 1); + if (ret) + goto err_rx_id; + + /* get receivers ID */ + ret = mhdp_hdcp_mailbox_read_receive(mhdp, rx_id, mbox_size - 2); + +err_rx_id: + mutex_unlock(&mhdp->api_lock); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_hdcp_tx_is_receiver_id_valid); + +int cdns_mhdp_hdcp_tx_respond_receiver_id_valid( + struct cdns_mhdp_device *mhdp, u8 val) +{ + int ret; + + mutex_lock(&mhdp->api_lock); + + ret = mhdp_hdcp_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TX_RESPOND_RECEIVER_ID_VALID, + sizeof(val), &val); + mutex_unlock(&mhdp->api_lock); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_hdcp_tx_respond_receiver_id_valid); + +int cdns_mhdp_hdcp_tx_reauth(struct cdns_mhdp_device *mhdp, u8 msg) +{ + int ret; + + mutex_lock(&mhdp->api_lock); + + ret = mhdp_hdcp_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TX_DO_AUTH_REQ, sizeof(msg), &msg); + + mutex_unlock(&mhdp->api_lock); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_hdcp_tx_reauth); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.h linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.h --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.h 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,29 @@ +/* + * Copyright 2021 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef CDNS_HDMI_HDCP_H +#define CDNS_HDMI_HDCP_H + +int cdns_mhdp_hdcp2_tx_respond_km(struct cdns_mhdp_device *mhdp, + u8 *msg, u16 len); +int cdns_mhdp_hdcp_tx_config(struct cdns_mhdp_device *mhdp, u8 config); +int cdns_mhdp_hdcp_tx_status_req(struct cdns_mhdp_device *mhdp, + u8 *status, u16 len); +int cdns_mhdp_hdcp2_tx_is_km_stored_req(struct cdns_mhdp_device *mhdp, u8 *data, u16 len); +int cdns_mhdp_hdcp2_tx_store_km(struct cdns_mhdp_device *mhdp, + u8 *reg, u16 len); +int cdns_mhdp_hdcp_tx_is_receiver_id_valid(struct cdns_mhdp_device *mhdp, + u8 *rx_id, u8 *num); +int cdns_mhdp_hdcp_tx_respond_receiver_id_valid(struct cdns_mhdp_device *mhdp, + u8 val); +int cdns_mhdp_hdcp_tx_test_keys(struct cdns_mhdp_device *mhdp, u8 type, u8 resp); +int cdns_mhdp_hdcp_tx_reauth(struct cdns_mhdp_device *mhdp, u8 msg); + +#endif /* CDNS_HDMI_HDCP_H */ diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c 2024-06-19 12:34:01.892253989 +0200 @@ -0,0 +1,342 @@ +/* + * Copyright 2019-2021 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +void cdns_mhdp_infoframe_set(struct cdns_mhdp_device *mhdp, + u8 entry_id, u8 packet_len, u8 *packet, u8 packet_type) +{ + u32 *packet32, len32; + u32 val, i; + + /* invalidate entry */ + val = F_ACTIVE_IDLE_TYPE(1) | F_PKT_ALLOC_ADDRESS(entry_id); + cdns_mhdp_bus_write(val, mhdp, SOURCE_PIF_PKT_ALLOC_REG); + cdns_mhdp_bus_write(F_PKT_ALLOC_WR_EN(1), mhdp, SOURCE_PIF_PKT_ALLOC_WR_EN); + + /* flush fifo 1 */ + cdns_mhdp_bus_write(F_FIFO1_FLUSH(1), mhdp, SOURCE_PIF_FIFO1_FLUSH); + + /* write packet into memory */ + packet32 = (u32 *)packet; + len32 = packet_len / 4; + for (i = 0; i < len32; i++) + cdns_mhdp_bus_write(F_DATA_WR(packet32[i]), mhdp, SOURCE_PIF_DATA_WR); + + /* write entry id */ + cdns_mhdp_bus_write(F_WR_ADDR(entry_id), mhdp, SOURCE_PIF_WR_ADDR); + + /* write request */ + cdns_mhdp_bus_write(F_HOST_WR(1), mhdp, SOURCE_PIF_WR_REQ); + + /* update entry */ + val = F_ACTIVE_IDLE_TYPE(1) | F_TYPE_VALID(1) | + F_PACKET_TYPE(packet_type) | F_PKT_ALLOC_ADDRESS(entry_id); + cdns_mhdp_bus_write(val, mhdp, SOURCE_PIF_PKT_ALLOC_REG); + + cdns_mhdp_bus_write(F_PKT_ALLOC_WR_EN(1), mhdp, SOURCE_PIF_PKT_ALLOC_WR_EN); +} + +int cdns_hdmi_get_edid_block(void *data, u8 *edid, + u32 block, size_t length) +{ + struct cdns_mhdp_device *mhdp = data; + u8 msg[2], reg[5], i; + int ret; + + mutex_lock(&mhdp->api_lock); + + for (i = 0; i < 4; i++) { + msg[0] = block / 2; + msg[1] = block % 2; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID, + sizeof(msg), msg); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, + HDMI_TX_EDID, sizeof(reg) + length); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length); + if (ret) + continue; + + if ((reg[3] << 8 | reg[4]) == length) + break; + } + + mutex_unlock(&mhdp->api_lock); + + if (ret) + DRM_ERROR("get block[%d] edid failed: %d\n", block, ret); + return ret; +} + +int cdns_hdmi_scdc_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data) +{ + u8 msg[4], reg[6]; + int ret; + + mutex_lock(&mhdp->api_lock); + + msg[0] = 0x54; + msg[1] = addr; + msg[2] = 0; + msg[3] = 1; + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_READ, + sizeof(msg), msg); + if (ret) + goto err_scdc_read; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, + HDMI_TX_READ, sizeof(reg)); + if (ret) + goto err_scdc_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_scdc_read; + + *data = reg[5]; + +err_scdc_read: + mutex_unlock(&mhdp->api_lock); + if (ret) + DRM_ERROR("scdc read failed: %d\n", ret); + return ret; +} + +int cdns_hdmi_scdc_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 value) +{ + u8 msg[5], reg[5]; + int ret; + + mutex_lock(&mhdp->api_lock); + + msg[0] = 0x54; + msg[1] = addr; + msg[2] = 0; + msg[3] = 1; + msg[4] = value; + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE, + sizeof(msg), msg); + if (ret) + goto err_scdc_write; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, + HDMI_TX_WRITE, sizeof(reg)); + if (ret) + goto err_scdc_write; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_scdc_write; + + if (reg[0] != 0) + ret = -EINVAL; + +err_scdc_write: + mutex_unlock(&mhdp->api_lock); + if (ret) + DRM_ERROR("scdc write failed: %d\n", ret); + return ret; +} + +int cdns_hdmi_ctrl_init(struct cdns_mhdp_device *mhdp, + int protocol, + u32 char_rate) +{ + u32 reg0; + u32 reg1; + u32 val; + int ret; + + /* Set PHY to HDMI data */ + ret = cdns_mhdp_reg_write(mhdp, PHY_DATA_SEL, F_SOURCE_PHY_MHDP_SEL(1)); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_HPD, + F_HPD_VALID_WIDTH(4) | F_HPD_GLITCH_WIDTH(0)); + if (ret < 0) + return ret; + + /* open CARS */ + ret = cdns_mhdp_reg_write(mhdp, SOURCE_PHY_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, 0xFF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_PKT_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_AIF_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_CIPHER_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_CRYPTO_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_CEC_CAR, 3); + if (ret < 0) + return ret; + + reg0 = reg1 = 0x7c1f; + if (protocol == MODE_HDMI_2_0 && char_rate >= 340000) { + reg0 = 0; + reg1 = 0xFFFFF; + } + ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_0, reg0); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_1, reg1); + if (ret < 0) + return ret; + + /* set hdmi mode and preemble mode data enable */ + val = F_HDMI_MODE(protocol) | F_HDMI2_PREAMBLE_EN(1) | F_DATA_EN(1) | + F_HDMI2_CTRL_IL_MODE(1) | F_BCH_EN(1) | F_PIC_3D(0XF) | F_CLEAR_AVMUTE(1); + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + + return ret; +} + +int cdns_hdmi_mode_config(struct cdns_mhdp_device *mhdp, + struct drm_display_mode *mode, + struct video_info *video_info) +{ + int ret; + u32 val; + u32 vsync_lines = mode->vsync_end - mode->vsync_start; + u32 eof_lines = mode->vsync_start - mode->vdisplay; + u32 sof_lines = mode->vtotal - mode->vsync_end; + u32 hblank = mode->htotal - mode->hdisplay; + u32 hactive = mode->hdisplay; + u32 vblank = mode->vtotal - mode->vdisplay; + u32 vactive = mode->vdisplay; + u32 hfront = mode->hsync_start - mode->hdisplay; + u32 hback = mode->htotal - mode->hsync_end; + u32 vfront = eof_lines; + u32 hsync = hblank - hfront - hback; + u32 vsync = vsync_lines; + u32 vback = sof_lines; + u32 v_h_polarity = ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1) + + ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : 2); + + ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_H_SIZE, (hactive << 16) + hblank); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_V_SIZE, (vactive << 16) + vblank); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_FRONT_WIDTH, (vfront << 16) + hfront); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_SYNC_WIDTH, (vsync << 16) + hsync); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_BACK_WIDTH, (vback << 16) + hback); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, v_h_polarity); + if (ret < 0) + return ret; + + /* Reset Data Enable */ + val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); + val &= ~F_DATA_EN(1); + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + if (ret < 0) + return ret; + + /* Set bpc */ + val &= ~F_VIF_DATA_WIDTH(3); + switch (video_info->color_depth) { + case 10: + val |= F_VIF_DATA_WIDTH(1); + break; + case 12: + val |= F_VIF_DATA_WIDTH(2); + break; + case 16: + val |= F_VIF_DATA_WIDTH(3); + break; + case 8: + default: + val |= F_VIF_DATA_WIDTH(0); + break; + } + + /* select color encoding */ + val &= ~F_HDMI_ENCODING(3); + switch (video_info->color_fmt) { + case YCBCR_4_4_4: + val |= F_HDMI_ENCODING(2); + break; + case YCBCR_4_2_2: + val |= F_HDMI_ENCODING(1); + break; + case YCBCR_4_2_0: + val |= F_HDMI_ENCODING(3); + break; + case PXL_RGB: + default: + val |= F_HDMI_ENCODING(0); + break; + } + + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + if (ret < 0) + return ret; + + /* set data enable */ + val |= F_DATA_EN(1); + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + + return ret; +} + +int cdns_hdmi_disable_gcp(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); + val &= ~F_GCP_EN(1); + + return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); +} + +int cdns_hdmi_enable_gcp(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); + val |= F_GCP_EN(1); + + return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); +} diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/Kconfig linux-imx-phytec/drivers/gpu/drm/bridge/cadence/Kconfig --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/Kconfig 2024-06-19 12:34:01.892253989 +0200 @@ -25,3 +25,39 @@ initializes the J721E Display Port and sets up the clock and data muxes. endif + +config DRM_CDNS_MHDP + tristate "Cadence MHDP COMMON API driver" + select DRM_DISPLAY_DP_HELPER + select DRM_DISPLAY_HELPER + select DRM_DISPLAY_HDCP_HELPER + select DRM_KMS_HELPER + select DRM_PANEL_BRIDGE + depends on OF + help + Support Cadence MHDP API library. + +config DRM_CDNS_HDMI + tristate "Cadence HDMI DRM driver" + depends on DRM_CDNS_MHDP + +config DRM_CDNS_DP + tristate "Cadence DP DRM driver" + depends on DRM_CDNS_MHDP + +config DRM_CDNS_AUDIO + tristate "Cadence MHDP Audio driver" + depends on DRM_CDNS_MHDP + +config DRM_CDNS_HDCP + tristate "Cadence HDMI/DP HDCP driver" + depends on DRM_CDNS_MHDP + help + Support HDCP for either HDMI or DisplayPort. This + requires that the SOC has HDCP keys programmed + in production. + +config DRM_CDNS_HDMI_CEC + tristate "Cadence MHDP HDMI CEC driver" + select CEC_CORE + select CEC_NOTIFIER diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/cadence/Makefile linux-imx-phytec/drivers/gpu/drm/bridge/cadence/Makefile --- linux-6.1.55/drivers/gpu/drm/bridge/cadence/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/cadence/Makefile 2024-06-19 12:34:01.892253989 +0200 @@ -2,3 +2,13 @@ obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o + +cdns_mhdp_drmcore-y := cdns-mhdp-common.o cdns-mhdp-dp.o cdns-mhdp-hdmi.o + +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_HDMI) += cdns-hdmi-core.o +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_DP) += cdns-dp-core.o +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_AUDIO) += cdns-mhdp-audio.o +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_HDCP) += cdns-mhdp-hdcp.o cdns-hdcp-common.o +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_HDMI_CEC) += cdns-mhdp-cec.o + +obj-$(CONFIG_DRM_CDNS_MHDP) += cdns_mhdp_drmcore.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/fsl-imx-ldb.c linux-imx-phytec/drivers/gpu/drm/bridge/fsl-imx-ldb.c --- linux-6.1.55/drivers/gpu/drm/bridge/fsl-imx-ldb.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/fsl-imx-ldb.c 2024-06-19 12:34:01.896254057 +0200 @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Sascha Hauer, Pengutronix + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0) +#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) +#define LDB_CH0_MODE_EN_MASK (3 << 0) +#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2) +#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) +#define LDB_CH1_MODE_EN_MASK (3 << 2) +#define LDB_SPLIT_MODE_EN (1 << 4) +#define LDB_DATA_WIDTH_CH0_24 (1 << 5) +#define LDB_BIT_MAP_CH0_JEIDA (1 << 6) +#define LDB_DATA_WIDTH_CH1_24 (1 << 7) +#define LDB_BIT_MAP_CH1_JEIDA (1 << 8) +#define LDB_DI0_VS_POL_ACT_LOW (1 << 9) +#define LDB_DI1_VS_POL_ACT_LOW (1 << 10) + +struct ldb_bit_mapping { + u32 bus_format; + u32 datawidth; + const char * const mapping; +}; + +static const struct ldb_bit_mapping ldb_bit_mappings[] = { + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" }, + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" }, + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" }, +}; + +static u32 of_get_bus_format(struct device *dev, struct device_node *np) +{ + const char *bm; + u32 datawidth = 0; + int ret, i; + + ret = of_property_read_string(np, "fsl,data-mapping", &bm); + if (ret < 0) + return ret; + + of_property_read_u32(np, "fsl,data-width", &datawidth); + + for (i = 0; i < ARRAY_SIZE(ldb_bit_mappings); i++) { + if (!strcasecmp(bm, ldb_bit_mappings[i].mapping) && + datawidth == ldb_bit_mappings[i].datawidth) + return ldb_bit_mappings[i].bus_format; + } + + dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm); + + return -ENOENT; +} + +static inline struct ldb_channel *bridge_to_ldb_ch(struct drm_bridge *b) +{ + return container_of(b, struct ldb_channel, bridge); +} + +static void ldb_ch_set_bus_format(struct ldb_channel *ldb_ch, u32 bus_format) +{ + struct ldb *ldb = ldb_ch->ldb; + + switch (bus_format) { + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + if (ldb_ch->chno == 0 || ldb->dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; + if (ldb_ch->chno == 1 || ldb->dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + if (ldb_ch->chno == 0 || ldb->dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | + LDB_BIT_MAP_CH0_JEIDA; + if (ldb_ch->chno == 1 || ldb->dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | + LDB_BIT_MAP_CH1_JEIDA; + break; + } +} + +static void ldb_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct ldb_channel *ldb_ch = bridge_to_ldb_ch(bridge); + struct ldb *ldb = ldb_ch->ldb; + + /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ + if (ldb_ch == ldb->channel[0] || ldb->dual) { + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) + ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; + else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) + ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW; + } + if (ldb_ch == ldb->channel[1] || ldb->dual) { + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) + ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; + else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) + ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW; + } + + ldb_ch_set_bus_format(ldb_ch, ldb_ch->bus_format); +} + +static void ldb_bridge_enable(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge_to_ldb_ch(bridge); + struct ldb *ldb = ldb_ch->ldb; + + if (pm_runtime_enabled(ldb->dev)) + pm_runtime_get_sync(ldb->dev); + + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); +} + +static void ldb_bridge_disable(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge_to_ldb_ch(bridge); + struct ldb *ldb = ldb_ch->ldb; + + if (ldb_ch == ldb->channel[0] || ldb->dual) + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; + if (ldb_ch == ldb->channel[1] || ldb->dual) + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; + + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); + + if (pm_runtime_enabled(ldb->dev)) + pm_runtime_put(ldb->dev); +} + +static int ldb_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct ldb_channel *ldb_ch = bridge_to_ldb_ch(bridge); + struct ldb *ldb = ldb_ch->ldb; + + if (!bridge->encoder) { + dev_err(ldb->dev, "failed to find encoder object\n"); + return -ENODEV; + } + + if (!ldb_ch->next_bridge) + return 0; + + return drm_bridge_attach(bridge->encoder, + ldb_ch->next_bridge, &ldb_ch->bridge, flags); +} + +static int ldb_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_display_info *di = &conn_state->connector->display_info; + struct drm_bridge_state *next_bridge_state = NULL; + struct drm_bridge *next_bridge; + u32 bus_flags = 0; + + next_bridge = drm_bridge_get_next_bridge(bridge); + if (next_bridge) + next_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state, + next_bridge); + + if (next_bridge_state) + bus_flags = next_bridge_state->input_bus_cfg.flags; + else if (di->num_bus_formats) + bus_flags = di->bus_flags; + + bridge_state->output_bus_cfg.flags = bus_flags; + bridge_state->input_bus_cfg.flags = bus_flags; + + return 0; +} + +static u32 *ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + u32 *output_fmts; + int i; + + *num_output_fmts = 0; + + output_fmts = kcalloc(ARRAY_SIZE(ldb_bit_mappings), + sizeof(*output_fmts), GFP_KERNEL); + if (!output_fmts) + return NULL; + + for (i = 0; i < ARRAY_SIZE(ldb_bit_mappings); i++) + output_fmts[i] = ldb_bit_mappings[i].bus_format; + + *num_output_fmts = ARRAY_SIZE(ldb_bit_mappings); + + return output_fmts; +} + +static const struct drm_bridge_funcs ldb_bridge_funcs = { + .mode_set = ldb_bridge_mode_set, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .enable = ldb_bridge_enable, + .disable = ldb_bridge_disable, + .attach = ldb_bridge_attach, + .atomic_check = ldb_bridge_atomic_check, + .atomic_get_output_bus_fmts = ldb_bridge_atomic_get_output_bus_fmts, +}; + +int ldb_bind(struct ldb *ldb, struct drm_encoder **encoder) +{ + struct device *dev = ldb->dev; + struct device_node *np = dev->of_node; + struct device_node *child; + int ret = 0; + int i; + + ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); + if (IS_ERR(ldb->regmap)) { + dev_err(dev, "failed to get parent regmap\n"); + return PTR_ERR(ldb->regmap); + } + + if (pm_runtime_enabled(dev)) + pm_runtime_get_sync(dev); + + /* disable LDB by resetting the control register to POR default */ + regmap_write(ldb->regmap, ldb->ctrl_reg, 0); + + if (pm_runtime_enabled(dev)) + pm_runtime_put(dev); + + ldb->dual = of_property_read_bool(np, "fsl,dual-channel"); + if (ldb->dual) + ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; + + for_each_child_of_node(np, child) { + struct ldb_channel *ldb_ch; + int bus_format; + + ret = of_property_read_u32(child, "reg", &i); + if (ret || i < 0 || i > 1) { + ret = -EINVAL; + goto free_child; + } + + if (!of_device_is_available(child)) + continue; + + if (ldb->dual && i > 0) { + dev_warn(dev, "dual-channel mode, ignoring second output\n"); + continue; + } + + ldb_ch = ldb->channel[i]; + ldb_ch->ldb = ldb; + ldb_ch->chno = i; + ldb_ch->is_valid = false; + + ret = drm_of_find_panel_or_bridge(child, + ldb->output_port, 0, + &ldb_ch->panel, + &ldb_ch->next_bridge); + if (ret && ret != -ENODEV) + goto free_child; + + bus_format = of_get_bus_format(dev, child); + if (bus_format == -EINVAL) { + /* + * If no bus format was specified in the device tree, + * we can still get it from the connected panel later. + */ + if (ldb_ch->panel && ldb_ch->panel->funcs && + ldb_ch->panel->funcs->get_modes) + bus_format = 0; + } + if (bus_format < 0) { + dev_warn(dev, "No data-mapping in DT, will use negotiated bus format.\n"); + bus_format = 0; + } + ldb_ch->bus_format = bus_format; + ldb_ch->child = child; + + if (ldb_ch->panel) { + ldb_ch->next_bridge = devm_drm_panel_bridge_add(dev, + ldb_ch->panel); + if (IS_ERR(ldb_ch->next_bridge)) { + ret = PTR_ERR(ldb_ch->next_bridge); + goto free_child; + } + } + + ldb_ch->bridge.driver_private = ldb_ch; + ldb_ch->bridge.funcs = &ldb_bridge_funcs; + ldb_ch->bridge.of_node = child; + + ret = drm_bridge_attach(encoder[i], &ldb_ch->bridge, NULL, 0); + if (ret) { + dev_err(dev, + "failed to attach bridge with encoder: %d\n", + ret); + goto free_child; + } + + ldb_ch->is_valid = true; + } + + return 0; + +free_child: + of_node_put(child); + return ret; +} +EXPORT_SYMBOL_GPL(ldb_bind); + +MODULE_DESCRIPTION("Freescale i.MX LVDS display bridge driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform: fsl-imx-ldb"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c linux-imx-phytec/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c --- linux-6.1.55/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,588 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -/* - * Copyright 2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "imx-ldb-helper.h" - -#define LDB_CH0_10BIT_EN BIT(22) -#define LDB_CH1_10BIT_EN BIT(23) -#define LDB_CH0_DATA_WIDTH_24BIT BIT(24) -#define LDB_CH1_DATA_WIDTH_24BIT BIT(26) -#define LDB_CH0_DATA_WIDTH_30BIT (2 << 24) -#define LDB_CH1_DATA_WIDTH_30BIT (2 << 26) - -#define SS_CTRL 0x20 -#define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) -#define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) -#define CH_PHSYNC(id) BIT(0 + ((id) * 2)) -#define CH_PVSYNC(id) BIT(1 + ((id) * 2)) - -#define DRIVER_NAME "imx8qm-ldb" - -struct imx8qm_ldb_channel { - struct ldb_channel base; - struct phy *phy; -}; - -struct imx8qm_ldb { - struct ldb base; - struct device *dev; - struct imx8qm_ldb_channel channel[MAX_LDB_CHAN_NUM]; - struct clk *clk_pixel; - struct clk *clk_bypass; - int active_chno; -}; - -static inline struct imx8qm_ldb_channel * -base_to_imx8qm_ldb_channel(struct ldb_channel *base) -{ - return container_of(base, struct imx8qm_ldb_channel, base); -} - -static inline struct imx8qm_ldb *base_to_imx8qm_ldb(struct ldb *base) -{ - return container_of(base, struct imx8qm_ldb, base); -} - -static void imx8qm_ldb_set_phy_cfg(struct imx8qm_ldb *imx8qm_ldb, - unsigned long di_clk, - bool is_split, bool is_slave, - struct phy_configure_opts_lvds *phy_cfg) -{ - phy_cfg->bits_per_lane_and_dclk_cycle = 7; - phy_cfg->lanes = 4; - phy_cfg->differential_clk_rate = is_split ? di_clk / 2 : di_clk; - phy_cfg->is_slave = is_slave; -} - -static int imx8qm_ldb_bridge_atomic_check(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - struct imx8qm_ldb_channel *imx8qm_ldb_ch = - base_to_imx8qm_ldb_channel(ldb_ch); - struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); - struct drm_display_mode *adj = &crtc_state->adjusted_mode; - unsigned long di_clk = adj->clock * 1000; - bool is_split = ldb_channel_is_split_link(ldb_ch); - union phy_configure_opts opts = { }; - struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; - int ret; - - ret = ldb_bridge_atomic_check_helper(bridge, bridge_state, - crtc_state, conn_state); - if (ret) - return ret; - - imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg); - ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); - if (ret < 0) { - DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev, - "failed to validate PHY: %d\n", ret); - return ret; - } - - if (is_split) { - imx8qm_ldb_ch = - &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1]; - imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true, - phy_cfg); - ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); - if (ret < 0) { - DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev, - "failed to validate slave PHY: %d\n", - ret); - return ret; - } - } - - return ret; -} - -static void -imx8qm_ldb_bridge_mode_set(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - struct imx8qm_ldb_channel *imx8qm_ldb_ch = - base_to_imx8qm_ldb_channel(ldb_ch); - struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); - struct device *dev = imx8qm_ldb->dev; - unsigned long di_clk = adjusted_mode->clock * 1000; - bool is_split = ldb_channel_is_split_link(ldb_ch); - union phy_configure_opts opts = { }; - struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; - u32 chno = ldb_ch->chno; - int ret; - - ret = pm_runtime_get_sync(dev); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret); - - ret = phy_init(imx8qm_ldb_ch->phy); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret); - - clk_set_rate(imx8qm_ldb->clk_bypass, di_clk); - clk_set_rate(imx8qm_ldb->clk_pixel, di_clk); - - imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg); - ret = phy_configure(imx8qm_ldb_ch->phy, &opts); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret); - - if (is_split) { - imx8qm_ldb_ch = - &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1]; - imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true, - phy_cfg); - ret = phy_configure(imx8qm_ldb_ch->phy, &opts); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to configure slave PHY: %d\n", - ret); - } - - /* input VSYNC signal from pixel link is active low */ - if (ldb_ch->chno == 0 || is_split) - ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; - if (ldb_ch->chno == 1 || is_split) - ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; - - switch (ldb_ch->out_bus_format) { - case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: - break; - case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: - case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: - if (ldb_ch->chno == 0 || is_split) - ldb->ldb_ctrl |= LDB_CH0_DATA_WIDTH_24BIT; - if (ldb_ch->chno == 1 || is_split) - ldb->ldb_ctrl |= LDB_CH1_DATA_WIDTH_24BIT; - break; - } - - ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode); - - if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) - regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0); - else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) - regmap_update_bits(ldb->regmap, SS_CTRL, - CH_VSYNC_M(chno), CH_PVSYNC(chno)); - - if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) - regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0); - else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) - regmap_update_bits(ldb->regmap, SS_CTRL, - CH_HSYNC_M(chno), CH_PHSYNC(chno)); -} - -static void -imx8qm_ldb_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_bridge_state *old_bridge_state) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - struct imx8qm_ldb_channel *imx8qm_ldb_ch = - base_to_imx8qm_ldb_channel(ldb_ch); - struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); - struct device *dev = imx8qm_ldb->dev; - bool is_split = ldb_channel_is_split_link(ldb_ch); - int ret; - - clk_prepare_enable(imx8qm_ldb->clk_pixel); - clk_prepare_enable(imx8qm_ldb->clk_bypass); - - /* both DI0 and DI1 connect with pixel link, so ok to use DI0 only */ - if (ldb_ch->chno == 0 || is_split) { - ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; - ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; - } - if (ldb_ch->chno == 1 || is_split) { - ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; - ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; - } - - if (is_split) { - ret = phy_power_on(imx8qm_ldb->channel[0].phy); - if (ret) - DRM_DEV_ERROR(dev, - "failed to power on channel0 PHY: %d\n", - ret); - - ret = phy_power_on(imx8qm_ldb->channel[1].phy); - if (ret) - DRM_DEV_ERROR(dev, - "failed to power on channel1 PHY: %d\n", - ret); - } else { - ret = phy_power_on(imx8qm_ldb_ch->phy); - if (ret) - DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret); - } - - ldb_bridge_enable_helper(bridge); -} - -static void -imx8qm_ldb_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_bridge_state *old_bridge_state) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - struct imx8qm_ldb_channel *imx8qm_ldb_ch = - base_to_imx8qm_ldb_channel(ldb_ch); - struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); - struct device *dev = imx8qm_ldb->dev; - bool is_split = ldb_channel_is_split_link(ldb_ch); - int ret; - - ldb_bridge_disable_helper(bridge); - - if (is_split) { - ret = phy_power_off(imx8qm_ldb->channel[0].phy); - if (ret) - DRM_DEV_ERROR(dev, - "failed to power off channel0 PHY: %d\n", - ret); - ret = phy_power_off(imx8qm_ldb->channel[1].phy); - if (ret) - DRM_DEV_ERROR(dev, - "failed to power off channel1 PHY: %d\n", - ret); - } else { - ret = phy_power_off(imx8qm_ldb_ch->phy); - if (ret) - DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret); - } - - clk_disable_unprepare(imx8qm_ldb->clk_bypass); - clk_disable_unprepare(imx8qm_ldb->clk_pixel); - - ret = pm_runtime_put(dev); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret); -} - -static const u32 imx8qm_ldb_bus_output_fmts[] = { - MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, - MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, - MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, - MEDIA_BUS_FMT_FIXED, -}; - -static bool imx8qm_ldb_bus_output_fmt_supported(u32 fmt) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); i++) { - if (imx8qm_ldb_bus_output_fmts[i] == fmt) - return true; - } - - return false; -} - -static u32 * -imx8qm_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state, - u32 output_fmt, - unsigned int *num_input_fmts) -{ - struct drm_display_info *di; - const struct drm_format_info *finfo; - u32 *input_fmts; - - if (!imx8qm_ldb_bus_output_fmt_supported(output_fmt)) - return NULL; - - *num_input_fmts = 1; - - input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); - if (!input_fmts) - return NULL; - - switch (output_fmt) { - case MEDIA_BUS_FMT_FIXED: - di = &conn_state->connector->display_info; - - /* - * Look at the first bus format to determine input format. - * Default to MEDIA_BUS_FMT_RGB888_1X36_CPADLO, if no match. - */ - if (di->num_bus_formats) { - finfo = drm_format_info(di->bus_formats[0]); - - input_fmts[0] = finfo->depth == 18 ? - MEDIA_BUS_FMT_RGB666_1X36_CPADLO : - MEDIA_BUS_FMT_RGB888_1X36_CPADLO; - } else { - input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO; - } - break; - case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: - input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO; - break; - case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: - case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: - input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO; - break; - default: - kfree(input_fmts); - input_fmts = NULL; - break; - } - - return input_fmts; -} - -static u32 * -imx8qm_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state, - unsigned int *num_output_fmts) -{ - *num_output_fmts = ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); - return kmemdup(imx8qm_ldb_bus_output_fmts, - sizeof(imx8qm_ldb_bus_output_fmts), GFP_KERNEL); -} - -static enum drm_mode_status -imx8qm_ldb_bridge_mode_valid(struct drm_bridge *bridge, - const struct drm_display_info *info, - const struct drm_display_mode *mode) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - bool is_single = ldb_channel_is_single_link(ldb_ch); - - if (mode->clock > 300000) - return MODE_CLOCK_HIGH; - - if (mode->clock > 150000 && is_single) - return MODE_CLOCK_HIGH; - - return MODE_OK; -} - -static const struct drm_bridge_funcs imx8qm_ldb_bridge_funcs = { - .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, - .atomic_reset = drm_atomic_helper_bridge_reset, - .mode_valid = imx8qm_ldb_bridge_mode_valid, - .attach = ldb_bridge_attach_helper, - .atomic_check = imx8qm_ldb_bridge_atomic_check, - .mode_set = imx8qm_ldb_bridge_mode_set, - .atomic_enable = imx8qm_ldb_bridge_atomic_enable, - .atomic_disable = imx8qm_ldb_bridge_atomic_disable, - .atomic_get_input_bus_fmts = - imx8qm_ldb_bridge_atomic_get_input_bus_fmts, - .atomic_get_output_bus_fmts = - imx8qm_ldb_bridge_atomic_get_output_bus_fmts, -}; - -static int imx8qm_ldb_get_phy(struct imx8qm_ldb *imx8qm_ldb) -{ - struct imx8qm_ldb_channel *imx8qm_ldb_ch; - struct ldb_channel *ldb_ch; - struct device *dev = imx8qm_ldb->dev; - int i, ret; - - for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { - imx8qm_ldb_ch = &imx8qm_ldb->channel[i]; - ldb_ch = &imx8qm_ldb_ch->base; - - if (!ldb_ch->is_available) - continue; - - imx8qm_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, - "lvds_phy"); - if (IS_ERR(imx8qm_ldb_ch->phy)) { - ret = PTR_ERR(imx8qm_ldb_ch->phy); - if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(dev, - "failed to get channel%d PHY: %d\n", - i, ret); - return ret; - } - } - - return 0; -} - -static int imx8qm_ldb_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct imx8qm_ldb *imx8qm_ldb; - struct imx8qm_ldb_channel *imx8qm_ldb_ch; - struct ldb *ldb; - struct ldb_channel *ldb_ch; - struct device_node *port1, *port2; - int pixel_order; - int ret, i; - - imx8qm_ldb = devm_kzalloc(dev, sizeof(*imx8qm_ldb), GFP_KERNEL); - if (!imx8qm_ldb) - return -ENOMEM; - - imx8qm_ldb->clk_pixel = devm_clk_get(dev, "pixel"); - if (IS_ERR(imx8qm_ldb->clk_pixel)) { - ret = PTR_ERR(imx8qm_ldb->clk_pixel); - if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(dev, - "failed to get pixel clock: %d\n", ret); - return ret; - } - - imx8qm_ldb->clk_bypass = devm_clk_get(dev, "bypass"); - if (IS_ERR(imx8qm_ldb->clk_bypass)) { - ret = PTR_ERR(imx8qm_ldb->clk_bypass); - if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(dev, - "failed to get bypass clock: %d\n", ret); - return ret; - } - - imx8qm_ldb->dev = dev; - - ldb = &imx8qm_ldb->base; - ldb->dev = dev; - ldb->ctrl_reg = 0xe0; - - for (i = 0; i < MAX_LDB_CHAN_NUM; i++) - ldb->channel[i] = &imx8qm_ldb->channel[i].base; - - ret = ldb_init_helper(ldb); - if (ret) - return ret; - - if (ldb->available_ch_cnt == 0) { - DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n"); - return 0; - } - - if (ldb->available_ch_cnt == 2) { - port1 = of_graph_get_port_by_id(ldb->channel[0]->np, 1); - port2 = of_graph_get_port_by_id(ldb->channel[1]->np, 1); - pixel_order = - drm_of_lvds_get_dual_link_pixel_order(port1, port2); - of_node_put(port1); - of_node_put(port2); - - if (pixel_order != DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { - DRM_DEV_ERROR(dev, "invalid dual link pixel order: %d\n", - pixel_order); - return -EINVAL; - } - - imx8qm_ldb->active_chno = 0; - imx8qm_ldb_ch = &imx8qm_ldb->channel[0]; - ldb_ch = &imx8qm_ldb_ch->base; - ldb_ch->link_type = pixel_order; - } else { - for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { - imx8qm_ldb_ch = &imx8qm_ldb->channel[i]; - ldb_ch = &imx8qm_ldb_ch->base; - - if (ldb_ch->is_available) { - imx8qm_ldb->active_chno = ldb_ch->chno; - break; - } - } - } - - ret = imx8qm_ldb_get_phy(imx8qm_ldb); - if (ret) - return ret; - - ret = ldb_find_next_bridge_helper(ldb); - if (ret) - return ret; - - platform_set_drvdata(pdev, imx8qm_ldb); - pm_runtime_enable(dev); - - ldb_add_bridge_helper(ldb, &imx8qm_ldb_bridge_funcs); - - return ret; -} - -static int imx8qm_ldb_remove(struct platform_device *pdev) -{ - struct imx8qm_ldb *imx8qm_ldb = platform_get_drvdata(pdev); - struct ldb *ldb = &imx8qm_ldb->base; - - ldb_remove_bridge_helper(ldb); - - pm_runtime_disable(&pdev->dev); - - return 0; -} - -static int __maybe_unused imx8qm_ldb_runtime_suspend(struct device *dev) -{ - return 0; -} - -static int __maybe_unused imx8qm_ldb_runtime_resume(struct device *dev) -{ - struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev); - struct ldb *ldb = &imx8qm_ldb->base; - - /* disable LDB by resetting the control register to POR default */ - regmap_write(ldb->regmap, ldb->ctrl_reg, 0); - - return 0; -} - -static const struct dev_pm_ops imx8qm_ldb_pm_ops = { - SET_RUNTIME_PM_OPS(imx8qm_ldb_runtime_suspend, - imx8qm_ldb_runtime_resume, NULL) -}; - -static const struct of_device_id imx8qm_ldb_dt_ids[] = { - { .compatible = "fsl,imx8qm-ldb" }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx8qm_ldb_dt_ids); - -static struct platform_driver imx8qm_ldb_driver = { - .probe = imx8qm_ldb_probe, - .remove = imx8qm_ldb_remove, - .driver = { - .pm = &imx8qm_ldb_pm_ops, - .name = DRIVER_NAME, - .of_match_table = imx8qm_ldb_dt_ids, - }, -}; -module_platform_driver(imx8qm_ldb_driver); - -MODULE_DESCRIPTION("i.MX8QM LVDS Display Bridge(LDB)/Pixel Mapper bridge driver"); -MODULE_AUTHOR("Liu Ying "); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:" DRIVER_NAME); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c linux-imx-phytec/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c --- linux-6.1.55/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,723 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -/* - * Copyright 2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "imx-ldb-helper.h" - -#define LDB_CH_SEL BIT(28) - -#define SS_CTRL 0x20 -#define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) -#define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) -#define CH_PHSYNC(id) BIT(0 + ((id) * 2)) -#define CH_PVSYNC(id) BIT(1 + ((id) * 2)) - -#define DRIVER_NAME "imx8qxp-ldb" - -struct imx8qxp_ldb_channel { - struct ldb_channel base; - struct phy *phy; - unsigned int di_id; -}; - -struct imx8qxp_ldb { - struct ldb base; - struct device *dev; - struct imx8qxp_ldb_channel channel[MAX_LDB_CHAN_NUM]; - struct clk *clk_pixel; - struct clk *clk_bypass; - struct drm_bridge *companion; - int active_chno; -}; - -static inline struct imx8qxp_ldb_channel * -base_to_imx8qxp_ldb_channel(struct ldb_channel *base) -{ - return container_of(base, struct imx8qxp_ldb_channel, base); -} - -static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base) -{ - return container_of(base, struct imx8qxp_ldb, base); -} - -static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb, - unsigned long di_clk, bool is_split, - struct phy_configure_opts_lvds *phy_cfg) -{ - phy_cfg->bits_per_lane_and_dclk_cycle = 7; - phy_cfg->lanes = 4; - - if (is_split) { - phy_cfg->differential_clk_rate = di_clk / 2; - phy_cfg->is_slave = !imx8qxp_ldb->companion; - } else { - phy_cfg->differential_clk_rate = di_clk; - phy_cfg->is_slave = false; - } -} - -static int -imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = - base_to_imx8qxp_ldb_channel(ldb_ch); - struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); - struct drm_bridge *companion = imx8qxp_ldb->companion; - struct drm_display_mode *adj = &crtc_state->adjusted_mode; - unsigned long di_clk = adj->clock * 1000; - bool is_split = ldb_channel_is_split_link(ldb_ch); - union phy_configure_opts opts = { }; - struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; - int ret; - - ret = ldb_bridge_atomic_check_helper(bridge, bridge_state, - crtc_state, conn_state); - if (ret) - return ret; - - imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); - ret = phy_validate(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); - if (ret < 0) { - DRM_DEV_DEBUG_DRIVER(imx8qxp_ldb->dev, - "failed to validate PHY: %d\n", ret); - return ret; - } - - if (is_split && companion) { - ret = companion->funcs->atomic_check(companion, - bridge_state, crtc_state, conn_state); - if (ret) - return ret; - } - - return ret; -} - -static void -imx8qxp_ldb_bridge_mode_set(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb_channel *companion_ldb_ch; - struct ldb *ldb = ldb_ch->ldb; - struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = - base_to_imx8qxp_ldb_channel(ldb_ch); - struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); - struct drm_bridge *companion = imx8qxp_ldb->companion; - struct device *dev = imx8qxp_ldb->dev; - unsigned long di_clk = adjusted_mode->clock * 1000; - bool is_split = ldb_channel_is_split_link(ldb_ch); - union phy_configure_opts opts = { }; - struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; - u32 chno = ldb_ch->chno; - int ret; - - ret = pm_runtime_get_sync(dev); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret); - - ret = phy_init(imx8qxp_ldb_ch->phy); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret); - - ret = phy_set_mode(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to set PHY mode: %d\n", ret); - - if (is_split && companion) { - companion_ldb_ch = bridge_to_ldb_ch(companion); - - companion_ldb_ch->in_bus_format = ldb_ch->in_bus_format; - companion_ldb_ch->out_bus_format = ldb_ch->out_bus_format; - } - - clk_set_rate(imx8qxp_ldb->clk_bypass, di_clk); - clk_set_rate(imx8qxp_ldb->clk_pixel, di_clk); - - imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); - ret = phy_configure(imx8qxp_ldb_ch->phy, &opts); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret); - - if (chno == 0) - ldb->ldb_ctrl &= ~LDB_CH_SEL; - else - ldb->ldb_ctrl |= LDB_CH_SEL; - - /* input VSYNC signal from pixel link is active low */ - if (imx8qxp_ldb_ch->di_id == 0) - ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; - else - ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; - - /* - * For split mode, settle input VSYNC signal polarity and - * channel selection down early. - */ - if (is_split) - regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); - - ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode); - - if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) - regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0); - else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) - regmap_update_bits(ldb->regmap, SS_CTRL, - CH_VSYNC_M(chno), CH_PVSYNC(chno)); - - if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) - regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0); - else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) - regmap_update_bits(ldb->regmap, SS_CTRL, - CH_HSYNC_M(chno), CH_PHSYNC(chno)); - - if (is_split && companion) - companion->funcs->mode_set(companion, mode, adjusted_mode); -} - -static void -imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_bridge_state *old_bridge_state) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); - struct drm_bridge *companion = imx8qxp_ldb->companion; - bool is_split = ldb_channel_is_split_link(ldb_ch); - - clk_prepare_enable(imx8qxp_ldb->clk_pixel); - clk_prepare_enable(imx8qxp_ldb->clk_bypass); - - if (is_split && companion) - companion->funcs->atomic_pre_enable(companion, old_bridge_state); -} - -static void -imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_bridge_state *old_bridge_state) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = - base_to_imx8qxp_ldb_channel(ldb_ch); - struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); - struct drm_bridge *companion = imx8qxp_ldb->companion; - struct device *dev = imx8qxp_ldb->dev; - bool is_split = ldb_channel_is_split_link(ldb_ch); - int ret; - - if (ldb_ch->chno == 0 || is_split) { - ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; - ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ? - LDB_CH0_MODE_EN_TO_DI0 : LDB_CH0_MODE_EN_TO_DI1; - } - if (ldb_ch->chno == 1 || is_split) { - ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; - ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ? - LDB_CH1_MODE_EN_TO_DI0 : LDB_CH1_MODE_EN_TO_DI1; - } - - ldb_bridge_enable_helper(bridge); - - ret = phy_power_on(imx8qxp_ldb_ch->phy); - if (ret) - DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret); - - if (is_split && companion) - companion->funcs->atomic_enable(companion, old_bridge_state); -} - -static void -imx8qxp_ldb_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_bridge_state *old_bridge_state) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = - base_to_imx8qxp_ldb_channel(ldb_ch); - struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); - struct drm_bridge *companion = imx8qxp_ldb->companion; - struct device *dev = imx8qxp_ldb->dev; - bool is_split = ldb_channel_is_split_link(ldb_ch); - int ret; - - ret = phy_power_off(imx8qxp_ldb_ch->phy); - if (ret) - DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret); - - ret = phy_exit(imx8qxp_ldb_ch->phy); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to teardown PHY: %d\n", ret); - - ldb_bridge_disable_helper(bridge); - - clk_disable_unprepare(imx8qxp_ldb->clk_bypass); - clk_disable_unprepare(imx8qxp_ldb->clk_pixel); - - if (is_split && companion) - companion->funcs->atomic_disable(companion, old_bridge_state); - - ret = pm_runtime_put(dev); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret); -} - -static const u32 imx8qxp_ldb_bus_output_fmts[] = { - MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, - MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, - MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, - MEDIA_BUS_FMT_FIXED, -}; - -static bool imx8qxp_ldb_bus_output_fmt_supported(u32 fmt) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); i++) { - if (imx8qxp_ldb_bus_output_fmts[i] == fmt) - return true; - } - - return false; -} - -static u32 * -imx8qxp_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state, - u32 output_fmt, - unsigned int *num_input_fmts) -{ - struct drm_display_info *di; - const struct drm_format_info *finfo; - u32 *input_fmts; - - if (!imx8qxp_ldb_bus_output_fmt_supported(output_fmt)) - return NULL; - - *num_input_fmts = 1; - - input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); - if (!input_fmts) - return NULL; - - switch (output_fmt) { - case MEDIA_BUS_FMT_FIXED: - di = &conn_state->connector->display_info; - - /* - * Look at the first bus format to determine input format. - * Default to MEDIA_BUS_FMT_RGB888_1X24, if no match. - */ - if (di->num_bus_formats) { - finfo = drm_format_info(di->bus_formats[0]); - - input_fmts[0] = finfo->depth == 18 ? - MEDIA_BUS_FMT_RGB666_1X24_CPADHI : - MEDIA_BUS_FMT_RGB888_1X24; - } else { - input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; - } - break; - case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: - input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X24_CPADHI; - break; - case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: - case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: - input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; - break; - default: - kfree(input_fmts); - input_fmts = NULL; - break; - } - - return input_fmts; -} - -static u32 * -imx8qxp_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state, - unsigned int *num_output_fmts) -{ - *num_output_fmts = ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); - return kmemdup(imx8qxp_ldb_bus_output_fmts, - sizeof(imx8qxp_ldb_bus_output_fmts), GFP_KERNEL); -} - -static enum drm_mode_status -imx8qxp_ldb_bridge_mode_valid(struct drm_bridge *bridge, - const struct drm_display_info *info, - const struct drm_display_mode *mode) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - bool is_single = ldb_channel_is_single_link(ldb_ch); - - if (mode->clock > 170000) - return MODE_CLOCK_HIGH; - - if (mode->clock > 150000 && is_single) - return MODE_CLOCK_HIGH; - - return MODE_OK; -} - -static const struct drm_bridge_funcs imx8qxp_ldb_bridge_funcs = { - .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, - .atomic_reset = drm_atomic_helper_bridge_reset, - .mode_valid = imx8qxp_ldb_bridge_mode_valid, - .attach = ldb_bridge_attach_helper, - .atomic_check = imx8qxp_ldb_bridge_atomic_check, - .mode_set = imx8qxp_ldb_bridge_mode_set, - .atomic_pre_enable = imx8qxp_ldb_bridge_atomic_pre_enable, - .atomic_enable = imx8qxp_ldb_bridge_atomic_enable, - .atomic_disable = imx8qxp_ldb_bridge_atomic_disable, - .atomic_get_input_bus_fmts = - imx8qxp_ldb_bridge_atomic_get_input_bus_fmts, - .atomic_get_output_bus_fmts = - imx8qxp_ldb_bridge_atomic_get_output_bus_fmts, -}; - -static int imx8qxp_ldb_set_di_id(struct imx8qxp_ldb *imx8qxp_ldb) -{ - struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = - &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno]; - struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base; - struct device_node *ep, *remote; - struct device *dev = imx8qxp_ldb->dev; - struct of_endpoint endpoint; - int ret; - - ep = of_graph_get_endpoint_by_regs(ldb_ch->np, 0, -1); - if (!ep) { - DRM_DEV_ERROR(dev, "failed to get port0 endpoint\n"); - return -EINVAL; - } - - remote = of_graph_get_remote_endpoint(ep); - of_node_put(ep); - if (!remote) { - DRM_DEV_ERROR(dev, "failed to get port0 remote endpoint\n"); - return -EINVAL; - } - - ret = of_graph_parse_endpoint(remote, &endpoint); - of_node_put(remote); - if (ret) { - DRM_DEV_ERROR(dev, "failed to parse port0 remote endpoint: %d\n", - ret); - return ret; - } - - imx8qxp_ldb_ch->di_id = endpoint.id; - - return 0; -} - -static int -imx8qxp_ldb_check_chno_and_dual_link(struct ldb_channel *ldb_ch, int link) -{ - if ((link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS && ldb_ch->chno != 0) || - (link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS && ldb_ch->chno != 1)) - return -EINVAL; - - return 0; -} - -static int imx8qxp_ldb_parse_dt_companion(struct imx8qxp_ldb *imx8qxp_ldb) -{ - struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = - &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno]; - struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base; - struct ldb_channel *companion_ldb_ch; - struct device_node *companion; - struct device_node *child; - struct device_node *companion_port = NULL; - struct device_node *port1, *port2; - struct device *dev = imx8qxp_ldb->dev; - const struct of_device_id *match; - u32 i; - int dual_link; - int ret; - - /* Locate the companion LDB for dual-link operation, if any. */ - companion = of_parse_phandle(dev->of_node, "fsl,companion-ldb", 0); - if (!companion) - return 0; - - if (!of_device_is_available(companion)) { - DRM_DEV_ERROR(dev, "companion LDB is not available\n"); - ret = -ENODEV; - goto out; - } - - /* - * Sanity check: the companion bridge must have the same compatible - * string. - */ - match = of_match_device(dev->driver->of_match_table, dev); - if (!of_device_is_compatible(companion, match->compatible)) { - DRM_DEV_ERROR(dev, "companion LDB is incompatible\n"); - ret = -ENXIO; - goto out; - } - - for_each_available_child_of_node(companion, child) { - ret = of_property_read_u32(child, "reg", &i); - if (ret || i > MAX_LDB_CHAN_NUM - 1) { - DRM_DEV_ERROR(dev, - "invalid channel node address: %u\n", i); - ret = -EINVAL; - of_node_put(child); - goto out; - } - - /* - * Channel numbers have to be different, because channel0 - * transmits odd pixels and channel1 transmits even pixels. - */ - if (i == (ldb_ch->chno ^ 0x1)) { - companion_port = child; - break; - } - } - - if (!companion_port) { - DRM_DEV_ERROR(dev, - "failed to find companion LDB channel port\n"); - ret = -EINVAL; - goto out; - } - - /* - * We need to work out if the sink is expecting us to function in - * dual-link mode. We do this by looking at the DT port nodes we are - * connected to. If they are marked as expecting odd pixels and - * even pixels than we need to enable LDB split mode. - */ - port1 = of_graph_get_port_by_id(ldb_ch->np, 1); - port2 = of_graph_get_port_by_id(companion_port, 1); - dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); - of_node_put(port1); - of_node_put(port2); - - switch (dual_link) { - case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS: - ldb_ch->link_type = LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS; - break; - case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS: - ldb_ch->link_type = LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS; - break; - default: - ret = dual_link; - DRM_DEV_ERROR(dev, - "failed to get dual link pixel order: %d\n", ret); - goto out; - } - - ret = imx8qxp_ldb_check_chno_and_dual_link(ldb_ch, dual_link); - if (ret < 0) { - DRM_DEV_ERROR(dev, - "unmatched channel number(%u) vs dual link(%d)\n", - ldb_ch->chno, dual_link); - goto out; - } - - imx8qxp_ldb->companion = of_drm_find_bridge(companion_port); - if (!imx8qxp_ldb->companion) { - ret = -EPROBE_DEFER; - DRM_DEV_DEBUG_DRIVER(dev, - "failed to find bridge for companion bridge: %d\n", - ret); - goto out; - } - - DRM_DEV_DEBUG_DRIVER(dev, - "dual-link configuration detected (companion bridge %pOF)\n", - companion); - - companion_ldb_ch = bridge_to_ldb_ch(imx8qxp_ldb->companion); - companion_ldb_ch->link_type = ldb_ch->link_type; -out: - of_node_put(companion_port); - of_node_put(companion); - return ret; -} - -static int imx8qxp_ldb_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct imx8qxp_ldb *imx8qxp_ldb; - struct imx8qxp_ldb_channel *imx8qxp_ldb_ch; - struct ldb *ldb; - struct ldb_channel *ldb_ch; - int ret, i; - - imx8qxp_ldb = devm_kzalloc(dev, sizeof(*imx8qxp_ldb), GFP_KERNEL); - if (!imx8qxp_ldb) - return -ENOMEM; - - imx8qxp_ldb->clk_pixel = devm_clk_get(dev, "pixel"); - if (IS_ERR(imx8qxp_ldb->clk_pixel)) { - ret = PTR_ERR(imx8qxp_ldb->clk_pixel); - if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(dev, - "failed to get pixel clock: %d\n", ret); - return ret; - } - - imx8qxp_ldb->clk_bypass = devm_clk_get(dev, "bypass"); - if (IS_ERR(imx8qxp_ldb->clk_bypass)) { - ret = PTR_ERR(imx8qxp_ldb->clk_bypass); - if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(dev, - "failed to get bypass clock: %d\n", ret); - return ret; - } - - imx8qxp_ldb->dev = dev; - - ldb = &imx8qxp_ldb->base; - ldb->dev = dev; - ldb->ctrl_reg = 0xe0; - - for (i = 0; i < MAX_LDB_CHAN_NUM; i++) - ldb->channel[i] = &imx8qxp_ldb->channel[i].base; - - ret = ldb_init_helper(ldb); - if (ret) - return ret; - - if (ldb->available_ch_cnt == 0) { - DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n"); - return 0; - } else if (ldb->available_ch_cnt > 1) { - DRM_DEV_ERROR(dev, "invalid available channel number(%u)\n", - ldb->available_ch_cnt); - return -EINVAL; - } - - for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { - imx8qxp_ldb_ch = &imx8qxp_ldb->channel[i]; - ldb_ch = &imx8qxp_ldb_ch->base; - - if (ldb_ch->is_available) { - imx8qxp_ldb->active_chno = ldb_ch->chno; - break; - } - } - - imx8qxp_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, "lvds_phy"); - if (IS_ERR(imx8qxp_ldb_ch->phy)) { - ret = PTR_ERR(imx8qxp_ldb_ch->phy); - if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(dev, "failed to get channel%d PHY: %d\n", - imx8qxp_ldb->active_chno, ret); - return ret; - } - - ret = ldb_find_next_bridge_helper(ldb); - if (ret) - return ret; - - ret = imx8qxp_ldb_set_di_id(imx8qxp_ldb); - if (ret) - return ret; - - ret = imx8qxp_ldb_parse_dt_companion(imx8qxp_ldb); - if (ret) - return ret; - - platform_set_drvdata(pdev, imx8qxp_ldb); - pm_runtime_enable(dev); - - ldb_add_bridge_helper(ldb, &imx8qxp_ldb_bridge_funcs); - - return ret; -} - -static int imx8qxp_ldb_remove(struct platform_device *pdev) -{ - struct imx8qxp_ldb *imx8qxp_ldb = platform_get_drvdata(pdev); - struct ldb *ldb = &imx8qxp_ldb->base; - - ldb_remove_bridge_helper(ldb); - - pm_runtime_disable(&pdev->dev); - - return 0; -} - -static int __maybe_unused imx8qxp_ldb_runtime_suspend(struct device *dev) -{ - return 0; -} - -static int __maybe_unused imx8qxp_ldb_runtime_resume(struct device *dev) -{ - struct imx8qxp_ldb *imx8qxp_ldb = dev_get_drvdata(dev); - struct ldb *ldb = &imx8qxp_ldb->base; - - /* disable LDB by resetting the control register to POR default */ - regmap_write(ldb->regmap, ldb->ctrl_reg, 0); - - return 0; -} - -static const struct dev_pm_ops imx8qxp_ldb_pm_ops = { - SET_RUNTIME_PM_OPS(imx8qxp_ldb_runtime_suspend, - imx8qxp_ldb_runtime_resume, NULL) -}; - -static const struct of_device_id imx8qxp_ldb_dt_ids[] = { - { .compatible = "fsl,imx8qxp-ldb" }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx8qxp_ldb_dt_ids); - -static struct platform_driver imx8qxp_ldb_driver = { - .probe = imx8qxp_ldb_probe, - .remove = imx8qxp_ldb_remove, - .driver = { - .pm = &imx8qxp_ldb_pm_ops, - .name = DRIVER_NAME, - .of_match_table = imx8qxp_ldb_dt_ids, - }, -}; -module_platform_driver(imx8qxp_ldb_driver); - -MODULE_DESCRIPTION("i.MX8QXP LVDS Display Bridge(LDB)/Pixel Mapper bridge driver"); -MODULE_AUTHOR("Liu Ying "); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:" DRIVER_NAME); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/imx/Kconfig linux-imx-phytec/drivers/gpu/drm/bridge/imx/Kconfig --- linux-6.1.55/drivers/gpu/drm/bridge/imx/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/imx/Kconfig 2024-06-19 12:34:01.896254057 +0200 @@ -1,23 +1,5 @@ if ARCH_MXC || COMPILE_TEST -config DRM_IMX8QM_LDB - tristate "Freescale i.MX8QM LVDS display bridge" - depends on OF - depends on COMMON_CLK - select DRM_KMS_HELPER - help - Choose this to enable the internal LVDS Display Bridge(LDB) found in - Freescale i.MX8qm processor. Official name of LDB is pixel mapper. - -config DRM_IMX8QXP_LDB - tristate "Freescale i.MX8QXP LVDS display bridge" - depends on OF - depends on COMMON_CLK - select DRM_KMS_HELPER - help - Choose this to enable the internal LVDS Display Bridge(LDB) found in - Freescale i.MX8qxp processor. Official name of LDB is pixel mapper. - config DRM_IMX8QXP_PIXEL_COMBINER tristate "Freescale i.MX8QM/QXP pixel combiner" depends on OF diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/imx/Makefile linux-imx-phytec/drivers/gpu/drm/bridge/imx/Makefile --- linux-6.1.55/drivers/gpu/drm/bridge/imx/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/imx/Makefile 2024-06-19 12:34:01.896254057 +0200 @@ -1,9 +1,3 @@ -imx8qm-ldb-objs := imx-ldb-helper.o imx8qm-ldb-drv.o -obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o - -imx8qxp-ldb-objs := imx-ldb-helper.o imx8qxp-ldb-drv.o -obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o - obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/it6161.c linux-imx-phytec/drivers/gpu/drm/bridge/it6161.c --- linux-6.1.55/drivers/gpu/drm/bridge/it6161.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/it6161.c 2024-06-19 12:34:01.896254057 +0200 @@ -0,0 +1,2406 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "it6161.h" + +#define AUX_WAIT_TIMEOUT_MS 100 +#define DEFAULT_DRV_HOLD 0 + +#define RGB_24b 0x3E +#define RGB_18b 0x1E + +#define InvMCLK TRUE +#define PDREFCLK FALSE +#define SkipStg 4 +#define MShift 8 +#define PPSFFRdStg 0x04 +#define RegAutoSync TRUE + +#define LMDbgSel 0 /* 0~7 */ +#define InvPCLK FALSE +#define PDREFCNT 0 /* when PDREFCLK=TRUE, 0:div2, 1:div4, 2:div8, 3:divg16 */ +#define EnIOIDDQ FALSE +#define EnStb2Rst FALSE +#define EnExtStdby FALSE +#define EnStandby FALSE +#define MPLaneSwap FALSE +#define MPPNSwap FALSE /* TRUE: MTK , FALSE: Solomon */ + +/* PPI */ +#define EnContCK TRUE +#define HSSetNum 3 +#define EnDeSkew TRUE +#define PPIDbgSel 12 +#define RegIgnrNull 1 +#define RegIgnrBlk 1 +#define RegEnDummyECC 0 +#define EOTPSel 0 + +/* PPS option */ +#define EnMBPM FALSE /* enable MIPI Bypass Mode */ +#if (EnMBPM == TRUE) + #define PREC_Update TRUE /* enable P-timing update */ + #define MREC_Update TRUE /* enable M-timing update */ + #define EnTBPM TRUE /* enable HDMITX Bypass Mode */ +#else + #define PREC_Update FALSE + #define MREC_Update FALSE + #define EnTBPM FALSE +#endif + +#define REGSELDEF FALSE +#define EnHReSync FALSE +#define EnVReSync FALSE +#define EnFReSync FALSE +#define EnVREnh FALSE +#define EnVREnhSel 1 /* 0:Div2, 1:Div4, 2:Div8, 3:Div16, 4:Div32 */ +#define EnMAvg TRUE + +#define PShift 3 +#define EnFFAutoRst TRUE +#define RegEnSyncErr FALSE +#define EnTxCRC TRUE +#define TxCRCnum 0x20 + +#define ENABLE_MIPI_RX_EXTERNAL_CLOCK FALSE + +#define NRTXRCLK TRUE /* true:set TRCLK by self */ +#define RCLKFreqSel TRUE /* false: 10MHz(div1); true: 20 MHz(OSSDIV2) */ +#define ForceTxCLKStb TRUE + +#define HDMI_TX_PCLK_DIV2 FALSE + +#define HDMI_TX_MODE HDMI_TX_ENABLE_DE_ONLY + +enum hdmi_tx_mode { + HDMI_TX_NONE, + HDMI_TX_BY_PASS, + HDMI_TX_ENABLE_DE_ONLY, + HDMI_TX_ENABLE_PATTERN_GENERATOR, +}; + +enum it6161_active_level { + LOW, + HIGH, +}; + +const struct RegSetEntry HDMITX_Init_Table[] = { + {0x0F, 0x40, 0x00}, + /*PLL Reset */ + {0x62, 0x08, 0x00}, /* XP_RESETB */ + {0x64, 0x04, 0x00}, /* IP_RESETB */ + {0x0F, 0x01, 0x00}, /* bank 0 ;3 */ + {0x8D, 0xFF, CEC_I2C_SLAVE_ADDR}, /* EnCEC */ + {0xA9, 0x80, (EnTBPM << 7)}, + {0xBF, 0x80, (NRTXRCLK << 7)}, + + /* Initial Value */ + {0xF8, 0xFF, 0xC3}, + {0xF8, 0xFF, 0xA5}, + {0xF4, 0x0C, 0x00}, + {0xF3, 0x02, 0x00}, + {0xF8, 0xFF, 0xFF}, + {0x5A, 0x0C, 0x0C}, + {0xD1, 0x0A, ((ForceTxCLKStb) << 3) + 0x02}, + {0x5D, 0x04, ((RCLKFreqSel) << 2)}, + {0x65, 0x03, 0x00}, + {0x71, 0xF9, 0x18}, + {0xCF, 0xFF, 0x00}, + {0xd1, 0x02, 0x00}, + {0x59, 0xD0, 0x40}, + {0xE1, 0x20, 0x00}, + {0xF5, 0x40, 0x00}, + {0x05, 0xC0, 0x40}, /* Setup INT Pin: Active Low & Open-Drain */ + {0x0C, 0xFF, 0xFF}, + {0x0D, 0xFF, 0xFF}, + {0x0E, 0x03, 0x03}, /* Clear all Interrupt */ + {0x0C, 0xFF, 0x00}, + {0x0D, 0xFF, 0x00}, + {0x0E, 0x02, 0x00}, + {0x20, 0x01, 0x00} +}; + +const struct RegSetEntry HDMITX_DefaultVideo_Table[] = { + /* Config default output format */ + {0x72, 0xff, 0x00}, + {0x70, 0xff, 0x00}, +/* GenCSC\RGB2YUV_ITU709_16_235 */ + {0x72, 0xFF, 0x02}, + {0x73, 0xFF, 0x00}, + {0x74, 0xFF, 0x80}, + {0x75, 0xFF, 0x00}, + {0x76, 0xFF, 0xB8}, + {0x77, 0xFF, 0x05}, + {0x78, 0xFF, 0xB4}, + {0x79, 0xFF, 0x01}, + {0x7A, 0xFF, 0x93}, + {0x7B, 0xFF, 0x00}, + {0x7C, 0xFF, 0x49}, + {0x7D, 0xFF, 0x3C}, + {0x7E, 0xFF, 0x18}, + {0x7F, 0xFF, 0x04}, + {0x80, 0xFF, 0x9F}, + {0x81, 0xFF, 0x3F}, + {0x82, 0xFF, 0xD9}, + {0x83, 0xFF, 0x3C}, + {0x84, 0xFF, 0x10}, + {0x85, 0xFF, 0x3F}, + {0x86, 0xFF, 0x18}, + {0x87, 0xFF, 0x04}, + {0x88, 0xF0, 0x00}, +}; + +/* Config default HDMI Mode */ +const struct RegSetEntry HDMITX_SetHDMI_Table[] = { + {0xC0, 0x01, 0x01}, + {0xC1, 0x03, 0x03}, + {0xC6, 0x03, 0x03} +}; + +/* Config default avi infoframe */ +const struct RegSetEntry HDMITX_DefaultAVIInfo_Table[] = { + {0x0F, 0x01, 0x01}, + {0x58, 0xFF, 0x10}, + {0x59, 0xFF, 0x08}, + {0x5A, 0xFF, 0x00}, + {0x5B, 0xFF, 0x00}, + {0x5C, 0xFF, 0x00}, + {0x5D, 0xFF, 0x57}, + {0x5E, 0xFF, 0x00}, + {0x5F, 0xFF, 0x00}, + {0x60, 0xFF, 0x00}, + {0x61, 0xFF, 0x00}, + {0x62, 0xFF, 0x00}, + {0x63, 0xFF, 0x00}, + {0x64, 0xFF, 0x00}, + {0x65, 0xFF, 0x00}, + {0x0F, 0x01, 0x00}, + {0xCD, 0x03, 0x03} +}; + +/* Config default audio infoframe */ +const struct RegSetEntry HDMITX_DeaultAudioInfo_Table[] = { + {0x0F, 0x01, 0x01}, + {0x68, 0xFF, 0x00}, + {0x69, 0xFF, 0x00}, + {0x6A, 0xFF, 0x00}, + {0x6B, 0xFF, 0x00}, + {0x6C, 0xFF, 0x00}, + {0x6D, 0xFF, 0x71}, + {0x0F, 0x01, 0x00}, + {0xCE, 0x03, 0x03} +}; + +const struct RegSetEntry HDMITX_Aud_CHStatus_LPCM_20bit_48Khz[] = { + {0x0F, 0x01, 0x01}, + {0x33, 0xFF, 0x00}, + {0x34, 0xFF, 0x18}, + {0x35, 0xFF, 0x00}, + {0x91, 0xFF, 0x00}, + {0x92, 0xFF, 0x00}, + {0x93, 0xFF, 0x01}, + {0x94, 0xFF, 0x00}, + {0x98, 0xFF, 0x02}, + {0x99, 0xFF, 0xDA}, + {0x0F, 0x01, 0x00} +}; + +const struct RegSetEntry HDMITX_AUD_SPDIF_2ch_24bit[] = { + {0x0F, 0x11, 0x00}, + {0x04, 0x14, 0x04}, + {0xE0, 0xFF, 0xD1}, + {0xE1, 0xFF, 0x01}, + {0xE2, 0xFF, 0xE4}, + {0xE3, 0xFF, 0x10}, + {0xE4, 0xFF, 0x00}, + {0xE5, 0xFF, 0x00}, + {0x04, 0x14, 0x00} +}; + +const struct RegSetEntry HDMITX_PwrOn_Table[] = { + /* PwrOn RCLK , IACLK ,TXCLK */ + {0x0F, 0x70, 0x00}, + /* PLL PwrOn */ + /* PwrOn DRV */ + {0x61, 0x20, 0x00}, + /* PwrOn XPLL */ + {0x62, 0x44, 0x00}, + /* PwrOn IPLL */ + {0x64, 0x40, 0x00}, + /* PLL Reset OFF */ + /* DRV_RST */ + {0x61, 0x10, 0x00}, + /* XP_RESETB */ + {0x62, 0x08, 0x08}, + /* IP_RESETB */ + {0x64, 0x04, 0x04} +}; + +struct it6161 { + struct drm_bridge bridge; + struct drm_connector connector; + struct i2c_client *i2c_mipi_rx; + struct i2c_client *i2c_hdmi_tx; + struct device_node *host_node; + struct mipi_dsi_device *dsi; + struct mutex mode_lock; + + struct regmap *regmap_mipi_rx; + struct regmap *regmap_hdmi_tx; + + u32 it6161_addr_hdmi_tx; + + struct gpio_desc *enable_gpio; + + u32 hdmi_tx_pclk; + u32 mipi_rx_rclk; + + /* video mode output to hdmi tx */ + struct drm_display_mode display_mode; + struct hdmi_avi_infoframe source_avi_infoframe; + + u8 mipi_rx_lane_count; + bool enable_drv_hold; + u8 hdmi_tx_output_color_space; + u8 hdmi_tx_input_color_space; + u8 hdmi_tx_mode; + u8 support_audio; + bool hdmi_mode; + u8 bAudioChannelEnable; + u8 bridge_enable; +}; + +struct it6161 *it6161; + +static const struct regmap_range it6161_mipi_rx_bridge_volatile_ranges[] = { + {.range_min = 0, .range_max = 0xFF}, +}; + +static const struct regmap_access_table it6161_mipi_rx_bridge_volatile_table = { + .yes_ranges = it6161_mipi_rx_bridge_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(it6161_mipi_rx_bridge_volatile_ranges), +}; + +static const struct regmap_config it6161_mipi_rx_bridge_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = &it6161_mipi_rx_bridge_volatile_table, + .cache_type = REGCACHE_NONE, +}; + +static const struct regmap_range it6161_hdmi_tx_bridge_volatile_ranges[] = { + {.range_min = 0, .range_max = 0xFF}, +}; + +static const struct regmap_access_table it6161_hdmi_tx_bridge_volatile_table = { + .yes_ranges = it6161_hdmi_tx_bridge_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(it6161_hdmi_tx_bridge_volatile_ranges), +}; + +static const struct regmap_config it6161_hdmi_tx_bridge_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = &it6161_hdmi_tx_bridge_volatile_table, + .cache_type = REGCACHE_NONE, +}; + +static int it6161_mipi_rx_read(struct it6161 *it6161, u32 reg_addr) +{ + struct device *dev = &it6161->i2c_mipi_rx->dev; + u32 value; + int err; + + err = regmap_read(it6161->regmap_mipi_rx, reg_addr, &value); + if (err < 0) { + DRM_DEV_ERROR(dev, "mipi rx read failed reg[0x%x] err: %d", reg_addr, err); + return err; + } + + return value; +} + +static int it6161_mipi_rx_write(struct it6161 *it6161, u32 addr, u32 val) +{ + struct device *dev = &it6161->i2c_mipi_rx->dev; + int err; + + err = regmap_write(it6161->regmap_mipi_rx, addr, val); + if (err < 0) { + DRM_DEV_ERROR(dev, "mipi rx write failed reg[0x%x] = 0x%x err = %d", + addr, val, err); + return err; + } + + return 0; +} + +static int it6161_mipi_rx_set_bits(struct it6161 *it6161, u32 reg, + u32 mask, u32 value) +{ + struct device *dev = &it6161->i2c_mipi_rx->dev; + int err; + + err = regmap_update_bits(it6161->regmap_mipi_rx, reg, mask, value); + if (err < 0) { + DRM_DEV_ERROR(dev, "mipi rx set reg[0x%x] = 0x%x mask = 0x%x failed err %d", + reg, value, mask, err); + return err; + } + + return 0; +} + +static int it6161_hdmi_tx_read(struct it6161 *it6161, u32 reg_addr) +{ + struct device *dev = &it6161->i2c_mipi_rx->dev; + u32 value; + int err; + + err = regmap_read(it6161->regmap_hdmi_tx, reg_addr, &value); + if (err < 0) { + DRM_DEV_ERROR(dev, "hdmi tx read failed reg[0x%x] err: %d", + reg_addr, err); + return err; + } + + return value; +} + +static int it6161_hdmi_tx_write(struct it6161 *it6161, u32 addr, u32 val) +{ + struct device *dev = &it6161->i2c_mipi_rx->dev; + int err; + + err = regmap_write(it6161->regmap_hdmi_tx, addr, val); + + if (err < 0) { + DRM_DEV_ERROR(dev, "hdmi tx write failed reg[0x%x] = 0x%x err = %d", + addr, val, err); + return err; + } + + return 0; +} + +static int it6161_hdmi_tx_set_bits(struct it6161 *it6161, u32 reg, + u32 mask, u32 value) +{ + int err; + struct device *dev = &it6161->i2c_mipi_rx->dev; + + err = regmap_update_bits(it6161->regmap_hdmi_tx, reg, mask, value); + if (err < 0) { + DRM_DEV_ERROR(dev, "hdmi tx set reg[0x%x] = 0x%x mask = 0x%x failed err %d", + reg, value, mask, err); + return err; + } + + return 0; +} + +static inline int it6161_hdmi_tx_change_bank(struct it6161 *it6161, int x) +{ + return it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, x & 0x03); +} + +static inline struct it6161 *connector_to_it6161(struct drm_connector *c) +{ + return container_of(c, struct it6161, connector); +} + +static inline struct it6161 *bridge_to_it6161(struct drm_bridge *bridge) +{ + return container_of(bridge, struct it6161, bridge); +} + +static void mipi_rx_logic_reset(struct it6161 *it6161) +{ + it6161_mipi_rx_set_bits(it6161, 0x05, 0x08, 0x08); +} + +static void mipi_rx_logic_reset_release(struct it6161 *it6161) +{ + it6161_mipi_rx_set_bits(it6161, 0x05, 0x08, 0x00); +} + +static void it6161_mipi_rx_int_mask_disable(struct it6161 *it6161) +{ + it6161_mipi_rx_set_bits(it6161, 0x0F, 0x03, 0x00); + it6161_mipi_rx_write(it6161, 0x09, 0x00); + it6161_mipi_rx_write(it6161, 0x0A, 0x00); + it6161_mipi_rx_write(it6161, 0x0B, 0x00); +} + +static void it6161_mipi_rx_int_mask_enable(struct it6161 *it6161) +{ + it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, 0x00); + it6161_mipi_rx_write(it6161, 0x09, 0x11); + it6161_mipi_rx_write(it6161, 0x0A, 0xc0); + it6161_mipi_rx_write(it6161, 0x0B, 0x40); +} + +static void it6161_hdmi_tx_int_mask_disable(struct it6161 *it6161) +{ + it6161_mipi_rx_set_bits(it6161, 0x0F, 0x03, 0x00); + it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK1, 0xFF); + it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK3, 0xFF); +} + +static void it6161_hdmi_tx_int_mask_enable(struct it6161 *it6161) +{ + it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, 0x00); + it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK1, + ~(B_TX_AUDIO_OVFLW_MASK | B_TX_DDC_FIFO_ERR_MASK | + B_TX_DDC_BUS_HANG_MASK | B_TX_HPD_MASK)); + it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK3, ~B_TX_VIDSTABLE_MASK); +} + +static void it6161_hdmi_tx_write_table(struct it6161 *it6161, + const struct RegSetEntry table[], int size) +{ + int i; + + for (i = 0; i < size; i++) { + if (table[i].mask == 0 && table[i].value == 0) + msleep(table[i].offset); + else if (table[i].mask == 0xFF) + it6161_hdmi_tx_write(it6161, table[i].offset, table[i].value); + else + it6161_hdmi_tx_set_bits(it6161, table[i].offset, table[i].mask, table[i].value); + } +} + +static inline void it6161_set_interrupts_active_level(enum it6161_active_level level) +{ + it6161_mipi_rx_set_bits(it6161, 0x0D, 0x02, level == HIGH ? 0x02 : 0x00); + it6161_hdmi_tx_set_bits(it6161, 0x05, 0xC0, level == HIGH ? 0x80 : 0x40); +} + +static void hdmi_tx_init(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + + DRM_DEV_DEBUG_DRIVER(dev, "it6161 init\n"); + + it6161_hdmi_tx_write_table(it6161, HDMITX_Init_Table, + ARRAY_SIZE(HDMITX_Init_Table)); + it6161_hdmi_tx_write_table(it6161, HDMITX_PwrOn_Table, + ARRAY_SIZE(HDMITX_PwrOn_Table)); + it6161_hdmi_tx_write_table(it6161, HDMITX_DefaultVideo_Table, + ARRAY_SIZE(HDMITX_DefaultVideo_Table)); + it6161_hdmi_tx_write_table(it6161, HDMITX_SetHDMI_Table, + ARRAY_SIZE(HDMITX_SetHDMI_Table)); + it6161_hdmi_tx_write_table(it6161, HDMITX_DefaultAVIInfo_Table, + ARRAY_SIZE(HDMITX_DefaultAVIInfo_Table)); + it6161_hdmi_tx_write_table(it6161, HDMITX_DeaultAudioInfo_Table, + ARRAY_SIZE(HDMITX_DeaultAudioInfo_Table)); + it6161_hdmi_tx_write_table(it6161, HDMITX_Aud_CHStatus_LPCM_20bit_48Khz, + ARRAY_SIZE(HDMITX_Aud_CHStatus_LPCM_20bit_48Khz)); + it6161_hdmi_tx_write_table(it6161, HDMITX_AUD_SPDIF_2ch_24bit, + ARRAY_SIZE(HDMITX_AUD_SPDIF_2ch_24bit)); +} + +static bool mipi_rx_get_m_video_stable(struct it6161 *it6161) +{ + return it6161_mipi_rx_read(it6161, 0x0D) & 0x10; +} + +static bool mipi_rx_get_p_video_stable(struct it6161 *it6161) +{ + return it6161_mipi_rx_read(it6161, 0x0D) & 0x20; +} + +static void mipi_rx_afe_configuration(struct it6161 *it6161, u8 data_id) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + u8 MPLaneNum = (it6161->mipi_rx_lane_count - 1); + + DRM_DEV_DEBUG_DRIVER(dev, "afe configuration data_id: 0x%02x", data_id); + + if (data_id == RGB_18b) { + if (MPLaneNum == 3) + /* MPPCLKSel = 1; 4-lane : MCLK = 1/1 PCLK */ + it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x02); + else if (MPLaneNum == 1) + /* MPPCLKSel = 6; 2-lane : MCLK = 1/1 PCLK */ + it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x05); + else if (MPLaneNum == 0) + /* MPPCLKSel = 8; 1-lane : MCLK = 3/4 PCLK */ + it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x08); + } else { + if (MPLaneNum == 3) + /* MPPCLKSel = 1; 4-lane : MCLK = 3/4 PCLK */ + it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x02); + else if (MPLaneNum == 1) + /* MPPCLKSel = 3; 2-lane : MCLK = 3/4 PCLK */ + it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x05); + else if (MPLaneNum == 0) + /* MPPCLKSel = 5; 1-lane : MCLK = 3/4 PCLK */ + it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x0b); + } +} + +static void mipi_rx_configuration(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + u8 mipi_lane_config = (it6161->mipi_rx_lane_count - 1); + + DRM_DEV_DEBUG_DRIVER(dev, "MIPI_LANE=%d\n", it6161->mipi_rx_lane_count); + + it6161_mipi_rx_set_bits(it6161, 0x10, 0x0F, 0x0F); + msleep(1); + it6161_mipi_rx_set_bits(it6161, 0x10, 0x0F, 0x00); + + mipi_rx_logic_reset(it6161); + msleep(1); + mipi_rx_logic_reset_release(it6161); + + it6161_mipi_rx_int_mask_disable(it6161); + + /* setup INT pin: active low */ + it6161_mipi_rx_set_bits(it6161, 0x0d, 0x02, 0x00); + + it6161_mipi_rx_set_bits(it6161, 0x0C, 0x0F, + (MPLaneSwap << 3) + (MPPNSwap << 2) + mipi_lane_config); + + it6161_mipi_rx_set_bits(it6161, 0x11, 0x3F, + (EnIOIDDQ << 5) + (EnStb2Rst << 4) + (EnExtStdby << 3) + + (EnStandby << 2) + (InvPCLK << 1) + InvMCLK); + + it6161_mipi_rx_set_bits(it6161, 0x12, 0x03, (PDREFCNT << 1) + PDREFCLK); + + it6161_mipi_rx_set_bits(it6161, 0x18, 0xf7, + (RegEnSyncErr << 7) + (SkipStg << 4) + HSSetNum); + it6161_mipi_rx_set_bits(it6161, 0x19, 0xf3, + (PPIDbgSel << 4) + (EnContCK << 1) + EnDeSkew); + it6161_mipi_rx_set_bits(it6161, 0x20, 0xf7, + (EOTPSel << 4) + (RegEnDummyECC << 2) + (RegIgnrBlk << 1) + RegIgnrNull); + it6161_mipi_rx_set_bits(it6161, 0x21, 0x07, LMDbgSel); + + it6161_mipi_rx_set_bits(it6161, 0x44, 0x3a, + (MREC_Update << 5) + (PREC_Update << 4) + (REGSELDEF << 3) + (RegAutoSync << 1)); + it6161_mipi_rx_set_bits(it6161, 0x4B, 0x1f, + (EnFReSync << 4) + (EnVREnh << 3) + EnVREnhSel); + it6161_mipi_rx_write(it6161, 0x4C, PPSFFRdStg); + it6161_mipi_rx_set_bits(it6161, 0x4D, 0x01, (PPSFFRdStg >> 8) & 0x01); + it6161_mipi_rx_set_bits(it6161, 0x4E, 0x0C, + (EnVReSync << 3) + (EnHReSync << 2)); + it6161_mipi_rx_set_bits(it6161, 0x4F, 0x03, EnFFAutoRst); + + it6161_mipi_rx_set_bits(it6161, 0x70, 0x01, EnMAvg); + it6161_mipi_rx_write(it6161, 0x72, MShift); + it6161_mipi_rx_write(it6161, 0x73, PShift); + it6161_mipi_rx_set_bits(it6161, 0x80, 0x20, ENABLE_MIPI_RX_EXTERNAL_CLOCK << 5); + + it6161_mipi_rx_write(it6161, 0x21, 0x00); + it6161_mipi_rx_set_bits(it6161, 0x84, 0x70, 0x00); + + it6161_mipi_rx_set_bits(it6161, 0xA0, 0x01, EnMBPM); + + /* enable auto detect format */ + it6161_mipi_rx_set_bits(it6161, 0x21, 0x08, 0x08); + + it6161_mipi_rx_set_bits(it6161, 0x70, 0x01, EnMAvg); + /* Video Clock Domain Reset */ + it6161_mipi_rx_set_bits(it6161, 0x05, 0x02, 0x02); + + if (EnMBPM) { + /* HRS offset */ + it6161_mipi_rx_write(it6161, 0xA1, 0x00); + /* VRS offset */ + it6161_mipi_rx_write(it6161, 0xA2, 0x00); + it6161_mipi_rx_write(it6161, 0xA3, 0x08); + it6161_mipi_rx_write(it6161, 0xA5, 0x04); + } + + if (REGSELDEF == false) { + it6161_mipi_rx_set_bits(it6161, 0x31, 0x80, 0x00); + it6161_mipi_rx_set_bits(it6161, 0x33, 0x80, 0x00); + it6161_mipi_rx_set_bits(it6161, 0x35, 0x80, 0x00); + it6161_mipi_rx_set_bits(it6161, 0x37, 0x80, 0x00); + it6161_mipi_rx_set_bits(it6161, 0x39, 0x80, 0x00); + it6161_mipi_rx_set_bits(it6161, 0x3A, 0x80, 0x00); + it6161_mipi_rx_set_bits(it6161, 0x3C, 0x80, 0x00); + it6161_mipi_rx_set_bits(it6161, 0x3E, 0x80, 0x00); + it6161_mipi_rx_set_bits(it6161, 0x41, 0x80, 0x00); + it6161_mipi_rx_set_bits(it6161, 0x43, 0x80, 0x00); + } +} + +static void mipi_rx_init(struct it6161 *it6161) +{ + mipi_rx_configuration(it6161); + /* Enable MPRX clock domain */ + it6161_mipi_rx_set_bits(it6161, 0x05, 0x03, 0x00); +} + +static void hdmi_tx_video_reset(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + + DRM_DEV_DEBUG_DRIVER(dev, "reg04: 0x%02x reg05: 0x%02x reg6: 0x%02x reg07: 0x%02x reg08: 0x%02x reg0e: 0x%02x", + it6161_hdmi_tx_read(it6161, 0x04), + it6161_hdmi_tx_read(it6161, 0x05), + it6161_hdmi_tx_read(it6161, 0x06), + it6161_hdmi_tx_read(it6161, 0x07), + it6161_hdmi_tx_read(it6161, 0x08), + it6161_hdmi_tx_read(it6161, 0x0e)); + + it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_VID_RST, B_HDMITX_VID_RST); + it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_VID_RST, 0x00); + msleep(10); +} + +/* DDC master will set to be host */ +static void it6161_hdmi_tx_clear_ddc_fifo(struct it6161 *it6161) +{ + it6161_hdmi_tx_change_bank(it6161, 0); + it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, + B_TX_MASTERDDC | B_TX_MASTERHOST); + it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_FIFO_CLR); + it6161_hdmi_tx_set_bits(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERHOST, 0x00); +} + +static void hdmi_tx_generate_blank_timing(struct it6161 *it6161) +{ + struct drm_display_mode *display_mode = &it6161->display_mode; + bool force_hdmi_tx_clock_stable = true; + bool force_hdmi_tx_video_stable = true; + bool hdmi_tx_by_pass_mode = false; + bool de_generation = false; + bool enable_de_only = true; + u8 polarity; + u16 hsync_start, hsync_end, vsync_start, vsync_end, htotal, hde_start, vtotal; + u16 vsync_start_2nd = 0, vsync_end_2nd = 0, vsync_rising_at_h_2nd; + + polarity = + ((display_mode->flags & DRM_MODE_FLAG_PHSYNC) == DRM_MODE_FLAG_PHSYNC) ? 0x02 : 0x00; + polarity |= + ((display_mode->flags & DRM_MODE_FLAG_PVSYNC) == DRM_MODE_FLAG_PVSYNC) ? 0x04 : 0x00; + + hsync_start = display_mode->hsync_start - display_mode->hdisplay - 1; + hsync_end = hsync_start + display_mode->hsync_end - display_mode->hsync_start; + vsync_rising_at_h_2nd = hsync_start + display_mode->htotal / 2; + hde_start = display_mode->htotal - display_mode->hsync_start; + + it6161_hdmi_tx_set_bits(it6161, 0xD1, 0x0C, + force_hdmi_tx_clock_stable << 3 | force_hdmi_tx_video_stable << 2); + it6161_hdmi_tx_set_bits(it6161, 0xA9, 0x80, hdmi_tx_by_pass_mode << 7); + it6161_hdmi_tx_set_bits(it6161, 0x90, 0x01, de_generation); + it6161_hdmi_tx_write(it6161, 0x91, vsync_rising_at_h_2nd >> 4); + it6161_hdmi_tx_set_bits(it6161, 0x90, 0xF0, (vsync_rising_at_h_2nd & 0x00F) << 4); + it6161_hdmi_tx_set_bits(it6161, 0x90, 0x06, polarity); + it6161_hdmi_tx_write(it6161, 0x95, (u8) hsync_start); + it6161_hdmi_tx_write(it6161, 0x96, (u8) hsync_end); + it6161_hdmi_tx_write(it6161, 0x97, (hsync_end & 0x0F00) >> 4 | hsync_start >> 8); + + vsync_start = display_mode->vsync_start - display_mode->vdisplay; + vsync_end = display_mode->vsync_end - display_mode->vdisplay; + + if ((display_mode->flags & DRM_MODE_FLAG_INTERLACE) != DRM_MODE_FLAG_INTERLACE) { + vsync_start_2nd = 0x0FFF; + vsync_end_2nd = 0x3F; + vtotal = display_mode->vtotal - 1; + it6161_hdmi_tx_set_bits(it6161, 0xA5, 0x10, 0x00); + } else { + vtotal = display_mode->vtotal * 2; + it6161_hdmi_tx_set_bits(it6161, 0xA5, 0x10, 0x10); + } + it6161_hdmi_tx_write(it6161, 0xA0, (u8) vsync_start); + it6161_hdmi_tx_write(it6161, 0xA1, (vsync_end & 0x0F) << 4 | vsync_start >> 8); + it6161_hdmi_tx_write(it6161, 0xA2, (u8) vsync_start_2nd); + it6161_hdmi_tx_write(it6161, 0xA6, (vsync_end_2nd & 0xF0) | vsync_end >> 4); + it6161_hdmi_tx_write(it6161, 0xA3, (vsync_end_2nd & 0x0F) << 4 | vsync_start_2nd >> 8); + it6161_hdmi_tx_write(it6161, 0xA4, vsync_rising_at_h_2nd); + + it6161_hdmi_tx_set_bits(it6161, 0xB1, 0x51, + (hsync_end & 0x1000) >> 6 | (hsync_start & 0x1000) >> 8 | hde_start >> 12); + it6161_hdmi_tx_set_bits(it6161, 0xA5, 0x2F, + enable_de_only << 5 | vsync_rising_at_h_2nd >> 8); + it6161_hdmi_tx_set_bits(it6161, 0xB2, 0x05, + (vsync_rising_at_h_2nd & 0x1000) >> 10 | (vsync_rising_at_h_2nd & 0x1000) >> 12); + + htotal = display_mode->htotal - 1; + it6161_hdmi_tx_set_bits(it6161, 0x90, 0xF0, (htotal & 0x0F) << 4); + it6161_hdmi_tx_write(it6161, 0x91, (htotal & 0x0FF0) >> 4); + it6161_hdmi_tx_set_bits(it6161, 0xB2, 0x01, (htotal & 0x1000) >> 12); + it6161_hdmi_tx_write(it6161, 0x98, vtotal & 0x0FF); + it6161_hdmi_tx_write(it6161, 0x99, (vtotal & 0xF00) >> 8); +} + +/* force abort DDC and reset DDC bus */ +static void it6161_hdmi_tx_abort_ddc(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + u8 sw_reset, ddc_master, retry = 2; + u8 uc, timeout, i; + + DRM_DEV_DEBUG_DRIVER(dev, "ddc abort\n"); + /* save the sw reset, ddc master and cp desire setting */ + sw_reset = it6161_hdmi_tx_read(it6161, REG_TX_SW_RST); + ddc_master = it6161_hdmi_tx_read(it6161, REG_TX_DDC_MASTER_CTRL); + + it6161_hdmi_tx_write(it6161, REG_TX_SW_RST, sw_reset | B_TX_HDCP_RST_HDMITX); + it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST); + + /* do abort DDC */ + for (i = 0; i < retry; i++) { + it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_DDC_ABORT); + it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_GEN_SCLCLK); + + for (timeout = 0; timeout < 200; timeout++) { + uc = it6161_hdmi_tx_read(it6161, REG_TX_DDC_STATUS); + if (uc & B_TX_DDC_DONE) + break; + + if (uc & (B_TX_DDC_NOACK | B_TX_DDC_WAITBUS | B_TX_DDC_ARBILOSE)) { + DRM_DEV_ERROR(dev, "it6161_hdmi_tx_abort_ddc Fail by reg16=%02X\n", (int)uc); + break; + } + /* delay 1 ms to stable */ + msleep(1); + } + } +} + +static bool hdmi_tx_get_video_state(struct it6161 *it6161) +{ + return B_TXVIDSTABLE & it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS); +} + +static inline bool hdmi_tx_get_sink_hpd(struct it6161 *it6161) +{ + return it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS) & B_TX_HPDETECT; +} + +static bool it6161_ddc_op_finished(struct it6161 *it6161) +{ + int reg16 = it6161_hdmi_tx_read(it6161, REG_TX_DDC_STATUS); + + if (reg16 < 0) + return false; + + return (reg16 & B_TX_DDC_DONE) == B_TX_DDC_DONE; +} + +static int it6161_ddc_wait(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_mipi_rx->dev; + int status; + unsigned long timeout; + + timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1; + + while (!it6161_ddc_op_finished(it6161)) { + if (time_after(jiffies, timeout)) { + DRM_DEV_ERROR(dev, "Timed out waiting AUX to finish"); + return -ETIMEDOUT; + } + usleep_range(1000, 2000); + } + + status = it6161_hdmi_tx_read(it6161, REG_TX_DDC_STATUS); + if (status < 0) { + DRM_DEV_ERROR(dev, "Failed to read DDC channel: 0x%02x", status); + return status; + } + + if (status & B_TX_DDC_DONE) + return 0; + else { + DRM_DEV_ERROR(dev, "DDC error: 0x%02x", status); + return -EIO; + } +} + +static void hdmi_tx_ddc_operation(struct it6161 *it6161, u8 addr, u8 offset, u8 size, + u8 segment, u8 cmd) +{ + size = min_t(u8, size, DDC_FIFO_MAXREQ); + it6161_hdmi_tx_change_bank(it6161, 0); + it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST); + it6161_hdmi_tx_write(it6161, REG_TX_DDC_HEADER, addr); + it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQOFF, offset); + it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQCOUNT, size); + it6161_hdmi_tx_write(it6161, REG_TX_DDC_EDIDSEG, segment); + it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, cmd); +} + +static int it6161_ddc_get_edid_operation(struct it6161 *it6161, u8 *buffer, + u8 segment, u8 offset, u8 size) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + int status, i; + + if (!buffer) + return -ENOMEM; + + if (it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1) & B_TX_INT_DDC_BUS_HANG) { + DRM_DEV_ERROR(dev, "Called it6161_hdmi_tx_abort_ddc()"); + it6161_hdmi_tx_abort_ddc(it6161); + } + + it6161_hdmi_tx_clear_ddc_fifo(it6161); + status = it6161_ddc_wait(it6161); + if (status < 0) + goto error; + + hdmi_tx_ddc_operation(it6161, DDC_EDID_ADDRESS, offset, size, segment, CMD_EDID_READ); + status = it6161_ddc_wait(it6161); + if (status < 0) + goto error; + + for (i = 0; i < size; i++) { + status = it6161_hdmi_tx_read(it6161, REG_TX_DDC_READFIFO); + if (status < 0) + goto error; + + buffer[i] = status; + } + + return i; + +error: + return status; +} + +static int it6161_get_edid_block(void *data, u8 *buf, u32 block_num, size_t len) +{ + struct it6161 *it6161 = data; + u8 offset, step = 8; + int ret; + + step = min_t(u8, step, DDC_FIFO_MAXREQ); + + for (offset = 0; offset < len; offset += step) { + ret = it6161_ddc_get_edid_operation(it6161, buf + offset, + block_num / 2, (block_num % 2) * EDID_LENGTH + offset, step); + if (ret < 0) + return ret; + } + return 0; +} + +static void hdmi_tx_set_capability_from_edid_parse(struct it6161 *it6161, struct edid *edid) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + struct drm_display_info *info = &it6161->connector.display_info; + + it6161->hdmi_mode = drm_detect_hdmi_monitor(edid); + it6161->support_audio = drm_detect_monitor_audio(edid); + + it6161->hdmi_tx_output_color_space = OUTPUT_COLOR_MODE; + it6161->hdmi_tx_input_color_space = INPUT_COLOR_MODE; + if (it6161->hdmi_tx_output_color_space == F_MODE_YUV444) { + if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) != DRM_COLOR_FORMAT_YCBCR444) { + it6161->hdmi_tx_output_color_space &= ~F_MODE_CLRMOD_MASK; + it6161->hdmi_tx_output_color_space |= F_MODE_RGB444; + } + } + + if (it6161->hdmi_tx_output_color_space == F_MODE_YUV422) { + if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) != DRM_COLOR_FORMAT_YCBCR422) { + it6161->hdmi_tx_output_color_space &= ~F_MODE_CLRMOD_MASK; + it6161->hdmi_tx_output_color_space |= F_MODE_RGB444; + } + } + DRM_DEV_DEBUG_DRIVER(dev, "%s mode, monitor %ssupport audio, outputcolormode:%d color_formats:0x%08x color_depth:%d", + it6161->hdmi_mode ? "HDMI" : "DVI", + it6161->support_audio ? "" : "not ", + it6161->hdmi_tx_output_color_space, + info->color_formats, + info->bpc); + + if ((info->color_formats & DRM_COLOR_FORMAT_RGB444) == DRM_COLOR_FORMAT_RGB444) + DRM_DEV_INFO(dev, "support RGB444 output"); + if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) == DRM_COLOR_FORMAT_YCBCR444) + DRM_DEV_INFO(dev, "support YUV444 output"); + if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) == DRM_COLOR_FORMAT_YCBCR422) + DRM_DEV_INFO(dev, "support YUV422 output"); +} + +static void it6161_variable_config(struct it6161 *it6161) +{ + it6161->hdmi_tx_mode = HDMI_TX_MODE; + it6161->mipi_rx_lane_count = MIPI_RX_LANE_COUNT; +} + +static struct edid *it6161_get_edid(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + struct edid *edid; + + edid = drm_do_get_edid(&it6161->connector, it6161_get_edid_block, it6161); + if (!edid) { + DRM_DEV_ERROR(dev, "Failed to read EDID\n"); + return 0; + } + + hdmi_tx_set_capability_from_edid_parse(it6161, edid); + + return edid; +} + +static int it6161_get_modes(struct drm_connector *connector) +{ + struct it6161 *it6161 = connector_to_it6161(connector); + int err, num_modes = 0; + struct edid *edid; + struct device *dev = &it6161->i2c_mipi_rx->dev; + + mutex_lock(&it6161->mode_lock); + + edid = it6161_get_edid(it6161); + if (!edid) { + DRM_DEV_ERROR(dev, "Failed to read EDID\n"); + return 0; + } + + err = drm_connector_update_edid_property(connector, edid); + if (err) { + DRM_DEV_ERROR(dev, "Failed to update EDID property: %d", err); + goto unlock; + } + + num_modes = drm_add_edid_modes(connector, edid); + + kfree(edid); +unlock: + DRM_DEV_DEBUG_DRIVER(dev, "edid mode number:%d", num_modes); + mutex_unlock(&it6161->mode_lock); + + return num_modes; +} + +static const struct drm_connector_helper_funcs it6161_connector_helper_funcs = { + .get_modes = it6161_get_modes, +}; + +static enum drm_connector_status it6161_detect(struct drm_connector *connector, bool force) +{ + struct it6161 *it6161 = connector_to_it6161(connector); + struct device *dev = &it6161->i2c_hdmi_tx->dev; + enum drm_connector_status status = connector_status_disconnected; + bool hpd; + + hpd = hdmi_tx_get_sink_hpd(it6161); + if (hpd) { + it6161_variable_config(it6161); + status = connector_status_connected; + } + DRM_DEV_INFO(dev, "hpd:%s\n", hpd ? "high" : "low"); + + it6161_set_interrupts_active_level(HIGH); + it6161_mipi_rx_int_mask_enable(it6161); + it6161_hdmi_tx_int_mask_enable(it6161); + + return status; +} + +static const struct drm_connector_funcs it6161_connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = it6161_detect, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static int it6161_attach_dsi(struct it6161 *it6161) +{ + struct mipi_dsi_host *host; + struct mipi_dsi_device *dsi; + int ret = 0; + const struct mipi_dsi_device_info info = {.type = "it6161", }; + struct device *dev = &it6161->i2c_hdmi_tx->dev; + + DRM_DEV_DEBUG_DRIVER(dev, "attach\n"); + host = of_find_mipi_dsi_host_by_node(it6161->host_node); + if (!host) { + DRM_DEV_ERROR(dev, "it6161 failed to find dsi host\n"); + return -EPROBE_DEFER; + } + + dsi = mipi_dsi_device_register_full(host, &info); + if (IS_ERR(dsi)) { + DRM_DEV_ERROR(dev, "it6161 failed to create dsi device\n"); + ret = PTR_ERR(dsi); + goto err_dsi_device; + } + + it6161->dsi = dsi; + + dsi->lanes = MIPI_RX_LANE_COUNT; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE; + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + DRM_DEV_ERROR(dev, "it6161 failed to attach dsi to host\n"); + goto err_dsi_attach; + } + + return 0; + +err_dsi_attach: + mipi_dsi_device_unregister(dsi); +err_dsi_device: + return ret; +} + +static int it6161_connector_init(struct drm_bridge *bridge, struct it6161 *it6161) +{ + struct device *dev; + int ret; + + dev = &it6161->i2c_mipi_rx->dev; + + if (!bridge->encoder) { + DRM_DEV_ERROR(dev, "Parent encoder object not found"); + return -ENODEV; + } + + it6161->connector.polled = DRM_CONNECTOR_POLL_HPD; + + ret = drm_connector_init(bridge->dev, &it6161->connector, + &it6161_connector_funcs, DRM_MODE_CONNECTOR_HDMIA); + if (ret < 0) { + DRM_DEV_ERROR(dev, "Failed to initialize connector: %d", ret); + return ret; + } + + drm_connector_helper_add(&it6161->connector, &it6161_connector_helper_funcs); + drm_connector_attach_encoder(&it6161->connector, bridge->encoder); + + return 0; +} + +static int it6161_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct it6161 *it6161 = bridge_to_it6161(bridge); + int ret; + + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + ret = it6161_connector_init(bridge, it6161); + if (ret < 0) + return ret; + } + + ret = it6161_attach_dsi(it6161); + + return ret; +} + +static void it6161_detach_dsi(struct it6161 *it6161) +{ + mipi_dsi_detach(it6161->dsi); + mipi_dsi_device_unregister(it6161->dsi); +} + +static void it6161_bridge_detach(struct drm_bridge *bridge) +{ + struct it6161 *it6161 = bridge_to_it6161(bridge); + + drm_connector_unregister(&it6161->connector); + drm_connector_cleanup(&it6161->connector); + it6161_detach_dsi(it6161); +} + +static enum drm_mode_status +it6161_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + if (mode->clock > 108000) + return MODE_CLOCK_HIGH; + + /* TODO, Only 480p60 work with imx8ulp now */ + if (mode->vdisplay > 480) + return MODE_BAD_VVALUE; + + return MODE_OK; +} + +static void it6161_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct it6161 *it6161 = bridge_to_it6161(bridge); + struct device *dev = &it6161->i2c_hdmi_tx->dev; + u8 polarity; + + DRM_DEV_DEBUG_DRIVER(dev, " mode " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); + DRM_DEV_DEBUG_DRIVER(dev, "adj mode " DRM_MODE_FMT "\n", DRM_MODE_ARG(adjusted_mode)); + + memcpy(&it6161->display_mode, mode, sizeof(struct drm_display_mode)); + + polarity = ((adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) == DRM_MODE_FLAG_PHSYNC) ? 0x01 : 0x00; + polarity |= ((adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) == DRM_MODE_FLAG_PVSYNC) ? 0x02 : 0x00; + + it6161_mipi_rx_set_bits(it6161, 0x4E, 0x03, polarity); +} + +static void it6161_bridge_enable(struct drm_bridge *bridge) +{ + struct it6161 *it6161 = bridge_to_it6161(bridge); + struct device *dev = &it6161->i2c_hdmi_tx->dev; + + DRM_DEV_DEBUG_DRIVER(dev, "start"); + + if (it6161->bridge_enable) + return; + + mipi_rx_init(it6161); + hdmi_tx_init(it6161); + it6161_set_interrupts_active_level(HIGH); + it6161_mipi_rx_int_mask_enable(it6161); + it6161_hdmi_tx_int_mask_enable(it6161); + + it6161->bridge_enable = true; + +} + +static void it6161_bridge_disable(struct drm_bridge *bridge) +{ + struct it6161 *it6161 = bridge_to_it6161(bridge); + struct device *dev = &it6161->i2c_hdmi_tx->dev; + + DRM_DEV_DEBUG_DRIVER(dev, "start"); + + /* only keep HPD for cabe detect */ + it6161_mipi_rx_int_mask_disable(it6161); + it6161_hdmi_tx_int_mask_disable(it6161); + it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, 0x00); + it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK1, ~B_TX_HPD_MASK); + + it6161->bridge_enable = false; +} + +static enum drm_connector_status it6161_bridge_detect(struct drm_bridge *bridge) +{ + struct it6161 *it6161 = bridge_to_it6161(bridge); + enum drm_connector_status status = connector_status_disconnected; + bool hpd = hdmi_tx_get_sink_hpd(it6161); + struct device *dev = &it6161->i2c_hdmi_tx->dev; + + DRM_DEV_DEBUG_DRIVER(dev, "hpd:%s", hpd ? "high" : "low"); + + if (hpd) { + it6161_variable_config(it6161); + status = connector_status_connected; + } + + it6161_set_interrupts_active_level(HIGH); + it6161_mipi_rx_int_mask_enable(it6161); + it6161_hdmi_tx_int_mask_enable(it6161); + + return status; +} + +static struct edid *it6161_bridge_get_edid(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct it6161 *it6161 = bridge_to_it6161(bridge); + + return it6161_get_edid(it6161); +} + +static const struct drm_bridge_funcs it6161_bridge_funcs = { + .attach = it6161_bridge_attach, + .detach = it6161_bridge_detach, + .mode_valid = it6161_bridge_mode_valid, + .mode_set = it6161_bridge_mode_set, + .enable = it6161_bridge_enable, + .disable = it6161_bridge_disable, + .detect = it6161_bridge_detect, + .get_edid = it6161_bridge_get_edid, +}; + +static bool it6161_check_device_ready(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + u8 Vendor_ID[2], Device_ID[2]; + + Vendor_ID[0] = it6161_mipi_rx_read(it6161, 0x00); + Vendor_ID[1] = it6161_mipi_rx_read(it6161, 0x01); + Device_ID[0] = it6161_mipi_rx_read(it6161, 0x02); + Device_ID[1] = it6161_mipi_rx_read(it6161, 0x03); + if (Vendor_ID[0] == 0x54 && Vendor_ID[1] == 0x49 && + Device_ID[0] == 0x61 && Device_ID[1] == 0x61) { + DRM_DEV_INFO(dev, "Find it6161 revision: 0x%2x", + (u32) it6161_mipi_rx_read(it6161, 0x04)); + return true; + } + DRM_DEV_INFO(dev, "find it6161 Fail"); + return false; +} + +static void it6161_hdmi_tx_set_av_mute(struct it6161 *it6161, u8 bEnable) +{ + it6161_hdmi_tx_change_bank(it6161, 0); + it6161_hdmi_tx_set_bits(it6161, REG_TX_GCP, + B_TX_SETAVMUTE, bEnable ? B_TX_SETAVMUTE : 0); + it6161_hdmi_tx_write(it6161, REG_TX_PKT_GENERAL_CTRL, + B_TX_ENABLE_PKT | B_TX_REPEAT_PKT); +} + +static void hdmi_tx_setup_pclk_div2(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + + if (HDMI_TX_PCLK_DIV2) { + DRM_DEV_DEBUG_DRIVER(dev, "PCLK Divided by 2 mode"); + it6161_hdmi_tx_set_bits(it6161, REG_TX_INPUT_MODE, + B_TX_PCLKDIV2, B_TX_PCLKDIV2); + } +} + +/************************************************************************* + * Function: hdmi_tx_setup_csc + * Parameter: input_mode - + * D[1:0] - Color Mode + * D[4] - Colorimetry 0: ITU_BT601 1: ITU_BT709 + * D[5] - Quantization 0: 0_255 1: 16_235 + * D[6] - Up/Dn Filter 'Required' + * 0: no up/down filter + * 1: enable up/down filter when csc need. + * D[7] - Dither Filter 'Required' + * 0: no dither enabled. + * 1: enable dither and dither free go "when required". + * output_mode - + * D[1:0] - Color mode. + * Return: N/A + * Remark: reg72~reg8D will be programmed depended the input with table + * **********************************************************************/ +static void hdmi_tx_setup_csc(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + u8 ucData, csc = 0, i; + u8 filter = 0; /* filter is for Video CTRL DN_FREE_GO,EN_DITHER,and ENUDFILT */ + u8 input_mode = it6161->hdmi_tx_input_color_space; + u8 output_mode = it6161->hdmi_tx_output_color_space; + u8 *ptable = NULL; + + /* (1) YUV422 in,RGB/YUV444 output (Output is 8-bit,input is 12-bit) + * (2) YUV444/422 in,RGB output (CSC enable,and output is not YUV422) + * (3) RGB in,YUV444 output (CSC enable,and output is not YUV422) + * + * YUV444/RGB24 <-> YUV422 need set up/down filter. + */ + DRM_DEV_DEBUG_DRIVER(dev, "hdmi_tx_setup_csc(u8 input_mode = %x,u8 output_mode = %x)\n", + (int)input_mode, (int)output_mode); + + switch (input_mode & F_MODE_CLRMOD_MASK) { + /* YUV444 INPUT */ + case F_MODE_YUV444: + switch (output_mode & F_MODE_CLRMOD_MASK) { + case F_MODE_YUV444: + csc = B_HDMITX_CSC_BYPASS; + break; + case F_MODE_YUV422: + /* YUV444 to YUV422 need up/down filter for processing. */ + if (input_mode & F_VIDMODE_EN_UDFILT) + filter |= B_TX_EN_UDFILTER; + csc = B_HDMITX_CSC_BYPASS; + break; + case F_MODE_RGB444: + csc = B_HDMITX_CSC_YUV2RGB; + /* YUV444 to RGB24 need dither */ + if (input_mode & F_VIDMODE_EN_DITHER) + filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO; + break; + } + break; + + /* YUV422 INPUT */ + case F_MODE_YUV422: + switch (output_mode & F_MODE_CLRMOD_MASK) { + case F_MODE_YUV444: + csc = B_HDMITX_CSC_BYPASS; + if (input_mode & F_VIDMODE_EN_UDFILT) + filter |= B_TX_EN_UDFILTER; + else if (input_mode & F_VIDMODE_EN_DITHER) + filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO; + break; + case F_MODE_YUV422: + csc = B_HDMITX_CSC_BYPASS; + break; + case F_MODE_RGB444: + csc = B_HDMITX_CSC_YUV2RGB; + if (input_mode & F_VIDMODE_EN_UDFILT) + filter |= B_TX_EN_UDFILTER; + else if (input_mode & F_VIDMODE_EN_DITHER) + filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO; + break; + } + break; + + /* RGB444 INPUT */ + case F_MODE_RGB444: + switch (output_mode & F_MODE_CLRMOD_MASK) { + case F_MODE_YUV444: + csc = B_HDMITX_CSC_RGB2YUV; + if (input_mode & F_VIDMODE_EN_DITHER) + filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO; + break; + case F_MODE_YUV422: + if (input_mode & F_VIDMODE_EN_UDFILT) + filter |= B_TX_EN_UDFILTER; + else if (input_mode & F_VIDMODE_EN_DITHER) + filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO; + csc = B_HDMITX_CSC_RGB2YUV; + break; + case F_MODE_RGB444: + csc = B_HDMITX_CSC_BYPASS; + break; + } + break; + } + + /* set the CSC metrix registers by colorimetry and quantization */ + if (csc == B_HDMITX_CSC_RGB2YUV) { + switch (input_mode & (F_VIDMODE_ITU709 | F_VIDMODE_16_235)) { + case F_VIDMODE_ITU709 | F_VIDMODE_16_235: + ptable = bCSCMtx_RGB2YUV_ITU709_16_235; + break; + case F_VIDMODE_ITU709 | F_VIDMODE_0_255: + ptable = bCSCMtx_RGB2YUV_ITU709_0_255; + break; + case F_VIDMODE_ITU601 | F_VIDMODE_16_235: + ptable = bCSCMtx_RGB2YUV_ITU601_16_235; + break; + case F_VIDMODE_ITU601 | F_VIDMODE_0_255: + default: + ptable = bCSCMtx_RGB2YUV_ITU601_0_255; + break; + } + } + + if (csc == B_HDMITX_CSC_YUV2RGB) { + switch (input_mode & (F_VIDMODE_ITU709 | F_VIDMODE_16_235)) { + case F_VIDMODE_ITU709 | F_VIDMODE_16_235: + ptable = bCSCMtx_YUV2RGB_ITU709_16_235; + break; + case F_VIDMODE_ITU709 | F_VIDMODE_0_255: + ptable = bCSCMtx_YUV2RGB_ITU709_0_255; + break; + case F_VIDMODE_ITU601 | F_VIDMODE_16_235: + ptable = bCSCMtx_YUV2RGB_ITU601_16_235; + break; + case F_VIDMODE_ITU601 | F_VIDMODE_0_255: + default: + ptable = bCSCMtx_YUV2RGB_ITU601_0_255; + break; + } + } + + if (csc == B_HDMITX_CSC_BYPASS) + it6161_hdmi_tx_set_bits(it6161, 0xF, 0x10, 0x10); + else { + if (ptable != NULL) + for (i = 0; i < SIZEOF_CSCMTX; i++) + it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF + i, ptable[i]); + it6161_hdmi_tx_set_bits(it6161, 0xF, 0x10, 0x00); + } + + ucData = it6161_hdmi_tx_read(it6161, + REG_TX_CSC_CTRL) & ~(M_TX_CSC_SEL | + B_TX_DNFREE_GO | + B_TX_EN_DITHER | + B_TX_EN_UDFILTER); + ucData |= filter | csc; + + it6161_hdmi_tx_write(it6161, REG_TX_CSC_CTRL, ucData); +} + +static void hdmi_tx_setup_afe(struct it6161 *it6161, u8 level) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + + it6161_hdmi_tx_write(it6161, REG_TX_AFE_DRV_CTRL, B_TX_AFE_DRV_RST); + switch (level) { + case PCLK_HIGH: + it6161_hdmi_tx_set_bits(it6161, 0x62, 0x90, 0x80); + it6161_hdmi_tx_set_bits(it6161, 0x64, 0x89, 0x80); + it6161_hdmi_tx_set_bits(it6161, 0x68, 0x10, 0x00); + it6161_hdmi_tx_set_bits(it6161, 0x66, 0x80, 0x80); + break; + default: + it6161_hdmi_tx_set_bits(it6161, 0x62, 0x90, 0x10); + it6161_hdmi_tx_set_bits(it6161, 0x64, 0x89, 0x09); + it6161_hdmi_tx_set_bits(it6161, 0x68, 0x10, 0x10); + break; + } + DRM_DEV_DEBUG_DRIVER(dev, "setup afe: %s", level ? "high" : "low"); +} + +static void hdmi_tx_fire_afe(struct it6161 *it6161) +{ + it6161_hdmi_tx_change_bank(it6161, 0x00); + it6161_hdmi_tx_write(it6161, REG_TX_AFE_DRV_CTRL, 0x00); +} + +static void hdmi_tx_disable_video_output(struct it6161 *it6161) +{ + it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_VID_RST, B_HDMITX_VID_RST); + it6161_hdmi_tx_write(it6161, REG_TX_AFE_DRV_CTRL, B_TX_AFE_DRV_RST | B_TX_AFE_DRV_PWD); + it6161_hdmi_tx_set_bits(it6161, 0x62, 0x90, 0x00); + it6161_hdmi_tx_set_bits(it6161, 0x64, 0x89, 0x00); +} + +static void hdmi_tx_enable_video_output(struct it6161 *it6161, u8 level) +{ + it6161_hdmi_tx_write(it6161, REG_TX_SW_RST, + B_HDMITX_AUD_RST | B_TX_AREF_RST | B_TX_HDCP_RST_HDMITX); + it6161_hdmi_tx_change_bank(it6161, 1); + it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB1, 0x00); + it6161_hdmi_tx_change_bank(it6161, 0); + + if (it6161->hdmi_mode) + it6161_hdmi_tx_set_av_mute(it6161, true); + + hdmi_tx_setup_pclk_div2(it6161); + hdmi_tx_setup_csc(it6161); + it6161_hdmi_tx_write(it6161, REG_TX_HDMI_MODE, + it6161->hdmi_mode ? B_TX_HDMI_MODE : B_TX_DVI_MODE); + hdmi_tx_setup_afe(it6161, level); + hdmi_tx_fire_afe(it6161); +} + +static void setHDMITX_ChStat(struct it6161 *it6161, u8 ucIEC60958ChStat[]) +{ + u8 uc; + + it6161_hdmi_tx_change_bank(it6161, 1); + uc = (ucIEC60958ChStat[0] << 1) & 0x7C; + it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_MODE, uc); + it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_CAT, ucIEC60958ChStat[1]); + it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_SRCNUM, ucIEC60958ChStat[2] & 0xF); + it6161_hdmi_tx_write(it6161, REG_TX_AUD0CHST_CHTNUM, (ucIEC60958ChStat[2] >> 4) & 0xF); + it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_CA_FS, ucIEC60958ChStat[3]); + it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_OFS_WL, ucIEC60958ChStat[4]); + it6161_hdmi_tx_change_bank(it6161, 0); +} + +static void setHDMITX_LPCMAudio(u8 AudioSrcNum, u8 AudSWL, u8 bAudInterface) +{ + u8 AudioEnable = 0, AudioFormat = 0, bTDMSetting; + + switch (AudSWL) { + case 16: + AudioEnable |= M_TX_AUD_16BIT; + break; + case 18: + AudioEnable |= M_TX_AUD_18BIT; + break; + case 20: + AudioEnable |= M_TX_AUD_20BIT; + break; + case 24: + default: + AudioEnable |= M_TX_AUD_24BIT; + break; + } + if (bAudInterface == SPDIF) { + AudioFormat &= ~0x40; + AudioEnable |= B_TX_AUD_SPDIF | B_TX_AUD_EN_I2S0; + } else { + AudioFormat |= 0x40; + switch (AudioSrcNum) { + case 4: + AudioEnable |= + B_TX_AUD_EN_I2S3 | B_TX_AUD_EN_I2S2 | + B_TX_AUD_EN_I2S1 | B_TX_AUD_EN_I2S0; + break; + + case 3: + AudioEnable |= + B_TX_AUD_EN_I2S2 | B_TX_AUD_EN_I2S1 | B_TX_AUD_EN_I2S0; + break; + + case 2: + AudioEnable |= B_TX_AUD_EN_I2S1 | B_TX_AUD_EN_I2S0; + break; + + case 1: + default: + AudioFormat &= ~0x40; + AudioEnable |= B_TX_AUD_EN_I2S0; + break; + + } + } + AudioFormat |= 0x01; + it6161->bAudioChannelEnable = AudioEnable; + + it6161_hdmi_tx_change_bank(it6161, 0); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, AudioEnable & 0xF0); + + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1, AudioFormat); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP, 0xE4); + + if (bAudInterface == SPDIF) + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3, B_TX_CHSTSEL); + else + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3, 0); + + it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT, 0x00); + it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO, 0x00); + + if (bAudInterface == SPDIF) { + u8 i; + + it6161_hdmi_tx_set_bits(it6161, 0x5c, (1 << 6), (1 << 6)); + for (i = 0; i < 100; i++) + if (it6161_hdmi_tx_read(it6161, REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK) + break; /* stable clock. */ + } else { + bTDMSetting = it6161_hdmi_tx_read(it6161, REG_TX_AUD_HDAUDIO); + if (bAudInterface == TDM) { + bTDMSetting |= B_TX_TDM; + bTDMSetting &= 0x9F; + bTDMSetting |= (AudioSrcNum - 1) << 5; + } else + bTDMSetting &= ~B_TX_TDM; + + /* 1 channel NLPCM, no TDM mode. */ + it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO, bTDMSetting); + } +} + +static void setHDMITX_NLPCMAudio(u8 bAudInterface) +{ + u8 AudioEnable, AudioFormat; + u8 i; + + /* NLPCM must use standard I2S mode. */ + AudioFormat = 0x01; + if (bAudInterface == SPDIF) + AudioEnable = M_TX_AUD_24BIT | B_TX_AUD_SPDIF; + else + AudioEnable = M_TX_AUD_24BIT; + + it6161_hdmi_tx_change_bank(it6161, 0); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, AudioEnable); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1, 0x01); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP, 0xE4); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3, B_TX_CHSTSEL); + it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT, 0x00); + it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO, 0x00); + + if (bAudInterface == SPDIF) { + for (i = 0; i < 100; i++) + if (it6161_hdmi_tx_read(it6161, REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK) + break; + } else { + i = it6161_hdmi_tx_read(it6161, REG_TX_AUD_HDAUDIO); + i &= ~B_TX_TDM; + /* 2 channel NLPCM, no TDM mode. */ + it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO, i); + } + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, + AudioEnable | B_TX_AUD_EN_I2S0); +} + +static void setHDMITX_HBRAudio(u8 bAudInterface) +{ + it6161_hdmi_tx_change_bank(it6161, 0); + + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1, 0x47); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP, 0xE4); + + if (bAudInterface == SPDIF) { + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, + M_TX_AUD_24BIT | B_TX_AUD_SPDIF); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3, B_TX_CHSTSEL); + } else { + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3, 0); + } + it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT, 0x08); + it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO, B_TX_HBR); + + if (bAudInterface == SPDIF) { + u8 i; + + for (i = 0; i < 100; i++) + if (it6161_hdmi_tx_read(it6161, REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK) + break; + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, + M_TX_AUD_24BIT | B_TX_AUD_SPDIF | B_TX_AUD_EN_SPDIF); + } else { + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, + M_TX_AUD_24BIT | B_TX_AUD_EN_I2S3 | + B_TX_AUD_EN_I2S2 | B_TX_AUD_EN_I2S1 | + B_TX_AUD_EN_I2S0); + } + it6161_hdmi_tx_set_bits(it6161, 0x5c, 1 << 6, 0x00); + it6161->bAudioChannelEnable = it6161_hdmi_tx_read(it6161, REG_TX_AUDIO_CTRL0); +} + +static void setHDMITX_DSDAudio(void) +{ + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1, 0x41); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP, 0xE4); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3, 0); + it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT, 0x00); + it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO, B_TX_DSD); + + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, + M_TX_AUD_24BIT | B_TX_AUD_EN_I2S3 | + B_TX_AUD_EN_I2S2 | B_TX_AUD_EN_I2S1 | + B_TX_AUD_EN_I2S0); +} + +static void HDMITX_DisableAudioOutput(struct it6161 *it6161) +{ + it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, + (B_HDMITX_AUD_RST | B_TX_AREF_RST), + (B_HDMITX_AUD_RST | B_TX_AREF_RST)); + it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x10, 0x10); +} + +static void setHDMITX_NCTS(u8 Fs) +{ + u32 n, LastCTS = 0; + bool HBR_mode; + + if (B_TX_HBR & it6161_hdmi_tx_read(it6161, REG_TX_AUD_HDAUDIO)) + HBR_mode = true; + else + HBR_mode = false; + + switch (Fs) { + case AUDFS_32KHz: + n = 4096; + break; + case AUDFS_44p1KHz: + n = 6272; + break; + case AUDFS_48KHz: + n = 6144; + break; + case AUDFS_88p2KHz: + n = 12544; + break; + case AUDFS_96KHz: + n = 12288; + break; + case AUDFS_176p4KHz: + n = 25088; + break; + case AUDFS_192KHz: + n = 24576; + break; + case AUDFS_768KHz: + n = 24576; + break; + default: + n = 6144; + } + + it6161_hdmi_tx_change_bank(it6161, 1); + it6161_hdmi_tx_write(it6161, REGPktAudN0, (u8) ((n) & 0xFF)); + it6161_hdmi_tx_write(it6161, REGPktAudN1, (u8) ((n >> 8) & 0xFF)); + it6161_hdmi_tx_write(it6161, REGPktAudN2, (u8) ((n >> 16) & 0xF)); + + it6161_hdmi_tx_write(it6161, REGPktAudCTS0, (u8) ((LastCTS) & 0xFF)); + it6161_hdmi_tx_write(it6161, REGPktAudCTS1, (u8) ((LastCTS >> 8) & 0xFF)); + it6161_hdmi_tx_write(it6161, REGPktAudCTS2, (u8) ((LastCTS >> 16) & 0xF)); + it6161_hdmi_tx_change_bank(it6161, 0); + + it6161_hdmi_tx_write(it6161, 0xF8, 0xC3); + it6161_hdmi_tx_write(it6161, 0xF8, 0xA5); + /* D[1] = 0, HW auto count CTS */ + it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL, B_TX_SW_CTS, 0x00); + it6161_hdmi_tx_write(it6161, 0xF8, 0xFF); + + if (false == HBR_mode) { + /* LPCM */ + u8 uData; + + it6161_hdmi_tx_change_bank(it6161, 1); + Fs = AUDFS_768KHz; + it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_CA_FS, 0x00 | Fs); + /* OFS is the one's complement of FS */ + Fs = ~Fs; + uData = (0x0f & it6161_hdmi_tx_read(it6161, REG_TX_AUDCHST_OFS_WL)); + it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_OFS_WL, (Fs << 4) | uData); + it6161_hdmi_tx_change_bank(it6161, 0); + } +} + +static void HDMITX_EnableAudioOutput(struct it6161 *it6161, u8 AudioType, + u8 bAudInterface, u32 SampleFreq, u8 ChNum, u8 *pIEC60958ChStat) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + static u8 ucIEC60958ChStat[5]; + u8 Fs; + + it6161->bAudioChannelEnable = 0; + it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, + (B_HDMITX_AUD_RST | B_TX_AREF_RST), + (B_HDMITX_AUD_RST | B_TX_AREF_RST)); + it6161_hdmi_tx_write(it6161, REG_TX_CLK_CTRL0, + B_TX_AUTO_OVER_SAMPLING_CLOCK | B_TX_EXT_256FS | 0x01); + + /* power on the ACLK */ + it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x10, 0x00); + + if (bAudInterface == SPDIF) { + if (AudioType == T_AUDIO_HBR) + it6161_hdmi_tx_write(it6161, REG_TX_CLK_CTRL0, 0x81); + + it6161_hdmi_tx_set_bits(it6161, REG_TX_AUDIO_CTRL0, + B_TX_AUD_SPDIF, B_TX_AUD_SPDIF); + } else + it6161_hdmi_tx_set_bits(it6161, REG_TX_AUDIO_CTRL0, B_TX_AUD_SPDIF, 0x00); + + if (AudioType != T_AUDIO_DSD) { + /* one bit audio have no channel status. */ + switch (SampleFreq) { + case 44100L: + Fs = AUDFS_44p1KHz; + break; + case 88200L: + Fs = AUDFS_88p2KHz; + break; + case 176400L: + Fs = AUDFS_176p4KHz; + break; + case 32000L: + Fs = AUDFS_32KHz; + break; + case 48000L: + Fs = AUDFS_48KHz; + break; + case 96000L: + Fs = AUDFS_96KHz; + break; + case 192000L: + Fs = AUDFS_192KHz; + break; + case 768000L: + Fs = AUDFS_768KHz; + break; + default: + SampleFreq = 48000L; + Fs = AUDFS_48KHz; + break; + } + + setHDMITX_NCTS(Fs); + if (pIEC60958ChStat == NULL) { + ucIEC60958ChStat[0] = 0; + ucIEC60958ChStat[1] = 0; + ucIEC60958ChStat[2] = (ChNum + 1) / 2; + + if (ucIEC60958ChStat[2] < 1) + ucIEC60958ChStat[2] = 1; + else if (ucIEC60958ChStat[2] > 4) + ucIEC60958ChStat[2] = 4; + + ucIEC60958ChStat[3] = Fs; + ucIEC60958ChStat[4] = (((~Fs) << 4) & 0xF0) | CHTSTS_SWCODE; + pIEC60958ChStat = ucIEC60958ChStat; + } + } + it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, + (B_HDMITX_AUD_RST | B_TX_AREF_RST), B_TX_AREF_RST); + + switch (AudioType) { + case T_AUDIO_HBR: + DRM_DEV_DEBUG_DRIVER(dev, "T_AUDIO_HBR\n"); + pIEC60958ChStat[0] |= 1 << 1; + pIEC60958ChStat[2] = 0; + pIEC60958ChStat[3] &= 0xF0; + pIEC60958ChStat[3] |= AUDFS_768KHz; + pIEC60958ChStat[4] |= (((~AUDFS_768KHz) << 4) & 0xF0) | 0xB; + setHDMITX_ChStat(it6161, pIEC60958ChStat); + setHDMITX_HBRAudio(bAudInterface); + break; + case T_AUDIO_DSD: + DRM_DEV_DEBUG_DRIVER(dev, "T_AUDIO_DSD\n"); + setHDMITX_DSDAudio(); + break; + case T_AUDIO_NLPCM: + DRM_DEV_DEBUG_DRIVER(dev, "T_AUDIO_NLPCM\n"); + pIEC60958ChStat[0] |= 1 << 1; + setHDMITX_ChStat(it6161, pIEC60958ChStat); + setHDMITX_NLPCMAudio(bAudInterface); + break; + case T_AUDIO_LPCM: + DRM_DEV_DEBUG_DRIVER(dev, "T_AUDIO_LPCM\n"); + pIEC60958ChStat[0] &= ~(1 << 1); + + setHDMITX_ChStat(it6161, pIEC60958ChStat); + setHDMITX_LPCMAudio((ChNum + 1) / 2, SUPPORT_AUDI_AudSWL, bAudInterface); + break; + } + it6161_hdmi_tx_set_bits(it6161, REG_TX_INT_MASK1, B_TX_AUDIO_OVFLW_MASK, 0x00); + it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, it6161->bAudioChannelEnable); + + it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, (B_HDMITX_AUD_RST | B_TX_AREF_RST), 0); +} + +static void hdmi_audio_info_frame_set(struct it6161 *it6161, u8 channels) +{ + struct hdmi_audio_infoframe frame; + u8 buf[16]; + int ret; + + hdmi_audio_infoframe_init(&frame); + + frame.channels = channels; + frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; + + ret = hdmi_audio_infoframe_pack(&frame, buf, sizeof(buf)); + if (ret < 0) { + DRM_ERROR("failed to pack audio infoframe: %d\n", ret); + return; + } + + /* set audio Data byte */ + it6161_hdmi_tx_change_bank(it6161, 1); + it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_SUM, buf[3]); + it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_CC, buf[4]); + it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_SF, buf[5]); + it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_CA, buf[7]); + it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_DM_LSV, buf[8]); + + /* Enable Audio info frame */ + it6161_hdmi_tx_change_bank(it6161, 0); + it6161_hdmi_tx_write(it6161, REG_TX_AUD_INFOFRM_CTRL, B_TX_ENABLE_PKT | B_TX_REPEAT_PKT); +} + +static void hdmi_tx_audio_process(struct it6161 *it6161) +{ + if (it6161->support_audio) { + hdmi_audio_info_frame_set(it6161, (u8) OUTPUT_CHANNEL); + + HDMITX_EnableAudioOutput(it6161, + CNOFIG_INPUT_AUDIO_TYPE, + CONFIG_INPUT_AUDIO_INTERFACE, + INPUT_SAMPLE_FREQ, + OUTPUT_CHANNEL, + NULL); + } +} + +static inline void hdmi_tx_disable_avi_infoframe(struct it6161 *it6161) +{ + it6161_hdmi_tx_change_bank(it6161, 0); + it6161_hdmi_tx_write(it6161, REG_TX_AVI_INFOFRM_CTRL, 0x00); +} + +static inline void hdmi_tx_enable_avi_infoframe(struct it6161 *it6161) +{ + it6161_hdmi_tx_change_bank(it6161, 0); + it6161_hdmi_tx_write(it6161, REG_TX_AVI_INFOFRM_CTRL, + B_TX_ENABLE_PKT | B_TX_REPEAT_PKT); +} + +static int hdmi_tx_avi_infoframe_set(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + struct hdmi_avi_infoframe *frame = &it6161->source_avi_infoframe; + struct drm_display_mode *display_mode = &it6161->display_mode; + u8 buf[32], i, *ptr; + int ret; + + DRM_DEV_DEBUG_DRIVER(dev, "avinfo set\n"); + hdmi_tx_disable_avi_infoframe(it6161); + + ret = drm_hdmi_avi_infoframe_from_display_mode( + frame, &it6161->connector, display_mode); + if (ret) { + DRM_DEV_ERROR(dev, "Failed to setup AVI infoframe: %d", ret); + return ret; + } + + if ((it6161->hdmi_tx_output_color_space & F_MODE_CLRMOD_MASK) == F_MODE_RGB444) + frame->colorspace = HDMI_COLORSPACE_RGB; + + if ((it6161->hdmi_tx_output_color_space & F_MODE_CLRMOD_MASK) == F_MODE_YUV444) + frame->colorspace = HDMI_COLORSPACE_YUV444; + + if ((it6161->hdmi_tx_output_color_space & F_MODE_CLRMOD_MASK) == F_MODE_YUV422) + frame->colorspace = HDMI_COLORSPACE_YUV422; + + ret = hdmi_avi_infoframe_pack(&it6161->source_avi_infoframe, buf, sizeof(buf)); + if (ret < 0) { + DRM_DEV_ERROR(dev, "Failed to pack AVI infoframe: %d", ret); + return ret; + } + + /* fill PB */ + it6161_hdmi_tx_change_bank(it6161, 1); + ptr = buf + HDMI_INFOFRAME_HEADER_SIZE; + for (i = 0; i < it6161->source_avi_infoframe.length; i++) + it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB1 + i, ptr[i]); + + it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_SUM, buf[3]); + + /* Enable */ + hdmi_tx_enable_avi_infoframe(it6161); + return 0; +} + +static void hdmi_tx_set_output_process(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + u8 level; + u32 TMDSClock; + + DRM_DEV_DEBUG_DRIVER(dev, "hdmi tx set\n"); + + TMDSClock = it6161->hdmi_tx_pclk * 1000 * + (it6161->source_avi_infoframe.pixel_repeat + 1); + + HDMITX_DisableAudioOutput(it6161); + hdmi_tx_disable_avi_infoframe(it6161); + + if (TMDSClock > 80000000L) + level = PCLK_HIGH; + else if (TMDSClock > 20000000L) + level = PCLK_MEDIUM; + else + level = PCLK_LOW; + + hdmi_tx_enable_video_output(it6161, level); + + if (it6161->hdmi_mode) { + hdmi_tx_avi_infoframe_set(it6161); + hdmi_tx_audio_process(it6161); + } + + it6161_hdmi_tx_set_av_mute(it6161, false); +} + +static void mipi_rx_calc_rclk(struct it6161 *it6161) +{ + struct device *dev = &it6161->i2c_mipi_rx->dev; + u32 sum = 0, i, retry = 5; + int t10usint; + + for (i = 0; i < retry; i++) { + /* Enable RCLK 100ms count */ + it6161_mipi_rx_set_bits(it6161, 0x94, 0x80, 0x80); + msleep(100); + /* Disable RCLK 100ms count */ + it6161_mipi_rx_set_bits(it6161, 0x94, 0x80, 0x00); + + it6161->mipi_rx_rclk = it6161_mipi_rx_read(it6161, 0x97); + it6161->mipi_rx_rclk <<= 8; + it6161->mipi_rx_rclk += it6161_mipi_rx_read(it6161, 0x96); + it6161->mipi_rx_rclk <<= 8; + it6161->mipi_rx_rclk += it6161_mipi_rx_read(it6161, 0x95); + sum += it6161->mipi_rx_rclk; + } + + sum /= retry; + it6161->mipi_rx_rclk = sum / 108; + t10usint = it6161->mipi_rx_rclk; + DRM_DEV_DEBUG_DRIVER(dev, "mipi_rx_rclk = %d,%03d,%03d\n", + (sum * 10) / 1000000, ((sum * 10) % 1000000) / 1000, ((sum * 10) % 100)); + it6161_mipi_rx_write(it6161, 0x91, t10usint & 0xFF); +} + +static void mipi_rx_reset_p_domain(struct it6161 *it6161) +{ + /* Video Clock Domain Reset */ + it6161_mipi_rx_set_bits(it6161, 0x05, 0x04, 0x04); + /* Release Video Clock Domain Reset */ + it6161_mipi_rx_set_bits(it6161, 0x05, 0x04, 0x00); +} + +static void it6161_mipi_rx_interrupt_clear(struct it6161 *it6161, u8 reg06, u8 reg07, u8 reg08) +{ + it6161_mipi_rx_write(it6161, 0x06, reg06); + it6161_mipi_rx_write(it6161, 0x07, reg07); + it6161_mipi_rx_write(it6161, 0x08, reg08); +} + +static void it6161_mipi_rx_interrupt_reg06_process(struct it6161 *it6161, u8 reg06) +{ + struct device *dev = &it6161->i2c_mipi_rx->dev; + bool m_video_stable, p_video_stable; + u8 data_id; + + if (reg06 & 0x01) { + m_video_stable = mipi_rx_get_m_video_stable(it6161); + DRM_DEV_DEBUG_DRIVER(dev, "PPS M video stable Change Interrupt, %sstable", + m_video_stable ? "" : "un"); + + if (m_video_stable) { + data_id = it6161_mipi_rx_read(it6161, 0x28); + DRM_DEV_DEBUG_DRIVER(dev, "mipi receive video format: 0x%02x", data_id); + mipi_rx_calc_rclk(it6161); + mipi_rx_afe_configuration(it6161, data_id); + mipi_rx_reset_p_domain(it6161); + } + } else if (reg06 & 0x10) { + + p_video_stable = mipi_rx_get_p_video_stable(it6161); + DRM_DEV_DEBUG_DRIVER(dev, "PPS P video stable Change Interrupt, %sstable", p_video_stable ? "" : "un"); + if (p_video_stable) { + DRM_DEV_DEBUG_DRIVER(dev, "PVidStb Change to HIGH"); + mipi_rx_calc_rclk(it6161); + + it6161_mipi_rx_write(it6161, 0xC0, (EnTxCRC << 7) + TxCRCnum); + /* setup 1 sec timer interrupt */ + it6161_mipi_rx_set_bits(it6161, 0x0b, 0x40, 0x40); + + switch (it6161->hdmi_tx_mode) { + case HDMI_TX_BY_PASS: + it6161_hdmi_tx_set_bits(it6161, 0xA9, 0x80, 0x80); + break; + + case HDMI_TX_ENABLE_DE_ONLY: + hdmi_tx_generate_blank_timing(it6161); + break; + + default: + DRM_DEV_ERROR(dev, "use hdmi tx normal mode"); + break; + } + + hdmi_tx_video_reset(it6161); + } + } else + DRM_DEV_DEBUG_DRIVER(dev, "MIPI Rx int reg06=0x%x\n", reg06); +} + +static void it6161_mipi_rx_interrupt_reg07_process(struct it6161 *it6161, u8 reg07) +{ + struct device *dev = &it6161->i2c_mipi_rx->dev; + + if (reg07 & 0x40) { + DRM_DEV_DEBUG_DRIVER(dev, "PPS FIFO over read Interrupt !!! tx video statle:%d", + hdmi_tx_get_video_state(it6161)); + it6161_mipi_rx_set_bits(it6161, 0x07, 0x40, 0x40); + } else if (reg07 & 0x80) { + DRM_DEV_DEBUG_DRIVER(dev, "PPS FIFO over write Interrupt !!!\n"); + it6161_mipi_rx_set_bits(it6161, 0x07, 0x80, 0x80); + } else + DRM_DEV_DEBUG_DRIVER(dev, "MIPI Rx int reg07=0x%x\n", reg07); +} + +static void it6161_mipi_rx_interrupt_reg08_process(struct it6161 *it6161, u8 reg08) +{ + struct device *dev = &it6161->i2c_mipi_rx->dev; + int crc; + + if (reg08 & 0x40) { + it6161_mipi_rx_set_bits(it6161, 0x0b, 0x40, 0x00); + + if ((it6161_mipi_rx_read(it6161, 0xC1) & 0x03) == 0x03) + DRM_DEV_DEBUG_DRIVER(dev, "CRC Fail !!!\n"); + + if ((it6161_mipi_rx_read(it6161, 0xC1) & 0x05) == 0x05) { + DRM_DEV_DEBUG_DRIVER(dev, "CRC Pass !!!\n"); + crc = it6161_mipi_rx_read(it6161, 0xC2) + + (it6161_mipi_rx_read(it6161, 0xC3) << 8); + DRM_DEV_DEBUG_DRIVER(dev, "CRCR = 0x%x !!!\n", crc); + crc = it6161_mipi_rx_read(it6161, 0xC4) + + (it6161_mipi_rx_read(it6161, 0xC5) << 8); + DRM_DEV_DEBUG_DRIVER(dev, "CRCG = 0x%x !!!\n", crc); + crc = it6161_mipi_rx_read(it6161, 0xC6) + + (it6161_mipi_rx_read(it6161, 0xC7) << 8); + DRM_DEV_DEBUG_DRIVER(dev, "CRCB = 0x%x !!!\n", crc); + } + } else + DRM_DEV_DEBUG_DRIVER(dev, "MIPI Rx int reg08=0x%x\n", reg08); +} + +static void it6161_hdmi_tx_interrupt_clear(struct it6161 *it6161, u8 reg06, u8 reg08) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + u8 int_clear; + + if (reg06 & B_TX_INT_AUD_OVERFLOW) { + DRM_DEV_ERROR(dev, "B_TX_INT_AUD_OVERFLOW"); + it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, + (B_HDMITX_AUD_RST | B_TX_AREF_RST), + (B_HDMITX_AUD_RST | B_TX_AREF_RST)); + it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_AUD_RST | B_TX_AREF_RST, 0x00); + } else if (reg06 & B_TX_INT_DDCFIFO_ERR) { + DRM_DEV_ERROR(dev, "DDC FIFO Error"); + it6161_hdmi_tx_clear_ddc_fifo(it6161); + } else if (reg06 & B_TX_INT_DDC_BUS_HANG) { + DRM_DEV_ERROR(dev, "DDC BUS HANG"); + it6161_hdmi_tx_abort_ddc(it6161); + } + + /* clear interrupt */ + it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR0, 0xFF); + it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR1, 0xFF); + /* write B_TX_INTACTDONE '1' to trigger clear interrupt */ + int_clear = (it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS)) | B_TX_CLR_AUD_CTS | B_TX_INTACTDONE; + it6161_hdmi_tx_write(it6161, REG_TX_SYS_STATUS, int_clear); +} + +static void it6161_hdmi_tx_interrupt_reg06_process(struct it6161 *it6161, u8 reg06) +{ + struct device *dev = &it6161->i2c_hdmi_tx->dev; + + if (reg06 & B_TX_INT_HPD_PLUG) { + /* + * sometimes the interrupt is triggered before init bridge.dev. + * So avoid null pointer + */ + if (it6161->bridge.dev) + drm_helper_hpd_irq_event(it6161->bridge.dev); + if (hdmi_tx_get_sink_hpd(it6161)) { + DRM_DEV_INFO(dev, "HDMI Cable Plug In\n"); + hdmi_tx_video_reset(it6161); + } else { + DRM_DEV_INFO(dev, "HDMI Cable Plug Out"); + hdmi_tx_disable_video_output(it6161); + } + } +} + +static void it6161_hdmi_tx_interrupt_reg08_process(struct it6161 *it6161, u8 reg08) +{ + if (reg08 & B_TX_INT_VIDSTABLE) { + it6161_hdmi_tx_write(it6161, REG_TX_INT_STAT3, reg08); + if (hdmi_tx_get_video_state(it6161)) { + hdmi_tx_set_output_process(it6161); + it6161_hdmi_tx_set_av_mute(it6161, FALSE); + } + } +} + +static irqreturn_t it6161_intp_threaded_handler(int unused, void *data) +{ + struct it6161 *it6161 = data; + struct device *dev = &it6161->i2c_hdmi_tx->dev; + u8 mipi_rx_reg06, mipi_rx_reg07, mipi_rx_reg08, mipi_rx_reg0d; + u8 hdmi_tx_reg06, hdmi_tx_reg08; + + mipi_rx_reg06 = it6161_mipi_rx_read(it6161, 0x06); + mipi_rx_reg07 = it6161_mipi_rx_read(it6161, 0x07); + mipi_rx_reg08 = it6161_mipi_rx_read(it6161, 0x08); + mipi_rx_reg0d = it6161_mipi_rx_read(it6161, 0x0D); + + hdmi_tx_reg06 = it6161_hdmi_tx_read(it6161, 0x06); + hdmi_tx_reg08 = it6161_hdmi_tx_read(it6161, 0x08); + + if ((mipi_rx_reg06 != 0) || (mipi_rx_reg07 != 0) || (mipi_rx_reg08 != 0)) { + DRM_DEV_DEBUG_DRIVER(dev, "[MIPI rx ++] reg06: 0x%02x reg07: 0x%02x reg08: 0x%02x reg0d: 0x%02x", + mipi_rx_reg06, mipi_rx_reg07, mipi_rx_reg08, mipi_rx_reg0d); + it6161_mipi_rx_interrupt_clear(it6161, mipi_rx_reg06, mipi_rx_reg07, mipi_rx_reg08); + } + + if ((hdmi_tx_reg06 != 0) || (hdmi_tx_reg08 != 0)) { + DRM_DEV_DEBUG_DRIVER(dev, "[HDMI tx ++] reg06: 0x%02x reg08: 0x%02x", + hdmi_tx_reg06, hdmi_tx_reg08); + it6161_hdmi_tx_interrupt_clear(it6161, hdmi_tx_reg06, hdmi_tx_reg08); + } + + it6161_mipi_rx_interrupt_reg08_process(it6161, mipi_rx_reg08); + it6161_mipi_rx_interrupt_reg06_process(it6161, mipi_rx_reg06); + it6161_mipi_rx_interrupt_reg07_process(it6161, mipi_rx_reg07); + it6161_hdmi_tx_interrupt_reg06_process(it6161, hdmi_tx_reg06); + it6161_hdmi_tx_interrupt_reg08_process(it6161, hdmi_tx_reg08); + + return IRQ_HANDLED; +} + +static ssize_t hdmi_output_color_space_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct it6161 *it6161 = dev_get_drvdata(dev); + + DRM_DEV_DEBUG_DRIVER(dev, "config color space: %s", buf); + it6161->hdmi_tx_output_color_space &= ~F_MODE_CLRMOD_MASK; + + if (strncmp(buf, "ycbcr444", strlen(buf) - 1) == 0 + || strncmp(buf, "yuv444", strlen(buf) - 1) == 0) { + it6161->hdmi_tx_output_color_space |= F_MODE_YUV444; + goto end; + } + + if (strncmp(buf, "ycbcr422", strlen(buf) - 1) == 0 + || strncmp(buf, "yuv422", strlen(buf) - 1) == 0) { + it6161->hdmi_tx_output_color_space |= F_MODE_YUV422; + goto end; + } + + if (strncmp(buf, "rgb444", strlen(buf) - 1) == 0) { + it6161->hdmi_tx_output_color_space |= F_MODE_RGB444; + goto end; + } + + DRM_DEV_DEBUG_DRIVER(dev, + "not support this color space, only support ycbcr444/yuv444, ycbcr422/yuv422, rgb444"); + return count; + +end: + DRM_DEV_INFO(dev, "nconfig color space: %s value:0x%02x", buf, + it6161->hdmi_tx_output_color_space); + return count; +} + +static ssize_t hdmi_output_color_space_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct it6161 *it6161 = dev_get_drvdata(dev); + char *str = buf, *end = buf + PAGE_SIZE; + + str += scnprintf(str, end - str, + "it6161->hdmi_tx_output_color_space:%d\n", it6161->hdmi_tx_output_color_space); + + return str - buf; +} + +static DEVICE_ATTR_RW(hdmi_output_color_space); + +static const struct attribute *it6161_attrs[] = { + &dev_attr_hdmi_output_color_space.attr, + NULL, +}; + +static int it6161_parse_dt(struct it6161 *it6161, struct device_node *np) +{ + struct device *dev = &it6161->i2c_mipi_rx->dev; + + it6161->host_node = of_graph_get_remote_node(np, 0, 0); + if (!it6161->host_node) { + DRM_DEV_ERROR(dev, "no host node"); + return -ENODEV; + } + of_node_put(it6161->host_node); + + return 0; +} + +static int it6161_i2c_probe(struct i2c_client *i2c_mipi_rx, + const struct i2c_device_id *id) +{ + struct device *dev = &i2c_mipi_rx->dev; + int err, intp_irq; + + it6161 = devm_kzalloc(dev, sizeof(*it6161), GFP_KERNEL); + if (!it6161) + return -ENOMEM; + + it6161->i2c_mipi_rx = i2c_mipi_rx; + mutex_init(&it6161->mode_lock); + + it6161->bridge.of_node = i2c_mipi_rx->dev.of_node; + + it6161_parse_dt(it6161, dev->of_node); + it6161->regmap_mipi_rx = devm_regmap_init_i2c(i2c_mipi_rx, &it6161_mipi_rx_bridge_regmap_config); + if (IS_ERR(it6161->regmap_mipi_rx)) { + DRM_DEV_ERROR(dev, "regmap_mipi_rx i2c init failed"); + return PTR_ERR(it6161->regmap_mipi_rx); + } + + if (device_property_read_u32(dev, "it6161-addr-hdmi-tx", &it6161->it6161_addr_hdmi_tx) < 0) + it6161->it6161_addr_hdmi_tx = 0x4C; + it6161->i2c_hdmi_tx = i2c_new_dummy_device(i2c_mipi_rx->adapter, it6161->it6161_addr_hdmi_tx); + it6161->regmap_hdmi_tx = devm_regmap_init_i2c(it6161->i2c_hdmi_tx, &it6161_hdmi_tx_bridge_regmap_config); + if (IS_ERR(it6161->regmap_hdmi_tx)) { + DRM_DEV_ERROR(dev, "regmap_hdmi_tx i2c init failed"); + return PTR_ERR(it6161->regmap_hdmi_tx); + } + + if (!it6161_check_device_ready(it6161)) + return -ENODEV; + + /* The enable GPIO is optional. */ + it6161->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); + if (IS_ERR(it6161->enable_gpio)) + DRM_DEV_INFO(dev, "No enable GPIO"); + else + gpiod_set_value_cansleep(it6161->enable_gpio, 1); + + it6161->enable_drv_hold = DEFAULT_DRV_HOLD; + it6161_set_interrupts_active_level(HIGH); + + intp_irq = i2c_mipi_rx->irq; + + if (!intp_irq) { + DRM_DEV_ERROR(dev, "it6112 failed to get INTP IRQ"); + return -ENODEV; + } + + err = devm_request_threaded_irq(&i2c_mipi_rx->dev, intp_irq, NULL, + it6161_intp_threaded_handler, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "it6161-intp", it6161); + if (err) { + DRM_DEV_ERROR(dev, "it6112 failed to request INTP threaded IRQ: %d", err); + return err; + } + + i2c_set_clientdata(i2c_mipi_rx, it6161); + it6161->bridge.funcs = &it6161_bridge_funcs; + it6161->bridge.of_node = i2c_mipi_rx->dev.of_node; + it6161->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | + DRM_BRIDGE_OP_HPD | DRM_BRIDGE_OP_MODES; + it6161->bridge.type = DRM_MODE_CONNECTOR_HDMIA; + + drm_bridge_add(&it6161->bridge); + + err = sysfs_create_files(&i2c_mipi_rx->dev.kobj, it6161_attrs); + if (err) + return err; + + return 0; +} + +static void it6161_remove(struct i2c_client *i2c_mipi_rx) +{ + struct it6161 *it6161 = i2c_get_clientdata(i2c_mipi_rx); + + drm_connector_unregister(&it6161->connector); + drm_connector_cleanup(&it6161->connector); + drm_bridge_remove(&it6161->bridge); +} + +static const struct i2c_device_id it6161_id[] = { + {"it6161", 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, it6161_id); + +static const struct of_device_id it6161_of_match[] = { + {.compatible = "ite,it6161"}, + {} +}; + +static struct i2c_driver it6161_i2c_driver = { + .driver = { + .name = "it6161_mipirx_hdmitx", + .of_match_table = it6161_of_match, + }, + .id_table = it6161_id, + .probe = it6161_i2c_probe, + .remove = it6161_remove, +}; + +module_i2c_driver(it6161_i2c_driver); + +MODULE_AUTHOR("allen chen "); +MODULE_DESCRIPTION("it6161 HDMI Transmitter driver"); +MODULE_LICENSE("GPL v2"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/it6161.h linux-imx-phytec/drivers/gpu/drm/bridge/it6161.h --- linux-6.1.55/drivers/gpu/drm/bridge/it6161.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/it6161.h 2024-06-19 12:34:01.896254057 +0200 @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * IT6161 MIPI to HDMI Converter driver + * + * Copyright (C) 2021 NXP + */ +#ifndef __IT6161_H__ +#define __IT6161_H__ + +/* Video Configuration */ +#define F_MODE_RGB444 0 +#define F_MODE_YUV422 1 +#define F_MODE_YUV444 2 +#define F_MODE_CLRMOD_MASK 3 + +#define F_VIDMODE_ITU709 (1<<4) +#define F_VIDMODE_ITU601 0 +#define F_VIDMODE_16_235 (1<<5) +#define F_VIDMODE_0_255 0 + +#define F_VIDMODE_EN_UDFILT (1<<6) +#define F_VIDMODE_EN_DITHER (1<<7) + +#define INPUT_COLOR_MODE F_MODE_RGB444 +#define OUTPUT_COLOR_MODE F_MODE_RGB444 + +/* Audio Configuration */ + +/* Audio interface */ +#define I2S 0 +#define SPDIF 1 +#define TDM 2 + +/* Audio sample clock */ +#define AUDFS_44p1KHz 0 +#define AUDFS_88p2KHz 8 +#define AUDFS_176p4KHz 12 +#define AUDFS_32KHz 3 +#define AUDFS_48KHz 2 +#define AUDFS_96KHz 10 +#define AUDFS_192KHz 14 +#define AUDFS_768KHz 9 + +#define F_AUDIO_ON (1<<7) +#define F_AUDIO_HBR (1<<6) +#define F_AUDIO_DSD (1<<5) +#define F_AUDIO_NLPCM (1<<4) +#define F_AUDIO_LAYOUT_1 (1<<3) +#define F_AUDIO_LAYOUT_0 (0<<3) + +#define T_AUDIO_HBR (F_AUDIO_ON | F_AUDIO_HBR) +#define T_AUDIO_DSD (F_AUDIO_ON | F_AUDIO_DSD) +#define T_AUDIO_NLPCM (F_AUDIO_ON | F_AUDIO_NLPCM) +#define T_AUDIO_LPCM (F_AUDIO_ON) + +/* #define SUPPORT_HBR_AUDIO */ +#ifndef SUPPORT_HBR_AUDIO + #define INPUT_SAMPLE_FREQ AUDFS_48KHz + #define INPUT_SAMPLE_FREQ_HZ 48000L + #define OUTPUT_CHANNEL 2 /* 3,4,5,6,7,8 */ + #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_LPCM + #define CONFIG_INPUT_AUDIO_INTERFACE SPDIF + #define I2S_FORMAT 0x01 /* 32bit I2S audio */ +#else /* SUPPORT_HBR_AUDIO */ + #define INPUT_SAMPLE_FREQ AUDFS_768KHz + #define INPUT_SAMPLE_FREQ_HZ 768000L + #define OUTPUT_CHANNEL 8 + #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_HBR + #define CONFIG_INPUT_AUDIO_INTERFACE SPDIF + #define I2S_FORMAT 0x47 /* 32bit audio */ +#endif + +/* MIPI Rx Configuration */ +#define MIPI_RX_LANE_COUNT 2 /* 1~4 */ + +#define SUPPORT_AUDI_AudSWL 24 + +#if (SUPPORT_AUDI_AudSWL == 16) + #define CHTSTS_SWCODE 0x02 +#elif (SUPPORT_AUDI_AudSWL == 18) + #define CHTSTS_SWCODE 0x04 +#elif (SUPPORT_AUDI_AudSWL == 20) + #define CHTSTS_SWCODE 0x03 +#else + #define CHTSTS_SWCODE 0x0B +#endif + +#define DDC_FIFO_MAXREQ 0x20 + +/* I2C address */ +#define DDC_EDID_ADDRESS 0xA0 +#define CEC_I2C_SLAVE_ADDR 0x9C + +/* HDMI TX Register offset */ +#define REG_TX_SW_RST 0x04 +#define B_TX_AREF_RST (1<<4) +#define B_HDMITX_VID_RST (1<<3) +#define B_HDMITX_AUD_RST (1<<2) +#define B_TX_HDMI_RST (1<<1) +#define B_TX_HDCP_RST_HDMITX (1<<0) + +#define REG_TX_INT_STAT1 0x06 +#define B_TX_INT_AUD_OVERFLOW (1<<7) +#define B_TX_INT_DDCFIFO_ERR (1<<4) +#define B_TX_INT_DDC_BUS_HANG (1<<2) +#define B_TX_INT_HPD_PLUG (1<<0) + +#define REG_TX_INT_STAT3 0x08 +#define B_TX_INT_VIDSTABLE (1<<4) + +#define REG_TX_INT_MASK1 0x09 +#define B_TX_AUDIO_OVFLW_MASK (1<<7) +#define B_TX_DDC_FIFO_ERR_MASK (1<<4) +#define B_TX_DDC_BUS_HANG_MASK (1<<2) +#define B_TX_RXSEN_MASK (1<<1) +#define B_TX_HPD_MASK (1<<0) + +#define REG_TX_INT_MASK3 0x0B +#define B_TX_VIDSTABLE_MASK (1<<3) + +#define REG_TX_INT_CLR0 0x0C +#define REG_TX_INT_CLR1 0x0D +#define REG_TX_SYS_STATUS 0x0E +#define B_TX_HPDETECT (1<<6) +#define B_TX_RXSENDETECT (1<<5) +#define B_TXVIDSTABLE (1<<4) +#define B_TX_CLR_AUD_CTS (1<<1) +#define B_TX_INTACTDONE (1<<0) + +/* DDC */ +#define REG_TX_DDC_MASTER_CTRL 0x10 +#define B_TX_MASTERROM (1<<1) +#define B_TX_MASTERDDC (0<<1) +#define B_TX_MASTERHOST (1<<0) + +#define REG_TX_DDC_HEADER 0x11 +#define REG_TX_DDC_REQOFF 0x12 +#define REG_TX_DDC_REQCOUNT 0x13 +#define REG_TX_DDC_EDIDSEG 0x14 +#define REG_TX_DDC_CMD 0x15 +#define CMD_EDID_READ 3 +#define CMD_FIFO_CLR 9 +#define CMD_GEN_SCLCLK 0xA +#define CMD_DDC_ABORT 0xF + +#define REG_TX_DDC_STATUS 0x16 +#define B_TX_DDC_DONE (1<<7) +#define B_TX_DDC_NOACK (1<<5) +#define B_TX_DDC_WAITBUS (1<<4) +#define B_TX_DDC_ARBILOSE (1<<3) + +#define REG_TX_DDC_READFIFO 0x17 +#define REG_TX_CLK_CTRL0 0x58 +#define B_TX_AUTO_OVER_SAMPLING_CLOCK (1<<4) +#define O_TX_EXT_MCLK_SEL 2 +#define M_TX_EXT_MCLK_SEL (3< +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG_VENDOR_ID(n) (0x00 + (n)) /* n: 0/1 */ +#define REG_DEVICE_ID(n) (0x02 + (n)) /* n: 0/1 */ +#define LVDS_VENDER_ID_LOW 0x15 +#define LVDS_VENDER_ID_HIGH 0xCA +#define LVDS_DEVICE_ID_LOW 0x61 +#define LVDS_DEVICE_ID_HIGH 0x62 +#define HDMI_VENDER_ID_LOW 0x01 +#define HDMI_VENDER_ID_HIGH 0xCA +#define HDMI_DEVICE_ID_LOW 0x13 +#define HDMI_DEVICE_ID_HIGH 0x76 + +/* LVDS registers */ +#define LVDS_REG_SW_RST 0x05 +#define SOFT_REFCLK_DM_RST BIT(0) +#define SOFT_PCLK_DM_RST BIT(1) + +#define LVDS_REG_MODE 0x2C +#define LVDS_COLOR_DEPTH 0x3 +enum { + LVDS_COLOR_DEPTH_18, + LVDS_COLOR_DEPTH_24, + LVDS_COLOR_DEPTH_30, + LVDS_COLOR_DEPTH_36, +}; +#define LVDS_OUT_MAP BIT(4) +#define VESA BIT(4) +#define JEIDA 0 +#define DMODE BIT(7) +#define SPLIT_MODE BIT(7) +#define SINGLE_MODE 0 + +#define LVDS_REG_STABLE 0x30 +#define VIDEO_STABLE BIT(0) +#define PCLK_LOCK BIT(1) + +#define LVDS_REG_39 0x39 + +#define LVDS_REG_PLL 0x3C +#define LVDS_REG_AFE_3E 0x3E +#define LVDS_REG_AFE_3F 0x3F +#define LVDS_REG_AFE_47 0x47 +#define LVDS_REG_AFE_48 0x48 +#define LVDS_REG_AFE_4F 0x4F +#define LVDS_REG_52 0x52 +#define LVDS_REG_PCLK_CNT_HIGH 0x57 +#define LVDS_REG_PCLK_CNT_LOW 0x58 + +/* + * HDMI registers + * + * Registers are separated into three banks: + * 1) common bank: 0x00 ~ 0x2F + * 2) bank0: 0x30 ~ 0xFF + * 3) bank1: 0x130 ~ 0x1FF (HDMI packet registers) + * + * Use register HDMI_REG_BANK_CTRL @ 0x0F[1:0] to select bank0/1: + * 2b'00 - bank0 + * 2b'01 - bank1 + */ + +/******************************/ +/* HDMI register common bank */ +/******************************/ + +/* HDMI genernal registers */ +#define HDMI_REG_SW_RST 0x04 +#define SOFTREF_RST BIT(5) +#define SOFTA_RST BIT(4) +#define SOFTV_RST BIT(3) +#define AUD_RST BIT(2) +#define HDCP_RST BIT(0) +#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \ + AUD_RST | HDCP_RST) + +#define HDMI_REG_INT_CTRL 0x05 +#define INTPOL_ACTH BIT(7) +#define INTPOL_ACTL 0 +#define INTIOMODE_OPENDRAIN BIT(6) +#define INTIOMODE_PUSHPULL 0 +#define SELXTAL BIT(5) /* REFCLK <= XTALCLK */ +#define SELXTAL_QUARTER 0 /* REFCLK <= OSCCLK/4 */ +#define PDREFCNT(n) (((n) >> 2) << 2) /* REFCLK Div(n) */ +#define PDREFCLK BIT(1) +#define PDTXCLK_GATED BIT(0) +#define PDTXCLK_ACTIVE 0 + +#define HDMI_REG_INT_STAT(n) (0x05 + (n)) /* n: 1/2/3 */ +#define HDMI_REG_INT_MASK(n) (0x08 + (n)) /* n: 1/2/3 */ + +/* INT1 */ +#define INT_AUD_OVERFLOW BIT(7) +#define INT_RDDC_NOACK BIT(5) +#define INT_DDCFIFO_ERR BIT(4) +#define INT_DDC_BUS_HANG BIT(2) +#define INT_RX_SENSE BIT(1) +#define INT_HPD BIT(0) + +/* INT2 */ +#define INT_VID_UNSTABLE BIT(6) +#define INT_PKTACP BIT(5) +#define INT_PKTNULL BIT(4) +#define INT_PKTGEN BIT(3) +#define INT_KSVLIST_CHK BIT(2) +#define INT_AUTH_DONE BIT(1) +#define INT_AUTH_FAIL BIT(0) + +/* INT3 */ +#define INT_AUD_CTS BIT(6) +#define INT_VSYNC BIT(5) +#define INT_VIDSTABLE BIT(4) +#define INT_PKTMPG BIT(3) +#define INT_PKTGBD BIT(2) +#define INT_PKTAUD BIT(1) +#define INT_PKTAVI BIT(0) + +#define INT_MASK_AUD_CTS BIT(5) +#define INT_MASK_VSYNC BIT(4) +#define INT_MASK_VIDSTABLE BIT(3) +#define INT_MASK_PKTMPG BIT(2) +#define INT_MASK_PKTGBD BIT(1) +#define INT_MASK_PKTAUD BIT(0) + +#define HDMI_REG_INT_CLR(n) (0x0C + (n)) /* n: 0/1 */ + +/* CLR0 */ +#define INT_CLR_PKTACP BIT(7) +#define INT_CLR_PKTNULL BIT(6) +#define INT_CLR_PKTGEN BIT(5) +#define INT_CLR_KSVLIST_CHK BIT(4) +#define INT_CLR_AUTH_DONE BIT(3) +#define INT_CLR_AUTH_FAIL BIT(2) +#define INT_CLR_RXSENSE BIT(1) +#define INT_CLR_HPD BIT(0) + +/* CLR1 */ +#define INT_CLR_VSYNC BIT(7) +#define INT_CLR_VIDSTABLE BIT(6) +#define INT_CLR_PKTMPG BIT(5) +#define INT_CLR_PKTGBD BIT(4) +#define INT_CLR_PKTAUD BIT(3) +#define INT_CLR_PKTAVI BIT(2) +#define INT_CLR_VID_UNSTABLE BIT(0) + +#define HDMI_REG_SYS_STATUS 0x0E +#define INT_ACTIVE BIT(7) +#define HPDETECT BIT(6) +#define RXSENDETECT BIT(5) +#define TXVIDSTABLE BIT(4) +#define CTSINTSTEP 0xC +#define CLR_AUD_CTS BIT(1) +#define INTACTDONE BIT(0) + +#define HDMI_REG_BANK_CTRL 0x0F +#define BANK_SEL(n) ((n) ? 1 : 0) + +/* HDMI System DDC control registers */ +#define HDMI_REG_DDC_MASTER_CTRL 0x10 +#define MASTER_SEL_HOST BIT(0) +#define MASTER_SEL_HDCP 0 + +#define HDMI_REG_DDC_HEADER 0x11 +#define DDC_HDCP_ADDRESS 0x74 + +#define HDMI_REG_DDC_REQOFF 0x12 +#define HDMI_REG_DDC_REQCOUNT 0x13 +#define HDMI_REG_DDC_EDIDSEG 0x14 + +#define HDMI_REG_DDC_CMD 0x15 +#define DDC_CMD_SEQ_BURSTREAD 0x0 +#define DDC_CMD_LINK_CHKREAD 0x2 +#define DDC_CMD_EDID_READ 0x3 +#define DDC_CMD_FIFO_CLR 0x9 +#define DDC_CMD_GEN_SCLCLK 0xA +#define DDC_CMD_ABORT 0xF + +#define HDMI_REG_DDC_STATUS 0x16 +#define DDC_DONE BIT(7) +#define DDC_ACT BIT(6) +#define DDC_NOACK BIT(5) +#define DDC_WAITBUS BIT(4) +#define DDC_ARBILOSE BIT(3) +#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE) +#define DDC_FIFOFULL BIT(2) +#define DDC_FIFOEMPTY BIT(1) + +#define HDMI_DDC_FIFO_SIZE 32 /* bytes */ +#define HDMI_REG_DDC_READFIFO 0x17 +#define HDMI_REG_ROM_STAT 0x1C +#define HDMI_REG_LVDS_PORT 0x1D /* LVDS input ctrl i2c addr */ +#define HDMI_REG_LVDS_PORT_EN 0x1E /* and to enable */ +#define LVDS_INPUT_CTRL_I2C_ADDR 0x33 + +/***********************/ +/* HDMI register bank0 */ +/***********************/ + +/* HDMI clock control registers */ +#define HDMI_REG_CLK_CTRL1 0x59 +#define EN_TXCLK_COUNT BIT(5) +#define VDO_LATCH_EDGE BIT(3) + +/* HDMI AFE registers */ +#define HDMI_REG_AFE_DRV_CTRL 0x61 +#define AFE_DRV_PWD BIT(5) +#define AFE_DRV_RST BIT(4) +#define AFE_DRV_PDRXDET BIT(2) +#define AFE_DRV_TERMON BIT(1) +#define AFE_DRV_ENCAL BIT(0) + +#define HDMI_REG_AFE_XP_CTRL 0x62 +#define AFE_XP_GAINBIT BIT(7) +#define AFE_XP_PWDPLL BIT(6) +#define AFE_XP_ENI BIT(5) +#define AFE_XP_ER0 BIT(4) +#define AFE_XP_RESETB BIT(3) +#define AFE_XP_PWDI BIT(2) +#define AFE_XP_DEI BIT(1) +#define AFE_XP_DER BIT(0) + +#define HDMI_REG_AFE_ISW_CTRL 0x63 +#define AFE_RTERM_SEL BIT(7) +#define AFE_IP_BYPASS BIT(6) +#define AFE_DRV_ISW 0x38 +#define AFE_DRV_ISWK 7 + +#define HDMI_REG_AFE_IP_CTRL 0x64 +#define AFE_IP_GAINBIT BIT(7) +#define AFE_IP_PWDPLL BIT(6) +#define AFE_IP_CKSEL 0x30 +#define AFE_IP_ER0 BIT(3) +#define AFE_IP_RESETB BIT(2) +#define AFE_IP_ENC BIT(1) +#define AFE_IP_EC1 BIT(0) + +/* HDMI input data format registers */ +#define HDMI_REG_INPUT_MODE 0x70 +#define IN_RGB 0x00 +#define IN_YUV422 0x40 +#define IN_YUV444 0x80 + +#define HDMI_REG_TXFIFO_RST 0x71 +#define ENAVMUTERST BIT(0) +#define TXFFRST BIT(1) + +/* HDMI pattern generation SYNC/DE registers */ +#define HDMI_REG_9X(n) (0x90 + (n)) /* n: 0x0 ~ 0xF */ +#define HDMI_REG_AX(n) (0xA0 + (n)) /* n: 0x0 ~ 0xF */ +#define HDMI_REG_B0 0xB0 + +/* HDMI general control registers */ +#define HDMI_REG_HDMI_MODE 0xC0 +#define TX_HDMI_MODE 1 +#define TX_DVI_MODE 0 + +#define HDMI_REG_GCP 0xC1 +#define AVMUTE BIT(0) +#define BLUE_SCR_MUTE BIT(1) +#define NODEF_PHASE BIT(2) +#define PHASE_RESYNC BIT(3) +#define HDMI_COLOR_DEPTH 0x70 +enum { + HDMI_COLOR_DEPTH_DEF = 0x0, /* default as 24bit */ + HDMI_COLOR_DEPTH_24 = 0x40, + HDMI_COLOR_DEPTH_30 = 0x50, + HDMI_COLOR_DEPTH_36 = 0x60, + HDMI_COLOR_DEPTH_48 = 0x70, +}; + +#define HDMI_REG_OESS_CYCLE 0xC3 +#define HDMI_REG_ENCRYPTION 0xC4 /* HDCP */ + +#define HDMI_REG_PKT_SINGLE_CTRL 0xC5 +#define SINGLE_PKT BIT(0) +#define BURST_PKT 0 + +#define HDMI_REG_PKT_GENERAL_CTRL 0xC6 +#define HDMI_REG_NULL_CTRL 0xC9 +#define HDMI_REG_ACP_CTRL 0xCA +#define HDMI_REG_ISRC1_CTRL 0xCB +#define HDMI_REG_ISRC2_CTRL 0xCC +#define HDMI_REG_AVI_INFOFRM_CTRL 0xCD +#define HDMI_REG_AUD_INFOFRM_CTRL 0xCE +#define HDMI_REG_SPD_INFOFRM_CTRL 0xCF +#define HDMI_REG_MPG_INFOFRM_CTRL 0xD0 +#define ENABLE_PKT BIT(0) +#define REPEAT_PKT BIT(1) + +/***********************/ +/* HDMI register bank1 */ +/***********************/ + +/* AVI packet registers */ +#define HDMI_REG_AVI_DB1 0x58 +#define AVI_DB1_COLOR_SPACE 0x60 +enum { + AVI_COLOR_SPACE_RGB = 0x00, + AVI_COLOR_SPACE_YUV422 = 0x20, + AVI_COLOR_SPACE_YUV444 = 0x40, +}; + +struct it6263 { + struct i2c_client *hdmi_i2c; + struct i2c_client *lvds_i2c; + struct regmap *hdmi_regmap; + struct regmap *lvds_regmap; + struct drm_bridge bridge; + struct drm_connector connector; + struct gpio_desc *reset_gpio; + bool is_hdmi; + bool split_mode; +}; + +struct it6263_minimode { + int hdisplay; + int vdisplay; + int vrefresh; +}; + +static const struct it6263_minimode it6263_bad_mode_db[] = { + {1600, 900, 60}, + {1280, 1024, 60}, + {1280, 720, 30}, + {1280, 720, 25}, + {1280, 720, 24}, + {1152, 864, 75}, +}; + +static inline struct it6263 *bridge_to_it6263(struct drm_bridge *bridge) +{ + return container_of(bridge, struct it6263, bridge); +} + +static inline struct it6263 *connector_to_it6263(struct drm_connector *con) +{ + return container_of(con, struct it6263, connector); +} + +static inline void lvds_update_bits(struct it6263 *it6263, unsigned int reg, + unsigned int mask, unsigned int val) +{ + regmap_update_bits(it6263->lvds_regmap, reg, mask, val); +} + +static inline void hdmi_update_bits(struct it6263 *it6263, unsigned int reg, + unsigned int mask, unsigned int val) +{ + regmap_update_bits(it6263->hdmi_regmap, reg, mask, val); +} + +static void it6263_reset(struct it6263 *it6263) +{ + if (!it6263->reset_gpio) + return; + + gpiod_set_value_cansleep(it6263->reset_gpio, 0); + + usleep_range(1000, 2000); + + gpiod_set_value_cansleep(it6263->reset_gpio, 1); + + /* + * The chip maker says the low pulse should be at least 40ms, + * so 41ms is sure to be enough. + */ + usleep_range(41000, 45000); + + gpiod_set_value_cansleep(it6263->reset_gpio, 0); + + /* somehow, addtional time to wait the high voltage to be stable */ + usleep_range(5000, 6000); +} + +static void it6263_lvds_reset(struct it6263 *it6263) +{ + /* AFE PLL reset */ + lvds_update_bits(it6263, LVDS_REG_PLL, 0x1, 0x0); + usleep_range(1000, 2000); + lvds_update_bits(it6263, LVDS_REG_PLL, 0x1, 0x1); + + /* pclk reset */ + lvds_update_bits(it6263, LVDS_REG_SW_RST, + SOFT_PCLK_DM_RST, SOFT_PCLK_DM_RST); + usleep_range(1000, 2000); + lvds_update_bits(it6263, LVDS_REG_SW_RST, SOFT_PCLK_DM_RST, 0x0); + + usleep_range(1000, 2000); +} + +static void it6263_lvds_set_interface(struct it6263 *it6263) +{ + /* color depth */ + lvds_update_bits(it6263, LVDS_REG_MODE, LVDS_COLOR_DEPTH, + LVDS_COLOR_DEPTH_24); + + /* jeida mapping */ + lvds_update_bits(it6263, LVDS_REG_MODE, LVDS_OUT_MAP, JEIDA); + + if (it6263->split_mode) { + lvds_update_bits(it6263, LVDS_REG_MODE, DMODE, SPLIT_MODE); + lvds_update_bits(it6263, LVDS_REG_52, BIT(1), BIT(1)); + } else { + lvds_update_bits(it6263, LVDS_REG_MODE, DMODE, SINGLE_MODE); + lvds_update_bits(it6263, LVDS_REG_52, BIT(1), 0); + } +} + +static void it6263_lvds_set_afe(struct it6263 *it6263) +{ + struct regmap *regmap = it6263->lvds_regmap; + + regmap_write(regmap, LVDS_REG_AFE_3E, 0xaa); + regmap_write(regmap, LVDS_REG_AFE_3F, 0x02); + regmap_write(regmap, LVDS_REG_AFE_47, 0xaa); + regmap_write(regmap, LVDS_REG_AFE_48, 0x02); + regmap_write(regmap, LVDS_REG_AFE_4F, 0x11); + + lvds_update_bits(it6263, LVDS_REG_PLL, 0x07, 0); +} + +static void it6263_lvds_config(struct it6263 *it6263) +{ + it6263_lvds_reset(it6263); + it6263_lvds_set_interface(it6263); + it6263_lvds_set_afe(it6263); +} + +static void it6263_hdmi_config(struct it6263 *it6263) +{ + regmap_write(it6263->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB); + + hdmi_update_bits(it6263, HDMI_REG_GCP, HDMI_COLOR_DEPTH, + HDMI_COLOR_DEPTH_24); +} + +static bool it6263_hpd_is_connected(struct it6263 *it6263) +{ + unsigned int status; + + regmap_read(it6263->hdmi_regmap, HDMI_REG_SYS_STATUS, &status); + + return !!(status & HPDETECT); +} + +static enum drm_connector_status +it6263_connector_detect(struct drm_connector *connector, bool force) +{ + struct it6263 *it6263 = connector_to_it6263(connector); + int i; + + if (force) { + /* + * FIXME: We read status tens of times to workaround + * cable detection failure issue at boot time on some + * platforms. + * Spin on this for up to one second. + */ + for (i = 0; i < 100; i++) { + if (it6263_hpd_is_connected(it6263)) + return connector_status_connected; + usleep_range(5000, 10000); + } + } else { + if (it6263_hpd_is_connected(it6263)) + return connector_status_connected; + } + + return connector_status_disconnected; +} + +static const struct drm_connector_funcs it6263_connector_funcs = { + .detect = it6263_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static int +it6263_read_edid(void *data, u8 *buf, unsigned int block, size_t len) +{ + struct it6263 *it6263 = data; + struct regmap *regmap = it6263->hdmi_regmap; + unsigned long timeout; + unsigned int status, count, val; + unsigned int segment = block >> 1; + unsigned int start = (block % 2) * EDID_LENGTH; + + regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST); + regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1); + regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment); + + while (len) { + /* clear DDC FIFO */ + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR); + + timeout = jiffies + msecs_to_jiffies(10); + do { + regmap_read(regmap, HDMI_REG_DDC_STATUS, &status); + } while (!(status & DDC_DONE) && time_before(jiffies, timeout)); + + if (!(status & DDC_DONE)) { + dev_err(&it6263->hdmi_i2c->dev, + "failed to clear DDC FIFO\n"); + return -ETIMEDOUT; + } + + count = len > HDMI_DDC_FIFO_SIZE ? HDMI_DDC_FIFO_SIZE : len; + + /* fire the read command */ + regmap_write(regmap, HDMI_REG_DDC_REQOFF, start); + regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count); + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ); + + start += count; + len -= count; + + /* wait for reading done */ + timeout = jiffies + msecs_to_jiffies(250); + do { + regmap_read(regmap, HDMI_REG_DDC_STATUS, &status); + if (status & DDC_ERROR) { + dev_err(&it6263->hdmi_i2c->dev, "DDC error\n"); + return -EIO; + } + } while (!(status & DDC_DONE) && time_before(jiffies, timeout)); + + if (!(status & DDC_DONE)) { + dev_err(&it6263->hdmi_i2c->dev, + "failed to read EDID\n"); + return -ETIMEDOUT; + } + + /* cache to buffer */ + for (; count > 0; count--) { + regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val); + *(buf++) = val; + } + } + + return 0; +} + +static int it6263_get_modes(struct drm_connector *connector) +{ + struct it6263 *it6263 = connector_to_it6263(connector); + u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; + struct edid *edid; + int num = 0; + int ret; + + edid = drm_do_get_edid(connector, it6263_read_edid, it6263); + drm_connector_update_edid_property(connector, edid); + if (edid) { + num = drm_add_edid_modes(connector, edid); + it6263->is_hdmi = drm_detect_hdmi_monitor(edid); + kfree(edid); + } + + ret = drm_display_info_set_bus_formats(&connector->display_info, + &bus_format, 1); + if (ret) + dev_dbg(&it6263->hdmi_i2c->dev, + "failed to set the supported bus format %d\n", ret); + + return num; +} + +static enum drm_mode_status it6263_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + const struct it6263_minimode *m; + int i, vrefresh = drm_mode_vrefresh(mode); + + if (mode->clock > 150000) + return MODE_CLOCK_HIGH; + + for (i = 0; i < ARRAY_SIZE(it6263_bad_mode_db); i++) { + m = &it6263_bad_mode_db[i]; + if ((mode->hdisplay == m->hdisplay) && + (mode->vdisplay == m->vdisplay) && + (vrefresh == m->vrefresh)) + return MODE_BAD; + } + + return MODE_OK; +} + +static const struct drm_connector_helper_funcs it6263_connector_helper_funcs = { + .get_modes = it6263_get_modes, + .mode_valid = it6263_mode_valid, +}; + +static void it6263_bridge_disable(struct drm_bridge *bridge) +{ + struct it6263 *it6263 = bridge_to_it6263(bridge); + struct regmap *regmap = it6263->hdmi_regmap; + + /* AV mute */ + hdmi_update_bits(it6263, HDMI_REG_GCP, AVMUTE, AVMUTE); + + if (it6263->is_hdmi) + regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, 0); + + hdmi_update_bits(it6263, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST); + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST | AFE_DRV_PWD); +} + +static void it6263_bridge_enable(struct drm_bridge *bridge) +{ + struct it6263 *it6263 = bridge_to_it6263(bridge); + struct regmap *regmap = it6263->hdmi_regmap; + unsigned long timeout; + unsigned int status; + bool is_stable = false; + int i; + + regmap_write(it6263->hdmi_regmap, HDMI_REG_BANK_CTRL, BANK_SEL(1)); + /* set the color space to RGB in the AVI packet */ + hdmi_update_bits(it6263, HDMI_REG_AVI_DB1, AVI_DB1_COLOR_SPACE, + AVI_COLOR_SPACE_RGB); + regmap_write(it6263->hdmi_regmap, HDMI_REG_BANK_CTRL, BANK_SEL(0)); + + /* software video reset */ + hdmi_update_bits(it6263, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST); + usleep_range(1000, 2000); + hdmi_update_bits(it6263, HDMI_REG_SW_RST, SOFTV_RST, 0); + + /* reconfigure LVDS and retry several times in case video is instable */ + for (i = 0; i < 3; i++) { + timeout = jiffies + msecs_to_jiffies(500); + do { + regmap_read(regmap, HDMI_REG_SYS_STATUS, &status); + } while (!(status & TXVIDSTABLE) && + time_before(jiffies, timeout)); + + if (status & TXVIDSTABLE) { + is_stable = true; + break; + } + + it6263_lvds_config(it6263); + + dev_dbg(&it6263->hdmi_i2c->dev, + "retry to lock input video %d\n", i); + } + + if (!is_stable) + dev_warn(&it6263->hdmi_i2c->dev, + "failed to wait for video stable\n"); + + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0); + + /* AV unmute */ + hdmi_update_bits(it6263, HDMI_REG_GCP, AVMUTE, 0); + + if (it6263->is_hdmi) + regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, + ENABLE_PKT | REPEAT_PKT); +} + +static void it6263_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adj) +{ + struct it6263 *it6263 = bridge_to_it6263(bridge); + struct regmap *regmap = it6263->hdmi_regmap; + bool pclk_high = adj->clock > 80000 ? true : false; + + regmap_write(regmap, HDMI_REG_HDMI_MODE, + it6263->is_hdmi ? TX_HDMI_MODE : TX_DVI_MODE); + + dev_dbg(&it6263->hdmi_i2c->dev, "%s mode\n", + it6263->is_hdmi ? "HDMI" : "DVI"); + + /* setup AFE */ + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST); + if (pclk_high) + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL, + AFE_XP_GAINBIT | AFE_XP_RESETB); + else + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL, + AFE_XP_ER0 | AFE_XP_RESETB); + regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10); + if (pclk_high) + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL, + AFE_IP_GAINBIT | AFE_IP_RESETB); + else + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL, + AFE_IP_ER0 | AFE_IP_RESETB); +} + +static int it6263_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct it6263 *it6263 = bridge_to_it6263(bridge); + struct drm_device *drm = bridge->dev; + int ret; + + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { + DRM_ERROR("Fix bridge driver to make connector optional!"); + return -EINVAL; + } + + if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) { + dev_err(&it6263->hdmi_i2c->dev, + "it6263 driver only copes with atomic updates\n"); + return -ENOTSUPP; + } + + it6263->connector.polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; + ret = drm_connector_init(drm, &it6263->connector, + &it6263_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + if (ret) { + dev_err(&it6263->hdmi_i2c->dev, + "Failed to initialize connector with drm\n"); + return ret; + } + + drm_connector_helper_add(&it6263->connector, + &it6263_connector_helper_funcs); + drm_connector_attach_encoder(&it6263->connector, bridge->encoder); + + return ret; +} + +static int it6263_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_display_info *di = &conn_state->connector->display_info; + u32 flags = di->bus_flags; + + flags &= ~DRM_BUS_FLAG_DE_LOW; + + bridge_state->input_bus_cfg.flags = flags | DRM_BUS_FLAG_DE_HIGH; + bridge_state->output_bus_cfg.flags = flags | DRM_BUS_FLAG_DE_HIGH; + + return 0; +} + +static u32 +*it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + *num_input_fmts = 0; + + input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + /* we only accept Jeida 1x7x4 inputs currently */ + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA; + *num_input_fmts = 1; + + return input_fmts; +} + +static const struct drm_bridge_funcs it6263_bridge_funcs = { + .attach = it6263_bridge_attach, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .mode_set = it6263_bridge_mode_set, + .disable = it6263_bridge_disable, + .enable = it6263_bridge_enable, + .atomic_check = it6263_bridge_atomic_check, + .atomic_get_input_bus_fmts = it6263_bridge_atomic_get_input_bus_fmts, +}; + +static int it6263_check_chipid(struct it6263 *it6263) +{ + struct device *dev = &it6263->hdmi_i2c->dev; + u8 vendor_id[2], device_id[2]; + int ret; + + ret = regmap_bulk_read(it6263->hdmi_regmap, REG_VENDOR_ID(0), + &vendor_id, 2); + if (ret) { + dev_err(dev, "regmap_bulk_read failed %d\n", ret); + return ret; + } + + if (vendor_id[0] != HDMI_VENDER_ID_LOW || + vendor_id[1] != HDMI_VENDER_ID_HIGH) { + dev_err(dev, + "Invalid hdmi vendor id %02x %02x(expect 0x01 0xca)\n", + vendor_id[0], vendor_id[1]); + return -EINVAL; + } + + ret = regmap_bulk_read(it6263->hdmi_regmap, REG_DEVICE_ID(0), + &device_id, 2); + if (ret) { + dev_err(dev, "regmap_bulk_read failed %d\n", ret); + return ret; + } + + if (device_id[0] != HDMI_DEVICE_ID_LOW || + device_id[1] != HDMI_DEVICE_ID_HIGH) { + dev_err(dev, + "Invalid hdmi device id %02x %02x(expect 0x13 0x76)\n", + device_id[0], device_id[1]); + return -EINVAL; + } + + ret = regmap_bulk_read(it6263->lvds_regmap, REG_VENDOR_ID(0), + &vendor_id, 2); + if (ret) { + dev_err(dev, "regmap_bulk_read failed %d\n", ret); + return ret; + } + + if (vendor_id[0] != LVDS_VENDER_ID_LOW || + vendor_id[1] != LVDS_VENDER_ID_HIGH) { + dev_err(dev, + "Invalid lvds vendor id %02x %02x(expect 0x15 0xca)\n", + vendor_id[0], vendor_id[1]); + return -EINVAL; + } + + ret = regmap_bulk_read(it6263->lvds_regmap, REG_DEVICE_ID(0), + &device_id, 2); + if (ret) { + dev_err(dev, "regmap_bulk_read failed %d\n", ret); + return ret; + } + + if (device_id[0] != LVDS_DEVICE_ID_LOW || + device_id[1] != LVDS_DEVICE_ID_HIGH) { + dev_err(dev, + "Invalid lvds device id %02x %02x(expect 0x61 0x62)\n", + device_id[0], device_id[1]); + return -EINVAL; + } + + return ret; +} + +static const struct regmap_range it6263_hdmi_volatile_ranges[] = { + { .range_min = 0, .range_max = 0x1ff }, +}; + +static const struct regmap_access_table it6263_hdmi_volatile_table = { + .yes_ranges = it6263_hdmi_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(it6263_hdmi_volatile_ranges), +}; + +static const struct regmap_config it6263_hdmi_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = &it6263_hdmi_volatile_table, + .cache_type = REGCACHE_NONE, +}; + +static const struct regmap_range it6263_lvds_volatile_ranges[] = { + { .range_min = 0, .range_max = 0xff }, +}; + +static const struct regmap_access_table it6263_lvds_volatile_table = { + .yes_ranges = it6263_lvds_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(it6263_lvds_volatile_ranges), +}; + +static const struct regmap_config it6263_lvds_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = &it6263_lvds_volatile_table, + .cache_type = REGCACHE_NONE, +}; + +static int it6263_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device_node *np = dev->of_node; +#if IS_ENABLED(CONFIG_OF_DYNAMIC) + struct device_node *remote_node = NULL, *endpoint = NULL; + struct of_changeset ocs; + struct property *prop; +#endif + struct it6263 *it6263; + int ret; + + it6263 = devm_kzalloc(dev, sizeof(*it6263), GFP_KERNEL); + if (!it6263) + return -ENOMEM; + + it6263->split_mode = of_property_read_bool(np, "split-mode"); + + it6263->hdmi_i2c = client; + it6263->lvds_i2c = i2c_new_dummy_device(client->adapter, + LVDS_INPUT_CTRL_I2C_ADDR); + if (!it6263->lvds_i2c) { + ret = -ENODEV; + goto of_reconfig; + } + + it6263->hdmi_regmap = devm_regmap_init_i2c(client, + &it6263_hdmi_regmap_config); + if (IS_ERR(it6263->hdmi_regmap)) { + ret = PTR_ERR(it6263->hdmi_regmap); + goto unregister_lvds_i2c; + } + + it6263->lvds_regmap = devm_regmap_init_i2c(it6263->lvds_i2c, + &it6263_lvds_regmap_config); + if (IS_ERR(it6263->lvds_regmap)) { + ret = PTR_ERR(it6263->lvds_regmap); + goto unregister_lvds_i2c; + } + + it6263->reset_gpio = devm_gpiod_get_optional(dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(it6263->reset_gpio)) { + ret = PTR_ERR(it6263->reset_gpio); + + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get reset gpio: %d\n", ret); + + goto unregister_lvds_i2c; + } + + it6263_reset(it6263); + + ret = regmap_write(it6263->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL); + if (ret) + goto unregister_lvds_i2c; + + usleep_range(1000, 2000); + + ret = regmap_write(it6263->hdmi_regmap, HDMI_REG_LVDS_PORT, + LVDS_INPUT_CTRL_I2C_ADDR << 1); + if (ret) + goto unregister_lvds_i2c; + + ret = regmap_write(it6263->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, 0x01); + if (ret) + goto unregister_lvds_i2c; + + /* select HDMI bank0 */ + ret = regmap_write(it6263->hdmi_regmap, HDMI_REG_BANK_CTRL, + BANK_SEL(0)); + if (ret) + goto unregister_lvds_i2c; + + ret = it6263_check_chipid(it6263); + if (ret) + goto unregister_lvds_i2c; + + it6263_lvds_config(it6263); + it6263_hdmi_config(it6263); + + it6263->bridge.funcs = &it6263_bridge_funcs; + it6263->bridge.of_node = np; + drm_bridge_add(&it6263->bridge); + + i2c_set_clientdata(client, it6263); + + return ret; + +unregister_lvds_i2c: + i2c_unregister_device(it6263->lvds_i2c); + if (ret == -EPROBE_DEFER) + return ret; + +of_reconfig: +#if IS_ENABLED(CONFIG_OF_DYNAMIC) + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); + if (endpoint) + remote_node = of_graph_get_remote_port_parent(endpoint); + + if (remote_node) { + int num_endpoints = 0; + + /* + * Remote node should have two endpoints (input and output: us) + * If remote node has more than two endpoints, probably that it + * has more outputs, so there is no need to disable it. + */ + endpoint = NULL; + while ((endpoint = of_graph_get_next_endpoint(remote_node, + endpoint))) + num_endpoints++; + + if (num_endpoints > 2) { + of_node_put(remote_node); + return ret; + } + + prop = devm_kzalloc(dev, sizeof(*prop), GFP_KERNEL); + prop->name = devm_kstrdup(dev, "status", GFP_KERNEL); + prop->value = devm_kstrdup(dev, "disabled", GFP_KERNEL); + prop->length = 9; + of_changeset_init(&ocs); + of_changeset_update_property(&ocs, remote_node, prop); + ret = of_changeset_apply(&ocs); + if (!ret) + dev_warn(dev, + "Probe failed. Remote port '%s' disabled\n", + remote_node->full_name); + + of_node_put(remote_node); + }; +#endif + + return ret; +} + +static void it6263_remove(struct i2c_client *client) + +{ + struct it6263 *it6263 = i2c_get_clientdata(client); + + drm_bridge_remove(&it6263->bridge); + i2c_unregister_device(it6263->lvds_i2c); +} + +static const struct of_device_id it6263_dt_ids[] = { + { .compatible = "ite,it6263", }, + { } +}; +MODULE_DEVICE_TABLE(of, it6263_dt_ids); + +static const struct i2c_device_id it6263_i2c_ids[] = { + { "it6263", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids); + +static struct i2c_driver it6263_driver = { + .probe = it6263_probe, + .remove = it6263_remove, + .driver = { + .name = "it6263", + .of_match_table = it6263_dt_ids, + }, + .id_table = it6263_i2c_ids, +}; +module_i2c_driver(it6263_driver); + +MODULE_AUTHOR("NXP Semiconductor"); +MODULE_DESCRIPTION("ITE Tech. Inc. IT6263 LVDS->HDMI bridge"); +MODULE_LICENSE("GPL"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/Kconfig linux-imx-phytec/drivers/gpu/drm/bridge/Kconfig --- linux-6.1.55/drivers/gpu/drm/bridge/Kconfig 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/Kconfig 2024-06-19 12:34:01.888253921 +0200 @@ -164,6 +164,15 @@ help Support for ITE IT66121 HDMI bridge. +config DRM_FSL_IMX_LVDS_BRIDGE + tristate "Freescale i.MX LVDS display bridge" + depends on MFD_SYSCON + depends on OF + select DRM_PANEL_BRIDGE + help + Support Freescale i.MX parallel to LVDS Display Bridge (LDB). + This bridge is embedded in a SoC. + config DRM_LVDS_CODEC tristate "Transparent LVDS encoders and decoders support" depends on OF @@ -173,6 +182,21 @@ Support for transparent LVDS encoders and decoders that don't require any configuration. +config DRM_MAX96752_LVDS + tristate "Analog Devices MAX96752 deserializer LVDS bridge" + depends on DRM && OF && MFD_MAX96752 + select DRM_KMS_HELPER + help + This adds LVDS bridge support for the MAX96752 deserializer chip. + +config DRM_MAX96789_DSI + tristate "Analog Devices MAX96789 serializer DSI bridge" + depends on DRM && OF && MFD_MAX96789 + select DRM_KMS_HELPER + select DRM_MIPI_DSI + help + This adds MIPI-DSI bridge support for the MAX96789 serializer chip. + config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW tristate "MegaChips stdp4028-ge-b850v3-fw and stdp2690-ge-b850v3-fw" depends on OF @@ -200,6 +224,20 @@ This enables the Northwest Logic MIPI DSI Host controller as for example found on NXP's i.MX8 Processors. +config DRM_SEC_MIPI_DSIM + tristate "Samsung MIPI DSIM Bridge" + depends on OF + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + help + The Samsung MPI DSIM Bridge driver. + +config DRM_NXP_SEIKO_43WVFIG + tristate "Legacy Freescale Seiko 43WVFIG panel DPI adapter bridge" + select DRM_KMS_HELPER + select DRM_PANEL + config DRM_NXP_PTN3460 tristate "NXP PTN3460 DP/LVDS bridge" depends on OF @@ -389,4 +427,20 @@ source "drivers/gpu/drm/bridge/synopsys/Kconfig" +config DRM_ITE_IT6263 + tristate "ITE IT6263 LVDS/HDMI bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + help + ITE IT6263 bridge chip driver. + +config DRM_ITE_IT6161 + tristate "ITE IT6161 MIPI/HDMI bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + help + ITE IT6161 bridge chip driver. + endmenu diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/Makefile linux-imx-phytec/drivers/gpu/drm/bridge/Makefile --- linux-6.1.55/drivers/gpu/drm/bridge/Makefile 2023-09-23 11:11:13.000000000 +0200 +++ linux-imx-phytec/drivers/gpu/drm/bridge/Makefile 2024-06-19 12:34:01.888253921 +0200 @@ -10,7 +10,10 @@ obj-$(CONFIG_DRM_LONTIUM_LT9211) += lontium-lt9211.o obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o +obj-$(CONFIG_DRM_FSL_IMX_LVDS_BRIDGE) += fsl-imx-ldb.o obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o +obj-$(CONFIG_DRM_MAX96752_LVDS) += max96752-lvds.o +obj-$(CONFIG_DRM_MAX96789_DSI) += max96789-dsi.o obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o @@ -38,3 +41,7 @@ obj-y += cadence/ obj-y += imx/ obj-y += synopsys/ +obj-$(CONFIG_DRM_ITE_IT6263) += it6263.o +obj-$(CONFIG_DRM_ITE_IT6161) += it6161.o +obj-$(CONFIG_DRM_SEC_MIPI_DSIM) += sec-dsim.o +obj-$(CONFIG_DRM_NXP_SEIKO_43WVFIG) += nxp-seiko-43wvfig.o diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/max96752-lvds.c linux-imx-phytec/drivers/gpu/drm/bridge/max96752-lvds.c --- linux-6.1.55/drivers/gpu/drm/bridge/max96752-lvds.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/max96752-lvds.c 2024-06-19 12:34:01.896254057 +0200 @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Core MFD support for Analog Devices MAX96752 MIPI-DSI serializer + * + * Copyright 2023 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + + +#include +#include +#include + +enum max96752_lvds_id { + LVDS_PORT_A, + LVDS_PORT_B, + MAX_LVDS_PORTS +}; + +enum max96752_lvds_bus_format { + BUS_FORMAT_OLDI, + BUS_FORMAT_VESA, +}; + +struct max96752_lvds { + struct device *dev; + struct max96752 *max96752_mfd; + + struct drm_bridge bridge; + struct drm_bridge *panel_bridge; + + enum max96752_lvds_bus_format bus_format; + bool dual_channel; +}; + +static void max96752_lvds_bridge_atomic_pre_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct max96752_lvds *max96752_lvds = container_of(bridge, struct max96752_lvds, bridge); + struct max96752 *mfd = max96752_lvds->max96752_mfd; + unsigned int reg_mask, reg_val; + + + reg_mask = (max96752_lvds->dual_channel ? OLDI_SPL_EN : 0) | OLDI_FORMAT; + reg_val = (max96752_lvds->dual_channel ? OLDI_SPL_EN : 0) | + (max96752_lvds->bus_format ? OLDI_FORMAT : 0); + regmap_update_bits(mfd->regmap, MAX96752_VRX_OLDI1, reg_mask, reg_val); +} + +static int max96752_lvds_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct max96752_lvds *max96752_lvds = container_of(bridge, struct max96752_lvds, bridge); + struct device *dev = max96752_lvds->dev; + + max96752_lvds->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 1); + if (IS_ERR(max96752_lvds->panel_bridge)) { + dev_err(dev, "Couldn't find next panel/bridge: %ld\n", + PTR_ERR(max96752_lvds->panel_bridge)); + + return PTR_ERR(max96752_lvds->panel_bridge); + } + + return drm_bridge_attach(bridge->encoder, max96752_lvds->panel_bridge, bridge, flags); +} + +static int max96752_lvds_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_display_info *di = &conn_state->connector->display_info; + struct drm_bridge_state *next_bridge_state = NULL; + struct drm_bridge *next_bridge; + u32 bus_flags = 0; + u32 bus_format = 0; + struct max96752_lvds *max96752_lvds = container_of(bridge, struct max96752_lvds, bridge); + + next_bridge = drm_bridge_get_next_bridge(bridge); + if (next_bridge) + next_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state, + next_bridge); + + if (next_bridge_state) { + bus_flags = next_bridge_state->input_bus_cfg.flags; + bus_format = next_bridge_state->input_bus_cfg.format; + } else if (di->num_bus_formats) { + bus_flags = di->bus_flags; + bus_format = di->bus_formats[0]; + } + + bridge_state->output_bus_cfg.flags = bus_flags; + + if (bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) + max96752_lvds->bus_format = BUS_FORMAT_VESA; + else if (bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) + max96752_lvds->bus_format = BUS_FORMAT_OLDI; + else + return -EINVAL; + + return 0; +} + +static const struct drm_bridge_funcs max96752_lvds_bridge_funcs = { + .atomic_check = max96752_lvds_atomic_check, + .atomic_pre_enable = max96752_lvds_bridge_atomic_pre_enable, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .attach = max96752_lvds_bridge_attach, +}; + +static int max96752_lvds_dt_parse(struct max96752_lvds *max96752_lvds) +{ + struct device *dev = max96752_lvds->dev; + struct device_node *dt_port; + + dt_port = of_graph_get_port_by_id(dev->of_node, 0); + if (!dt_port) { + dev_err(dev, "port definition is missing in DT\n"); + return -ENODEV; + } + + of_node_put(dt_port); + + max96752_lvds->dual_channel = of_property_read_bool(dev->of_node, "maxim,dual-channel"); + max96752_lvds->bridge.driver_private = max96752_lvds; + max96752_lvds->bridge.funcs = &max96752_lvds_bridge_funcs; + max96752_lvds->bridge.of_node = dev->of_node; + + drm_bridge_add(&max96752_lvds->bridge); + + return 0; +} + +static const struct of_device_id max96752_of_match[] = { + { .compatible = "maxim,max96752", .data = (void *)ID_MAX96752 }, + {} +}; +MODULE_DEVICE_TABLE(of, max96752_of_match); + +static int max96752_lvds_drm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct max96752_lvds *max96752_lvds; + struct max96752 *mfd = dev_get_drvdata(dev->parent); + const struct of_device_id *match; + + match = of_match_node(max96752_of_match, dev->parent->of_node); + if (!match) { + dev_err(dev, "invalid compatible string\n"); + return -ENODEV; + } + + if (!mfd->link_setup_finished) + return -EPROBE_DEFER; + + max96752_lvds = devm_kzalloc(dev, sizeof(*max96752_lvds), GFP_KERNEL); + if (!max96752_lvds) + return -ENOMEM; + + max96752_lvds->dev = dev; + max96752_lvds->max96752_mfd = mfd; + + dev_set_drvdata(dev, max96752_lvds); + + return max96752_lvds_dt_parse(max96752_lvds); +} + +static int max96752_lvds_drm_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct of_device_id max96752_lvds_of_match[] = { + { .compatible = "maxim,max96752-lvds", .data = (void *)ID_MAX96752 }, + {} +}; +MODULE_DEVICE_TABLE(of, max96752_lvds_of_match); + +static struct platform_driver max96752_lvds_platform_driver = { + .probe = max96752_lvds_drm_probe, + .remove = max96752_lvds_drm_remove, + .driver = { + .name = "max96752-lvds", + .of_match_table = of_match_ptr(max96752_lvds_of_match), + }, +}; + +drm_module_platform_driver(max96752_lvds_platform_driver); + +MODULE_AUTHOR("Laurentiu Palcu "); +MODULE_DESCRIPTION("MAX96752 deserializer LVDS bridge driver"); +MODULE_LICENSE("GPL v2"); diff '--color=auto' -Nur '--exclude=.git*' --no-dereference linux-6.1.55/drivers/gpu/drm/bridge/max96789-dsi.c linux-imx-phytec/drivers/gpu/drm/bridge/max96789-dsi.c --- linux-6.1.55/drivers/gpu/drm/bridge/max96789-dsi.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-imx-phytec/drivers/gpu/drm/bridge/max96789-dsi.c 2024-06-19 12:34:01.896254057 +0200 @@ -0,0 +1,455 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Core MFD support for Analog Devices MAX96789 MIPI-DSI serializer + * + * Copyright 2023 NXP + */ + +#include +#include +#include +#include +#include +#include + +#include